Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.06 98.12 92.46 97.66 91.30 95.42 98.67 91.81


Total test records in report: 1470
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html
T1306 /workspace/coverage/default/1.i2c_alert_test.2808079798 Apr 15 03:28:42 PM PDT 24 Apr 15 03:28:43 PM PDT 24 25417978 ps
T1307 /workspace/coverage/default/4.i2c_target_hrst.805568191 Apr 15 03:28:53 PM PDT 24 Apr 15 03:28:56 PM PDT 24 1397397602 ps
T1308 /workspace/coverage/default/41.i2c_host_stretch_timeout.3927364025 Apr 15 03:33:52 PM PDT 24 Apr 15 03:34:03 PM PDT 24 1158182677 ps
T1309 /workspace/coverage/default/36.i2c_host_error_intr.312629003 Apr 15 03:33:09 PM PDT 24 Apr 15 03:33:12 PM PDT 24 364619834 ps
T1310 /workspace/coverage/default/27.i2c_target_stress_wr.2360249674 Apr 15 03:31:56 PM PDT 24 Apr 15 03:32:29 PM PDT 24 16155628156 ps
T1311 /workspace/coverage/default/10.i2c_target_bad_addr.2352293568 Apr 15 03:29:31 PM PDT 24 Apr 15 03:29:36 PM PDT 24 927255371 ps
T1312 /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.3108835307 Apr 15 03:30:46 PM PDT 24 Apr 15 03:30:47 PM PDT 24 514078685 ps
T1313 /workspace/coverage/default/10.i2c_host_fifo_full.1677679754 Apr 15 03:29:25 PM PDT 24 Apr 15 03:30:02 PM PDT 24 1287933833 ps
T1314 /workspace/coverage/default/44.i2c_alert_test.1415821450 Apr 15 03:34:24 PM PDT 24 Apr 15 03:34:25 PM PDT 24 60649996 ps
T1315 /workspace/coverage/default/45.i2c_host_fifo_overflow.1686227474 Apr 15 03:34:26 PM PDT 24 Apr 15 03:35:50 PM PDT 24 2361215834 ps
T1316 /workspace/coverage/default/3.i2c_target_hrst.127794462 Apr 15 03:28:54 PM PDT 24 Apr 15 03:28:58 PM PDT 24 547629357 ps
T1317 /workspace/coverage/default/19.i2c_target_intr_stress_wr.46656299 Apr 15 03:30:44 PM PDT 24 Apr 15 03:31:57 PM PDT 24 11426165149 ps
T1318 /workspace/coverage/default/18.i2c_target_fifo_reset_tx.2238361291 Apr 15 03:30:35 PM PDT 24 Apr 15 03:30:52 PM PDT 24 10156166638 ps
T1319 /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1149471622 Apr 15 03:29:59 PM PDT 24 Apr 15 03:30:06 PM PDT 24 759371440 ps
T1320 /workspace/coverage/default/27.i2c_target_stretch.3765365370 Apr 15 03:31:57 PM PDT 24 Apr 15 04:27:30 PM PDT 24 17471899475 ps
T1321 /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.759000530 Apr 15 03:30:21 PM PDT 24 Apr 15 03:30:42 PM PDT 24 394325535 ps
T1322 /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.3870913176 Apr 15 03:29:01 PM PDT 24 Apr 15 03:29:07 PM PDT 24 484990500 ps
T1323 /workspace/coverage/default/46.i2c_host_perf.1354715359 Apr 15 03:34:54 PM PDT 24 Apr 15 03:37:48 PM PDT 24 6440391256 ps
T1324 /workspace/coverage/default/7.i2c_host_fifo_reset_rx.3411733925 Apr 15 03:29:07 PM PDT 24 Apr 15 03:29:12 PM PDT 24 661035062 ps
T1325 /workspace/coverage/default/6.i2c_alert_test.3607013448 Apr 15 03:29:04 PM PDT 24 Apr 15 03:29:05 PM PDT 24 37577716 ps
T1326 /workspace/coverage/default/38.i2c_target_bad_addr.1582872760 Apr 15 03:33:32 PM PDT 24 Apr 15 03:33:36 PM PDT 24 4597223372 ps
T1327 /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1643869155 Apr 15 03:31:14 PM PDT 24 Apr 15 03:31:21 PM PDT 24 608730704 ps
T1328 /workspace/coverage/default/29.i2c_host_error_intr.55739471 Apr 15 03:32:13 PM PDT 24 Apr 15 03:32:15 PM PDT 24 156966884 ps
T1329 /workspace/coverage/default/46.i2c_host_stress_all.3640030180 Apr 15 03:34:37 PM PDT 24 Apr 15 03:41:03 PM PDT 24 20904830641 ps
T1330 /workspace/coverage/default/9.i2c_target_intr_stress_wr.527167432 Apr 15 03:29:23 PM PDT 24 Apr 15 03:31:44 PM PDT 24 14178475055 ps
T222 /workspace/coverage/default/16.i2c_target_fifo_reset_acq.1198215897 Apr 15 03:30:22 PM PDT 24 Apr 15 03:31:00 PM PDT 24 10167084686 ps
T1331 /workspace/coverage/default/49.i2c_target_stretch.1562721181 Apr 15 03:34:58 PM PDT 24 Apr 15 04:32:17 PM PDT 24 35255038719 ps
T1332 /workspace/coverage/default/22.i2c_target_smoke.3107506908 Apr 15 03:31:14 PM PDT 24 Apr 15 03:31:27 PM PDT 24 8283341467 ps
T1333 /workspace/coverage/default/24.i2c_host_override.1934251709 Apr 15 03:31:23 PM PDT 24 Apr 15 03:31:24 PM PDT 24 18247522 ps
T1334 /workspace/coverage/default/10.i2c_target_smoke.4080434669 Apr 15 03:29:31 PM PDT 24 Apr 15 03:29:44 PM PDT 24 899646308 ps
T1335 /workspace/coverage/default/32.i2c_target_timeout.548055829 Apr 15 03:32:42 PM PDT 24 Apr 15 03:32:48 PM PDT 24 10302411567 ps
T1336 /workspace/coverage/default/44.i2c_target_hrst.3411996312 Apr 15 03:34:20 PM PDT 24 Apr 15 03:34:23 PM PDT 24 206589145 ps
T1337 /workspace/coverage/default/43.i2c_host_fifo_overflow.2276884693 Apr 15 03:34:08 PM PDT 24 Apr 15 03:35:26 PM PDT 24 1226402901 ps
T1338 /workspace/coverage/default/31.i2c_host_error_intr.2209094471 Apr 15 03:32:30 PM PDT 24 Apr 15 03:32:32 PM PDT 24 206486305 ps
T1339 /workspace/coverage/default/22.i2c_host_fifo_overflow.755590411 Apr 15 03:31:04 PM PDT 24 Apr 15 03:31:45 PM PDT 24 7884083306 ps
T1340 /workspace/coverage/default/19.i2c_target_stress_wr.2955154030 Apr 15 03:30:43 PM PDT 24 Apr 15 03:30:52 PM PDT 24 14846969093 ps
T1341 /workspace/coverage/default/33.i2c_host_fifo_watermark.1937993609 Apr 15 03:32:49 PM PDT 24 Apr 15 03:35:00 PM PDT 24 8596515457 ps
T1342 /workspace/coverage/default/30.i2c_target_stress_wr.3867460125 Apr 15 03:32:18 PM PDT 24 Apr 15 03:33:56 PM PDT 24 32745004110 ps
T1343 /workspace/coverage/default/43.i2c_target_stress_rd.2159883854 Apr 15 03:34:14 PM PDT 24 Apr 15 03:34:19 PM PDT 24 241466580 ps
T1344 /workspace/coverage/default/24.i2c_target_fifo_reset_tx.1825311305 Apr 15 03:31:29 PM PDT 24 Apr 15 03:31:45 PM PDT 24 10173017387 ps
T1345 /workspace/coverage/default/18.i2c_host_fifo_reset_rx.2189590718 Apr 15 03:30:31 PM PDT 24 Apr 15 03:30:35 PM PDT 24 282752438 ps
T1346 /workspace/coverage/default/33.i2c_host_perf.4132398514 Apr 15 03:32:46 PM PDT 24 Apr 15 03:33:39 PM PDT 24 5200056061 ps
T1347 /workspace/coverage/default/12.i2c_target_hrst.1523847822 Apr 15 03:29:44 PM PDT 24 Apr 15 03:29:48 PM PDT 24 552938145 ps
T1348 /workspace/coverage/default/25.i2c_target_hrst.293595435 Apr 15 03:31:44 PM PDT 24 Apr 15 03:31:47 PM PDT 24 327852044 ps
T1349 /workspace/coverage/default/27.i2c_host_stretch_timeout.3203005016 Apr 15 03:31:52 PM PDT 24 Apr 15 03:32:09 PM PDT 24 4018542906 ps
T1350 /workspace/coverage/default/22.i2c_target_hrst.1445607182 Apr 15 03:31:14 PM PDT 24 Apr 15 03:31:17 PM PDT 24 313040368 ps
T1351 /workspace/coverage/default/30.i2c_target_stretch.1126273523 Apr 15 03:32:21 PM PDT 24 Apr 15 03:32:39 PM PDT 24 8059916640 ps
T1352 /workspace/coverage/default/15.i2c_host_override.4031179243 Apr 15 03:30:06 PM PDT 24 Apr 15 03:30:07 PM PDT 24 25444322 ps
T259 /workspace/coverage/default/34.i2c_host_fifo_watermark.2346532647 Apr 15 03:33:00 PM PDT 24 Apr 15 03:34:20 PM PDT 24 6193121413 ps
T1353 /workspace/coverage/default/45.i2c_host_smoke.124447995 Apr 15 03:34:34 PM PDT 24 Apr 15 03:34:55 PM PDT 24 4337507802 ps
T1354 /workspace/coverage/default/19.i2c_target_stretch.846161859 Apr 15 03:30:42 PM PDT 24 Apr 15 03:35:47 PM PDT 24 24266324030 ps
T1355 /workspace/coverage/default/2.i2c_target_bad_addr.1883185504 Apr 15 03:28:43 PM PDT 24 Apr 15 03:28:50 PM PDT 24 1790252961 ps
T1356 /workspace/coverage/default/21.i2c_target_timeout.2273854207 Apr 15 03:31:01 PM PDT 24 Apr 15 03:31:08 PM PDT 24 1599174306 ps
T1357 /workspace/coverage/default/3.i2c_target_stretch.3271649966 Apr 15 03:28:45 PM PDT 24 Apr 15 03:32:40 PM PDT 24 34010397247 ps
T1358 /workspace/coverage/default/35.i2c_host_stretch_timeout.3040515793 Apr 15 03:33:03 PM PDT 24 Apr 15 03:33:32 PM PDT 24 1074823718 ps
T1359 /workspace/coverage/default/43.i2c_alert_test.3615747467 Apr 15 03:34:21 PM PDT 24 Apr 15 03:34:22 PM PDT 24 18314460 ps
T1360 /workspace/coverage/default/43.i2c_host_fifo_full.5380413 Apr 15 03:34:14 PM PDT 24 Apr 15 03:37:27 PM PDT 24 5454178583 ps
T62 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1921722509 Apr 15 12:39:34 PM PDT 24 Apr 15 12:39:35 PM PDT 24 25915777 ps
T1361 /workspace/coverage/cover_reg_top/3.i2c_intr_test.4029697853 Apr 15 12:39:52 PM PDT 24 Apr 15 12:39:53 PM PDT 24 17237905 ps
T1362 /workspace/coverage/cover_reg_top/47.i2c_intr_test.277451449 Apr 15 12:40:08 PM PDT 24 Apr 15 12:40:09 PM PDT 24 17445483 ps
T116 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.774195776 Apr 15 12:39:55 PM PDT 24 Apr 15 12:39:57 PM PDT 24 209560438 ps
T63 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2940858909 Apr 15 12:40:08 PM PDT 24 Apr 15 12:40:10 PM PDT 24 45237133 ps
T64 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.605010647 Apr 15 12:40:03 PM PDT 24 Apr 15 12:40:05 PM PDT 24 80741668 ps
T167 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.901174849 Apr 15 12:39:36 PM PDT 24 Apr 15 12:39:38 PM PDT 24 26000409 ps
T154 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1293198774 Apr 15 12:39:47 PM PDT 24 Apr 15 12:39:49 PM PDT 24 38453739 ps
T1363 /workspace/coverage/cover_reg_top/22.i2c_intr_test.3430383073 Apr 15 12:40:11 PM PDT 24 Apr 15 12:40:13 PM PDT 24 101903941 ps
T155 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1200835881 Apr 15 12:39:47 PM PDT 24 Apr 15 12:39:49 PM PDT 24 99916278 ps
T156 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1539274116 Apr 15 12:39:51 PM PDT 24 Apr 15 12:39:52 PM PDT 24 20667830 ps
T1364 /workspace/coverage/cover_reg_top/24.i2c_intr_test.29771970 Apr 15 12:40:14 PM PDT 24 Apr 15 12:40:16 PM PDT 24 56802901 ps
T129 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3335046311 Apr 15 12:40:13 PM PDT 24 Apr 15 12:40:15 PM PDT 24 31564629 ps
T1365 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3650413840 Apr 15 12:39:58 PM PDT 24 Apr 15 12:39:59 PM PDT 24 275127764 ps
T151 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.845339578 Apr 15 12:40:17 PM PDT 24 Apr 15 12:40:20 PM PDT 24 22912632 ps
T130 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.668946961 Apr 15 12:39:59 PM PDT 24 Apr 15 12:40:03 PM PDT 24 170951882 ps
T152 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.4244138922 Apr 15 12:39:49 PM PDT 24 Apr 15 12:39:50 PM PDT 24 26955019 ps
T1366 /workspace/coverage/cover_reg_top/28.i2c_intr_test.2048341671 Apr 15 12:40:14 PM PDT 24 Apr 15 12:40:15 PM PDT 24 32346368 ps
T1367 /workspace/coverage/cover_reg_top/43.i2c_intr_test.938888304 Apr 15 12:40:05 PM PDT 24 Apr 15 12:40:06 PM PDT 24 28136901 ps
T131 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.472473153 Apr 15 12:40:15 PM PDT 24 Apr 15 12:40:18 PM PDT 24 79639246 ps
T157 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3450204617 Apr 15 12:39:32 PM PDT 24 Apr 15 12:39:34 PM PDT 24 18451310 ps
T168 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.833381968 Apr 15 12:40:03 PM PDT 24 Apr 15 12:40:06 PM PDT 24 213037323 ps
T132 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.770956613 Apr 15 12:39:57 PM PDT 24 Apr 15 12:39:59 PM PDT 24 149516323 ps
T135 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3402218019 Apr 15 12:39:54 PM PDT 24 Apr 15 12:39:56 PM PDT 24 203791142 ps
T1368 /workspace/coverage/cover_reg_top/23.i2c_intr_test.896265508 Apr 15 12:40:15 PM PDT 24 Apr 15 12:40:16 PM PDT 24 26308436 ps
T1369 /workspace/coverage/cover_reg_top/1.i2c_intr_test.2264754476 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:37 PM PDT 24 43878051 ps
T153 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3289481525 Apr 15 12:39:36 PM PDT 24 Apr 15 12:39:38 PM PDT 24 211747315 ps
T1370 /workspace/coverage/cover_reg_top/39.i2c_intr_test.1426796077 Apr 15 12:40:07 PM PDT 24 Apr 15 12:40:09 PM PDT 24 54493156 ps
T137 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3341430164 Apr 15 12:39:52 PM PDT 24 Apr 15 12:39:53 PM PDT 24 26016506 ps
T149 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.37112549 Apr 15 12:40:03 PM PDT 24 Apr 15 12:40:05 PM PDT 24 90344437 ps
T133 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.19001063 Apr 15 12:40:10 PM PDT 24 Apr 15 12:40:12 PM PDT 24 185210572 ps
T1371 /workspace/coverage/cover_reg_top/25.i2c_intr_test.3553225523 Apr 15 12:40:10 PM PDT 24 Apr 15 12:40:11 PM PDT 24 152284689 ps
T1372 /workspace/coverage/cover_reg_top/21.i2c_intr_test.1843262617 Apr 15 12:40:17 PM PDT 24 Apr 15 12:40:19 PM PDT 24 15480204 ps
T1373 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.167729147 Apr 15 12:40:11 PM PDT 24 Apr 15 12:40:13 PM PDT 24 37849412 ps
T1374 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3664857786 Apr 15 12:39:47 PM PDT 24 Apr 15 12:39:50 PM PDT 24 61360991 ps
T1375 /workspace/coverage/cover_reg_top/7.i2c_intr_test.4012442930 Apr 15 12:39:59 PM PDT 24 Apr 15 12:40:01 PM PDT 24 63433915 ps
T1376 /workspace/coverage/cover_reg_top/36.i2c_intr_test.3499991932 Apr 15 12:40:11 PM PDT 24 Apr 15 12:40:12 PM PDT 24 45388398 ps
T1377 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3095415146 Apr 15 12:40:13 PM PDT 24 Apr 15 12:40:14 PM PDT 24 19650124 ps
T169 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3745544617 Apr 15 12:39:46 PM PDT 24 Apr 15 12:39:48 PM PDT 24 18624597 ps
T1378 /workspace/coverage/cover_reg_top/29.i2c_intr_test.3328836570 Apr 15 12:40:09 PM PDT 24 Apr 15 12:40:10 PM PDT 24 20682594 ps
T170 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.377632612 Apr 15 12:39:47 PM PDT 24 Apr 15 12:39:49 PM PDT 24 255053283 ps
T171 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.408946992 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:37 PM PDT 24 160620196 ps
T134 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2330008967 Apr 15 12:39:48 PM PDT 24 Apr 15 12:39:56 PM PDT 24 293518367 ps
T1379 /workspace/coverage/cover_reg_top/17.i2c_intr_test.2472388360 Apr 15 12:40:06 PM PDT 24 Apr 15 12:40:08 PM PDT 24 23345067 ps
T146 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1459775513 Apr 15 12:39:40 PM PDT 24 Apr 15 12:39:43 PM PDT 24 128870472 ps
T158 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1608365660 Apr 15 12:39:44 PM PDT 24 Apr 15 12:39:45 PM PDT 24 66818046 ps
T1380 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2280745885 Apr 15 12:39:47 PM PDT 24 Apr 15 12:39:49 PM PDT 24 102563706 ps
T1381 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.629403885 Apr 15 12:39:56 PM PDT 24 Apr 15 12:40:03 PM PDT 24 88368207 ps
T172 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.294474839 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:37 PM PDT 24 31732090 ps
T1382 /workspace/coverage/cover_reg_top/37.i2c_intr_test.3745506270 Apr 15 12:40:10 PM PDT 24 Apr 15 12:40:11 PM PDT 24 44834020 ps
T173 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3231116526 Apr 15 12:39:34 PM PDT 24 Apr 15 12:39:36 PM PDT 24 21400560 ps
T175 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1567318554 Apr 15 12:39:30 PM PDT 24 Apr 15 12:39:33 PM PDT 24 25699624 ps
T1383 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2764612494 Apr 15 12:39:44 PM PDT 24 Apr 15 12:39:46 PM PDT 24 32654036 ps
T1384 /workspace/coverage/cover_reg_top/48.i2c_intr_test.2786156090 Apr 15 12:40:17 PM PDT 24 Apr 15 12:40:20 PM PDT 24 42735176 ps
T1385 /workspace/coverage/cover_reg_top/45.i2c_intr_test.3088448651 Apr 15 12:40:03 PM PDT 24 Apr 15 12:40:05 PM PDT 24 64194539 ps
T176 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1583602790 Apr 15 12:39:42 PM PDT 24 Apr 15 12:39:44 PM PDT 24 56299819 ps
T159 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2350434058 Apr 15 12:40:06 PM PDT 24 Apr 15 12:40:07 PM PDT 24 17398342 ps
T1386 /workspace/coverage/cover_reg_top/11.i2c_intr_test.1727584867 Apr 15 12:39:48 PM PDT 24 Apr 15 12:39:50 PM PDT 24 18748276 ps
T160 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.4074449636 Apr 15 12:39:55 PM PDT 24 Apr 15 12:39:56 PM PDT 24 54405887 ps
T239 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1288852217 Apr 15 12:39:43 PM PDT 24 Apr 15 12:39:44 PM PDT 24 157891144 ps
T1387 /workspace/coverage/cover_reg_top/40.i2c_intr_test.754953690 Apr 15 12:40:10 PM PDT 24 Apr 15 12:40:12 PM PDT 24 24835343 ps
T1388 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.4029295255 Apr 15 12:40:13 PM PDT 24 Apr 15 12:40:20 PM PDT 24 32681717 ps
T1389 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.424094548 Apr 15 12:40:17 PM PDT 24 Apr 15 12:40:20 PM PDT 24 17124579 ps
T148 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2516463477 Apr 15 12:40:15 PM PDT 24 Apr 15 12:40:19 PM PDT 24 180692046 ps
T161 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2090124291 Apr 15 12:39:56 PM PDT 24 Apr 15 12:39:58 PM PDT 24 24126780 ps
T1390 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4129868608 Apr 15 12:39:37 PM PDT 24 Apr 15 12:39:39 PM PDT 24 57112502 ps
T1391 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3222164708 Apr 15 12:40:01 PM PDT 24 Apr 15 12:40:03 PM PDT 24 35752110 ps
T1392 /workspace/coverage/cover_reg_top/15.i2c_intr_test.1383595768 Apr 15 12:40:04 PM PDT 24 Apr 15 12:40:06 PM PDT 24 109511276 ps
T1393 /workspace/coverage/cover_reg_top/38.i2c_intr_test.1586617793 Apr 15 12:40:17 PM PDT 24 Apr 15 12:40:20 PM PDT 24 30363344 ps
T192 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1260697533 Apr 15 12:39:55 PM PDT 24 Apr 15 12:39:58 PM PDT 24 120880178 ps
T1394 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.292097373 Apr 15 12:40:05 PM PDT 24 Apr 15 12:40:07 PM PDT 24 26023600 ps
T147 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1554236373 Apr 15 12:39:54 PM PDT 24 Apr 15 12:39:56 PM PDT 24 60949121 ps
T162 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3029702188 Apr 15 12:39:39 PM PDT 24 Apr 15 12:39:41 PM PDT 24 91020805 ps
T1395 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3241291789 Apr 15 12:39:48 PM PDT 24 Apr 15 12:39:55 PM PDT 24 2122651492 ps
T1396 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3297262708 Apr 15 12:39:46 PM PDT 24 Apr 15 12:39:48 PM PDT 24 59972572 ps
T1397 /workspace/coverage/cover_reg_top/13.i2c_intr_test.1004310610 Apr 15 12:40:06 PM PDT 24 Apr 15 12:40:08 PM PDT 24 16130703 ps
T1398 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3130646286 Apr 15 12:39:44 PM PDT 24 Apr 15 12:39:46 PM PDT 24 58280623 ps
T143 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.4196023866 Apr 15 12:40:10 PM PDT 24 Apr 15 12:40:12 PM PDT 24 89091363 ps
T144 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3875719269 Apr 15 12:39:51 PM PDT 24 Apr 15 12:39:53 PM PDT 24 151698931 ps
T138 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3308344023 Apr 15 12:39:33 PM PDT 24 Apr 15 12:39:36 PM PDT 24 108015115 ps
T1399 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1471623921 Apr 15 12:40:06 PM PDT 24 Apr 15 12:40:07 PM PDT 24 139076514 ps
T1400 /workspace/coverage/cover_reg_top/8.i2c_intr_test.1060313488 Apr 15 12:39:56 PM PDT 24 Apr 15 12:39:58 PM PDT 24 24144539 ps
T1401 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1530915822 Apr 15 12:40:15 PM PDT 24 Apr 15 12:40:18 PM PDT 24 123201626 ps
T1402 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2140412185 Apr 15 12:40:06 PM PDT 24 Apr 15 12:40:07 PM PDT 24 19763217 ps
T1403 /workspace/coverage/cover_reg_top/9.i2c_intr_test.362190467 Apr 15 12:40:01 PM PDT 24 Apr 15 12:40:03 PM PDT 24 18854377 ps
T163 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2478892817 Apr 15 12:40:04 PM PDT 24 Apr 15 12:40:06 PM PDT 24 20456821 ps
T1404 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1544300830 Apr 15 12:39:42 PM PDT 24 Apr 15 12:39:48 PM PDT 24 42966514 ps
T1405 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2344927971 Apr 15 12:39:47 PM PDT 24 Apr 15 12:39:48 PM PDT 24 60051178 ps
T1406 /workspace/coverage/cover_reg_top/19.i2c_intr_test.2477113788 Apr 15 12:40:10 PM PDT 24 Apr 15 12:40:11 PM PDT 24 120432173 ps
T145 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.662321073 Apr 15 12:40:02 PM PDT 24 Apr 15 12:40:04 PM PDT 24 271243762 ps
T1407 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2527952057 Apr 15 12:40:11 PM PDT 24 Apr 15 12:40:12 PM PDT 24 65667782 ps
T1408 /workspace/coverage/cover_reg_top/30.i2c_intr_test.2195849316 Apr 15 12:40:15 PM PDT 24 Apr 15 12:40:17 PM PDT 24 38117589 ps
T164 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2484577022 Apr 15 12:39:32 PM PDT 24 Apr 15 12:39:36 PM PDT 24 1206438270 ps
T1409 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3915841118 Apr 15 12:39:38 PM PDT 24 Apr 15 12:39:40 PM PDT 24 53781548 ps
T1410 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2521238658 Apr 15 12:40:14 PM PDT 24 Apr 15 12:40:16 PM PDT 24 78109743 ps
T1411 /workspace/coverage/cover_reg_top/35.i2c_intr_test.2536691271 Apr 15 12:40:33 PM PDT 24 Apr 15 12:40:34 PM PDT 24 47513535 ps
T1412 /workspace/coverage/cover_reg_top/33.i2c_intr_test.2987300825 Apr 15 12:40:17 PM PDT 24 Apr 15 12:40:20 PM PDT 24 49909849 ps
T1413 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.741361051 Apr 15 12:39:49 PM PDT 24 Apr 15 12:39:51 PM PDT 24 51160380 ps
T1414 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.18538433 Apr 15 12:39:47 PM PDT 24 Apr 15 12:39:50 PM PDT 24 48157156 ps
T1415 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.291683258 Apr 15 12:39:47 PM PDT 24 Apr 15 12:39:50 PM PDT 24 238785440 ps
T139 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1250128833 Apr 15 12:40:03 PM PDT 24 Apr 15 12:40:06 PM PDT 24 72102492 ps
T1416 /workspace/coverage/cover_reg_top/46.i2c_intr_test.2906940301 Apr 15 12:40:16 PM PDT 24 Apr 15 12:40:18 PM PDT 24 16111583 ps
T1417 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3381806120 Apr 15 12:39:59 PM PDT 24 Apr 15 12:40:01 PM PDT 24 202900336 ps
T140 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.496126231 Apr 15 12:40:10 PM PDT 24 Apr 15 12:40:12 PM PDT 24 46605623 ps
T1418 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3061176346 Apr 15 12:39:48 PM PDT 24 Apr 15 12:39:50 PM PDT 24 19337542 ps
T165 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3418916123 Apr 15 12:40:06 PM PDT 24 Apr 15 12:40:08 PM PDT 24 116417361 ps
T1419 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1549828388 Apr 15 12:40:07 PM PDT 24 Apr 15 12:40:10 PM PDT 24 39969059 ps
T1420 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.564634635 Apr 15 12:40:15 PM PDT 24 Apr 15 12:40:16 PM PDT 24 21658897 ps
T1421 /workspace/coverage/cover_reg_top/0.i2c_intr_test.3165037210 Apr 15 12:39:37 PM PDT 24 Apr 15 12:39:39 PM PDT 24 33369014 ps
T1422 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1113817252 Apr 15 12:40:12 PM PDT 24 Apr 15 12:40:15 PM PDT 24 62267992 ps
T1423 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1294603916 Apr 15 12:39:44 PM PDT 24 Apr 15 12:39:47 PM PDT 24 148098995 ps
T1424 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2649823204 Apr 15 12:40:08 PM PDT 24 Apr 15 12:40:09 PM PDT 24 56311098 ps
T150 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3732450580 Apr 15 12:39:56 PM PDT 24 Apr 15 12:39:59 PM PDT 24 91710873 ps
T142 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3940692661 Apr 15 12:39:33 PM PDT 24 Apr 15 12:39:36 PM PDT 24 273005262 ps
T1425 /workspace/coverage/cover_reg_top/32.i2c_intr_test.848049070 Apr 15 12:40:23 PM PDT 24 Apr 15 12:40:24 PM PDT 24 31284221 ps
T1426 /workspace/coverage/cover_reg_top/12.i2c_intr_test.3742750102 Apr 15 12:40:07 PM PDT 24 Apr 15 12:40:09 PM PDT 24 18523000 ps
T1427 /workspace/coverage/cover_reg_top/20.i2c_intr_test.2573845047 Apr 15 12:40:27 PM PDT 24 Apr 15 12:40:28 PM PDT 24 17313732 ps
T1428 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1783862329 Apr 15 12:39:38 PM PDT 24 Apr 15 12:39:41 PM PDT 24 130390443 ps
T1429 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1937541035 Apr 15 12:39:46 PM PDT 24 Apr 15 12:39:47 PM PDT 24 38135371 ps
T1430 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.279598808 Apr 15 12:40:11 PM PDT 24 Apr 15 12:40:13 PM PDT 24 70753189 ps
T1431 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1347140785 Apr 15 12:39:46 PM PDT 24 Apr 15 12:39:48 PM PDT 24 41392357 ps
T1432 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.799976596 Apr 15 12:39:48 PM PDT 24 Apr 15 12:39:51 PM PDT 24 108411382 ps
T238 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2352788661 Apr 15 12:40:10 PM PDT 24 Apr 15 12:40:12 PM PDT 24 244094428 ps
T141 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.456724107 Apr 15 12:40:02 PM PDT 24 Apr 15 12:40:05 PM PDT 24 245444118 ps
T1433 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.395993077 Apr 15 12:40:18 PM PDT 24 Apr 15 12:40:21 PM PDT 24 67104147 ps
T1434 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1033389938 Apr 15 12:39:48 PM PDT 24 Apr 15 12:39:50 PM PDT 24 84211634 ps
T1435 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.341407277 Apr 15 12:39:46 PM PDT 24 Apr 15 12:39:48 PM PDT 24 103464702 ps
T1436 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1651061246 Apr 15 12:39:35 PM PDT 24 Apr 15 12:39:38 PM PDT 24 25191364 ps
T1437 /workspace/coverage/cover_reg_top/49.i2c_intr_test.3577656754 Apr 15 12:40:12 PM PDT 24 Apr 15 12:40:13 PM PDT 24 25140655 ps
T1438 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3212872699 Apr 15 12:39:56 PM PDT 24 Apr 15 12:39:58 PM PDT 24 77992244 ps
T1439 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2872168814 Apr 15 12:39:34 PM PDT 24 Apr 15 12:39:38 PM PDT 24 1212509569 ps
T1440 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2619187934 Apr 15 12:39:42 PM PDT 24 Apr 15 12:39:44 PM PDT 24 91134712 ps
T1441 /workspace/coverage/cover_reg_top/6.i2c_intr_test.2254915241 Apr 15 12:40:04 PM PDT 24 Apr 15 12:40:06 PM PDT 24 16991929 ps
T1442 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1726334689 Apr 15 12:39:58 PM PDT 24 Apr 15 12:40:01 PM PDT 24 418101694 ps
T1443 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1051602939 Apr 15 12:40:01 PM PDT 24 Apr 15 12:40:04 PM PDT 24 167615416 ps
T1444 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3189939139 Apr 15 12:39:45 PM PDT 24 Apr 15 12:39:46 PM PDT 24 24692537 ps
T1445 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1954999876 Apr 15 12:39:33 PM PDT 24 Apr 15 12:39:36 PM PDT 24 224128986 ps
T1446 /workspace/coverage/cover_reg_top/41.i2c_intr_test.1096070716 Apr 15 12:40:05 PM PDT 24 Apr 15 12:40:07 PM PDT 24 189893181 ps
T1447 /workspace/coverage/cover_reg_top/34.i2c_intr_test.2605840654 Apr 15 12:40:15 PM PDT 24 Apr 15 12:40:18 PM PDT 24 16299531 ps
T1448 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3900451643 Apr 15 12:40:03 PM PDT 24 Apr 15 12:40:05 PM PDT 24 99994860 ps
T1449 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2534780553 Apr 15 12:40:14 PM PDT 24 Apr 15 12:40:17 PM PDT 24 132702959 ps
T1450 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1175237721 Apr 15 12:40:07 PM PDT 24 Apr 15 12:40:09 PM PDT 24 35329357 ps
T1451 /workspace/coverage/cover_reg_top/2.i2c_intr_test.3819075286 Apr 15 12:39:34 PM PDT 24 Apr 15 12:39:35 PM PDT 24 53699493 ps
T1452 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1619398350 Apr 15 12:39:53 PM PDT 24 Apr 15 12:39:54 PM PDT 24 18803399 ps
T1453 /workspace/coverage/cover_reg_top/27.i2c_intr_test.347905475 Apr 15 12:40:00 PM PDT 24 Apr 15 12:40:02 PM PDT 24 40334836 ps
T1454 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2799708199 Apr 15 12:39:47 PM PDT 24 Apr 15 12:39:49 PM PDT 24 102209175 ps
T1455 /workspace/coverage/cover_reg_top/42.i2c_intr_test.645174538 Apr 15 12:40:16 PM PDT 24 Apr 15 12:40:18 PM PDT 24 16950341 ps
T1456 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3728871217 Apr 15 12:40:13 PM PDT 24 Apr 15 12:40:15 PM PDT 24 280322716 ps
T1457 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4158582684 Apr 15 12:39:57 PM PDT 24 Apr 15 12:39:59 PM PDT 24 29482639 ps
T1458 /workspace/coverage/cover_reg_top/31.i2c_intr_test.4001982135 Apr 15 12:40:17 PM PDT 24 Apr 15 12:40:19 PM PDT 24 17116216 ps
T1459 /workspace/coverage/cover_reg_top/44.i2c_intr_test.1016617646 Apr 15 12:40:04 PM PDT 24 Apr 15 12:40:06 PM PDT 24 51117704 ps
T1460 /workspace/coverage/cover_reg_top/4.i2c_intr_test.1692541064 Apr 15 12:39:40 PM PDT 24 Apr 15 12:39:41 PM PDT 24 24148485 ps
T1461 /workspace/coverage/cover_reg_top/18.i2c_intr_test.2826691022 Apr 15 12:40:12 PM PDT 24 Apr 15 12:40:13 PM PDT 24 18557596 ps
T1462 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1788239688 Apr 15 12:40:03 PM PDT 24 Apr 15 12:40:07 PM PDT 24 47204952 ps
T1463 /workspace/coverage/cover_reg_top/16.i2c_intr_test.1215384412 Apr 15 12:40:07 PM PDT 24 Apr 15 12:40:08 PM PDT 24 22698699 ps
T1464 /workspace/coverage/cover_reg_top/5.i2c_intr_test.1129414070 Apr 15 12:39:42 PM PDT 24 Apr 15 12:39:44 PM PDT 24 27515596 ps
T1465 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3098536313 Apr 15 12:39:52 PM PDT 24 Apr 15 12:39:53 PM PDT 24 127131563 ps
T166 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3755904764 Apr 15 12:39:36 PM PDT 24 Apr 15 12:39:38 PM PDT 24 140795648 ps
T1466 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.15696679 Apr 15 12:39:51 PM PDT 24 Apr 15 12:39:53 PM PDT 24 49385415 ps
T1467 /workspace/coverage/cover_reg_top/26.i2c_intr_test.2185433321 Apr 15 12:40:14 PM PDT 24 Apr 15 12:40:15 PM PDT 24 75219135 ps
T1468 /workspace/coverage/cover_reg_top/10.i2c_intr_test.3927094526 Apr 15 12:39:48 PM PDT 24 Apr 15 12:39:50 PM PDT 24 21399379 ps
T1469 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3502181299 Apr 15 12:40:05 PM PDT 24 Apr 15 12:40:07 PM PDT 24 87528387 ps
T1470 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2104700429 Apr 15 12:39:59 PM PDT 24 Apr 15 12:40:01 PM PDT 24 35874703 ps

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.3828806371
Short name T6
Test name
Test status
Simulation time 2790770186 ps
CPU time 185.24 seconds
Started Apr 15 03:31:10 PM PDT 24
Finished Apr 15 03:34:16 PM PDT 24
Peak memory 842468 kb
Host smart-58798a6e-462c-4da0-acbd-f237392cb920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828806371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.3828806371
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.520106443
Short name T11
Test name
Test status
Simulation time 1280330206 ps
CPU time 6.96 seconds
Started Apr 15 03:30:09 PM PDT 24
Finished Apr 15 03:30:16 PM PDT 24
Peak memory 204016 kb
Host smart-fa1e9ee6-31e4-4827-81de-b3c484c9fcd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520106443 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_timeout.520106443
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.3133203559
Short name T16
Test name
Test status
Simulation time 9025667911 ps
CPU time 8.8 seconds
Started Apr 15 03:28:32 PM PDT 24
Finished Apr 15 03:28:42 PM PDT 24
Peak memory 204208 kb
Host smart-00e47e84-71cc-450b-bf64-bb9f82fba4a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133203559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.3133203559
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.1922774415
Short name T65
Test name
Test status
Simulation time 24231335296 ps
CPU time 451.75 seconds
Started Apr 15 03:34:34 PM PDT 24
Finished Apr 15 03:42:07 PM PDT 24
Peak memory 965956 kb
Host smart-258ed609-d47d-425f-9612-d6e3a755a556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922774415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.1922774415
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.774195776
Short name T116
Test name
Test status
Simulation time 209560438 ps
CPU time 1.89 seconds
Started Apr 15 12:39:55 PM PDT 24
Finished Apr 15 12:39:57 PM PDT 24
Peak memory 203732 kb
Host smart-9247c2aa-193e-4d1a-8745-0dcc0c78ccd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774195776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.774195776
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.1937577154
Short name T2
Test name
Test status
Simulation time 62374565890 ps
CPU time 286.22 seconds
Started Apr 15 03:34:50 PM PDT 24
Finished Apr 15 03:39:37 PM PDT 24
Peak memory 2756104 kb
Host smart-864d78be-c648-498c-b0de-e6d1410361e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937577154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.1937577154
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.1037657230
Short name T69
Test name
Test status
Simulation time 2379349780 ps
CPU time 6.32 seconds
Started Apr 15 03:33:58 PM PDT 24
Finished Apr 15 03:34:05 PM PDT 24
Peak memory 203988 kb
Host smart-881f08c7-eb5c-4ce9-bc3b-080abe2ff88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037657230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.1037657230
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.3809497180
Short name T36
Test name
Test status
Simulation time 10135595500 ps
CPU time 58.46 seconds
Started Apr 15 03:34:49 PM PDT 24
Finished Apr 15 03:35:48 PM PDT 24
Peak memory 479304 kb
Host smart-df5591b2-fa89-4e4c-8b1d-d324b6ae21a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809497180 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.3809497180
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_host_override.2971982238
Short name T34
Test name
Test status
Simulation time 58612769 ps
CPU time 0.66 seconds
Started Apr 15 03:34:01 PM PDT 24
Finished Apr 15 03:34:02 PM PDT 24
Peak memory 203664 kb
Host smart-c224c8b7-3ac3-4432-aa6d-8d1513abe963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971982238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2971982238
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1172282093
Short name T117
Test name
Test status
Simulation time 48742004 ps
CPU time 0.87 seconds
Started Apr 15 03:28:28 PM PDT 24
Finished Apr 15 03:28:30 PM PDT 24
Peak memory 221160 kb
Host smart-bd5f471a-fc9d-43bd-88cc-a46a975f6c1e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172282093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1172282093
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1539274116
Short name T156
Test name
Test status
Simulation time 20667830 ps
CPU time 0.74 seconds
Started Apr 15 12:39:51 PM PDT 24
Finished Apr 15 12:39:52 PM PDT 24
Peak memory 203488 kb
Host smart-4eac3264-369a-4e83-9028-c064741c00f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539274116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1539274116
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.2634409388
Short name T41
Test name
Test status
Simulation time 20328440087 ps
CPU time 174.52 seconds
Started Apr 15 03:31:32 PM PDT 24
Finished Apr 15 03:34:27 PM PDT 24
Peak memory 972360 kb
Host smart-c6964d48-cd23-45d2-9093-e20ebe5f9f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634409388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.2634409388
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.1867425006
Short name T92
Test name
Test status
Simulation time 7527650705 ps
CPU time 40.43 seconds
Started Apr 15 03:34:53 PM PDT 24
Finished Apr 15 03:35:34 PM PDT 24
Peak memory 412644 kb
Host smart-ecbedc5d-432e-4d47-9bb3-4c90bdd62e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867425006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.1867425006
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.3262184104
Short name T178
Test name
Test status
Simulation time 14666187302 ps
CPU time 365.34 seconds
Started Apr 15 03:29:05 PM PDT 24
Finished Apr 15 03:35:11 PM PDT 24
Peak memory 1065668 kb
Host smart-82599690-8b3b-4753-8eef-83aa4d65f072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262184104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.3262184104
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.1384020544
Short name T89
Test name
Test status
Simulation time 25962917912 ps
CPU time 449.24 seconds
Started Apr 15 03:29:49 PM PDT 24
Finished Apr 15 03:37:19 PM PDT 24
Peak memory 919032 kb
Host smart-32993d0d-e0e2-489b-a9fc-e3a58174d4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384020544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.1384020544
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.360379696
Short name T8
Test name
Test status
Simulation time 990978178 ps
CPU time 4.55 seconds
Started Apr 15 03:35:00 PM PDT 24
Finished Apr 15 03:35:05 PM PDT 24
Peak memory 204032 kb
Host smart-2241a777-1d16-46ee-a0d5-46a0e745e8f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360379696 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.360379696
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2330008967
Short name T134
Test name
Test status
Simulation time 293518367 ps
CPU time 1.99 seconds
Started Apr 15 12:39:48 PM PDT 24
Finished Apr 15 12:39:56 PM PDT 24
Peak memory 203852 kb
Host smart-a8de2316-2cc3-4b3b-bd8f-45dc2cd29e33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330008967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2330008967
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.1707070078
Short name T26
Test name
Test status
Simulation time 472123940 ps
CPU time 2.65 seconds
Started Apr 15 03:30:15 PM PDT 24
Finished Apr 15 03:30:18 PM PDT 24
Peak memory 204152 kb
Host smart-dd383204-8af8-4c16-82aa-4c3faee0ce3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707070078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.1707070078
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.3291912600
Short name T243
Test name
Test status
Simulation time 634740721 ps
CPU time 2.16 seconds
Started Apr 15 03:29:53 PM PDT 24
Finished Apr 15 03:29:56 PM PDT 24
Peak memory 203984 kb
Host smart-90b0e69c-0569-4d95-8cfa-6c417ecaacc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291912600 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.3291912600
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.3883029047
Short name T86
Test name
Test status
Simulation time 279095107 ps
CPU time 0.91 seconds
Started Apr 15 03:29:40 PM PDT 24
Finished Apr 15 03:29:42 PM PDT 24
Peak memory 203740 kb
Host smart-664d6109-46f2-4b43-b595-dac903573b03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883029047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.3883029047
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.1413796159
Short name T263
Test name
Test status
Simulation time 126419648728 ps
CPU time 1712.9 seconds
Started Apr 15 03:29:33 PM PDT 24
Finished Apr 15 03:58:07 PM PDT 24
Peak memory 2237980 kb
Host smart-c1ae28e1-41ff-4699-b2ca-ed86859573aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413796159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.1413796159
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_alert_test.1627445619
Short name T283
Test name
Test status
Simulation time 16158743 ps
CPU time 0.62 seconds
Started Apr 15 03:29:34 PM PDT 24
Finished Apr 15 03:29:36 PM PDT 24
Peak memory 203556 kb
Host smart-ff46b19a-4f5e-44cd-8f4b-3ac39c46d159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627445619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.1627445619
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.2350591355
Short name T81
Test name
Test status
Simulation time 933217231 ps
CPU time 16.94 seconds
Started Apr 15 03:30:46 PM PDT 24
Finished Apr 15 03:31:03 PM PDT 24
Peak memory 252004 kb
Host smart-84988a74-b9dd-4001-93aa-e7f4b4a86769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350591355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.2350591355
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.4193114833
Short name T124
Test name
Test status
Simulation time 441914808 ps
CPU time 3.23 seconds
Started Apr 15 03:29:57 PM PDT 24
Finished Apr 15 03:30:00 PM PDT 24
Peak memory 203932 kb
Host smart-1d1596d7-1cc8-4aad-93fe-ee757e557c32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193114833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.4193114833
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.668611902
Short name T229
Test name
Test status
Simulation time 317958270 ps
CPU time 1.18 seconds
Started Apr 15 03:34:03 PM PDT 24
Finished Apr 15 03:34:05 PM PDT 24
Peak memory 203896 kb
Host smart-e17b7f9c-22a1-450c-9f71-bd6b158632fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668611902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fm
t.668611902
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_target_unexp_stop.371464345
Short name T1262
Test name
Test status
Simulation time 4826790836 ps
CPU time 6.09 seconds
Started Apr 15 03:30:08 PM PDT 24
Finished Apr 15 03:30:14 PM PDT 24
Peak memory 207816 kb
Host smart-925553b6-16f2-4e55-90d7-d8b3ef9e152f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371464345 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_unexp_stop.371464345
Directory /workspace/14.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.2769995363
Short name T225
Test name
Test status
Simulation time 17933126997 ps
CPU time 1742.74 seconds
Started Apr 15 03:30:23 PM PDT 24
Finished Apr 15 03:59:26 PM PDT 24
Peak memory 4237920 kb
Host smart-6cd56614-a9a5-43b7-b2cd-5c16a18eb707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769995363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.2769995363
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.1433486957
Short name T4
Test name
Test status
Simulation time 1878136649 ps
CPU time 15.51 seconds
Started Apr 15 03:28:27 PM PDT 24
Finished Apr 15 03:28:43 PM PDT 24
Peak memory 230400 kb
Host smart-e07ea1c1-a32b-450d-8f46-34b9c450bcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433486957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.1433486957
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.1324443812
Short name T547
Test name
Test status
Simulation time 10118084765 ps
CPU time 48.95 seconds
Started Apr 15 03:33:33 PM PDT 24
Finished Apr 15 03:34:23 PM PDT 24
Peak memory 444376 kb
Host smart-1d42419e-8628-4c84-9328-04bb79e4cb47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324443812 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.1324443812
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3450204617
Short name T157
Test name
Test status
Simulation time 18451310 ps
CPU time 0.67 seconds
Started Apr 15 12:39:32 PM PDT 24
Finished Apr 15 12:39:34 PM PDT 24
Peak memory 203504 kb
Host smart-d350e792-a6b9-4618-89da-8e46d1973efa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450204617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.3450204617
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.4280751170
Short name T47
Test name
Test status
Simulation time 10290194150 ps
CPU time 95.1 seconds
Started Apr 15 03:28:37 PM PDT 24
Finished Apr 15 03:30:14 PM PDT 24
Peak memory 821968 kb
Host smart-e280f8a4-b0da-41c3-b3c0-4e32604d3a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280751170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.4280751170
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.1198215897
Short name T222
Test name
Test status
Simulation time 10167084686 ps
CPU time 37.4 seconds
Started Apr 15 03:30:22 PM PDT 24
Finished Apr 15 03:31:00 PM PDT 24
Peak memory 348736 kb
Host smart-f1c22645-5c53-4f57-93fa-4fc76b0d0aaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198215897 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.1198215897
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.2682055924
Short name T242
Test name
Test status
Simulation time 18657319256 ps
CPU time 2632.08 seconds
Started Apr 15 03:31:58 PM PDT 24
Finished Apr 15 04:15:51 PM PDT 24
Peak memory 2273040 kb
Host smart-780c8d90-9bbc-471c-b1ba-b163113549d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682055924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.2682055924
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.2852183304
Short name T253
Test name
Test status
Simulation time 1310351076 ps
CPU time 10.98 seconds
Started Apr 15 03:34:24 PM PDT 24
Finished Apr 15 03:34:35 PM PDT 24
Peak memory 220384 kb
Host smart-48f1e5d0-36d8-4ef8-ada1-a3c9fa032f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852183304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.2852183304
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.3607708732
Short name T84
Test name
Test status
Simulation time 8635248010 ps
CPU time 28.53 seconds
Started Apr 15 03:33:08 PM PDT 24
Finished Apr 15 03:33:37 PM PDT 24
Peak memory 358208 kb
Host smart-cb2e2c55-0942-405e-b4d6-5c208b151b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607708732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.3607708732
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.4196023866
Short name T143
Test name
Test status
Simulation time 89091363 ps
CPU time 1.29 seconds
Started Apr 15 12:40:10 PM PDT 24
Finished Apr 15 12:40:12 PM PDT 24
Peak memory 203856 kb
Host smart-6cfe6c9d-fba5-4bb9-9bc2-a9b93dc5cdd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196023866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.4196023866
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.3859139499
Short name T87
Test name
Test status
Simulation time 90346607951 ps
CPU time 2663.33 seconds
Started Apr 15 03:28:29 PM PDT 24
Finished Apr 15 04:12:54 PM PDT 24
Peak memory 2354856 kb
Host smart-39397990-59c8-4fe0-b321-e0238e42b235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859139499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.3859139499
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.398794906
Short name T83
Test name
Test status
Simulation time 38310409673 ps
CPU time 426.95 seconds
Started Apr 15 03:28:33 PM PDT 24
Finished Apr 15 03:35:40 PM PDT 24
Peak memory 738812 kb
Host smart-4fe83fee-40bf-489f-a412-98be9b805bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398794906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.398794906
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3308344023
Short name T138
Test name
Test status
Simulation time 108015115 ps
CPU time 2.11 seconds
Started Apr 15 12:39:33 PM PDT 24
Finished Apr 15 12:39:36 PM PDT 24
Peak memory 203792 kb
Host smart-2a363236-36bb-410d-b469-c4fad92218a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308344023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3308344023
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.29771970
Short name T1364
Test name
Test status
Simulation time 56802901 ps
CPU time 0.64 seconds
Started Apr 15 12:40:14 PM PDT 24
Finished Apr 15 12:40:16 PM PDT 24
Peak memory 203376 kb
Host smart-dbb0e634-5519-4368-98fe-eef19ff591ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29771970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.29771970
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.2096959395
Short name T246
Test name
Test status
Simulation time 1183491681 ps
CPU time 51.33 seconds
Started Apr 15 03:30:36 PM PDT 24
Finished Apr 15 03:31:28 PM PDT 24
Peak memory 204844 kb
Host smart-8e3f89d8-90e1-4e81-ab2e-6244b93b41f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096959395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.2096959395
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.2830989499
Short name T260
Test name
Test status
Simulation time 2778684337 ps
CPU time 12.6 seconds
Started Apr 15 03:30:41 PM PDT 24
Finished Apr 15 03:30:55 PM PDT 24
Peak memory 220208 kb
Host smart-dd59d4bf-8527-4619-ac6b-dcee4301bf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830989499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.2830989499
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.3721331741
Short name T258
Test name
Test status
Simulation time 765814940 ps
CPU time 13.66 seconds
Started Apr 15 03:31:45 PM PDT 24
Finished Apr 15 03:31:59 PM PDT 24
Peak memory 220416 kb
Host smart-3e01e251-b7db-4a25-bdd1-981ee05321ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721331741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3721331741
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.85030758
Short name T235
Test name
Test status
Simulation time 10174432428 ps
CPU time 69.61 seconds
Started Apr 15 03:34:19 PM PDT 24
Finished Apr 15 03:35:29 PM PDT 24
Peak memory 509528 kb
Host smart-1d6cdc77-2f0b-491f-87b6-2e3d3e4812be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85030758 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_fifo_reset_acq.85030758
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3289481525
Short name T153
Test name
Test status
Simulation time 211747315 ps
CPU time 1.25 seconds
Started Apr 15 12:39:36 PM PDT 24
Finished Apr 15 12:39:38 PM PDT 24
Peak memory 203696 kb
Host smart-5e7ac790-0186-4722-8e0c-76a96bf7bf49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289481525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3289481525
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.1838979469
Short name T54
Test name
Test status
Simulation time 10155098182 ps
CPU time 13.73 seconds
Started Apr 15 03:28:38 PM PDT 24
Finished Apr 15 03:28:52 PM PDT 24
Peak memory 272892 kb
Host smart-94ec5b4f-c18b-4e6a-b14d-1648b1588965
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838979469 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.1838979469
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3732450580
Short name T150
Test name
Test status
Simulation time 91710873 ps
CPU time 2.07 seconds
Started Apr 15 12:39:56 PM PDT 24
Finished Apr 15 12:39:59 PM PDT 24
Peak memory 203780 kb
Host smart-eb3eb898-25b2-48dc-9de9-1bfba7e1dda0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732450580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.3732450580
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.19001063
Short name T133
Test name
Test status
Simulation time 185210572 ps
CPU time 1.26 seconds
Started Apr 15 12:40:10 PM PDT 24
Finished Apr 15 12:40:12 PM PDT 24
Peak memory 203784 kb
Host smart-29bdcafe-8582-4f53-9464-b6fc8947bb77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19001063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.19001063
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.2983820580
Short name T93
Test name
Test status
Simulation time 7778677434 ps
CPU time 107.49 seconds
Started Apr 15 03:29:44 PM PDT 24
Finished Apr 15 03:31:32 PM PDT 24
Peak memory 471500 kb
Host smart-5264c135-b735-446d-8943-59307eb1eb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983820580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.2983820580
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.2095301402
Short name T1256
Test name
Test status
Simulation time 10035720018 ps
CPU time 78.94 seconds
Started Apr 15 03:29:47 PM PDT 24
Finished Apr 15 03:31:07 PM PDT 24
Peak memory 540084 kb
Host smart-f38e9520-6e65-4f70-946a-814b701a63d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095301402 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.2095301402
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1954999876
Short name T1445
Test name
Test status
Simulation time 224128986 ps
CPU time 1.87 seconds
Started Apr 15 12:39:33 PM PDT 24
Finished Apr 15 12:39:36 PM PDT 24
Peak memory 203644 kb
Host smart-48c1dddc-5d69-45f7-9d48-e6f1c77e9552
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954999876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1954999876
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2872168814
Short name T1439
Test name
Test status
Simulation time 1212509569 ps
CPU time 3.17 seconds
Started Apr 15 12:39:34 PM PDT 24
Finished Apr 15 12:39:38 PM PDT 24
Peak memory 203780 kb
Host smart-c5539556-bb01-4021-8198-b7c1b7cd9082
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872168814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.2872168814
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1567318554
Short name T175
Test name
Test status
Simulation time 25699624 ps
CPU time 0.74 seconds
Started Apr 15 12:39:30 PM PDT 24
Finished Apr 15 12:39:33 PM PDT 24
Peak memory 203472 kb
Host smart-e74add4f-9687-47f6-94b1-144a701faaef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567318554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1567318554
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1651061246
Short name T1436
Test name
Test status
Simulation time 25191364 ps
CPU time 1.11 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:38 PM PDT 24
Peak memory 203912 kb
Host smart-6f80ee07-0421-4435-a804-9776c32161e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651061246 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1651061246
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.3165037210
Short name T1421
Test name
Test status
Simulation time 33369014 ps
CPU time 0.66 seconds
Started Apr 15 12:39:37 PM PDT 24
Finished Apr 15 12:39:39 PM PDT 24
Peak memory 203448 kb
Host smart-023d65f0-7735-4f95-aa42-16983d2c74f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165037210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3165037210
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.408946992
Short name T171
Test name
Test status
Simulation time 160620196 ps
CPU time 0.9 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 203592 kb
Host smart-d5210eee-e9e7-4d61-abba-3d81dcfa4f97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408946992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_out
standing.408946992
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1783862329
Short name T1428
Test name
Test status
Simulation time 130390443 ps
CPU time 1.5 seconds
Started Apr 15 12:39:38 PM PDT 24
Finished Apr 15 12:39:41 PM PDT 24
Peak memory 203748 kb
Host smart-e3aae7a8-a4c2-469a-95ca-eea9201c62b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783862329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1783862329
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3029702188
Short name T162
Test name
Test status
Simulation time 91020805 ps
CPU time 1.75 seconds
Started Apr 15 12:39:39 PM PDT 24
Finished Apr 15 12:39:41 PM PDT 24
Peak memory 203768 kb
Host smart-47613547-7ec2-40ce-a4fc-d78947beef5f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029702188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3029702188
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2484577022
Short name T164
Test name
Test status
Simulation time 1206438270 ps
CPU time 3.03 seconds
Started Apr 15 12:39:32 PM PDT 24
Finished Apr 15 12:39:36 PM PDT 24
Peak memory 203596 kb
Host smart-99995408-609f-43b3-bf88-25426d741d69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484577022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2484577022
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1921722509
Short name T62
Test name
Test status
Simulation time 25915777 ps
CPU time 0.79 seconds
Started Apr 15 12:39:34 PM PDT 24
Finished Apr 15 12:39:35 PM PDT 24
Peak memory 203620 kb
Host smart-2afc78bd-32ac-4cfc-9567-ae0798a0cacb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921722509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1921722509
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4129868608
Short name T1390
Test name
Test status
Simulation time 57112502 ps
CPU time 0.86 seconds
Started Apr 15 12:39:37 PM PDT 24
Finished Apr 15 12:39:39 PM PDT 24
Peak memory 203668 kb
Host smart-d11e27f0-0f32-46a7-bf7a-e6a5228ac266
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129868608 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.4129868608
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3231116526
Short name T173
Test name
Test status
Simulation time 21400560 ps
CPU time 0.7 seconds
Started Apr 15 12:39:34 PM PDT 24
Finished Apr 15 12:39:36 PM PDT 24
Peak memory 203580 kb
Host smart-06c35a46-8794-4a6e-9872-e949ecdeb6ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231116526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.3231116526
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.2264754476
Short name T1369
Test name
Test status
Simulation time 43878051 ps
CPU time 0.67 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 203460 kb
Host smart-d2801efb-d9bf-4102-ad02-154a32059f8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264754476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.2264754476
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.294474839
Short name T172
Test name
Test status
Simulation time 31732090 ps
CPU time 0.85 seconds
Started Apr 15 12:39:35 PM PDT 24
Finished Apr 15 12:39:37 PM PDT 24
Peak memory 203532 kb
Host smart-10911a9d-99ce-400e-8e11-2a3667a51417
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294474839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_out
standing.294474839
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1288852217
Short name T239
Test name
Test status
Simulation time 157891144 ps
CPU time 1.29 seconds
Started Apr 15 12:39:43 PM PDT 24
Finished Apr 15 12:39:44 PM PDT 24
Peak memory 203812 kb
Host smart-7851e345-5cba-487d-aa60-f9939eb2412e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288852217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1288852217
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1937541035
Short name T1429
Test name
Test status
Simulation time 38135371 ps
CPU time 1.05 seconds
Started Apr 15 12:39:46 PM PDT 24
Finished Apr 15 12:39:47 PM PDT 24
Peak memory 203904 kb
Host smart-a1302700-7f80-40f7-96ba-a0938d98fe69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937541035 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.1937541035
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2090124291
Short name T161
Test name
Test status
Simulation time 24126780 ps
CPU time 0.68 seconds
Started Apr 15 12:39:56 PM PDT 24
Finished Apr 15 12:39:58 PM PDT 24
Peak memory 203504 kb
Host smart-55db2be7-6384-4da8-a792-b5092e688b85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090124291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.2090124291
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.3927094526
Short name T1468
Test name
Test status
Simulation time 21399379 ps
CPU time 0.65 seconds
Started Apr 15 12:39:48 PM PDT 24
Finished Apr 15 12:39:50 PM PDT 24
Peak memory 203428 kb
Host smart-28492270-0add-4e23-a3e4-941864253b67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927094526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3927094526
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.377632612
Short name T170
Test name
Test status
Simulation time 255053283 ps
CPU time 1.19 seconds
Started Apr 15 12:39:47 PM PDT 24
Finished Apr 15 12:39:49 PM PDT 24
Peak memory 203824 kb
Host smart-c3cb2371-5523-4505-a74d-b906f5ebc6fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377632612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_ou
tstanding.377632612
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2799708199
Short name T1454
Test name
Test status
Simulation time 102209175 ps
CPU time 1.46 seconds
Started Apr 15 12:39:47 PM PDT 24
Finished Apr 15 12:39:49 PM PDT 24
Peak memory 203892 kb
Host smart-ccf30132-8aa4-4a65-9cf2-224e2b29c421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799708199 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.2799708199
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2478892817
Short name T163
Test name
Test status
Simulation time 20456821 ps
CPU time 0.79 seconds
Started Apr 15 12:40:04 PM PDT 24
Finished Apr 15 12:40:06 PM PDT 24
Peak memory 203516 kb
Host smart-67eaa1ab-63d0-4470-85cc-7f35699c184b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478892817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2478892817
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.1727584867
Short name T1386
Test name
Test status
Simulation time 18748276 ps
CPU time 0.67 seconds
Started Apr 15 12:39:48 PM PDT 24
Finished Apr 15 12:39:50 PM PDT 24
Peak memory 203440 kb
Host smart-502fe779-2a68-4649-b4c4-669b1194dee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727584867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1727584867
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2344927971
Short name T1405
Test name
Test status
Simulation time 60051178 ps
CPU time 0.79 seconds
Started Apr 15 12:39:47 PM PDT 24
Finished Apr 15 12:39:48 PM PDT 24
Peak memory 203536 kb
Host smart-c3a1b289-e7f1-490f-ae0b-119409b36739
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344927971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.2344927971
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3664857786
Short name T1374
Test name
Test status
Simulation time 61360991 ps
CPU time 1.57 seconds
Started Apr 15 12:39:47 PM PDT 24
Finished Apr 15 12:39:50 PM PDT 24
Peak memory 203772 kb
Host smart-43a160e7-33d6-4d65-9e4c-29056db305d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664857786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3664857786
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3728871217
Short name T1456
Test name
Test status
Simulation time 280322716 ps
CPU time 1.44 seconds
Started Apr 15 12:40:13 PM PDT 24
Finished Apr 15 12:40:15 PM PDT 24
Peak memory 203820 kb
Host smart-34eb2a50-8bf0-467c-9ce8-3702b2f74be3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728871217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.3728871217
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3095415146
Short name T1377
Test name
Test status
Simulation time 19650124 ps
CPU time 0.77 seconds
Started Apr 15 12:40:13 PM PDT 24
Finished Apr 15 12:40:14 PM PDT 24
Peak memory 203548 kb
Host smart-a9808d7d-7d11-4ca2-a02b-b743bbee6b96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095415146 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3095415146
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.279598808
Short name T1430
Test name
Test status
Simulation time 70753189 ps
CPU time 0.76 seconds
Started Apr 15 12:40:11 PM PDT 24
Finished Apr 15 12:40:13 PM PDT 24
Peak memory 203420 kb
Host smart-b78d2d1d-ea54-4dd0-9be9-afafb4eceb14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279598808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.279598808
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.3742750102
Short name T1426
Test name
Test status
Simulation time 18523000 ps
CPU time 0.66 seconds
Started Apr 15 12:40:07 PM PDT 24
Finished Apr 15 12:40:09 PM PDT 24
Peak memory 203464 kb
Host smart-0ea2e6dd-9ddd-495a-89ca-bde77b452868
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742750102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3742750102
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.833381968
Short name T168
Test name
Test status
Simulation time 213037323 ps
CPU time 1.14 seconds
Started Apr 15 12:40:03 PM PDT 24
Finished Apr 15 12:40:06 PM PDT 24
Peak memory 203836 kb
Host smart-05700073-1b1b-4be8-822e-87e673a4656a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833381968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_ou
tstanding.833381968
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.291683258
Short name T1415
Test name
Test status
Simulation time 238785440 ps
CPU time 1.32 seconds
Started Apr 15 12:39:47 PM PDT 24
Finished Apr 15 12:39:50 PM PDT 24
Peak memory 203784 kb
Host smart-f1ffbd95-6454-4b31-a7db-9eacfb50f865
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291683258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.291683258
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.605010647
Short name T64
Test name
Test status
Simulation time 80741668 ps
CPU time 0.85 seconds
Started Apr 15 12:40:03 PM PDT 24
Finished Apr 15 12:40:05 PM PDT 24
Peak memory 203660 kb
Host smart-b388ff50-ba35-4e18-90d8-ef5eb2bac6a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605010647 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.605010647
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.167729147
Short name T1373
Test name
Test status
Simulation time 37849412 ps
CPU time 0.69 seconds
Started Apr 15 12:40:11 PM PDT 24
Finished Apr 15 12:40:13 PM PDT 24
Peak memory 203480 kb
Host smart-1dc06a17-a329-4e82-a548-870694c7fee9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167729147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.167729147
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.1004310610
Short name T1397
Test name
Test status
Simulation time 16130703 ps
CPU time 0.68 seconds
Started Apr 15 12:40:06 PM PDT 24
Finished Apr 15 12:40:08 PM PDT 24
Peak memory 203384 kb
Host smart-120db0f3-8073-4ee4-98a1-56de22a63a3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004310610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1004310610
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3098536313
Short name T1465
Test name
Test status
Simulation time 127131563 ps
CPU time 0.8 seconds
Started Apr 15 12:39:52 PM PDT 24
Finished Apr 15 12:39:53 PM PDT 24
Peak memory 203496 kb
Host smart-4d610782-5173-4638-baf4-a26889d00d48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098536313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.3098536313
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2534780553
Short name T1449
Test name
Test status
Simulation time 132702959 ps
CPU time 1.89 seconds
Started Apr 15 12:40:14 PM PDT 24
Finished Apr 15 12:40:17 PM PDT 24
Peak memory 203696 kb
Host smart-3c71476c-6efa-4c9c-9b08-08a7dd3472b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534780553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2534780553
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1051602939
Short name T1443
Test name
Test status
Simulation time 167615416 ps
CPU time 1.9 seconds
Started Apr 15 12:40:01 PM PDT 24
Finished Apr 15 12:40:04 PM PDT 24
Peak memory 203740 kb
Host smart-95175832-15f4-42a8-82f2-21cbf80ef00f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051602939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.1051602939
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2940858909
Short name T63
Test name
Test status
Simulation time 45237133 ps
CPU time 1.04 seconds
Started Apr 15 12:40:08 PM PDT 24
Finished Apr 15 12:40:10 PM PDT 24
Peak memory 203648 kb
Host smart-97951a47-f6cd-43ed-bb1e-fad4d89d5b59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940858909 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.2940858909
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2649823204
Short name T1424
Test name
Test status
Simulation time 56311098 ps
CPU time 0.77 seconds
Started Apr 15 12:40:08 PM PDT 24
Finished Apr 15 12:40:09 PM PDT 24
Peak memory 203592 kb
Host smart-db051d55-9c96-4545-b3f8-ba83c0bb72ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649823204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2649823204
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3650413840
Short name T1365
Test name
Test status
Simulation time 275127764 ps
CPU time 0.69 seconds
Started Apr 15 12:39:58 PM PDT 24
Finished Apr 15 12:39:59 PM PDT 24
Peak memory 203428 kb
Host smart-ef726d2d-f7e0-4119-8c85-8b4f2423543b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650413840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3650413840
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1471623921
Short name T1399
Test name
Test status
Simulation time 139076514 ps
CPU time 0.86 seconds
Started Apr 15 12:40:06 PM PDT 24
Finished Apr 15 12:40:07 PM PDT 24
Peak memory 203556 kb
Host smart-d248cdab-117a-4873-b059-28faad8cbd55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471623921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.1471623921
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.1549828388
Short name T1419
Test name
Test status
Simulation time 39969059 ps
CPU time 2.05 seconds
Started Apr 15 12:40:07 PM PDT 24
Finished Apr 15 12:40:10 PM PDT 24
Peak memory 203676 kb
Host smart-fd76bd78-4aa7-4741-9ea3-90677c40fe94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549828388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.1549828388
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3502181299
Short name T1469
Test name
Test status
Simulation time 87528387 ps
CPU time 1.4 seconds
Started Apr 15 12:40:05 PM PDT 24
Finished Apr 15 12:40:07 PM PDT 24
Peak memory 203768 kb
Host smart-ef7cda66-1187-4370-80af-27b8be26132c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502181299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3502181299
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2140412185
Short name T1402
Test name
Test status
Simulation time 19763217 ps
CPU time 0.79 seconds
Started Apr 15 12:40:06 PM PDT 24
Finished Apr 15 12:40:07 PM PDT 24
Peak memory 203644 kb
Host smart-0f7b49a7-cb50-4917-941c-02a27912145a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140412185 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.2140412185
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.15696679
Short name T1466
Test name
Test status
Simulation time 49385415 ps
CPU time 0.66 seconds
Started Apr 15 12:39:51 PM PDT 24
Finished Apr 15 12:39:53 PM PDT 24
Peak memory 203492 kb
Host smart-e803b95f-9d4b-456f-9d44-d88856adddaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15696679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.15696679
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.1383595768
Short name T1392
Test name
Test status
Simulation time 109511276 ps
CPU time 0.71 seconds
Started Apr 15 12:40:04 PM PDT 24
Finished Apr 15 12:40:06 PM PDT 24
Peak memory 203452 kb
Host smart-bc8d6aac-a3ab-4005-a0d3-ede1ea762ef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383595768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1383595768
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3381806120
Short name T1417
Test name
Test status
Simulation time 202900336 ps
CPU time 0.93 seconds
Started Apr 15 12:39:59 PM PDT 24
Finished Apr 15 12:40:01 PM PDT 24
Peak memory 203556 kb
Host smart-2523abca-624b-4533-aae0-92d2dbf49f84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381806120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.3381806120
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.770956613
Short name T132
Test name
Test status
Simulation time 149516323 ps
CPU time 1.34 seconds
Started Apr 15 12:39:57 PM PDT 24
Finished Apr 15 12:39:59 PM PDT 24
Peak memory 203740 kb
Host smart-38d31ddd-003d-4adb-b843-5c19b72cfcad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770956613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.770956613
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.4029295255
Short name T1388
Test name
Test status
Simulation time 32681717 ps
CPU time 0.89 seconds
Started Apr 15 12:40:13 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 203640 kb
Host smart-6a44cdb0-4144-415c-a6ea-b44d38019c74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029295255 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.4029295255
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2350434058
Short name T159
Test name
Test status
Simulation time 17398342 ps
CPU time 0.67 seconds
Started Apr 15 12:40:06 PM PDT 24
Finished Apr 15 12:40:07 PM PDT 24
Peak memory 203504 kb
Host smart-da1e4d99-a697-4572-a491-edc4d0c60750
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350434058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2350434058
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.1215384412
Short name T1463
Test name
Test status
Simulation time 22698699 ps
CPU time 0.69 seconds
Started Apr 15 12:40:07 PM PDT 24
Finished Apr 15 12:40:08 PM PDT 24
Peak memory 203456 kb
Host smart-af831826-a77e-44d9-9de0-70a96770e253
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215384412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1215384412
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3900451643
Short name T1448
Test name
Test status
Simulation time 99994860 ps
CPU time 1.18 seconds
Started Apr 15 12:40:03 PM PDT 24
Finished Apr 15 12:40:05 PM PDT 24
Peak memory 203740 kb
Host smart-b4bd24a8-a9e0-4945-bf81-2fda33b1164c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900451643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.3900451643
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.668946961
Short name T130
Test name
Test status
Simulation time 170951882 ps
CPU time 2.85 seconds
Started Apr 15 12:39:59 PM PDT 24
Finished Apr 15 12:40:03 PM PDT 24
Peak memory 203660 kb
Host smart-1641891c-633a-4c72-bea6-0266e4dd36dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668946961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.668946961
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2352788661
Short name T238
Test name
Test status
Simulation time 244094428 ps
CPU time 1.47 seconds
Started Apr 15 12:40:10 PM PDT 24
Finished Apr 15 12:40:12 PM PDT 24
Peak memory 203748 kb
Host smart-a12cb0ec-27cc-4c6b-977b-0e018f34a014
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352788661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2352788661
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.845339578
Short name T151
Test name
Test status
Simulation time 22912632 ps
CPU time 0.76 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 203576 kb
Host smart-45c9bc19-2bfa-4707-89c2-ec74b2bdba23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845339578 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.845339578
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.395993077
Short name T1433
Test name
Test status
Simulation time 67104147 ps
CPU time 0.66 seconds
Started Apr 15 12:40:18 PM PDT 24
Finished Apr 15 12:40:21 PM PDT 24
Peak memory 203472 kb
Host smart-b340420e-2e2a-444a-a00b-db11c6d77a65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395993077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.395993077
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.2472388360
Short name T1379
Test name
Test status
Simulation time 23345067 ps
CPU time 0.68 seconds
Started Apr 15 12:40:06 PM PDT 24
Finished Apr 15 12:40:08 PM PDT 24
Peak memory 203460 kb
Host smart-3ca82784-b867-43c2-95cb-18849ca2a3d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472388360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2472388360
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1175237721
Short name T1450
Test name
Test status
Simulation time 35329357 ps
CPU time 0.84 seconds
Started Apr 15 12:40:07 PM PDT 24
Finished Apr 15 12:40:09 PM PDT 24
Peak memory 203588 kb
Host smart-8343f74f-07b9-4af9-becc-4560aa5217bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175237721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.1175237721
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1113817252
Short name T1422
Test name
Test status
Simulation time 62267992 ps
CPU time 1.64 seconds
Started Apr 15 12:40:12 PM PDT 24
Finished Apr 15 12:40:15 PM PDT 24
Peak memory 203692 kb
Host smart-5f2c36a9-0b62-40b3-ba4d-b6ba485f1453
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113817252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1113817252
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.472473153
Short name T131
Test name
Test status
Simulation time 79639246 ps
CPU time 2.03 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:18 PM PDT 24
Peak memory 203732 kb
Host smart-10aab1d5-7241-46b8-af0d-b698136f6bb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472473153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.472473153
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.292097373
Short name T1394
Test name
Test status
Simulation time 26023600 ps
CPU time 0.83 seconds
Started Apr 15 12:40:05 PM PDT 24
Finished Apr 15 12:40:07 PM PDT 24
Peak memory 203584 kb
Host smart-0e4c8dc4-0dd3-4080-8b46-aea86a8478a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292097373 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.292097373
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.424094548
Short name T1389
Test name
Test status
Simulation time 17124579 ps
CPU time 0.7 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 203604 kb
Host smart-eebb6652-b5c8-40c4-8e7e-d32eb030abda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424094548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.424094548
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.2826691022
Short name T1461
Test name
Test status
Simulation time 18557596 ps
CPU time 0.75 seconds
Started Apr 15 12:40:12 PM PDT 24
Finished Apr 15 12:40:13 PM PDT 24
Peak memory 203436 kb
Host smart-d6914056-8ee4-4440-ab42-c8b2434cada3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826691022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2826691022
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2527952057
Short name T1407
Test name
Test status
Simulation time 65667782 ps
CPU time 0.82 seconds
Started Apr 15 12:40:11 PM PDT 24
Finished Apr 15 12:40:12 PM PDT 24
Peak memory 203560 kb
Host smart-2faf62d7-76e8-414e-a3e2-83ba95b1528a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527952057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2527952057
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2516463477
Short name T148
Test name
Test status
Simulation time 180692046 ps
CPU time 2.33 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:19 PM PDT 24
Peak memory 203728 kb
Host smart-283ee5eb-8aee-4de2-aed4-528d2e51b569
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516463477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2516463477
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1250128833
Short name T139
Test name
Test status
Simulation time 72102492 ps
CPU time 1.43 seconds
Started Apr 15 12:40:03 PM PDT 24
Finished Apr 15 12:40:06 PM PDT 24
Peak memory 203800 kb
Host smart-bf800531-2b93-4e7a-8a6c-52173728d4ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250128833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1250128833
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3335046311
Short name T129
Test name
Test status
Simulation time 31564629 ps
CPU time 0.89 seconds
Started Apr 15 12:40:13 PM PDT 24
Finished Apr 15 12:40:15 PM PDT 24
Peak memory 203580 kb
Host smart-b2db9eda-b533-473f-bd02-ed04b58848be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335046311 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3335046311
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.564634635
Short name T1420
Test name
Test status
Simulation time 21658897 ps
CPU time 0.69 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:16 PM PDT 24
Peak memory 203468 kb
Host smart-2688b428-23e1-4620-9f64-3da9a5d2b4e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564634635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.564634635
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.2477113788
Short name T1406
Test name
Test status
Simulation time 120432173 ps
CPU time 0.62 seconds
Started Apr 15 12:40:10 PM PDT 24
Finished Apr 15 12:40:11 PM PDT 24
Peak memory 203456 kb
Host smart-fbf17951-c78d-403d-86bf-7e7cde34cf21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477113788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2477113788
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1530915822
Short name T1401
Test name
Test status
Simulation time 123201626 ps
CPU time 1.11 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:18 PM PDT 24
Peak memory 203860 kb
Host smart-a57a1353-e21f-461c-ad94-639eec335a76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530915822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.1530915822
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2521238658
Short name T1410
Test name
Test status
Simulation time 78109743 ps
CPU time 1.69 seconds
Started Apr 15 12:40:14 PM PDT 24
Finished Apr 15 12:40:16 PM PDT 24
Peak memory 203676 kb
Host smart-0a4435c8-7169-44d1-9f5b-5a4251dac1ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521238658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2521238658
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.496126231
Short name T140
Test name
Test status
Simulation time 46605623 ps
CPU time 1.41 seconds
Started Apr 15 12:40:10 PM PDT 24
Finished Apr 15 12:40:12 PM PDT 24
Peak memory 203772 kb
Host smart-47356dff-ec5b-434f-946a-77068838d3cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496126231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.496126231
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3915841118
Short name T1409
Test name
Test status
Simulation time 53781548 ps
CPU time 1.38 seconds
Started Apr 15 12:39:38 PM PDT 24
Finished Apr 15 12:39:40 PM PDT 24
Peak memory 203696 kb
Host smart-34f408d4-ae05-438c-94e4-9d8993010a22
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915841118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3915841118
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3755904764
Short name T166
Test name
Test status
Simulation time 140795648 ps
CPU time 0.74 seconds
Started Apr 15 12:39:36 PM PDT 24
Finished Apr 15 12:39:38 PM PDT 24
Peak memory 203540 kb
Host smart-4f407c9f-55f6-4c2b-8aab-76ea74336f14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755904764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.3755904764
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2764612494
Short name T1383
Test name
Test status
Simulation time 32654036 ps
CPU time 0.91 seconds
Started Apr 15 12:39:44 PM PDT 24
Finished Apr 15 12:39:46 PM PDT 24
Peak memory 203604 kb
Host smart-19b4710b-4f48-46ed-ae0c-c1796b2afe9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764612494 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.2764612494
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.901174849
Short name T167
Test name
Test status
Simulation time 26000409 ps
CPU time 0.65 seconds
Started Apr 15 12:39:36 PM PDT 24
Finished Apr 15 12:39:38 PM PDT 24
Peak memory 203500 kb
Host smart-27aab24c-a6be-4cc2-8aae-311fbffaf592
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901174849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.901174849
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.3819075286
Short name T1451
Test name
Test status
Simulation time 53699493 ps
CPU time 0.67 seconds
Started Apr 15 12:39:34 PM PDT 24
Finished Apr 15 12:39:35 PM PDT 24
Peak memory 203464 kb
Host smart-5fad3e06-8c6c-451e-9e99-c660cdd25625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819075286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3819075286
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2619187934
Short name T1440
Test name
Test status
Simulation time 91134712 ps
CPU time 1.03 seconds
Started Apr 15 12:39:42 PM PDT 24
Finished Apr 15 12:39:44 PM PDT 24
Peak memory 203824 kb
Host smart-ac025762-8610-4d02-90f6-57b71b82b1c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619187934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.2619187934
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1294603916
Short name T1423
Test name
Test status
Simulation time 148098995 ps
CPU time 2.5 seconds
Started Apr 15 12:39:44 PM PDT 24
Finished Apr 15 12:39:47 PM PDT 24
Peak memory 203700 kb
Host smart-73eaecf5-c5ec-4144-997e-2620aafbf98b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294603916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1294603916
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3940692661
Short name T142
Test name
Test status
Simulation time 273005262 ps
CPU time 2 seconds
Started Apr 15 12:39:33 PM PDT 24
Finished Apr 15 12:39:36 PM PDT 24
Peak memory 203812 kb
Host smart-cd7261c0-7cf4-460a-ae0a-905a841640cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940692661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3940692661
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.2573845047
Short name T1427
Test name
Test status
Simulation time 17313732 ps
CPU time 0.69 seconds
Started Apr 15 12:40:27 PM PDT 24
Finished Apr 15 12:40:28 PM PDT 24
Peak memory 203432 kb
Host smart-50a81515-bd5d-45b4-9768-8f97ff7c3f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573845047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2573845047
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.1843262617
Short name T1372
Test name
Test status
Simulation time 15480204 ps
CPU time 0.65 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:19 PM PDT 24
Peak memory 203448 kb
Host smart-88989b54-cca6-4758-852c-242cad757af0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843262617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1843262617
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.3430383073
Short name T1363
Test name
Test status
Simulation time 101903941 ps
CPU time 0.7 seconds
Started Apr 15 12:40:11 PM PDT 24
Finished Apr 15 12:40:13 PM PDT 24
Peak memory 203452 kb
Host smart-3acf11d3-9b47-47a9-9ed3-e318909de615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430383073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3430383073
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.896265508
Short name T1368
Test name
Test status
Simulation time 26308436 ps
CPU time 0.66 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:16 PM PDT 24
Peak memory 203468 kb
Host smart-f949d48c-f2f7-45b0-8fbe-630131696b23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896265508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.896265508
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3553225523
Short name T1371
Test name
Test status
Simulation time 152284689 ps
CPU time 0.68 seconds
Started Apr 15 12:40:10 PM PDT 24
Finished Apr 15 12:40:11 PM PDT 24
Peak memory 203440 kb
Host smart-045c5bf5-8f07-40f4-aa27-7061e77e723c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553225523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3553225523
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.2185433321
Short name T1467
Test name
Test status
Simulation time 75219135 ps
CPU time 0.65 seconds
Started Apr 15 12:40:14 PM PDT 24
Finished Apr 15 12:40:15 PM PDT 24
Peak memory 203440 kb
Host smart-ed56b4a2-9cf3-42d5-8c4a-b21b8880392f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185433321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2185433321
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.347905475
Short name T1453
Test name
Test status
Simulation time 40334836 ps
CPU time 0.66 seconds
Started Apr 15 12:40:00 PM PDT 24
Finished Apr 15 12:40:02 PM PDT 24
Peak memory 203448 kb
Host smart-9fcdf1aa-a95f-4b9f-bd59-96dd6ec99935
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347905475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.347905475
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.2048341671
Short name T1366
Test name
Test status
Simulation time 32346368 ps
CPU time 0.63 seconds
Started Apr 15 12:40:14 PM PDT 24
Finished Apr 15 12:40:15 PM PDT 24
Peak memory 203444 kb
Host smart-a3f501a7-2808-4958-9f99-4df61ada8c7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048341671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.2048341671
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.3328836570
Short name T1378
Test name
Test status
Simulation time 20682594 ps
CPU time 0.73 seconds
Started Apr 15 12:40:09 PM PDT 24
Finished Apr 15 12:40:10 PM PDT 24
Peak memory 203464 kb
Host smart-422a4840-93e2-447a-b88c-810927949fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328836570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3328836570
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3418916123
Short name T165
Test name
Test status
Simulation time 116417361 ps
CPU time 1.23 seconds
Started Apr 15 12:40:06 PM PDT 24
Finished Apr 15 12:40:08 PM PDT 24
Peak memory 203732 kb
Host smart-de56755c-9ea7-49f6-b229-2baec7fb3cc9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418916123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3418916123
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3241291789
Short name T1395
Test name
Test status
Simulation time 2122651492 ps
CPU time 5.87 seconds
Started Apr 15 12:39:48 PM PDT 24
Finished Apr 15 12:39:55 PM PDT 24
Peak memory 203784 kb
Host smart-aa0533f4-12c1-4fc3-bd84-82c841ffcf13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241291789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3241291789
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3189939139
Short name T1444
Test name
Test status
Simulation time 24692537 ps
CPU time 0.79 seconds
Started Apr 15 12:39:45 PM PDT 24
Finished Apr 15 12:39:46 PM PDT 24
Peak memory 203580 kb
Host smart-429cf2ab-3066-446e-9575-84fe4a76d3ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189939139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3189939139
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2280745885
Short name T1380
Test name
Test status
Simulation time 102563706 ps
CPU time 0.9 seconds
Started Apr 15 12:39:47 PM PDT 24
Finished Apr 15 12:39:49 PM PDT 24
Peak memory 203668 kb
Host smart-9d4839f1-9e43-4a34-8841-f45bec2899d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280745885 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.2280745885
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3130646286
Short name T1398
Test name
Test status
Simulation time 58280623 ps
CPU time 0.68 seconds
Started Apr 15 12:39:44 PM PDT 24
Finished Apr 15 12:39:46 PM PDT 24
Peak memory 203496 kb
Host smart-e7bbc134-8eb1-4b02-9281-cc0f1cb71d9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130646286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3130646286
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.4029697853
Short name T1361
Test name
Test status
Simulation time 17237905 ps
CPU time 0.65 seconds
Started Apr 15 12:39:52 PM PDT 24
Finished Apr 15 12:39:53 PM PDT 24
Peak memory 203400 kb
Host smart-57fc379f-19ce-4135-ba14-4787759ef3e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029697853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.4029697853
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1033389938
Short name T1434
Test name
Test status
Simulation time 84211634 ps
CPU time 1.06 seconds
Started Apr 15 12:39:48 PM PDT 24
Finished Apr 15 12:39:50 PM PDT 24
Peak memory 203840 kb
Host smart-dd6c14c0-961a-4945-aac3-c8e85c5d63a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033389938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.1033389938
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.341407277
Short name T1435
Test name
Test status
Simulation time 103464702 ps
CPU time 2.11 seconds
Started Apr 15 12:39:46 PM PDT 24
Finished Apr 15 12:39:48 PM PDT 24
Peak memory 203660 kb
Host smart-e7a6db17-c9c4-4771-9a04-75839fc8b9d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341407277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.341407277
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.629403885
Short name T1381
Test name
Test status
Simulation time 88368207 ps
CPU time 1.31 seconds
Started Apr 15 12:39:56 PM PDT 24
Finished Apr 15 12:40:03 PM PDT 24
Peak memory 203824 kb
Host smart-07444a69-4270-41ff-a95d-e816385b4750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629403885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.629403885
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.2195849316
Short name T1408
Test name
Test status
Simulation time 38117589 ps
CPU time 0.64 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:17 PM PDT 24
Peak memory 203392 kb
Host smart-572258bf-c714-4b2e-aa60-f6db21208181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195849316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2195849316
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.4001982135
Short name T1458
Test name
Test status
Simulation time 17116216 ps
CPU time 0.63 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:19 PM PDT 24
Peak memory 203420 kb
Host smart-0a4f4b25-c0be-4f01-95ca-9990006ec5bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001982135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.4001982135
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.848049070
Short name T1425
Test name
Test status
Simulation time 31284221 ps
CPU time 0.66 seconds
Started Apr 15 12:40:23 PM PDT 24
Finished Apr 15 12:40:24 PM PDT 24
Peak memory 203452 kb
Host smart-f0376943-0f70-4fbd-81d8-e13fa6041a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848049070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.848049070
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.2987300825
Short name T1412
Test name
Test status
Simulation time 49909849 ps
CPU time 0.61 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 203088 kb
Host smart-0a463f19-26df-47fd-875d-969b1b19bc98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987300825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.2987300825
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.2605840654
Short name T1447
Test name
Test status
Simulation time 16299531 ps
CPU time 0.67 seconds
Started Apr 15 12:40:15 PM PDT 24
Finished Apr 15 12:40:18 PM PDT 24
Peak memory 203412 kb
Host smart-f7915f4f-4df3-4714-9c3a-097dca49a138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605840654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2605840654
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.2536691271
Short name T1411
Test name
Test status
Simulation time 47513535 ps
CPU time 0.77 seconds
Started Apr 15 12:40:33 PM PDT 24
Finished Apr 15 12:40:34 PM PDT 24
Peak memory 203440 kb
Host smart-62823ac9-f670-4ad7-8052-afcb2417fa73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536691271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.2536691271
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.3499991932
Short name T1376
Test name
Test status
Simulation time 45388398 ps
CPU time 0.67 seconds
Started Apr 15 12:40:11 PM PDT 24
Finished Apr 15 12:40:12 PM PDT 24
Peak memory 203448 kb
Host smart-a333eb43-7d6b-4db6-a50c-51d88cab598b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499991932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3499991932
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.3745506270
Short name T1382
Test name
Test status
Simulation time 44834020 ps
CPU time 0.7 seconds
Started Apr 15 12:40:10 PM PDT 24
Finished Apr 15 12:40:11 PM PDT 24
Peak memory 203444 kb
Host smart-9309e550-269d-463c-8272-5b1a90dee9f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745506270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3745506270
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.1586617793
Short name T1393
Test name
Test status
Simulation time 30363344 ps
CPU time 0.66 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 203352 kb
Host smart-757a9fa7-7fab-46c0-a090-099b46224a51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586617793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1586617793
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1426796077
Short name T1370
Test name
Test status
Simulation time 54493156 ps
CPU time 0.71 seconds
Started Apr 15 12:40:07 PM PDT 24
Finished Apr 15 12:40:09 PM PDT 24
Peak memory 203392 kb
Host smart-a6823583-5f0a-4ae8-bdbb-df08a3500e54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426796077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1426796077
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1200835881
Short name T155
Test name
Test status
Simulation time 99916278 ps
CPU time 1.21 seconds
Started Apr 15 12:39:47 PM PDT 24
Finished Apr 15 12:39:49 PM PDT 24
Peak memory 203736 kb
Host smart-561f74b2-a4a8-4394-a960-e7a84168e94a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200835881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1200835881
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3341430164
Short name T137
Test name
Test status
Simulation time 26016506 ps
CPU time 1.16 seconds
Started Apr 15 12:39:52 PM PDT 24
Finished Apr 15 12:39:53 PM PDT 24
Peak memory 203760 kb
Host smart-840fe6b4-23f5-4356-a499-58e55f40f8e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341430164 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3341430164
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1544300830
Short name T1404
Test name
Test status
Simulation time 42966514 ps
CPU time 0.76 seconds
Started Apr 15 12:39:42 PM PDT 24
Finished Apr 15 12:39:48 PM PDT 24
Peak memory 203556 kb
Host smart-4fbb1b72-f9e8-46e2-a027-77ba36714d2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544300830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1544300830
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.1692541064
Short name T1460
Test name
Test status
Simulation time 24148485 ps
CPU time 0.64 seconds
Started Apr 15 12:39:40 PM PDT 24
Finished Apr 15 12:39:41 PM PDT 24
Peak memory 203448 kb
Host smart-2d781a75-5cb0-463f-8859-0664a0e47b39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692541064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1692541064
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2104700429
Short name T1470
Test name
Test status
Simulation time 35874703 ps
CPU time 0.85 seconds
Started Apr 15 12:39:59 PM PDT 24
Finished Apr 15 12:40:01 PM PDT 24
Peak memory 203572 kb
Host smart-133fd7f8-284c-4630-a193-fca2134b3b91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104700429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.2104700429
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1260697533
Short name T192
Test name
Test status
Simulation time 120880178 ps
CPU time 2.12 seconds
Started Apr 15 12:39:55 PM PDT 24
Finished Apr 15 12:39:58 PM PDT 24
Peak memory 203700 kb
Host smart-7b3a62bb-88e2-4aaf-b5be-2ac25fa73a7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260697533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.1260697533
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1459775513
Short name T146
Test name
Test status
Simulation time 128870472 ps
CPU time 2.33 seconds
Started Apr 15 12:39:40 PM PDT 24
Finished Apr 15 12:39:43 PM PDT 24
Peak memory 203800 kb
Host smart-04e41258-8f9e-4488-af0c-957823f85a17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459775513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.1459775513
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.754953690
Short name T1387
Test name
Test status
Simulation time 24835343 ps
CPU time 0.68 seconds
Started Apr 15 12:40:10 PM PDT 24
Finished Apr 15 12:40:12 PM PDT 24
Peak memory 203444 kb
Host smart-0cf94f33-c266-4d34-ac38-ce8a7e64572d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754953690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.754953690
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.1096070716
Short name T1446
Test name
Test status
Simulation time 189893181 ps
CPU time 0.7 seconds
Started Apr 15 12:40:05 PM PDT 24
Finished Apr 15 12:40:07 PM PDT 24
Peak memory 203416 kb
Host smart-723571d9-8370-40cf-a97e-355cc0592fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096070716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1096070716
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.645174538
Short name T1455
Test name
Test status
Simulation time 16950341 ps
CPU time 0.65 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:18 PM PDT 24
Peak memory 203348 kb
Host smart-a5877710-f6a9-48f5-a358-e1dcadaa1754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645174538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.645174538
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.938888304
Short name T1367
Test name
Test status
Simulation time 28136901 ps
CPU time 0.68 seconds
Started Apr 15 12:40:05 PM PDT 24
Finished Apr 15 12:40:06 PM PDT 24
Peak memory 203448 kb
Host smart-da04f745-603c-412a-9ece-8376ca46bce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938888304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.938888304
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1016617646
Short name T1459
Test name
Test status
Simulation time 51117704 ps
CPU time 0.66 seconds
Started Apr 15 12:40:04 PM PDT 24
Finished Apr 15 12:40:06 PM PDT 24
Peak memory 203444 kb
Host smart-b7d8892d-eca3-41c8-8fa6-b00b9e956d0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016617646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1016617646
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.3088448651
Short name T1385
Test name
Test status
Simulation time 64194539 ps
CPU time 0.67 seconds
Started Apr 15 12:40:03 PM PDT 24
Finished Apr 15 12:40:05 PM PDT 24
Peak memory 203388 kb
Host smart-cf045a23-105b-460c-a35e-dfa0445ab2d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088448651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.3088448651
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.2906940301
Short name T1416
Test name
Test status
Simulation time 16111583 ps
CPU time 0.65 seconds
Started Apr 15 12:40:16 PM PDT 24
Finished Apr 15 12:40:18 PM PDT 24
Peak memory 203348 kb
Host smart-f64733ff-46a2-42cb-97fa-15873cd4735a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906940301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2906940301
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.277451449
Short name T1362
Test name
Test status
Simulation time 17445483 ps
CPU time 0.69 seconds
Started Apr 15 12:40:08 PM PDT 24
Finished Apr 15 12:40:09 PM PDT 24
Peak memory 203392 kb
Host smart-b16f5311-d98e-455f-944b-75b1906f17eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277451449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.277451449
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.2786156090
Short name T1384
Test name
Test status
Simulation time 42735176 ps
CPU time 0.68 seconds
Started Apr 15 12:40:17 PM PDT 24
Finished Apr 15 12:40:20 PM PDT 24
Peak memory 203352 kb
Host smart-9329e862-ccba-4dd0-ad45-c0949cfaf31e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786156090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2786156090
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.3577656754
Short name T1437
Test name
Test status
Simulation time 25140655 ps
CPU time 0.65 seconds
Started Apr 15 12:40:12 PM PDT 24
Finished Apr 15 12:40:13 PM PDT 24
Peak memory 203456 kb
Host smart-68a252c0-b589-4d62-b6ad-7d93b11109c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577656754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.3577656754
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3212872699
Short name T1438
Test name
Test status
Simulation time 77992244 ps
CPU time 0.78 seconds
Started Apr 15 12:39:56 PM PDT 24
Finished Apr 15 12:39:58 PM PDT 24
Peak memory 203648 kb
Host smart-5d1ba011-4dd7-4108-a7f2-ec52022fa80b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212872699 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3212872699
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1608365660
Short name T158
Test name
Test status
Simulation time 66818046 ps
CPU time 0.75 seconds
Started Apr 15 12:39:44 PM PDT 24
Finished Apr 15 12:39:45 PM PDT 24
Peak memory 203584 kb
Host smart-6a6c9317-d347-4581-9253-94a768cf5842
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608365660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1608365660
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.1129414070
Short name T1464
Test name
Test status
Simulation time 27515596 ps
CPU time 0.67 seconds
Started Apr 15 12:39:42 PM PDT 24
Finished Apr 15 12:39:44 PM PDT 24
Peak memory 203416 kb
Host smart-7eaece1b-aea1-4632-b0f3-bfc67974d61c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129414070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.1129414070
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4158582684
Short name T1457
Test name
Test status
Simulation time 29482639 ps
CPU time 1.06 seconds
Started Apr 15 12:39:57 PM PDT 24
Finished Apr 15 12:39:59 PM PDT 24
Peak memory 203812 kb
Host smart-2263ab53-d952-4fc1-aca3-e9ae829359b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158582684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.4158582684
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3402218019
Short name T135
Test name
Test status
Simulation time 203791142 ps
CPU time 1.69 seconds
Started Apr 15 12:39:54 PM PDT 24
Finished Apr 15 12:39:56 PM PDT 24
Peak memory 203736 kb
Host smart-073d3e9b-4d0e-4a06-8150-0fdd028a9502
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402218019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3402218019
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.456724107
Short name T141
Test name
Test status
Simulation time 245444118 ps
CPU time 2.11 seconds
Started Apr 15 12:40:02 PM PDT 24
Finished Apr 15 12:40:05 PM PDT 24
Peak memory 203728 kb
Host smart-b194cabb-9c86-489a-8bc6-942f8056f24a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456724107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.456724107
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.4244138922
Short name T152
Test name
Test status
Simulation time 26955019 ps
CPU time 0.81 seconds
Started Apr 15 12:39:49 PM PDT 24
Finished Apr 15 12:39:50 PM PDT 24
Peak memory 203652 kb
Host smart-5df482bb-6ea1-49e5-a7d2-28902a24f73a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244138922 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.4244138922
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.1293198774
Short name T154
Test name
Test status
Simulation time 38453739 ps
CPU time 0.64 seconds
Started Apr 15 12:39:47 PM PDT 24
Finished Apr 15 12:39:49 PM PDT 24
Peak memory 203492 kb
Host smart-fcda8ada-f864-4a7d-95b4-b9a9911d1fa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293198774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1293198774
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.2254915241
Short name T1441
Test name
Test status
Simulation time 16991929 ps
CPU time 0.68 seconds
Started Apr 15 12:40:04 PM PDT 24
Finished Apr 15 12:40:06 PM PDT 24
Peak memory 203456 kb
Host smart-d107712e-97d5-447c-98ab-10f7d50e662e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254915241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2254915241
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1583602790
Short name T176
Test name
Test status
Simulation time 56299819 ps
CPU time 1.23 seconds
Started Apr 15 12:39:42 PM PDT 24
Finished Apr 15 12:39:44 PM PDT 24
Peak memory 203720 kb
Host smart-f64b3e8c-f8f0-4084-ac49-26bc38063bba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583602790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.1583602790
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.799976596
Short name T1432
Test name
Test status
Simulation time 108411382 ps
CPU time 1.32 seconds
Started Apr 15 12:39:48 PM PDT 24
Finished Apr 15 12:39:51 PM PDT 24
Peak memory 203680 kb
Host smart-153518b6-d210-4371-ad44-d3e94a650c3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799976596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.799976596
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.1554236373
Short name T147
Test name
Test status
Simulation time 60949121 ps
CPU time 1.37 seconds
Started Apr 15 12:39:54 PM PDT 24
Finished Apr 15 12:39:56 PM PDT 24
Peak memory 203800 kb
Host smart-b42240df-2f44-476a-b688-ffc1afba6d36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554236373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.1554236373
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1347140785
Short name T1431
Test name
Test status
Simulation time 41392357 ps
CPU time 0.79 seconds
Started Apr 15 12:39:46 PM PDT 24
Finished Apr 15 12:39:48 PM PDT 24
Peak memory 203624 kb
Host smart-b8d8dc68-5a80-4b7d-9d1a-276911336603
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347140785 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1347140785
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3745544617
Short name T169
Test name
Test status
Simulation time 18624597 ps
CPU time 0.82 seconds
Started Apr 15 12:39:46 PM PDT 24
Finished Apr 15 12:39:48 PM PDT 24
Peak memory 203512 kb
Host smart-291d0145-a915-41fb-826d-f9a2d4b0a0fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745544617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3745544617
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.4012442930
Short name T1375
Test name
Test status
Simulation time 63433915 ps
CPU time 0.73 seconds
Started Apr 15 12:39:59 PM PDT 24
Finished Apr 15 12:40:01 PM PDT 24
Peak memory 203456 kb
Host smart-35403ba4-bcda-455b-9b06-b183d5022db1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012442930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.4012442930
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.741361051
Short name T1413
Test name
Test status
Simulation time 51160380 ps
CPU time 1.05 seconds
Started Apr 15 12:39:49 PM PDT 24
Finished Apr 15 12:39:51 PM PDT 24
Peak memory 203816 kb
Host smart-dc70f02b-aa84-477f-9976-3edb02c6d799
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741361051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_out
standing.741361051
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1726334689
Short name T1442
Test name
Test status
Simulation time 418101694 ps
CPU time 2.29 seconds
Started Apr 15 12:39:58 PM PDT 24
Finished Apr 15 12:40:01 PM PDT 24
Peak memory 203756 kb
Host smart-2b8aa680-2af4-4a73-8229-cac4d4e54d64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726334689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.1726334689
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.37112549
Short name T149
Test name
Test status
Simulation time 90344437 ps
CPU time 1.15 seconds
Started Apr 15 12:40:03 PM PDT 24
Finished Apr 15 12:40:05 PM PDT 24
Peak memory 203752 kb
Host smart-789810b8-3e65-4fee-85f5-703786bfe314
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37112549 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.37112549
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1619398350
Short name T1452
Test name
Test status
Simulation time 18803399 ps
CPU time 0.75 seconds
Started Apr 15 12:39:53 PM PDT 24
Finished Apr 15 12:39:54 PM PDT 24
Peak memory 203600 kb
Host smart-2e2e6a07-b5c6-4aef-ae62-6dae2c5bc8ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619398350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1619398350
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1060313488
Short name T1400
Test name
Test status
Simulation time 24144539 ps
CPU time 0.69 seconds
Started Apr 15 12:39:56 PM PDT 24
Finished Apr 15 12:39:58 PM PDT 24
Peak memory 203432 kb
Host smart-809c71c9-3a64-4e48-a3f9-e9674faf633f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060313488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1060313488
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3297262708
Short name T1396
Test name
Test status
Simulation time 59972572 ps
CPU time 1.12 seconds
Started Apr 15 12:39:46 PM PDT 24
Finished Apr 15 12:39:48 PM PDT 24
Peak memory 203800 kb
Host smart-9558b99a-021e-429b-bcd3-a8ad3809fc61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297262708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.3297262708
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1788239688
Short name T1462
Test name
Test status
Simulation time 47204952 ps
CPU time 2.34 seconds
Started Apr 15 12:40:03 PM PDT 24
Finished Apr 15 12:40:07 PM PDT 24
Peak memory 203668 kb
Host smart-94a079e7-665c-494f-9f74-10d2085ab632
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788239688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1788239688
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.662321073
Short name T145
Test name
Test status
Simulation time 271243762 ps
CPU time 1.5 seconds
Started Apr 15 12:40:02 PM PDT 24
Finished Apr 15 12:40:04 PM PDT 24
Peak memory 203756 kb
Host smart-35cf9e8f-db39-4031-88a0-9e8de8d21ac6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662321073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.662321073
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3061176346
Short name T1418
Test name
Test status
Simulation time 19337542 ps
CPU time 0.82 seconds
Started Apr 15 12:39:48 PM PDT 24
Finished Apr 15 12:39:50 PM PDT 24
Peak memory 203568 kb
Host smart-fa842129-92f4-45e7-b2b6-f5d2959c5b19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061176346 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3061176346
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.4074449636
Short name T160
Test name
Test status
Simulation time 54405887 ps
CPU time 0.75 seconds
Started Apr 15 12:39:55 PM PDT 24
Finished Apr 15 12:39:56 PM PDT 24
Peak memory 203476 kb
Host smart-890c7d67-e529-4966-a35d-23d21a47af8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074449636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.4074449636
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.362190467
Short name T1403
Test name
Test status
Simulation time 18854377 ps
CPU time 0.66 seconds
Started Apr 15 12:40:01 PM PDT 24
Finished Apr 15 12:40:03 PM PDT 24
Peak memory 203444 kb
Host smart-c16fe199-83a3-4d65-afcb-0d1f0e1acfb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362190467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.362190467
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3222164708
Short name T1391
Test name
Test status
Simulation time 35752110 ps
CPU time 0.94 seconds
Started Apr 15 12:40:01 PM PDT 24
Finished Apr 15 12:40:03 PM PDT 24
Peak memory 203616 kb
Host smart-ec402737-9855-41f1-b6a8-e7388e73f119
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222164708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.3222164708
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.18538433
Short name T1414
Test name
Test status
Simulation time 48157156 ps
CPU time 2.2 seconds
Started Apr 15 12:39:47 PM PDT 24
Finished Apr 15 12:39:50 PM PDT 24
Peak memory 203728 kb
Host smart-856ab850-d4e6-4f16-b948-c748d335f205
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18538433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.18538433
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3875719269
Short name T144
Test name
Test status
Simulation time 151698931 ps
CPU time 1.45 seconds
Started Apr 15 12:39:51 PM PDT 24
Finished Apr 15 12:39:53 PM PDT 24
Peak memory 203856 kb
Host smart-52f8c6de-d434-40ec-bd6e-4fc71957d934
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875719269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.3875719269
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.1033376477
Short name T647
Test name
Test status
Simulation time 18113163 ps
CPU time 0.64 seconds
Started Apr 15 03:28:29 PM PDT 24
Finished Apr 15 03:28:30 PM PDT 24
Peak memory 203568 kb
Host smart-46c94a5b-595f-4634-9d29-e02ea18e5be5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033376477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.1033376477
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.3989497380
Short name T1070
Test name
Test status
Simulation time 146767432 ps
CPU time 1.25 seconds
Started Apr 15 03:28:29 PM PDT 24
Finished Apr 15 03:28:31 PM PDT 24
Peak memory 212288 kb
Host smart-5d365212-4d2e-40e6-861e-b864122ab34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989497380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.3989497380
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2205347471
Short name T365
Test name
Test status
Simulation time 738948567 ps
CPU time 5.04 seconds
Started Apr 15 03:28:25 PM PDT 24
Finished Apr 15 03:28:31 PM PDT 24
Peak memory 255572 kb
Host smart-6a366c97-b153-49ea-bc3c-f83871bad808
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205347471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.2205347471
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.2761024856
Short name T308
Test name
Test status
Simulation time 4765209054 ps
CPU time 206.68 seconds
Started Apr 15 03:28:28 PM PDT 24
Finished Apr 15 03:31:55 PM PDT 24
Peak memory 821660 kb
Host smart-4238a229-b2c8-4c4d-bbce-59087e55a66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761024856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.2761024856
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.1101047245
Short name T955
Test name
Test status
Simulation time 3296761255 ps
CPU time 45.65 seconds
Started Apr 15 03:28:26 PM PDT 24
Finished Apr 15 03:29:13 PM PDT 24
Peak memory 481852 kb
Host smart-986af2ad-363f-41a3-b1d3-7f3b930f6406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101047245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.1101047245
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.2818364937
Short name T1267
Test name
Test status
Simulation time 124416409 ps
CPU time 1.01 seconds
Started Apr 15 03:28:27 PM PDT 24
Finished Apr 15 03:28:29 PM PDT 24
Peak memory 203756 kb
Host smart-bf1999a9-9f4e-4f54-90a9-d45143284baf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818364937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.2818364937
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.652185185
Short name T877
Test name
Test status
Simulation time 345089494 ps
CPU time 5.54 seconds
Started Apr 15 03:28:26 PM PDT 24
Finished Apr 15 03:28:33 PM PDT 24
Peak memory 217128 kb
Host smart-792148ac-bcd2-48ac-ab29-dd747b0b6b9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652185185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.652185185
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.1891502512
Short name T1253
Test name
Test status
Simulation time 15486219006 ps
CPU time 102.9 seconds
Started Apr 15 03:28:27 PM PDT 24
Finished Apr 15 03:30:10 PM PDT 24
Peak memory 1168868 kb
Host smart-4b7a7ea5-6513-4b80-8f6d-2c2d06e220ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891502512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1891502512
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.3995988182
Short name T1104
Test name
Test status
Simulation time 609851071 ps
CPU time 27.15 seconds
Started Apr 15 03:28:31 PM PDT 24
Finished Apr 15 03:28:58 PM PDT 24
Peak memory 204012 kb
Host smart-63a5ace3-bc28-43cb-855d-36069a93bf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995988182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.3995988182
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.2971065150
Short name T1163
Test name
Test status
Simulation time 6320886903 ps
CPU time 34.18 seconds
Started Apr 15 03:28:30 PM PDT 24
Finished Apr 15 03:29:05 PM PDT 24
Peak memory 405676 kb
Host smart-2ac3a022-5ddc-4c10-968c-799ad2f5ecbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971065150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.2971065150
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.3715123525
Short name T7
Test name
Test status
Simulation time 17815311 ps
CPU time 0.66 seconds
Started Apr 15 03:28:29 PM PDT 24
Finished Apr 15 03:28:30 PM PDT 24
Peak memory 203636 kb
Host smart-4e651bb3-f6ee-4ed4-ab68-c8f4fccde73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715123525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3715123525
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.494694044
Short name T1017
Test name
Test status
Simulation time 4925947880 ps
CPU time 212.61 seconds
Started Apr 15 03:28:25 PM PDT 24
Finished Apr 15 03:31:58 PM PDT 24
Peak memory 212192 kb
Host smart-7d56101b-2bbb-4552-b822-dee0e9191758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494694044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.494694044
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.3145076132
Short name T976
Test name
Test status
Simulation time 5478642501 ps
CPU time 21.15 seconds
Started Apr 15 03:28:27 PM PDT 24
Finished Apr 15 03:28:49 PM PDT 24
Peak memory 304768 kb
Host smart-27535ccf-37af-4b17-a0bf-2ff2620eb0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145076132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.3145076132
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.3742483434
Short name T1194
Test name
Test status
Simulation time 742566740 ps
CPU time 3.55 seconds
Started Apr 15 03:28:27 PM PDT 24
Finished Apr 15 03:28:31 PM PDT 24
Peak memory 204056 kb
Host smart-b70f0077-54d8-4a3e-a087-5d6afa04f937
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742483434 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.3742483434
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2070167831
Short name T1289
Test name
Test status
Simulation time 10322364280 ps
CPU time 7.06 seconds
Started Apr 15 03:28:27 PM PDT 24
Finished Apr 15 03:28:35 PM PDT 24
Peak memory 232548 kb
Host smart-3fb7f3d4-d935-4ebe-821d-86aeefb3afdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070167831 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2070167831
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.2613295889
Short name T673
Test name
Test status
Simulation time 10243734501 ps
CPU time 34.11 seconds
Started Apr 15 03:28:28 PM PDT 24
Finished Apr 15 03:29:03 PM PDT 24
Peak memory 373212 kb
Host smart-a0860b62-4bae-4c12-a7a1-895e378703e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613295889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.2613295889
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.482244253
Short name T23
Test name
Test status
Simulation time 6766591985 ps
CPU time 10.46 seconds
Started Apr 15 03:28:24 PM PDT 24
Finished Apr 15 03:28:36 PM PDT 24
Peak memory 204252 kb
Host smart-683edba3-e7c0-4e75-b274-7dde5837b4a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482244253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.482244253
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.219311156
Short name T755
Test name
Test status
Simulation time 4519778240 ps
CPU time 2.53 seconds
Started Apr 15 03:28:30 PM PDT 24
Finished Apr 15 03:28:33 PM PDT 24
Peak memory 204008 kb
Host smart-674dad7e-f227-4e86-b67a-3c2fbd8dae32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219311156 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.i2c_target_hrst.219311156
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.1629975484
Short name T892
Test name
Test status
Simulation time 1810096233 ps
CPU time 4.44 seconds
Started Apr 15 03:28:29 PM PDT 24
Finished Apr 15 03:28:34 PM PDT 24
Peak memory 203988 kb
Host smart-acea8518-f872-4f4a-9057-3d88d2e3498e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629975484 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.1629975484
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.251917024
Short name T204
Test name
Test status
Simulation time 20810992059 ps
CPU time 58.91 seconds
Started Apr 15 03:28:29 PM PDT 24
Finished Apr 15 03:29:29 PM PDT 24
Peak memory 872728 kb
Host smart-22ab7920-d96c-4e30-89ac-0f0293e25696
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251917024 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.251917024
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.2255219962
Short name T1168
Test name
Test status
Simulation time 885658366 ps
CPU time 21.65 seconds
Started Apr 15 03:28:26 PM PDT 24
Finished Apr 15 03:28:48 PM PDT 24
Peak memory 204008 kb
Host smart-9405fc1a-0c13-49b2-b4db-c8b38b257966
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255219962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.2255219962
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.3346081196
Short name T1021
Test name
Test status
Simulation time 995039282 ps
CPU time 14.82 seconds
Started Apr 15 03:28:26 PM PDT 24
Finished Apr 15 03:28:42 PM PDT 24
Peak memory 214728 kb
Host smart-ef6094e9-fc7e-4327-a745-f43535eb87ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346081196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.3346081196
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.3295847259
Short name T780
Test name
Test status
Simulation time 9144211883 ps
CPU time 3.06 seconds
Started Apr 15 03:28:29 PM PDT 24
Finished Apr 15 03:28:33 PM PDT 24
Peak memory 204028 kb
Host smart-80ad58e5-c6ae-4683-bf7b-9f15b987fb5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295847259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.3295847259
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.326828399
Short name T832
Test name
Test status
Simulation time 11712034106 ps
CPU time 59.17 seconds
Started Apr 15 03:28:29 PM PDT 24
Finished Apr 15 03:29:29 PM PDT 24
Peak memory 663712 kb
Host smart-6989b120-25ab-4e1f-95a7-601be736a6ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326828399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_ta
rget_stretch.326828399
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.3310594665
Short name T517
Test name
Test status
Simulation time 2981739160 ps
CPU time 7.02 seconds
Started Apr 15 03:28:28 PM PDT 24
Finished Apr 15 03:28:36 PM PDT 24
Peak memory 212184 kb
Host smart-81a78205-d235-454a-b7a6-e79155bfe964
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310594665 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.3310594665
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.2808079798
Short name T1306
Test name
Test status
Simulation time 25417978 ps
CPU time 0.6 seconds
Started Apr 15 03:28:42 PM PDT 24
Finished Apr 15 03:28:43 PM PDT 24
Peak memory 203540 kb
Host smart-1088af3f-497c-45d8-a01d-7b6f3371a012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808079798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.2808079798
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.4014238443
Short name T675
Test name
Test status
Simulation time 254350880 ps
CPU time 1.65 seconds
Started Apr 15 03:28:37 PM PDT 24
Finished Apr 15 03:28:40 PM PDT 24
Peak memory 212228 kb
Host smart-cb646aec-de82-40aa-a9bf-6ab6383c8002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014238443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.4014238443
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.1154531496
Short name T385
Test name
Test status
Simulation time 254484938 ps
CPU time 12.08 seconds
Started Apr 15 03:28:32 PM PDT 24
Finished Apr 15 03:28:45 PM PDT 24
Peak memory 249720 kb
Host smart-db1d5654-daa3-43d5-b89d-00e86bccf15e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154531496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.1154531496
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.3406092313
Short name T303
Test name
Test status
Simulation time 9248778193 ps
CPU time 89.57 seconds
Started Apr 15 03:28:34 PM PDT 24
Finished Apr 15 03:30:04 PM PDT 24
Peak memory 756280 kb
Host smart-d3357905-696c-417f-9b62-84cf9c137a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406092313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.3406092313
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.3818550942
Short name T1061
Test name
Test status
Simulation time 2247944850 ps
CPU time 35.11 seconds
Started Apr 15 03:28:30 PM PDT 24
Finished Apr 15 03:29:06 PM PDT 24
Peak memory 477840 kb
Host smart-51f578cd-13a8-4845-812a-70377fcc08fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818550942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.3818550942
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.2266233901
Short name T1185
Test name
Test status
Simulation time 178515967 ps
CPU time 0.8 seconds
Started Apr 15 03:28:29 PM PDT 24
Finished Apr 15 03:28:31 PM PDT 24
Peak memory 203716 kb
Host smart-7e32ffb3-65b4-4f2a-8471-107b1e707f31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266233901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.2266233901
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.2164271243
Short name T1170
Test name
Test status
Simulation time 289378245 ps
CPU time 7.25 seconds
Started Apr 15 03:28:38 PM PDT 24
Finished Apr 15 03:28:46 PM PDT 24
Peak memory 203936 kb
Host smart-151fcbb2-c62e-4ce2-887b-3710d71603cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164271243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
2164271243
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.2737390735
Short name T843
Test name
Test status
Simulation time 3700330338 ps
CPU time 95.62 seconds
Started Apr 15 03:28:29 PM PDT 24
Finished Apr 15 03:30:06 PM PDT 24
Peak memory 1124620 kb
Host smart-3e7207b0-1018-412e-bd48-7ccbbcc4ba4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737390735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.2737390735
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.815984844
Short name T1052
Test name
Test status
Simulation time 1255753778 ps
CPU time 9.21 seconds
Started Apr 15 03:28:40 PM PDT 24
Finished Apr 15 03:28:50 PM PDT 24
Peak memory 203940 kb
Host smart-973e72af-6109-4a0c-adf3-b74068b588b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815984844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.815984844
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.4096971041
Short name T1049
Test name
Test status
Simulation time 5632556867 ps
CPU time 27.45 seconds
Started Apr 15 03:28:38 PM PDT 24
Finished Apr 15 03:29:07 PM PDT 24
Peak memory 358752 kb
Host smart-2b0f4571-9524-4af4-970e-9b2c6ad8b151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096971041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.4096971041
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.2949108816
Short name T213
Test name
Test status
Simulation time 30400362 ps
CPU time 0.71 seconds
Started Apr 15 03:28:29 PM PDT 24
Finished Apr 15 03:28:30 PM PDT 24
Peak memory 203652 kb
Host smart-ebedcd05-2999-409a-8352-29e5b540e467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949108816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2949108816
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.611622648
Short name T609
Test name
Test status
Simulation time 1085112451 ps
CPU time 10.61 seconds
Started Apr 15 03:28:38 PM PDT 24
Finished Apr 15 03:28:49 PM PDT 24
Peak memory 246876 kb
Host smart-efaa459f-0391-4933-9058-c704421a7095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611622648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.611622648
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.2412044520
Short name T917
Test name
Test status
Simulation time 1950368364 ps
CPU time 19.67 seconds
Started Apr 15 03:28:31 PM PDT 24
Finished Apr 15 03:28:51 PM PDT 24
Peak memory 275864 kb
Host smart-d28e44ba-a0c3-4249-8bc2-bf1c8e81f1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412044520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2412044520
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.2195170574
Short name T795
Test name
Test status
Simulation time 582685981 ps
CPU time 26.67 seconds
Started Apr 15 03:28:32 PM PDT 24
Finished Apr 15 03:29:00 PM PDT 24
Peak memory 212232 kb
Host smart-3f38ece7-c119-4bd0-8e77-9f85d43eccfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195170574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2195170574
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.119594024
Short name T121
Test name
Test status
Simulation time 117632891 ps
CPU time 0.96 seconds
Started Apr 15 03:28:41 PM PDT 24
Finished Apr 15 03:28:42 PM PDT 24
Peak memory 222188 kb
Host smart-b1e30ea3-b704-4970-822a-a19966973c93
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119594024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.119594024
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.314098264
Short name T628
Test name
Test status
Simulation time 1028069290 ps
CPU time 3.5 seconds
Started Apr 15 03:28:33 PM PDT 24
Finished Apr 15 03:28:38 PM PDT 24
Peak memory 204000 kb
Host smart-06ea7edc-5026-4c20-8086-efd19adb2c4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314098264 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.314098264
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.1950009819
Short name T729
Test name
Test status
Simulation time 10132810084 ps
CPU time 84.22 seconds
Started Apr 15 03:28:37 PM PDT 24
Finished Apr 15 03:30:02 PM PDT 24
Peak memory 573460 kb
Host smart-b46da5d1-33fc-48c2-9385-ebd0d20974c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950009819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.1950009819
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.2103674907
Short name T14
Test name
Test status
Simulation time 2786184654 ps
CPU time 2.43 seconds
Started Apr 15 03:28:32 PM PDT 24
Finished Apr 15 03:28:36 PM PDT 24
Peak memory 204020 kb
Host smart-ae7422c9-086c-43ee-9e97-76b2a424ba23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103674907 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.2103674907
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.131503239
Short name T1124
Test name
Test status
Simulation time 1798987437 ps
CPU time 4.69 seconds
Started Apr 15 03:28:33 PM PDT 24
Finished Apr 15 03:28:39 PM PDT 24
Peak memory 204000 kb
Host smart-658f19b7-e922-41b4-acac-d9fe1331504b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131503239 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_intr_smoke.131503239
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.2548092988
Short name T935
Test name
Test status
Simulation time 16463428416 ps
CPU time 26.01 seconds
Started Apr 15 03:28:35 PM PDT 24
Finished Apr 15 03:29:02 PM PDT 24
Peak memory 565084 kb
Host smart-7ca9b03a-a5f9-44f6-9dba-dd1004d04773
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548092988 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.2548092988
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1774896956
Short name T1145
Test name
Test status
Simulation time 1605047620 ps
CPU time 11.12 seconds
Started Apr 15 03:28:35 PM PDT 24
Finished Apr 15 03:28:46 PM PDT 24
Peak memory 203936 kb
Host smart-9fbdbec2-f872-460d-a89b-05393fc60c57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774896956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1774896956
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.3588101186
Short name T1263
Test name
Test status
Simulation time 13832257916 ps
CPU time 68.41 seconds
Started Apr 15 03:28:36 PM PDT 24
Finished Apr 15 03:29:45 PM PDT 24
Peak memory 209212 kb
Host smart-a61f0a5e-2bf3-45d4-a637-3bce02ed8f66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588101186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.3588101186
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.2208838439
Short name T1249
Test name
Test status
Simulation time 61212244874 ps
CPU time 1815.9 seconds
Started Apr 15 03:28:40 PM PDT 24
Finished Apr 15 03:58:57 PM PDT 24
Peak memory 9570580 kb
Host smart-443b1896-3933-492e-8e88-b6daf04ffd89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208838439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.2208838439
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.109612152
Short name T506
Test name
Test status
Simulation time 15940491994 ps
CPU time 270.09 seconds
Started Apr 15 03:29:12 PM PDT 24
Finished Apr 15 03:33:43 PM PDT 24
Peak memory 1729396 kb
Host smart-a7371cc2-b54e-49c2-a7ef-51d8b6121c7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109612152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_ta
rget_stretch.109612152
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.2538937585
Short name T676
Test name
Test status
Simulation time 1474701005 ps
CPU time 7.48 seconds
Started Apr 15 03:28:33 PM PDT 24
Finished Apr 15 03:28:42 PM PDT 24
Peak memory 218320 kb
Host smart-7d1b70f9-2755-42f1-9244-6c2e69a8d1ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538937585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.2538937585
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.1421369116
Short name T919
Test name
Test status
Simulation time 104609554 ps
CPU time 1.69 seconds
Started Apr 15 03:29:29 PM PDT 24
Finished Apr 15 03:29:32 PM PDT 24
Peak memory 212284 kb
Host smart-2fa3d05a-f35f-4fb3-a42b-ddb8bb2982b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421369116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.1421369116
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.1394545268
Short name T1265
Test name
Test status
Simulation time 522573010 ps
CPU time 5.88 seconds
Started Apr 15 03:29:26 PM PDT 24
Finished Apr 15 03:29:32 PM PDT 24
Peak memory 219968 kb
Host smart-637b45df-a5e7-4122-897e-dd518ba62d17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394545268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.1394545268
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.1677679754
Short name T1313
Test name
Test status
Simulation time 1287933833 ps
CPU time 35.56 seconds
Started Apr 15 03:29:25 PM PDT 24
Finished Apr 15 03:30:02 PM PDT 24
Peak memory 521040 kb
Host smart-281c8248-832d-49c6-a489-3fd722fc908e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677679754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.1677679754
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.518536348
Short name T1276
Test name
Test status
Simulation time 1335478739 ps
CPU time 37.56 seconds
Started Apr 15 03:29:25 PM PDT 24
Finished Apr 15 03:30:03 PM PDT 24
Peak memory 477052 kb
Host smart-52a37327-2c5d-4831-960a-49e95dfe443d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518536348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.518536348
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.2069720874
Short name T683
Test name
Test status
Simulation time 73815072 ps
CPU time 0.87 seconds
Started Apr 15 03:29:26 PM PDT 24
Finished Apr 15 03:29:28 PM PDT 24
Peak memory 203744 kb
Host smart-a2651104-141a-490d-aea2-631b7abf6dd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069720874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.2069720874
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.2657889004
Short name T759
Test name
Test status
Simulation time 440572474 ps
CPU time 3.04 seconds
Started Apr 15 03:29:26 PM PDT 24
Finished Apr 15 03:29:30 PM PDT 24
Peak memory 222756 kb
Host smart-1a77f67a-a8ae-4440-9f73-6dd6514a21f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657889004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.2657889004
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.2709731506
Short name T95
Test name
Test status
Simulation time 3248021773 ps
CPU time 91.93 seconds
Started Apr 15 03:29:26 PM PDT 24
Finished Apr 15 03:30:58 PM PDT 24
Peak memory 973276 kb
Host smart-922f6d23-8e64-40d2-bc79-ab2c8f6c541e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709731506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2709731506
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.4045331083
Short name T1187
Test name
Test status
Simulation time 1581365204 ps
CPU time 6.43 seconds
Started Apr 15 03:29:36 PM PDT 24
Finished Apr 15 03:29:43 PM PDT 24
Peak memory 203932 kb
Host smart-172c8222-62c3-408b-872f-3104571e3569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045331083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.4045331083
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.3041381707
Short name T1009
Test name
Test status
Simulation time 7639258492 ps
CPU time 49.1 seconds
Started Apr 15 03:29:31 PM PDT 24
Finished Apr 15 03:30:21 PM PDT 24
Peak memory 448680 kb
Host smart-46854702-7066-4d68-91aa-d6c93496cae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041381707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.3041381707
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.1585382049
Short name T552
Test name
Test status
Simulation time 74251012 ps
CPU time 0.66 seconds
Started Apr 15 03:29:28 PM PDT 24
Finished Apr 15 03:29:30 PM PDT 24
Peak memory 203672 kb
Host smart-30564201-7413-46ab-8da5-4ac7066e3e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585382049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.1585382049
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.624155183
Short name T802
Test name
Test status
Simulation time 27761417545 ps
CPU time 393.42 seconds
Started Apr 15 03:29:39 PM PDT 24
Finished Apr 15 03:36:13 PM PDT 24
Peak memory 232972 kb
Host smart-91d9d00b-6861-4426-9f90-3bc9aadf7443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624155183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.624155183
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.2912121394
Short name T925
Test name
Test status
Simulation time 5011704174 ps
CPU time 58.85 seconds
Started Apr 15 03:29:24 PM PDT 24
Finished Apr 15 03:30:24 PM PDT 24
Peak memory 294520 kb
Host smart-945aa22b-c0b9-44b3-b35a-c92886657e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912121394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.2912121394
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.1134115189
Short name T194
Test name
Test status
Simulation time 29844396602 ps
CPU time 296.74 seconds
Started Apr 15 03:29:35 PM PDT 24
Finished Apr 15 03:34:32 PM PDT 24
Peak memory 1593288 kb
Host smart-edfb8462-ca51-4832-abc8-ed34b9e38230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134115189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.1134115189
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.736976521
Short name T1067
Test name
Test status
Simulation time 805971730 ps
CPU time 11.91 seconds
Started Apr 15 03:29:29 PM PDT 24
Finished Apr 15 03:29:42 PM PDT 24
Peak memory 227820 kb
Host smart-5314ac80-0be0-4244-8401-d3f1a0310c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736976521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.736976521
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.2352293568
Short name T1311
Test name
Test status
Simulation time 927255371 ps
CPU time 4.15 seconds
Started Apr 15 03:29:31 PM PDT 24
Finished Apr 15 03:29:36 PM PDT 24
Peak memory 212228 kb
Host smart-b275683e-bc61-4973-8c81-7f6453f6a798
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352293568 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.2352293568
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.3757353889
Short name T100
Test name
Test status
Simulation time 10764876410 ps
CPU time 5.75 seconds
Started Apr 15 03:29:35 PM PDT 24
Finished Apr 15 03:29:42 PM PDT 24
Peak memory 223908 kb
Host smart-8bf4f0f9-8a11-4562-93b3-326bbee136c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757353889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.3757353889
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.373534083
Short name T345
Test name
Test status
Simulation time 10078774012 ps
CPU time 33.76 seconds
Started Apr 15 03:29:33 PM PDT 24
Finished Apr 15 03:30:08 PM PDT 24
Peak memory 372876 kb
Host smart-aedc7934-d6c7-4278-8573-0f9369c3635c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373534083 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_fifo_reset_tx.373534083
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.4177634444
Short name T711
Test name
Test status
Simulation time 680814960 ps
CPU time 2.6 seconds
Started Apr 15 03:29:31 PM PDT 24
Finished Apr 15 03:29:35 PM PDT 24
Peak memory 204016 kb
Host smart-7e9ffce3-1a51-4088-913a-61e36fca171a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177634444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.4177634444
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.3686219616
Short name T821
Test name
Test status
Simulation time 2431460079 ps
CPU time 3.22 seconds
Started Apr 15 03:29:31 PM PDT 24
Finished Apr 15 03:29:36 PM PDT 24
Peak memory 204100 kb
Host smart-bf53b7ef-2baf-4b7b-a9b7-2b976d1cf1b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686219616 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.3686219616
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.3049554613
Short name T425
Test name
Test status
Simulation time 20438870414 ps
CPU time 54.32 seconds
Started Apr 15 03:29:30 PM PDT 24
Finished Apr 15 03:30:25 PM PDT 24
Peak memory 891352 kb
Host smart-11d62106-e593-4813-9576-530ffff3a24b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049554613 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.3049554613
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.4080434669
Short name T1334
Test name
Test status
Simulation time 899646308 ps
CPU time 11.46 seconds
Started Apr 15 03:29:31 PM PDT 24
Finished Apr 15 03:29:44 PM PDT 24
Peak memory 203968 kb
Host smart-ed0e8fbf-fcc2-416e-8811-53c0c98acddd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080434669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.4080434669
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.2554679493
Short name T957
Test name
Test status
Simulation time 857736463 ps
CPU time 14.46 seconds
Started Apr 15 03:29:30 PM PDT 24
Finished Apr 15 03:29:46 PM PDT 24
Peak memory 216804 kb
Host smart-05932832-a158-412c-8861-d9e71c9e6810
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554679493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.2554679493
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.2875185328
Short name T1032
Test name
Test status
Simulation time 30408650781 ps
CPU time 84.36 seconds
Started Apr 15 03:29:35 PM PDT 24
Finished Apr 15 03:31:00 PM PDT 24
Peak memory 1305840 kb
Host smart-bcb1342a-57c1-4ef7-88d7-fbe864ce59fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875185328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.2875185328
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.1110168571
Short name T1107
Test name
Test status
Simulation time 15611654343 ps
CPU time 630.88 seconds
Started Apr 15 03:29:30 PM PDT 24
Finished Apr 15 03:40:02 PM PDT 24
Peak memory 3423004 kb
Host smart-6475617d-8680-4a39-b9a6-2382e4bd2765
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110168571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.1110168571
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.3324567042
Short name T1213
Test name
Test status
Simulation time 1416615035 ps
CPU time 6.73 seconds
Started Apr 15 03:29:28 PM PDT 24
Finished Apr 15 03:29:36 PM PDT 24
Peak memory 204028 kb
Host smart-a044b729-99a5-495f-8dd6-e20e7f3b9a36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324567042 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.3324567042
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.2329986456
Short name T732
Test name
Test status
Simulation time 54791944 ps
CPU time 0.62 seconds
Started Apr 15 03:29:40 PM PDT 24
Finished Apr 15 03:29:41 PM PDT 24
Peak memory 203548 kb
Host smart-42ab7aca-e632-42ac-8e69-8e74b1b5865d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329986456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.2329986456
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.3112033250
Short name T833
Test name
Test status
Simulation time 83506960 ps
CPU time 1.44 seconds
Started Apr 15 03:29:32 PM PDT 24
Finished Apr 15 03:29:34 PM PDT 24
Peak memory 212304 kb
Host smart-d046f287-aa94-4dbf-b34a-fb362a1db162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112033250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.3112033250
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.3906894634
Short name T217
Test name
Test status
Simulation time 1142555371 ps
CPU time 14.07 seconds
Started Apr 15 03:29:38 PM PDT 24
Finished Apr 15 03:29:53 PM PDT 24
Peak memory 257636 kb
Host smart-bc44d80a-9550-4ec7-b5ab-27d36c11cdbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906894634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.3906894634
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.4071474238
Short name T1273
Test name
Test status
Simulation time 17919328378 ps
CPU time 84.03 seconds
Started Apr 15 03:29:34 PM PDT 24
Finished Apr 15 03:30:58 PM PDT 24
Peak memory 724736 kb
Host smart-92c42ea5-95bb-4f87-b511-34e3c76ac57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071474238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.4071474238
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.1035763314
Short name T346
Test name
Test status
Simulation time 8104333443 ps
CPU time 141.85 seconds
Started Apr 15 03:29:32 PM PDT 24
Finished Apr 15 03:31:55 PM PDT 24
Peak memory 595908 kb
Host smart-c77b6c24-2acf-47a3-b7d2-c870d3c6952b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035763314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.1035763314
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.1682254368
Short name T820
Test name
Test status
Simulation time 359113397 ps
CPU time 9.96 seconds
Started Apr 15 03:29:33 PM PDT 24
Finished Apr 15 03:29:44 PM PDT 24
Peak memory 203964 kb
Host smart-b5775466-c6e9-46c6-ab48-ed063e126c6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682254368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.1682254368
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.3978288198
Short name T558
Test name
Test status
Simulation time 4208017003 ps
CPU time 133.2 seconds
Started Apr 15 03:29:39 PM PDT 24
Finished Apr 15 03:31:53 PM PDT 24
Peak memory 1251268 kb
Host smart-0db6422d-3cc1-4b18-bd69-10acf74d44a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978288198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.3978288198
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.349715529
Short name T871
Test name
Test status
Simulation time 648012570 ps
CPU time 2.97 seconds
Started Apr 15 03:29:37 PM PDT 24
Finished Apr 15 03:29:41 PM PDT 24
Peak memory 203904 kb
Host smart-1325c7d3-d59c-40c7-9cc2-491fc4a34984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349715529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.349715529
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.243892331
Short name T1173
Test name
Test status
Simulation time 1440796278 ps
CPU time 28.79 seconds
Started Apr 15 03:29:39 PM PDT 24
Finished Apr 15 03:30:08 PM PDT 24
Peak memory 325932 kb
Host smart-9f45677b-d78f-490e-94ef-d051fc653c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243892331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.243892331
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.2384045746
Short name T551
Test name
Test status
Simulation time 42824331 ps
CPU time 0.67 seconds
Started Apr 15 03:29:34 PM PDT 24
Finished Apr 15 03:29:36 PM PDT 24
Peak memory 203692 kb
Host smart-2542604d-2ac0-4310-9606-ae78a8ac9029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384045746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.2384045746
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.2656669453
Short name T219
Test name
Test status
Simulation time 27274469411 ps
CPU time 359.84 seconds
Started Apr 15 03:29:36 PM PDT 24
Finished Apr 15 03:35:36 PM PDT 24
Peak memory 226744 kb
Host smart-89f5a297-2c57-4c59-a3cc-1b16e6d1ff04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656669453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.2656669453
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.3943343834
Short name T653
Test name
Test status
Simulation time 3435242315 ps
CPU time 37.72 seconds
Started Apr 15 03:29:34 PM PDT 24
Finished Apr 15 03:30:13 PM PDT 24
Peak memory 367392 kb
Host smart-dfb82587-ed2c-4bb6-bde0-f2ae72f7efa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943343834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.3943343834
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.1683748051
Short name T421
Test name
Test status
Simulation time 750357791 ps
CPU time 11.91 seconds
Started Apr 15 03:29:33 PM PDT 24
Finished Apr 15 03:29:46 PM PDT 24
Peak memory 220264 kb
Host smart-e79ac704-579a-4471-bf1c-0614ef8c23cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683748051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.1683748051
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.2417125524
Short name T652
Test name
Test status
Simulation time 607843967 ps
CPU time 3.37 seconds
Started Apr 15 03:29:39 PM PDT 24
Finished Apr 15 03:29:43 PM PDT 24
Peak memory 204028 kb
Host smart-bd7761a5-8a5c-4af6-bc03-490ea79dee14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417125524 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.2417125524
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.2740103668
Short name T704
Test name
Test status
Simulation time 10079325975 ps
CPU time 71.95 seconds
Started Apr 15 03:29:38 PM PDT 24
Finished Apr 15 03:30:51 PM PDT 24
Peak memory 485948 kb
Host smart-cd1fd4f9-bbbc-41ba-ae91-9e8f72f0ab86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740103668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.2740103668
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.2387437209
Short name T1190
Test name
Test status
Simulation time 10148969415 ps
CPU time 13.15 seconds
Started Apr 15 03:29:57 PM PDT 24
Finished Apr 15 03:30:11 PM PDT 24
Peak memory 273420 kb
Host smart-427a6495-be70-45a2-8358-58850d9ec452
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387437209 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.2387437209
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.1904803801
Short name T451
Test name
Test status
Simulation time 343544009 ps
CPU time 2.16 seconds
Started Apr 15 03:29:41 PM PDT 24
Finished Apr 15 03:29:43 PM PDT 24
Peak memory 203964 kb
Host smart-fc6cffaf-6015-4923-935c-b025f6c79be5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904803801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.1904803801
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.1925860443
Short name T405
Test name
Test status
Simulation time 1155207070 ps
CPU time 5.73 seconds
Started Apr 15 03:29:32 PM PDT 24
Finished Apr 15 03:29:38 PM PDT 24
Peak memory 203996 kb
Host smart-a35567ea-e7d6-46c6-97fa-d766cf1f0a34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925860443 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.1925860443
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.3578298362
Short name T670
Test name
Test status
Simulation time 14074465269 ps
CPU time 141.36 seconds
Started Apr 15 03:29:37 PM PDT 24
Finished Apr 15 03:31:59 PM PDT 24
Peak memory 1879956 kb
Host smart-0eef84ea-8bcd-4f40-885d-d52e36feb490
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578298362 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.3578298362
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.3300041637
Short name T474
Test name
Test status
Simulation time 3260014952 ps
CPU time 12.96 seconds
Started Apr 15 03:29:35 PM PDT 24
Finished Apr 15 03:29:49 PM PDT 24
Peak memory 204028 kb
Host smart-6b849fc5-79e3-4570-9dba-d78ff7d197c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300041637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.3300041637
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.1525011751
Short name T898
Test name
Test status
Simulation time 14456071491 ps
CPU time 68.97 seconds
Started Apr 15 03:29:32 PM PDT 24
Finished Apr 15 03:30:41 PM PDT 24
Peak memory 209516 kb
Host smart-70035f70-18d8-4d0f-9704-ca0d79ff0d46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525011751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.1525011751
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.1865616385
Short name T311
Test name
Test status
Simulation time 35585450901 ps
CPU time 58.85 seconds
Started Apr 15 03:29:33 PM PDT 24
Finished Apr 15 03:30:33 PM PDT 24
Peak memory 1039244 kb
Host smart-56833967-6803-4cd0-8154-0e2980eff5bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865616385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.1865616385
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.910433271
Short name T1012
Test name
Test status
Simulation time 5839034053 ps
CPU time 126.38 seconds
Started Apr 15 03:29:34 PM PDT 24
Finished Apr 15 03:31:42 PM PDT 24
Peak memory 1476940 kb
Host smart-7f984cbe-af7c-45a0-bf5e-ef58f5952981
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910433271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_t
arget_stretch.910433271
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.1158810217
Short name T972
Test name
Test status
Simulation time 3826990026 ps
CPU time 5.68 seconds
Started Apr 15 03:29:36 PM PDT 24
Finished Apr 15 03:29:43 PM PDT 24
Peak memory 204104 kb
Host smart-3c2ba284-2a38-43d1-aec7-1e21fd3b3432
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158810217 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.1158810217
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.305748365
Short name T614
Test name
Test status
Simulation time 111498420 ps
CPU time 0.6 seconds
Started Apr 15 03:29:48 PM PDT 24
Finished Apr 15 03:29:49 PM PDT 24
Peak memory 203580 kb
Host smart-b83040f3-f59c-44c5-a23e-84ca7abf522c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305748365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.305748365
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.2865254974
Short name T293
Test name
Test status
Simulation time 90480803 ps
CPU time 1.45 seconds
Started Apr 15 03:29:44 PM PDT 24
Finished Apr 15 03:29:46 PM PDT 24
Peak memory 212276 kb
Host smart-ab76a823-7cab-45d8-a8ba-3d82111da670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865254974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.2865254974
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.1035628344
Short name T819
Test name
Test status
Simulation time 530970915 ps
CPU time 4.55 seconds
Started Apr 15 03:29:43 PM PDT 24
Finished Apr 15 03:29:48 PM PDT 24
Peak memory 231148 kb
Host smart-21fed718-282d-47ee-b1e6-1b11f67aaba4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035628344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.1035628344
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.796437096
Short name T1192
Test name
Test status
Simulation time 2949306187 ps
CPU time 49.64 seconds
Started Apr 15 03:29:40 PM PDT 24
Finished Apr 15 03:30:31 PM PDT 24
Peak memory 571352 kb
Host smart-0b2708f3-1f67-40b1-acca-af788f7f4187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796437096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.796437096
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.3735520393
Short name T1138
Test name
Test status
Simulation time 118381841 ps
CPU time 0.98 seconds
Started Apr 15 03:29:42 PM PDT 24
Finished Apr 15 03:29:44 PM PDT 24
Peak memory 203716 kb
Host smart-787174e9-1c9a-405b-885b-def4a23d0346
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735520393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.3735520393
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.3832095990
Short name T224
Test name
Test status
Simulation time 240480713 ps
CPU time 2.99 seconds
Started Apr 15 03:29:41 PM PDT 24
Finished Apr 15 03:29:45 PM PDT 24
Peak memory 203980 kb
Host smart-a137b71e-2292-435b-b669-d3b493eaec37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832095990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.3832095990
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.1054826005
Short name T507
Test name
Test status
Simulation time 14501840427 ps
CPU time 108.6 seconds
Started Apr 15 03:29:42 PM PDT 24
Finished Apr 15 03:31:32 PM PDT 24
Peak memory 1071296 kb
Host smart-beab8a34-431b-4a9c-9ff3-bea900af67c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054826005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1054826005
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.2717512867
Short name T630
Test name
Test status
Simulation time 2813871055 ps
CPU time 10.99 seconds
Started Apr 15 03:29:47 PM PDT 24
Finished Apr 15 03:29:59 PM PDT 24
Peak memory 203992 kb
Host smart-20cedf3a-ecda-40aa-9c0d-3fbfec882f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717512867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.2717512867
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.4178836212
Short name T38
Test name
Test status
Simulation time 1170506604 ps
CPU time 20.05 seconds
Started Apr 15 03:29:45 PM PDT 24
Finished Apr 15 03:30:06 PM PDT 24
Peak memory 263956 kb
Host smart-ed6ce27d-ed68-46db-be83-f0406842e9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178836212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.4178836212
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.986599187
Short name T209
Test name
Test status
Simulation time 31368268 ps
CPU time 0.66 seconds
Started Apr 15 03:29:40 PM PDT 24
Finished Apr 15 03:29:41 PM PDT 24
Peak memory 203648 kb
Host smart-72491655-b22d-46a5-88d0-64272881b7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986599187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.986599187
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.817043383
Short name T469
Test name
Test status
Simulation time 49124285543 ps
CPU time 92.92 seconds
Started Apr 15 03:29:42 PM PDT 24
Finished Apr 15 03:31:16 PM PDT 24
Peak memory 219596 kb
Host smart-be36d686-31fc-4443-b370-46c555e1f18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817043383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.817043383
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.4184180945
Short name T336
Test name
Test status
Simulation time 25545744862 ps
CPU time 29.71 seconds
Started Apr 15 03:29:43 PM PDT 24
Finished Apr 15 03:30:14 PM PDT 24
Peak memory 378640 kb
Host smart-d27ec68b-88f9-4c05-a7a5-b0b33a2bcdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184180945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.4184180945
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.2118998438
Short name T185
Test name
Test status
Simulation time 48646239827 ps
CPU time 375.72 seconds
Started Apr 15 03:29:44 PM PDT 24
Finished Apr 15 03:36:00 PM PDT 24
Peak memory 1266572 kb
Host smart-8f7925b8-8a9d-4ab5-b3b7-8a0a18b2376d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118998438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.2118998438
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.145083978
Short name T1174
Test name
Test status
Simulation time 2269053592 ps
CPU time 9.37 seconds
Started Apr 15 03:29:44 PM PDT 24
Finished Apr 15 03:29:54 PM PDT 24
Peak memory 220388 kb
Host smart-00294395-424a-4db8-8ec1-4898baea2b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145083978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.145083978
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.124277322
Short name T995
Test name
Test status
Simulation time 1914480567 ps
CPU time 4.11 seconds
Started Apr 15 03:29:45 PM PDT 24
Finished Apr 15 03:29:50 PM PDT 24
Peak memory 212172 kb
Host smart-5b39bd36-bc0c-4567-b204-64f3fbefe7d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124277322 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.124277322
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.509260594
Short name T723
Test name
Test status
Simulation time 10157784490 ps
CPU time 10.73 seconds
Started Apr 15 03:29:46 PM PDT 24
Finished Apr 15 03:29:58 PM PDT 24
Peak memory 270628 kb
Host smart-a189d4ad-18a4-44c7-b8db-2a51e2ff158a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509260594 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.509260594
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.1523847822
Short name T1347
Test name
Test status
Simulation time 552938145 ps
CPU time 2.93 seconds
Started Apr 15 03:29:44 PM PDT 24
Finished Apr 15 03:29:48 PM PDT 24
Peak memory 203984 kb
Host smart-02854980-9af4-4a57-8391-896c43aa8571
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523847822 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.1523847822
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.3486848477
Short name T268
Test name
Test status
Simulation time 5079223041 ps
CPU time 5.15 seconds
Started Apr 15 03:29:42 PM PDT 24
Finished Apr 15 03:29:48 PM PDT 24
Peak memory 212224 kb
Host smart-49da30f2-d58c-4458-acd9-f14d7ae111d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486848477 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.3486848477
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.2355885651
Short name T1214
Test name
Test status
Simulation time 10192283200 ps
CPU time 5.93 seconds
Started Apr 15 03:29:42 PM PDT 24
Finished Apr 15 03:29:48 PM PDT 24
Peak memory 204044 kb
Host smart-9b34580c-0aa6-43c9-85ce-c670a47458c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355885651 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.2355885651
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.1190489968
Short name T1086
Test name
Test status
Simulation time 5167327383 ps
CPU time 54.05 seconds
Started Apr 15 03:29:41 PM PDT 24
Finished Apr 15 03:30:36 PM PDT 24
Peak memory 204056 kb
Host smart-657ea86f-dde6-4b44-a232-b32128982144
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190489968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.1190489968
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.1022672367
Short name T799
Test name
Test status
Simulation time 515807351 ps
CPU time 11.06 seconds
Started Apr 15 03:29:44 PM PDT 24
Finished Apr 15 03:29:55 PM PDT 24
Peak memory 203992 kb
Host smart-fa484238-79f7-4b40-82dd-3f3242758864
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022672367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.1022672367
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.1600795281
Short name T320
Test name
Test status
Simulation time 31722649489 ps
CPU time 299.82 seconds
Started Apr 15 03:29:44 PM PDT 24
Finished Apr 15 03:34:45 PM PDT 24
Peak memory 2943688 kb
Host smart-a90bff60-7a0f-4245-98dd-1f1679f77427
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600795281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.1600795281
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.1343324148
Short name T693
Test name
Test status
Simulation time 25747375347 ps
CPU time 1350.09 seconds
Started Apr 15 03:29:42 PM PDT 24
Finished Apr 15 03:52:14 PM PDT 24
Peak memory 5045140 kb
Host smart-639b7f2b-d18c-4907-a02c-c8b9bd701643
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343324148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.1343324148
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.2757384849
Short name T1288
Test name
Test status
Simulation time 1404919873 ps
CPU time 6.86 seconds
Started Apr 15 03:29:46 PM PDT 24
Finished Apr 15 03:29:54 PM PDT 24
Peak memory 213928 kb
Host smart-089af0ec-664e-429d-9c1e-661d64399cb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757384849 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.2757384849
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2054916880
Short name T1272
Test name
Test status
Simulation time 43033365 ps
CPU time 0.62 seconds
Started Apr 15 03:29:58 PM PDT 24
Finished Apr 15 03:29:59 PM PDT 24
Peak memory 203532 kb
Host smart-1dd2a302-50f3-4c58-8f00-408a76c1835e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054916880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2054916880
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.386294641
Short name T792
Test name
Test status
Simulation time 316930419 ps
CPU time 1.4 seconds
Started Apr 15 03:29:49 PM PDT 24
Finished Apr 15 03:29:51 PM PDT 24
Peak memory 212344 kb
Host smart-d2a13bfb-6fe1-474b-b495-705589f27b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386294641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.386294641
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.1189086093
Short name T1092
Test name
Test status
Simulation time 607985503 ps
CPU time 14.81 seconds
Started Apr 15 03:29:46 PM PDT 24
Finished Apr 15 03:30:02 PM PDT 24
Peak memory 250520 kb
Host smart-d5d626d5-3ab1-4b75-92fb-2a65d8ee5916
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189086093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.1189086093
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.3968061108
Short name T918
Test name
Test status
Simulation time 2291336047 ps
CPU time 163.42 seconds
Started Apr 15 03:29:45 PM PDT 24
Finished Apr 15 03:32:30 PM PDT 24
Peak memory 714268 kb
Host smart-4c695f06-f078-433a-8a11-0b1afc296de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968061108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.3968061108
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.1354162889
Short name T575
Test name
Test status
Simulation time 2434994102 ps
CPU time 71.52 seconds
Started Apr 15 03:29:47 PM PDT 24
Finished Apr 15 03:30:59 PM PDT 24
Peak memory 718940 kb
Host smart-cc8dd984-0773-4676-a8e8-93ea1a6a40fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354162889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.1354162889
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2393247826
Short name T784
Test name
Test status
Simulation time 146108510 ps
CPU time 0.93 seconds
Started Apr 15 03:29:45 PM PDT 24
Finished Apr 15 03:29:47 PM PDT 24
Peak memory 203736 kb
Host smart-0af19474-6f36-4609-b17b-16f23ca3069f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393247826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2393247826
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.2823072768
Short name T1258
Test name
Test status
Simulation time 268860924 ps
CPU time 3.31 seconds
Started Apr 15 03:29:47 PM PDT 24
Finished Apr 15 03:29:51 PM PDT 24
Peak memory 203904 kb
Host smart-30d94369-024e-480f-a786-39514911840d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823072768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.2823072768
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.1931108923
Short name T181
Test name
Test status
Simulation time 3756998556 ps
CPU time 91.25 seconds
Started Apr 15 03:29:47 PM PDT 24
Finished Apr 15 03:31:19 PM PDT 24
Peak memory 1138860 kb
Host smart-6fb286d8-de86-4f37-8f2f-da74b8a9a030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931108923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.1931108923
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.3282863036
Short name T848
Test name
Test status
Simulation time 635652386 ps
CPU time 13.24 seconds
Started Apr 15 03:29:55 PM PDT 24
Finished Apr 15 03:30:08 PM PDT 24
Peak memory 203920 kb
Host smart-c22fad31-411e-4f6a-893f-6982112f9efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282863036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.3282863036
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.1444605003
Short name T366
Test name
Test status
Simulation time 4651029468 ps
CPU time 56.86 seconds
Started Apr 15 03:29:55 PM PDT 24
Finished Apr 15 03:30:52 PM PDT 24
Peak memory 266156 kb
Host smart-d200aae0-1eb8-4a66-a2b2-e933e5bb6313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444605003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.1444605003
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.2106341443
Short name T1237
Test name
Test status
Simulation time 21416383 ps
CPU time 0.63 seconds
Started Apr 15 03:29:46 PM PDT 24
Finished Apr 15 03:29:47 PM PDT 24
Peak memory 203672 kb
Host smart-983360d8-3b2f-4f5a-b088-c743176e8bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106341443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.2106341443
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.2456423634
Short name T904
Test name
Test status
Simulation time 1333830188 ps
CPU time 2.89 seconds
Started Apr 15 03:29:50 PM PDT 24
Finished Apr 15 03:29:53 PM PDT 24
Peak memory 218532 kb
Host smart-74a6d570-e095-42a7-add0-244b3065bf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456423634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.2456423634
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.994878293
Short name T439
Test name
Test status
Simulation time 5938387102 ps
CPU time 29.67 seconds
Started Apr 15 03:29:45 PM PDT 24
Finished Apr 15 03:30:15 PM PDT 24
Peak memory 315732 kb
Host smart-655500a3-b2c2-4ce0-b5df-16a267428768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994878293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.994878293
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.1320523495
Short name T631
Test name
Test status
Simulation time 769502866 ps
CPU time 12.94 seconds
Started Apr 15 03:29:49 PM PDT 24
Finished Apr 15 03:30:02 PM PDT 24
Peak memory 220364 kb
Host smart-293c59bb-4c8d-4b9a-9399-b34701391d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320523495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.1320523495
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.1677956880
Short name T705
Test name
Test status
Simulation time 1902216107 ps
CPU time 2.52 seconds
Started Apr 15 03:29:53 PM PDT 24
Finished Apr 15 03:29:57 PM PDT 24
Peak memory 204052 kb
Host smart-e00e009c-36ca-4d2d-8281-e403d4105c80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677956880 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.1677956880
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.3402761597
Short name T633
Test name
Test status
Simulation time 10084375015 ps
CPU time 77.98 seconds
Started Apr 15 03:29:54 PM PDT 24
Finished Apr 15 03:31:13 PM PDT 24
Peak memory 507872 kb
Host smart-9959d7bd-768c-4aa4-82ba-38a259329954
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402761597 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.3402761597
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.3102231159
Short name T1120
Test name
Test status
Simulation time 10079816346 ps
CPU time 29.97 seconds
Started Apr 15 03:29:54 PM PDT 24
Finished Apr 15 03:30:24 PM PDT 24
Peak memory 398268 kb
Host smart-e83b5605-637e-4407-86f0-961181ac19fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102231159 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.3102231159
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.387343332
Short name T1143
Test name
Test status
Simulation time 973420785 ps
CPU time 5.1 seconds
Started Apr 15 03:29:54 PM PDT 24
Finished Apr 15 03:29:59 PM PDT 24
Peak memory 208028 kb
Host smart-bee94f39-a59d-4715-a221-6cfc9ca0e7c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387343332 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_intr_smoke.387343332
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.1007447392
Short name T380
Test name
Test status
Simulation time 12360536936 ps
CPU time 11.18 seconds
Started Apr 15 03:29:55 PM PDT 24
Finished Apr 15 03:30:06 PM PDT 24
Peak memory 329892 kb
Host smart-48bf43b5-9fc2-4c94-b91e-62931af5b9ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007447392 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.1007447392
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.2420502930
Short name T31
Test name
Test status
Simulation time 2056580186 ps
CPU time 40.32 seconds
Started Apr 15 03:29:49 PM PDT 24
Finished Apr 15 03:30:30 PM PDT 24
Peak memory 204016 kb
Host smart-75050602-4c1c-45a2-9abf-08e45dbb39cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420502930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.2420502930
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.1723761293
Short name T1117
Test name
Test status
Simulation time 1323073778 ps
CPU time 56.86 seconds
Started Apr 15 03:29:51 PM PDT 24
Finished Apr 15 03:30:48 PM PDT 24
Peak memory 204876 kb
Host smart-f8970e73-ae9c-4adf-b905-a02aeeef54f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723761293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.1723761293
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.1617861695
Short name T306
Test name
Test status
Simulation time 34516349709 ps
CPU time 343.84 seconds
Started Apr 15 03:29:52 PM PDT 24
Finished Apr 15 03:35:36 PM PDT 24
Peak memory 3549220 kb
Host smart-24c8b4ed-3806-4ba4-842d-46565377d765
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617861695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.1617861695
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.1713953384
Short name T415
Test name
Test status
Simulation time 13814445197 ps
CPU time 271.7 seconds
Started Apr 15 03:29:54 PM PDT 24
Finished Apr 15 03:34:27 PM PDT 24
Peak memory 1798412 kb
Host smart-e94d528b-f952-498c-9500-c6e1b395f4b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713953384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.1713953384
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.2640697456
Short name T13
Test name
Test status
Simulation time 4322764910 ps
CPU time 5.87 seconds
Started Apr 15 03:29:55 PM PDT 24
Finished Apr 15 03:30:01 PM PDT 24
Peak memory 220280 kb
Host smart-4b22272a-da62-48fa-b20a-5d58108eddff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640697456 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.2640697456
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.2822012638
Short name T32
Test name
Test status
Simulation time 64083962 ps
CPU time 0.62 seconds
Started Apr 15 03:30:04 PM PDT 24
Finished Apr 15 03:30:05 PM PDT 24
Peak memory 203580 kb
Host smart-a0c6e372-f855-4886-aed9-e3f21afeb4a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822012638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.2822012638
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.2435545413
Short name T863
Test name
Test status
Simulation time 128594562 ps
CPU time 1.34 seconds
Started Apr 15 03:29:57 PM PDT 24
Finished Apr 15 03:29:59 PM PDT 24
Peak memory 204048 kb
Host smart-77f3fb47-4d4d-46df-b50c-f97414195e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435545413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.2435545413
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1149471622
Short name T1319
Test name
Test status
Simulation time 759371440 ps
CPU time 7.31 seconds
Started Apr 15 03:29:59 PM PDT 24
Finished Apr 15 03:30:06 PM PDT 24
Peak memory 271156 kb
Host smart-671d0dcb-b676-4326-b96e-91ab2bb5849f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149471622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.1149471622
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.2518254261
Short name T1073
Test name
Test status
Simulation time 9816575073 ps
CPU time 143.6 seconds
Started Apr 15 03:29:57 PM PDT 24
Finished Apr 15 03:32:21 PM PDT 24
Peak memory 544220 kb
Host smart-01620d8d-3a76-4752-bc5c-dc7a4c48a5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518254261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.2518254261
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.898787374
Short name T1157
Test name
Test status
Simulation time 2118176056 ps
CPU time 57.51 seconds
Started Apr 15 03:29:57 PM PDT 24
Finished Apr 15 03:30:55 PM PDT 24
Peak memory 645324 kb
Host smart-6fab9b39-8ca1-46d8-bbd2-7dfb183384ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898787374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.898787374
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2438783329
Short name T608
Test name
Test status
Simulation time 110217808 ps
CPU time 1.09 seconds
Started Apr 15 03:29:56 PM PDT 24
Finished Apr 15 03:29:58 PM PDT 24
Peak memory 203956 kb
Host smart-074bf16a-fceb-4937-bcc9-8cef1dddf3f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438783329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2438783329
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.3169006152
Short name T571
Test name
Test status
Simulation time 8699442499 ps
CPU time 140.39 seconds
Started Apr 15 03:29:57 PM PDT 24
Finished Apr 15 03:32:18 PM PDT 24
Peak memory 1265996 kb
Host smart-0154a0c7-adce-4d89-a2f1-92023abb6fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169006152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.3169006152
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.4210658838
Short name T1102
Test name
Test status
Simulation time 1227479028 ps
CPU time 7.97 seconds
Started Apr 15 03:30:17 PM PDT 24
Finished Apr 15 03:30:25 PM PDT 24
Peak memory 204016 kb
Host smart-c74959f2-e923-46a5-badd-33625d576a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210658838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.4210658838
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.2107770757
Short name T361
Test name
Test status
Simulation time 1599135303 ps
CPU time 27.84 seconds
Started Apr 15 03:30:05 PM PDT 24
Finished Apr 15 03:30:34 PM PDT 24
Peak memory 300268 kb
Host smart-aba2ffe3-a4bf-4318-966c-67aeab3c3fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107770757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.2107770757
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.3559860468
Short name T409
Test name
Test status
Simulation time 25614258 ps
CPU time 0.62 seconds
Started Apr 15 03:29:57 PM PDT 24
Finished Apr 15 03:29:59 PM PDT 24
Peak memory 203680 kb
Host smart-170e9555-67fe-4eff-8d55-b3793c323a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559860468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3559860468
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.2074927645
Short name T862
Test name
Test status
Simulation time 12434093003 ps
CPU time 1338.97 seconds
Started Apr 15 03:29:56 PM PDT 24
Finished Apr 15 03:52:16 PM PDT 24
Peak memory 1590608 kb
Host smart-5fbdb9ee-2d50-4f41-b9ef-3d00824aca4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074927645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.2074927645
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.3593116020
Short name T651
Test name
Test status
Simulation time 1385145116 ps
CPU time 71.58 seconds
Started Apr 15 03:29:57 PM PDT 24
Finished Apr 15 03:31:09 PM PDT 24
Peak memory 404644 kb
Host smart-b2438623-637b-44cf-a6ff-0ea218d713f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593116020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3593116020
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.1920284559
Short name T273
Test name
Test status
Simulation time 1151990029 ps
CPU time 26.04 seconds
Started Apr 15 03:29:55 PM PDT 24
Finished Apr 15 03:30:22 PM PDT 24
Peak memory 212168 kb
Host smart-bccd02b7-107b-4dc9-9b93-55057cbf8f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920284559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.1920284559
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.3133383638
Short name T508
Test name
Test status
Simulation time 1891854603 ps
CPU time 4.63 seconds
Started Apr 15 03:30:04 PM PDT 24
Finished Apr 15 03:30:09 PM PDT 24
Peak memory 212184 kb
Host smart-f78efbbc-d877-4018-896e-06a82cd461f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133383638 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.3133383638
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.1349288409
Short name T446
Test name
Test status
Simulation time 10169953344 ps
CPU time 29.89 seconds
Started Apr 15 03:30:04 PM PDT 24
Finished Apr 15 03:30:34 PM PDT 24
Peak memory 325476 kb
Host smart-ec8a4ebe-a054-4e68-8b39-7cc70c35e9ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349288409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.1349288409
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.4051413926
Short name T847
Test name
Test status
Simulation time 10514870617 ps
CPU time 13.52 seconds
Started Apr 15 03:30:02 PM PDT 24
Finished Apr 15 03:30:16 PM PDT 24
Peak memory 294748 kb
Host smart-ebe88be0-dcfc-4de4-9981-432741a46a09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051413926 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.4051413926
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.2192561117
Short name T707
Test name
Test status
Simulation time 310216666 ps
CPU time 2.16 seconds
Started Apr 15 03:30:01 PM PDT 24
Finished Apr 15 03:30:04 PM PDT 24
Peak memory 204004 kb
Host smart-fdf66ad6-1349-4d3e-a371-7512eea2b2cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192561117 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.2192561117
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.2112914786
Short name T726
Test name
Test status
Simulation time 2554621206 ps
CPU time 3.78 seconds
Started Apr 15 03:29:59 PM PDT 24
Finished Apr 15 03:30:04 PM PDT 24
Peak memory 204036 kb
Host smart-0ec78e51-4d32-46fc-bb3b-2db25e180b82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112914786 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.2112914786
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.1081203865
Short name T1177
Test name
Test status
Simulation time 21469221890 ps
CPU time 41.41 seconds
Started Apr 15 03:29:59 PM PDT 24
Finished Apr 15 03:30:41 PM PDT 24
Peak memory 726452 kb
Host smart-95c1337c-7189-4e9a-95f0-84d09d914fa3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081203865 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.1081203865
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.526427994
Short name T679
Test name
Test status
Simulation time 799118194 ps
CPU time 26.93 seconds
Started Apr 15 03:29:59 PM PDT 24
Finished Apr 15 03:30:27 PM PDT 24
Peak memory 203968 kb
Host smart-0397b343-3f0f-4f84-8556-08f1ea2f5cef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526427994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_tar
get_smoke.526427994
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.3531651858
Short name T540
Test name
Test status
Simulation time 3216836381 ps
CPU time 13.49 seconds
Started Apr 15 03:29:59 PM PDT 24
Finished Apr 15 03:30:13 PM PDT 24
Peak memory 216532 kb
Host smart-289a7018-16c1-4414-a037-ae436948677f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531651858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.3531651858
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.2598023476
Short name T272
Test name
Test status
Simulation time 58412174559 ps
CPU time 1908.54 seconds
Started Apr 15 03:30:03 PM PDT 24
Finished Apr 15 04:01:52 PM PDT 24
Peak memory 9542668 kb
Host smart-4eb57cc8-2f61-4121-9346-1fb47b6d5028
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598023476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.2598023476
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.3799505996
Short name T462
Test name
Test status
Simulation time 31572487114 ps
CPU time 2089.84 seconds
Started Apr 15 03:29:58 PM PDT 24
Finished Apr 15 04:04:49 PM PDT 24
Peak memory 3651832 kb
Host smart-1f5e324c-10bd-4627-887e-b1b5ea933c11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799505996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.3799505996
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.624974939
Short name T1127
Test name
Test status
Simulation time 2431905213 ps
CPU time 6.43 seconds
Started Apr 15 03:30:01 PM PDT 24
Finished Apr 15 03:30:08 PM PDT 24
Peak memory 220272 kb
Host smart-e9f8e1a6-5a4b-4009-895d-5ba3e40a915d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624974939 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_timeout.624974939
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.3963053692
Short name T1125
Test name
Test status
Simulation time 42328826 ps
CPU time 0.62 seconds
Started Apr 15 03:30:17 PM PDT 24
Finished Apr 15 03:30:19 PM PDT 24
Peak memory 203532 kb
Host smart-cee12c81-5560-496b-9e9e-62a862c66f77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963053692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.3963053692
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.2059955130
Short name T1112
Test name
Test status
Simulation time 149630427 ps
CPU time 1.4 seconds
Started Apr 15 03:30:07 PM PDT 24
Finished Apr 15 03:30:09 PM PDT 24
Peak memory 212300 kb
Host smart-9746e404-1c66-4cc9-bfc0-f6a93649c9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059955130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.2059955130
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.788088311
Short name T931
Test name
Test status
Simulation time 615499499 ps
CPU time 8.77 seconds
Started Apr 15 03:30:05 PM PDT 24
Finished Apr 15 03:30:15 PM PDT 24
Peak memory 234132 kb
Host smart-db624300-c1cc-44f5-8dc8-f71670dd8dbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788088311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empt
y.788088311
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.3453996169
Short name T677
Test name
Test status
Simulation time 14978646516 ps
CPU time 113.21 seconds
Started Apr 15 03:30:07 PM PDT 24
Finished Apr 15 03:32:01 PM PDT 24
Peak memory 518324 kb
Host smart-4fb2c3e0-0b76-4187-b58c-9babf90d6ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453996169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.3453996169
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.3485986762
Short name T545
Test name
Test status
Simulation time 5388399424 ps
CPU time 86.11 seconds
Started Apr 15 03:30:06 PM PDT 24
Finished Apr 15 03:31:33 PM PDT 24
Peak memory 513580 kb
Host smart-1980298c-0926-4c48-b768-29ed6b87ce49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485986762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.3485986762
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.907142135
Short name T351
Test name
Test status
Simulation time 119981667 ps
CPU time 1.09 seconds
Started Apr 15 03:30:07 PM PDT 24
Finished Apr 15 03:30:09 PM PDT 24
Peak memory 203924 kb
Host smart-b3f72867-de94-4ad6-97ae-9253bf0d8495
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907142135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fm
t.907142135
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.1556914741
Short name T576
Test name
Test status
Simulation time 301496587 ps
CPU time 4.73 seconds
Started Apr 15 03:30:07 PM PDT 24
Finished Apr 15 03:30:12 PM PDT 24
Peak memory 232692 kb
Host smart-8d7f7d7b-7562-47a2-8591-0591ded58361
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556914741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.1556914741
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.802683816
Short name T636
Test name
Test status
Simulation time 5696030124 ps
CPU time 133.52 seconds
Started Apr 15 03:30:05 PM PDT 24
Finished Apr 15 03:32:19 PM PDT 24
Peak memory 1181772 kb
Host smart-386b328f-b3f6-4001-bc76-78ebcd76da2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802683816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.802683816
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.4163309709
Short name T5
Test name
Test status
Simulation time 371554320 ps
CPU time 5.9 seconds
Started Apr 15 03:30:16 PM PDT 24
Finished Apr 15 03:30:23 PM PDT 24
Peak memory 204004 kb
Host smart-e466edda-5512-4fc9-b56f-1b5e71237a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163309709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.4163309709
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.2837185995
Short name T1081
Test name
Test status
Simulation time 6307423232 ps
CPU time 67.27 seconds
Started Apr 15 03:30:14 PM PDT 24
Finished Apr 15 03:31:22 PM PDT 24
Peak memory 284916 kb
Host smart-ef06d094-22ce-4c5a-9eba-6d3da1cadd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837185995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.2837185995
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.4031179243
Short name T1352
Test name
Test status
Simulation time 25444322 ps
CPU time 0.7 seconds
Started Apr 15 03:30:06 PM PDT 24
Finished Apr 15 03:30:07 PM PDT 24
Peak memory 203688 kb
Host smart-27ec3fa3-3241-49b6-b26b-5dbcc1351faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031179243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.4031179243
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.934286288
Short name T607
Test name
Test status
Simulation time 30308005121 ps
CPU time 2586.65 seconds
Started Apr 15 03:30:08 PM PDT 24
Finished Apr 15 04:13:15 PM PDT 24
Peak memory 4216544 kb
Host smart-fbf50476-a22c-41e7-a40f-aff7de8ee00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934286288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.934286288
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.1231788273
Short name T205
Test name
Test status
Simulation time 1099048095 ps
CPU time 21.49 seconds
Started Apr 15 03:30:04 PM PDT 24
Finished Apr 15 03:30:26 PM PDT 24
Peak memory 347600 kb
Host smart-568a4eb3-396d-43fa-9d9b-08514a0a38fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231788273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1231788273
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.416300007
Short name T1304
Test name
Test status
Simulation time 13996220359 ps
CPU time 701.6 seconds
Started Apr 15 03:30:09 PM PDT 24
Finished Apr 15 03:41:51 PM PDT 24
Peak memory 3107648 kb
Host smart-d14e73b2-e27b-4a69-b96a-9ac75f868b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416300007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.416300007
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.180963954
Short name T287
Test name
Test status
Simulation time 1959346214 ps
CPU time 46.22 seconds
Started Apr 15 03:30:10 PM PDT 24
Finished Apr 15 03:30:57 PM PDT 24
Peak memory 214940 kb
Host smart-92b3bcc8-70d5-4ac0-8203-c25e53793897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180963954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.180963954
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.875261407
Short name T851
Test name
Test status
Simulation time 3408652141 ps
CPU time 3.31 seconds
Started Apr 15 03:30:12 PM PDT 24
Finished Apr 15 03:30:16 PM PDT 24
Peak memory 204088 kb
Host smart-0bcc23b4-dacc-4a10-a180-a58cf8117ab1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875261407 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.875261407
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.4134144157
Short name T52
Test name
Test status
Simulation time 10036296189 ps
CPU time 64.55 seconds
Started Apr 15 03:30:12 PM PDT 24
Finished Apr 15 03:31:17 PM PDT 24
Peak memory 490188 kb
Host smart-c22330d8-6c51-41a8-aad5-c409136bb788
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134144157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.4134144157
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.2571896204
Short name T266
Test name
Test status
Simulation time 10382433256 ps
CPU time 15.94 seconds
Started Apr 15 03:30:12 PM PDT 24
Finished Apr 15 03:30:28 PM PDT 24
Peak memory 313796 kb
Host smart-33a1b3bd-3c5e-4e69-833d-8c4e15632614
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571896204 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.2571896204
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.3702449735
Short name T333
Test name
Test status
Simulation time 2009473606 ps
CPU time 5.6 seconds
Started Apr 15 03:30:06 PM PDT 24
Finished Apr 15 03:30:13 PM PDT 24
Peak memory 212220 kb
Host smart-7754133d-832b-49ab-9023-774c3c007435
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702449735 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.3702449735
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.126964088
Short name T715
Test name
Test status
Simulation time 15315948004 ps
CPU time 3.61 seconds
Started Apr 15 03:30:08 PM PDT 24
Finished Apr 15 03:30:12 PM PDT 24
Peak memory 204080 kb
Host smart-b4c3b5d1-d2d7-42ed-a7e3-c5a640cfbccd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126964088 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.126964088
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1311828265
Short name T416
Test name
Test status
Simulation time 1533695353 ps
CPU time 12.6 seconds
Started Apr 15 03:30:09 PM PDT 24
Finished Apr 15 03:30:22 PM PDT 24
Peak memory 204016 kb
Host smart-35a83fb7-4c1f-487e-9938-43941b92fa6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311828265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1311828265
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.2094624073
Short name T190
Test name
Test status
Simulation time 2639416645 ps
CPU time 24.56 seconds
Started Apr 15 03:30:09 PM PDT 24
Finished Apr 15 03:30:34 PM PDT 24
Peak memory 219424 kb
Host smart-785b25e2-af58-471e-8287-2ca0ae927c6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094624073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.2094624073
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.752657021
Short name T962
Test name
Test status
Simulation time 8830492612 ps
CPU time 4.93 seconds
Started Apr 15 03:30:08 PM PDT 24
Finished Apr 15 03:30:14 PM PDT 24
Peak memory 203984 kb
Host smart-bad5bfab-7b64-44d8-9ad8-e3bf8ce29057
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752657021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_wr.752657021
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.837453465
Short name T719
Test name
Test status
Simulation time 6468471316 ps
CPU time 542.86 seconds
Started Apr 15 03:30:08 PM PDT 24
Finished Apr 15 03:39:12 PM PDT 24
Peak memory 1597508 kb
Host smart-e168b1ca-6427-4ed3-ac27-b18ee14551d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837453465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_t
arget_stretch.837453465
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_alert_test.2811468413
Short name T374
Test name
Test status
Simulation time 47723853 ps
CPU time 0.64 seconds
Started Apr 15 03:30:21 PM PDT 24
Finished Apr 15 03:30:23 PM PDT 24
Peak memory 203564 kb
Host smart-53f52b40-09ca-4ce0-a06b-d2d9517c6b30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811468413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.2811468413
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.908219221
Short name T460
Test name
Test status
Simulation time 123581049 ps
CPU time 2.18 seconds
Started Apr 15 03:30:21 PM PDT 24
Finished Apr 15 03:30:24 PM PDT 24
Peak memory 212300 kb
Host smart-109a5b49-3a4b-44cd-9a07-3b6012a268e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908219221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.908219221
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.4252412605
Short name T1188
Test name
Test status
Simulation time 447029792 ps
CPU time 8.8 seconds
Started Apr 15 03:30:20 PM PDT 24
Finished Apr 15 03:30:30 PM PDT 24
Peak memory 288696 kb
Host smart-2d446cc8-c46d-4446-8605-baba8734abf6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252412605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.4252412605
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.547509396
Short name T44
Test name
Test status
Simulation time 8072757823 ps
CPU time 101.45 seconds
Started Apr 15 03:30:20 PM PDT 24
Finished Apr 15 03:32:02 PM PDT 24
Peak memory 557420 kb
Host smart-3a174386-d16c-4b46-a6ae-34ff74e654bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547509396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.547509396
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.3568975476
Short name T1202
Test name
Test status
Simulation time 10976091058 ps
CPU time 67.04 seconds
Started Apr 15 03:30:21 PM PDT 24
Finished Apr 15 03:31:29 PM PDT 24
Peak memory 638844 kb
Host smart-4c8eb7fa-e9fd-479d-bf58-34d872909f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568975476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.3568975476
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.3747089090
Short name T606
Test name
Test status
Simulation time 480411847 ps
CPU time 1.05 seconds
Started Apr 15 03:30:18 PM PDT 24
Finished Apr 15 03:30:20 PM PDT 24
Peak memory 203864 kb
Host smart-24aae900-d2da-4e52-943e-07d7af21e9e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747089090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.3747089090
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.3216209994
Short name T822
Test name
Test status
Simulation time 577801258 ps
CPU time 7.07 seconds
Started Apr 15 03:30:26 PM PDT 24
Finished Apr 15 03:30:34 PM PDT 24
Peak memory 203916 kb
Host smart-3fc3f84e-dbb2-455c-a469-c6b32376a0ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216209994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.3216209994
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.342205646
Short name T1231
Test name
Test status
Simulation time 9060881382 ps
CPU time 133.11 seconds
Started Apr 15 03:30:15 PM PDT 24
Finished Apr 15 03:32:28 PM PDT 24
Peak memory 1307188 kb
Host smart-42ee1987-a6af-4669-b729-0f9a428fd6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342205646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.342205646
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.607270269
Short name T492
Test name
Test status
Simulation time 489102435 ps
CPU time 6.04 seconds
Started Apr 15 03:30:20 PM PDT 24
Finished Apr 15 03:30:27 PM PDT 24
Peak memory 203996 kb
Host smart-3ee6f0ae-30a3-4bd3-b193-5bea89a4c6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607270269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.607270269
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.1703814718
Short name T993
Test name
Test status
Simulation time 13082781464 ps
CPU time 49.05 seconds
Started Apr 15 03:30:21 PM PDT 24
Finished Apr 15 03:31:11 PM PDT 24
Peak memory 405472 kb
Host smart-eda8a7c2-7ac3-4608-b465-dd975c337dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703814718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.1703814718
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.1185000056
Short name T956
Test name
Test status
Simulation time 72966971 ps
CPU time 0.63 seconds
Started Apr 15 03:30:35 PM PDT 24
Finished Apr 15 03:30:36 PM PDT 24
Peak memory 203644 kb
Host smart-1854b93a-e548-4964-8d3e-3f751cbc0bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185000056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.1185000056
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.1022172319
Short name T1236
Test name
Test status
Simulation time 27269812458 ps
CPU time 259.44 seconds
Started Apr 15 03:30:16 PM PDT 24
Finished Apr 15 03:34:36 PM PDT 24
Peak memory 230148 kb
Host smart-69f09920-6564-4993-894f-76d11abb116d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022172319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.1022172319
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.2938000444
Short name T966
Test name
Test status
Simulation time 2498654542 ps
CPU time 40.77 seconds
Started Apr 15 03:30:20 PM PDT 24
Finished Apr 15 03:31:02 PM PDT 24
Peak memory 297260 kb
Host smart-d44bbca8-e1e3-4050-a842-16b56956a7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938000444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.2938000444
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.4055617386
Short name T1184
Test name
Test status
Simulation time 1274667188 ps
CPU time 27.91 seconds
Started Apr 15 03:30:19 PM PDT 24
Finished Apr 15 03:30:47 PM PDT 24
Peak memory 212192 kb
Host smart-e27dd63f-6053-4be2-983f-55a550ac797a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055617386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.4055617386
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.963949981
Short name T1239
Test name
Test status
Simulation time 1254771441 ps
CPU time 6.29 seconds
Started Apr 15 03:30:21 PM PDT 24
Finished Apr 15 03:30:28 PM PDT 24
Peak memory 212468 kb
Host smart-20ac6a2b-eb1a-4841-a459-910440fb9d8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963949981 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.963949981
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.154898991
Short name T104
Test name
Test status
Simulation time 10300521159 ps
CPU time 14.35 seconds
Started Apr 15 03:30:21 PM PDT 24
Finished Apr 15 03:30:36 PM PDT 24
Peak memory 299768 kb
Host smart-4516cbdf-2d81-4468-93d9-0dad46b5b0c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154898991 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_fifo_reset_tx.154898991
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.1003769778
Short name T389
Test name
Test status
Simulation time 1632689052 ps
CPU time 2.54 seconds
Started Apr 15 03:30:19 PM PDT 24
Finished Apr 15 03:30:22 PM PDT 24
Peak memory 203892 kb
Host smart-145dd36a-6a62-4a0a-9848-270bd1f4aeb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003769778 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.1003769778
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.3672113525
Short name T813
Test name
Test status
Simulation time 1656507709 ps
CPU time 4.57 seconds
Started Apr 15 03:30:15 PM PDT 24
Finished Apr 15 03:30:20 PM PDT 24
Peak memory 204008 kb
Host smart-0b599ce3-a75a-424b-8f74-78b1b658aea7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672113525 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.3672113525
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.244276872
Short name T656
Test name
Test status
Simulation time 10414502611 ps
CPU time 27.44 seconds
Started Apr 15 03:30:20 PM PDT 24
Finished Apr 15 03:30:49 PM PDT 24
Peak memory 635696 kb
Host smart-a477d7fc-484f-420b-9143-644e25667d11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244276872 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.244276872
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.3302551975
Short name T867
Test name
Test status
Simulation time 5204102707 ps
CPU time 24.54 seconds
Started Apr 15 03:30:20 PM PDT 24
Finished Apr 15 03:30:45 PM PDT 24
Peak memory 204088 kb
Host smart-981f1145-c378-4b82-8d4e-c5049574f0f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302551975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.3302551975
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.3961821837
Short name T392
Test name
Test status
Simulation time 14291143773 ps
CPU time 13.03 seconds
Started Apr 15 03:30:17 PM PDT 24
Finished Apr 15 03:30:30 PM PDT 24
Peak memory 209480 kb
Host smart-5314394b-c12f-4329-9a3e-1e12048d5c47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961821837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.3961821837
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.732802119
Short name T324
Test name
Test status
Simulation time 42561644618 ps
CPU time 866.5 seconds
Started Apr 15 03:30:19 PM PDT 24
Finished Apr 15 03:44:46 PM PDT 24
Peak memory 5444472 kb
Host smart-8c07404e-f204-4ae3-b062-7112f931874c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732802119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_wr.732802119
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.3789770275
Short name T364
Test name
Test status
Simulation time 13175786530 ps
CPU time 536.98 seconds
Started Apr 15 03:30:18 PM PDT 24
Finished Apr 15 03:39:15 PM PDT 24
Peak memory 3138696 kb
Host smart-ad5375a3-467d-4e3d-be1c-23cd7a75edb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789770275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.3789770275
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.3478088814
Short name T894
Test name
Test status
Simulation time 4547453694 ps
CPU time 6 seconds
Started Apr 15 03:30:20 PM PDT 24
Finished Apr 15 03:30:27 PM PDT 24
Peak memory 212280 kb
Host smart-d2a10496-5799-4ca6-b90f-49af0f145182
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478088814 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.3478088814
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.4056678474
Short name T377
Test name
Test status
Simulation time 161027211 ps
CPU time 0.63 seconds
Started Apr 15 03:30:27 PM PDT 24
Finished Apr 15 03:30:28 PM PDT 24
Peak memory 203524 kb
Host smart-d09a56f9-eb67-4538-99a4-2b3781cdd937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056678474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.4056678474
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.3588037998
Short name T605
Test name
Test status
Simulation time 982696592 ps
CPU time 1.59 seconds
Started Apr 15 03:30:23 PM PDT 24
Finished Apr 15 03:30:26 PM PDT 24
Peak memory 212336 kb
Host smart-acf1501d-4155-425f-b367-029a86d906bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588037998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3588037998
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.759000530
Short name T1321
Test name
Test status
Simulation time 394325535 ps
CPU time 20.62 seconds
Started Apr 15 03:30:21 PM PDT 24
Finished Apr 15 03:30:42 PM PDT 24
Peak memory 290468 kb
Host smart-4b7dec42-b0d9-46e9-ae92-a05cb2530f10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759000530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empt
y.759000530
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.2180246569
Short name T381
Test name
Test status
Simulation time 9220829368 ps
CPU time 201.52 seconds
Started Apr 15 03:30:24 PM PDT 24
Finished Apr 15 03:33:46 PM PDT 24
Peak memory 829724 kb
Host smart-99060ea1-2c58-4bf1-9ed0-ce4d4cdf2ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180246569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.2180246569
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.102258966
Short name T953
Test name
Test status
Simulation time 4284297932 ps
CPU time 67.61 seconds
Started Apr 15 03:30:22 PM PDT 24
Finished Apr 15 03:31:31 PM PDT 24
Peak memory 736152 kb
Host smart-38e95ae2-5a2e-4672-bc28-66fe1fe71d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102258966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.102258966
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.1292901237
Short name T228
Test name
Test status
Simulation time 112260504 ps
CPU time 0.97 seconds
Started Apr 15 03:30:18 PM PDT 24
Finished Apr 15 03:30:20 PM PDT 24
Peak memory 203732 kb
Host smart-0964f9e1-12b8-4890-91ca-625c5d5f6a80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292901237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.1292901237
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.1419310976
Short name T773
Test name
Test status
Simulation time 120060075 ps
CPU time 3.01 seconds
Started Apr 15 03:30:21 PM PDT 24
Finished Apr 15 03:30:25 PM PDT 24
Peak memory 203964 kb
Host smart-b717cce1-31c2-48c5-89a5-46fe63ff7f05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419310976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.1419310976
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.1788465593
Short name T411
Test name
Test status
Simulation time 13354423987 ps
CPU time 88.66 seconds
Started Apr 15 03:30:18 PM PDT 24
Finished Apr 15 03:31:48 PM PDT 24
Peak memory 939408 kb
Host smart-3f11c911-c94b-4a31-a28f-43ebeb1bbc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788465593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.1788465593
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1563548333
Short name T1154
Test name
Test status
Simulation time 366383122 ps
CPU time 14.71 seconds
Started Apr 15 03:30:27 PM PDT 24
Finished Apr 15 03:30:42 PM PDT 24
Peak memory 203980 kb
Host smart-2badcf8e-f5a5-4805-80d6-5f460597a501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563548333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1563548333
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.182935926
Short name T556
Test name
Test status
Simulation time 2062245976 ps
CPU time 98.28 seconds
Started Apr 15 03:30:29 PM PDT 24
Finished Apr 15 03:32:08 PM PDT 24
Peak memory 364880 kb
Host smart-6b590f22-6a5a-417c-aaff-96921cf72cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182935926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.182935926
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.3473487719
Short name T626
Test name
Test status
Simulation time 31157279 ps
CPU time 0.69 seconds
Started Apr 15 03:30:21 PM PDT 24
Finished Apr 15 03:30:23 PM PDT 24
Peak memory 203668 kb
Host smart-56182186-1df0-411e-a70c-fc53ef3eacb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473487719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.3473487719
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.3796741141
Short name T922
Test name
Test status
Simulation time 7495463783 ps
CPU time 156.98 seconds
Started Apr 15 03:30:23 PM PDT 24
Finished Apr 15 03:33:00 PM PDT 24
Peak memory 777628 kb
Host smart-5fd48e60-fbbf-4659-97fb-58e9e48e4385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796741141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.3796741141
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.2425513036
Short name T668
Test name
Test status
Simulation time 1071072869 ps
CPU time 21.72 seconds
Started Apr 15 03:30:23 PM PDT 24
Finished Apr 15 03:30:46 PM PDT 24
Peak memory 297632 kb
Host smart-b8713d22-7960-4f6a-a773-329df7618302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425513036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.2425513036
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.3651955488
Short name T496
Test name
Test status
Simulation time 2317076184 ps
CPU time 9.88 seconds
Started Apr 15 03:30:26 PM PDT 24
Finished Apr 15 03:30:36 PM PDT 24
Peak memory 220436 kb
Host smart-80797ba3-f32c-4744-a050-49bd3b808f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651955488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.3651955488
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.579347437
Short name T766
Test name
Test status
Simulation time 3195027798 ps
CPU time 3.98 seconds
Started Apr 15 03:30:27 PM PDT 24
Finished Apr 15 03:30:32 PM PDT 24
Peak memory 204016 kb
Host smart-b962a5a3-b5b8-46ef-a850-8ffcbd280a71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579347437 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.579347437
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.514533063
Short name T114
Test name
Test status
Simulation time 10276741053 ps
CPU time 12.41 seconds
Started Apr 15 03:30:28 PM PDT 24
Finished Apr 15 03:30:41 PM PDT 24
Peak memory 269164 kb
Host smart-58b310bc-d6cb-4606-ad85-58250f441623
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514533063 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_acq.514533063
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.2062399072
Short name T939
Test name
Test status
Simulation time 10115132520 ps
CPU time 59.05 seconds
Started Apr 15 03:30:28 PM PDT 24
Finished Apr 15 03:31:28 PM PDT 24
Peak memory 522324 kb
Host smart-b87e151c-7352-4ec5-81a0-3642fa321cc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062399072 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.2062399072
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.1582877085
Short name T827
Test name
Test status
Simulation time 1500241489 ps
CPU time 2.09 seconds
Started Apr 15 03:30:29 PM PDT 24
Finished Apr 15 03:30:32 PM PDT 24
Peak memory 204032 kb
Host smart-1c2e6b29-3537-47e5-95b4-9f0d39fe3df7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582877085 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.1582877085
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.598777756
Short name T349
Test name
Test status
Simulation time 3614751576 ps
CPU time 5.29 seconds
Started Apr 15 03:30:26 PM PDT 24
Finished Apr 15 03:30:32 PM PDT 24
Peak memory 212240 kb
Host smart-43979bcf-73fa-4efd-a03b-ec5a5015e2a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598777756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_intr_smoke.598777756
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.1057376854
Short name T1134
Test name
Test status
Simulation time 23752671145 ps
CPU time 78.95 seconds
Started Apr 15 03:30:26 PM PDT 24
Finished Apr 15 03:31:45 PM PDT 24
Peak memory 1036888 kb
Host smart-672be908-6be8-41e4-a577-7255c3a31268
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057376854 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.1057376854
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.1360273416
Short name T765
Test name
Test status
Simulation time 1031652114 ps
CPU time 15.98 seconds
Started Apr 15 03:30:23 PM PDT 24
Finished Apr 15 03:30:39 PM PDT 24
Peak memory 203988 kb
Host smart-ff317e4e-aedf-4ca1-a3fb-b8132aae3a6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360273416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.1360273416
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.3111297702
Short name T382
Test name
Test status
Simulation time 5088489779 ps
CPU time 19.19 seconds
Started Apr 15 03:30:23 PM PDT 24
Finished Apr 15 03:30:43 PM PDT 24
Peak memory 221872 kb
Host smart-22899fd2-178e-44eb-877f-63d354ffd8b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111297702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.3111297702
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.3102506182
Short name T340
Test name
Test status
Simulation time 51274034333 ps
CPU time 165.18 seconds
Started Apr 15 03:30:24 PM PDT 24
Finished Apr 15 03:33:09 PM PDT 24
Peak memory 2054672 kb
Host smart-426d63c2-4429-4348-b764-0124ff0aaba5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102506182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.3102506182
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.2611335479
Short name T1207
Test name
Test status
Simulation time 23499090378 ps
CPU time 1418.43 seconds
Started Apr 15 03:30:25 PM PDT 24
Finished Apr 15 03:54:04 PM PDT 24
Peak memory 5739088 kb
Host smart-08abe068-cda5-4093-9b28-bacd6c8146c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611335479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.2611335479
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.1692176440
Short name T12
Test name
Test status
Simulation time 10435002656 ps
CPU time 6.79 seconds
Started Apr 15 03:30:23 PM PDT 24
Finished Apr 15 03:30:31 PM PDT 24
Peak memory 210888 kb
Host smart-ebee1de6-7d15-42a0-9220-bf710396634d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692176440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.1692176440
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.1482475467
Short name T1159
Test name
Test status
Simulation time 35838178 ps
CPU time 0.63 seconds
Started Apr 15 03:30:38 PM PDT 24
Finished Apr 15 03:30:39 PM PDT 24
Peak memory 203584 kb
Host smart-7a5fb8d1-04b0-425f-b931-10fac0a1e7b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482475467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.1482475467
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.717601896
Short name T295
Test name
Test status
Simulation time 88793429 ps
CPU time 1.42 seconds
Started Apr 15 03:30:32 PM PDT 24
Finished Apr 15 03:30:34 PM PDT 24
Peak memory 212332 kb
Host smart-642e33cb-6416-4cb3-be31-c6a6185bef46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717601896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.717601896
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2406127909
Short name T835
Test name
Test status
Simulation time 3833521120 ps
CPU time 8.15 seconds
Started Apr 15 03:30:31 PM PDT 24
Finished Apr 15 03:30:39 PM PDT 24
Peak memory 255908 kb
Host smart-5b788077-1125-46fb-b008-5c745c1dea85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406127909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.2406127909
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.1753592685
Short name T1044
Test name
Test status
Simulation time 1864715639 ps
CPU time 62.77 seconds
Started Apr 15 03:30:33 PM PDT 24
Finished Apr 15 03:31:36 PM PDT 24
Peak memory 646660 kb
Host smart-43796f6e-2a1d-4b4d-8a5c-0b56da98e1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753592685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.1753592685
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.2983205069
Short name T687
Test name
Test status
Simulation time 6929225867 ps
CPU time 53.52 seconds
Started Apr 15 03:30:33 PM PDT 24
Finished Apr 15 03:31:27 PM PDT 24
Peak memory 643632 kb
Host smart-4f75446f-193d-4e74-a91d-78c7879ee237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983205069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2983205069
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.1795439491
Short name T926
Test name
Test status
Simulation time 233323791 ps
CPU time 0.96 seconds
Started Apr 15 03:30:31 PM PDT 24
Finished Apr 15 03:30:32 PM PDT 24
Peak memory 203772 kb
Host smart-5b25603f-5c2f-4a98-ac3f-008ac37aebb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795439491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.1795439491
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.2189590718
Short name T1345
Test name
Test status
Simulation time 282752438 ps
CPU time 3.57 seconds
Started Apr 15 03:30:31 PM PDT 24
Finished Apr 15 03:30:35 PM PDT 24
Peak memory 226388 kb
Host smart-8c44122b-e893-426c-ac91-80e7fb368828
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189590718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.2189590718
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.616243088
Short name T944
Test name
Test status
Simulation time 10443196885 ps
CPU time 181.49 seconds
Started Apr 15 03:30:32 PM PDT 24
Finished Apr 15 03:33:34 PM PDT 24
Peak memory 854864 kb
Host smart-0273b4e5-aa52-4b08-ad30-e8eaed11b1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616243088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.616243088
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.4202022910
Short name T312
Test name
Test status
Simulation time 464642553 ps
CPU time 3.9 seconds
Started Apr 15 03:30:38 PM PDT 24
Finished Apr 15 03:30:43 PM PDT 24
Peak memory 203968 kb
Host smart-ac175ccb-604b-43c1-be7a-58051124660c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202022910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.4202022910
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.510419514
Short name T450
Test name
Test status
Simulation time 6080423894 ps
CPU time 67.18 seconds
Started Apr 15 03:30:42 PM PDT 24
Finished Apr 15 03:31:50 PM PDT 24
Peak memory 285388 kb
Host smart-daa56800-4b09-4d33-83b1-6f23503f7c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510419514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.510419514
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.1976110409
Short name T343
Test name
Test status
Simulation time 29463448 ps
CPU time 0.68 seconds
Started Apr 15 03:30:32 PM PDT 24
Finished Apr 15 03:30:34 PM PDT 24
Peak memory 203628 kb
Host smart-4f82f271-efc7-4e48-b9f3-069b14cb6cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976110409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.1976110409
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.271043369
Short name T1212
Test name
Test status
Simulation time 5306623454 ps
CPU time 30.29 seconds
Started Apr 15 03:30:33 PM PDT 24
Finished Apr 15 03:31:04 PM PDT 24
Peak memory 226996 kb
Host smart-c6483809-13c6-4848-8e69-5baad0efa5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271043369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.271043369
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.2860553207
Short name T928
Test name
Test status
Simulation time 1141900839 ps
CPU time 51.67 seconds
Started Apr 15 03:30:29 PM PDT 24
Finished Apr 15 03:31:21 PM PDT 24
Peak memory 309364 kb
Host smart-4cbaaf74-4e5e-4f75-91e0-984a3fe90d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860553207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2860553207
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.3662267650
Short name T970
Test name
Test status
Simulation time 10734921662 ps
CPU time 522.17 seconds
Started Apr 15 03:30:37 PM PDT 24
Finished Apr 15 03:39:21 PM PDT 24
Peak memory 1739228 kb
Host smart-a2655a2a-9a9f-4592-804a-adfc67dbb9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662267650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.3662267650
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.3055991892
Short name T337
Test name
Test status
Simulation time 2256828494 ps
CPU time 7.58 seconds
Started Apr 15 03:30:31 PM PDT 24
Finished Apr 15 03:30:40 PM PDT 24
Peak memory 212296 kb
Host smart-dd99ef73-b7d2-4ef9-accb-69d226b0fd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055991892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.3055991892
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.2657497739
Short name T757
Test name
Test status
Simulation time 2075476040 ps
CPU time 3.22 seconds
Started Apr 15 03:30:35 PM PDT 24
Finished Apr 15 03:30:39 PM PDT 24
Peak memory 203980 kb
Host smart-40ae9f20-079a-428e-93fd-ce8bc202cad0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657497739 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.2657497739
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.182390740
Short name T383
Test name
Test status
Simulation time 10046050315 ps
CPU time 78.53 seconds
Started Apr 15 03:30:36 PM PDT 24
Finished Apr 15 03:31:55 PM PDT 24
Peak memory 529920 kb
Host smart-608fe345-4b74-4622-b0a7-11b3f7b9a1ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182390740 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_acq.182390740
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.2238361291
Short name T1318
Test name
Test status
Simulation time 10156166638 ps
CPU time 15.86 seconds
Started Apr 15 03:30:35 PM PDT 24
Finished Apr 15 03:30:52 PM PDT 24
Peak memory 285904 kb
Host smart-191c4902-1976-494a-ab19-3499b5a7639c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238361291 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.2238361291
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.370826294
Short name T619
Test name
Test status
Simulation time 2184309812 ps
CPU time 2.75 seconds
Started Apr 15 03:30:39 PM PDT 24
Finished Apr 15 03:30:42 PM PDT 24
Peak memory 204000 kb
Host smart-75ac854a-e69d-4225-9444-461b6536dd7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370826294 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.i2c_target_hrst.370826294
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.2481346657
Short name T1122
Test name
Test status
Simulation time 1083992636 ps
CPU time 4.91 seconds
Started Apr 15 03:30:39 PM PDT 24
Finished Apr 15 03:30:45 PM PDT 24
Peak memory 204820 kb
Host smart-503f4b94-8a22-4d60-a3cc-25652fab9bec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481346657 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.2481346657
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.2913030069
Short name T654
Test name
Test status
Simulation time 12561170186 ps
CPU time 8.44 seconds
Started Apr 15 03:30:38 PM PDT 24
Finished Apr 15 03:30:47 PM PDT 24
Peak memory 260220 kb
Host smart-a22767d1-fbef-4dd2-b345-c68bd1060ece
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913030069 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.2913030069
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.2108365908
Short name T1098
Test name
Test status
Simulation time 1151873139 ps
CPU time 45.15 seconds
Started Apr 15 03:30:34 PM PDT 24
Finished Apr 15 03:31:20 PM PDT 24
Peak memory 204012 kb
Host smart-b8dc3e04-3832-448c-bd68-96f1cb90b11b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108365908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.2108365908
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.396187788
Short name T876
Test name
Test status
Simulation time 18532972228 ps
CPU time 32.31 seconds
Started Apr 15 03:30:39 PM PDT 24
Finished Apr 15 03:31:13 PM PDT 24
Peak memory 204104 kb
Host smart-39c326ab-ddd8-4192-a3a9-89f9ebad28b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396187788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_wr.396187788
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.2686311308
Short name T709
Test name
Test status
Simulation time 24873357950 ps
CPU time 466.38 seconds
Started Apr 15 03:30:36 PM PDT 24
Finished Apr 15 03:38:23 PM PDT 24
Peak memory 2935724 kb
Host smart-9c14ef50-a65f-4b16-a948-266407a62ca3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686311308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.2686311308
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.1227812804
Short name T680
Test name
Test status
Simulation time 3776829001 ps
CPU time 5.84 seconds
Started Apr 15 03:30:35 PM PDT 24
Finished Apr 15 03:30:42 PM PDT 24
Peak memory 204116 kb
Host smart-02857a18-f9e1-4fe0-b144-0a749ab74d88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227812804 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.1227812804
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2434410246
Short name T511
Test name
Test status
Simulation time 36565223 ps
CPU time 0.58 seconds
Started Apr 15 03:30:44 PM PDT 24
Finished Apr 15 03:30:45 PM PDT 24
Peak memory 203568 kb
Host smart-635fd46e-add1-4c70-826a-b9c11a2466bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434410246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2434410246
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.1772736954
Short name T785
Test name
Test status
Simulation time 107957996 ps
CPU time 1.23 seconds
Started Apr 15 03:30:44 PM PDT 24
Finished Apr 15 03:30:45 PM PDT 24
Peak memory 204080 kb
Host smart-b3b14ca2-68e7-452b-b1c0-665f662bb5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772736954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.1772736954
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.1650001349
Short name T269
Test name
Test status
Simulation time 550800873 ps
CPU time 3.28 seconds
Started Apr 15 03:30:39 PM PDT 24
Finished Apr 15 03:30:43 PM PDT 24
Peak memory 227044 kb
Host smart-f6e952f5-1a8e-475f-b463-dcbe23e0e59f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650001349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.1650001349
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.3406513047
Short name T861
Test name
Test status
Simulation time 1224129333 ps
CPU time 69.32 seconds
Started Apr 15 03:30:41 PM PDT 24
Finished Apr 15 03:31:51 PM PDT 24
Peak memory 449580 kb
Host smart-756efa85-3780-4681-97dd-62075ee98c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406513047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.3406513047
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.2214476251
Short name T912
Test name
Test status
Simulation time 1359071337 ps
CPU time 96.18 seconds
Started Apr 15 03:30:38 PM PDT 24
Finished Apr 15 03:32:15 PM PDT 24
Peak memory 524740 kb
Host smart-dc16896b-2d56-40d6-be1e-3b8de3446d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214476251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.2214476251
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.1240731668
Short name T1225
Test name
Test status
Simulation time 115190505 ps
CPU time 1.01 seconds
Started Apr 15 03:30:39 PM PDT 24
Finished Apr 15 03:30:41 PM PDT 24
Peak memory 203728 kb
Host smart-b2b436b3-42ef-44cd-b2d1-b3e5c6b5e34e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240731668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.1240731668
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.189733221
Short name T314
Test name
Test status
Simulation time 333353460 ps
CPU time 9.89 seconds
Started Apr 15 03:30:41 PM PDT 24
Finished Apr 15 03:30:52 PM PDT 24
Peak memory 236012 kb
Host smart-3d99e5a4-4216-44e4-941d-9bffafb51bda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189733221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.
189733221
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.1888998260
Short name T186
Test name
Test status
Simulation time 13933240333 ps
CPU time 66.51 seconds
Started Apr 15 03:30:39 PM PDT 24
Finished Apr 15 03:31:46 PM PDT 24
Peak memory 905132 kb
Host smart-f3e1a631-0416-4d8f-b282-ac535eaff4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888998260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.1888998260
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.2490422538
Short name T1048
Test name
Test status
Simulation time 1296505269 ps
CPU time 4.79 seconds
Started Apr 15 03:30:46 PM PDT 24
Finished Apr 15 03:30:52 PM PDT 24
Peak memory 203920 kb
Host smart-b8248466-8eeb-4d27-ac8d-dcbfc160a623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490422538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.2490422538
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_override.1973238721
Short name T206
Test name
Test status
Simulation time 20861522 ps
CPU time 0.71 seconds
Started Apr 15 03:30:40 PM PDT 24
Finished Apr 15 03:30:41 PM PDT 24
Peak memory 203636 kb
Host smart-7f4ed7ec-877c-462b-ad9c-90f04d72c68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973238721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.1973238721
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.4224912797
Short name T621
Test name
Test status
Simulation time 29340017563 ps
CPU time 258 seconds
Started Apr 15 03:30:43 PM PDT 24
Finished Apr 15 03:35:02 PM PDT 24
Peak memory 1307904 kb
Host smart-5dba230d-225f-4b1f-b7ec-086684f7069e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224912797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.4224912797
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2390485031
Short name T541
Test name
Test status
Simulation time 4183510959 ps
CPU time 16.52 seconds
Started Apr 15 03:30:40 PM PDT 24
Finished Apr 15 03:30:57 PM PDT 24
Peak memory 275036 kb
Host smart-c2de0634-9eed-4472-a9eb-fda0b555678f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390485031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2390485031
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.2387308253
Short name T232
Test name
Test status
Simulation time 70701468630 ps
CPU time 1862.51 seconds
Started Apr 15 03:30:43 PM PDT 24
Finished Apr 15 04:01:46 PM PDT 24
Peak memory 2652472 kb
Host smart-19a44099-8b19-4620-b698-616380f75e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387308253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.2387308253
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.925044511
Short name T534
Test name
Test status
Simulation time 10136543795 ps
CPU time 3.3 seconds
Started Apr 15 03:30:45 PM PDT 24
Finished Apr 15 03:30:49 PM PDT 24
Peak memory 204032 kb
Host smart-c78ca669-ac60-46dd-bbe8-9fa0f41a7e56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925044511 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.925044511
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.2387492281
Short name T1298
Test name
Test status
Simulation time 10034436346 ps
CPU time 66.58 seconds
Started Apr 15 03:30:44 PM PDT 24
Finished Apr 15 03:31:51 PM PDT 24
Peak memory 519664 kb
Host smart-f76982e3-2946-4a32-a60b-747d65f5acbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387492281 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.2387492281
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.3597333794
Short name T923
Test name
Test status
Simulation time 10153994062 ps
CPU time 38.21 seconds
Started Apr 15 03:30:57 PM PDT 24
Finished Apr 15 03:31:36 PM PDT 24
Peak memory 434048 kb
Host smart-0fa6c864-41d5-4c3c-a165-d751b55bcdcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597333794 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.3597333794
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.3107340809
Short name T1091
Test name
Test status
Simulation time 751818519 ps
CPU time 2.36 seconds
Started Apr 15 03:30:46 PM PDT 24
Finished Apr 15 03:30:49 PM PDT 24
Peak memory 203940 kb
Host smart-a3d18651-27e3-4f04-ad1f-02a4fa0c14c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107340809 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.3107340809
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.87558936
Short name T872
Test name
Test status
Simulation time 2257350213 ps
CPU time 6.39 seconds
Started Apr 15 03:30:42 PM PDT 24
Finished Apr 15 03:30:49 PM PDT 24
Peak memory 212200 kb
Host smart-5cb5bd22-9fa9-4eb1-ae92-3edc88b7648b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87558936 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.87558936
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.46656299
Short name T1317
Test name
Test status
Simulation time 11426165149 ps
CPU time 72.77 seconds
Started Apr 15 03:30:44 PM PDT 24
Finished Apr 15 03:31:57 PM PDT 24
Peak memory 1247080 kb
Host smart-fcd57e8c-b1dd-4b1c-b325-58d2f4634b0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46656299 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.46656299
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.3764053585
Short name T1152
Test name
Test status
Simulation time 1436232227 ps
CPU time 11.59 seconds
Started Apr 15 03:30:43 PM PDT 24
Finished Apr 15 03:30:56 PM PDT 24
Peak memory 204004 kb
Host smart-3c09e3e6-81d3-4b0b-9af0-2255041d71d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764053585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.3764053585
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.532713821
Short name T355
Test name
Test status
Simulation time 275955807 ps
CPU time 4.69 seconds
Started Apr 15 03:30:53 PM PDT 24
Finished Apr 15 03:30:58 PM PDT 24
Peak memory 203968 kb
Host smart-3b5a4992-bb27-4694-b4e6-bb958d31e36b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532713821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c
_target_stress_rd.532713821
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2955154030
Short name T1340
Test name
Test status
Simulation time 14846969093 ps
CPU time 8.12 seconds
Started Apr 15 03:30:43 PM PDT 24
Finished Apr 15 03:30:52 PM PDT 24
Peak memory 204052 kb
Host smart-6cd85500-54e3-43a5-84bc-86c5d7176751
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955154030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2955154030
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.846161859
Short name T1354
Test name
Test status
Simulation time 24266324030 ps
CPU time 304.61 seconds
Started Apr 15 03:30:42 PM PDT 24
Finished Apr 15 03:35:47 PM PDT 24
Peak memory 1987636 kb
Host smart-21efe26c-3e01-4f07-b5d9-4b4c9ea76bb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846161859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_t
arget_stretch.846161859
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2527351220
Short name T1005
Test name
Test status
Simulation time 1405053430 ps
CPU time 6.83 seconds
Started Apr 15 03:30:44 PM PDT 24
Finished Apr 15 03:30:52 PM PDT 24
Peak memory 220208 kb
Host smart-83893b87-eb96-4b00-8f0c-82b9fee10c10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527351220 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2527351220
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_unexp_stop.4071455016
Short name T18
Test name
Test status
Simulation time 4513487691 ps
CPU time 5.08 seconds
Started Apr 15 03:30:42 PM PDT 24
Finished Apr 15 03:30:48 PM PDT 24
Peak memory 204084 kb
Host smart-004e80b1-6a1a-4d98-a651-6578ac65b73f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071455016 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.i2c_target_unexp_stop.4071455016
Directory /workspace/19.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/2.i2c_alert_test.4167791053
Short name T1046
Test name
Test status
Simulation time 45619542 ps
CPU time 0.66 seconds
Started Apr 15 03:28:42 PM PDT 24
Finished Apr 15 03:28:45 PM PDT 24
Peak memory 203576 kb
Host smart-9ffd7000-ff1f-4034-8b40-6f0b93595ef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167791053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.4167791053
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.4171400368
Short name T753
Test name
Test status
Simulation time 601537836 ps
CPU time 1.57 seconds
Started Apr 15 03:28:37 PM PDT 24
Finished Apr 15 03:28:39 PM PDT 24
Peak memory 204084 kb
Host smart-df54cb2f-9682-477d-b888-f1cc55b0d5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171400368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.4171400368
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.2022561823
Short name T660
Test name
Test status
Simulation time 190760211 ps
CPU time 4.15 seconds
Started Apr 15 03:28:41 PM PDT 24
Finished Apr 15 03:28:46 PM PDT 24
Peak memory 236088 kb
Host smart-cb8e294d-24ae-493f-bc1b-bcc5531daf50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022561823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.2022561823
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.1596497264
Short name T187
Test name
Test status
Simulation time 3397398277 ps
CPU time 126.59 seconds
Started Apr 15 03:28:36 PM PDT 24
Finished Apr 15 03:30:44 PM PDT 24
Peak memory 625032 kb
Host smart-eedff540-6559-4a3b-acf3-cccffe7b9dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596497264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.1596497264
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.1631147858
Short name T1036
Test name
Test status
Simulation time 108417037 ps
CPU time 0.92 seconds
Started Apr 15 03:28:42 PM PDT 24
Finished Apr 15 03:28:43 PM PDT 24
Peak memory 203732 kb
Host smart-57521cc1-47df-4880-aab2-3d8853f17ed0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631147858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.1631147858
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3907929199
Short name T645
Test name
Test status
Simulation time 555165874 ps
CPU time 7.69 seconds
Started Apr 15 03:28:37 PM PDT 24
Finished Apr 15 03:28:46 PM PDT 24
Peak memory 224320 kb
Host smart-3d6d81c9-3b61-43a2-8bbc-297c57aa1c14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907929199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3907929199
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.1071193939
Short name T179
Test name
Test status
Simulation time 32918879841 ps
CPU time 76.92 seconds
Started Apr 15 03:28:39 PM PDT 24
Finished Apr 15 03:29:56 PM PDT 24
Peak memory 1022396 kb
Host smart-a4f506bc-77b7-4c07-af7e-0809e022a030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071193939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.1071193939
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.4087810692
Short name T808
Test name
Test status
Simulation time 1595381120 ps
CPU time 4.88 seconds
Started Apr 15 03:28:43 PM PDT 24
Finished Apr 15 03:28:49 PM PDT 24
Peak memory 203932 kb
Host smart-e13dad5a-18c7-4fac-8ac3-eb97cc92b8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087810692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.4087810692
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.296069783
Short name T824
Test name
Test status
Simulation time 1969459727 ps
CPU time 104.04 seconds
Started Apr 15 03:28:47 PM PDT 24
Finished Apr 15 03:30:32 PM PDT 24
Peak memory 455468 kb
Host smart-2320db71-e7b9-4709-bba8-0ab9ea804606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296069783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.296069783
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.3596113522
Short name T434
Test name
Test status
Simulation time 24584080 ps
CPU time 0.68 seconds
Started Apr 15 03:28:38 PM PDT 24
Finished Apr 15 03:28:39 PM PDT 24
Peak memory 203712 kb
Host smart-8b5932f4-8304-43eb-ad70-5c10f0dc0a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596113522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.3596113522
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.2694241040
Short name T553
Test name
Test status
Simulation time 6149020804 ps
CPU time 443.16 seconds
Started Apr 15 03:28:39 PM PDT 24
Finished Apr 15 03:36:03 PM PDT 24
Peak memory 1228696 kb
Host smart-17268f41-2de1-4fc1-80ef-7669b5aa7f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694241040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.2694241040
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.482550056
Short name T984
Test name
Test status
Simulation time 7259849757 ps
CPU time 72.14 seconds
Started Apr 15 03:28:38 PM PDT 24
Finished Apr 15 03:29:51 PM PDT 24
Peak memory 294724 kb
Host smart-b8d4e76d-0791-431f-bde2-2cb584ad050b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482550056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.482550056
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.3339063530
Short name T362
Test name
Test status
Simulation time 2795220499 ps
CPU time 11.62 seconds
Started Apr 15 03:28:37 PM PDT 24
Finished Apr 15 03:28:50 PM PDT 24
Peak memory 220436 kb
Host smart-8a02b505-773f-4112-8700-997552c20212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339063530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3339063530
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.518477880
Short name T119
Test name
Test status
Simulation time 106220732 ps
CPU time 1.15 seconds
Started Apr 15 03:28:42 PM PDT 24
Finished Apr 15 03:28:44 PM PDT 24
Peak memory 222116 kb
Host smart-124c3aa3-e73a-4f77-932f-b631057cf029
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518477880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.518477880
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.1883185504
Short name T1355
Test name
Test status
Simulation time 1790252961 ps
CPU time 4.41 seconds
Started Apr 15 03:28:43 PM PDT 24
Finished Apr 15 03:28:50 PM PDT 24
Peak memory 212184 kb
Host smart-cff27c9b-f919-4ebc-8b76-5f929f10fe8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883185504 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.1883185504
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.2271822364
Short name T617
Test name
Test status
Simulation time 10152584470 ps
CPU time 10.89 seconds
Started Apr 15 03:28:43 PM PDT 24
Finished Apr 15 03:28:55 PM PDT 24
Peak memory 247292 kb
Host smart-a2c2933b-f7f4-48fa-8adb-0b439ff9daa2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271822364 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.2271822364
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.435430560
Short name T509
Test name
Test status
Simulation time 10208259262 ps
CPU time 10.37 seconds
Started Apr 15 03:28:42 PM PDT 24
Finished Apr 15 03:28:53 PM PDT 24
Peak memory 279108 kb
Host smart-4c18f544-f8f4-468b-8009-ed8adc617169
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435430560 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_fifo_reset_tx.435430560
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.147494528
Short name T1062
Test name
Test status
Simulation time 2082806535 ps
CPU time 3.02 seconds
Started Apr 15 03:28:42 PM PDT 24
Finished Apr 15 03:28:47 PM PDT 24
Peak memory 204200 kb
Host smart-b61ef5d9-bafc-4992-8d2e-ce5fcd0ac0e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147494528 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.i2c_target_hrst.147494528
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.4265808054
Short name T982
Test name
Test status
Simulation time 5451751365 ps
CPU time 7.14 seconds
Started Apr 15 03:28:40 PM PDT 24
Finished Apr 15 03:28:48 PM PDT 24
Peak memory 218988 kb
Host smart-417b7000-9aa7-41dd-adfb-36bba863e68d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265808054 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.4265808054
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.3515548712
Short name T294
Test name
Test status
Simulation time 15520296122 ps
CPU time 181.23 seconds
Started Apr 15 03:28:43 PM PDT 24
Finished Apr 15 03:31:46 PM PDT 24
Peak memory 2304092 kb
Host smart-b8c9eef5-7309-4fe1-9b75-d167997c5b5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515548712 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.3515548712
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.857623634
Short name T521
Test name
Test status
Simulation time 716120782 ps
CPU time 25.55 seconds
Started Apr 15 03:28:43 PM PDT 24
Finished Apr 15 03:29:10 PM PDT 24
Peak memory 203972 kb
Host smart-e7ff4a80-f24b-4b6c-a512-3c192d805cd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857623634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_targ
et_smoke.857623634
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.456023309
Short name T767
Test name
Test status
Simulation time 1167174428 ps
CPU time 6.87 seconds
Started Apr 15 03:28:41 PM PDT 24
Finished Apr 15 03:28:48 PM PDT 24
Peak memory 204044 kb
Host smart-fca0a2d6-86d1-4861-aecd-67c19405c883
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456023309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_rd.456023309
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.3917520194
Short name T459
Test name
Test status
Simulation time 14796530939 ps
CPU time 20.13 seconds
Started Apr 15 03:28:37 PM PDT 24
Finished Apr 15 03:28:58 PM PDT 24
Peak memory 204004 kb
Host smart-88731213-3ad8-441d-8fba-647a2aa07862
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917520194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.3917520194
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.209742232
Short name T737
Test name
Test status
Simulation time 33472275656 ps
CPU time 2714.02 seconds
Started Apr 15 03:28:42 PM PDT 24
Finished Apr 15 04:13:58 PM PDT 24
Peak memory 7401716 kb
Host smart-5b817f10-de30-4e5e-8ee6-f01b30317e30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209742232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_ta
rget_stretch.209742232
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.2237334255
Short name T960
Test name
Test status
Simulation time 1175013691 ps
CPU time 5.83 seconds
Started Apr 15 03:28:41 PM PDT 24
Finished Apr 15 03:28:48 PM PDT 24
Peak memory 212224 kb
Host smart-164c3adc-0386-4c32-ab22-7e771d7e7949
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237334255 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.2237334255
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_unexp_stop.4045846535
Short name T738
Test name
Test status
Simulation time 3123110082 ps
CPU time 4.31 seconds
Started Apr 15 03:28:42 PM PDT 24
Finished Apr 15 03:28:47 PM PDT 24
Peak memory 204056 kb
Host smart-08bcb02a-ce5b-41d4-a732-8b1a7bec2d77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045846535 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.i2c_target_unexp_stop.4045846535
Directory /workspace/2.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1152249525
Short name T291
Test name
Test status
Simulation time 40928543 ps
CPU time 0.6 seconds
Started Apr 15 03:31:02 PM PDT 24
Finished Apr 15 03:31:03 PM PDT 24
Peak memory 203568 kb
Host smart-7208f900-dbfa-4dac-be56-9dda488a6f28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152249525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1152249525
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.2014997611
Short name T1004
Test name
Test status
Simulation time 259759887 ps
CPU time 1.17 seconds
Started Apr 15 03:30:48 PM PDT 24
Finished Apr 15 03:30:50 PM PDT 24
Peak memory 212268 kb
Host smart-8d428780-a5a1-43dc-a1d9-e75c8edfe007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014997611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.2014997611
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.906464752
Short name T787
Test name
Test status
Simulation time 1565694156 ps
CPU time 5.13 seconds
Started Apr 15 03:30:51 PM PDT 24
Finished Apr 15 03:30:56 PM PDT 24
Peak memory 257840 kb
Host smart-1711e9d7-9950-42b8-8a76-1ac89c56ede8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906464752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empt
y.906464752
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.1580705474
Short name T370
Test name
Test status
Simulation time 1637384616 ps
CPU time 49.08 seconds
Started Apr 15 03:30:50 PM PDT 24
Finished Apr 15 03:31:39 PM PDT 24
Peak memory 608344 kb
Host smart-0705963e-157a-49ee-939c-4f52a26c0d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580705474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.1580705474
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.202758214
Short name T466
Test name
Test status
Simulation time 1791088361 ps
CPU time 60.65 seconds
Started Apr 15 03:30:51 PM PDT 24
Finished Apr 15 03:31:53 PM PDT 24
Peak memory 628848 kb
Host smart-437b3d68-09d6-441f-bf29-39f944662c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202758214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.202758214
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.3108835307
Short name T1312
Test name
Test status
Simulation time 514078685 ps
CPU time 1.02 seconds
Started Apr 15 03:30:46 PM PDT 24
Finished Apr 15 03:30:47 PM PDT 24
Peak memory 203708 kb
Host smart-25a37be6-577c-42de-aa34-45f5e8d2b5bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108835307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.3108835307
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.201289302
Short name T682
Test name
Test status
Simulation time 1496696847 ps
CPU time 6.59 seconds
Started Apr 15 03:30:51 PM PDT 24
Finished Apr 15 03:30:58 PM PDT 24
Peak memory 203896 kb
Host smart-1473682b-288d-44d4-981f-5b3631ec8a31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201289302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.
201289302
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.1525421987
Short name T183
Test name
Test status
Simulation time 26041029628 ps
CPU time 96.47 seconds
Started Apr 15 03:30:45 PM PDT 24
Finished Apr 15 03:32:23 PM PDT 24
Peak memory 1036756 kb
Host smart-2cb887d6-2d35-4bbb-916d-2ec6fe0bc1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525421987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.1525421987
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.4096860111
Short name T1083
Test name
Test status
Simulation time 406321887 ps
CPU time 15.88 seconds
Started Apr 15 03:31:01 PM PDT 24
Finished Apr 15 03:31:17 PM PDT 24
Peak memory 203928 kb
Host smart-2e05c402-5247-456d-be14-03a819296d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096860111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.4096860111
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.662690356
Short name T372
Test name
Test status
Simulation time 13324698537 ps
CPU time 17.56 seconds
Started Apr 15 03:30:56 PM PDT 24
Finished Apr 15 03:31:14 PM PDT 24
Peak memory 341132 kb
Host smart-9307bddd-40dc-4253-862b-36a35a65dc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662690356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.662690356
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.488867221
Short name T103
Test name
Test status
Simulation time 30687779 ps
CPU time 0.71 seconds
Started Apr 15 03:30:47 PM PDT 24
Finished Apr 15 03:30:48 PM PDT 24
Peak memory 203680 kb
Host smart-9b6a44ba-ecac-4d2d-9fa5-e294aba9acad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488867221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.488867221
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.1046686562
Short name T794
Test name
Test status
Simulation time 2930827993 ps
CPU time 82.35 seconds
Started Apr 15 03:30:50 PM PDT 24
Finished Apr 15 03:32:13 PM PDT 24
Peak memory 495056 kb
Host smart-05cba969-34e8-43ea-b2d5-90060df6f0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046686562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.1046686562
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.4115482068
Short name T1058
Test name
Test status
Simulation time 1710501195 ps
CPU time 84.17 seconds
Started Apr 15 03:30:49 PM PDT 24
Finished Apr 15 03:32:13 PM PDT 24
Peak memory 346004 kb
Host smart-1e066f95-0232-4fe6-ab5d-428c9e6bb487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115482068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.4115482068
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.4285426041
Short name T770
Test name
Test status
Simulation time 8814028521 ps
CPU time 273.9 seconds
Started Apr 15 03:30:51 PM PDT 24
Finished Apr 15 03:35:26 PM PDT 24
Peak memory 797196 kb
Host smart-8d93966e-cec9-45c1-993b-349964446f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285426041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.4285426041
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.2191626649
Short name T646
Test name
Test status
Simulation time 714331053 ps
CPU time 11.71 seconds
Started Apr 15 03:30:49 PM PDT 24
Finished Apr 15 03:31:01 PM PDT 24
Peak memory 220172 kb
Host smart-89789b12-25ee-4097-a99b-ff7fc78d8e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191626649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.2191626649
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.4238737069
Short name T869
Test name
Test status
Simulation time 656551642 ps
CPU time 2.75 seconds
Started Apr 15 03:30:55 PM PDT 24
Finished Apr 15 03:30:58 PM PDT 24
Peak memory 204040 kb
Host smart-4a5ee9c1-d1c6-4721-8eb8-c4310d3ca076
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238737069 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.4238737069
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.2930783075
Short name T402
Test name
Test status
Simulation time 10045123385 ps
CPU time 62.58 seconds
Started Apr 15 03:30:52 PM PDT 24
Finished Apr 15 03:31:55 PM PDT 24
Peak memory 516504 kb
Host smart-c2418597-8db1-4836-913a-6221772e3fbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930783075 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.2930783075
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.2902249827
Short name T1290
Test name
Test status
Simulation time 10266462903 ps
CPU time 11.38 seconds
Started Apr 15 03:30:53 PM PDT 24
Finished Apr 15 03:31:05 PM PDT 24
Peak memory 280328 kb
Host smart-4e70d6f1-e969-455b-b349-1e1abd0913b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902249827 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.2902249827
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.2190327378
Short name T577
Test name
Test status
Simulation time 823346802 ps
CPU time 2.46 seconds
Started Apr 15 03:30:56 PM PDT 24
Finished Apr 15 03:30:59 PM PDT 24
Peak memory 203920 kb
Host smart-1bfe1ff9-8069-49e5-8e60-9a0d6796eef0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190327378 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.2190327378
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.2640258280
Short name T963
Test name
Test status
Simulation time 16800339819 ps
CPU time 6.8 seconds
Started Apr 15 03:30:53 PM PDT 24
Finished Apr 15 03:31:00 PM PDT 24
Peak memory 216180 kb
Host smart-f4e1dbc3-0682-45cf-aa32-045372b40541
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640258280 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.2640258280
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.4146759696
Short name T275
Test name
Test status
Simulation time 20912963259 ps
CPU time 320.07 seconds
Started Apr 15 03:30:55 PM PDT 24
Finished Apr 15 03:36:15 PM PDT 24
Peak memory 3282212 kb
Host smart-5da8aa11-be0f-450f-8dc8-bf15dbc990c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146759696 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.4146759696
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.3810094638
Short name T855
Test name
Test status
Simulation time 938686453 ps
CPU time 29.63 seconds
Started Apr 15 03:30:49 PM PDT 24
Finished Apr 15 03:31:19 PM PDT 24
Peak memory 204040 kb
Host smart-5f086e47-2c90-4974-b0a2-3992bef53ab7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810094638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.3810094638
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.2024529508
Short name T106
Test name
Test status
Simulation time 1134040548 ps
CPU time 10.27 seconds
Started Apr 15 03:31:01 PM PDT 24
Finished Apr 15 03:31:11 PM PDT 24
Peak memory 207220 kb
Host smart-befa8bb6-b157-4aa5-bd56-6e0964d2e151
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024529508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.2024529508
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.2012142053
Short name T1097
Test name
Test status
Simulation time 59451028693 ps
CPU time 1967.51 seconds
Started Apr 15 03:30:51 PM PDT 24
Finished Apr 15 04:03:40 PM PDT 24
Peak memory 9969528 kb
Host smart-c0fec32e-4263-40e8-921e-dfd8e04d1619
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012142053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.2012142053
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.2625850300
Short name T1078
Test name
Test status
Simulation time 19169111685 ps
CPU time 108.39 seconds
Started Apr 15 03:30:51 PM PDT 24
Finished Apr 15 03:32:40 PM PDT 24
Peak memory 1145576 kb
Host smart-a277f8fe-3815-4a64-ad6d-e5f2fbd520f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625850300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.2625850300
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.2875256014
Short name T1209
Test name
Test status
Simulation time 1124886133 ps
CPU time 6.16 seconds
Started Apr 15 03:31:00 PM PDT 24
Finished Apr 15 03:31:07 PM PDT 24
Peak memory 212220 kb
Host smart-5f825602-a4cd-44df-8d74-ff5ef7402474
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875256014 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.2875256014
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.347278714
Short name T279
Test name
Test status
Simulation time 20685574 ps
CPU time 0.62 seconds
Started Apr 15 03:31:05 PM PDT 24
Finished Apr 15 03:31:06 PM PDT 24
Peak memory 203616 kb
Host smart-5a7f1121-12e6-4aab-96a3-c48422889739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347278714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.347278714
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.1115713204
Short name T958
Test name
Test status
Simulation time 168377223 ps
CPU time 1.46 seconds
Started Apr 15 03:30:59 PM PDT 24
Finished Apr 15 03:31:01 PM PDT 24
Peak memory 212268 kb
Host smart-ce8367ab-bc03-4fa7-90fc-f0bd5d190e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115713204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.1115713204
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.3191138888
Short name T395
Test name
Test status
Simulation time 384910214 ps
CPU time 18.9 seconds
Started Apr 15 03:31:00 PM PDT 24
Finished Apr 15 03:31:20 PM PDT 24
Peak memory 283764 kb
Host smart-652d79be-7f61-446d-9088-20eb979dfddb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191138888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.3191138888
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.4152630857
Short name T1295
Test name
Test status
Simulation time 1693900828 ps
CPU time 113.83 seconds
Started Apr 15 03:31:02 PM PDT 24
Finished Apr 15 03:32:57 PM PDT 24
Peak memory 559332 kb
Host smart-10099269-8621-43cb-9078-c9a7dda2f69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152630857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.4152630857
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.4144826824
Short name T569
Test name
Test status
Simulation time 1643724377 ps
CPU time 50 seconds
Started Apr 15 03:30:55 PM PDT 24
Finished Apr 15 03:31:45 PM PDT 24
Peak memory 566636 kb
Host smart-460cdd9a-a805-4017-99df-34531e64431d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144826824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.4144826824
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.377198227
Short name T1260
Test name
Test status
Simulation time 88554814 ps
CPU time 0.88 seconds
Started Apr 15 03:30:54 PM PDT 24
Finished Apr 15 03:30:56 PM PDT 24
Peak memory 203724 kb
Host smart-2fe5a2da-ff6e-47ab-a3d9-08d2d117f46b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377198227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fm
t.377198227
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.964764005
Short name T70
Test name
Test status
Simulation time 132396818 ps
CPU time 6.82 seconds
Started Apr 15 03:31:06 PM PDT 24
Finished Apr 15 03:31:13 PM PDT 24
Peak memory 223736 kb
Host smart-c698557c-54b8-4cc6-819d-31a9caf7e0c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964764005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.
964764005
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2533825658
Short name T256
Test name
Test status
Simulation time 15231183282 ps
CPU time 299.67 seconds
Started Apr 15 03:30:56 PM PDT 24
Finished Apr 15 03:35:56 PM PDT 24
Peak memory 1114596 kb
Host smart-32a106c5-27cc-43ee-b529-c486365f45da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533825658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2533825658
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.201681539
Short name T1246
Test name
Test status
Simulation time 1397779826 ps
CPU time 4.2 seconds
Started Apr 15 03:31:05 PM PDT 24
Finished Apr 15 03:31:09 PM PDT 24
Peak memory 204000 kb
Host smart-366d3354-e895-4677-b5fe-141764a210ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201681539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.201681539
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.1795886881
Short name T91
Test name
Test status
Simulation time 5295949815 ps
CPU time 57.36 seconds
Started Apr 15 03:31:02 PM PDT 24
Finished Apr 15 03:32:00 PM PDT 24
Peak memory 318448 kb
Host smart-597e26e5-7de4-4fd9-b766-702ad3468af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795886881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.1795886881
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.3332088805
Short name T515
Test name
Test status
Simulation time 89136285 ps
CPU time 0.65 seconds
Started Apr 15 03:30:56 PM PDT 24
Finished Apr 15 03:30:57 PM PDT 24
Peak memory 203532 kb
Host smart-870b55ef-2cf6-4a2d-a995-9ae01d697a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332088805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.3332088805
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.2193250774
Short name T471
Test name
Test status
Simulation time 7080098589 ps
CPU time 48.26 seconds
Started Apr 15 03:31:04 PM PDT 24
Finished Apr 15 03:31:53 PM PDT 24
Peak memory 204016 kb
Host smart-9f74990f-f0eb-458c-985f-989063256d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193250774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2193250774
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.3361899482
Short name T932
Test name
Test status
Simulation time 6338890128 ps
CPU time 31.75 seconds
Started Apr 15 03:31:00 PM PDT 24
Finished Apr 15 03:31:33 PM PDT 24
Peak memory 382636 kb
Host smart-33f4777f-8cf8-4a91-9c4d-6fc4eb64a613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361899482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.3361899482
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.2734372937
Short name T1286
Test name
Test status
Simulation time 5267317984 ps
CPU time 408.22 seconds
Started Apr 15 03:31:06 PM PDT 24
Finished Apr 15 03:37:55 PM PDT 24
Peak memory 954480 kb
Host smart-3e3dd2a7-b6d4-4314-86e2-7ae9b762e1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734372937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.2734372937
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.4159527390
Short name T350
Test name
Test status
Simulation time 3168658625 ps
CPU time 13.67 seconds
Started Apr 15 03:31:05 PM PDT 24
Finished Apr 15 03:31:19 PM PDT 24
Peak memory 220484 kb
Host smart-f9992bd4-f0a0-47ea-b4f9-3d2ce11e5bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159527390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.4159527390
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.1322740215
Short name T695
Test name
Test status
Simulation time 1416926191 ps
CPU time 3.23 seconds
Started Apr 15 03:31:06 PM PDT 24
Finished Apr 15 03:31:10 PM PDT 24
Peak memory 203984 kb
Host smart-9a3dc445-b30a-4f26-8d48-f19286b5d942
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322740215 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.1322740215
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.2630174774
Short name T475
Test name
Test status
Simulation time 10455660897 ps
CPU time 11.27 seconds
Started Apr 15 03:31:07 PM PDT 24
Finished Apr 15 03:31:19 PM PDT 24
Peak memory 255200 kb
Host smart-027306ba-648f-4726-8b2c-4037543d86d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630174774 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.2630174774
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.539746089
Short name T797
Test name
Test status
Simulation time 10362406285 ps
CPU time 6.71 seconds
Started Apr 15 03:31:04 PM PDT 24
Finished Apr 15 03:31:11 PM PDT 24
Peak memory 257532 kb
Host smart-6d894485-4c03-4e9d-a685-9f4cccfc50e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539746089 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_fifo_reset_tx.539746089
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.3371548069
Short name T644
Test name
Test status
Simulation time 356867510 ps
CPU time 2.06 seconds
Started Apr 15 03:31:06 PM PDT 24
Finished Apr 15 03:31:09 PM PDT 24
Peak memory 204028 kb
Host smart-fbbb0f8a-d977-43e9-808d-fe5c40573aff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371548069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.3371548069
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.2673082251
Short name T1303
Test name
Test status
Simulation time 1611393014 ps
CPU time 4.02 seconds
Started Apr 15 03:31:00 PM PDT 24
Finished Apr 15 03:31:05 PM PDT 24
Peak memory 203956 kb
Host smart-c8f8e1e8-7202-4810-8b9f-132f95277b53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673082251 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.2673082251
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.2703368442
Short name T1275
Test name
Test status
Simulation time 14278039857 ps
CPU time 13.35 seconds
Started Apr 15 03:31:05 PM PDT 24
Finished Apr 15 03:31:19 PM PDT 24
Peak memory 366064 kb
Host smart-d5b44172-e6be-423f-b959-6f2694c534b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703368442 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.2703368442
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.1937618784
Short name T727
Test name
Test status
Simulation time 1300384335 ps
CPU time 21.14 seconds
Started Apr 15 03:31:06 PM PDT 24
Finished Apr 15 03:31:28 PM PDT 24
Peak memory 204128 kb
Host smart-6a192841-d7b4-4c71-b0f5-82b075ed0da8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937618784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.1937618784
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.1641024529
Short name T911
Test name
Test status
Simulation time 7159952529 ps
CPU time 26.8 seconds
Started Apr 15 03:31:04 PM PDT 24
Finished Apr 15 03:31:32 PM PDT 24
Peak memory 232996 kb
Host smart-8aa8c0cd-5de1-4cc5-9c30-8c90af18e133
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641024529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.1641024529
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.3284431295
Short name T1135
Test name
Test status
Simulation time 40685889645 ps
CPU time 89.26 seconds
Started Apr 15 03:31:02 PM PDT 24
Finished Apr 15 03:32:32 PM PDT 24
Peak memory 1324536 kb
Host smart-e4178290-c81d-40d0-8494-a9eec1a482f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284431295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.3284431295
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.624583684
Short name T514
Test name
Test status
Simulation time 5772089440 ps
CPU time 125.3 seconds
Started Apr 15 03:31:04 PM PDT 24
Finished Apr 15 03:33:10 PM PDT 24
Peak memory 1407616 kb
Host smart-442c1d3a-8806-40d8-8e9d-3c11635fa7fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624583684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_t
arget_stretch.624583684
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2273854207
Short name T1356
Test name
Test status
Simulation time 1599174306 ps
CPU time 6.67 seconds
Started Apr 15 03:31:01 PM PDT 24
Finished Apr 15 03:31:08 PM PDT 24
Peak memory 209232 kb
Host smart-75ea81af-7d64-4eee-a9e8-f113d98dab8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273854207 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2273854207
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1936453674
Short name T895
Test name
Test status
Simulation time 26742204 ps
CPU time 0.62 seconds
Started Apr 15 03:31:16 PM PDT 24
Finished Apr 15 03:31:17 PM PDT 24
Peak memory 203620 kb
Host smart-69370878-a993-4c42-acf0-b5866a73f1a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936453674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1936453674
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.1373476768
Short name T949
Test name
Test status
Simulation time 409686682 ps
CPU time 1.51 seconds
Started Apr 15 03:31:08 PM PDT 24
Finished Apr 15 03:31:10 PM PDT 24
Peak memory 212280 kb
Host smart-7bde7c8a-f604-4075-8d68-7f29e36c0aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373476768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.1373476768
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1643869155
Short name T1327
Test name
Test status
Simulation time 608730704 ps
CPU time 5.95 seconds
Started Apr 15 03:31:14 PM PDT 24
Finished Apr 15 03:31:21 PM PDT 24
Peak memory 269420 kb
Host smart-6a65703f-84ba-48b6-bd40-7642a2d1e126
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643869155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1643869155
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.3614037262
Short name T533
Test name
Test status
Simulation time 1187095907 ps
CPU time 39.2 seconds
Started Apr 15 03:31:07 PM PDT 24
Finished Apr 15 03:31:47 PM PDT 24
Peak memory 495868 kb
Host smart-ae52f506-077d-4f1b-acc4-9746a59c3b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614037262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.3614037262
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.755590411
Short name T1339
Test name
Test status
Simulation time 7884083306 ps
CPU time 40.11 seconds
Started Apr 15 03:31:04 PM PDT 24
Finished Apr 15 03:31:45 PM PDT 24
Peak memory 511004 kb
Host smart-5b7de61b-ca94-4629-89d9-b34056722304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755590411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.755590411
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2783883246
Short name T1010
Test name
Test status
Simulation time 474289793 ps
CPU time 0.99 seconds
Started Apr 15 03:31:07 PM PDT 24
Finished Apr 15 03:31:09 PM PDT 24
Peak memory 202984 kb
Host smart-ff13e7c7-83ad-43f9-8b29-c5aef6b4d7e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783883246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.2783883246
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.4262353977
Short name T1002
Test name
Test status
Simulation time 572328896 ps
CPU time 4.26 seconds
Started Apr 15 03:31:10 PM PDT 24
Finished Apr 15 03:31:15 PM PDT 24
Peak memory 228312 kb
Host smart-0cb71abb-c36d-4d45-83dd-820b3a5f7ff2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262353977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.4262353977
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.2810808574
Short name T518
Test name
Test status
Simulation time 315301659 ps
CPU time 11.79 seconds
Started Apr 15 03:31:18 PM PDT 24
Finished Apr 15 03:31:31 PM PDT 24
Peak memory 203928 kb
Host smart-aae31b27-065c-4308-b5fb-4bca9ba51338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810808574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.2810808574
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.4180627656
Short name T75
Test name
Test status
Simulation time 1743451132 ps
CPU time 86.55 seconds
Started Apr 15 03:31:15 PM PDT 24
Finished Apr 15 03:32:42 PM PDT 24
Peak memory 362136 kb
Host smart-43ba978d-78a5-4b0c-b555-ef26fef6e2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180627656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.4180627656
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.2509186014
Short name T417
Test name
Test status
Simulation time 37809998 ps
CPU time 0.69 seconds
Started Apr 15 03:31:05 PM PDT 24
Finished Apr 15 03:31:06 PM PDT 24
Peak memory 203660 kb
Host smart-9a89b8a1-7c73-4d4d-b525-845f4e8677a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509186014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2509186014
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.3497720586
Short name T316
Test name
Test status
Simulation time 18435776960 ps
CPU time 687.8 seconds
Started Apr 15 03:31:13 PM PDT 24
Finished Apr 15 03:42:42 PM PDT 24
Peak memory 993324 kb
Host smart-955c789c-d380-4ed0-bc56-3239706992be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497720586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.3497720586
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.3343580208
Short name T1056
Test name
Test status
Simulation time 1567944277 ps
CPU time 75.84 seconds
Started Apr 15 03:31:06 PM PDT 24
Finished Apr 15 03:32:23 PM PDT 24
Peak memory 324888 kb
Host smart-4cccb97b-62da-4d81-899b-79ce266ea344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343580208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.3343580208
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.3855341428
Short name T526
Test name
Test status
Simulation time 4561363968 ps
CPU time 110.85 seconds
Started Apr 15 03:31:09 PM PDT 24
Finished Apr 15 03:33:01 PM PDT 24
Peak memory 698340 kb
Host smart-f7d87aae-a044-4825-a801-fa850acbb6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855341428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.3855341428
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.3278857439
Short name T880
Test name
Test status
Simulation time 4238467239 ps
CPU time 23.31 seconds
Started Apr 15 03:31:06 PM PDT 24
Finished Apr 15 03:31:30 PM PDT 24
Peak memory 212208 kb
Host smart-2cb82b75-b13f-47bb-8cc8-66b0c2976c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278857439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.3278857439
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.3738855602
Short name T20
Test name
Test status
Simulation time 558446234 ps
CPU time 3 seconds
Started Apr 15 03:31:17 PM PDT 24
Finished Apr 15 03:31:20 PM PDT 24
Peak memory 204036 kb
Host smart-1a3472d1-05dc-4061-8d63-9ca523649768
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738855602 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.3738855602
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.4243031624
Short name T842
Test name
Test status
Simulation time 10069154047 ps
CPU time 70.96 seconds
Started Apr 15 03:31:13 PM PDT 24
Finished Apr 15 03:32:24 PM PDT 24
Peak memory 502336 kb
Host smart-a2e7660a-85ee-4155-86f9-248c54853faa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243031624 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.4243031624
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.2438127078
Short name T549
Test name
Test status
Simulation time 10104175411 ps
CPU time 12.03 seconds
Started Apr 15 03:31:09 PM PDT 24
Finished Apr 15 03:31:22 PM PDT 24
Peak memory 282588 kb
Host smart-f47ed79e-9a39-4d4d-abe7-3679bb6f4617
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438127078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.2438127078
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.1445607182
Short name T1350
Test name
Test status
Simulation time 313040368 ps
CPU time 2.16 seconds
Started Apr 15 03:31:14 PM PDT 24
Finished Apr 15 03:31:17 PM PDT 24
Peak memory 204028 kb
Host smart-e2203a80-77ce-47f0-b965-46a5b263f54f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445607182 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.1445607182
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.3642652266
Short name T1093
Test name
Test status
Simulation time 1552426583 ps
CPU time 7 seconds
Started Apr 15 03:31:07 PM PDT 24
Finished Apr 15 03:31:15 PM PDT 24
Peak memory 216260 kb
Host smart-6fe130fb-8d49-41f3-87f7-cd611b762890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642652266 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.3642652266
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.381781911
Short name T885
Test name
Test status
Simulation time 13842218686 ps
CPU time 117.46 seconds
Started Apr 15 03:31:10 PM PDT 24
Finished Apr 15 03:33:09 PM PDT 24
Peak memory 1769400 kb
Host smart-7ab2fdd4-f2fb-4749-a771-23af077ebe55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381781911 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.381781911
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.3107506908
Short name T1332
Test name
Test status
Simulation time 8283341467 ps
CPU time 11.98 seconds
Started Apr 15 03:31:14 PM PDT 24
Finished Apr 15 03:31:27 PM PDT 24
Peak memory 204060 kb
Host smart-f6cf184d-bef4-4b83-93f1-d2080dd5e20f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107506908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.3107506908
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.267428358
Short name T489
Test name
Test status
Simulation time 654880668 ps
CPU time 13.49 seconds
Started Apr 15 03:31:15 PM PDT 24
Finished Apr 15 03:31:29 PM PDT 24
Peak memory 204036 kb
Host smart-a9d94d90-431a-4fb0-908f-46f7efc9ddaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267428358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_rd.267428358
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.527076547
Short name T440
Test name
Test status
Simulation time 16938958148 ps
CPU time 34.11 seconds
Started Apr 15 03:31:07 PM PDT 24
Finished Apr 15 03:31:41 PM PDT 24
Peak memory 204028 kb
Host smart-56ba2a5a-1b12-4c95-8fb8-27c1ad934223
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527076547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_wr.527076547
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.2071736617
Short name T671
Test name
Test status
Simulation time 1468563089 ps
CPU time 6.99 seconds
Started Apr 15 03:31:12 PM PDT 24
Finished Apr 15 03:31:19 PM PDT 24
Peak memory 212152 kb
Host smart-68c4ebfc-f873-46ca-ae9b-1c0d6433b8d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071736617 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.2071736617
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_unexp_stop.873257687
Short name T1128
Test name
Test status
Simulation time 24660522406 ps
CPU time 6.91 seconds
Started Apr 15 03:31:13 PM PDT 24
Finished Apr 15 03:31:20 PM PDT 24
Peak memory 219908 kb
Host smart-a093829f-a90a-40eb-b2ed-e93a9df329e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873257687 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_unexp_stop.873257687
Directory /workspace/22.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/23.i2c_alert_test.1870595898
Short name T974
Test name
Test status
Simulation time 41653720 ps
CPU time 0.65 seconds
Started Apr 15 03:31:24 PM PDT 24
Finished Apr 15 03:31:25 PM PDT 24
Peak memory 203560 kb
Host smart-bc6d9e9a-a400-4ce3-9c80-ec8de65b181e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870595898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.1870595898
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.1873075518
Short name T860
Test name
Test status
Simulation time 214962079 ps
CPU time 1.16 seconds
Started Apr 15 03:31:16 PM PDT 24
Finished Apr 15 03:31:18 PM PDT 24
Peak memory 204004 kb
Host smart-19e6e0ac-57bd-4ac3-a772-10c12720a60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873075518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.1873075518
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.893064281
Short name T1077
Test name
Test status
Simulation time 158228357 ps
CPU time 3.63 seconds
Started Apr 15 03:31:16 PM PDT 24
Finished Apr 15 03:31:21 PM PDT 24
Peak memory 230248 kb
Host smart-f82e2691-b302-4b80-b2f5-fd7b0e86280d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893064281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empt
y.893064281
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.1300628273
Short name T710
Test name
Test status
Simulation time 7176650869 ps
CPU time 63.99 seconds
Started Apr 15 03:31:18 PM PDT 24
Finished Apr 15 03:32:23 PM PDT 24
Peak memory 700472 kb
Host smart-3eb714fc-4155-4b08-be46-a4a94112e008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300628273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1300628273
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.2550703168
Short name T734
Test name
Test status
Simulation time 23912622862 ps
CPU time 67.38 seconds
Started Apr 15 03:31:14 PM PDT 24
Finished Apr 15 03:32:22 PM PDT 24
Peak memory 740076 kb
Host smart-539146f8-23c4-423f-96d0-18a3e9999edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550703168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.2550703168
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3858611093
Short name T839
Test name
Test status
Simulation time 316109282 ps
CPU time 1.18 seconds
Started Apr 15 03:31:17 PM PDT 24
Finished Apr 15 03:31:19 PM PDT 24
Peak memory 203884 kb
Host smart-8667d67d-343b-423f-845c-129f4bf2da55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858611093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.3858611093
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1519241881
Short name T875
Test name
Test status
Simulation time 192693749 ps
CPU time 4.35 seconds
Started Apr 15 03:31:15 PM PDT 24
Finished Apr 15 03:31:20 PM PDT 24
Peak memory 203952 kb
Host smart-a514f6c6-0622-4dbd-9c6c-91fcd7a11869
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519241881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.1519241881
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.2883090892
Short name T1051
Test name
Test status
Simulation time 4912585437 ps
CPU time 54.41 seconds
Started Apr 15 03:31:17 PM PDT 24
Finished Apr 15 03:32:12 PM PDT 24
Peak memory 813360 kb
Host smart-6b5fc555-82d3-482c-8d94-f8ba2380b47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883090892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.2883090892
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.4177135303
Short name T625
Test name
Test status
Simulation time 301847610 ps
CPU time 12.04 seconds
Started Apr 15 03:31:20 PM PDT 24
Finished Apr 15 03:31:33 PM PDT 24
Peak memory 203984 kb
Host smart-8b4a37d4-381d-411d-9b05-3054792c58f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177135303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.4177135303
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.579880541
Short name T838
Test name
Test status
Simulation time 4264185010 ps
CPU time 16.57 seconds
Started Apr 15 03:31:26 PM PDT 24
Finished Apr 15 03:31:43 PM PDT 24
Peak memory 309812 kb
Host smart-ba0c109d-2072-4a3c-8f9b-24f14f2d22af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579880541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.579880541
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.1196916302
Short name T332
Test name
Test status
Simulation time 48492320 ps
CPU time 0.65 seconds
Started Apr 15 03:31:16 PM PDT 24
Finished Apr 15 03:31:17 PM PDT 24
Peak memory 203664 kb
Host smart-e66d4e4c-52cc-4648-83ae-2cae122c215f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196916302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1196916302
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.1967148105
Short name T80
Test name
Test status
Simulation time 23995067609 ps
CPU time 166.89 seconds
Started Apr 15 03:31:19 PM PDT 24
Finished Apr 15 03:34:06 PM PDT 24
Peak memory 220244 kb
Host smart-9155d7a9-e8dd-4e6e-8042-c5609308e54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967148105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.1967148105
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3503295284
Short name T563
Test name
Test status
Simulation time 4370988275 ps
CPU time 24.78 seconds
Started Apr 15 03:31:17 PM PDT 24
Finished Apr 15 03:31:43 PM PDT 24
Peak memory 314764 kb
Host smart-cb5bd639-36e9-406d-a638-248b62f97e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503295284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3503295284
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.1601258158
Short name T559
Test name
Test status
Simulation time 38439368090 ps
CPU time 380.65 seconds
Started Apr 15 03:31:18 PM PDT 24
Finished Apr 15 03:37:39 PM PDT 24
Peak memory 1508888 kb
Host smart-3724e4a2-ed58-41c9-8cca-9c55246b9e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601258158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.1601258158
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.4228081020
Short name T310
Test name
Test status
Simulation time 3841511355 ps
CPU time 12.35 seconds
Started Apr 15 03:31:24 PM PDT 24
Finished Apr 15 03:31:37 PM PDT 24
Peak memory 212220 kb
Host smart-e1def9be-03cf-4a60-884d-a2adf868b774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228081020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.4228081020
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.281998597
Short name T1095
Test name
Test status
Simulation time 9343003386 ps
CPU time 3.07 seconds
Started Apr 15 03:31:21 PM PDT 24
Finished Apr 15 03:31:25 PM PDT 24
Peak memory 204020 kb
Host smart-3c9c4658-9bc5-4b6e-b95a-c7a7291abbd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281998597 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.281998597
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2891091194
Short name T964
Test name
Test status
Simulation time 10089676759 ps
CPU time 67.8 seconds
Started Apr 15 03:31:20 PM PDT 24
Finished Apr 15 03:32:29 PM PDT 24
Peak memory 497004 kb
Host smart-3e197f6c-6d20-4ee5-a1b2-d4f86efd5ce1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891091194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2891091194
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.536701830
Short name T642
Test name
Test status
Simulation time 10090732396 ps
CPU time 28.04 seconds
Started Apr 15 03:31:17 PM PDT 24
Finished Apr 15 03:31:46 PM PDT 24
Peak memory 404536 kb
Host smart-5047303f-649f-4830-8ef7-54d28c483317
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536701830 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_fifo_reset_tx.536701830
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.482931901
Short name T127
Test name
Test status
Simulation time 406335674 ps
CPU time 2.25 seconds
Started Apr 15 03:31:22 PM PDT 24
Finished Apr 15 03:31:25 PM PDT 24
Peak memory 204004 kb
Host smart-9791847a-0c33-4afd-b1a0-f51241f490fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482931901 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.i2c_target_hrst.482931901
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.1023122518
Short name T907
Test name
Test status
Simulation time 2366171824 ps
CPU time 6.06 seconds
Started Apr 15 03:31:17 PM PDT 24
Finished Apr 15 03:31:24 PM PDT 24
Peak memory 211332 kb
Host smart-e7af478b-e6aa-423a-a470-ebba140b2a04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023122518 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.1023122518
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.2682221806
Short name T1022
Test name
Test status
Simulation time 19925006269 ps
CPU time 6.48 seconds
Started Apr 15 03:31:16 PM PDT 24
Finished Apr 15 03:31:23 PM PDT 24
Peak memory 204076 kb
Host smart-30a20dfd-4805-4fcc-9f94-2ba98b71894e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682221806 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.2682221806
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.4023872585
Short name T702
Test name
Test status
Simulation time 613986255 ps
CPU time 8.04 seconds
Started Apr 15 03:31:18 PM PDT 24
Finished Apr 15 03:31:27 PM PDT 24
Peak memory 203936 kb
Host smart-aa4e00bf-3b71-42f2-b575-0480b18b951c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023872585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.4023872585
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.1377993845
Short name T1028
Test name
Test status
Simulation time 1253312251 ps
CPU time 21.84 seconds
Started Apr 15 03:31:18 PM PDT 24
Finished Apr 15 03:31:40 PM PDT 24
Peak memory 220752 kb
Host smart-ebc4fd65-8069-42fe-b15e-ef6a60a1c023
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377993845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.1377993845
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.3497395740
Short name T412
Test name
Test status
Simulation time 38350059525 ps
CPU time 54.16 seconds
Started Apr 15 03:31:18 PM PDT 24
Finished Apr 15 03:32:13 PM PDT 24
Peak memory 967832 kb
Host smart-55b6f6cb-f2fb-4d67-9179-f3fc7c22e8fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497395740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.3497395740
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.3400383850
Short name T983
Test name
Test status
Simulation time 22922063750 ps
CPU time 3238.3 seconds
Started Apr 15 03:31:22 PM PDT 24
Finished Apr 15 04:25:21 PM PDT 24
Peak memory 4472696 kb
Host smart-2403645a-1815-4d01-aee3-16437274628b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400383850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.3400383850
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.2313679090
Short name T1296
Test name
Test status
Simulation time 5381257390 ps
CPU time 6.34 seconds
Started Apr 15 03:31:21 PM PDT 24
Finished Apr 15 03:31:28 PM PDT 24
Peak memory 212296 kb
Host smart-97f3950e-142c-42da-aaba-236a77c3667d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313679090 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.2313679090
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.3322113019
Short name T1259
Test name
Test status
Simulation time 25640914 ps
CPU time 0.63 seconds
Started Apr 15 03:31:29 PM PDT 24
Finished Apr 15 03:31:31 PM PDT 24
Peak memory 203600 kb
Host smart-c55b36e0-8d00-43ec-86f2-dd1718325bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322113019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.3322113019
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.3898641830
Short name T739
Test name
Test status
Simulation time 49848165 ps
CPU time 1.27 seconds
Started Apr 15 03:31:27 PM PDT 24
Finished Apr 15 03:31:30 PM PDT 24
Peak memory 204032 kb
Host smart-50f333b3-ddf2-4cfe-98b9-34fea1a75034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898641830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.3898641830
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.2126057564
Short name T1153
Test name
Test status
Simulation time 3946956538 ps
CPU time 14.96 seconds
Started Apr 15 03:31:25 PM PDT 24
Finished Apr 15 03:31:40 PM PDT 24
Peak memory 260360 kb
Host smart-fd40c1b1-5b4a-4120-8ee7-95b90b8d651f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126057564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.2126057564
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2031466906
Short name T578
Test name
Test status
Simulation time 4571315601 ps
CPU time 76.21 seconds
Started Apr 15 03:31:26 PM PDT 24
Finished Apr 15 03:32:43 PM PDT 24
Peak memory 774772 kb
Host smart-15388d70-15b9-4557-9429-14f3f2f8ede3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031466906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2031466906
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.4273067204
Short name T712
Test name
Test status
Simulation time 2816204282 ps
CPU time 41.22 seconds
Started Apr 15 03:31:20 PM PDT 24
Finished Apr 15 03:32:03 PM PDT 24
Peak memory 555020 kb
Host smart-553e4157-d8d9-4789-946b-60c651c9bcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273067204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.4273067204
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.4004096055
Short name T685
Test name
Test status
Simulation time 204248542 ps
CPU time 0.94 seconds
Started Apr 15 03:31:27 PM PDT 24
Finished Apr 15 03:31:29 PM PDT 24
Peak memory 203736 kb
Host smart-765fc020-4e80-4ca2-901f-aef95bcdc93e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004096055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.4004096055
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.613980880
Short name T750
Test name
Test status
Simulation time 234937454 ps
CPU time 7.08 seconds
Started Apr 15 03:31:26 PM PDT 24
Finished Apr 15 03:31:33 PM PDT 24
Peak memory 223724 kb
Host smart-ae6193c5-ee4c-4cb3-b7e2-abdab114c517
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613980880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.
613980880
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1227404196
Short name T456
Test name
Test status
Simulation time 31306880728 ps
CPU time 133.8 seconds
Started Apr 15 03:31:21 PM PDT 24
Finished Apr 15 03:33:36 PM PDT 24
Peak memory 1267880 kb
Host smart-f4dbd1be-6d1f-463c-9f20-323c45445afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227404196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1227404196
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.35045119
Short name T663
Test name
Test status
Simulation time 319176951 ps
CPU time 13.05 seconds
Started Apr 15 03:31:30 PM PDT 24
Finished Apr 15 03:31:44 PM PDT 24
Peak memory 204000 kb
Host smart-7cbe2e12-a857-453e-807b-9a9270383263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35045119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.35045119
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.1255842073
Short name T708
Test name
Test status
Simulation time 2897560537 ps
CPU time 31.83 seconds
Started Apr 15 03:31:27 PM PDT 24
Finished Apr 15 03:32:00 PM PDT 24
Peak memory 336628 kb
Host smart-68b8df04-830a-4b2b-bb77-ee477256b556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255842073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.1255842073
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.1934251709
Short name T1333
Test name
Test status
Simulation time 18247522 ps
CPU time 0.66 seconds
Started Apr 15 03:31:23 PM PDT 24
Finished Apr 15 03:31:24 PM PDT 24
Peak memory 203680 kb
Host smart-4b4ad522-e62f-42e1-be48-6698b744980b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934251709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1934251709
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.1973754789
Short name T1167
Test name
Test status
Simulation time 28300219783 ps
CPU time 606.29 seconds
Started Apr 15 03:31:24 PM PDT 24
Finished Apr 15 03:41:31 PM PDT 24
Peak memory 930160 kb
Host smart-9f46a11a-896d-43a8-97c2-474f6b3012ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973754789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.1973754789
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.3043175197
Short name T927
Test name
Test status
Simulation time 965134544 ps
CPU time 13.48 seconds
Started Apr 15 03:31:21 PM PDT 24
Finished Apr 15 03:31:35 PM PDT 24
Peak memory 262136 kb
Host smart-7ab5aad8-924f-4ad3-b9ed-863c4ce6e604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043175197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.3043175197
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.582845220
Short name T66
Test name
Test status
Simulation time 6735672009 ps
CPU time 315.82 seconds
Started Apr 15 03:31:27 PM PDT 24
Finished Apr 15 03:36:44 PM PDT 24
Peak memory 1596004 kb
Host smart-efd7122c-da8b-4d6a-8775-d13bffb4b09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582845220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.582845220
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.535931307
Short name T257
Test name
Test status
Simulation time 777744578 ps
CPU time 37.72 seconds
Started Apr 15 03:31:27 PM PDT 24
Finished Apr 15 03:32:06 PM PDT 24
Peak memory 213224 kb
Host smart-f15cf0fc-f185-4410-a920-7a79c999d288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535931307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.535931307
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.408369440
Short name T811
Test name
Test status
Simulation time 1279508761 ps
CPU time 4.69 seconds
Started Apr 15 03:31:30 PM PDT 24
Finished Apr 15 03:31:36 PM PDT 24
Peak memory 204060 kb
Host smart-aedf66d2-03fd-4133-9857-4bf5263c5604
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408369440 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.408369440
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.3833401992
Short name T77
Test name
Test status
Simulation time 10136140705 ps
CPU time 61.62 seconds
Started Apr 15 03:31:43 PM PDT 24
Finished Apr 15 03:32:45 PM PDT 24
Peak memory 483356 kb
Host smart-f49c90b0-ace2-4121-bf0b-eb2cd23c772d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833401992 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.3833401992
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.1825311305
Short name T1344
Test name
Test status
Simulation time 10173017387 ps
CPU time 14.34 seconds
Started Apr 15 03:31:29 PM PDT 24
Finished Apr 15 03:31:45 PM PDT 24
Peak memory 287348 kb
Host smart-7748251a-cea9-440b-8e0c-beb2d382a831
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825311305 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.1825311305
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.1696623920
Short name T27
Test name
Test status
Simulation time 1214306360 ps
CPU time 1.76 seconds
Started Apr 15 03:31:30 PM PDT 24
Finished Apr 15 03:31:33 PM PDT 24
Peak memory 203944 kb
Host smart-2395b91a-8432-4713-b5c8-3ad667aea901
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696623920 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.1696623920
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.3549887277
Short name T1121
Test name
Test status
Simulation time 766637751 ps
CPU time 4.18 seconds
Started Apr 15 03:31:43 PM PDT 24
Finished Apr 15 03:31:47 PM PDT 24
Peak memory 204036 kb
Host smart-06fa7cb9-2e08-4959-a70a-140e4eddbc99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549887277 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.3549887277
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.2643754245
Short name T774
Test name
Test status
Simulation time 17247131744 ps
CPU time 34.82 seconds
Started Apr 15 03:31:43 PM PDT 24
Finished Apr 15 03:32:18 PM PDT 24
Peak memory 677148 kb
Host smart-59c2ca20-123c-4ba9-a75d-192b423ece06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643754245 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.2643754245
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.2051365917
Short name T480
Test name
Test status
Simulation time 2727719228 ps
CPU time 9.62 seconds
Started Apr 15 03:31:25 PM PDT 24
Finished Apr 15 03:31:35 PM PDT 24
Peak memory 204072 kb
Host smart-4fe5cfc0-9f85-4288-a88a-40b5b0f9ecef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051365917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.2051365917
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.4211490157
Short name T1015
Test name
Test status
Simulation time 5135392757 ps
CPU time 24.01 seconds
Started Apr 15 03:31:26 PM PDT 24
Finished Apr 15 03:31:51 PM PDT 24
Peak memory 216684 kb
Host smart-2a2776a3-44b1-4f21-9f66-63bccb1a17d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211490157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.4211490157
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.4101990328
Short name T1203
Test name
Test status
Simulation time 15163913985 ps
CPU time 6.83 seconds
Started Apr 15 03:31:26 PM PDT 24
Finished Apr 15 03:31:33 PM PDT 24
Peak memory 204044 kb
Host smart-6f3d5eff-92d0-479a-aa55-172ff36e23c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101990328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.4101990328
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.1943115691
Short name T990
Test name
Test status
Simulation time 4901774217 ps
CPU time 53.47 seconds
Started Apr 15 03:31:29 PM PDT 24
Finished Apr 15 03:32:23 PM PDT 24
Peak memory 693172 kb
Host smart-843c719e-f86f-4835-a1a3-d9703c3da10a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943115691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.1943115691
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.3927503048
Short name T887
Test name
Test status
Simulation time 5509990452 ps
CPU time 6.76 seconds
Started Apr 15 03:31:30 PM PDT 24
Finished Apr 15 03:31:38 PM PDT 24
Peak memory 204100 kb
Host smart-8cff5016-80e9-4870-836a-6f73d0057aa5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927503048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.3927503048
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_unexp_stop.939935605
Short name T968
Test name
Test status
Simulation time 4260357529 ps
CPU time 4.84 seconds
Started Apr 15 03:31:30 PM PDT 24
Finished Apr 15 03:31:36 PM PDT 24
Peak memory 207612 kb
Host smart-4ea46abb-cc81-447e-abbc-d980cb1cd431
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939935605 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_unexp_stop.939935605
Directory /workspace/24.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/25.i2c_alert_test.855936442
Short name T804
Test name
Test status
Simulation time 47028470 ps
CPU time 0.61 seconds
Started Apr 15 03:31:45 PM PDT 24
Finished Apr 15 03:31:47 PM PDT 24
Peak memory 203620 kb
Host smart-8180ff08-a23a-4e62-9596-3195f9b1387a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855936442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.855936442
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.1976057758
Short name T873
Test name
Test status
Simulation time 63135729 ps
CPU time 1.32 seconds
Started Apr 15 03:31:43 PM PDT 24
Finished Apr 15 03:31:45 PM PDT 24
Peak memory 212292 kb
Host smart-a0c0212a-50a9-4e6c-a96f-aea6983e989f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976057758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.1976057758
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.633670457
Short name T741
Test name
Test status
Simulation time 382312860 ps
CPU time 18.54 seconds
Started Apr 15 03:31:35 PM PDT 24
Finished Apr 15 03:31:54 PM PDT 24
Peak memory 277200 kb
Host smart-4c4a6ded-7169-4345-86d3-4a7f64842067
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633670457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empt
y.633670457
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.1907160318
Short name T1041
Test name
Test status
Simulation time 1715084428 ps
CPU time 48.08 seconds
Started Apr 15 03:31:33 PM PDT 24
Finished Apr 15 03:32:22 PM PDT 24
Peak memory 508500 kb
Host smart-2b0261e3-9399-4139-99e4-8817c1bf3bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907160318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.1907160318
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.2687885875
Short name T1217
Test name
Test status
Simulation time 1422861388 ps
CPU time 99.58 seconds
Started Apr 15 03:31:35 PM PDT 24
Finished Apr 15 03:33:15 PM PDT 24
Peak memory 542824 kb
Host smart-4bc6ecb3-2b29-4dc4-adfb-b90cc31d2278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687885875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.2687885875
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.34045721
Short name T1142
Test name
Test status
Simulation time 113697150 ps
CPU time 0.96 seconds
Started Apr 15 03:31:32 PM PDT 24
Finished Apr 15 03:31:34 PM PDT 24
Peak memory 203720 kb
Host smart-305c1e56-e656-4b31-80e6-1da97e637c62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34045721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fmt
.34045721
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.2031136374
Short name T96
Test name
Test status
Simulation time 844810187 ps
CPU time 2.68 seconds
Started Apr 15 03:31:33 PM PDT 24
Finished Apr 15 03:31:36 PM PDT 24
Peak memory 203936 kb
Host smart-a5414496-3f08-458c-a02a-e244d6af794c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031136374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.2031136374
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.1995039417
Short name T180
Test name
Test status
Simulation time 3448355075 ps
CPU time 81.99 seconds
Started Apr 15 03:31:31 PM PDT 24
Finished Apr 15 03:32:54 PM PDT 24
Peak memory 1033552 kb
Host smart-2a666baa-c9ea-408f-aa65-b2d589e91f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995039417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.1995039417
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.652579421
Short name T488
Test name
Test status
Simulation time 234902555 ps
CPU time 3.83 seconds
Started Apr 15 03:31:44 PM PDT 24
Finished Apr 15 03:31:48 PM PDT 24
Peak memory 203928 kb
Host smart-9eead190-6775-48d0-8fa6-adaa93e3794a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652579421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.652579421
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.1073002872
Short name T358
Test name
Test status
Simulation time 8346250166 ps
CPU time 31.19 seconds
Started Apr 15 03:31:46 PM PDT 24
Finished Apr 15 03:32:18 PM PDT 24
Peak memory 333668 kb
Host smart-5df826fb-229e-4835-8219-f29ea87c29a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073002872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.1073002872
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.253245362
Short name T634
Test name
Test status
Simulation time 17114285 ps
CPU time 0.64 seconds
Started Apr 15 03:31:43 PM PDT 24
Finished Apr 15 03:31:44 PM PDT 24
Peak memory 203668 kb
Host smart-cceffeb1-387a-4859-a0b3-5b1bd627fd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253245362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.253245362
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.3863891229
Short name T544
Test name
Test status
Simulation time 2727964507 ps
CPU time 110.52 seconds
Started Apr 15 03:31:33 PM PDT 24
Finished Apr 15 03:33:24 PM PDT 24
Peak memory 265824 kb
Host smart-327f9886-0214-49d3-bcd8-a9069e438057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863891229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.3863891229
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.667850394
Short name T747
Test name
Test status
Simulation time 1309047694 ps
CPU time 59.55 seconds
Started Apr 15 03:31:30 PM PDT 24
Finished Apr 15 03:32:31 PM PDT 24
Peak memory 283544 kb
Host smart-df868a80-d236-4cb3-80e0-4c37c1c262a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667850394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.667850394
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.2576137046
Short name T1035
Test name
Test status
Simulation time 468317089 ps
CPU time 8.39 seconds
Started Apr 15 03:31:33 PM PDT 24
Finished Apr 15 03:31:42 PM PDT 24
Peak memory 214824 kb
Host smart-13e72633-023c-4b35-b43a-9642e9c7e84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576137046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.2576137046
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.4212006400
Short name T1040
Test name
Test status
Simulation time 9825025572 ps
CPU time 3.75 seconds
Started Apr 15 03:31:39 PM PDT 24
Finished Apr 15 03:31:43 PM PDT 24
Peak memory 204028 kb
Host smart-3883922d-f94b-425c-9c5b-0be43112a2cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212006400 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.4212006400
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.1474340970
Short name T37
Test name
Test status
Simulation time 10186377224 ps
CPU time 7.39 seconds
Started Apr 15 03:31:38 PM PDT 24
Finished Apr 15 03:31:46 PM PDT 24
Peak memory 252672 kb
Host smart-a4750a1e-5ca5-4b25-9953-73f2872dec41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474340970 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.1474340970
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.53991007
Short name T267
Test name
Test status
Simulation time 10265658078 ps
CPU time 13.08 seconds
Started Apr 15 03:31:44 PM PDT 24
Finished Apr 15 03:31:58 PM PDT 24
Peak memory 298300 kb
Host smart-fc741ef7-27c5-4287-a2fb-8ab397cd31a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53991007 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.i2c_target_fifo_reset_tx.53991007
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.293595435
Short name T1348
Test name
Test status
Simulation time 327852044 ps
CPU time 2.2 seconds
Started Apr 15 03:31:44 PM PDT 24
Finished Apr 15 03:31:47 PM PDT 24
Peak memory 203988 kb
Host smart-61178a34-5674-4197-abf0-9f2cc85e3d41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293595435 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.i2c_target_hrst.293595435
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.4125324632
Short name T938
Test name
Test status
Simulation time 936397448 ps
CPU time 4.48 seconds
Started Apr 15 03:31:39 PM PDT 24
Finished Apr 15 03:31:44 PM PDT 24
Peak memory 203952 kb
Host smart-3a1064f9-49cc-47c4-8950-9dad5954d466
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125324632 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.4125324632
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.575744955
Short name T123
Test name
Test status
Simulation time 11757888796 ps
CPU time 14.83 seconds
Started Apr 15 03:31:37 PM PDT 24
Finished Apr 15 03:31:52 PM PDT 24
Peak memory 381168 kb
Host smart-ce843d60-de74-40f3-9e61-659a764649bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575744955 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.575744955
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.2879239965
Short name T1268
Test name
Test status
Simulation time 972778304 ps
CPU time 16.15 seconds
Started Apr 15 03:31:43 PM PDT 24
Finished Apr 15 03:32:00 PM PDT 24
Peak memory 204016 kb
Host smart-9997cd3f-c8e7-4930-a8b2-7e7069c10875
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879239965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.2879239965
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.3917718550
Short name T603
Test name
Test status
Simulation time 461253198 ps
CPU time 8.16 seconds
Started Apr 15 03:31:36 PM PDT 24
Finished Apr 15 03:31:45 PM PDT 24
Peak memory 204020 kb
Host smart-9a978a47-1a47-4789-87d3-400b6be478d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917718550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.3917718550
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.3077855159
Short name T1029
Test name
Test status
Simulation time 10612727881 ps
CPU time 11.56 seconds
Started Apr 15 03:31:38 PM PDT 24
Finished Apr 15 03:31:50 PM PDT 24
Peak memory 204012 kb
Host smart-221706a2-33f6-4a40-8798-310faecdb030
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077855159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.3077855159
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.1325224827
Short name T858
Test name
Test status
Simulation time 32579734296 ps
CPU time 674.97 seconds
Started Apr 15 03:31:38 PM PDT 24
Finished Apr 15 03:42:54 PM PDT 24
Peak memory 3648940 kb
Host smart-fe9157c9-f0f6-4669-b5a6-34bc6daf9bdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325224827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.1325224827
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.3887074433
Short name T536
Test name
Test status
Simulation time 5586050090 ps
CPU time 6.86 seconds
Started Apr 15 03:31:40 PM PDT 24
Finished Apr 15 03:31:47 PM PDT 24
Peak memory 220276 kb
Host smart-93f2b932-3714-4579-a6b1-b5098c8698e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887074433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.3887074433
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.304994984
Short name T751
Test name
Test status
Simulation time 16806742 ps
CPU time 0.58 seconds
Started Apr 15 03:31:53 PM PDT 24
Finished Apr 15 03:31:54 PM PDT 24
Peak memory 203560 kb
Host smart-ab338ff8-7489-48a8-a284-f9635d49cb4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304994984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.304994984
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.472226353
Short name T655
Test name
Test status
Simulation time 223284504 ps
CPU time 1.56 seconds
Started Apr 15 03:31:44 PM PDT 24
Finished Apr 15 03:31:47 PM PDT 24
Peak memory 212344 kb
Host smart-731849af-7d07-419a-b230-5e53eb9bdde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472226353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.472226353
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.2343320104
Short name T849
Test name
Test status
Simulation time 1866017477 ps
CPU time 9.92 seconds
Started Apr 15 03:31:44 PM PDT 24
Finished Apr 15 03:31:54 PM PDT 24
Peak memory 288752 kb
Host smart-59693182-a882-432a-bffc-e734ca74465c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343320104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.2343320104
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2202365606
Short name T461
Test name
Test status
Simulation time 26117820446 ps
CPU time 128.25 seconds
Started Apr 15 03:31:43 PM PDT 24
Finished Apr 15 03:33:52 PM PDT 24
Peak memory 619948 kb
Host smart-31a1bb57-3249-41e0-8fa8-56acba760df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202365606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2202365606
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.188426641
Short name T1299
Test name
Test status
Simulation time 3481708520 ps
CPU time 125 seconds
Started Apr 15 03:31:41 PM PDT 24
Finished Apr 15 03:33:46 PM PDT 24
Peak memory 601996 kb
Host smart-26ad3549-4921-476b-ab8d-7a2c290a0aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188426641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.188426641
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.1265420246
Short name T85
Test name
Test status
Simulation time 194191045 ps
CPU time 1 seconds
Started Apr 15 03:31:39 PM PDT 24
Finished Apr 15 03:31:40 PM PDT 24
Peak memory 203960 kb
Host smart-00625ebc-0d36-426e-a592-59a2b1772ebd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265420246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.1265420246
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.1271105158
Short name T1215
Test name
Test status
Simulation time 715310927 ps
CPU time 4.57 seconds
Started Apr 15 03:31:44 PM PDT 24
Finished Apr 15 03:31:49 PM PDT 24
Peak memory 238760 kb
Host smart-181f8995-2190-4a28-9651-09cc0faf8edf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271105158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.1271105158
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.1204601183
Short name T1171
Test name
Test status
Simulation time 6088789726 ps
CPU time 69.99 seconds
Started Apr 15 03:31:44 PM PDT 24
Finished Apr 15 03:32:55 PM PDT 24
Peak memory 946748 kb
Host smart-76257739-c9a0-4758-8931-eb7ad7eb4265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204601183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.1204601183
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.634367182
Short name T240
Test name
Test status
Simulation time 589030511 ps
CPU time 5.15 seconds
Started Apr 15 03:31:53 PM PDT 24
Finished Apr 15 03:31:58 PM PDT 24
Peak memory 203964 kb
Host smart-3d3c2866-2fc7-49d4-9a16-d6df25688556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634367182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.634367182
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.4061988449
Short name T76
Test name
Test status
Simulation time 4626861083 ps
CPU time 24.77 seconds
Started Apr 15 03:31:53 PM PDT 24
Finished Apr 15 03:32:18 PM PDT 24
Peak memory 296924 kb
Host smart-4977ccb4-f1f1-47c9-b004-bdfd40eadcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061988449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.4061988449
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.4198435463
Short name T419
Test name
Test status
Simulation time 28802042 ps
CPU time 0.68 seconds
Started Apr 15 03:31:40 PM PDT 24
Finished Apr 15 03:31:42 PM PDT 24
Peak memory 203664 kb
Host smart-6fb960a7-7878-492a-893d-a2ffeb0802f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198435463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.4198435463
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.2714165019
Short name T122
Test name
Test status
Simulation time 7664224463 ps
CPU time 20.85 seconds
Started Apr 15 03:31:46 PM PDT 24
Finished Apr 15 03:32:08 PM PDT 24
Peak memory 212192 kb
Host smart-861729bb-1d30-4122-ad1f-6665d15959f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714165019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2714165019
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.649625457
Short name T900
Test name
Test status
Simulation time 5242856242 ps
CPU time 24.07 seconds
Started Apr 15 03:31:43 PM PDT 24
Finished Apr 15 03:32:08 PM PDT 24
Peak memory 301512 kb
Host smart-0d69c4b3-bd33-4288-83d8-6dca0bf601c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649625457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.649625457
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.3359272092
Short name T1245
Test name
Test status
Simulation time 9267237372 ps
CPU time 3.32 seconds
Started Apr 15 03:31:50 PM PDT 24
Finished Apr 15 03:31:54 PM PDT 24
Peak memory 204036 kb
Host smart-b8b18ba1-0da5-400d-be9d-e1f2aabf201d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359272092 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.3359272092
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.2240799327
Short name T1205
Test name
Test status
Simulation time 10056919714 ps
CPU time 25.35 seconds
Started Apr 15 03:31:48 PM PDT 24
Finished Apr 15 03:32:14 PM PDT 24
Peak memory 307532 kb
Host smart-bb6b3bba-d6d6-4a99-8c5f-da57890579ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240799327 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.2240799327
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.171646288
Short name T1206
Test name
Test status
Simulation time 10175735556 ps
CPU time 32.5 seconds
Started Apr 15 03:31:50 PM PDT 24
Finished Apr 15 03:32:23 PM PDT 24
Peak memory 413892 kb
Host smart-6cde524c-1dae-4038-8496-cce613439c79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171646288 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_fifo_reset_tx.171646288
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.3977030057
Short name T15
Test name
Test status
Simulation time 1416993032 ps
CPU time 2.19 seconds
Started Apr 15 03:31:51 PM PDT 24
Finished Apr 15 03:31:54 PM PDT 24
Peak memory 204016 kb
Host smart-1960ded9-4da0-4d08-a92c-bbe28d1f20fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977030057 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.3977030057
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.602961278
Short name T561
Test name
Test status
Simulation time 3704993533 ps
CPU time 4.45 seconds
Started Apr 15 03:31:50 PM PDT 24
Finished Apr 15 03:31:55 PM PDT 24
Peak memory 204060 kb
Host smart-90c9d844-e81d-4555-aa97-bd6c54b796da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602961278 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_intr_smoke.602961278
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.2293241586
Short name T21
Test name
Test status
Simulation time 18982694246 ps
CPU time 44.39 seconds
Started Apr 15 03:31:48 PM PDT 24
Finished Apr 15 03:32:33 PM PDT 24
Peak memory 773448 kb
Host smart-26761ab0-5dd9-4bf0-94f8-f45f5ddb784f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293241586 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.2293241586
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.3524615253
Short name T746
Test name
Test status
Simulation time 1104255419 ps
CPU time 17.15 seconds
Started Apr 15 03:31:43 PM PDT 24
Finished Apr 15 03:32:01 PM PDT 24
Peak memory 204028 kb
Host smart-4a8340cd-3563-4e89-8bf1-463152a887ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524615253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.3524615253
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.1058289188
Short name T3
Test name
Test status
Simulation time 7282605210 ps
CPU time 27.52 seconds
Started Apr 15 03:31:45 PM PDT 24
Finished Apr 15 03:32:13 PM PDT 24
Peak memory 228360 kb
Host smart-f9dd46a6-ce97-4ea7-b3a8-2af23ef0dc81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058289188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.1058289188
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.582090603
Short name T1003
Test name
Test status
Simulation time 62960655439 ps
CPU time 227.81 seconds
Started Apr 15 03:31:44 PM PDT 24
Finished Apr 15 03:35:33 PM PDT 24
Peak memory 2199216 kb
Host smart-c9619660-1512-4bcf-8545-198761c9b13b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582090603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_wr.582090603
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.68776543
Short name T1006
Test name
Test status
Simulation time 52210083106 ps
CPU time 1517.65 seconds
Started Apr 15 03:31:48 PM PDT 24
Finished Apr 15 03:57:07 PM PDT 24
Peak memory 6451944 kb
Host smart-9ba6fad3-847d-46a4-8b4d-e79a2120304d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68776543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_stretch.68776543
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.3976261231
Short name T775
Test name
Test status
Simulation time 4386044519 ps
CPU time 6.86 seconds
Started Apr 15 03:31:49 PM PDT 24
Finished Apr 15 03:31:57 PM PDT 24
Peak memory 220248 kb
Host smart-daf2972e-9f74-4e2d-a6e3-0763b2946054
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976261231 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.3976261231
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_unexp_stop.4166841241
Short name T1221
Test name
Test status
Simulation time 1117741385 ps
CPU time 6.07 seconds
Started Apr 15 03:31:50 PM PDT 24
Finished Apr 15 03:31:57 PM PDT 24
Peak memory 209568 kb
Host smart-bb9a8652-da3d-4626-9e33-fbcd5c8a9816
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166841241 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.i2c_target_unexp_stop.4166841241
Directory /workspace/26.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/27.i2c_alert_test.1348701833
Short name T1045
Test name
Test status
Simulation time 22730868 ps
CPU time 0.65 seconds
Started Apr 15 03:32:02 PM PDT 24
Finished Apr 15 03:32:04 PM PDT 24
Peak memory 203552 kb
Host smart-f81cadf5-78c6-4c51-aa02-c755c40744c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348701833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.1348701833
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.2957884026
Short name T777
Test name
Test status
Simulation time 239522301 ps
CPU time 1.28 seconds
Started Apr 15 03:31:55 PM PDT 24
Finished Apr 15 03:31:57 PM PDT 24
Peak memory 212300 kb
Host smart-a9f6892b-9420-4fd2-8deb-ec859f4297e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957884026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.2957884026
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.3152784726
Short name T386
Test name
Test status
Simulation time 1310638461 ps
CPU time 6.05 seconds
Started Apr 15 03:31:53 PM PDT 24
Finished Apr 15 03:32:00 PM PDT 24
Peak memory 277100 kb
Host smart-5781f496-411c-4f56-aa45-a7accb39b53c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152784726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.3152784726
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.1417127811
Short name T724
Test name
Test status
Simulation time 6009657456 ps
CPU time 42.5 seconds
Started Apr 15 03:31:51 PM PDT 24
Finished Apr 15 03:32:34 PM PDT 24
Peak memory 561336 kb
Host smart-90567b0e-272d-4776-8242-8bfbd8ea1044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417127811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.1417127811
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.227060370
Short name T278
Test name
Test status
Simulation time 6440918574 ps
CPU time 43.34 seconds
Started Apr 15 03:31:53 PM PDT 24
Finished Apr 15 03:32:37 PM PDT 24
Peak memory 589372 kb
Host smart-76599ee3-8938-4789-9004-62bee2898673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227060370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.227060370
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2158726144
Short name T230
Test name
Test status
Simulation time 194921360 ps
CPU time 0.9 seconds
Started Apr 15 03:31:54 PM PDT 24
Finished Apr 15 03:31:55 PM PDT 24
Peak memory 203728 kb
Host smart-fbc9bbf3-1262-427e-bbad-c1db40e30c82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158726144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.2158726144
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.740138018
Short name T420
Test name
Test status
Simulation time 396612818 ps
CPU time 10.9 seconds
Started Apr 15 03:31:52 PM PDT 24
Finished Apr 15 03:32:04 PM PDT 24
Peak memory 241072 kb
Host smart-7af90efd-96a9-460d-8e22-f6d7378bf4b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740138018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.
740138018
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.2905096620
Short name T806
Test name
Test status
Simulation time 25714011768 ps
CPU time 107.65 seconds
Started Apr 15 03:31:52 PM PDT 24
Finished Apr 15 03:33:40 PM PDT 24
Peak memory 1101316 kb
Host smart-c880c2ef-e2c4-4c30-9c95-01926559b28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905096620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.2905096620
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.1163778893
Short name T1064
Test name
Test status
Simulation time 1271303201 ps
CPU time 7.46 seconds
Started Apr 15 03:32:00 PM PDT 24
Finished Apr 15 03:32:09 PM PDT 24
Peak memory 204000 kb
Host smart-78a69714-dab8-4ba5-9670-70760432ad87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163778893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.1163778893
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.1165574834
Short name T788
Test name
Test status
Simulation time 30563435842 ps
CPU time 70.28 seconds
Started Apr 15 03:31:58 PM PDT 24
Finished Apr 15 03:33:09 PM PDT 24
Peak memory 319092 kb
Host smart-d7590be1-b213-44fe-a70c-9d625094f2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165574834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.1165574834
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.2813434898
Short name T1071
Test name
Test status
Simulation time 15805179 ps
CPU time 0.65 seconds
Started Apr 15 03:31:52 PM PDT 24
Finished Apr 15 03:31:54 PM PDT 24
Peak memory 203672 kb
Host smart-26a371f5-12fb-4c2f-92b4-fe371a6ddbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813434898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.2813434898
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.4212337105
Short name T1084
Test name
Test status
Simulation time 52816572190 ps
CPU time 503.86 seconds
Started Apr 15 03:31:57 PM PDT 24
Finished Apr 15 03:40:22 PM PDT 24
Peak memory 212272 kb
Host smart-5c5f2ebb-62b2-4c7b-959c-f55e6d468002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212337105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.4212337105
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.245954884
Short name T1162
Test name
Test status
Simulation time 3476765003 ps
CPU time 42.48 seconds
Started Apr 15 03:31:52 PM PDT 24
Finished Apr 15 03:32:35 PM PDT 24
Peak memory 220316 kb
Host smart-16c3b2a2-aa00-49c7-b613-2dff2c695532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245954884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.245954884
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3203005016
Short name T1349
Test name
Test status
Simulation time 4018542906 ps
CPU time 17.18 seconds
Started Apr 15 03:31:52 PM PDT 24
Finished Apr 15 03:32:09 PM PDT 24
Peak memory 217780 kb
Host smart-b314348b-f461-4055-b562-635c68a8dbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203005016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3203005016
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.3032234758
Short name T298
Test name
Test status
Simulation time 1856080426 ps
CPU time 2.52 seconds
Started Apr 15 03:32:01 PM PDT 24
Finished Apr 15 03:32:05 PM PDT 24
Peak memory 204016 kb
Host smart-e91de609-8337-4e9f-ba4e-c76fef4ce211
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032234758 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.3032234758
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3251172799
Short name T1229
Test name
Test status
Simulation time 10075898568 ps
CPU time 25.08 seconds
Started Apr 15 03:31:59 PM PDT 24
Finished Apr 15 03:32:25 PM PDT 24
Peak memory 344460 kb
Host smart-3714ad9d-8bc7-472f-a4a9-537ec0f0e28a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251172799 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.3251172799
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.2411502800
Short name T457
Test name
Test status
Simulation time 11115062239 ps
CPU time 5.54 seconds
Started Apr 15 03:31:55 PM PDT 24
Finished Apr 15 03:32:01 PM PDT 24
Peak memory 238264 kb
Host smart-521dd9fe-2a43-440e-8c8c-6b6ba2b68896
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411502800 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.2411502800
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.1769279437
Short name T1300
Test name
Test status
Simulation time 3773382742 ps
CPU time 2.5 seconds
Started Apr 15 03:31:59 PM PDT 24
Finished Apr 15 03:32:02 PM PDT 24
Peak memory 204092 kb
Host smart-fd44c96e-a2fb-4e7e-bd0a-0baef21cedd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769279437 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.1769279437
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.3049660766
Short name T933
Test name
Test status
Simulation time 6139005423 ps
CPU time 6.84 seconds
Started Apr 15 03:31:55 PM PDT 24
Finished Apr 15 03:32:02 PM PDT 24
Peak memory 220176 kb
Host smart-fdbc8ae1-a333-46fe-a791-85b39a0ad2dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049660766 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.3049660766
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.908042633
Short name T1271
Test name
Test status
Simulation time 2834071361 ps
CPU time 3.81 seconds
Started Apr 15 03:31:55 PM PDT 24
Finished Apr 15 03:31:59 PM PDT 24
Peak memory 204100 kb
Host smart-80716b34-3944-43a9-a990-bd762b64254f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908042633 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.908042633
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.2456106285
Short name T1277
Test name
Test status
Simulation time 3434085894 ps
CPU time 10.61 seconds
Started Apr 15 03:31:57 PM PDT 24
Finished Apr 15 03:32:09 PM PDT 24
Peak memory 204108 kb
Host smart-3262b6ba-e980-4643-a02e-515ccece1f69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456106285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.2456106285
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.2022426837
Short name T318
Test name
Test status
Simulation time 1028198328 ps
CPU time 15.94 seconds
Started Apr 15 03:31:55 PM PDT 24
Finished Apr 15 03:32:12 PM PDT 24
Peak memory 218460 kb
Host smart-a4981959-486d-4b2a-af95-79b913a34ccf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022426837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.2022426837
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.2360249674
Short name T1310
Test name
Test status
Simulation time 16155628156 ps
CPU time 32.2 seconds
Started Apr 15 03:31:56 PM PDT 24
Finished Apr 15 03:32:29 PM PDT 24
Peak memory 204076 kb
Host smart-c3b8c7ec-d4bb-48c4-a2ec-8a38904adaf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360249674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.2360249674
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.3765365370
Short name T1320
Test name
Test status
Simulation time 17471899475 ps
CPU time 3332.38 seconds
Started Apr 15 03:31:57 PM PDT 24
Finished Apr 15 04:27:30 PM PDT 24
Peak memory 4328608 kb
Host smart-79e1ae0f-9090-4280-8c33-6be1b47dc81e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765365370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.3765365370
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.865182726
Short name T623
Test name
Test status
Simulation time 23096890892 ps
CPU time 6.71 seconds
Started Apr 15 03:32:13 PM PDT 24
Finished Apr 15 03:32:21 PM PDT 24
Peak memory 217120 kb
Host smart-ef9b5acc-6f58-4198-8a70-1b37d7083d95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865182726 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_timeout.865182726
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.2722556340
Short name T589
Test name
Test status
Simulation time 17893837 ps
CPU time 0.62 seconds
Started Apr 15 03:32:25 PM PDT 24
Finished Apr 15 03:32:26 PM PDT 24
Peak memory 203576 kb
Host smart-1f4810dd-cec5-4b1e-acf5-49b44e5dfe7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722556340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.2722556340
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.269443102
Short name T315
Test name
Test status
Simulation time 115231630 ps
CPU time 1.42 seconds
Started Apr 15 03:32:02 PM PDT 24
Finished Apr 15 03:32:04 PM PDT 24
Peak memory 204036 kb
Host smart-dc6dd613-a4e1-428b-8146-83af6b7343ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269443102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.269443102
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.524713954
Short name T815
Test name
Test status
Simulation time 160021680 ps
CPU time 7.6 seconds
Started Apr 15 03:32:04 PM PDT 24
Finished Apr 15 03:32:12 PM PDT 24
Peak memory 232152 kb
Host smart-ed9946eb-50f7-4a71-a430-3d2507db6eb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524713954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empt
y.524713954
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3096155607
Short name T692
Test name
Test status
Simulation time 8916767154 ps
CPU time 65.89 seconds
Started Apr 15 03:32:02 PM PDT 24
Finished Apr 15 03:33:09 PM PDT 24
Peak memory 736564 kb
Host smart-9371783f-a4c3-4707-a7d3-e8f0502cb6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096155607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3096155607
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.199475238
Short name T40
Test name
Test status
Simulation time 2033736026 ps
CPU time 151.11 seconds
Started Apr 15 03:32:02 PM PDT 24
Finished Apr 15 03:34:34 PM PDT 24
Peak memory 688632 kb
Host smart-ec72d3bd-c6cb-4f20-9b26-5784527870ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199475238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.199475238
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.3399420943
Short name T722
Test name
Test status
Simulation time 407489797 ps
CPU time 1.1 seconds
Started Apr 15 03:32:03 PM PDT 24
Finished Apr 15 03:32:05 PM PDT 24
Peak memory 203928 kb
Host smart-1e29b80e-a63c-4f00-b3b9-f6c40df2df9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399420943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.3399420943
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.728472297
Short name T921
Test name
Test status
Simulation time 198960468 ps
CPU time 4.53 seconds
Started Apr 15 03:32:04 PM PDT 24
Finished Apr 15 03:32:10 PM PDT 24
Peak memory 203944 kb
Host smart-9654a1bb-a035-4f5f-a5b5-4b1fcd78a694
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728472297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.
728472297
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.3619388758
Short name T1293
Test name
Test status
Simulation time 2955391550 ps
CPU time 82.33 seconds
Started Apr 15 03:32:04 PM PDT 24
Finished Apr 15 03:33:28 PM PDT 24
Peak memory 913000 kb
Host smart-ea8aca34-6202-4c9a-90da-b404d0a9308b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619388758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3619388758
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.3893705907
Short name T384
Test name
Test status
Simulation time 921295319 ps
CPU time 3.81 seconds
Started Apr 15 03:32:08 PM PDT 24
Finished Apr 15 03:32:13 PM PDT 24
Peak memory 204028 kb
Host smart-4e20b783-ddbb-43e4-b7c5-8c2e2d2369ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893705907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.3893705907
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.1034836351
Short name T562
Test name
Test status
Simulation time 22725527585 ps
CPU time 20.1 seconds
Started Apr 15 03:32:08 PM PDT 24
Finished Apr 15 03:32:29 PM PDT 24
Peak memory 298768 kb
Host smart-4062623d-1f26-4ec7-820b-01d6ea278ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034836351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.1034836351
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.493505181
Short name T33
Test name
Test status
Simulation time 240815960 ps
CPU time 0.67 seconds
Started Apr 15 03:32:02 PM PDT 24
Finished Apr 15 03:32:04 PM PDT 24
Peak memory 203664 kb
Host smart-99d7ad9e-85d2-404c-a9f7-78d91983248a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493505181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.493505181
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.2485799962
Short name T1075
Test name
Test status
Simulation time 49804858705 ps
CPU time 554.72 seconds
Started Apr 15 03:32:03 PM PDT 24
Finished Apr 15 03:41:19 PM PDT 24
Peak memory 203976 kb
Host smart-dade128a-c3c8-485c-82e6-5945c5715ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485799962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.2485799962
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1903321551
Short name T568
Test name
Test status
Simulation time 7281577042 ps
CPU time 17.95 seconds
Started Apr 15 03:32:03 PM PDT 24
Finished Apr 15 03:32:22 PM PDT 24
Peak memory 292952 kb
Host smart-bd41126d-068b-4790-9ccf-471314b9057b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903321551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1903321551
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.144923922
Short name T264
Test name
Test status
Simulation time 15735815025 ps
CPU time 270.44 seconds
Started Apr 15 03:32:03 PM PDT 24
Finished Apr 15 03:36:34 PM PDT 24
Peak memory 711524 kb
Host smart-1ca323a9-b9e3-4324-ae75-5dbb1308d649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144923922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.144923922
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.717883355
Short name T783
Test name
Test status
Simulation time 1521096718 ps
CPU time 12.05 seconds
Started Apr 15 03:32:02 PM PDT 24
Finished Apr 15 03:32:15 PM PDT 24
Peak memory 219644 kb
Host smart-28cea53e-356a-47b1-ae2b-434ced1dbd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717883355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.717883355
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.1201395414
Short name T490
Test name
Test status
Simulation time 3029241539 ps
CPU time 3.89 seconds
Started Apr 15 03:32:07 PM PDT 24
Finished Apr 15 03:32:12 PM PDT 24
Peak memory 204068 kb
Host smart-f3c85fd2-390d-4e6b-856e-523b34c546aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201395414 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.1201395414
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.111185189
Short name T79
Test name
Test status
Simulation time 12202471629 ps
CPU time 3.82 seconds
Started Apr 15 03:32:07 PM PDT 24
Finished Apr 15 03:32:12 PM PDT 24
Peak memory 213776 kb
Host smart-c1244a38-ddce-4e91-a51a-7496d0b41202
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111185189 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_acq.111185189
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.1918046339
Short name T929
Test name
Test status
Simulation time 10154828477 ps
CPU time 16.12 seconds
Started Apr 15 03:32:04 PM PDT 24
Finished Apr 15 03:32:21 PM PDT 24
Peak memory 310988 kb
Host smart-93b8be26-f89e-4b60-97cb-11302af06391
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918046339 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.1918046339
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.1533375912
Short name T24
Test name
Test status
Simulation time 1066437587 ps
CPU time 2.81 seconds
Started Apr 15 03:32:06 PM PDT 24
Finished Apr 15 03:32:10 PM PDT 24
Peak memory 204016 kb
Host smart-fe356c85-59d3-4c07-ae51-4fbcade21438
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533375912 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.1533375912
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.4103159711
Short name T868
Test name
Test status
Simulation time 3015868008 ps
CPU time 3.84 seconds
Started Apr 15 03:32:07 PM PDT 24
Finished Apr 15 03:32:12 PM PDT 24
Peak memory 204036 kb
Host smart-208aef60-3016-4b9d-a5df-bdf78205c658
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103159711 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.4103159711
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.2815408972
Short name T951
Test name
Test status
Simulation time 19199366979 ps
CPU time 17.72 seconds
Started Apr 15 03:32:07 PM PDT 24
Finished Apr 15 03:32:26 PM PDT 24
Peak memory 423172 kb
Host smart-9b6b181b-8d7d-4d84-8739-17c687d9bdc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815408972 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.2815408972
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1022128137
Short name T888
Test name
Test status
Simulation time 2994827661 ps
CPU time 12.5 seconds
Started Apr 15 03:32:01 PM PDT 24
Finished Apr 15 03:32:15 PM PDT 24
Peak memory 204028 kb
Host smart-c62506ea-de84-4c78-9a9e-68ea44116637
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022128137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1022128137
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.3259121586
Short name T323
Test name
Test status
Simulation time 1604838153 ps
CPU time 24.12 seconds
Started Apr 15 03:32:06 PM PDT 24
Finished Apr 15 03:32:31 PM PDT 24
Peak memory 226160 kb
Host smart-9f69764d-c844-46a4-9571-84bc7224030d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259121586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.3259121586
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.2457009237
Short name T690
Test name
Test status
Simulation time 65541578813 ps
CPU time 245.65 seconds
Started Apr 15 03:32:06 PM PDT 24
Finished Apr 15 03:36:13 PM PDT 24
Peak memory 2547264 kb
Host smart-5cd1749f-723e-4c63-bfea-3b6869fadf27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457009237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.2457009237
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.1951870377
Short name T379
Test name
Test status
Simulation time 37774275795 ps
CPU time 177.48 seconds
Started Apr 15 03:32:06 PM PDT 24
Finished Apr 15 03:35:05 PM PDT 24
Peak memory 1642312 kb
Host smart-611cdad5-608d-4f62-aef1-c06753c84aac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951870377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.1951870377
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.3645759026
Short name T397
Test name
Test status
Simulation time 1428098482 ps
CPU time 6.82 seconds
Started Apr 15 03:32:05 PM PDT 24
Finished Apr 15 03:32:12 PM PDT 24
Peak memory 220192 kb
Host smart-5e7b79ba-9a6e-4b3e-b478-80ab1ee8f8df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645759026 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.3645759026
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.599891264
Short name T115
Test name
Test status
Simulation time 25773930 ps
CPU time 0.63 seconds
Started Apr 15 03:32:21 PM PDT 24
Finished Apr 15 03:32:23 PM PDT 24
Peak memory 203596 kb
Host smart-54ba9050-7fca-429b-b631-47d9fcb1d79c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599891264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.599891264
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.55739471
Short name T1328
Test name
Test status
Simulation time 156966884 ps
CPU time 1.75 seconds
Started Apr 15 03:32:13 PM PDT 24
Finished Apr 15 03:32:15 PM PDT 24
Peak memory 212332 kb
Host smart-9291d2bf-8892-47dc-949d-d3cb4460562f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55739471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.55739471
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.2928532450
Short name T884
Test name
Test status
Simulation time 316185948 ps
CPU time 5.69 seconds
Started Apr 15 03:32:09 PM PDT 24
Finished Apr 15 03:32:16 PM PDT 24
Peak memory 268876 kb
Host smart-9095909f-6976-4d66-b1bd-55e344ad0c60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928532450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.2928532450
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.2343294205
Short name T1166
Test name
Test status
Simulation time 2193122093 ps
CPU time 67.22 seconds
Started Apr 15 03:32:11 PM PDT 24
Finished Apr 15 03:33:19 PM PDT 24
Peak memory 720612 kb
Host smart-7b7934af-86bd-4767-a40b-bd3b5a7f35d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343294205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.2343294205
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.1591310701
Short name T659
Test name
Test status
Simulation time 2153374851 ps
CPU time 58.06 seconds
Started Apr 15 03:32:09 PM PDT 24
Finished Apr 15 03:33:08 PM PDT 24
Peak memory 642808 kb
Host smart-06669eb9-c665-49d4-ab9b-ce5493c6a741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591310701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1591310701
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.2427358931
Short name T736
Test name
Test status
Simulation time 175644736 ps
CPU time 1.08 seconds
Started Apr 15 03:32:09 PM PDT 24
Finished Apr 15 03:32:11 PM PDT 24
Peak memory 203748 kb
Host smart-9a332227-d2ee-41e5-ac02-721ef221684f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427358931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.2427358931
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.2836562702
Short name T292
Test name
Test status
Simulation time 191508745 ps
CPU time 5.28 seconds
Started Apr 15 03:32:12 PM PDT 24
Finished Apr 15 03:32:17 PM PDT 24
Peak memory 236032 kb
Host smart-5328e3fe-da24-4ca9-bc45-59911df56497
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836562702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.2836562702
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.4071749453
Short name T1108
Test name
Test status
Simulation time 14951180735 ps
CPU time 110.38 seconds
Started Apr 15 03:32:07 PM PDT 24
Finished Apr 15 03:33:59 PM PDT 24
Peak memory 1135688 kb
Host smart-17726830-46c9-4251-9f1c-4842b15a3324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071749453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.4071749453
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.3199779807
Short name T1114
Test name
Test status
Simulation time 1769328007 ps
CPU time 6.82 seconds
Started Apr 15 03:32:22 PM PDT 24
Finished Apr 15 03:32:29 PM PDT 24
Peak memory 203980 kb
Host smart-dc888d52-42d0-4d50-a8fc-d26ca050da41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199779807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.3199779807
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.1008268194
Short name T807
Test name
Test status
Simulation time 1627980522 ps
CPU time 32.16 seconds
Started Apr 15 03:32:16 PM PDT 24
Finished Apr 15 03:32:48 PM PDT 24
Peak memory 413428 kb
Host smart-96cb8f03-4f42-408e-94d8-0c10a2ff4e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008268194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.1008268194
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.3839378515
Short name T498
Test name
Test status
Simulation time 26565863 ps
CPU time 0.67 seconds
Started Apr 15 03:32:09 PM PDT 24
Finished Apr 15 03:32:10 PM PDT 24
Peak memory 203696 kb
Host smart-8263d5b7-66e3-4a5b-8058-f45991918ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839378515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3839378515
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.623183349
Short name T221
Test name
Test status
Simulation time 5824740709 ps
CPU time 20.03 seconds
Started Apr 15 03:32:12 PM PDT 24
Finished Apr 15 03:32:32 PM PDT 24
Peak memory 325748 kb
Host smart-e45f3d61-a92d-4f34-a088-5186918bb92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623183349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.623183349
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.2218567602
Short name T339
Test name
Test status
Simulation time 14082979508 ps
CPU time 20.06 seconds
Started Apr 15 03:32:11 PM PDT 24
Finished Apr 15 03:32:31 PM PDT 24
Peak memory 282836 kb
Host smart-13f0ebc0-548e-4c14-9ca3-925393a6599a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218567602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.2218567602
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.2901566573
Short name T233
Test name
Test status
Simulation time 40106596029 ps
CPU time 1321.48 seconds
Started Apr 15 03:32:14 PM PDT 24
Finished Apr 15 03:54:16 PM PDT 24
Peak memory 2459388 kb
Host smart-1e53d306-78a6-4ca4-aa0c-55e187d97087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901566573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.2901566573
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.2608166285
Short name T478
Test name
Test status
Simulation time 500485195 ps
CPU time 22.19 seconds
Started Apr 15 03:32:10 PM PDT 24
Finished Apr 15 03:32:33 PM PDT 24
Peak memory 212164 kb
Host smart-ac88ce95-da0e-48ae-a2e3-28c97c474d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608166285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.2608166285
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.1264455185
Short name T1274
Test name
Test status
Simulation time 1609837279 ps
CPU time 3.9 seconds
Started Apr 15 03:32:21 PM PDT 24
Finished Apr 15 03:32:26 PM PDT 24
Peak memory 203984 kb
Host smart-ac70ccf4-795b-457c-bc21-225c9b28f7b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264455185 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.1264455185
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.4042005211
Short name T51
Test name
Test status
Simulation time 10078873762 ps
CPU time 80.77 seconds
Started Apr 15 03:32:17 PM PDT 24
Finished Apr 15 03:33:38 PM PDT 24
Peak memory 531728 kb
Host smart-22f1ef04-50f8-4273-93f5-d1fcc28b5f64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042005211 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.4042005211
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3177984298
Short name T649
Test name
Test status
Simulation time 10114921906 ps
CPU time 32.34 seconds
Started Apr 15 03:32:18 PM PDT 24
Finished Apr 15 03:32:51 PM PDT 24
Peak memory 404600 kb
Host smart-7d2391eb-d5e4-4491-b589-ed6888fd3319
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177984298 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3177984298
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.335474665
Short name T288
Test name
Test status
Simulation time 2706666126 ps
CPU time 2.18 seconds
Started Apr 15 03:32:16 PM PDT 24
Finished Apr 15 03:32:18 PM PDT 24
Peak memory 204088 kb
Host smart-b620b942-8698-4f1a-ac86-fc59914fab1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335474665 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.i2c_target_hrst.335474665
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.1024843477
Short name T546
Test name
Test status
Simulation time 2024668600 ps
CPU time 5.24 seconds
Started Apr 15 03:32:20 PM PDT 24
Finished Apr 15 03:32:26 PM PDT 24
Peak memory 207480 kb
Host smart-86bab128-abfe-41c8-bdf0-28b7d7e5fd2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024843477 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.1024843477
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.746427240
Short name T585
Test name
Test status
Simulation time 5152637310 ps
CPU time 3.54 seconds
Started Apr 15 03:32:17 PM PDT 24
Finished Apr 15 03:32:22 PM PDT 24
Peak memory 204096 kb
Host smart-144a2415-286e-453c-8c5e-23bbb90f6108
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746427240 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.746427240
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.8259935
Short name T818
Test name
Test status
Simulation time 1090293032 ps
CPU time 40.81 seconds
Started Apr 15 03:32:12 PM PDT 24
Finished Apr 15 03:32:53 PM PDT 24
Peak memory 203960 kb
Host smart-171b4cb6-c969-421e-a11c-fd8dada5bb35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8259935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_targe
t_smoke.8259935
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.340875994
Short name T1014
Test name
Test status
Simulation time 1818884571 ps
CPU time 26.51 seconds
Started Apr 15 03:32:18 PM PDT 24
Finished Apr 15 03:32:45 PM PDT 24
Peak memory 233428 kb
Host smart-ae070744-9462-4106-84bb-ba25616f30a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340875994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_rd.340875994
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.3974753260
Short name T744
Test name
Test status
Simulation time 11745965539 ps
CPU time 6.24 seconds
Started Apr 15 03:32:13 PM PDT 24
Finished Apr 15 03:32:19 PM PDT 24
Peak memory 204020 kb
Host smart-c030afef-95a1-41c1-86e4-b27149e91e41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974753260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.3974753260
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.1776533403
Short name T1156
Test name
Test status
Simulation time 5921342224 ps
CPU time 85.16 seconds
Started Apr 15 03:32:17 PM PDT 24
Finished Apr 15 03:33:43 PM PDT 24
Peak memory 886308 kb
Host smart-53870d95-0d17-4276-bf1e-cf7708430afe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776533403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.1776533403
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.2832635869
Short name T501
Test name
Test status
Simulation time 5011008467 ps
CPU time 6.73 seconds
Started Apr 15 03:32:22 PM PDT 24
Finished Apr 15 03:32:29 PM PDT 24
Peak memory 211256 kb
Host smart-28e82cbc-7f4f-43fc-96bd-4194da1ed701
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832635869 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.2832635869
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.3201975627
Short name T1126
Test name
Test status
Simulation time 16876156 ps
CPU time 0.63 seconds
Started Apr 15 03:28:53 PM PDT 24
Finished Apr 15 03:28:54 PM PDT 24
Peak memory 203572 kb
Host smart-d4b0e4bc-f2ef-40b6-8a38-f5f9488681c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201975627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.3201975627
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.2380457807
Short name T356
Test name
Test status
Simulation time 192488534 ps
CPU time 1.63 seconds
Started Apr 15 03:28:45 PM PDT 24
Finished Apr 15 03:28:48 PM PDT 24
Peak memory 212252 kb
Host smart-12eb1abf-1156-4cfd-a5e4-5cf55f9bbb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380457807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.2380457807
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2904348539
Short name T1132
Test name
Test status
Simulation time 258139904 ps
CPU time 4.5 seconds
Started Apr 15 03:28:47 PM PDT 24
Finished Apr 15 03:28:52 PM PDT 24
Peak memory 241200 kb
Host smart-6fb2bee0-a149-4b85-a7b0-2057cf3555e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904348539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2904348539
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3026021044
Short name T1031
Test name
Test status
Simulation time 6211994179 ps
CPU time 102.19 seconds
Started Apr 15 03:28:46 PM PDT 24
Finished Apr 15 03:30:29 PM PDT 24
Peak memory 553436 kb
Host smart-a37031c9-a599-4f10-b221-dc8080ad96ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026021044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3026021044
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.2627789711
Short name T1172
Test name
Test status
Simulation time 4766451712 ps
CPU time 33.41 seconds
Started Apr 15 03:28:41 PM PDT 24
Finished Apr 15 03:29:16 PM PDT 24
Peak memory 500824 kb
Host smart-8ee910ef-66ea-4547-9d88-f42aa93f3b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627789711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.2627789711
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.516650959
Short name T602
Test name
Test status
Simulation time 103287391 ps
CPU time 1 seconds
Started Apr 15 03:28:44 PM PDT 24
Finished Apr 15 03:28:46 PM PDT 24
Peak memory 203852 kb
Host smart-4a642efa-d9a0-4f87-82f5-955b40213270
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516650959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt
.516650959
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.1596490120
Short name T883
Test name
Test status
Simulation time 668934290 ps
CPU time 3.81 seconds
Started Apr 15 03:28:46 PM PDT 24
Finished Apr 15 03:28:51 PM PDT 24
Peak memory 203852 kb
Host smart-b9ce9d1f-618d-4d4a-b476-1a7df0f8adda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596490120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
1596490120
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.881695179
Short name T261
Test name
Test status
Simulation time 3296550049 ps
CPU time 78.45 seconds
Started Apr 15 03:28:41 PM PDT 24
Finished Apr 15 03:30:01 PM PDT 24
Peak memory 997076 kb
Host smart-608ff4c1-6da1-42ba-929f-e051f043eaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881695179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.881695179
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.3540326086
Short name T703
Test name
Test status
Simulation time 1151005272 ps
CPU time 4.87 seconds
Started Apr 15 03:28:49 PM PDT 24
Finished Apr 15 03:28:54 PM PDT 24
Peak memory 204004 kb
Host smart-99cb3571-23a0-4d23-8f04-fe4acd6df1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540326086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.3540326086
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.2913219022
Short name T487
Test name
Test status
Simulation time 4314569341 ps
CPU time 19.63 seconds
Started Apr 15 03:28:49 PM PDT 24
Finished Apr 15 03:29:10 PM PDT 24
Peak memory 296476 kb
Host smart-f8f61d6b-8655-4b54-9982-3639e9381cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913219022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.2913219022
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.3329892740
Short name T735
Test name
Test status
Simulation time 46402046 ps
CPU time 0.65 seconds
Started Apr 15 03:28:43 PM PDT 24
Finished Apr 15 03:28:45 PM PDT 24
Peak memory 203664 kb
Host smart-e3378df6-eec9-4628-a5c0-120b6f40da8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329892740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3329892740
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.2986305683
Short name T1037
Test name
Test status
Simulation time 6190697722 ps
CPU time 40.95 seconds
Started Apr 15 03:28:45 PM PDT 24
Finished Apr 15 03:29:27 PM PDT 24
Peak memory 600416 kb
Host smart-fa0a46f2-7cd0-4d11-9f4c-17fa839437f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986305683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.2986305683
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.3715554579
Short name T913
Test name
Test status
Simulation time 2637621954 ps
CPU time 68.39 seconds
Started Apr 15 03:28:42 PM PDT 24
Finished Apr 15 03:29:51 PM PDT 24
Peak memory 400148 kb
Host smart-451da5c4-8b85-4c34-96c8-598990b90b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715554579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.3715554579
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.1370746413
Short name T196
Test name
Test status
Simulation time 34871649012 ps
CPU time 813.56 seconds
Started Apr 15 03:28:48 PM PDT 24
Finished Apr 15 03:42:22 PM PDT 24
Peak memory 1226692 kb
Host smart-7280b82c-c000-428f-82ca-383881b590f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370746413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.1370746413
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.4002479610
Short name T590
Test name
Test status
Simulation time 1083011249 ps
CPU time 8.5 seconds
Started Apr 15 03:28:45 PM PDT 24
Finished Apr 15 03:28:55 PM PDT 24
Peak memory 220396 kb
Host smart-3794c5ab-3957-4d20-add0-c7699a83d372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002479610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.4002479610
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.2382483687
Short name T118
Test name
Test status
Simulation time 134484222 ps
CPU time 0.95 seconds
Started Apr 15 03:28:52 PM PDT 24
Finished Apr 15 03:28:54 PM PDT 24
Peak memory 222136 kb
Host smart-774b600b-31bf-485d-8659-5a0190de44e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382483687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.2382483687
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.1933666910
Short name T321
Test name
Test status
Simulation time 3259610724 ps
CPU time 4.11 seconds
Started Apr 15 03:28:48 PM PDT 24
Finished Apr 15 03:28:53 PM PDT 24
Peak memory 204080 kb
Host smart-bf708e2b-2567-48f1-a060-c69ff205a2a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933666910 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.1933666910
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.2644264841
Short name T1164
Test name
Test status
Simulation time 10202976066 ps
CPU time 12.34 seconds
Started Apr 15 03:28:48 PM PDT 24
Finished Apr 15 03:29:01 PM PDT 24
Peak memory 264216 kb
Host smart-c492a4bb-43dc-44d3-8f99-36d09b9e4edd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644264841 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.2644264841
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.3184813777
Short name T463
Test name
Test status
Simulation time 10055409196 ps
CPU time 76.1 seconds
Started Apr 15 03:28:54 PM PDT 24
Finished Apr 15 03:30:12 PM PDT 24
Peak memory 554780 kb
Host smart-d006a2ae-1e43-4eab-9beb-3135cbdc8c62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184813777 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.3184813777
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.127794462
Short name T1316
Test name
Test status
Simulation time 547629357 ps
CPU time 2.36 seconds
Started Apr 15 03:28:54 PM PDT 24
Finished Apr 15 03:28:58 PM PDT 24
Peak memory 204008 kb
Host smart-2a46bfaa-180b-4e7f-be38-254059c79b88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127794462 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.i2c_target_hrst.127794462
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.2618365160
Short name T610
Test name
Test status
Simulation time 1004243287 ps
CPU time 5 seconds
Started Apr 15 03:28:48 PM PDT 24
Finished Apr 15 03:28:54 PM PDT 24
Peak memory 210936 kb
Host smart-3a21085d-95e6-4475-9dee-c8cca5c21df4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618365160 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.2618365160
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3603438025
Short name T1123
Test name
Test status
Simulation time 22489213680 ps
CPU time 57.82 seconds
Started Apr 15 03:28:46 PM PDT 24
Finished Apr 15 03:29:45 PM PDT 24
Peak memory 881764 kb
Host smart-56dcacbf-4470-4782-93df-38e04a972337
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603438025 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3603438025
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.2544769048
Short name T756
Test name
Test status
Simulation time 1104368565 ps
CPU time 13.74 seconds
Started Apr 15 03:28:46 PM PDT 24
Finished Apr 15 03:29:01 PM PDT 24
Peak memory 204008 kb
Host smart-18e90411-29d2-4a22-899a-eec2354a3f69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544769048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.2544769048
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.710532887
Short name T969
Test name
Test status
Simulation time 6200681969 ps
CPU time 10.97 seconds
Started Apr 15 03:28:44 PM PDT 24
Finished Apr 15 03:28:56 PM PDT 24
Peak memory 212844 kb
Host smart-616b4a38-0998-45a4-89fa-5b5b96290dc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710532887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_rd.710532887
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.396023649
Short name T1090
Test name
Test status
Simulation time 37373900802 ps
CPU time 168.39 seconds
Started Apr 15 03:28:44 PM PDT 24
Finished Apr 15 03:31:34 PM PDT 24
Peak memory 2199344 kb
Host smart-98a49a8a-e51d-4a8b-8c5e-cde04fe08b87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396023649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_wr.396023649
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.3271649966
Short name T1357
Test name
Test status
Simulation time 34010397247 ps
CPU time 233.37 seconds
Started Apr 15 03:28:45 PM PDT 24
Finished Apr 15 03:32:40 PM PDT 24
Peak memory 1670760 kb
Host smart-f76f944d-8e67-4b81-9f64-13ee8d162a6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271649966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.3271649966
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.1684257482
Short name T565
Test name
Test status
Simulation time 20232119072 ps
CPU time 6.91 seconds
Started Apr 15 03:28:50 PM PDT 24
Finished Apr 15 03:28:58 PM PDT 24
Peak memory 220240 kb
Host smart-569b28b4-2ac5-4dee-a634-6f381e3570c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684257482 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.1684257482
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.670741068
Short name T528
Test name
Test status
Simulation time 18951892 ps
CPU time 0.62 seconds
Started Apr 15 03:32:28 PM PDT 24
Finished Apr 15 03:32:30 PM PDT 24
Peak memory 203556 kb
Host smart-fc22627f-fa58-45c5-b7ad-530dc8ca47ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670741068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.670741068
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.3937872404
Short name T667
Test name
Test status
Simulation time 291216720 ps
CPU time 1.36 seconds
Started Apr 15 03:32:20 PM PDT 24
Finished Apr 15 03:32:22 PM PDT 24
Peak memory 212280 kb
Host smart-046a0b8e-8c90-4101-9a9a-f39c83b023be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937872404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.3937872404
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.2866321716
Short name T1131
Test name
Test status
Simulation time 1435686508 ps
CPU time 5.53 seconds
Started Apr 15 03:32:22 PM PDT 24
Finished Apr 15 03:32:29 PM PDT 24
Peak memory 267784 kb
Host smart-f1d1d5ef-117f-446d-9852-b6e88ef2b458
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866321716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.2866321716
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.2119020409
Short name T564
Test name
Test status
Simulation time 3764313638 ps
CPU time 44.39 seconds
Started Apr 15 03:32:22 PM PDT 24
Finished Apr 15 03:33:08 PM PDT 24
Peak memory 280068 kb
Host smart-148f6445-6a10-4183-8efe-30f3e3e32ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119020409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.2119020409
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.3749626762
Short name T1059
Test name
Test status
Simulation time 13161241427 ps
CPU time 134.67 seconds
Started Apr 15 03:32:21 PM PDT 24
Finished Apr 15 03:34:37 PM PDT 24
Peak memory 642920 kb
Host smart-b842417d-cfdd-426d-8899-58ea8eb92748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749626762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.3749626762
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.4095969066
Short name T1191
Test name
Test status
Simulation time 140058201 ps
CPU time 0.82 seconds
Started Apr 15 03:32:22 PM PDT 24
Finished Apr 15 03:32:23 PM PDT 24
Peak memory 203728 kb
Host smart-885d6dad-8795-4224-9f43-2919bdd011dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095969066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.4095969066
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.805492116
Short name T629
Test name
Test status
Simulation time 527011680 ps
CPU time 7.11 seconds
Started Apr 15 03:32:18 PM PDT 24
Finished Apr 15 03:32:26 PM PDT 24
Peak memory 224380 kb
Host smart-c8f5755e-227f-4a90-ab67-864ffa902779
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805492116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.
805492116
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.2942464045
Short name T934
Test name
Test status
Simulation time 4560185748 ps
CPU time 128.69 seconds
Started Apr 15 03:32:21 PM PDT 24
Finished Apr 15 03:34:31 PM PDT 24
Peak memory 1281216 kb
Host smart-a7eedc59-a215-470c-870c-ed9f27d2cae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942464045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.2942464045
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.2221227343
Short name T1016
Test name
Test status
Simulation time 2441387373 ps
CPU time 10.17 seconds
Started Apr 15 03:32:27 PM PDT 24
Finished Apr 15 03:32:37 PM PDT 24
Peak memory 204016 kb
Host smart-02eaf68b-f597-4acb-81aa-f5f18af6c020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221227343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.2221227343
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.468566760
Short name T954
Test name
Test status
Simulation time 2631547826 ps
CPU time 52.76 seconds
Started Apr 15 03:32:30 PM PDT 24
Finished Apr 15 03:33:23 PM PDT 24
Peak memory 240540 kb
Host smart-f5caa941-b517-4630-965c-15d9e7a1a945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468566760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.468566760
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.1615652921
Short name T214
Test name
Test status
Simulation time 103013853 ps
CPU time 0.67 seconds
Started Apr 15 03:32:21 PM PDT 24
Finished Apr 15 03:32:22 PM PDT 24
Peak memory 203664 kb
Host smart-c1c69e97-2f77-436a-a8e1-ae5adfd493c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615652921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.1615652921
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.1447226152
Short name T1129
Test name
Test status
Simulation time 27085884269 ps
CPU time 76.08 seconds
Started Apr 15 03:32:21 PM PDT 24
Finished Apr 15 03:33:38 PM PDT 24
Peak memory 281152 kb
Host smart-f0aa4969-a151-4e14-b614-8d5aecdc60f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447226152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.1447226152
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.588255277
Short name T779
Test name
Test status
Simulation time 6622741346 ps
CPU time 33.58 seconds
Started Apr 15 03:32:21 PM PDT 24
Finished Apr 15 03:32:55 PM PDT 24
Peak memory 386108 kb
Host smart-d4201a5f-b342-4376-8a94-db765b378ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588255277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.588255277
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.2138929408
Short name T193
Test name
Test status
Simulation time 72533352630 ps
CPU time 414.52 seconds
Started Apr 15 03:32:21 PM PDT 24
Finished Apr 15 03:39:17 PM PDT 24
Peak memory 1398156 kb
Host smart-de49a2a9-aa20-4495-90a8-f90b0eb8615d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138929408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.2138929408
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.3752592554
Short name T1105
Test name
Test status
Simulation time 1012895451 ps
CPU time 23.34 seconds
Started Apr 15 03:32:23 PM PDT 24
Finished Apr 15 03:32:47 PM PDT 24
Peak memory 212196 kb
Host smart-f578b0f0-40af-4875-b6bb-077d0f7dd313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752592554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.3752592554
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.3068151556
Short name T1201
Test name
Test status
Simulation time 5472242781 ps
CPU time 4.68 seconds
Started Apr 15 03:32:27 PM PDT 24
Finished Apr 15 03:32:32 PM PDT 24
Peak memory 204096 kb
Host smart-12960d06-761e-4f29-8f7f-ce995ca90f1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068151556 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3068151556
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.1651658127
Short name T53
Test name
Test status
Simulation time 10469020998 ps
CPU time 13.37 seconds
Started Apr 15 03:32:25 PM PDT 24
Finished Apr 15 03:32:39 PM PDT 24
Peak memory 274616 kb
Host smart-20303f92-1b0f-4d69-8b2a-3aaeddabbfa3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651658127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.1651658127
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.645819557
Short name T879
Test name
Test status
Simulation time 10298102448 ps
CPU time 14.77 seconds
Started Apr 15 03:32:24 PM PDT 24
Finished Apr 15 03:32:40 PM PDT 24
Peak memory 313888 kb
Host smart-8a3ba543-835a-4ff4-9166-1b6e06f06ede
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645819557 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_fifo_reset_tx.645819557
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.4015291010
Short name T857
Test name
Test status
Simulation time 1484705891 ps
CPU time 2.46 seconds
Started Apr 15 03:32:32 PM PDT 24
Finished Apr 15 03:32:36 PM PDT 24
Peak memory 203972 kb
Host smart-65e4b381-0c79-47cf-ae48-edee940ef1b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015291010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.4015291010
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.2640770036
Short name T125
Test name
Test status
Simulation time 2170323699 ps
CPU time 3.1 seconds
Started Apr 15 03:32:23 PM PDT 24
Finished Apr 15 03:32:27 PM PDT 24
Peak memory 204084 kb
Host smart-b77ee836-983b-48b3-9cd5-15740baca6df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640770036 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.2640770036
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.414779185
Short name T22
Test name
Test status
Simulation time 7639541529 ps
CPU time 16.98 seconds
Started Apr 15 03:32:23 PM PDT 24
Finished Apr 15 03:32:41 PM PDT 24
Peak memory 329412 kb
Host smart-8e5b6d53-9cfa-4d21-95dc-469ec57c043e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414779185 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.414779185
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.4100562237
Short name T388
Test name
Test status
Simulation time 11978006824 ps
CPU time 68.17 seconds
Started Apr 15 03:32:20 PM PDT 24
Finished Apr 15 03:33:28 PM PDT 24
Peak memory 204068 kb
Host smart-eeb482e4-0ebb-4eef-9ba9-958ba2c4ecee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100562237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.4100562237
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.2685668858
Short name T612
Test name
Test status
Simulation time 4506131867 ps
CPU time 17.34 seconds
Started Apr 15 03:32:22 PM PDT 24
Finished Apr 15 03:32:40 PM PDT 24
Peak memory 223228 kb
Host smart-33369e22-1d83-477a-b55f-f687c502b531
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685668858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.2685668858
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.3867460125
Short name T1342
Test name
Test status
Simulation time 32745004110 ps
CPU time 97.86 seconds
Started Apr 15 03:32:18 PM PDT 24
Finished Apr 15 03:33:56 PM PDT 24
Peak memory 1621992 kb
Host smart-46904daf-ed7f-4668-b777-f920cd96c106
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867460125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.3867460125
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.1126273523
Short name T1351
Test name
Test status
Simulation time 8059916640 ps
CPU time 17.11 seconds
Started Apr 15 03:32:21 PM PDT 24
Finished Apr 15 03:32:39 PM PDT 24
Peak memory 355188 kb
Host smart-be8cc80b-5b6c-4484-9a01-d87240be38d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126273523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.1126273523
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.4293147349
Short name T248
Test name
Test status
Simulation time 1097468000 ps
CPU time 5.77 seconds
Started Apr 15 03:32:24 PM PDT 24
Finished Apr 15 03:32:31 PM PDT 24
Peak memory 218952 kb
Host smart-df57857c-e3ab-4ad1-9b93-71140cdb479c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293147349 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.4293147349
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.2238071838
Short name T107
Test name
Test status
Simulation time 66971923 ps
CPU time 0.59 seconds
Started Apr 15 03:32:44 PM PDT 24
Finished Apr 15 03:32:45 PM PDT 24
Peak memory 203580 kb
Host smart-2e33f8d9-b9df-4613-93d1-ba375ce22880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238071838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2238071838
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.2209094471
Short name T1338
Test name
Test status
Simulation time 206486305 ps
CPU time 1.4 seconds
Started Apr 15 03:32:30 PM PDT 24
Finished Apr 15 03:32:32 PM PDT 24
Peak memory 212268 kb
Host smart-0a449b16-e3ce-4f7f-bfb2-a07ebdc84d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209094471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.2209094471
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.4144331497
Short name T598
Test name
Test status
Simulation time 781045574 ps
CPU time 9.25 seconds
Started Apr 15 03:32:29 PM PDT 24
Finished Apr 15 03:32:39 PM PDT 24
Peak memory 272956 kb
Host smart-581d0859-5b14-4abb-88e7-0f77a9824226
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144331497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.4144331497
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.1107919869
Short name T688
Test name
Test status
Simulation time 1909653794 ps
CPU time 56.24 seconds
Started Apr 15 03:32:28 PM PDT 24
Finished Apr 15 03:33:25 PM PDT 24
Peak memory 621696 kb
Host smart-0193be4e-3c46-4554-8a6f-212dd55062e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107919869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.1107919869
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.3223749018
Short name T1094
Test name
Test status
Simulation time 16526465469 ps
CPU time 44.3 seconds
Started Apr 15 03:32:26 PM PDT 24
Finished Apr 15 03:33:11 PM PDT 24
Peak memory 532136 kb
Host smart-a3f05c3a-cc41-4ffc-9b2c-c8f3d9ffbf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223749018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.3223749018
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.3717478393
Short name T1038
Test name
Test status
Simulation time 200129764 ps
CPU time 0.87 seconds
Started Apr 15 03:32:27 PM PDT 24
Finished Apr 15 03:32:29 PM PDT 24
Peak memory 203724 kb
Host smart-f563cbea-7c6c-4262-96a1-be9b3895c92f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717478393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.3717478393
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.2531534434
Short name T816
Test name
Test status
Simulation time 584767627 ps
CPU time 4.27 seconds
Started Apr 15 03:32:26 PM PDT 24
Finished Apr 15 03:32:31 PM PDT 24
Peak memory 228544 kb
Host smart-3b2e594e-acd6-4bbe-a1df-6687f8484376
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531534434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.2531534434
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.1989892607
Short name T94
Test name
Test status
Simulation time 3893400137 ps
CPU time 112.79 seconds
Started Apr 15 03:32:27 PM PDT 24
Finished Apr 15 03:34:20 PM PDT 24
Peak memory 1150976 kb
Host smart-ffb5c0e6-f26c-4147-9cc1-8dd20cb5a6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989892607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.1989892607
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.1342715902
Short name T68
Test name
Test status
Simulation time 717737430 ps
CPU time 12.55 seconds
Started Apr 15 03:32:34 PM PDT 24
Finished Apr 15 03:32:47 PM PDT 24
Peak memory 203944 kb
Host smart-95519be8-9b5d-48af-85d9-5ca9afd8f09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342715902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.1342715902
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.1317533483
Short name T1181
Test name
Test status
Simulation time 3817993008 ps
CPU time 19.4 seconds
Started Apr 15 03:32:36 PM PDT 24
Finished Apr 15 03:32:56 PM PDT 24
Peak memory 333356 kb
Host smart-b20f9b8d-7948-4ab4-b973-4394470f7efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317533483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.1317533483
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.3992994658
Short name T210
Test name
Test status
Simulation time 47244442 ps
CPU time 0.64 seconds
Started Apr 15 03:32:28 PM PDT 24
Finished Apr 15 03:32:29 PM PDT 24
Peak memory 203652 kb
Host smart-26f8f6cc-f2ab-4822-8b13-3abdfa856409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992994658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.3992994658
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3885803271
Short name T952
Test name
Test status
Simulation time 6757106769 ps
CPU time 25.97 seconds
Started Apr 15 03:32:32 PM PDT 24
Finished Apr 15 03:32:59 PM PDT 24
Peak memory 452548 kb
Host smart-1bfb8b3c-d546-44ed-b56f-e524825dca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885803271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3885803271
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.3011282136
Short name T299
Test name
Test status
Simulation time 1151130344 ps
CPU time 52.17 seconds
Started Apr 15 03:32:30 PM PDT 24
Finished Apr 15 03:33:23 PM PDT 24
Peak memory 284020 kb
Host smart-424bf446-6c90-42eb-8386-051127b36076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011282136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.3011282136
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.3957385267
Short name T265
Test name
Test status
Simulation time 27971022921 ps
CPU time 198.39 seconds
Started Apr 15 03:32:34 PM PDT 24
Finished Apr 15 03:35:53 PM PDT 24
Peak memory 794120 kb
Host smart-e816f1c3-a017-42fe-967a-dedb1af1a8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957385267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.3957385267
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.512381769
Short name T200
Test name
Test status
Simulation time 311494382 ps
CPU time 13.12 seconds
Started Apr 15 03:32:31 PM PDT 24
Finished Apr 15 03:32:45 PM PDT 24
Peak memory 212156 kb
Host smart-77603464-215e-4ee2-8c63-378c653ccfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512381769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.512381769
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.2743949169
Short name T1235
Test name
Test status
Simulation time 936098679 ps
CPU time 4.06 seconds
Started Apr 15 03:32:45 PM PDT 24
Finished Apr 15 03:32:50 PM PDT 24
Peak memory 203984 kb
Host smart-ba25de83-a283-43d5-8f86-69727f5ab422
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743949169 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.2743949169
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.1298916113
Short name T658
Test name
Test status
Simulation time 10029726534 ps
CPU time 58.04 seconds
Started Apr 15 03:32:31 PM PDT 24
Finished Apr 15 03:33:30 PM PDT 24
Peak memory 477484 kb
Host smart-5a65570e-96cd-46d7-b06a-6525308e0857
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298916113 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.1298916113
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.2587345925
Short name T56
Test name
Test status
Simulation time 10100280023 ps
CPU time 89.87 seconds
Started Apr 15 03:32:45 PM PDT 24
Finished Apr 15 03:34:15 PM PDT 24
Peak memory 583092 kb
Host smart-494e4f46-0505-49a5-9f3b-cb5d536572e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587345925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.2587345925
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.3323949341
Short name T664
Test name
Test status
Simulation time 1709193651 ps
CPU time 2.42 seconds
Started Apr 15 03:32:37 PM PDT 24
Finished Apr 15 03:32:40 PM PDT 24
Peak memory 203968 kb
Host smart-fc0331c2-9260-4ed4-a3bc-c2b8d5ce0225
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323949341 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.3323949341
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.2420157483
Short name T793
Test name
Test status
Simulation time 3346845889 ps
CPU time 3.81 seconds
Started Apr 15 03:32:30 PM PDT 24
Finished Apr 15 03:32:34 PM PDT 24
Peak memory 204092 kb
Host smart-22cd916a-e9be-420b-95cd-bbce49d81b70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420157483 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.2420157483
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.3377353323
Short name T834
Test name
Test status
Simulation time 13888849523 ps
CPU time 149.97 seconds
Started Apr 15 03:32:35 PM PDT 24
Finished Apr 15 03:35:05 PM PDT 24
Peak memory 1907088 kb
Host smart-1b525724-a759-4e06-b648-7a1b28ce8f7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377353323 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.3377353323
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.762839943
Short name T1197
Test name
Test status
Simulation time 700258998 ps
CPU time 10.32 seconds
Started Apr 15 03:32:31 PM PDT 24
Finished Apr 15 03:32:42 PM PDT 24
Peak memory 203980 kb
Host smart-cd279dd4-95d5-479c-b9e7-69ed67152f75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762839943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_tar
get_smoke.762839943
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.152865285
Short name T902
Test name
Test status
Simulation time 1852088739 ps
CPU time 9.83 seconds
Started Apr 15 03:32:49 PM PDT 24
Finished Apr 15 03:32:59 PM PDT 24
Peak memory 204316 kb
Host smart-44734198-589e-4f29-b29d-889786534333
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152865285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c
_target_stress_rd.152865285
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.3033012878
Short name T1179
Test name
Test status
Simulation time 12277290327 ps
CPU time 4.56 seconds
Started Apr 15 03:32:32 PM PDT 24
Finished Apr 15 03:32:37 PM PDT 24
Peak memory 204004 kb
Host smart-98bf46d8-0dfc-44e9-8a5e-a5358f7c39d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033012878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.3033012878
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.2616035042
Short name T1182
Test name
Test status
Simulation time 12890963486 ps
CPU time 182.95 seconds
Started Apr 15 03:32:32 PM PDT 24
Finished Apr 15 03:35:36 PM PDT 24
Peak memory 1591512 kb
Host smart-b4478ce4-d2f4-4e57-b773-c010f5dc98e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616035042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.2616035042
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.3105403478
Short name T1287
Test name
Test status
Simulation time 1079133130 ps
CPU time 5.82 seconds
Started Apr 15 03:32:31 PM PDT 24
Finished Apr 15 03:32:38 PM PDT 24
Peak memory 204012 kb
Host smart-78719ef7-1d84-428b-b8db-dd5bc4b8491f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105403478 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.3105403478
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.293279978
Short name T403
Test name
Test status
Simulation time 19231789 ps
CPU time 0.64 seconds
Started Apr 15 03:32:49 PM PDT 24
Finished Apr 15 03:32:51 PM PDT 24
Peak memory 203612 kb
Host smart-767bacb9-3346-4d6b-8404-837e6f725110
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293279978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.293279978
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.772092228
Short name T300
Test name
Test status
Simulation time 197086793 ps
CPU time 1.39 seconds
Started Apr 15 03:32:38 PM PDT 24
Finished Apr 15 03:32:40 PM PDT 24
Peak memory 212300 kb
Host smart-20de0dca-27a8-4510-912d-579bd18ff579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772092228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.772092228
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.1372674166
Short name T378
Test name
Test status
Simulation time 390148464 ps
CPU time 6.01 seconds
Started Apr 15 03:32:45 PM PDT 24
Finished Apr 15 03:32:51 PM PDT 24
Peak memory 273924 kb
Host smart-246726fa-4005-423c-a9ae-247b498ebf83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372674166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.1372674166
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.3515397130
Short name T581
Test name
Test status
Simulation time 28164811399 ps
CPU time 71.23 seconds
Started Apr 15 03:32:39 PM PDT 24
Finished Apr 15 03:33:51 PM PDT 24
Peak memory 658560 kb
Host smart-6af77dc6-8957-4185-bf74-186fe8b04e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515397130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.3515397130
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.3434932266
Short name T1100
Test name
Test status
Simulation time 1246165399 ps
CPU time 30.15 seconds
Started Apr 15 03:32:35 PM PDT 24
Finished Apr 15 03:33:06 PM PDT 24
Peak memory 316036 kb
Host smart-b95f4610-7aac-422b-a5e1-42844bfd0dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434932266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.3434932266
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.2161347045
Short name T539
Test name
Test status
Simulation time 891581532 ps
CPU time 1.15 seconds
Started Apr 15 03:32:38 PM PDT 24
Finished Apr 15 03:32:40 PM PDT 24
Peak memory 203888 kb
Host smart-6c80f838-054c-4e33-b9e8-603342e44d19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161347045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.2161347045
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.72291183
Short name T678
Test name
Test status
Simulation time 305142345 ps
CPU time 3.62 seconds
Started Apr 15 03:32:37 PM PDT 24
Finished Apr 15 03:32:42 PM PDT 24
Peak memory 203888 kb
Host smart-2d3573b4-83ba-4b7c-9636-eb658859cb21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72291183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.72291183
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.658504041
Short name T810
Test name
Test status
Simulation time 2621348936 ps
CPU time 70.17 seconds
Started Apr 15 03:32:45 PM PDT 24
Finished Apr 15 03:33:56 PM PDT 24
Peak memory 835876 kb
Host smart-09c8e915-2e52-4a7b-bb94-155f1f9a9370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658504041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.658504041
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.570269271
Short name T597
Test name
Test status
Simulation time 207056166 ps
CPU time 2.88 seconds
Started Apr 15 03:32:47 PM PDT 24
Finished Apr 15 03:32:50 PM PDT 24
Peak memory 204004 kb
Host smart-a83f9090-eb62-46fc-8926-1a577b5f5ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570269271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.570269271
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.675815893
Short name T1195
Test name
Test status
Simulation time 1207503652 ps
CPU time 19.97 seconds
Started Apr 15 03:32:48 PM PDT 24
Finished Apr 15 03:33:09 PM PDT 24
Peak memory 332628 kb
Host smart-df338bb8-fa61-4149-b8ad-fff664d5e7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675815893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.675815893
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.505139902
Short name T1242
Test name
Test status
Simulation time 19485009 ps
CPU time 0.65 seconds
Started Apr 15 03:32:35 PM PDT 24
Finished Apr 15 03:32:37 PM PDT 24
Peak memory 203648 kb
Host smart-5c8aa67c-e547-4cfb-bb3a-eed3dcebf6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505139902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.505139902
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1584385425
Short name T218
Test name
Test status
Simulation time 13140243943 ps
CPU time 254.4 seconds
Started Apr 15 03:32:38 PM PDT 24
Finished Apr 15 03:36:54 PM PDT 24
Peak memory 212236 kb
Host smart-ddc886a7-8516-4de5-adc7-4c1d1795cae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584385425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1584385425
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.4005736551
Short name T1160
Test name
Test status
Simulation time 6592190017 ps
CPU time 26.67 seconds
Started Apr 15 03:32:36 PM PDT 24
Finished Apr 15 03:33:03 PM PDT 24
Peak memory 329308 kb
Host smart-325b3b38-d6c3-4824-8359-2a065bdd752c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005736551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.4005736551
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.620213424
Short name T136
Test name
Test status
Simulation time 53945981650 ps
CPU time 2940.01 seconds
Started Apr 15 03:32:39 PM PDT 24
Finished Apr 15 04:21:40 PM PDT 24
Peak memory 4346408 kb
Host smart-96c6b3bf-dbc4-410e-a721-8e509ae8469f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620213424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.620213424
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.1332972311
Short name T1186
Test name
Test status
Simulation time 2538786221 ps
CPU time 24.43 seconds
Started Apr 15 03:32:39 PM PDT 24
Finished Apr 15 03:33:04 PM PDT 24
Peak memory 212208 kb
Host smart-ea18996e-c4aa-4de5-aa61-c5a8c83b443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332972311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.1332972311
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.411211271
Short name T591
Test name
Test status
Simulation time 661598855 ps
CPU time 3.05 seconds
Started Apr 15 03:32:43 PM PDT 24
Finished Apr 15 03:32:46 PM PDT 24
Peak memory 203984 kb
Host smart-ce3febad-d5d9-4c55-b856-c9ebc204bc45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411211271 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.411211271
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.2732351454
Short name T586
Test name
Test status
Simulation time 10056502509 ps
CPU time 69.08 seconds
Started Apr 15 03:32:44 PM PDT 24
Finished Apr 15 03:33:54 PM PDT 24
Peak memory 436068 kb
Host smart-7ea5de07-f259-40b1-8fd0-799aa1684240
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732351454 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.2732351454
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.60922281
Short name T414
Test name
Test status
Simulation time 10222187621 ps
CPU time 18.6 seconds
Started Apr 15 03:32:44 PM PDT 24
Finished Apr 15 03:33:04 PM PDT 24
Peak memory 288152 kb
Host smart-7b7ce4ac-3a15-4c7a-8caf-78db10029305
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60922281 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 32.i2c_target_fifo_reset_tx.60922281
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3157261289
Short name T831
Test name
Test status
Simulation time 688979693 ps
CPU time 2.08 seconds
Started Apr 15 03:32:42 PM PDT 24
Finished Apr 15 03:32:45 PM PDT 24
Peak memory 203916 kb
Host smart-e22aeef8-9a4f-472c-8a5e-12c7534cb798
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157261289 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3157261289
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.859996235
Short name T593
Test name
Test status
Simulation time 2714332937 ps
CPU time 3.55 seconds
Started Apr 15 03:32:40 PM PDT 24
Finished Apr 15 03:32:44 PM PDT 24
Peak memory 204032 kb
Host smart-18dcb7ff-4b01-40ad-90b2-7cb522b49aa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859996235 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_intr_smoke.859996235
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.1000276476
Short name T535
Test name
Test status
Simulation time 22569781902 ps
CPU time 6 seconds
Started Apr 15 03:32:39 PM PDT 24
Finished Apr 15 03:32:45 PM PDT 24
Peak memory 204056 kb
Host smart-9e80d9c1-cc72-4558-a320-4513fd6dd101
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000276476 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.1000276476
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.4195808928
Short name T686
Test name
Test status
Simulation time 1105250299 ps
CPU time 16.73 seconds
Started Apr 15 03:32:40 PM PDT 24
Finished Apr 15 03:32:58 PM PDT 24
Peak memory 204000 kb
Host smart-f03f0e4d-88bf-41f4-89f8-6e5e01546ee5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195808928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.4195808928
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.1909456895
Short name T817
Test name
Test status
Simulation time 5085478496 ps
CPU time 19.49 seconds
Started Apr 15 03:32:39 PM PDT 24
Finished Apr 15 03:32:59 PM PDT 24
Peak memory 220496 kb
Host smart-e84a54c2-4e2a-4a83-8abb-60a472d01551
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909456895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.1909456895
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.2862801733
Short name T1069
Test name
Test status
Simulation time 60986550231 ps
CPU time 301.51 seconds
Started Apr 15 03:32:40 PM PDT 24
Finished Apr 15 03:37:42 PM PDT 24
Peak memory 2737492 kb
Host smart-92853165-ab10-4c7f-b2e5-68a4b16206ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862801733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.2862801733
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1644809558
Short name T971
Test name
Test status
Simulation time 13497876362 ps
CPU time 74.55 seconds
Started Apr 15 03:32:39 PM PDT 24
Finished Apr 15 03:33:54 PM PDT 24
Peak memory 902668 kb
Host smart-037b7664-f165-4714-9d52-4836c9d65e9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644809558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1644809558
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.548055829
Short name T1335
Test name
Test status
Simulation time 10302411567 ps
CPU time 6.29 seconds
Started Apr 15 03:32:42 PM PDT 24
Finished Apr 15 03:32:48 PM PDT 24
Peak memory 204068 kb
Host smart-05934e89-da84-4a49-abb3-db581a5860fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548055829 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_timeout.548055829
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.3123977249
Short name T98
Test name
Test status
Simulation time 23254270 ps
CPU time 0.63 seconds
Started Apr 15 03:32:55 PM PDT 24
Finished Apr 15 03:32:56 PM PDT 24
Peak memory 203572 kb
Host smart-e61dd53f-9fc5-4a3c-b269-b354124c2545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123977249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.3123977249
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.2195921670
Short name T1255
Test name
Test status
Simulation time 428360676 ps
CPU time 1.8 seconds
Started Apr 15 03:32:46 PM PDT 24
Finished Apr 15 03:32:49 PM PDT 24
Peak memory 212304 kb
Host smart-c4bc27ab-e5ed-46c1-9850-4daec720b925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195921670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.2195921670
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.2505196081
Short name T661
Test name
Test status
Simulation time 1223541558 ps
CPU time 5.93 seconds
Started Apr 15 03:32:48 PM PDT 24
Finished Apr 15 03:32:54 PM PDT 24
Peak memory 269164 kb
Host smart-684b22fc-f530-478a-abf6-71dbedb523d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505196081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.2505196081
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.1215836205
Short name T965
Test name
Test status
Simulation time 2625486987 ps
CPU time 177.89 seconds
Started Apr 15 03:32:50 PM PDT 24
Finished Apr 15 03:35:49 PM PDT 24
Peak memory 722704 kb
Host smart-a6498114-65ba-4b75-9e30-63ea9d9cb3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215836205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.1215836205
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2251800853
Short name T865
Test name
Test status
Simulation time 6709421235 ps
CPU time 56.71 seconds
Started Apr 15 03:32:47 PM PDT 24
Finished Apr 15 03:33:44 PM PDT 24
Peak memory 620892 kb
Host smart-53f283ea-5df1-44e1-9ba9-288c4ae534b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251800853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2251800853
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.3343813401
Short name T691
Test name
Test status
Simulation time 284217227 ps
CPU time 1 seconds
Started Apr 15 03:32:50 PM PDT 24
Finished Apr 15 03:32:51 PM PDT 24
Peak memory 203736 kb
Host smart-42ebab1c-0a4a-4ac6-82b8-33fb3e1b21ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343813401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.3343813401
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.2172083196
Short name T1193
Test name
Test status
Simulation time 387911047 ps
CPU time 5.72 seconds
Started Apr 15 03:32:49 PM PDT 24
Finished Apr 15 03:32:55 PM PDT 24
Peak memory 203968 kb
Host smart-bd73ee61-d255-487f-ae7c-2696a901b59e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172083196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.2172083196
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.1937993609
Short name T1341
Test name
Test status
Simulation time 8596515457 ps
CPU time 130.29 seconds
Started Apr 15 03:32:49 PM PDT 24
Finished Apr 15 03:35:00 PM PDT 24
Peak memory 1253148 kb
Host smart-133457ef-eda2-4b1b-8076-ecdf8d9e205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937993609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.1937993609
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.4210693349
Short name T441
Test name
Test status
Simulation time 1388974094 ps
CPU time 14.43 seconds
Started Apr 15 03:32:57 PM PDT 24
Finished Apr 15 03:33:13 PM PDT 24
Peak memory 203972 kb
Host smart-a0042d13-f8f1-43da-a7d2-a902889c0cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210693349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.4210693349
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1618481235
Short name T369
Test name
Test status
Simulation time 3268807188 ps
CPU time 34.95 seconds
Started Apr 15 03:32:55 PM PDT 24
Finished Apr 15 03:33:30 PM PDT 24
Peak memory 325552 kb
Host smart-bea8dfa9-5c39-4f2b-9138-e05a018c6bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618481235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1618481235
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.3396317061
Short name T481
Test name
Test status
Simulation time 17332048 ps
CPU time 0.67 seconds
Started Apr 15 03:32:48 PM PDT 24
Finished Apr 15 03:32:49 PM PDT 24
Peak memory 203696 kb
Host smart-5ae27902-9d14-4697-911c-6df1bf7a4674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396317061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3396317061
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.4132398514
Short name T1346
Test name
Test status
Simulation time 5200056061 ps
CPU time 52.33 seconds
Started Apr 15 03:32:46 PM PDT 24
Finished Apr 15 03:33:39 PM PDT 24
Peak memory 225748 kb
Host smart-c76415fb-72c5-478f-a0b9-8eda98918a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132398514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.4132398514
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.3839461820
Short name T948
Test name
Test status
Simulation time 3122426486 ps
CPU time 15.14 seconds
Started Apr 15 03:32:50 PM PDT 24
Finished Apr 15 03:33:06 PM PDT 24
Peak memory 293400 kb
Host smart-75ede0b6-bf54-4d30-97b8-e76cd5883d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839461820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.3839461820
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.481115117
Short name T197
Test name
Test status
Simulation time 36381651115 ps
CPU time 338.28 seconds
Started Apr 15 03:32:47 PM PDT 24
Finished Apr 15 03:38:26 PM PDT 24
Peak memory 864272 kb
Host smart-acdcb8ad-1d2d-4882-93fe-4802ec795dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481115117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.481115117
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.1709507384
Short name T701
Test name
Test status
Simulation time 639196762 ps
CPU time 28.11 seconds
Started Apr 15 03:32:48 PM PDT 24
Finished Apr 15 03:33:16 PM PDT 24
Peak memory 212240 kb
Host smart-08eae9e5-dfe1-4708-8619-8e1be852358c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709507384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.1709507384
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.2928861832
Short name T322
Test name
Test status
Simulation time 3811894909 ps
CPU time 4.35 seconds
Started Apr 15 03:32:53 PM PDT 24
Finished Apr 15 03:32:58 PM PDT 24
Peak memory 212256 kb
Host smart-f9a8c1ee-2228-4168-956f-ea516f39cde8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928861832 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.2928861832
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.1352883042
Short name T50
Test name
Test status
Simulation time 10096691896 ps
CPU time 82.22 seconds
Started Apr 15 03:32:52 PM PDT 24
Finished Apr 15 03:34:15 PM PDT 24
Peak memory 498424 kb
Host smart-0b527368-a395-489f-9e52-7a2fd5c397f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352883042 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.1352883042
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.147973958
Short name T1066
Test name
Test status
Simulation time 10059618309 ps
CPU time 100.18 seconds
Started Apr 15 03:32:49 PM PDT 24
Finished Apr 15 03:34:30 PM PDT 24
Peak memory 592296 kb
Host smart-e88b5294-69c3-4af0-8cc7-9c4d26c06e0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147973958 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_fifo_reset_tx.147973958
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.2323271014
Short name T1057
Test name
Test status
Simulation time 1554273158 ps
CPU time 2.25 seconds
Started Apr 15 03:32:50 PM PDT 24
Finished Apr 15 03:32:53 PM PDT 24
Peak memory 203980 kb
Host smart-9538d57a-e3b1-488b-9ad5-b675f1e46b29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323271014 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.2323271014
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.3231001891
Short name T328
Test name
Test status
Simulation time 1385305867 ps
CPU time 3.49 seconds
Started Apr 15 03:32:50 PM PDT 24
Finished Apr 15 03:32:54 PM PDT 24
Peak memory 204348 kb
Host smart-f19ed452-ad64-4607-b608-704127ea11de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231001891 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.3231001891
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.909306377
Short name T468
Test name
Test status
Simulation time 21820489385 ps
CPU time 62.86 seconds
Started Apr 15 03:32:50 PM PDT 24
Finished Apr 15 03:33:54 PM PDT 24
Peak memory 892440 kb
Host smart-905a7bf4-04de-4e19-8386-d5861b97a42b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909306377 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.909306377
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.2555777720
Short name T641
Test name
Test status
Simulation time 843641793 ps
CPU time 11.08 seconds
Started Apr 15 03:32:45 PM PDT 24
Finished Apr 15 03:32:57 PM PDT 24
Peak memory 203952 kb
Host smart-22f179e2-55d6-445a-9d81-f6c51092b497
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555777720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.2555777720
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_all.2846157742
Short name T17
Test name
Test status
Simulation time 30028112861 ps
CPU time 30.79 seconds
Started Apr 15 03:32:49 PM PDT 24
Finished Apr 15 03:33:21 PM PDT 24
Peak memory 250208 kb
Host smart-963234ac-ce6e-4270-b322-6cc4fbefaaa4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846157742 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.i2c_target_stress_all.2846157742
Directory /workspace/33.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.2049039061
Short name T594
Test name
Test status
Simulation time 416702109 ps
CPU time 6.02 seconds
Started Apr 15 03:32:51 PM PDT 24
Finished Apr 15 03:32:57 PM PDT 24
Peak memory 204028 kb
Host smart-c5dc2e80-e757-4b77-9740-d04703610b3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049039061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.2049039061
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.1453072321
Short name T800
Test name
Test status
Simulation time 39693247317 ps
CPU time 707.95 seconds
Started Apr 15 03:32:52 PM PDT 24
Finished Apr 15 03:44:40 PM PDT 24
Peak memory 4928356 kb
Host smart-51566d7f-aa95-4637-b4a0-96fbc806db30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453072321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.1453072321
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.4272329959
Short name T674
Test name
Test status
Simulation time 31734380019 ps
CPU time 659.44 seconds
Started Apr 15 03:32:48 PM PDT 24
Finished Apr 15 03:43:48 PM PDT 24
Peak memory 3672040 kb
Host smart-545cad26-0668-41a0-a146-c7d165653f8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272329959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.4272329959
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.428051767
Short name T583
Test name
Test status
Simulation time 2477861533 ps
CPU time 6.38 seconds
Started Apr 15 03:32:51 PM PDT 24
Finished Apr 15 03:32:58 PM PDT 24
Peak memory 212288 kb
Host smart-43d9fc8f-6d32-40c3-b7bb-a74c8e27c0a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428051767 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_timeout.428051767
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.1804257414
Short name T296
Test name
Test status
Simulation time 26783692 ps
CPU time 0.59 seconds
Started Apr 15 03:33:00 PM PDT 24
Finished Apr 15 03:33:01 PM PDT 24
Peak memory 203588 kb
Host smart-55d7fa48-1dd6-4485-9153-c67aeb98df5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804257414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.1804257414
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.1176678668
Short name T189
Test name
Test status
Simulation time 117171017 ps
CPU time 2.09 seconds
Started Apr 15 03:32:56 PM PDT 24
Finished Apr 15 03:32:59 PM PDT 24
Peak memory 212292 kb
Host smart-a3126ff2-5d05-4f41-87a4-9addeab3b54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176678668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.1176678668
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.114152942
Short name T635
Test name
Test status
Simulation time 1269630109 ps
CPU time 17.55 seconds
Started Apr 15 03:32:56 PM PDT 24
Finished Apr 15 03:33:14 PM PDT 24
Peak memory 264456 kb
Host smart-bc73c246-a1d8-4850-9649-30860167f1b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114152942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empt
y.114152942
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.1403506421
Short name T73
Test name
Test status
Simulation time 3522368122 ps
CPU time 39.07 seconds
Started Apr 15 03:32:57 PM PDT 24
Finished Apr 15 03:33:37 PM PDT 24
Peak memory 459844 kb
Host smart-d3538b65-0fc7-4d74-ad8d-e22ce79be954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403506421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.1403506421
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.3523284550
Short name T1151
Test name
Test status
Simulation time 1662289986 ps
CPU time 54.39 seconds
Started Apr 15 03:32:55 PM PDT 24
Finished Apr 15 03:33:50 PM PDT 24
Peak memory 608844 kb
Host smart-71b03bbb-95f5-4d04-a236-cf40101e8720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523284550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3523284550
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.1914727684
Short name T101
Test name
Test status
Simulation time 86976089 ps
CPU time 0.94 seconds
Started Apr 15 03:32:56 PM PDT 24
Finished Apr 15 03:32:58 PM PDT 24
Peak memory 203728 kb
Host smart-ad38a075-5815-4d43-a45b-5e6a9c6b29a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914727684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.1914727684
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.3527050107
Short name T801
Test name
Test status
Simulation time 135994803 ps
CPU time 7.73 seconds
Started Apr 15 03:32:56 PM PDT 24
Finished Apr 15 03:33:04 PM PDT 24
Peak memory 224204 kb
Host smart-7b95c5ca-07f1-4a37-bcb8-ce7e1d528937
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527050107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.3527050107
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2346532647
Short name T259
Test name
Test status
Simulation time 6193121413 ps
CPU time 79.18 seconds
Started Apr 15 03:33:00 PM PDT 24
Finished Apr 15 03:34:20 PM PDT 24
Peak memory 889520 kb
Host smart-f756e31c-68ec-48ef-b497-b29400fa0ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346532647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2346532647
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.1124211679
Short name T566
Test name
Test status
Simulation time 468996154 ps
CPU time 9.13 seconds
Started Apr 15 03:32:58 PM PDT 24
Finished Apr 15 03:33:08 PM PDT 24
Peak memory 203964 kb
Host smart-8d03a68d-3ad1-4197-a8f6-6b446d26d001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124211679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.1124211679
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.3794963326
Short name T477
Test name
Test status
Simulation time 3358753377 ps
CPU time 21.64 seconds
Started Apr 15 03:32:59 PM PDT 24
Finished Apr 15 03:33:21 PM PDT 24
Peak memory 318948 kb
Host smart-477f1810-9ce5-40b9-add5-10979b7a8ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794963326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.3794963326
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.2102202548
Short name T891
Test name
Test status
Simulation time 19562130 ps
CPU time 0.66 seconds
Started Apr 15 03:32:59 PM PDT 24
Finished Apr 15 03:33:00 PM PDT 24
Peak memory 203680 kb
Host smart-396450bb-3988-4c33-91a3-40893ac4fe6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102202548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.2102202548
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.1378399713
Short name T720
Test name
Test status
Simulation time 6322740469 ps
CPU time 184.95 seconds
Started Apr 15 03:32:53 PM PDT 24
Finished Apr 15 03:35:58 PM PDT 24
Peak memory 1506732 kb
Host smart-659d9378-eda6-4e28-9bbf-0a3dd1a61528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378399713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.1378399713
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.336601651
Short name T234
Test name
Test status
Simulation time 2598989064 ps
CPU time 31.8 seconds
Started Apr 15 03:32:56 PM PDT 24
Finished Apr 15 03:33:29 PM PDT 24
Peak memory 361676 kb
Host smart-80c0b3ec-856c-4780-8964-7cd55501c3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336601651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.336601651
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.1216437502
Short name T1291
Test name
Test status
Simulation time 37016477042 ps
CPU time 1229.26 seconds
Started Apr 15 03:32:54 PM PDT 24
Finished Apr 15 03:53:24 PM PDT 24
Peak memory 1914972 kb
Host smart-41a17ed7-1a3b-4ad0-9068-4f2522190434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216437502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.1216437502
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.3322270103
Short name T648
Test name
Test status
Simulation time 854887184 ps
CPU time 13.95 seconds
Started Apr 15 03:32:58 PM PDT 24
Finished Apr 15 03:33:13 PM PDT 24
Peak memory 212240 kb
Host smart-2fc4d839-1fc7-4801-bbbd-7a82543dbbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322270103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3322270103
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.2550756531
Short name T760
Test name
Test status
Simulation time 724907119 ps
CPU time 3.66 seconds
Started Apr 15 03:32:58 PM PDT 24
Finished Apr 15 03:33:02 PM PDT 24
Peak memory 203992 kb
Host smart-8802d23e-73cc-4708-9821-81c045d215e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550756531 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.2550756531
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.2407406074
Short name T1302
Test name
Test status
Simulation time 10152572616 ps
CPU time 61.89 seconds
Started Apr 15 03:33:00 PM PDT 24
Finished Apr 15 03:34:02 PM PDT 24
Peak memory 466668 kb
Host smart-852b1389-9191-405f-9433-5226f53418a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407406074 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.2407406074
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.521764827
Short name T326
Test name
Test status
Simulation time 10205353186 ps
CPU time 14.71 seconds
Started Apr 15 03:33:03 PM PDT 24
Finished Apr 15 03:33:18 PM PDT 24
Peak memory 281920 kb
Host smart-3e832b31-0da4-4633-903d-3d0026b05094
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521764827 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_fifo_reset_tx.521764827
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.1928929438
Short name T650
Test name
Test status
Simulation time 451422144 ps
CPU time 2.56 seconds
Started Apr 15 03:32:58 PM PDT 24
Finished Apr 15 03:33:01 PM PDT 24
Peak memory 203912 kb
Host smart-201765f1-66a2-4dde-83d2-986d8413cb49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928929438 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.1928929438
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.3723366175
Short name T582
Test name
Test status
Simulation time 4134744451 ps
CPU time 4.76 seconds
Started Apr 15 03:32:57 PM PDT 24
Finished Apr 15 03:33:03 PM PDT 24
Peak memory 212288 kb
Host smart-6557e8d2-8d8d-4611-b303-fcf7581beb5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723366175 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.3723366175
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.3861559929
Short name T61
Test name
Test status
Simulation time 25070982442 ps
CPU time 7.07 seconds
Started Apr 15 03:32:59 PM PDT 24
Finished Apr 15 03:33:07 PM PDT 24
Peak memory 204184 kb
Host smart-e3393a37-46c3-4aa0-8696-dc327e68b621
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861559929 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.3861559929
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.1300151791
Short name T622
Test name
Test status
Simulation time 658792375 ps
CPU time 9.87 seconds
Started Apr 15 03:32:53 PM PDT 24
Finished Apr 15 03:33:04 PM PDT 24
Peak memory 204036 kb
Host smart-90dc5cb7-15d2-439e-922d-d0370ecb78d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300151791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.1300151791
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.1852338936
Short name T503
Test name
Test status
Simulation time 988258238 ps
CPU time 14.71 seconds
Started Apr 15 03:32:57 PM PDT 24
Finished Apr 15 03:33:13 PM PDT 24
Peak memory 219088 kb
Host smart-3bdb10cc-e6da-4649-bc88-e63b3efaef58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852338936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.1852338936
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.2013545808
Short name T640
Test name
Test status
Simulation time 55339766716 ps
CPU time 519.85 seconds
Started Apr 15 03:32:58 PM PDT 24
Finished Apr 15 03:41:39 PM PDT 24
Peak memory 4474256 kb
Host smart-eccafecc-348f-40da-b0bf-eb78c7986e64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013545808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.2013545808
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.3051391351
Short name T771
Test name
Test status
Simulation time 7028725866 ps
CPU time 57.98 seconds
Started Apr 15 03:32:59 PM PDT 24
Finished Apr 15 03:33:58 PM PDT 24
Peak memory 816936 kb
Host smart-47f0d0be-37ec-4619-9f58-f34d956bbba8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051391351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.3051391351
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.646854027
Short name T1165
Test name
Test status
Simulation time 1470830437 ps
CPU time 7.09 seconds
Started Apr 15 03:32:58 PM PDT 24
Finished Apr 15 03:33:06 PM PDT 24
Peak memory 212220 kb
Host smart-19db1859-1888-42ba-be56-093eb844fee0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646854027 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_timeout.646854027
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.3715809403
Short name T391
Test name
Test status
Simulation time 16500962 ps
CPU time 0.61 seconds
Started Apr 15 03:33:11 PM PDT 24
Finished Apr 15 03:33:13 PM PDT 24
Peak memory 203528 kb
Host smart-964ceb63-74e6-4dd3-8f67-034ac8f9fe42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715809403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.3715809403
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.472300419
Short name T99
Test name
Test status
Simulation time 99671296 ps
CPU time 1.38 seconds
Started Apr 15 03:33:05 PM PDT 24
Finished Apr 15 03:33:07 PM PDT 24
Peak memory 212336 kb
Host smart-a688faa6-0b7a-402e-81dd-3e8bc38235b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472300419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.472300419
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1850796024
Short name T1240
Test name
Test status
Simulation time 317828506 ps
CPU time 6.08 seconds
Started Apr 15 03:33:08 PM PDT 24
Finished Apr 15 03:33:15 PM PDT 24
Peak memory 242468 kb
Host smart-25c40c2f-dbea-4791-8ab2-7fbf419dfba5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850796024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1850796024
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.2870303294
Short name T878
Test name
Test status
Simulation time 8320867439 ps
CPU time 64.72 seconds
Started Apr 15 03:33:01 PM PDT 24
Finished Apr 15 03:34:06 PM PDT 24
Peak memory 661888 kb
Host smart-73d5e124-c4e7-44ed-a32e-42e9ada357b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870303294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.2870303294
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.1611742930
Short name T1198
Test name
Test status
Simulation time 1610847096 ps
CPU time 43.82 seconds
Started Apr 15 03:33:01 PM PDT 24
Finished Apr 15 03:33:46 PM PDT 24
Peak memory 588460 kb
Host smart-ae4642b0-e476-4db8-b26d-80abaefc610c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611742930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.1611742930
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.208079419
Short name T1139
Test name
Test status
Simulation time 150568314 ps
CPU time 0.89 seconds
Started Apr 15 03:33:09 PM PDT 24
Finished Apr 15 03:33:10 PM PDT 24
Peak memory 203740 kb
Host smart-598d84e7-adf2-467e-bb00-b8d85517557d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208079419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fm
t.208079419
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.3614650897
Short name T959
Test name
Test status
Simulation time 563546812 ps
CPU time 7 seconds
Started Apr 15 03:33:05 PM PDT 24
Finished Apr 15 03:33:13 PM PDT 24
Peak memory 223304 kb
Host smart-adea12a2-9de7-4f60-beea-dab234ad6b26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614650897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.3614650897
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.2079725601
Short name T554
Test name
Test status
Simulation time 8792779679 ps
CPU time 343.03 seconds
Started Apr 15 03:33:03 PM PDT 24
Finished Apr 15 03:38:46 PM PDT 24
Peak memory 1163728 kb
Host smart-8155f0d3-09d5-410b-967b-738315a04911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079725601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.2079725601
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.1714269499
Short name T341
Test name
Test status
Simulation time 853276985 ps
CPU time 8.59 seconds
Started Apr 15 03:33:09 PM PDT 24
Finished Apr 15 03:33:19 PM PDT 24
Peak memory 203980 kb
Host smart-84118c95-a683-4e05-8ee8-80d46d0baeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714269499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.1714269499
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_override.2613910153
Short name T211
Test name
Test status
Simulation time 87378120 ps
CPU time 0.66 seconds
Started Apr 15 03:33:01 PM PDT 24
Finished Apr 15 03:33:03 PM PDT 24
Peak memory 203660 kb
Host smart-b917584a-2bfe-4031-a4f6-571a90b9085d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613910153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2613910153
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.1012666377
Short name T188
Test name
Test status
Simulation time 1024568069 ps
CPU time 11.02 seconds
Started Apr 15 03:33:05 PM PDT 24
Finished Apr 15 03:33:16 PM PDT 24
Peak memory 214332 kb
Host smart-9fab6180-6273-47d1-8b6f-78931fa5ec54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012666377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.1012666377
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.528770668
Short name T717
Test name
Test status
Simulation time 976037194 ps
CPU time 47.69 seconds
Started Apr 15 03:33:43 PM PDT 24
Finished Apr 15 03:34:32 PM PDT 24
Peak memory 293552 kb
Host smart-241132ab-f813-4fba-9a81-c51a31a77bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528770668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.528770668
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.492200057
Short name T846
Test name
Test status
Simulation time 83094948284 ps
CPU time 1702.29 seconds
Started Apr 15 03:33:03 PM PDT 24
Finished Apr 15 04:01:26 PM PDT 24
Peak memory 3416608 kb
Host smart-52fab9e0-cda5-4533-abfa-074f90951ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492200057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.492200057
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.3040515793
Short name T1358
Test name
Test status
Simulation time 1074823718 ps
CPU time 28.76 seconds
Started Apr 15 03:33:03 PM PDT 24
Finished Apr 15 03:33:32 PM PDT 24
Peak memory 212244 kb
Host smart-cd635332-bd25-4a47-b746-137df6765810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040515793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.3040515793
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.597982451
Short name T290
Test name
Test status
Simulation time 2840583907 ps
CPU time 3.43 seconds
Started Apr 15 03:33:08 PM PDT 24
Finished Apr 15 03:33:12 PM PDT 24
Peak memory 204104 kb
Host smart-90148cda-43b6-4282-923c-9de3e4893040
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597982451 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.597982451
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.3160134138
Short name T977
Test name
Test status
Simulation time 10091238742 ps
CPU time 66.26 seconds
Started Apr 15 03:33:03 PM PDT 24
Finished Apr 15 03:34:10 PM PDT 24
Peak memory 441268 kb
Host smart-26088997-9d76-4370-8442-8b58e397750d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160134138 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.3160134138
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.744841867
Short name T454
Test name
Test status
Simulation time 10096793828 ps
CPU time 25.9 seconds
Started Apr 15 03:33:08 PM PDT 24
Finished Apr 15 03:33:35 PM PDT 24
Peak memory 397624 kb
Host smart-4e0be8ca-1a73-45f4-b0f0-7bbe68ad2b1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744841867 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.744841867
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.1861695597
Short name T483
Test name
Test status
Simulation time 376302641 ps
CPU time 2.11 seconds
Started Apr 15 03:33:08 PM PDT 24
Finished Apr 15 03:33:11 PM PDT 24
Peak memory 204012 kb
Host smart-aaa8cb9a-e142-4e6d-a269-3d1e0ed74483
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861695597 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.1861695597
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.1731652184
Short name T604
Test name
Test status
Simulation time 7925924408 ps
CPU time 4.74 seconds
Started Apr 15 03:33:04 PM PDT 24
Finished Apr 15 03:33:09 PM PDT 24
Peak memory 216248 kb
Host smart-715e60ba-76f4-4aba-9f90-b8891a24d4cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731652184 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.1731652184
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.3130685393
Short name T354
Test name
Test status
Simulation time 12574255546 ps
CPU time 14.31 seconds
Started Apr 15 03:33:04 PM PDT 24
Finished Apr 15 03:33:19 PM PDT 24
Peak memory 399964 kb
Host smart-20c5021a-1742-4350-b4a1-b4b7fc4dd19c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130685393 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.3130685393
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.1592790010
Short name T745
Test name
Test status
Simulation time 989132583 ps
CPU time 37.61 seconds
Started Apr 15 03:33:01 PM PDT 24
Finished Apr 15 03:33:40 PM PDT 24
Peak memory 203968 kb
Host smart-6fec76f5-1f10-4b07-9363-1838446e4de0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592790010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.1592790010
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.2728140260
Short name T376
Test name
Test status
Simulation time 2313720966 ps
CPU time 58.13 seconds
Started Apr 15 03:33:07 PM PDT 24
Finished Apr 15 03:34:06 PM PDT 24
Peak memory 205044 kb
Host smart-de6fc57f-d869-456e-9e0e-8e6c0fafc93f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728140260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.2728140260
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.2659826235
Short name T404
Test name
Test status
Simulation time 16678270042 ps
CPU time 5.65 seconds
Started Apr 15 03:33:12 PM PDT 24
Finished Apr 15 03:33:18 PM PDT 24
Peak memory 204000 kb
Host smart-64c02f97-f157-4816-b9f1-c17dd379a7a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659826235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.2659826235
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.1169815615
Short name T470
Test name
Test status
Simulation time 46139607014 ps
CPU time 1242.4 seconds
Started Apr 15 03:33:05 PM PDT 24
Finished Apr 15 03:53:49 PM PDT 24
Peak memory 2642092 kb
Host smart-41cb55dc-d5d5-426b-afac-1fd581cad548
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169815615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.1169815615
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.3714580678
Short name T743
Test name
Test status
Simulation time 1486667180 ps
CPU time 7.01 seconds
Started Apr 15 03:33:05 PM PDT 24
Finished Apr 15 03:33:13 PM PDT 24
Peak memory 204028 kb
Host smart-14be65d0-2a3b-4a89-af9c-be15ca77f270
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714580678 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.3714580678
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.1742403642
Short name T1161
Test name
Test status
Simulation time 25147447 ps
CPU time 0.6 seconds
Started Apr 15 03:33:17 PM PDT 24
Finished Apr 15 03:33:18 PM PDT 24
Peak memory 203528 kb
Host smart-510a82c4-41e1-4af7-92b2-d797a65ec8f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742403642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.1742403642
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.312629003
Short name T1309
Test name
Test status
Simulation time 364619834 ps
CPU time 1.58 seconds
Started Apr 15 03:33:09 PM PDT 24
Finished Apr 15 03:33:12 PM PDT 24
Peak memory 212308 kb
Host smart-a7c0f025-a85b-475b-bae0-19b5c3c54e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312629003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.312629003
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.3891599903
Short name T1169
Test name
Test status
Simulation time 315985726 ps
CPU time 7.27 seconds
Started Apr 15 03:33:10 PM PDT 24
Finished Apr 15 03:33:18 PM PDT 24
Peak memory 263808 kb
Host smart-2a850bb4-a009-4dd4-bceb-5f9951eb8a9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891599903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.3891599903
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.1163298302
Short name T893
Test name
Test status
Simulation time 7447249012 ps
CPU time 36.96 seconds
Started Apr 15 03:33:13 PM PDT 24
Finished Apr 15 03:33:50 PM PDT 24
Peak memory 482968 kb
Host smart-fed4f475-a9f1-449c-a650-c67585a2099b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163298302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.1163298302
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.404278813
Short name T39
Test name
Test status
Simulation time 2564454418 ps
CPU time 38.69 seconds
Started Apr 15 03:33:10 PM PDT 24
Finished Apr 15 03:33:49 PM PDT 24
Peak memory 510740 kb
Host smart-eb26cdda-ae85-4de3-973d-3251b94ce23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404278813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.404278813
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.4246312297
Short name T1072
Test name
Test status
Simulation time 78923956 ps
CPU time 0.91 seconds
Started Apr 15 03:33:11 PM PDT 24
Finished Apr 15 03:33:13 PM PDT 24
Peak memory 203740 kb
Host smart-e6370717-c5a8-458c-ae8a-3c64a4696aa3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246312297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.4246312297
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.1632632487
Short name T223
Test name
Test status
Simulation time 469875311 ps
CPU time 3.44 seconds
Started Apr 15 03:33:14 PM PDT 24
Finished Apr 15 03:33:18 PM PDT 24
Peak memory 220444 kb
Host smart-472e4c8d-6ccf-4f92-982c-ed2e144bbdf5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632632487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.1632632487
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.709340912
Short name T426
Test name
Test status
Simulation time 3298664313 ps
CPU time 221.87 seconds
Started Apr 15 03:33:10 PM PDT 24
Finished Apr 15 03:36:52 PM PDT 24
Peak memory 907764 kb
Host smart-62b46261-761a-477a-af3c-23ca9e43f8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709340912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.709340912
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.403196931
Short name T486
Test name
Test status
Simulation time 1394808366 ps
CPU time 13.98 seconds
Started Apr 15 03:33:18 PM PDT 24
Finished Apr 15 03:33:33 PM PDT 24
Peak memory 203972 kb
Host smart-9d065c33-9c28-4381-9651-23b4496be1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403196931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.403196931
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.2572032990
Short name T1208
Test name
Test status
Simulation time 3105831692 ps
CPU time 69.25 seconds
Started Apr 15 03:33:18 PM PDT 24
Finished Apr 15 03:34:28 PM PDT 24
Peak memory 321136 kb
Host smart-fdaaf766-f1f8-4230-91c5-25b584ef7929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572032990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.2572032990
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.383795605
Short name T950
Test name
Test status
Simulation time 29943697 ps
CPU time 0.67 seconds
Started Apr 15 03:33:08 PM PDT 24
Finished Apr 15 03:33:10 PM PDT 24
Peak memory 203656 kb
Host smart-0afc2e52-055b-4fbe-ad37-f027739ebed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383795605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.383795605
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.2845297647
Short name T752
Test name
Test status
Simulation time 2821706737 ps
CPU time 32.59 seconds
Started Apr 15 03:33:11 PM PDT 24
Finished Apr 15 03:33:44 PM PDT 24
Peak memory 359796 kb
Host smart-7f52b5a1-315a-4d7e-95d5-087c9e36ce9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845297647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.2845297647
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.3042123910
Short name T730
Test name
Test status
Simulation time 4574249846 ps
CPU time 25.81 seconds
Started Apr 15 03:33:10 PM PDT 24
Finished Apr 15 03:33:36 PM PDT 24
Peak memory 366344 kb
Host smart-a2423e22-9932-4a96-84bc-e56781c77b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042123910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.3042123910
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.2137245841
Short name T1211
Test name
Test status
Simulation time 37270189318 ps
CPU time 1866.49 seconds
Started Apr 15 03:33:12 PM PDT 24
Finished Apr 15 04:04:20 PM PDT 24
Peak memory 2665316 kb
Host smart-40bd82a0-632f-492d-9aaf-ff51c5f7afc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137245841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.2137245841
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.3356661596
Short name T280
Test name
Test status
Simulation time 982161266 ps
CPU time 9.74 seconds
Started Apr 15 03:33:11 PM PDT 24
Finished Apr 15 03:33:21 PM PDT 24
Peak memory 212184 kb
Host smart-acc73464-211e-4daa-8f8d-d50026beacfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356661596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.3356661596
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.2150454270
Short name T1025
Test name
Test status
Simulation time 1130529699 ps
CPU time 4.85 seconds
Started Apr 15 03:33:11 PM PDT 24
Finished Apr 15 03:33:17 PM PDT 24
Peak memory 212224 kb
Host smart-93adebba-400c-4771-b6af-d50eaa22e058
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150454270 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2150454270
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.3958602566
Short name T309
Test name
Test status
Simulation time 10093840443 ps
CPU time 78.66 seconds
Started Apr 15 03:33:16 PM PDT 24
Finished Apr 15 03:34:36 PM PDT 24
Peak memory 500592 kb
Host smart-54e67de8-19ba-413c-a7b1-0c0fc9fa7c71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958602566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.3958602566
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.1342047012
Short name T352
Test name
Test status
Simulation time 10064756998 ps
CPU time 76.37 seconds
Started Apr 15 03:33:17 PM PDT 24
Finished Apr 15 03:34:34 PM PDT 24
Peak memory 577660 kb
Host smart-1e6f4f9d-e955-4e97-b18c-fcce61840871
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342047012 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.1342047012
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.3991208775
Short name T359
Test name
Test status
Simulation time 2411137606 ps
CPU time 3.12 seconds
Started Apr 15 03:33:15 PM PDT 24
Finished Apr 15 03:33:18 PM PDT 24
Peak memory 204052 kb
Host smart-943f3ac0-f93a-4193-8a95-7cf4abdc12a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991208775 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.3991208775
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.806291171
Short name T520
Test name
Test status
Simulation time 1138431128 ps
CPU time 5.97 seconds
Started Apr 15 03:33:13 PM PDT 24
Finished Apr 15 03:33:20 PM PDT 24
Peak memory 203972 kb
Host smart-cf752a2d-5bd6-40d8-99f9-f40da6b6a0d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806291171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_intr_smoke.806291171
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.2676822890
Short name T889
Test name
Test status
Simulation time 13611962237 ps
CPU time 17.9 seconds
Started Apr 15 03:33:14 PM PDT 24
Finished Apr 15 03:33:32 PM PDT 24
Peak memory 443560 kb
Host smart-405b64e6-5d49-4e18-acec-8709e658fc27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676822890 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.2676822890
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.3545209719
Short name T786
Test name
Test status
Simulation time 5388892243 ps
CPU time 22.73 seconds
Started Apr 15 03:33:13 PM PDT 24
Finished Apr 15 03:33:37 PM PDT 24
Peak memory 204056 kb
Host smart-a4f2b0a2-756e-4c64-8b22-609d43150546
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545209719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.3545209719
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.1159766069
Short name T430
Test name
Test status
Simulation time 3176301184 ps
CPU time 32.89 seconds
Started Apr 15 03:33:17 PM PDT 24
Finished Apr 15 03:33:50 PM PDT 24
Peak memory 204060 kb
Host smart-a35d168d-bfe3-4d53-8963-e4f1190c06ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159766069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.1159766069
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.3935812119
Short name T29
Test name
Test status
Simulation time 34857606130 ps
CPU time 142.67 seconds
Started Apr 15 03:33:17 PM PDT 24
Finished Apr 15 03:35:41 PM PDT 24
Peak memory 1932920 kb
Host smart-b433f61b-4479-4ec2-83d1-3747cb5cd0e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935812119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.3935812119
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.1325467303
Short name T998
Test name
Test status
Simulation time 25362028109 ps
CPU time 2147.48 seconds
Started Apr 15 03:33:13 PM PDT 24
Finished Apr 15 04:09:01 PM PDT 24
Peak memory 5733212 kb
Host smart-6a2fecf6-81f8-4629-b129-cd5f609567a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325467303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.1325467303
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1149086116
Short name T1178
Test name
Test status
Simulation time 1012824357 ps
CPU time 5.37 seconds
Started Apr 15 03:33:13 PM PDT 24
Finished Apr 15 03:33:19 PM PDT 24
Peak memory 203980 kb
Host smart-f3ad330c-dbd3-4a7b-9c58-7cd546a1f680
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149086116 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1149086116
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.46830812
Short name T853
Test name
Test status
Simulation time 105780025 ps
CPU time 0.62 seconds
Started Apr 15 03:33:29 PM PDT 24
Finished Apr 15 03:33:30 PM PDT 24
Peak memory 203576 kb
Host smart-d8d0f3c1-61b0-4d9e-be0c-637595849841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46830812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.46830812
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.2241884083
Short name T731
Test name
Test status
Simulation time 1377448304 ps
CPU time 1.78 seconds
Started Apr 15 03:33:23 PM PDT 24
Finished Apr 15 03:33:25 PM PDT 24
Peak memory 212304 kb
Host smart-f8974287-9427-4550-8527-a84b5b0bd657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241884083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.2241884083
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.397297128
Short name T910
Test name
Test status
Simulation time 293611719 ps
CPU time 3.55 seconds
Started Apr 15 03:33:16 PM PDT 24
Finished Apr 15 03:33:21 PM PDT 24
Peak memory 229332 kb
Host smart-5d7a1975-3ad0-4338-acd5-4b78036a6419
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397297128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empt
y.397297128
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.3078930763
Short name T1113
Test name
Test status
Simulation time 1416723929 ps
CPU time 42.77 seconds
Started Apr 15 03:33:22 PM PDT 24
Finished Apr 15 03:34:05 PM PDT 24
Peak memory 470568 kb
Host smart-6125931e-4367-4554-b6c8-f3c6d8649b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078930763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.3078930763
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.3965587893
Short name T985
Test name
Test status
Simulation time 2105331694 ps
CPU time 151.57 seconds
Started Apr 15 03:33:18 PM PDT 24
Finished Apr 15 03:35:50 PM PDT 24
Peak memory 703612 kb
Host smart-e301e815-8db9-4589-9df7-29c596cc80cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965587893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.3965587893
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.797490434
Short name T408
Test name
Test status
Simulation time 370018379 ps
CPU time 0.99 seconds
Started Apr 15 03:33:18 PM PDT 24
Finished Apr 15 03:33:19 PM PDT 24
Peak memory 203720 kb
Host smart-2ee8e5e0-cca3-4d71-9ca5-eb3b351fd574
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797490434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fm
t.797490434
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.3733881114
Short name T1026
Test name
Test status
Simulation time 149686649 ps
CPU time 2.39 seconds
Started Apr 15 03:33:18 PM PDT 24
Finished Apr 15 03:33:21 PM PDT 24
Peak memory 203928 kb
Host smart-6b0b17f9-0008-4ef8-a78b-a9a99c99bcb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733881114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.3733881114
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1763986083
Short name T1024
Test name
Test status
Simulation time 11612108784 ps
CPU time 191.09 seconds
Started Apr 15 03:33:18 PM PDT 24
Finished Apr 15 03:36:29 PM PDT 24
Peak memory 895924 kb
Host smart-42b323ed-8705-4d44-ad80-0d97d98ea2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763986083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1763986083
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.347431298
Short name T1001
Test name
Test status
Simulation time 283355095 ps
CPU time 4.69 seconds
Started Apr 15 03:33:31 PM PDT 24
Finished Apr 15 03:33:36 PM PDT 24
Peak memory 203940 kb
Host smart-45544f6f-593b-41a7-aec7-3e8627fc0ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347431298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.347431298
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.651767035
Short name T82
Test name
Test status
Simulation time 5062405699 ps
CPU time 59.59 seconds
Started Apr 15 03:33:23 PM PDT 24
Finished Apr 15 03:34:23 PM PDT 24
Peak memory 296356 kb
Host smart-10ec1053-6fcb-4b58-a8c6-3d28c89d2f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651767035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.651767035
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.1721659653
Short name T987
Test name
Test status
Simulation time 54486699 ps
CPU time 0.64 seconds
Started Apr 15 03:33:18 PM PDT 24
Finished Apr 15 03:33:19 PM PDT 24
Peak memory 203664 kb
Host smart-a5d76924-87e3-4482-980b-a0b61ba5e009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721659653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.1721659653
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.871064904
Short name T220
Test name
Test status
Simulation time 4449141593 ps
CPU time 9.47 seconds
Started Apr 15 03:33:24 PM PDT 24
Finished Apr 15 03:33:35 PM PDT 24
Peak memory 294112 kb
Host smart-afc5eb99-883b-4b37-be0e-39556f8c3001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871064904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.871064904
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.2269169819
Short name T947
Test name
Test status
Simulation time 1938538371 ps
CPU time 20.65 seconds
Started Apr 15 03:33:16 PM PDT 24
Finished Apr 15 03:33:38 PM PDT 24
Peak memory 317480 kb
Host smart-a4c502ae-5620-4699-a362-b2d6d05c08fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269169819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.2269169819
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.1452908886
Short name T262
Test name
Test status
Simulation time 15314691641 ps
CPU time 1275.02 seconds
Started Apr 15 03:33:25 PM PDT 24
Finished Apr 15 03:54:41 PM PDT 24
Peak memory 2618792 kb
Host smart-187cd22f-61f2-4139-845d-f2aa80ac8766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452908886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.1452908886
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.2374270397
Short name T1141
Test name
Test status
Simulation time 540186336 ps
CPU time 24.38 seconds
Started Apr 15 03:33:24 PM PDT 24
Finished Apr 15 03:33:49 PM PDT 24
Peak memory 212224 kb
Host smart-0746dbec-2db2-4c7e-b616-d7ad501cf23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374270397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.2374270397
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.3963191488
Short name T1136
Test name
Test status
Simulation time 1250681505 ps
CPU time 3.21 seconds
Started Apr 15 03:33:25 PM PDT 24
Finished Apr 15 03:33:29 PM PDT 24
Peak memory 204100 kb
Host smart-da70b83b-0c91-4538-8e0f-3e1a5f23ca44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963191488 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.3963191488
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.814834454
Short name T989
Test name
Test status
Simulation time 10050669453 ps
CPU time 37.59 seconds
Started Apr 15 03:33:26 PM PDT 24
Finished Apr 15 03:34:04 PM PDT 24
Peak memory 367464 kb
Host smart-fff393d8-2b12-470f-850b-dde250b603c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814834454 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_acq.814834454
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.593960761
Short name T1241
Test name
Test status
Simulation time 10065853343 ps
CPU time 68.37 seconds
Started Apr 15 03:33:27 PM PDT 24
Finished Apr 15 03:34:36 PM PDT 24
Peak memory 490916 kb
Host smart-f2675ce4-7817-4ab3-9a1b-1aa1b25e94fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593960761 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.i2c_target_fifo_reset_tx.593960761
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.3423888477
Short name T1292
Test name
Test status
Simulation time 465501946 ps
CPU time 2.66 seconds
Started Apr 15 03:33:23 PM PDT 24
Finished Apr 15 03:33:27 PM PDT 24
Peak memory 204020 kb
Host smart-e6f2531e-c5ee-4317-aa39-8e0a4af935bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423888477 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.3423888477
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.3829309828
Short name T1222
Test name
Test status
Simulation time 661564755 ps
CPU time 3.59 seconds
Started Apr 15 03:33:22 PM PDT 24
Finished Apr 15 03:33:26 PM PDT 24
Peak memory 203960 kb
Host smart-2548882d-5770-487d-98f1-ee0760f10c1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829309828 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.3829309828
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.4013499400
Short name T1034
Test name
Test status
Simulation time 14555640439 ps
CPU time 17.16 seconds
Started Apr 15 03:33:26 PM PDT 24
Finished Apr 15 03:33:44 PM PDT 24
Peak memory 478416 kb
Host smart-08b983dd-bdea-4373-abdc-cc175684da4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013499400 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.4013499400
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.1158966097
Short name T476
Test name
Test status
Simulation time 3085185185 ps
CPU time 31.4 seconds
Started Apr 15 03:33:24 PM PDT 24
Finished Apr 15 03:33:56 PM PDT 24
Peak memory 204080 kb
Host smart-4ba7a7f5-e998-4124-9012-229bf07ed3f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158966097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.1158966097
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.4279524716
Short name T304
Test name
Test status
Simulation time 406136038 ps
CPU time 16.75 seconds
Started Apr 15 03:33:24 PM PDT 24
Finished Apr 15 03:33:42 PM PDT 24
Peak memory 204004 kb
Host smart-992dcae7-027f-4bf1-bde9-1adf8d209569
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279524716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.4279524716
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.820877125
Short name T850
Test name
Test status
Simulation time 26840287577 ps
CPU time 19.34 seconds
Started Apr 15 03:33:23 PM PDT 24
Finished Apr 15 03:33:43 PM PDT 24
Peak memory 450036 kb
Host smart-89e98243-eb10-4501-99d0-d52c31b39740
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820877125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_wr.820877125
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.36806533
Short name T1079
Test name
Test status
Simulation time 27879868180 ps
CPU time 681.34 seconds
Started Apr 15 03:33:25 PM PDT 24
Finished Apr 15 03:44:47 PM PDT 24
Peak memory 1699548 kb
Host smart-0384b1a3-626a-4b54-ba5c-5168ebb975d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36806533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_stretch.36806533
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.1915168734
Short name T252
Test name
Test status
Simulation time 19795609188 ps
CPU time 6.82 seconds
Started Apr 15 03:33:24 PM PDT 24
Finished Apr 15 03:33:32 PM PDT 24
Peak memory 209828 kb
Host smart-2b5767d4-a599-4ab8-a772-44565866ba8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915168734 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.1915168734
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.3772252324
Short name T406
Test name
Test status
Simulation time 38123505 ps
CPU time 0.61 seconds
Started Apr 15 03:33:38 PM PDT 24
Finished Apr 15 03:33:40 PM PDT 24
Peak memory 203564 kb
Host smart-9172a8bd-c0f3-4f9e-a259-c7d3bd928cd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772252324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.3772252324
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3879899970
Short name T1137
Test name
Test status
Simulation time 97462600 ps
CPU time 1.66 seconds
Started Apr 15 03:33:31 PM PDT 24
Finished Apr 15 03:33:34 PM PDT 24
Peak memory 212292 kb
Host smart-dd1214d8-cbe0-44cc-8f15-58fdaa853e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879899970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3879899970
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2605386764
Short name T637
Test name
Test status
Simulation time 551161757 ps
CPU time 13.71 seconds
Started Apr 15 03:33:28 PM PDT 24
Finished Apr 15 03:33:42 PM PDT 24
Peak memory 256588 kb
Host smart-423f92e2-1de5-4d2f-9516-cf0caafe77f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605386764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2605386764
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.518728884
Short name T1053
Test name
Test status
Simulation time 28166053835 ps
CPU time 60.03 seconds
Started Apr 15 03:33:29 PM PDT 24
Finished Apr 15 03:34:30 PM PDT 24
Peak memory 697364 kb
Host smart-ffe61ce6-f3aa-4b42-b5da-2b20e73b0f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518728884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.518728884
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.422846968
Short name T587
Test name
Test status
Simulation time 5901371374 ps
CPU time 45.76 seconds
Started Apr 15 03:33:28 PM PDT 24
Finished Apr 15 03:34:14 PM PDT 24
Peak memory 529784 kb
Host smart-f1a9fbba-ad62-44bf-b2eb-e8f71fc4590b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422846968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.422846968
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.1533699143
Short name T231
Test name
Test status
Simulation time 142164443 ps
CPU time 1.09 seconds
Started Apr 15 03:33:30 PM PDT 24
Finished Apr 15 03:33:31 PM PDT 24
Peak memory 203872 kb
Host smart-8cf50185-eb37-4d42-b8ee-c4322ad6da99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533699143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.1533699143
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.4142087907
Short name T700
Test name
Test status
Simulation time 1191531251 ps
CPU time 3.15 seconds
Started Apr 15 03:33:31 PM PDT 24
Finished Apr 15 03:33:35 PM PDT 24
Peak memory 203900 kb
Host smart-620e4b6d-b017-4aaa-9725-fe62bf0875ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142087907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.4142087907
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.3930449954
Short name T979
Test name
Test status
Simulation time 3193935181 ps
CPU time 212.71 seconds
Started Apr 15 03:33:38 PM PDT 24
Finished Apr 15 03:37:11 PM PDT 24
Peak memory 958828 kb
Host smart-bb068cd5-5ec6-4407-b5ed-5250bde04ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930449954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.3930449954
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.750876470
Short name T1220
Test name
Test status
Simulation time 1392843280 ps
CPU time 14.08 seconds
Started Apr 15 03:33:35 PM PDT 24
Finished Apr 15 03:33:50 PM PDT 24
Peak memory 203976 kb
Host smart-d8e7f1dd-9b5a-43d5-b9de-9126c06fa07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750876470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.750876470
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.2083460442
Short name T67
Test name
Test status
Simulation time 2482331864 ps
CPU time 56.14 seconds
Started Apr 15 03:33:32 PM PDT 24
Finished Apr 15 03:34:29 PM PDT 24
Peak memory 285344 kb
Host smart-f740243a-45a0-4588-958c-7bc6daf7ddd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083460442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.2083460442
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.2941335048
Short name T1087
Test name
Test status
Simulation time 35508739 ps
CPU time 0.64 seconds
Started Apr 15 03:33:28 PM PDT 24
Finished Apr 15 03:33:29 PM PDT 24
Peak memory 203656 kb
Host smart-f6cbec6e-66c8-474c-9d16-fb62b22c84a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941335048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.2941335048
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.266063835
Short name T1008
Test name
Test status
Simulation time 2485713961 ps
CPU time 155.42 seconds
Started Apr 15 03:33:27 PM PDT 24
Finished Apr 15 03:36:03 PM PDT 24
Peak memory 747708 kb
Host smart-7e2ae0d6-7578-4b50-be4e-82af53eda020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266063835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.266063835
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.3939312279
Short name T413
Test name
Test status
Simulation time 3788469181 ps
CPU time 45.61 seconds
Started Apr 15 03:33:30 PM PDT 24
Finished Apr 15 03:34:16 PM PDT 24
Peak memory 298436 kb
Host smart-93495455-4d40-497a-a8ca-6c4fea2a673f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939312279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.3939312279
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.468183341
Short name T241
Test name
Test status
Simulation time 44868157251 ps
CPU time 1438.99 seconds
Started Apr 15 03:33:29 PM PDT 24
Finished Apr 15 03:57:29 PM PDT 24
Peak memory 2444096 kb
Host smart-c8db44e9-508c-4658-b80e-49258df4aa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468183341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.468183341
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.2165973674
Short name T588
Test name
Test status
Simulation time 723112946 ps
CPU time 13.69 seconds
Started Apr 15 03:33:33 PM PDT 24
Finished Apr 15 03:33:47 PM PDT 24
Peak memory 220404 kb
Host smart-13fbe233-9d1b-4bfb-a29b-c2891202b0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165973674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.2165973674
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.1582872760
Short name T1326
Test name
Test status
Simulation time 4597223372 ps
CPU time 3.59 seconds
Started Apr 15 03:33:32 PM PDT 24
Finished Apr 15 03:33:36 PM PDT 24
Peak memory 204100 kb
Host smart-6ddcc231-13a8-4ee1-b70c-bb772f1fc6f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582872760 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.1582872760
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.1035442401
Short name T689
Test name
Test status
Simulation time 10117851553 ps
CPU time 69.26 seconds
Started Apr 15 03:33:31 PM PDT 24
Finished Apr 15 03:34:41 PM PDT 24
Peak memory 566160 kb
Host smart-02c0dd60-f15c-4555-8a13-a5afad5d97a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035442401 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.1035442401
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.4138394135
Short name T856
Test name
Test status
Simulation time 1280779482 ps
CPU time 2 seconds
Started Apr 15 03:33:33 PM PDT 24
Finished Apr 15 03:33:35 PM PDT 24
Peak memory 203984 kb
Host smart-0b442a20-b0e0-468e-aae8-afa34b0dbc9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138394135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.4138394135
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.182691429
Short name T899
Test name
Test status
Simulation time 1671597662 ps
CPU time 3.9 seconds
Started Apr 15 03:33:32 PM PDT 24
Finished Apr 15 03:33:36 PM PDT 24
Peak memory 203976 kb
Host smart-0f3d6651-adef-4847-988d-308028f626e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182691429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_intr_smoke.182691429
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.4195155433
Short name T1089
Test name
Test status
Simulation time 9672910189 ps
CPU time 6.38 seconds
Started Apr 15 03:33:32 PM PDT 24
Finished Apr 15 03:33:39 PM PDT 24
Peak memory 204052 kb
Host smart-eeb68ef1-5b7e-4de2-aacd-b1d66cc2ba3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195155433 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.4195155433
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.1106342713
Short name T1050
Test name
Test status
Simulation time 1999270327 ps
CPU time 14.71 seconds
Started Apr 15 03:33:33 PM PDT 24
Finished Apr 15 03:33:48 PM PDT 24
Peak memory 204000 kb
Host smart-f57de08e-64a5-4b84-978a-fe78e829a153
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106342713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.1106342713
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.610652228
Short name T245
Test name
Test status
Simulation time 2823446355 ps
CPU time 34.26 seconds
Started Apr 15 03:33:30 PM PDT 24
Finished Apr 15 03:34:05 PM PDT 24
Peak memory 204084 kb
Host smart-b41cb144-6b5a-43bf-849b-7e1ece6b6272
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610652228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_rd.610652228
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.2602866679
Short name T618
Test name
Test status
Simulation time 16137931011 ps
CPU time 5.38 seconds
Started Apr 15 03:33:32 PM PDT 24
Finished Apr 15 03:33:38 PM PDT 24
Peak memory 204064 kb
Host smart-001a2550-18e4-4e31-b59f-eb6f761009d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602866679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.2602866679
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.137302507
Short name T249
Test name
Test status
Simulation time 30376967104 ps
CPU time 769.33 seconds
Started Apr 15 03:33:27 PM PDT 24
Finished Apr 15 03:46:17 PM PDT 24
Peak memory 3629016 kb
Host smart-e56648b4-33cf-4dc0-85ec-22e158bbdb2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137302507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_t
arget_stretch.137302507
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.2468054888
Short name T1234
Test name
Test status
Simulation time 2439655126 ps
CPU time 5.96 seconds
Started Apr 15 03:33:32 PM PDT 24
Finished Apr 15 03:33:39 PM PDT 24
Peak memory 204084 kb
Host smart-49acef48-cb03-4a34-9186-a3b236d531db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468054888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.2468054888
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.953023260
Short name T1011
Test name
Test status
Simulation time 15849239 ps
CPU time 0.59 seconds
Started Apr 15 03:33:44 PM PDT 24
Finished Apr 15 03:33:45 PM PDT 24
Peak memory 203528 kb
Host smart-70b75d07-7753-4cc0-aef8-39f86e487aee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953023260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.953023260
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.3193547486
Short name T524
Test name
Test status
Simulation time 50461050 ps
CPU time 1.44 seconds
Started Apr 15 03:33:40 PM PDT 24
Finished Apr 15 03:33:42 PM PDT 24
Peak memory 212220 kb
Host smart-b1018efb-c711-4118-be2e-835d6763197d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193547486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.3193547486
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.2183317627
Short name T357
Test name
Test status
Simulation time 3856430948 ps
CPU time 7.38 seconds
Started Apr 15 03:33:36 PM PDT 24
Finished Apr 15 03:33:45 PM PDT 24
Peak memory 289584 kb
Host smart-18d92062-b15e-46e9-9ae2-10d5d8345da5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183317627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.2183317627
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.1990061091
Short name T497
Test name
Test status
Simulation time 1334439033 ps
CPU time 30.16 seconds
Started Apr 15 03:33:35 PM PDT 24
Finished Apr 15 03:34:06 PM PDT 24
Peak memory 232444 kb
Host smart-822eaf17-fe15-43b7-a1a2-91c84f3adacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990061091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.1990061091
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.4133365865
Short name T672
Test name
Test status
Simulation time 1586589105 ps
CPU time 57.44 seconds
Started Apr 15 03:33:36 PM PDT 24
Finished Apr 15 03:34:34 PM PDT 24
Peak memory 587728 kb
Host smart-dc48f8bc-ad27-41cf-b080-dc0cfb37fcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133365865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.4133365865
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.2043940872
Short name T226
Test name
Test status
Simulation time 2205404760 ps
CPU time 1.03 seconds
Started Apr 15 03:33:36 PM PDT 24
Finished Apr 15 03:33:38 PM PDT 24
Peak memory 204000 kb
Host smart-6342bb69-7c05-4564-b66b-5b23b8661767
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043940872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.2043940872
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.1517515220
Short name T1223
Test name
Test status
Simulation time 117248836 ps
CPU time 2.51 seconds
Started Apr 15 03:33:36 PM PDT 24
Finished Apr 15 03:33:40 PM PDT 24
Peak memory 203936 kb
Host smart-0234075f-ebef-41b9-a7f5-9d779890d7e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517515220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.1517515220
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.658146476
Short name T113
Test name
Test status
Simulation time 9961904395 ps
CPU time 266.48 seconds
Started Apr 15 03:33:44 PM PDT 24
Finished Apr 15 03:38:11 PM PDT 24
Peak memory 1043180 kb
Host smart-973056ba-831b-45ef-802e-368ffc55141b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658146476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.658146476
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.2972603617
Short name T1027
Test name
Test status
Simulation time 337134101 ps
CPU time 4.2 seconds
Started Apr 15 03:33:51 PM PDT 24
Finished Apr 15 03:33:56 PM PDT 24
Peak memory 203940 kb
Host smart-b44de21b-30e2-436e-8854-f63f3fe2e748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972603617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.2972603617
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.3643709389
Short name T360
Test name
Test status
Simulation time 6027397046 ps
CPU time 25.73 seconds
Started Apr 15 03:33:45 PM PDT 24
Finished Apr 15 03:34:12 PM PDT 24
Peak memory 329972 kb
Host smart-70e3df08-a724-4cff-9b8c-eb522a82b289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643709389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.3643709389
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.3422745381
Short name T1047
Test name
Test status
Simulation time 18865788 ps
CPU time 0.64 seconds
Started Apr 15 03:33:34 PM PDT 24
Finished Apr 15 03:33:35 PM PDT 24
Peak memory 203660 kb
Host smart-877ea451-e6cf-4b20-8c3e-eb83d9f9df54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422745381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.3422745381
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.3451816522
Short name T305
Test name
Test status
Simulation time 398981648 ps
CPU time 6.32 seconds
Started Apr 15 03:33:35 PM PDT 24
Finished Apr 15 03:33:43 PM PDT 24
Peak memory 228480 kb
Host smart-fae8a788-6d02-41db-b59e-420af724f4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451816522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.3451816522
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.693053025
Short name T823
Test name
Test status
Simulation time 1518116772 ps
CPU time 28.78 seconds
Started Apr 15 03:33:35 PM PDT 24
Finished Apr 15 03:34:05 PM PDT 24
Peak memory 306520 kb
Host smart-b65d923d-7174-43e3-ae87-4a44624f91d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693053025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.693053025
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.3934891547
Short name T1280
Test name
Test status
Simulation time 15732893527 ps
CPU time 79.58 seconds
Started Apr 15 03:33:39 PM PDT 24
Finished Apr 15 03:35:00 PM PDT 24
Peak memory 421060 kb
Host smart-88da5cce-e150-4383-a060-4468187f072e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934891547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.3934891547
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.3305240270
Short name T334
Test name
Test status
Simulation time 409457189 ps
CPU time 6.82 seconds
Started Apr 15 03:33:40 PM PDT 24
Finished Apr 15 03:33:47 PM PDT 24
Peak memory 212268 kb
Host smart-7ef07ff5-30e7-4f46-aea6-c8d78a22c179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305240270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.3305240270
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.1286412446
Short name T624
Test name
Test status
Simulation time 919242276 ps
CPU time 4.46 seconds
Started Apr 15 03:33:43 PM PDT 24
Finished Apr 15 03:33:48 PM PDT 24
Peak memory 204044 kb
Host smart-42b53bcf-bad1-4027-a51f-a21b8d8898b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286412446 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1286412446
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2684736884
Short name T1238
Test name
Test status
Simulation time 10092304600 ps
CPU time 18.1 seconds
Started Apr 15 03:33:40 PM PDT 24
Finished Apr 15 03:33:59 PM PDT 24
Peak memory 288888 kb
Host smart-9e9586df-aec8-4dfd-b659-e71a52527b6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684736884 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.2684736884
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.192654432
Short name T840
Test name
Test status
Simulation time 10296029328 ps
CPU time 31.4 seconds
Started Apr 15 03:33:40 PM PDT 24
Finished Apr 15 03:34:12 PM PDT 24
Peak memory 411032 kb
Host smart-06af882d-e88c-45dc-9934-de36518a1819
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192654432 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_fifo_reset_tx.192654432
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.1526802038
Short name T1269
Test name
Test status
Simulation time 1266916934 ps
CPU time 2.32 seconds
Started Apr 15 03:33:44 PM PDT 24
Finished Apr 15 03:33:47 PM PDT 24
Peak memory 203952 kb
Host smart-efd7fba0-ac2e-490b-9a86-02f2c1a9ebd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526802038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.1526802038
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.2289762540
Short name T772
Test name
Test status
Simulation time 1662839294 ps
CPU time 6.99 seconds
Started Apr 15 03:34:08 PM PDT 24
Finished Apr 15 03:34:16 PM PDT 24
Peak memory 204044 kb
Host smart-32aa9ce2-ff76-46c4-9112-7e96161bd3b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289762540 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.2289762540
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.3672908289
Short name T758
Test name
Test status
Simulation time 20220383784 ps
CPU time 137.49 seconds
Started Apr 15 03:33:41 PM PDT 24
Finished Apr 15 03:35:59 PM PDT 24
Peak memory 1700152 kb
Host smart-74fdb689-99e1-4cf0-b2ad-8379f751e7ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672908289 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.3672908289
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.4079449394
Short name T109
Test name
Test status
Simulation time 902201209 ps
CPU time 12.96 seconds
Started Apr 15 03:33:42 PM PDT 24
Finished Apr 15 03:33:55 PM PDT 24
Peak memory 203996 kb
Host smart-ba377d7f-6244-40ea-9111-746aa203816d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079449394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.4079449394
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.3874694740
Short name T368
Test name
Test status
Simulation time 1773238020 ps
CPU time 72.88 seconds
Started Apr 15 03:33:40 PM PDT 24
Finished Apr 15 03:34:53 PM PDT 24
Peak memory 207480 kb
Host smart-e3be8336-3430-4390-a272-402cf41beeb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874694740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.3874694740
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.3904324349
Short name T836
Test name
Test status
Simulation time 8991645145 ps
CPU time 5.4 seconds
Started Apr 15 03:33:40 PM PDT 24
Finished Apr 15 03:33:46 PM PDT 24
Peak memory 203916 kb
Host smart-566729a9-d87e-4dea-a5ac-0d1c7a0c6fa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904324349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.3904324349
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.1724109165
Short name T790
Test name
Test status
Simulation time 13984970593 ps
CPU time 72.17 seconds
Started Apr 15 03:33:39 PM PDT 24
Finished Apr 15 03:34:52 PM PDT 24
Peak memory 445288 kb
Host smart-1dd4623a-6b16-44a6-9727-79c0c77293cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724109165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.1724109165
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.963161959
Short name T445
Test name
Test status
Simulation time 1457969024 ps
CPU time 7.22 seconds
Started Apr 15 03:33:41 PM PDT 24
Finished Apr 15 03:33:48 PM PDT 24
Peak memory 220184 kb
Host smart-3c069a9b-3268-47a3-9695-21da2b20028e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963161959 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_timeout.963161959
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.379799964
Short name T550
Test name
Test status
Simulation time 16535842 ps
CPU time 0.61 seconds
Started Apr 15 03:28:53 PM PDT 24
Finished Apr 15 03:28:55 PM PDT 24
Peak memory 203608 kb
Host smart-525f9196-95fe-4758-bfdc-39ace309f2c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379799964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.379799964
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.196376694
Short name T762
Test name
Test status
Simulation time 266998195 ps
CPU time 1.42 seconds
Started Apr 15 03:28:53 PM PDT 24
Finished Apr 15 03:28:56 PM PDT 24
Peak memory 212276 kb
Host smart-7b41f371-887e-49f6-ab41-d4b35b5a227b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196376694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.196376694
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.272241748
Short name T532
Test name
Test status
Simulation time 4404429811 ps
CPU time 4.86 seconds
Started Apr 15 03:28:53 PM PDT 24
Finished Apr 15 03:28:59 PM PDT 24
Peak memory 247440 kb
Host smart-0c5eb85c-5295-4997-b45c-edf0d89d90a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272241748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty
.272241748
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.3763210635
Short name T881
Test name
Test status
Simulation time 1722122350 ps
CPU time 54.2 seconds
Started Apr 15 03:28:55 PM PDT 24
Finished Apr 15 03:29:50 PM PDT 24
Peak memory 510616 kb
Host smart-b363d20c-5a43-4d06-918a-508e1b93c93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763210635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3763210635
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.4117266032
Short name T599
Test name
Test status
Simulation time 2140424125 ps
CPU time 62.15 seconds
Started Apr 15 03:28:49 PM PDT 24
Finished Apr 15 03:29:52 PM PDT 24
Peak memory 718404 kb
Host smart-2874a0ee-34dd-40e7-8feb-56f0cbc0b065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117266032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.4117266032
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.992043101
Short name T909
Test name
Test status
Simulation time 1131247010 ps
CPU time 1.11 seconds
Started Apr 15 03:28:54 PM PDT 24
Finished Apr 15 03:28:57 PM PDT 24
Peak memory 203960 kb
Host smart-5bb2d11a-0b9e-4ade-80a3-4f71a0cecc00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992043101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt
.992043101
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.1691516258
Short name T996
Test name
Test status
Simulation time 128857148 ps
CPU time 3.39 seconds
Started Apr 15 03:28:51 PM PDT 24
Finished Apr 15 03:28:55 PM PDT 24
Peak memory 224612 kb
Host smart-e535bac7-6688-41fd-ad84-46816c5addc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691516258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
1691516258
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.3747827177
Short name T942
Test name
Test status
Simulation time 3248872038 ps
CPU time 92.37 seconds
Started Apr 15 03:28:55 PM PDT 24
Finished Apr 15 03:30:28 PM PDT 24
Peak memory 987588 kb
Host smart-384b931e-47e7-416e-85a5-c9a5645db373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747827177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.3747827177
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.261767500
Short name T236
Test name
Test status
Simulation time 2899452425 ps
CPU time 8.29 seconds
Started Apr 15 03:28:53 PM PDT 24
Finished Apr 15 03:29:02 PM PDT 24
Peak memory 203996 kb
Host smart-adc0b5be-c395-44f8-8aee-ffce7ea67fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261767500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.261767500
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.1737146968
Short name T716
Test name
Test status
Simulation time 7398286211 ps
CPU time 31.51 seconds
Started Apr 15 03:28:55 PM PDT 24
Finished Apr 15 03:29:28 PM PDT 24
Peak memory 330872 kb
Host smart-4eef8465-143e-4c6a-8d91-a8776df2355c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737146968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.1737146968
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.2203820591
Short name T1175
Test name
Test status
Simulation time 16148660 ps
CPU time 0.64 seconds
Started Apr 15 03:28:54 PM PDT 24
Finished Apr 15 03:28:56 PM PDT 24
Peak memory 203680 kb
Host smart-7b6ed40c-b5c1-4297-964f-883d8bbd5404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203820591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.2203820591
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.166445369
Short name T97
Test name
Test status
Simulation time 6824505525 ps
CPU time 46.92 seconds
Started Apr 15 03:28:52 PM PDT 24
Finished Apr 15 03:29:40 PM PDT 24
Peak memory 204016 kb
Host smart-fb478873-d26c-4677-a7d7-26ef80e39636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166445369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.166445369
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1244834957
Short name T761
Test name
Test status
Simulation time 1597526212 ps
CPU time 78.16 seconds
Started Apr 15 03:28:53 PM PDT 24
Finished Apr 15 03:30:12 PM PDT 24
Peak memory 343596 kb
Host smart-9f25b917-57d7-4e16-b033-a14e7c1bc9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244834957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1244834957
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.978718030
Short name T1155
Test name
Test status
Simulation time 42454519570 ps
CPU time 1431.17 seconds
Started Apr 15 03:28:54 PM PDT 24
Finished Apr 15 03:52:46 PM PDT 24
Peak memory 2252404 kb
Host smart-3ad053b3-e203-47b2-bb5c-be2c0c9ee32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978718030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.978718030
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.3303406022
Short name T344
Test name
Test status
Simulation time 2324101271 ps
CPU time 8.18 seconds
Started Apr 15 03:28:50 PM PDT 24
Finished Apr 15 03:28:59 PM PDT 24
Peak memory 219984 kb
Host smart-6cc15efb-08b1-4543-b1f9-63ddf08e4bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303406022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.3303406022
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.1110604598
Short name T120
Test name
Test status
Simulation time 241504225 ps
CPU time 0.93 seconds
Started Apr 15 03:28:55 PM PDT 24
Finished Apr 15 03:28:57 PM PDT 24
Peak memory 222124 kb
Host smart-6d5c86c2-4d16-4736-b619-242724a51505
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110604598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.1110604598
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.691853688
Short name T423
Test name
Test status
Simulation time 2196523248 ps
CPU time 2.97 seconds
Started Apr 15 03:28:57 PM PDT 24
Finished Apr 15 03:29:01 PM PDT 24
Peak memory 204032 kb
Host smart-09a47776-db8f-43b5-8a98-9a9ddb0850f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691853688 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.691853688
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3446071803
Short name T297
Test name
Test status
Simulation time 10811331715 ps
CPU time 4.45 seconds
Started Apr 15 03:28:52 PM PDT 24
Finished Apr 15 03:28:57 PM PDT 24
Peak memory 218136 kb
Host smart-2ad55740-77b8-4d8c-bba6-f0840019f206
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446071803 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.3446071803
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.2591514905
Short name T57
Test name
Test status
Simulation time 10047560256 ps
CPU time 46.73 seconds
Started Apr 15 03:28:52 PM PDT 24
Finished Apr 15 03:29:40 PM PDT 24
Peak memory 460652 kb
Host smart-25ea6614-e854-41a6-ac8c-9ec5eae00156
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591514905 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.2591514905
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.805568191
Short name T1307
Test name
Test status
Simulation time 1397397602 ps
CPU time 2.58 seconds
Started Apr 15 03:28:53 PM PDT 24
Finished Apr 15 03:28:56 PM PDT 24
Peak memory 204024 kb
Host smart-95889cd3-0dfe-407c-bd54-2a255233e5ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805568191 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.i2c_target_hrst.805568191
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.4007532041
Short name T375
Test name
Test status
Simulation time 1692598491 ps
CPU time 4.6 seconds
Started Apr 15 03:28:50 PM PDT 24
Finished Apr 15 03:28:55 PM PDT 24
Peak memory 203972 kb
Host smart-7495e88e-24e2-4642-b592-6b1150fcc045
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007532041 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.4007532041
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.1613722260
Short name T580
Test name
Test status
Simulation time 9109872781 ps
CPU time 32.17 seconds
Started Apr 15 03:28:49 PM PDT 24
Finished Apr 15 03:29:22 PM PDT 24
Peak memory 696848 kb
Host smart-820526c0-f5c3-432c-a1bb-24d9d4eabedd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613722260 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.1613722260
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.3155475306
Short name T42
Test name
Test status
Simulation time 1619111131 ps
CPU time 10.62 seconds
Started Apr 15 03:28:49 PM PDT 24
Finished Apr 15 03:29:01 PM PDT 24
Peak memory 204012 kb
Host smart-120bef01-564b-4c67-ada9-824f4af16281
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155475306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.3155475306
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.3153179961
Short name T854
Test name
Test status
Simulation time 6619886584 ps
CPU time 70.04 seconds
Started Apr 15 03:28:55 PM PDT 24
Finished Apr 15 03:30:06 PM PDT 24
Peak memory 208072 kb
Host smart-c2cc1da5-4735-41b1-a1f8-4c1df177a76f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153179961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.3153179961
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2895733390
Short name T484
Test name
Test status
Simulation time 13031355169 ps
CPU time 3.42 seconds
Started Apr 15 03:28:51 PM PDT 24
Finished Apr 15 03:28:55 PM PDT 24
Peak memory 204080 kb
Host smart-122d55af-9d6a-4a9c-81b6-9e943ae7462a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895733390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2895733390
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.3070757957
Short name T289
Test name
Test status
Simulation time 22700954352 ps
CPU time 143.18 seconds
Started Apr 15 03:28:49 PM PDT 24
Finished Apr 15 03:31:13 PM PDT 24
Peak memory 1317804 kb
Host smart-fdfacac6-672b-4457-a0e3-669613adc3f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070757957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.3070757957
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.3458993914
Short name T393
Test name
Test status
Simulation time 1079775220 ps
CPU time 5.75 seconds
Started Apr 15 03:28:48 PM PDT 24
Finished Apr 15 03:28:55 PM PDT 24
Peak memory 204040 kb
Host smart-365bc284-8af3-450e-a355-12fec1efb5fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458993914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.3458993914
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1878233107
Short name T512
Test name
Test status
Simulation time 15568234 ps
CPU time 0.63 seconds
Started Apr 15 03:33:52 PM PDT 24
Finished Apr 15 03:33:53 PM PDT 24
Peak memory 203584 kb
Host smart-46cb99d6-4b34-4833-9144-c6de67a69f86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878233107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1878233107
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.3831051717
Short name T1
Test name
Test status
Simulation time 63802881 ps
CPU time 1.55 seconds
Started Apr 15 03:33:44 PM PDT 24
Finished Apr 15 03:33:46 PM PDT 24
Peak memory 212256 kb
Host smart-ff7c6b7c-c55d-4f83-852f-7f3ba87ea4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831051717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3831051717
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.3677038750
Short name T467
Test name
Test status
Simulation time 257507739 ps
CPU time 5.41 seconds
Started Apr 15 03:33:43 PM PDT 24
Finished Apr 15 03:33:49 PM PDT 24
Peak memory 249168 kb
Host smart-dbe46414-9a77-4439-9bc7-c41529a9378f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677038750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.3677038750
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.2349576370
Short name T43
Test name
Test status
Simulation time 2129236821 ps
CPU time 64.58 seconds
Started Apr 15 03:33:51 PM PDT 24
Finished Apr 15 03:34:56 PM PDT 24
Peak memory 670972 kb
Host smart-88ab75c5-5710-4f40-892a-bb89cda55a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349576370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.2349576370
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.3488445696
Short name T284
Test name
Test status
Simulation time 8175554714 ps
CPU time 63.63 seconds
Started Apr 15 03:33:44 PM PDT 24
Finished Apr 15 03:34:48 PM PDT 24
Peak memory 448716 kb
Host smart-39a5593e-487f-4626-9a54-001f5490bbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488445696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.3488445696
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3704986958
Short name T227
Test name
Test status
Simulation time 74968326 ps
CPU time 0.88 seconds
Started Apr 15 03:33:43 PM PDT 24
Finished Apr 15 03:33:45 PM PDT 24
Peak memory 203864 kb
Host smart-bd5127de-c9ff-445c-8147-56f40f7ab058
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704986958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.3704986958
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1402933173
Short name T782
Test name
Test status
Simulation time 490443176 ps
CPU time 3.75 seconds
Started Apr 15 03:33:45 PM PDT 24
Finished Apr 15 03:33:50 PM PDT 24
Peak memory 224788 kb
Host smart-a8e6ec43-d132-443f-8c9a-82ce8b8bdf3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402933173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1402933173
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.476085179
Short name T570
Test name
Test status
Simulation time 10581239239 ps
CPU time 89.62 seconds
Started Apr 15 03:33:51 PM PDT 24
Finished Apr 15 03:35:21 PM PDT 24
Peak memory 942332 kb
Host smart-0cf5ac04-dae3-47c0-b84b-9be4612c279c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476085179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.476085179
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.647759247
Short name T537
Test name
Test status
Simulation time 219368094 ps
CPU time 3.61 seconds
Started Apr 15 03:33:55 PM PDT 24
Finished Apr 15 03:33:59 PM PDT 24
Peak memory 204008 kb
Host smart-ad6977a2-c013-4e78-8e17-f04dfaf878e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647759247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.647759247
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.3226179546
Short name T699
Test name
Test status
Simulation time 1064400838 ps
CPU time 50.56 seconds
Started Apr 15 03:33:50 PM PDT 24
Finished Apr 15 03:34:41 PM PDT 24
Peak memory 307780 kb
Host smart-3f56f59e-824d-480e-8a53-242ab42df8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226179546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.3226179546
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.3044659483
Short name T208
Test name
Test status
Simulation time 31013166 ps
CPU time 0.72 seconds
Started Apr 15 03:33:47 PM PDT 24
Finished Apr 15 03:33:48 PM PDT 24
Peak memory 203676 kb
Host smart-3f804495-0979-4d6e-ac1b-d2531d350791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044659483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3044659483
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.2918008621
Short name T452
Test name
Test status
Simulation time 27233737036 ps
CPU time 1875.02 seconds
Started Apr 15 03:33:45 PM PDT 24
Finished Apr 15 04:05:01 PM PDT 24
Peak memory 2919664 kb
Host smart-289ba977-7869-47d2-9981-551d5e92421d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918008621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.2918008621
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.739639603
Short name T464
Test name
Test status
Simulation time 4951018427 ps
CPU time 26.7 seconds
Started Apr 15 03:33:47 PM PDT 24
Finished Apr 15 03:34:15 PM PDT 24
Peak memory 331144 kb
Host smart-0f3bfc16-f843-4cf0-a323-3b178390c727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739639603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.739639603
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.2694941687
Short name T195
Test name
Test status
Simulation time 23203403027 ps
CPU time 147.45 seconds
Started Apr 15 03:33:48 PM PDT 24
Finished Apr 15 03:36:16 PM PDT 24
Peak memory 918712 kb
Host smart-89cb73c0-04b9-4079-a200-346776663bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694941687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.2694941687
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.3526176911
Short name T930
Test name
Test status
Simulation time 2334052848 ps
CPU time 25.64 seconds
Started Apr 15 03:33:51 PM PDT 24
Finished Apr 15 03:34:17 PM PDT 24
Peak memory 212272 kb
Host smart-11561002-3b79-4a58-84cd-e019632ad2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526176911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.3526176911
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.2037813057
Short name T749
Test name
Test status
Simulation time 1445498355 ps
CPU time 2.7 seconds
Started Apr 15 03:33:51 PM PDT 24
Finished Apr 15 03:33:55 PM PDT 24
Peak memory 204024 kb
Host smart-8e5e37cf-d773-4f34-96c2-75134ee5567c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037813057 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.2037813057
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2801244161
Short name T58
Test name
Test status
Simulation time 10412655954 ps
CPU time 12.88 seconds
Started Apr 15 03:33:47 PM PDT 24
Finished Apr 15 03:34:01 PM PDT 24
Peak memory 277308 kb
Host smart-f9b9c1d6-98f0-4547-88c4-e4b27634ad7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801244161 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2801244161
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.2947598406
Short name T1148
Test name
Test status
Simulation time 10354611897 ps
CPU time 14.28 seconds
Started Apr 15 03:33:46 PM PDT 24
Finished Apr 15 03:34:01 PM PDT 24
Peak memory 282080 kb
Host smart-4ba3ea2c-7371-47d8-baee-5945bd9a968e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947598406 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.2947598406
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.2778080069
Short name T754
Test name
Test status
Simulation time 6171255837 ps
CPU time 2.43 seconds
Started Apr 15 03:33:50 PM PDT 24
Finished Apr 15 03:33:53 PM PDT 24
Peak memory 204032 kb
Host smart-922be12f-6fdf-46bb-a52d-1fbb4c451852
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778080069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.2778080069
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.3007423932
Short name T567
Test name
Test status
Simulation time 4244180228 ps
CPU time 4.89 seconds
Started Apr 15 03:33:48 PM PDT 24
Finished Apr 15 03:33:53 PM PDT 24
Peak memory 217388 kb
Host smart-1e1ac7c5-364b-4135-8aa9-b3a8d7b00fb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007423932 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.3007423932
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.2165983045
Short name T394
Test name
Test status
Simulation time 4003606607 ps
CPU time 8.69 seconds
Started Apr 15 03:33:48 PM PDT 24
Finished Apr 15 03:33:57 PM PDT 24
Peak memory 204044 kb
Host smart-295b03d6-5275-4ab9-b010-1b7f52401f90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165983045 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.2165983045
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.250481561
Short name T768
Test name
Test status
Simulation time 5605731462 ps
CPU time 22.15 seconds
Started Apr 15 03:33:48 PM PDT 24
Finished Apr 15 03:34:11 PM PDT 24
Peak memory 204052 kb
Host smart-ca58fe84-d593-4a24-b5a4-ba918cebe042
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250481561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.250481561
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.358855893
Short name T128
Test name
Test status
Simulation time 2049074806 ps
CPU time 43.08 seconds
Started Apr 15 03:33:49 PM PDT 24
Finished Apr 15 03:34:32 PM PDT 24
Peak memory 203988 kb
Host smart-df4f3c12-d6d6-470e-9b1b-9cf432ed2602
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358855893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_rd.358855893
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.478038784
Short name T1110
Test name
Test status
Simulation time 47878387191 ps
CPU time 153.72 seconds
Started Apr 15 03:33:51 PM PDT 24
Finished Apr 15 03:36:25 PM PDT 24
Peak memory 1831068 kb
Host smart-e7ee1d8c-35b9-4551-9e84-f6f75d30ae8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478038784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_wr.478038784
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.3213108775
Short name T1103
Test name
Test status
Simulation time 5338292875 ps
CPU time 18.14 seconds
Started Apr 15 03:33:47 PM PDT 24
Finished Apr 15 03:34:06 PM PDT 24
Peak memory 245680 kb
Host smart-c07fa4c2-d469-43ca-9f75-6734921f35a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213108775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.3213108775
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.782246270
Short name T665
Test name
Test status
Simulation time 2544105584 ps
CPU time 6.59 seconds
Started Apr 15 03:33:50 PM PDT 24
Finished Apr 15 03:33:57 PM PDT 24
Peak memory 210968 kb
Host smart-65dc6341-9b94-48ec-bc27-9be7f20c4b33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782246270 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_timeout.782246270
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.1351355719
Short name T733
Test name
Test status
Simulation time 18090515 ps
CPU time 0.62 seconds
Started Apr 15 03:34:08 PM PDT 24
Finished Apr 15 03:34:09 PM PDT 24
Peak memory 203560 kb
Host smart-779f8ce8-128b-46f1-920b-ea08bf78f12e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351355719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.1351355719
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.3293857306
Short name T769
Test name
Test status
Simulation time 682736233 ps
CPU time 1.63 seconds
Started Apr 15 03:33:53 PM PDT 24
Finished Apr 15 03:33:56 PM PDT 24
Peak memory 212352 kb
Host smart-856ae21d-4960-4f86-92a9-53b1a17304d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293857306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3293857306
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.1113630047
Short name T277
Test name
Test status
Simulation time 385994713 ps
CPU time 8.11 seconds
Started Apr 15 03:33:50 PM PDT 24
Finished Apr 15 03:33:58 PM PDT 24
Peak memory 283468 kb
Host smart-9f43b157-fa4b-411d-b83c-4f80ce9a9fb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113630047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.1113630047
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.2590619716
Short name T371
Test name
Test status
Simulation time 5280653076 ps
CPU time 88.62 seconds
Started Apr 15 03:33:50 PM PDT 24
Finished Apr 15 03:35:19 PM PDT 24
Peak memory 534204 kb
Host smart-f1d17d47-01e6-4274-976b-75fe324ddea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590619716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2590619716
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.3704530423
Short name T980
Test name
Test status
Simulation time 7125120875 ps
CPU time 35.39 seconds
Started Apr 15 03:33:51 PM PDT 24
Finished Apr 15 03:34:27 PM PDT 24
Peak memory 486136 kb
Host smart-bb77c88e-70da-4a2f-bc75-4feabf254bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704530423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.3704530423
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.2069088685
Short name T973
Test name
Test status
Simulation time 359745713 ps
CPU time 0.88 seconds
Started Apr 15 03:33:52 PM PDT 24
Finished Apr 15 03:33:54 PM PDT 24
Peak memory 203744 kb
Host smart-fd9c3144-680f-4fbe-8c7b-b0d386ee54ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069088685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.2069088685
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.1289492431
Short name T866
Test name
Test status
Simulation time 483277585 ps
CPU time 4.72 seconds
Started Apr 15 03:33:49 PM PDT 24
Finished Apr 15 03:33:54 PM PDT 24
Peak memory 233948 kb
Host smart-bc33ce32-beea-4e9c-ac04-613ea07fb1b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289492431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.1289492431
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.1391499956
Short name T449
Test name
Test status
Simulation time 9031326255 ps
CPU time 147.16 seconds
Started Apr 15 03:33:51 PM PDT 24
Finished Apr 15 03:36:19 PM PDT 24
Peak memory 1303384 kb
Host smart-ab2c0da1-6fe2-401e-b48d-17d01c3d0aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391499956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1391499956
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.1676805292
Short name T473
Test name
Test status
Simulation time 1826123612 ps
CPU time 90.63 seconds
Started Apr 15 03:33:58 PM PDT 24
Finished Apr 15 03:35:30 PM PDT 24
Peak memory 334024 kb
Host smart-e1769ede-5495-488a-9a17-9890228f784c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676805292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.1676805292
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.3358230834
Short name T199
Test name
Test status
Simulation time 38166731 ps
CPU time 0.68 seconds
Started Apr 15 03:34:02 PM PDT 24
Finished Apr 15 03:34:03 PM PDT 24
Peak memory 203688 kb
Host smart-78e21662-a324-41d0-ae37-e41c8af332df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358230834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3358230834
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.1566596303
Short name T325
Test name
Test status
Simulation time 5225900086 ps
CPU time 64.72 seconds
Started Apr 15 03:33:54 PM PDT 24
Finished Apr 15 03:34:59 PM PDT 24
Peak memory 220988 kb
Host smart-ce9cadc7-ee91-49e3-a123-cece63c3315d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566596303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.1566596303
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.873450032
Short name T713
Test name
Test status
Simulation time 7910670140 ps
CPU time 23.93 seconds
Started Apr 15 03:33:53 PM PDT 24
Finished Apr 15 03:34:18 PM PDT 24
Peak memory 360324 kb
Host smart-b8859763-428d-4914-ab3e-ffbde0e7bc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873450032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.873450032
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.3808072439
Short name T557
Test name
Test status
Simulation time 16945567429 ps
CPU time 890.05 seconds
Started Apr 15 03:33:54 PM PDT 24
Finished Apr 15 03:48:45 PM PDT 24
Peak memory 1602784 kb
Host smart-b42454f8-d7c5-424f-85e0-403d9d7c1c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808072439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.3808072439
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.3927364025
Short name T1308
Test name
Test status
Simulation time 1158182677 ps
CPU time 9.55 seconds
Started Apr 15 03:33:52 PM PDT 24
Finished Apr 15 03:34:03 PM PDT 24
Peak memory 219212 kb
Host smart-3722420b-6822-456a-9fce-acad56d84fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927364025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3927364025
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.2804058430
Short name T1144
Test name
Test status
Simulation time 965334740 ps
CPU time 4.33 seconds
Started Apr 15 03:33:59 PM PDT 24
Finished Apr 15 03:34:04 PM PDT 24
Peak memory 212796 kb
Host smart-4637fdfb-81ac-419d-a0bf-4d7afd7252eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804058430 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.2804058430
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.1846433876
Short name T49
Test name
Test status
Simulation time 10196689306 ps
CPU time 26.95 seconds
Started Apr 15 03:33:56 PM PDT 24
Finished Apr 15 03:34:23 PM PDT 24
Peak memory 348836 kb
Host smart-a659a356-31d6-4a6f-8304-de65cfbc7a16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846433876 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.1846433876
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.1621899778
Short name T937
Test name
Test status
Simulation time 10127278929 ps
CPU time 70.38 seconds
Started Apr 15 03:34:00 PM PDT 24
Finished Apr 15 03:35:11 PM PDT 24
Peak memory 543712 kb
Host smart-5f1c0737-4d5b-4298-ace2-778b9520a996
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621899778 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.1621899778
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.1120265845
Short name T1254
Test name
Test status
Simulation time 281598518 ps
CPU time 1.88 seconds
Started Apr 15 03:33:58 PM PDT 24
Finished Apr 15 03:34:01 PM PDT 24
Peak memory 203972 kb
Host smart-b98c8491-8ed1-4660-b57a-a07fe141d835
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120265845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.1120265845
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.3349937856
Short name T317
Test name
Test status
Simulation time 1008343213 ps
CPU time 3.13 seconds
Started Apr 15 03:33:54 PM PDT 24
Finished Apr 15 03:33:58 PM PDT 24
Peak memory 204000 kb
Host smart-bf947487-f0e6-4c49-b7bd-b234b6e0dea4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349937856 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.3349937856
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.3596488606
Short name T513
Test name
Test status
Simulation time 24136787683 ps
CPU time 533.61 seconds
Started Apr 15 03:33:57 PM PDT 24
Finished Apr 15 03:42:52 PM PDT 24
Peak memory 4143420 kb
Host smart-145ada81-a482-458e-8e07-fd8e179f5ecb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596488606 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.3596488606
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.1882156765
Short name T1270
Test name
Test status
Simulation time 616145215 ps
CPU time 8.2 seconds
Started Apr 15 03:33:55 PM PDT 24
Finished Apr 15 03:34:04 PM PDT 24
Peak memory 203988 kb
Host smart-af2401c6-3343-4c0d-a45d-88be5203cb85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882156765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.1882156765
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.2962499435
Short name T611
Test name
Test status
Simulation time 397685808 ps
CPU time 7.3 seconds
Started Apr 15 03:33:53 PM PDT 24
Finished Apr 15 03:34:01 PM PDT 24
Peak memory 204056 kb
Host smart-47dd1f03-f797-40f7-97e9-62a9999934fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962499435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.2962499435
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.4187479805
Short name T694
Test name
Test status
Simulation time 12145907271 ps
CPU time 11.54 seconds
Started Apr 15 03:33:58 PM PDT 24
Finished Apr 15 03:34:10 PM PDT 24
Peak memory 204048 kb
Host smart-6b35c2ae-1ddc-4371-b425-1ab4b35ae1bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187479805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.4187479805
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.1328748910
Short name T1224
Test name
Test status
Simulation time 27283809622 ps
CPU time 1038.33 seconds
Started Apr 15 03:33:55 PM PDT 24
Finished Apr 15 03:51:14 PM PDT 24
Peak memory 2308588 kb
Host smart-0d283b18-a795-4fb4-82f0-d6c79545a890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328748910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.1328748910
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.3687600845
Short name T251
Test name
Test status
Simulation time 3035613005 ps
CPU time 7.55 seconds
Started Apr 15 03:33:56 PM PDT 24
Finished Apr 15 03:34:04 PM PDT 24
Peak memory 204056 kb
Host smart-7280fb8e-fb48-4805-a865-5b72e8180c91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687600845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.3687600845
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.2263333035
Short name T447
Test name
Test status
Simulation time 33978177 ps
CPU time 0.61 seconds
Started Apr 15 03:34:14 PM PDT 24
Finished Apr 15 03:34:16 PM PDT 24
Peak memory 203564 kb
Host smart-2f05dff8-1c44-44bb-ad32-ee0847ac9fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263333035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.2263333035
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.3706417648
Short name T1133
Test name
Test status
Simulation time 81865615 ps
CPU time 1.45 seconds
Started Apr 15 03:34:00 PM PDT 24
Finished Apr 15 03:34:03 PM PDT 24
Peak memory 212328 kb
Host smart-5edbea3a-ace0-446e-a63d-0302690983cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706417648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.3706417648
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.436316733
Short name T1076
Test name
Test status
Simulation time 1113295626 ps
CPU time 13.23 seconds
Started Apr 15 03:34:07 PM PDT 24
Finished Apr 15 03:34:21 PM PDT 24
Peak memory 241120 kb
Host smart-838dfc4d-c03d-422f-a16f-cf5fd091c308
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436316733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt
y.436316733
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.1165100677
Short name T112
Test name
Test status
Simulation time 3723680230 ps
CPU time 51.93 seconds
Started Apr 15 03:34:03 PM PDT 24
Finished Apr 15 03:34:56 PM PDT 24
Peak memory 629288 kb
Host smart-e578625b-b8e8-4f7d-9df1-3b44ab555a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165100677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.1165100677
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.3643338148
Short name T458
Test name
Test status
Simulation time 2944011849 ps
CPU time 102.38 seconds
Started Apr 15 03:34:02 PM PDT 24
Finished Apr 15 03:35:45 PM PDT 24
Peak memory 542304 kb
Host smart-0e43a284-cdc8-438e-b6b7-06545d10ee32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643338148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.3643338148
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.1598288473
Short name T798
Test name
Test status
Simulation time 1461940380 ps
CPU time 2.85 seconds
Started Apr 15 03:34:02 PM PDT 24
Finished Apr 15 03:34:05 PM PDT 24
Peak memory 203940 kb
Host smart-83c18fa0-4203-443f-a6f5-bbef6bd36b49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598288473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.1598288473
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.1774462639
Short name T182
Test name
Test status
Simulation time 4785986818 ps
CPU time 67.06 seconds
Started Apr 15 03:34:02 PM PDT 24
Finished Apr 15 03:35:10 PM PDT 24
Peak memory 895400 kb
Host smart-e41d8477-682d-40d8-ba65-a9ed69431bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774462639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.1774462639
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.363364095
Short name T859
Test name
Test status
Simulation time 1185432416 ps
CPU time 4.09 seconds
Started Apr 15 03:34:12 PM PDT 24
Finished Apr 15 03:34:17 PM PDT 24
Peak memory 203988 kb
Host smart-9b98c53c-3be4-4c1f-a5da-b3508f8f559f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363364095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.363364095
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.198950617
Short name T347
Test name
Test status
Simulation time 7830165905 ps
CPU time 59.97 seconds
Started Apr 15 03:34:10 PM PDT 24
Finished Apr 15 03:35:11 PM PDT 24
Peak memory 300984 kb
Host smart-252836e5-973d-4b75-9b17-4268408dbace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198950617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.198950617
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_perf.2602877398
Short name T1054
Test name
Test status
Simulation time 48194803139 ps
CPU time 90.05 seconds
Started Apr 15 03:34:02 PM PDT 24
Finished Apr 15 03:35:33 PM PDT 24
Peak memory 246764 kb
Host smart-4cf00f2b-8ae0-47bc-97b3-03774741c23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602877398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2602877398
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.1822428168
Short name T435
Test name
Test status
Simulation time 3941812981 ps
CPU time 33.7 seconds
Started Apr 15 03:34:04 PM PDT 24
Finished Apr 15 03:34:38 PM PDT 24
Peak memory 347728 kb
Host smart-4d73d6d8-28ab-487b-b7c0-8751b4129a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822428168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.1822428168
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.581826768
Short name T493
Test name
Test status
Simulation time 6563423521 ps
CPU time 14.82 seconds
Started Apr 15 03:34:00 PM PDT 24
Finished Apr 15 03:34:15 PM PDT 24
Peak memory 212244 kb
Host smart-117405a6-78fe-4533-9b99-cb9e350257aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581826768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.581826768
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.1922796725
Short name T28
Test name
Test status
Simulation time 454645769 ps
CPU time 2.46 seconds
Started Apr 15 03:34:07 PM PDT 24
Finished Apr 15 03:34:10 PM PDT 24
Peak memory 204040 kb
Host smart-f906b48b-a08a-41bb-a43e-2e68afcb42ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922796725 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.1922796725
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.3585829342
Short name T538
Test name
Test status
Simulation time 10193959789 ps
CPU time 5.91 seconds
Started Apr 15 03:34:04 PM PDT 24
Finished Apr 15 03:34:11 PM PDT 24
Peak memory 222236 kb
Host smart-bc69eed0-45d7-4383-9728-2e398b185581
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585829342 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.3585829342
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.388979975
Short name T1204
Test name
Test status
Simulation time 10166568925 ps
CPU time 13.34 seconds
Started Apr 15 03:34:04 PM PDT 24
Finished Apr 15 03:34:18 PM PDT 24
Peak memory 284712 kb
Host smart-668934a0-6567-4c05-9722-fa02bec08fb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388979975 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_fifo_reset_tx.388979975
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.229673657
Short name T864
Test name
Test status
Simulation time 4413886364 ps
CPU time 2.4 seconds
Started Apr 15 03:34:09 PM PDT 24
Finished Apr 15 03:34:13 PM PDT 24
Peak memory 204080 kb
Host smart-0c0d9950-87d5-4349-a5b4-797909d21fbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229673657 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.i2c_target_hrst.229673657
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.776208126
Short name T809
Test name
Test status
Simulation time 712538956 ps
CPU time 3.37 seconds
Started Apr 15 03:34:05 PM PDT 24
Finished Apr 15 03:34:09 PM PDT 24
Peak memory 203972 kb
Host smart-84bd4572-34d8-4d00-a04e-6bc85087d119
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776208126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_intr_smoke.776208126
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.3297156205
Short name T448
Test name
Test status
Simulation time 18191169428 ps
CPU time 40.98 seconds
Started Apr 15 03:34:03 PM PDT 24
Finished Apr 15 03:34:44 PM PDT 24
Peak memory 737644 kb
Host smart-f6851f64-0715-47e7-a6e8-b0be74bb0423
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297156205 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.3297156205
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.2140716797
Short name T108
Test name
Test status
Simulation time 3515382995 ps
CPU time 10.96 seconds
Started Apr 15 03:34:05 PM PDT 24
Finished Apr 15 03:34:17 PM PDT 24
Peak memory 204020 kb
Host smart-5bfbc155-1b54-47fc-be28-dc9fc653674e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140716797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.2140716797
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.622427636
Short name T803
Test name
Test status
Simulation time 1534312287 ps
CPU time 26.16 seconds
Started Apr 15 03:34:09 PM PDT 24
Finished Apr 15 03:34:36 PM PDT 24
Peak memory 238648 kb
Host smart-471bfd56-dcb0-45be-b4f1-55e179334ead
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622427636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_rd.622427636
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.3367176775
Short name T841
Test name
Test status
Simulation time 59134208976 ps
CPU time 1628.73 seconds
Started Apr 15 03:34:06 PM PDT 24
Finished Apr 15 04:01:16 PM PDT 24
Peak memory 8221672 kb
Host smart-196eb5c0-dc05-4783-a81f-85f437b4b5ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367176775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.3367176775
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.1187224750
Short name T584
Test name
Test status
Simulation time 10041649958 ps
CPU time 283.59 seconds
Started Apr 15 03:34:05 PM PDT 24
Finished Apr 15 03:38:50 PM PDT 24
Peak memory 2330436 kb
Host smart-7a9d7ff3-035c-4fa1-a583-8e15429f1f58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187224750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.1187224750
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.1456040861
Short name T455
Test name
Test status
Simulation time 1612320907 ps
CPU time 7.27 seconds
Started Apr 15 03:34:05 PM PDT 24
Finished Apr 15 03:34:13 PM PDT 24
Peak memory 204028 kb
Host smart-33b6cdaf-59f7-4e39-adac-2f06c8df75ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456040861 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.1456040861
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_unexp_stop.3047533916
Short name T19
Test name
Test status
Simulation time 4014614308 ps
CPU time 9.65 seconds
Started Apr 15 03:34:04 PM PDT 24
Finished Apr 15 03:34:15 PM PDT 24
Peak memory 204108 kb
Host smart-8d2ab082-4c0f-4381-bf69-437dae689980
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047533916 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.i2c_target_unexp_stop.3047533916
Directory /workspace/42.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/43.i2c_alert_test.3615747467
Short name T1359
Test name
Test status
Simulation time 18314460 ps
CPU time 0.63 seconds
Started Apr 15 03:34:21 PM PDT 24
Finished Apr 15 03:34:22 PM PDT 24
Peak memory 203544 kb
Host smart-bb981f89-1a09-45af-9902-8981379afe52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615747467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.3615747467
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.2598894443
Short name T427
Test name
Test status
Simulation time 434798330 ps
CPU time 1.51 seconds
Started Apr 15 03:34:07 PM PDT 24
Finished Apr 15 03:34:10 PM PDT 24
Peak memory 212292 kb
Host smart-c1a99f82-51cc-4127-af1d-75e1b9a34687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598894443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.2598894443
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.2527228157
Short name T896
Test name
Test status
Simulation time 1233724396 ps
CPU time 7.01 seconds
Started Apr 15 03:34:11 PM PDT 24
Finished Apr 15 03:34:19 PM PDT 24
Peak memory 268836 kb
Host smart-1aa0c64a-455e-4625-a74b-c78af9f4f407
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527228157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.2527228157
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.5380413
Short name T1360
Test name
Test status
Simulation time 5454178583 ps
CPU time 191.42 seconds
Started Apr 15 03:34:14 PM PDT 24
Finished Apr 15 03:37:27 PM PDT 24
Peak memory 815756 kb
Host smart-f60c2563-2597-4615-b06d-69c2c9a6e5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5380413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.5380413
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.2276884693
Short name T1337
Test name
Test status
Simulation time 1226402901 ps
CPU time 76.67 seconds
Started Apr 15 03:34:08 PM PDT 24
Finished Apr 15 03:35:26 PM PDT 24
Peak memory 472832 kb
Host smart-5d262033-32b2-4908-b239-741ad9b33e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276884693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.2276884693
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.842048059
Short name T632
Test name
Test status
Simulation time 156278840 ps
CPU time 0.96 seconds
Started Apr 15 03:34:11 PM PDT 24
Finished Apr 15 03:34:13 PM PDT 24
Peak memory 203720 kb
Host smart-63a8b0a2-d0f0-461a-a585-36a3f71587fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842048059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.842048059
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.294048623
Short name T1106
Test name
Test status
Simulation time 682932966 ps
CPU time 9.8 seconds
Started Apr 15 03:34:12 PM PDT 24
Finished Apr 15 03:34:22 PM PDT 24
Peak memory 235840 kb
Host smart-616c2f70-f10c-4a71-b672-3677e852468a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294048623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.
294048623
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.755942372
Short name T502
Test name
Test status
Simulation time 4208387339 ps
CPU time 309.17 seconds
Started Apr 15 03:34:11 PM PDT 24
Finished Apr 15 03:39:22 PM PDT 24
Peak memory 1163840 kb
Host smart-2b09a0a6-555a-4a5e-aa76-cff0dbcc621b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755942372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.755942372
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.3157563792
Short name T1243
Test name
Test status
Simulation time 1041983867 ps
CPU time 8.3 seconds
Started Apr 15 03:34:15 PM PDT 24
Finished Apr 15 03:34:24 PM PDT 24
Peak memory 203940 kb
Host smart-145d1eee-5a02-4b7c-9994-04de0d46e343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157563792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.3157563792
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.3063444713
Short name T516
Test name
Test status
Simulation time 1615176484 ps
CPU time 26.6 seconds
Started Apr 15 03:34:15 PM PDT 24
Finished Apr 15 03:34:43 PM PDT 24
Peak memory 319804 kb
Host smart-b4ae4e1f-d9ac-465b-b6bc-f77584f9f34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063444713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.3063444713
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.534468237
Short name T212
Test name
Test status
Simulation time 97162914 ps
CPU time 0.65 seconds
Started Apr 15 03:34:11 PM PDT 24
Finished Apr 15 03:34:13 PM PDT 24
Peak memory 203676 kb
Host smart-e2401969-dd3b-4adf-b886-cbf19742f51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534468237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.534468237
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.2155340903
Short name T992
Test name
Test status
Simulation time 7770542418 ps
CPU time 158.21 seconds
Started Apr 15 03:34:14 PM PDT 24
Finished Apr 15 03:36:54 PM PDT 24
Peak memory 220288 kb
Host smart-0cddb68e-98e2-4f86-b508-a29a1fb4f19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155340903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.2155340903
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.2675108648
Short name T431
Test name
Test status
Simulation time 1589691244 ps
CPU time 81.45 seconds
Started Apr 15 03:34:14 PM PDT 24
Finished Apr 15 03:35:36 PM PDT 24
Peak memory 404908 kb
Host smart-bbb12c46-c462-4a39-8a69-f493f8f01b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675108648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.2675108648
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.1556920842
Short name T595
Test name
Test status
Simulation time 677606274 ps
CPU time 8.71 seconds
Started Apr 15 03:34:11 PM PDT 24
Finished Apr 15 03:34:21 PM PDT 24
Peak memory 227980 kb
Host smart-f36c8bbf-a4d7-4480-b92d-942f8c813a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556920842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.1556920842
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.2285549900
Short name T270
Test name
Test status
Simulation time 17093957946 ps
CPU time 4.88 seconds
Started Apr 15 03:34:14 PM PDT 24
Finished Apr 15 03:34:20 PM PDT 24
Peak memory 205588 kb
Host smart-3f366e1f-a1f7-4230-ba03-7835605db2fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285549900 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.2285549900
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.1897583613
Short name T401
Test name
Test status
Simulation time 10385027215 ps
CPU time 13.31 seconds
Started Apr 15 03:34:14 PM PDT 24
Finished Apr 15 03:34:29 PM PDT 24
Peak memory 281860 kb
Host smart-26a8df35-ae2d-4ab7-84cb-ee38197700c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897583613 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.1897583613
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.220185119
Short name T1013
Test name
Test status
Simulation time 10468596299 ps
CPU time 14.53 seconds
Started Apr 15 03:34:12 PM PDT 24
Finished Apr 15 03:34:28 PM PDT 24
Peak memory 283920 kb
Host smart-59e01048-634c-4e6b-a45c-b8e77ed9c6ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220185119 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_fifo_reset_tx.220185119
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.1912654350
Short name T491
Test name
Test status
Simulation time 546148660 ps
CPU time 2.87 seconds
Started Apr 15 03:34:12 PM PDT 24
Finished Apr 15 03:34:16 PM PDT 24
Peak memory 204012 kb
Host smart-9885b0fe-58b4-4d7b-bec2-4081f237b5fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912654350 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.1912654350
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.2331774384
Short name T510
Test name
Test status
Simulation time 1347932331 ps
CPU time 6.9 seconds
Started Apr 15 03:34:12 PM PDT 24
Finished Apr 15 03:34:20 PM PDT 24
Peak memory 215004 kb
Host smart-54f0f081-bfd0-4a00-a5b1-b737da19764f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331774384 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.2331774384
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.2997647137
Short name T1000
Test name
Test status
Simulation time 3110711450 ps
CPU time 2.59 seconds
Started Apr 15 03:34:15 PM PDT 24
Finished Apr 15 03:34:18 PM PDT 24
Peak memory 204012 kb
Host smart-35411efc-e2ea-42e7-90f7-24e1f205f5c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997647137 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2997647137
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.530535246
Short name T1232
Test name
Test status
Simulation time 998224896 ps
CPU time 40.77 seconds
Started Apr 15 03:34:15 PM PDT 24
Finished Apr 15 03:34:57 PM PDT 24
Peak memory 204048 kb
Host smart-58a7e256-25ee-422c-91b2-5eda3bf652c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530535246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_tar
get_smoke.530535246
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.2159883854
Short name T1343
Test name
Test status
Simulation time 241466580 ps
CPU time 3.84 seconds
Started Apr 15 03:34:14 PM PDT 24
Finished Apr 15 03:34:19 PM PDT 24
Peak memory 204016 kb
Host smart-1a11ccaa-bb5c-4ab4-b95a-71ed75d8392d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159883854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.2159883854
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.3554328068
Short name T1020
Test name
Test status
Simulation time 7244375468 ps
CPU time 6.75 seconds
Started Apr 15 03:34:13 PM PDT 24
Finished Apr 15 03:34:21 PM PDT 24
Peak memory 203952 kb
Host smart-6210b1ed-7a63-4c87-b89f-5d77a8736739
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554328068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.3554328068
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.2008862440
Short name T247
Test name
Test status
Simulation time 38175782880 ps
CPU time 1150.05 seconds
Started Apr 15 03:34:17 PM PDT 24
Finished Apr 15 03:53:28 PM PDT 24
Peak memory 4396564 kb
Host smart-7b6ec2eb-c8bd-4251-be05-06c62ed5458c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008862440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.2008862440
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.2529113799
Short name T1074
Test name
Test status
Simulation time 4594699277 ps
CPU time 6.26 seconds
Started Apr 15 03:34:15 PM PDT 24
Finished Apr 15 03:34:22 PM PDT 24
Peak memory 212280 kb
Host smart-4cdd099b-4556-42ac-9d4d-8e134aab4510
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529113799 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.2529113799
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.1415821450
Short name T1314
Test name
Test status
Simulation time 60649996 ps
CPU time 0.61 seconds
Started Apr 15 03:34:24 PM PDT 24
Finished Apr 15 03:34:25 PM PDT 24
Peak memory 203560 kb
Host smart-d7fc7080-ae7c-4a20-adac-b16290ac3007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415821450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.1415821450
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3305713906
Short name T560
Test name
Test status
Simulation time 658501539 ps
CPU time 1.21 seconds
Started Apr 15 03:34:21 PM PDT 24
Finished Apr 15 03:34:23 PM PDT 24
Peak memory 204084 kb
Host smart-ca82ab1d-e0b6-43c7-abb6-2b5af0f31632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305713906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3305713906
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.3177227389
Short name T1180
Test name
Test status
Simulation time 318773998 ps
CPU time 6.04 seconds
Started Apr 15 03:34:17 PM PDT 24
Finished Apr 15 03:34:24 PM PDT 24
Peak memory 268968 kb
Host smart-aeeaa7c7-8ff8-4028-83be-60924356d216
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177227389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.3177227389
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.210588421
Short name T728
Test name
Test status
Simulation time 37619816836 ps
CPU time 138.7 seconds
Started Apr 15 03:34:26 PM PDT 24
Finished Apr 15 03:36:45 PM PDT 24
Peak memory 674316 kb
Host smart-dc407ada-48e8-4ed3-a5e8-8041ed80d7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210588421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.210588421
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.1157938848
Short name T1183
Test name
Test status
Simulation time 2114156826 ps
CPU time 51 seconds
Started Apr 15 03:34:19 PM PDT 24
Finished Apr 15 03:35:11 PM PDT 24
Peak memory 566592 kb
Host smart-09d7223a-455b-4af1-bf7a-b73d74928a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157938848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.1157938848
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.1378069829
Short name T1099
Test name
Test status
Simulation time 218357839 ps
CPU time 1 seconds
Started Apr 15 03:34:15 PM PDT 24
Finished Apr 15 03:34:17 PM PDT 24
Peak memory 203712 kb
Host smart-bf1888ed-c994-4eca-9144-c7080356f56a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378069829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.1378069829
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.4278245537
Short name T407
Test name
Test status
Simulation time 982614963 ps
CPU time 3.73 seconds
Started Apr 15 03:34:14 PM PDT 24
Finished Apr 15 03:34:18 PM PDT 24
Peak memory 203920 kb
Host smart-3fe7fdde-ba43-494c-8cef-e0e283089d7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278245537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.4278245537
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.2012500766
Short name T530
Test name
Test status
Simulation time 9113047150 ps
CPU time 358.58 seconds
Started Apr 15 03:34:22 PM PDT 24
Finished Apr 15 03:40:22 PM PDT 24
Peak memory 1235980 kb
Host smart-9ce7bc68-0f4c-4f9e-a6fc-5d4516fc8e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012500766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2012500766
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.929355414
Short name T574
Test name
Test status
Simulation time 1667534287 ps
CPU time 6.83 seconds
Started Apr 15 03:34:34 PM PDT 24
Finished Apr 15 03:34:42 PM PDT 24
Peak memory 203988 kb
Host smart-1b220095-9e1c-4db7-bb78-05d3c4d1a09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929355414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.929355414
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.831200248
Short name T1218
Test name
Test status
Simulation time 2902791918 ps
CPU time 67.76 seconds
Started Apr 15 03:34:25 PM PDT 24
Finished Apr 15 03:35:34 PM PDT 24
Peak memory 322116 kb
Host smart-dcd164f5-6642-4c76-b9d8-772b0f575a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831200248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.831200248
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.2120948466
Short name T1116
Test name
Test status
Simulation time 86751345 ps
CPU time 0.67 seconds
Started Apr 15 03:34:16 PM PDT 24
Finished Apr 15 03:34:17 PM PDT 24
Peak memory 203652 kb
Host smart-415f6c45-3082-4dd9-ab64-27d4d31cba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120948466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.2120948466
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.817868151
Short name T353
Test name
Test status
Simulation time 2930379666 ps
CPU time 29.28 seconds
Started Apr 15 03:34:16 PM PDT 24
Finished Apr 15 03:34:46 PM PDT 24
Peak memory 225720 kb
Host smart-7ee539b3-0817-4d72-ba8e-36dad611b7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817868151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.817868151
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.3424253669
Short name T592
Test name
Test status
Simulation time 948177319 ps
CPU time 17.46 seconds
Started Apr 15 03:34:17 PM PDT 24
Finished Apr 15 03:34:35 PM PDT 24
Peak memory 280716 kb
Host smart-8f682aca-5130-4fef-85bf-cdc675bd64db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424253669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.3424253669
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.3170215330
Short name T1244
Test name
Test status
Simulation time 1952670087 ps
CPU time 18.08 seconds
Started Apr 15 03:34:14 PM PDT 24
Finished Apr 15 03:34:33 PM PDT 24
Peak memory 218788 kb
Host smart-1d7cd0a5-136e-4d18-ae21-8124c969697a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170215330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.3170215330
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3848195173
Short name T1252
Test name
Test status
Simulation time 597350503 ps
CPU time 3.2 seconds
Started Apr 15 03:34:21 PM PDT 24
Finished Apr 15 03:34:25 PM PDT 24
Peak memory 203968 kb
Host smart-c66e0b17-6077-4377-a41e-d261191e3189
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848195173 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3848195173
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.2106179935
Short name T1282
Test name
Test status
Simulation time 10144292650 ps
CPU time 29.28 seconds
Started Apr 15 03:34:20 PM PDT 24
Finished Apr 15 03:34:50 PM PDT 24
Peak memory 373832 kb
Host smart-41e1f2a4-be75-4c87-a801-3a656fa3b386
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106179935 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.2106179935
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.3411996312
Short name T1336
Test name
Test status
Simulation time 206589145 ps
CPU time 1.54 seconds
Started Apr 15 03:34:20 PM PDT 24
Finished Apr 15 03:34:23 PM PDT 24
Peak memory 203976 kb
Host smart-13b36c9b-5bbf-4ed1-bfea-d710a6906f3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411996312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.3411996312
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.4247812844
Short name T748
Test name
Test status
Simulation time 895046684 ps
CPU time 4.77 seconds
Started Apr 15 03:34:22 PM PDT 24
Finished Apr 15 03:34:27 PM PDT 24
Peak memory 204012 kb
Host smart-c8a0b25c-6984-4fc2-9876-e4143cc1e01a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247812844 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.4247812844
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.1855534236
Short name T494
Test name
Test status
Simulation time 17874565441 ps
CPU time 34.16 seconds
Started Apr 15 03:34:19 PM PDT 24
Finished Apr 15 03:34:55 PM PDT 24
Peak memory 688836 kb
Host smart-666e8da1-6a8d-49eb-b7b9-04e7ad97684a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855534236 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.1855534236
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.29411815
Short name T1101
Test name
Test status
Simulation time 1529223849 ps
CPU time 11.88 seconds
Started Apr 15 03:34:22 PM PDT 24
Finished Apr 15 03:34:35 PM PDT 24
Peak memory 203996 kb
Host smart-87840ca4-5ded-424c-aaf9-d766acbdf437
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29411815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_targ
et_smoke.29411815
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.2414233391
Short name T198
Test name
Test status
Simulation time 6914246410 ps
CPU time 28.04 seconds
Started Apr 15 03:34:33 PM PDT 24
Finished Apr 15 03:35:02 PM PDT 24
Peak memory 227224 kb
Host smart-2871d627-ecb9-4344-af9a-0966cb662e7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414233391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.2414233391
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.548371359
Short name T472
Test name
Test status
Simulation time 15733197918 ps
CPU time 29.26 seconds
Started Apr 15 03:34:23 PM PDT 24
Finished Apr 15 03:34:53 PM PDT 24
Peak memory 204020 kb
Host smart-14a613a0-9c92-4a11-9524-214479b103e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548371359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_wr.548371359
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.2681625148
Short name T669
Test name
Test status
Simulation time 17862328841 ps
CPU time 376.95 seconds
Started Apr 15 03:34:20 PM PDT 24
Finished Apr 15 03:40:38 PM PDT 24
Peak memory 2539608 kb
Host smart-a0eaae88-518e-43a6-b711-07b725ed8d93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681625148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.2681625148
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.1711377714
Short name T796
Test name
Test status
Simulation time 5457764025 ps
CPU time 6.73 seconds
Started Apr 15 03:34:33 PM PDT 24
Finished Apr 15 03:34:41 PM PDT 24
Peak memory 204080 kb
Host smart-354d8155-8b4b-4b0d-967d-48ddb1d3c742
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711377714 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.1711377714
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_unexp_stop.3352772537
Short name T1147
Test name
Test status
Simulation time 5037581454 ps
CPU time 5.66 seconds
Started Apr 15 03:34:21 PM PDT 24
Finished Apr 15 03:34:28 PM PDT 24
Peak memory 206096 kb
Host smart-7981ddfd-de4a-4615-b764-51c981219474
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352772537 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.i2c_target_unexp_stop.3352772537
Directory /workspace/44.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/45.i2c_alert_test.3272939911
Short name T387
Test name
Test status
Simulation time 17742619 ps
CPU time 0.63 seconds
Started Apr 15 03:34:32 PM PDT 24
Finished Apr 15 03:34:33 PM PDT 24
Peak memory 203564 kb
Host smart-03c79c32-80bc-415b-b27a-536729665767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272939911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.3272939911
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.3307383286
Short name T874
Test name
Test status
Simulation time 144706613 ps
CPU time 1.25 seconds
Started Apr 15 03:34:27 PM PDT 24
Finished Apr 15 03:34:29 PM PDT 24
Peak memory 204056 kb
Host smart-f3dfb4da-9dd9-4546-95a3-f0ee14dc7abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307383286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3307383286
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.1523404782
Short name T776
Test name
Test status
Simulation time 191986898 ps
CPU time 4.02 seconds
Started Apr 15 03:34:25 PM PDT 24
Finished Apr 15 03:34:29 PM PDT 24
Peak memory 239780 kb
Host smart-c6a121b2-a34b-488c-847f-563f10b9db27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523404782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.1523404782
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.4060219963
Short name T111
Test name
Test status
Simulation time 4650451025 ps
CPU time 70.39 seconds
Started Apr 15 03:34:34 PM PDT 24
Finished Apr 15 03:35:45 PM PDT 24
Peak memory 784880 kb
Host smart-625ddce4-1e19-4880-9865-f15c750d71ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060219963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.4060219963
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.1686227474
Short name T1315
Test name
Test status
Simulation time 2361215834 ps
CPU time 83.3 seconds
Started Apr 15 03:34:26 PM PDT 24
Finished Apr 15 03:35:50 PM PDT 24
Peak memory 730452 kb
Host smart-35960342-09b3-4ca0-8108-f617d409b4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686227474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.1686227474
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.3334793853
Short name T555
Test name
Test status
Simulation time 642607038 ps
CPU time 1.11 seconds
Started Apr 15 03:34:23 PM PDT 24
Finished Apr 15 03:34:25 PM PDT 24
Peak memory 204076 kb
Host smart-090ebcef-fc5d-4644-8b4a-82f61344da58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334793853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.3334793853
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.1169857370
Short name T1146
Test name
Test status
Simulation time 517635976 ps
CPU time 5.9 seconds
Started Apr 15 03:34:23 PM PDT 24
Finished Apr 15 03:34:30 PM PDT 24
Peak memory 203984 kb
Host smart-6dc9136a-d19a-40a1-a25d-83a4132c23d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169857370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.1169857370
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.1430514531
Short name T1257
Test name
Test status
Simulation time 9973405749 ps
CPU time 150.71 seconds
Started Apr 15 03:34:25 PM PDT 24
Finished Apr 15 03:36:57 PM PDT 24
Peak memory 768492 kb
Host smart-392f7c92-fbde-45cf-a4a5-763bd1a47f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430514531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1430514531
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.2818237731
Short name T903
Test name
Test status
Simulation time 610065133 ps
CPU time 3.63 seconds
Started Apr 15 03:34:33 PM PDT 24
Finished Apr 15 03:34:38 PM PDT 24
Peak memory 203956 kb
Host smart-f4f4a060-93aa-4fec-81e9-b0da1dbf068f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818237731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.2818237731
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.1840436854
Short name T638
Test name
Test status
Simulation time 3376774876 ps
CPU time 25.82 seconds
Started Apr 15 03:34:31 PM PDT 24
Finished Apr 15 03:34:57 PM PDT 24
Peak memory 364416 kb
Host smart-5eae5a8b-1293-439a-a192-c7702685d511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840436854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.1840436854
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.260666845
Short name T281
Test name
Test status
Simulation time 27066223 ps
CPU time 0.64 seconds
Started Apr 15 03:34:22 PM PDT 24
Finished Apr 15 03:34:23 PM PDT 24
Peak memory 203676 kb
Host smart-2e7bdf26-ac96-4df8-966d-e9f5a202f522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260666845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.260666845
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.2853851196
Short name T9
Test name
Test status
Simulation time 6857649821 ps
CPU time 132.32 seconds
Started Apr 15 03:34:22 PM PDT 24
Finished Apr 15 03:36:36 PM PDT 24
Peak memory 203996 kb
Host smart-33e93576-32d4-4730-a071-17cc92c9f0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853851196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.2853851196
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.124447995
Short name T1353
Test name
Test status
Simulation time 4337507802 ps
CPU time 19.79 seconds
Started Apr 15 03:34:34 PM PDT 24
Finished Apr 15 03:34:55 PM PDT 24
Peak memory 284204 kb
Host smart-f098b346-6398-4b61-bfda-94109c4e340b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124447995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.124447995
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.456715694
Short name T1219
Test name
Test status
Simulation time 612993758 ps
CPU time 2.81 seconds
Started Apr 15 03:34:28 PM PDT 24
Finished Apr 15 03:34:31 PM PDT 24
Peak memory 204036 kb
Host smart-63398df7-7c8a-41fc-a6ac-55500425a1e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456715694 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.456715694
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.2956253952
Short name T1250
Test name
Test status
Simulation time 10142083988 ps
CPU time 9.83 seconds
Started Apr 15 03:34:26 PM PDT 24
Finished Apr 15 03:34:37 PM PDT 24
Peak memory 253348 kb
Host smart-fb207f23-61a9-44e4-b484-1cbe5a898e01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956253952 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.2956253952
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.2319330098
Short name T789
Test name
Test status
Simulation time 10600191708 ps
CPU time 11.46 seconds
Started Apr 15 03:34:35 PM PDT 24
Finished Apr 15 03:34:47 PM PDT 24
Peak memory 273808 kb
Host smart-2b6203e7-4acc-4ff2-9448-a945272e0263
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319330098 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.2319330098
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.994896558
Short name T10
Test name
Test status
Simulation time 353804374 ps
CPU time 2.26 seconds
Started Apr 15 03:34:34 PM PDT 24
Finished Apr 15 03:34:38 PM PDT 24
Peak memory 203932 kb
Host smart-4df9b7fb-0238-4e8a-9649-7b71bd088590
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994896558 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.i2c_target_hrst.994896558
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1572019080
Short name T886
Test name
Test status
Simulation time 3051639437 ps
CPU time 6.75 seconds
Started Apr 15 03:34:27 PM PDT 24
Finished Apr 15 03:34:34 PM PDT 24
Peak memory 211168 kb
Host smart-a73697bf-35e1-4330-b22e-2bea9ac04f40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572019080 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1572019080
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.1115080092
Short name T814
Test name
Test status
Simulation time 4715354423 ps
CPU time 3.28 seconds
Started Apr 15 03:34:35 PM PDT 24
Finished Apr 15 03:34:39 PM PDT 24
Peak memory 204052 kb
Host smart-98c999ba-2774-470e-b270-a3c9bdbad61e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115080092 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.1115080092
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.735048834
Short name T110
Test name
Test status
Simulation time 3786036541 ps
CPU time 12.23 seconds
Started Apr 15 03:34:29 PM PDT 24
Finished Apr 15 03:34:42 PM PDT 24
Peak memory 204064 kb
Host smart-6dc8005a-273d-47b7-8318-39f643d49c24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735048834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_tar
get_smoke.735048834
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.2008320956
Short name T191
Test name
Test status
Simulation time 1113686903 ps
CPU time 20.22 seconds
Started Apr 15 03:34:28 PM PDT 24
Finished Apr 15 03:34:49 PM PDT 24
Peak memory 212760 kb
Host smart-7428a1dd-cdf9-4bec-92da-93f054448df6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008320956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.2008320956
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.1514183867
Short name T1200
Test name
Test status
Simulation time 7575144509 ps
CPU time 15.46 seconds
Started Apr 15 03:34:26 PM PDT 24
Finished Apr 15 03:34:42 PM PDT 24
Peak memory 204012 kb
Host smart-0fb70b06-bfad-412e-862b-0ef3cf6bade6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514183867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.1514183867
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.2181108344
Short name T126
Test name
Test status
Simulation time 19707265030 ps
CPU time 3437.84 seconds
Started Apr 15 03:34:27 PM PDT 24
Finished Apr 15 04:31:46 PM PDT 24
Peak memory 4531924 kb
Host smart-936a8a6b-b224-4591-a892-780365d2218c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181108344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.2181108344
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.2342193079
Short name T1266
Test name
Test status
Simulation time 1146827766 ps
CPU time 5.82 seconds
Started Apr 15 03:34:27 PM PDT 24
Finished Apr 15 03:34:34 PM PDT 24
Peak memory 217348 kb
Host smart-d15b5de1-1069-4003-9a4a-ed3505052fc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342193079 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.2342193079
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.1634160881
Short name T915
Test name
Test status
Simulation time 26687792 ps
CPU time 0.61 seconds
Started Apr 15 03:34:44 PM PDT 24
Finished Apr 15 03:34:45 PM PDT 24
Peak memory 203568 kb
Host smart-d9d7ab15-8711-478c-8158-d3f7b900b8be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634160881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1634160881
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.2296366132
Short name T1023
Test name
Test status
Simulation time 326578024 ps
CPU time 1.17 seconds
Started Apr 15 03:34:35 PM PDT 24
Finished Apr 15 03:34:37 PM PDT 24
Peak memory 212256 kb
Host smart-0518d42b-dc02-45a6-882c-2e817b36437a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296366132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.2296366132
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.3567080874
Short name T216
Test name
Test status
Simulation time 654281430 ps
CPU time 7.76 seconds
Started Apr 15 03:34:31 PM PDT 24
Finished Apr 15 03:34:40 PM PDT 24
Peak memory 274364 kb
Host smart-e170f816-0775-4670-b58b-2f9b0e5a4545
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567080874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.3567080874
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.3232222207
Short name T681
Test name
Test status
Simulation time 4968168149 ps
CPU time 76.42 seconds
Started Apr 15 03:34:32 PM PDT 24
Finished Apr 15 03:35:49 PM PDT 24
Peak memory 811876 kb
Host smart-0352a93c-7b83-4e32-9feb-d9d79f165fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232222207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.3232222207
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.939043333
Short name T422
Test name
Test status
Simulation time 1520506236 ps
CPU time 102.92 seconds
Started Apr 15 03:34:33 PM PDT 24
Finished Apr 15 03:36:16 PM PDT 24
Peak memory 565952 kb
Host smart-06f5da87-3920-4574-8b89-42ab92d989a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939043333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.939043333
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.1708708418
Short name T986
Test name
Test status
Simulation time 299316770 ps
CPU time 1.14 seconds
Started Apr 15 03:34:34 PM PDT 24
Finished Apr 15 03:34:36 PM PDT 24
Peak memory 203856 kb
Host smart-1de40d58-291a-4874-bb84-fc2a092c8541
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708708418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.1708708418
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2763403178
Short name T1082
Test name
Test status
Simulation time 464531709 ps
CPU time 2.84 seconds
Started Apr 15 03:34:32 PM PDT 24
Finished Apr 15 03:34:36 PM PDT 24
Peak memory 203980 kb
Host smart-ec003b89-34d8-467f-9b3d-0eafe9510694
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763403178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.2763403178
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.201989137
Short name T184
Test name
Test status
Simulation time 17286150992 ps
CPU time 64.55 seconds
Started Apr 15 03:34:30 PM PDT 24
Finished Apr 15 03:35:36 PM PDT 24
Peak memory 891144 kb
Host smart-113f3bdf-c5d7-4995-a3b8-3b7e47eeb4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201989137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.201989137
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.449043953
Short name T943
Test name
Test status
Simulation time 1590027425 ps
CPU time 4.79 seconds
Started Apr 15 03:34:44 PM PDT 24
Finished Apr 15 03:34:50 PM PDT 24
Peak memory 203948 kb
Host smart-713c151f-51df-44e5-baea-55653494f66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449043953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.449043953
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.3349387840
Short name T999
Test name
Test status
Simulation time 892922528 ps
CPU time 15.26 seconds
Started Apr 15 03:34:38 PM PDT 24
Finished Apr 15 03:34:54 PM PDT 24
Peak memory 306420 kb
Host smart-17a72728-20b9-4b7b-a862-640e1b4fd237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349387840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.3349387840
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.733741438
Short name T1216
Test name
Test status
Simulation time 19594775 ps
CPU time 0.65 seconds
Started Apr 15 03:34:30 PM PDT 24
Finished Apr 15 03:34:31 PM PDT 24
Peak memory 203664 kb
Host smart-881d0e03-8bdf-415a-aef8-6d6cbb1022b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733741438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.733741438
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.1354715359
Short name T1323
Test name
Test status
Simulation time 6440391256 ps
CPU time 172.95 seconds
Started Apr 15 03:34:54 PM PDT 24
Finished Apr 15 03:37:48 PM PDT 24
Peak memory 228396 kb
Host smart-f87bb887-65dc-4027-9309-b2a998f3dc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354715359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.1354715359
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.1204573873
Short name T698
Test name
Test status
Simulation time 5444873213 ps
CPU time 27.21 seconds
Started Apr 15 03:34:33 PM PDT 24
Finished Apr 15 03:35:02 PM PDT 24
Peak memory 352196 kb
Host smart-64d9b90f-3902-4ad6-bd47-a69b767c9dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204573873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.1204573873
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.3640030180
Short name T1329
Test name
Test status
Simulation time 20904830641 ps
CPU time 385.35 seconds
Started Apr 15 03:34:37 PM PDT 24
Finished Apr 15 03:41:03 PM PDT 24
Peak memory 2122008 kb
Host smart-b684bc88-db45-457f-9d8d-ddf278f95fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640030180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.3640030180
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.2054572155
Short name T662
Test name
Test status
Simulation time 9684750833 ps
CPU time 12.28 seconds
Started Apr 15 03:34:30 PM PDT 24
Finished Apr 15 03:34:43 PM PDT 24
Peak memory 220268 kb
Host smart-2a0ce1df-9f32-48b8-9dbe-e4181cd0054d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054572155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2054572155
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.1882248271
Short name T335
Test name
Test status
Simulation time 5254347858 ps
CPU time 3.52 seconds
Started Apr 15 03:34:37 PM PDT 24
Finished Apr 15 03:34:42 PM PDT 24
Peak memory 204036 kb
Host smart-1b644967-1bb4-43b5-b4dc-89dc52550583
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882248271 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.1882248271
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.1119394427
Short name T307
Test name
Test status
Simulation time 10269565093 ps
CPU time 31.21 seconds
Started Apr 15 03:34:34 PM PDT 24
Finished Apr 15 03:35:06 PM PDT 24
Peak memory 369788 kb
Host smart-f65d8545-538e-496b-b46e-f7d26d3aa58e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119394427 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.1119394427
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.905395016
Short name T313
Test name
Test status
Simulation time 10620551768 ps
CPU time 11.56 seconds
Started Apr 15 03:34:36 PM PDT 24
Finished Apr 15 03:34:48 PM PDT 24
Peak memory 283508 kb
Host smart-c00bf9f2-58e4-4425-a11e-039b5ba82709
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905395016 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_tx.905395016
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.1742949070
Short name T25
Test name
Test status
Simulation time 1505282997 ps
CPU time 2.28 seconds
Started Apr 15 03:34:39 PM PDT 24
Finished Apr 15 03:34:42 PM PDT 24
Peak memory 203960 kb
Host smart-4ba8421a-cb38-4ebb-9406-b4dfcc9f4391
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742949070 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.1742949070
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.356308139
Short name T988
Test name
Test status
Simulation time 1168170797 ps
CPU time 5.45 seconds
Started Apr 15 03:34:51 PM PDT 24
Finished Apr 15 03:34:57 PM PDT 24
Peak memory 212180 kb
Host smart-45e8fa1e-eff1-4824-86b9-e2e36942134a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356308139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.356308139
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.1421792722
Short name T1140
Test name
Test status
Simulation time 18977382985 ps
CPU time 61.73 seconds
Started Apr 15 03:34:35 PM PDT 24
Finished Apr 15 03:35:37 PM PDT 24
Peak memory 973780 kb
Host smart-b64323e1-3130-4491-81d5-3798f1cc39c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421792722 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.1421792722
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.873124039
Short name T529
Test name
Test status
Simulation time 2407806176 ps
CPU time 9.03 seconds
Started Apr 15 03:34:37 PM PDT 24
Finished Apr 15 03:34:46 PM PDT 24
Peak memory 204036 kb
Host smart-c1586786-a442-473e-9a3d-e16f480fb710
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873124039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_tar
get_smoke.873124039
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.546911814
Short name T30
Test name
Test status
Simulation time 413790504 ps
CPU time 16.83 seconds
Started Apr 15 03:34:35 PM PDT 24
Finished Apr 15 03:34:52 PM PDT 24
Peak memory 204040 kb
Host smart-4a39cad4-f767-4cb7-91ed-8d2ad819dfe0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546911814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_rd.546911814
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.457959450
Short name T1284
Test name
Test status
Simulation time 11044279785 ps
CPU time 11.09 seconds
Started Apr 15 03:34:34 PM PDT 24
Finished Apr 15 03:34:47 PM PDT 24
Peak memory 204036 kb
Host smart-67863182-9182-4e8c-9116-f57ef5a10f40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457959450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_wr.457959450
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.3314817070
Short name T1060
Test name
Test status
Simulation time 21337895534 ps
CPU time 1164.6 seconds
Started Apr 15 03:34:35 PM PDT 24
Finished Apr 15 03:54:01 PM PDT 24
Peak memory 4270040 kb
Host smart-9599c1ed-ddf0-4524-b215-632ef4ffff13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314817070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.3314817070
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2127212635
Short name T437
Test name
Test status
Simulation time 2893577167 ps
CPU time 6.8 seconds
Started Apr 15 03:34:36 PM PDT 24
Finished Apr 15 03:34:44 PM PDT 24
Peak memory 212256 kb
Host smart-59db735a-7ca8-452b-911f-83f7f0f64b63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127212635 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2127212635
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.2082141852
Short name T1096
Test name
Test status
Simulation time 46627070 ps
CPU time 0.6 seconds
Started Apr 15 03:34:46 PM PDT 24
Finished Apr 15 03:34:47 PM PDT 24
Peak memory 203592 kb
Host smart-66bcfa99-9aca-4f97-8bd0-f24779e2792c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082141852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.2082141852
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.1738046485
Short name T1233
Test name
Test status
Simulation time 766930227 ps
CPU time 1.33 seconds
Started Apr 15 03:34:44 PM PDT 24
Finished Apr 15 03:34:46 PM PDT 24
Peak memory 212296 kb
Host smart-e0331421-baf9-4284-9d7f-11f20f52d0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738046485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.1738046485
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.2932467100
Short name T1111
Test name
Test status
Simulation time 2216484279 ps
CPU time 4.01 seconds
Started Apr 15 03:34:37 PM PDT 24
Finished Apr 15 03:34:42 PM PDT 24
Peak memory 247908 kb
Host smart-cf8dc3b2-8e60-4f1a-923f-2f6043669bf4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932467100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.2932467100
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1869660436
Short name T1118
Test name
Test status
Simulation time 2927596025 ps
CPU time 41.17 seconds
Started Apr 15 03:34:38 PM PDT 24
Finished Apr 15 03:35:20 PM PDT 24
Peak memory 561844 kb
Host smart-f11b952b-c70f-4c4a-a638-e5f6572353a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869660436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1869660436
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.3635709632
Short name T531
Test name
Test status
Simulation time 5240074213 ps
CPU time 33.42 seconds
Started Apr 15 03:34:38 PM PDT 24
Finished Apr 15 03:35:12 PM PDT 24
Peak memory 515284 kb
Host smart-2170dfed-1976-4742-aacb-95188f6daf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635709632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.3635709632
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1137880155
Short name T978
Test name
Test status
Simulation time 104409127 ps
CPU time 0.93 seconds
Started Apr 15 03:34:38 PM PDT 24
Finished Apr 15 03:34:39 PM PDT 24
Peak memory 203740 kb
Host smart-e75a949d-3057-454a-b77c-3be98b608b5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137880155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.1137880155
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.3790916018
Short name T1285
Test name
Test status
Simulation time 334198082 ps
CPU time 4.87 seconds
Started Apr 15 03:34:41 PM PDT 24
Finished Apr 15 03:34:47 PM PDT 24
Peak memory 232564 kb
Host smart-c5bd6b2d-2e1f-4bda-a3b3-bef81ef240f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790916018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.3790916018
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.2540219613
Short name T442
Test name
Test status
Simulation time 16379704790 ps
CPU time 272.57 seconds
Started Apr 15 03:34:37 PM PDT 24
Finished Apr 15 03:39:11 PM PDT 24
Peak memory 1100772 kb
Host smart-031cdc5e-8d66-40c0-b9c4-ae2cf61a4a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540219613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.2540219613
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.2291956061
Short name T1065
Test name
Test status
Simulation time 442560187 ps
CPU time 6.38 seconds
Started Apr 15 03:34:46 PM PDT 24
Finished Apr 15 03:34:53 PM PDT 24
Peak memory 203968 kb
Host smart-19641099-217f-422f-9364-5a7023fad37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291956061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.2291956061
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.1377349452
Short name T1261
Test name
Test status
Simulation time 5018123111 ps
CPU time 31.96 seconds
Started Apr 15 03:34:46 PM PDT 24
Finished Apr 15 03:35:19 PM PDT 24
Peak memory 409884 kb
Host smart-88fc1807-83a0-485c-b6c1-a81a25e28886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377349452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.1377349452
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.595976883
Short name T215
Test name
Test status
Simulation time 86949639 ps
CPU time 0.71 seconds
Started Apr 15 03:34:37 PM PDT 24
Finished Apr 15 03:34:39 PM PDT 24
Peak memory 203696 kb
Host smart-dda5b12a-4709-43f2-9eba-94602e6fcb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595976883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.595976883
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.2277901545
Short name T714
Test name
Test status
Simulation time 4767087478 ps
CPU time 55.24 seconds
Started Apr 15 03:34:39 PM PDT 24
Finished Apr 15 03:35:35 PM PDT 24
Peak memory 225140 kb
Host smart-1dc97756-a91f-4b73-be43-7830015a7585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277901545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2277901545
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.1380809574
Short name T436
Test name
Test status
Simulation time 1895784994 ps
CPU time 34.32 seconds
Started Apr 15 03:34:45 PM PDT 24
Finished Apr 15 03:35:20 PM PDT 24
Peak memory 372048 kb
Host smart-13a603b3-5e37-4f6e-b747-a16b024c3a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380809574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.1380809574
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.3305200779
Short name T373
Test name
Test status
Simulation time 18449567979 ps
CPU time 1920.96 seconds
Started Apr 15 03:34:43 PM PDT 24
Finished Apr 15 04:06:45 PM PDT 24
Peak memory 4127344 kb
Host smart-1f04d331-7fb5-4764-a94b-189f60cbf85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305200779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3305200779
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.1830302377
Short name T666
Test name
Test status
Simulation time 499251467 ps
CPU time 18.87 seconds
Started Apr 15 03:34:44 PM PDT 24
Finished Apr 15 03:35:04 PM PDT 24
Peak memory 212208 kb
Host smart-a88cef2d-3baf-4c51-8184-393b61062fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830302377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.1830302377
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.2439167304
Short name T548
Test name
Test status
Simulation time 564545669 ps
CPU time 3.01 seconds
Started Apr 15 03:34:49 PM PDT 24
Finished Apr 15 03:34:53 PM PDT 24
Peak memory 203984 kb
Host smart-5c6d2af9-9808-4903-9138-78cd44810e1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439167304 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.2439167304
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.1000511863
Short name T1230
Test name
Test status
Simulation time 10079615101 ps
CPU time 13.04 seconds
Started Apr 15 03:34:46 PM PDT 24
Finished Apr 15 03:35:00 PM PDT 24
Peak memory 280956 kb
Host smart-a49ec720-c9c1-41a3-81fe-eee8d590134e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000511863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.1000511863
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.283951457
Short name T201
Test name
Test status
Simulation time 10208416569 ps
CPU time 10.69 seconds
Started Apr 15 03:34:46 PM PDT 24
Finished Apr 15 03:34:58 PM PDT 24
Peak memory 274756 kb
Host smart-2828e1b3-33c0-421b-9426-da5859ee0cc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283951457 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_fifo_reset_tx.283951457
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.1142735312
Short name T826
Test name
Test status
Simulation time 279008549 ps
CPU time 1.72 seconds
Started Apr 15 03:34:45 PM PDT 24
Finished Apr 15 03:34:47 PM PDT 24
Peak memory 204028 kb
Host smart-97a1a322-30c5-4593-9420-76a78c9dc8a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142735312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.1142735312
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.1433272156
Short name T319
Test name
Test status
Simulation time 1339465737 ps
CPU time 6.84 seconds
Started Apr 15 03:34:42 PM PDT 24
Finished Apr 15 03:34:50 PM PDT 24
Peak memory 219020 kb
Host smart-92d9e51d-6a4e-4fed-ac92-f5f12ad23de2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433272156 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.1433272156
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.4122218775
Short name T499
Test name
Test status
Simulation time 19976348153 ps
CPU time 321.92 seconds
Started Apr 15 03:34:42 PM PDT 24
Finished Apr 15 03:40:05 PM PDT 24
Peak memory 3240088 kb
Host smart-079f6865-c558-4b6b-9920-da899a5b6d6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122218775 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.4122218775
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.1920521139
Short name T1033
Test name
Test status
Simulation time 2048644412 ps
CPU time 7.27 seconds
Started Apr 15 03:34:44 PM PDT 24
Finished Apr 15 03:34:52 PM PDT 24
Peak memory 204020 kb
Host smart-c0099464-444c-4469-a294-9d3523b35ffc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920521139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.1920521139
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.1449567548
Short name T721
Test name
Test status
Simulation time 2026436661 ps
CPU time 18.83 seconds
Started Apr 15 03:34:44 PM PDT 24
Finished Apr 15 03:35:03 PM PDT 24
Peak memory 204032 kb
Host smart-ca245161-f7e8-46e1-bd3f-22bf37db94c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449567548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.1449567548
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.436445685
Short name T600
Test name
Test status
Simulation time 13327298830 ps
CPU time 13.48 seconds
Started Apr 15 03:34:45 PM PDT 24
Finished Apr 15 03:34:59 PM PDT 24
Peak memory 204000 kb
Host smart-4e0cd476-f559-4824-bb97-750addc90109
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436445685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_wr.436445685
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.3306979248
Short name T920
Test name
Test status
Simulation time 27123326345 ps
CPU time 1411.22 seconds
Started Apr 15 03:34:45 PM PDT 24
Finished Apr 15 03:58:17 PM PDT 24
Peak memory 5944328 kb
Host smart-93f73a13-5b42-4453-8ddf-121aa094250f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306979248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.3306979248
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1361594799
Short name T967
Test name
Test status
Simulation time 7613182661 ps
CPU time 6.91 seconds
Started Apr 15 03:34:43 PM PDT 24
Finished Apr 15 03:34:50 PM PDT 24
Peak memory 215404 kb
Host smart-4fe5750a-9d64-4c42-b3f7-bee626c29208
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361594799 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1361594799
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.3579056687
Short name T1080
Test name
Test status
Simulation time 17846911 ps
CPU time 0.61 seconds
Started Apr 15 03:34:54 PM PDT 24
Finished Apr 15 03:34:55 PM PDT 24
Peak memory 203584 kb
Host smart-de23f6db-fa53-4d59-aabd-03ecf68438d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579056687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.3579056687
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.1810325671
Short name T1281
Test name
Test status
Simulation time 186318318 ps
CPU time 1.62 seconds
Started Apr 15 03:34:49 PM PDT 24
Finished Apr 15 03:34:52 PM PDT 24
Peak memory 212248 kb
Host smart-e7fd9c46-2d46-4992-9934-ebfaf9a50dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810325671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.1810325671
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.551196501
Short name T1210
Test name
Test status
Simulation time 284981645 ps
CPU time 4.63 seconds
Started Apr 15 03:34:50 PM PDT 24
Finished Apr 15 03:34:56 PM PDT 24
Peak memory 247008 kb
Host smart-da7e9095-f288-4e78-9f24-2fb4864b81f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551196501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empt
y.551196501
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.4224416823
Short name T55
Test name
Test status
Simulation time 1734483879 ps
CPU time 120.7 seconds
Started Apr 15 03:34:47 PM PDT 24
Finished Apr 15 03:36:49 PM PDT 24
Peak memory 634276 kb
Host smart-e9de2001-700e-4e74-9789-2e5b11ecded1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224416823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.4224416823
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.2054814803
Short name T542
Test name
Test status
Simulation time 8242406106 ps
CPU time 76 seconds
Started Apr 15 03:34:54 PM PDT 24
Finished Apr 15 03:36:11 PM PDT 24
Peak memory 706500 kb
Host smart-5a35b74c-4984-44aa-a41f-81379590f8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054814803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.2054814803
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.815861709
Short name T945
Test name
Test status
Simulation time 418998763 ps
CPU time 1.12 seconds
Started Apr 15 03:34:50 PM PDT 24
Finished Apr 15 03:34:52 PM PDT 24
Peak memory 203896 kb
Host smart-e38c88a4-454d-4b5f-9d7f-e883114731f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815861709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fm
t.815861709
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.995010643
Short name T479
Test name
Test status
Simulation time 807561255 ps
CPU time 4.14 seconds
Started Apr 15 03:34:49 PM PDT 24
Finished Apr 15 03:34:53 PM PDT 24
Peak memory 203948 kb
Host smart-8394fc22-980b-4c7c-8b11-ba6cf9a7cd48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995010643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.
995010643
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.924261847
Short name T1158
Test name
Test status
Simulation time 7155672545 ps
CPU time 82.86 seconds
Started Apr 15 03:34:48 PM PDT 24
Finished Apr 15 03:36:12 PM PDT 24
Peak memory 971964 kb
Host smart-62801d8b-17ae-4f81-8480-03b35696f7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924261847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.924261847
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.3881588747
Short name T276
Test name
Test status
Simulation time 2732449076 ps
CPU time 4.35 seconds
Started Apr 15 03:34:54 PM PDT 24
Finished Apr 15 03:34:59 PM PDT 24
Peak memory 203988 kb
Host smart-5dd6b024-3d16-4b2c-b0de-2658696750f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881588747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.3881588747
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_override.4207274028
Short name T845
Test name
Test status
Simulation time 36980145 ps
CPU time 0.64 seconds
Started Apr 15 03:34:47 PM PDT 24
Finished Apr 15 03:34:49 PM PDT 24
Peak memory 203688 kb
Host smart-462a7701-4391-42b6-b977-c62c5150562c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207274028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.4207274028
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.3731477481
Short name T443
Test name
Test status
Simulation time 26401370927 ps
CPU time 195.28 seconds
Started Apr 15 03:34:50 PM PDT 24
Finished Apr 15 03:38:06 PM PDT 24
Peak memory 204016 kb
Host smart-79f38792-afec-4402-8714-66e8e51d2bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731477481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.3731477481
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.466617090
Short name T812
Test name
Test status
Simulation time 1622289696 ps
CPU time 27.21 seconds
Started Apr 15 03:34:47 PM PDT 24
Finished Apr 15 03:35:15 PM PDT 24
Peak memory 316232 kb
Host smart-d250f48e-c57b-4007-9201-3c134141a645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466617090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.466617090
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.2180778653
Short name T254
Test name
Test status
Simulation time 20390360825 ps
CPU time 2195.57 seconds
Started Apr 15 03:34:49 PM PDT 24
Finished Apr 15 04:11:26 PM PDT 24
Peak memory 3530440 kb
Host smart-d7ff24bc-05b1-42fc-a565-9b274c788279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180778653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.2180778653
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.2311077095
Short name T916
Test name
Test status
Simulation time 692808174 ps
CPU time 13.65 seconds
Started Apr 15 03:34:51 PM PDT 24
Finished Apr 15 03:35:05 PM PDT 24
Peak memory 220144 kb
Host smart-85c9ce08-f12e-4438-b876-d96110725baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311077095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.2311077095
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.3280882656
Short name T1085
Test name
Test status
Simulation time 6627001654 ps
CPU time 3.58 seconds
Started Apr 15 03:34:52 PM PDT 24
Finished Apr 15 03:34:56 PM PDT 24
Peak memory 212200 kb
Host smart-57baa4f9-fe65-4c8d-91f7-4c6fb896628a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280882656 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.3280882656
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.2961199645
Short name T573
Test name
Test status
Simulation time 10459777705 ps
CPU time 13.7 seconds
Started Apr 15 03:34:50 PM PDT 24
Finished Apr 15 03:35:04 PM PDT 24
Peak memory 264600 kb
Host smart-d9c54622-bca0-409f-9653-fed51aeecd3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961199645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.2961199645
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.274716082
Short name T941
Test name
Test status
Simulation time 1271087424 ps
CPU time 2.25 seconds
Started Apr 15 03:34:54 PM PDT 24
Finished Apr 15 03:34:57 PM PDT 24
Peak memory 204012 kb
Host smart-bbfec50a-b1f8-42a1-b195-dc67d91c7ff7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274716082 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.i2c_target_hrst.274716082
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.1892328117
Short name T616
Test name
Test status
Simulation time 1104681811 ps
CPU time 5.45 seconds
Started Apr 15 03:34:52 PM PDT 24
Finished Apr 15 03:34:59 PM PDT 24
Peak memory 213700 kb
Host smart-595b723c-e048-4b9d-8570-5d3ef6f3362a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892328117 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.1892328117
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.397261438
Short name T897
Test name
Test status
Simulation time 19476601704 ps
CPU time 125.15 seconds
Started Apr 15 03:34:49 PM PDT 24
Finished Apr 15 03:36:55 PM PDT 24
Peak memory 1581936 kb
Host smart-0273ca27-b180-48bb-948d-b844f6ab7f2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397261438 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.397261438
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.570823695
Short name T522
Test name
Test status
Simulation time 570485914 ps
CPU time 19.75 seconds
Started Apr 15 03:34:53 PM PDT 24
Finished Apr 15 03:35:13 PM PDT 24
Peak memory 203980 kb
Host smart-65acdc1b-6ea5-470f-9405-bbeffd62c15f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570823695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_tar
get_smoke.570823695
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.718726245
Short name T961
Test name
Test status
Simulation time 2740537662 ps
CPU time 10.78 seconds
Started Apr 15 03:34:53 PM PDT 24
Finished Apr 15 03:35:04 PM PDT 24
Peak memory 210668 kb
Host smart-fb6c99f4-2778-482e-b029-b122e2f1d1e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718726245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_rd.718726245
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.2712129359
Short name T432
Test name
Test status
Simulation time 1613337249 ps
CPU time 7.4 seconds
Started Apr 15 03:34:52 PM PDT 24
Finished Apr 15 03:35:00 PM PDT 24
Peak memory 211116 kb
Host smart-b3b0d6f6-7354-4139-a7b5-5080ebdaffa0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712129359 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.2712129359
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.2447632703
Short name T740
Test name
Test status
Simulation time 22728604 ps
CPU time 0.63 seconds
Started Apr 15 03:35:08 PM PDT 24
Finished Apr 15 03:35:09 PM PDT 24
Peak memory 203584 kb
Host smart-566d6afd-639a-4bc6-8be4-f4b972ee7855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447632703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.2447632703
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.927230682
Short name T829
Test name
Test status
Simulation time 214598712 ps
CPU time 1.54 seconds
Started Apr 15 03:34:59 PM PDT 24
Finished Apr 15 03:35:02 PM PDT 24
Peak memory 220400 kb
Host smart-6ced3f8c-d35b-4263-8c16-a8cf0bfe856a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927230682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.927230682
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.3518230774
Short name T1039
Test name
Test status
Simulation time 279739400 ps
CPU time 5.26 seconds
Started Apr 15 03:34:53 PM PDT 24
Finished Apr 15 03:34:59 PM PDT 24
Peak memory 255384 kb
Host smart-821c1b36-c73d-4a8d-b10f-ef08dd663a55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518230774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.3518230774
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.2970340841
Short name T255
Test name
Test status
Simulation time 9198387106 ps
CPU time 78.36 seconds
Started Apr 15 03:34:54 PM PDT 24
Finished Apr 15 03:36:13 PM PDT 24
Peak memory 708784 kb
Host smart-8311e3e7-b2bf-42d4-9b8f-e062eaf8602f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970340841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2970340841
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.988002310
Short name T1226
Test name
Test status
Simulation time 7348910725 ps
CPU time 61.52 seconds
Started Apr 15 03:34:53 PM PDT 24
Finished Apr 15 03:35:55 PM PDT 24
Peak memory 630712 kb
Host smart-c1034c7c-30ec-4488-86b6-71e71dd9dce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988002310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.988002310
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.187151033
Short name T696
Test name
Test status
Simulation time 426962298 ps
CPU time 1.13 seconds
Started Apr 15 03:34:53 PM PDT 24
Finished Apr 15 03:34:55 PM PDT 24
Peak memory 203956 kb
Host smart-16dd3887-ff50-4944-afb1-e377f0c2aca0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187151033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fm
t.187151033
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.3626120104
Short name T837
Test name
Test status
Simulation time 232064253 ps
CPU time 5.47 seconds
Started Apr 15 03:34:52 PM PDT 24
Finished Apr 15 03:34:58 PM PDT 24
Peak memory 203984 kb
Host smart-a451f473-bae9-4824-b389-d4a5f10dae8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626120104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.3626120104
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.565669424
Short name T338
Test name
Test status
Simulation time 15456796171 ps
CPU time 235.47 seconds
Started Apr 15 03:34:55 PM PDT 24
Finished Apr 15 03:38:51 PM PDT 24
Peak memory 944832 kb
Host smart-af42b748-d00c-49aa-ae85-0c40e6643c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565669424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.565669424
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.669250863
Short name T572
Test name
Test status
Simulation time 1331762425 ps
CPU time 5.56 seconds
Started Apr 15 03:35:02 PM PDT 24
Finished Apr 15 03:35:08 PM PDT 24
Peak memory 203944 kb
Host smart-4e213777-e400-42c4-a2fc-12dc2adf96d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669250863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.669250863
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.692519365
Short name T781
Test name
Test status
Simulation time 1082813949 ps
CPU time 19.62 seconds
Started Apr 15 03:35:00 PM PDT 24
Finished Apr 15 03:35:20 PM PDT 24
Peak memory 277148 kb
Host smart-a23fccc6-160a-4266-89f1-34b7cdc5b2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692519365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.692519365
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.1108548361
Short name T207
Test name
Test status
Simulation time 52978824 ps
CPU time 0.64 seconds
Started Apr 15 03:34:54 PM PDT 24
Finished Apr 15 03:34:55 PM PDT 24
Peak memory 203692 kb
Host smart-e7c8b87e-4cdd-4501-afa6-a8eb7f9447ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108548361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1108548361
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.2996065101
Short name T331
Test name
Test status
Simulation time 5672290378 ps
CPU time 23.71 seconds
Started Apr 15 03:34:57 PM PDT 24
Finished Apr 15 03:35:21 PM PDT 24
Peak memory 440872 kb
Host smart-39c4c7ed-4c27-40a6-ba89-0cd5ac288f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996065101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.2996065101
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.4153561466
Short name T684
Test name
Test status
Simulation time 1490886153 ps
CPU time 73.27 seconds
Started Apr 15 03:34:53 PM PDT 24
Finished Apr 15 03:36:07 PM PDT 24
Peak memory 334080 kb
Host smart-c60703d4-1e67-4d4b-9954-3e62d80a5304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153561466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.4153561466
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.4119492878
Short name T59
Test name
Test status
Simulation time 76467282979 ps
CPU time 895.17 seconds
Started Apr 15 03:34:56 PM PDT 24
Finished Apr 15 03:49:52 PM PDT 24
Peak memory 3378668 kb
Host smart-eea70e97-e0b2-4c29-8276-a06d30574ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119492878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.4119492878
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.2670462322
Short name T994
Test name
Test status
Simulation time 785635826 ps
CPU time 15.19 seconds
Started Apr 15 03:34:57 PM PDT 24
Finished Apr 15 03:35:13 PM PDT 24
Peak memory 220268 kb
Host smart-4d8c6ba2-cab3-4db3-8801-df53d03134f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670462322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.2670462322
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.1997827108
Short name T725
Test name
Test status
Simulation time 10122991987 ps
CPU time 61.11 seconds
Started Apr 15 03:34:56 PM PDT 24
Finished Apr 15 03:35:58 PM PDT 24
Peak memory 487092 kb
Host smart-839b0bcf-3e0e-41aa-be80-a4e2f7cefc9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997827108 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.1997827108
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.326998613
Short name T330
Test name
Test status
Simulation time 10286856337 ps
CPU time 30.43 seconds
Started Apr 15 03:34:59 PM PDT 24
Finished Apr 15 03:35:30 PM PDT 24
Peak memory 376032 kb
Host smart-1729186e-55cc-4e7c-ab14-63f6e1cd115b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326998613 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_fifo_reset_tx.326998613
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.4372452
Short name T438
Test name
Test status
Simulation time 241730871 ps
CPU time 1.87 seconds
Started Apr 15 03:35:04 PM PDT 24
Finished Apr 15 03:35:06 PM PDT 24
Peak memory 204028 kb
Host smart-df70978f-12da-4b60-8906-052983370a97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4372452 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.i2c_target_hrst.4372452
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.3385447822
Short name T250
Test name
Test status
Simulation time 4368475855 ps
CPU time 5.3 seconds
Started Apr 15 03:34:58 PM PDT 24
Finished Apr 15 03:35:04 PM PDT 24
Peak memory 215060 kb
Host smart-a998d9fd-9c0b-4f71-ab87-f99b38c78a64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385447822 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.3385447822
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.657999381
Short name T1248
Test name
Test status
Simulation time 14346170825 ps
CPU time 21.78 seconds
Started Apr 15 03:35:03 PM PDT 24
Finished Apr 15 03:35:25 PM PDT 24
Peak memory 504760 kb
Host smart-7dd76988-ad71-40c4-abb9-529e638083e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657999381 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.657999381
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.3389582755
Short name T639
Test name
Test status
Simulation time 1525011285 ps
CPU time 29.25 seconds
Started Apr 15 03:34:58 PM PDT 24
Finished Apr 15 03:35:28 PM PDT 24
Peak memory 203916 kb
Host smart-8891fdf4-1428-4f03-a779-01523ce97370
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389582755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.3389582755
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.3254546733
Short name T1018
Test name
Test status
Simulation time 1824169825 ps
CPU time 17.55 seconds
Started Apr 15 03:34:56 PM PDT 24
Finished Apr 15 03:35:14 PM PDT 24
Peak memory 214248 kb
Host smart-cd012b26-d15f-4ef1-abc5-4a744b5295cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254546733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.3254546733
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.2670645006
Short name T367
Test name
Test status
Simulation time 59782147949 ps
CPU time 51.35 seconds
Started Apr 15 03:34:58 PM PDT 24
Finished Apr 15 03:35:50 PM PDT 24
Peak memory 811268 kb
Host smart-4768d75c-61aa-4b9f-9dae-7eead6122f33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670645006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.2670645006
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.1562721181
Short name T1331
Test name
Test status
Simulation time 35255038719 ps
CPU time 3438.14 seconds
Started Apr 15 03:34:58 PM PDT 24
Finished Apr 15 04:32:17 PM PDT 24
Peak memory 8568588 kb
Host smart-9bf22a9f-2339-4944-a043-428e81886748
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562721181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.1562721181
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.320004248
Short name T410
Test name
Test status
Simulation time 4678770065 ps
CPU time 6.32 seconds
Started Apr 15 03:34:56 PM PDT 24
Finished Apr 15 03:35:03 PM PDT 24
Peak memory 218060 kb
Host smart-ed26b409-3847-4bd6-a126-104a3b45e50f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320004248 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_timeout.320004248
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.572910622
Short name T60
Test name
Test status
Simulation time 146678133 ps
CPU time 0.6 seconds
Started Apr 15 03:28:58 PM PDT 24
Finished Apr 15 03:29:00 PM PDT 24
Peak memory 203480 kb
Host smart-a50f457d-968b-413e-aba1-5a05584d0aac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572910622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.572910622
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.2596493443
Short name T1228
Test name
Test status
Simulation time 129901395 ps
CPU time 1.27 seconds
Started Apr 15 03:28:59 PM PDT 24
Finished Apr 15 03:29:02 PM PDT 24
Peak memory 212304 kb
Host smart-2ba68421-088d-4182-b2d9-7ef335059d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596493443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2596493443
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.2006213829
Short name T72
Test name
Test status
Simulation time 235836522 ps
CPU time 11.28 seconds
Started Apr 15 03:28:57 PM PDT 24
Finished Apr 15 03:29:09 PM PDT 24
Peak memory 236164 kb
Host smart-bf109a6e-9c5d-40cd-9d49-53ae22eeea57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006213829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.2006213829
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.3807207060
Short name T45
Test name
Test status
Simulation time 13354380687 ps
CPU time 94.26 seconds
Started Apr 15 03:28:56 PM PDT 24
Finished Apr 15 03:30:31 PM PDT 24
Peak memory 847784 kb
Host smart-c7520e7f-8b99-48ca-ad3b-73693a816924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807207060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.3807207060
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.59916327
Short name T1227
Test name
Test status
Simulation time 2997691859 ps
CPU time 106.83 seconds
Started Apr 15 03:28:54 PM PDT 24
Finished Apr 15 03:30:43 PM PDT 24
Peak memory 539844 kb
Host smart-472e5ac3-d897-485c-8c6c-4f083a39cf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59916327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.59916327
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.2059844209
Short name T579
Test name
Test status
Simulation time 80224997 ps
CPU time 0.86 seconds
Started Apr 15 03:28:56 PM PDT 24
Finished Apr 15 03:28:58 PM PDT 24
Peak memory 203720 kb
Host smart-ea586941-13ac-44ea-91b5-baadce5388a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059844209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.2059844209
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3961962534
Short name T525
Test name
Test status
Simulation time 179468551 ps
CPU time 10.26 seconds
Started Apr 15 03:28:54 PM PDT 24
Finished Apr 15 03:29:06 PM PDT 24
Peak memory 238412 kb
Host smart-3086e442-94f1-4d04-9bb9-ce3d8fc3a7e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961962534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
3961962534
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.3185513923
Short name T791
Test name
Test status
Simulation time 12839404555 ps
CPU time 251.48 seconds
Started Apr 15 03:28:54 PM PDT 24
Finished Apr 15 03:33:07 PM PDT 24
Peak memory 1015816 kb
Host smart-95f716be-8cb5-4af3-b6da-3a0b18d6853b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185513923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3185513923
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.108412162
Short name T1305
Test name
Test status
Simulation time 335754943 ps
CPU time 4.41 seconds
Started Apr 15 03:29:14 PM PDT 24
Finished Apr 15 03:29:19 PM PDT 24
Peak memory 203868 kb
Host smart-a43209ee-449c-48a9-ab27-ba88aba259be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108412162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.108412162
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.1602862789
Short name T778
Test name
Test status
Simulation time 917369834 ps
CPU time 42.97 seconds
Started Apr 15 03:28:58 PM PDT 24
Finished Apr 15 03:29:42 PM PDT 24
Peak memory 301532 kb
Host smart-9e642199-f530-4387-ae97-9e835b720465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602862789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.1602862789
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.2300486771
Short name T1196
Test name
Test status
Simulation time 32284897 ps
CPU time 0.67 seconds
Started Apr 15 03:28:55 PM PDT 24
Finished Apr 15 03:28:57 PM PDT 24
Peak memory 203676 kb
Host smart-0bb726e2-8c0c-4807-81ec-afe1a6967fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300486771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.2300486771
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.786331609
Short name T88
Test name
Test status
Simulation time 30363017078 ps
CPU time 163.24 seconds
Started Apr 15 03:28:54 PM PDT 24
Finished Apr 15 03:31:38 PM PDT 24
Peak memory 573380 kb
Host smart-226a49a1-6fdf-4a29-b9b2-887f014a5b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786331609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.786331609
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.2207893479
Short name T1251
Test name
Test status
Simulation time 1753422439 ps
CPU time 33.63 seconds
Started Apr 15 03:28:53 PM PDT 24
Finished Apr 15 03:29:28 PM PDT 24
Peak memory 404960 kb
Host smart-8d694e24-aacc-439f-bacd-9609b747d639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207893479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.2207893479
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.3537376195
Short name T46
Test name
Test status
Simulation time 42835168930 ps
CPU time 510.3 seconds
Started Apr 15 03:28:52 PM PDT 24
Finished Apr 15 03:37:23 PM PDT 24
Peak memory 2213396 kb
Host smart-b5cc420e-cc59-43b7-9259-7a93f5f3ed75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537376195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.3537376195
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.987789306
Short name T620
Test name
Test status
Simulation time 721074748 ps
CPU time 17.21 seconds
Started Apr 15 03:28:55 PM PDT 24
Finished Apr 15 03:29:14 PM PDT 24
Peak memory 212176 kb
Host smart-85dd28c3-af4a-4c73-9ba4-94a5cc71e42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987789306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.987789306
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.274185447
Short name T429
Test name
Test status
Simulation time 3635073183 ps
CPU time 4.27 seconds
Started Apr 15 03:29:05 PM PDT 24
Finished Apr 15 03:29:10 PM PDT 24
Peak memory 204116 kb
Host smart-052c4c48-d442-4e03-ad3b-39ace76c90b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274185447 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.274185447
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.1688698963
Short name T914
Test name
Test status
Simulation time 10134431102 ps
CPU time 45.05 seconds
Started Apr 15 03:28:56 PM PDT 24
Finished Apr 15 03:29:42 PM PDT 24
Peak memory 429260 kb
Host smart-f9ef05f4-040f-4542-9bc1-361959dfaf2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688698963 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.1688698963
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.2926452159
Short name T1247
Test name
Test status
Simulation time 10355603831 ps
CPU time 13.83 seconds
Started Apr 15 03:28:59 PM PDT 24
Finished Apr 15 03:29:14 PM PDT 24
Peak memory 298856 kb
Host smart-eb28f00d-2721-4850-b871-bf5926060c79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926452159 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.2926452159
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.2548624483
Short name T282
Test name
Test status
Simulation time 1384192079 ps
CPU time 2.46 seconds
Started Apr 15 03:28:57 PM PDT 24
Finished Apr 15 03:29:01 PM PDT 24
Peak memory 204012 kb
Host smart-b408b800-6702-4059-941f-d7e412cef2eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548624483 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.2548624483
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.549279112
Short name T828
Test name
Test status
Simulation time 1699011253 ps
CPU time 4.28 seconds
Started Apr 15 03:29:00 PM PDT 24
Finished Apr 15 03:29:05 PM PDT 24
Peak memory 204028 kb
Host smart-1bf3d320-bd29-489d-8561-d40289da3f9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549279112 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_intr_smoke.549279112
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.194451074
Short name T286
Test name
Test status
Simulation time 17127575839 ps
CPU time 236.61 seconds
Started Apr 15 03:28:59 PM PDT 24
Finished Apr 15 03:32:57 PM PDT 24
Peak memory 2520316 kb
Host smart-75c78d80-c449-4d5b-baa0-7972850896d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194451074 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.194451074
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.3112564331
Short name T527
Test name
Test status
Simulation time 2414461853 ps
CPU time 9.85 seconds
Started Apr 15 03:28:56 PM PDT 24
Finished Apr 15 03:29:07 PM PDT 24
Peak memory 204076 kb
Host smart-cc280dc3-63d5-4f17-8c15-d72e63dd9a38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112564331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.3112564331
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.2375027567
Short name T844
Test name
Test status
Simulation time 829236638 ps
CPU time 9.67 seconds
Started Apr 15 03:28:59 PM PDT 24
Finished Apr 15 03:29:11 PM PDT 24
Peak memory 207124 kb
Host smart-b5380e79-9741-4046-85a6-d45bacc5ec06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375027567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.2375027567
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.2280303896
Short name T301
Test name
Test status
Simulation time 55969988360 ps
CPU time 1912.53 seconds
Started Apr 15 03:28:57 PM PDT 24
Finished Apr 15 04:00:52 PM PDT 24
Peak memory 9132932 kb
Host smart-5326aa97-b0d7-4bce-943b-cc3935a9fe73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280303896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.2280303896
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.1075158175
Short name T74
Test name
Test status
Simulation time 44748405011 ps
CPU time 189.8 seconds
Started Apr 15 03:28:57 PM PDT 24
Finished Apr 15 03:32:08 PM PDT 24
Peak memory 1724608 kb
Host smart-d952a8d2-3679-4ee1-b327-dbefb7b632d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075158175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.1075158175
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.581097629
Short name T285
Test name
Test status
Simulation time 5840796899 ps
CPU time 6.53 seconds
Started Apr 15 03:29:00 PM PDT 24
Finished Apr 15 03:29:08 PM PDT 24
Peak memory 204096 kb
Host smart-426b980a-fbc1-4a22-982d-4636c882c8cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581097629 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_timeout.581097629
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.3607013448
Short name T1325
Test name
Test status
Simulation time 37577716 ps
CPU time 0.62 seconds
Started Apr 15 03:29:04 PM PDT 24
Finished Apr 15 03:29:05 PM PDT 24
Peak memory 203556 kb
Host smart-8851c3cd-17de-4f1f-9a70-468c49a41b68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607013448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.3607013448
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1671552882
Short name T1043
Test name
Test status
Simulation time 61554624 ps
CPU time 1.6 seconds
Started Apr 15 03:29:00 PM PDT 24
Finished Apr 15 03:29:03 PM PDT 24
Peak memory 220496 kb
Host smart-8b59687a-92d7-4633-bc0c-764aa63ed63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671552882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1671552882
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.429014182
Short name T399
Test name
Test status
Simulation time 1372790007 ps
CPU time 6.33 seconds
Started Apr 15 03:28:59 PM PDT 24
Finished Apr 15 03:29:07 PM PDT 24
Peak memory 256576 kb
Host smart-71167d91-b59b-48a1-b2a7-da480cc8cd2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429014182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty
.429014182
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.690313732
Short name T433
Test name
Test status
Simulation time 1659072467 ps
CPU time 47.43 seconds
Started Apr 15 03:28:57 PM PDT 24
Finished Apr 15 03:29:45 PM PDT 24
Peak memory 490848 kb
Host smart-a51b9aba-a53f-4836-a527-b5bab5009c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690313732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.690313732
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.1518945724
Short name T1109
Test name
Test status
Simulation time 5986830145 ps
CPU time 111.28 seconds
Started Apr 15 03:28:57 PM PDT 24
Finished Apr 15 03:30:49 PM PDT 24
Peak memory 577880 kb
Host smart-df0b69bf-be63-4933-b8d6-4dda2377fd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518945724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1518945724
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.923141424
Short name T274
Test name
Test status
Simulation time 210411994 ps
CPU time 1 seconds
Started Apr 15 03:28:56 PM PDT 24
Finished Apr 15 03:28:58 PM PDT 24
Peak memory 203752 kb
Host smart-67d0d07e-e0d6-4624-ab64-f48bbe55eb61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923141424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt
.923141424
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.1145352217
Short name T890
Test name
Test status
Simulation time 124128333 ps
CPU time 7.17 seconds
Started Apr 15 03:29:01 PM PDT 24
Finished Apr 15 03:29:09 PM PDT 24
Peak memory 224096 kb
Host smart-ccbc83ed-81f7-4feb-b85a-ed8bc78f75ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145352217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
1145352217
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.128681604
Short name T1042
Test name
Test status
Simulation time 9918969961 ps
CPU time 223.67 seconds
Started Apr 15 03:29:04 PM PDT 24
Finished Apr 15 03:32:48 PM PDT 24
Peak memory 970248 kb
Host smart-8a8989d4-2775-4560-b0c4-07b885458605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128681604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.128681604
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.3488488380
Short name T485
Test name
Test status
Simulation time 1013904656 ps
CPU time 9.72 seconds
Started Apr 15 03:29:00 PM PDT 24
Finished Apr 15 03:29:11 PM PDT 24
Peak memory 203904 kb
Host smart-f0906878-b64e-4266-9f43-4715eaec8196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488488380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.3488488380
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.518713489
Short name T1068
Test name
Test status
Simulation time 778551271 ps
CPU time 35.01 seconds
Started Apr 15 03:29:06 PM PDT 24
Finished Apr 15 03:29:42 PM PDT 24
Peak memory 244688 kb
Host smart-d084392e-d825-49e3-b9ab-78b19af84de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518713489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.518713489
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.3844120015
Short name T418
Test name
Test status
Simulation time 78589005 ps
CPU time 0.68 seconds
Started Apr 15 03:28:59 PM PDT 24
Finished Apr 15 03:29:02 PM PDT 24
Peak memory 203460 kb
Host smart-a6a99a89-f2a0-4d44-895f-bb5b5f3bcf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844120015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.3844120015
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.2549442963
Short name T71
Test name
Test status
Simulation time 13305681965 ps
CPU time 117.85 seconds
Started Apr 15 03:28:59 PM PDT 24
Finished Apr 15 03:30:57 PM PDT 24
Peak memory 1018344 kb
Host smart-4161d824-4766-4612-b79f-27b0a4e0c93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549442963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.2549442963
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.667878023
Short name T657
Test name
Test status
Simulation time 2676600767 ps
CPU time 71.58 seconds
Started Apr 15 03:28:59 PM PDT 24
Finished Apr 15 03:30:12 PM PDT 24
Peak memory 365768 kb
Host smart-5846b1e2-2657-4880-a05a-42544d2f3988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667878023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.667878023
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.1445675814
Short name T174
Test name
Test status
Simulation time 25856885553 ps
CPU time 668.56 seconds
Started Apr 15 03:28:58 PM PDT 24
Finished Apr 15 03:40:08 PM PDT 24
Peak memory 2127428 kb
Host smart-4ddf2ade-4d7e-4938-b9d7-ce29c6adc630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445675814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.1445675814
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.2753054419
Short name T906
Test name
Test status
Simulation time 530557761 ps
CPU time 23.88 seconds
Started Apr 15 03:29:04 PM PDT 24
Finished Apr 15 03:29:28 PM PDT 24
Peak memory 212192 kb
Host smart-991a156d-2806-476d-990a-f6d31cafd1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753054419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.2753054419
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.3699225673
Short name T1264
Test name
Test status
Simulation time 2242036714 ps
CPU time 4.96 seconds
Started Apr 15 03:29:05 PM PDT 24
Finished Apr 15 03:29:11 PM PDT 24
Peak memory 205360 kb
Host smart-d4d26f54-0a9c-4afe-8a04-5965401a7ec9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699225673 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.3699225673
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2008526226
Short name T764
Test name
Test status
Simulation time 10308474342 ps
CPU time 20.24 seconds
Started Apr 15 03:29:14 PM PDT 24
Finished Apr 15 03:29:35 PM PDT 24
Peak memory 314016 kb
Host smart-cbe4f862-43a9-4611-9a2c-193350d92e68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008526226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2008526226
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.3177445022
Short name T453
Test name
Test status
Simulation time 10199804396 ps
CPU time 11.02 seconds
Started Apr 15 03:29:02 PM PDT 24
Finished Apr 15 03:29:14 PM PDT 24
Peak memory 283740 kb
Host smart-0f288c8f-e7ff-4225-b23a-1c4d1fef9fb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177445022 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.3177445022
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.4170364619
Short name T1115
Test name
Test status
Simulation time 1278735133 ps
CPU time 2.78 seconds
Started Apr 15 03:29:01 PM PDT 24
Finished Apr 15 03:29:05 PM PDT 24
Peak memory 204016 kb
Host smart-d129bde8-5d48-49f0-9f30-a14d87e80e4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170364619 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.4170364619
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.4241163131
Short name T396
Test name
Test status
Simulation time 1247845524 ps
CPU time 5.75 seconds
Started Apr 15 03:29:02 PM PDT 24
Finished Apr 15 03:29:09 PM PDT 24
Peak memory 212020 kb
Host smart-2b5405a7-af0c-425b-946f-23d9f67847ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241163131 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.4241163131
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.1797527263
Short name T495
Test name
Test status
Simulation time 11863622008 ps
CPU time 17.24 seconds
Started Apr 15 03:29:04 PM PDT 24
Finished Apr 15 03:29:22 PM PDT 24
Peak memory 431060 kb
Host smart-c6855f1a-25bf-4fdd-bfa9-b6861f979420
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797527263 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.1797527263
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.699782811
Short name T444
Test name
Test status
Simulation time 953822061 ps
CPU time 14.41 seconds
Started Apr 15 03:29:00 PM PDT 24
Finished Apr 15 03:29:16 PM PDT 24
Peak memory 204012 kb
Host smart-d30333b7-a2a3-40db-8feb-4bd37a24227e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699782811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_targ
et_smoke.699782811
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.1350518779
Short name T613
Test name
Test status
Simulation time 3848815601 ps
CPU time 13.55 seconds
Started Apr 15 03:29:00 PM PDT 24
Finished Apr 15 03:29:15 PM PDT 24
Peak memory 217396 kb
Host smart-206a2c58-4ede-4628-b75f-3e40253d8983
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350518779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.1350518779
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.3184418408
Short name T500
Test name
Test status
Simulation time 45445854569 ps
CPU time 63.08 seconds
Started Apr 15 03:28:59 PM PDT 24
Finished Apr 15 03:30:03 PM PDT 24
Peak memory 1013980 kb
Host smart-c988f83c-bed8-40d2-b117-b1381927c5ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184418408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.3184418408
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.3002802955
Short name T997
Test name
Test status
Simulation time 11697828295 ps
CPU time 43.16 seconds
Started Apr 15 03:29:05 PM PDT 24
Finished Apr 15 03:29:49 PM PDT 24
Peak memory 560980 kb
Host smart-42e1fb3f-34ed-4490-8290-e0f4fc07b1a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002802955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.3002802955
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.2581162174
Short name T905
Test name
Test status
Simulation time 3129855033 ps
CPU time 6.8 seconds
Started Apr 15 03:29:01 PM PDT 24
Finished Apr 15 03:29:09 PM PDT 24
Peak memory 204056 kb
Host smart-5bb551da-463f-4d48-9b26-473ac4e62661
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581162174 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.2581162174
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.3157601270
Short name T870
Test name
Test status
Simulation time 41504511 ps
CPU time 0.66 seconds
Started Apr 15 03:29:07 PM PDT 24
Finished Apr 15 03:29:08 PM PDT 24
Peak memory 203604 kb
Host smart-3d575126-568b-4f32-99dc-de44efa6f14b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157601270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.3157601270
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.459837604
Short name T342
Test name
Test status
Simulation time 358145005 ps
CPU time 1.79 seconds
Started Apr 15 03:29:08 PM PDT 24
Finished Apr 15 03:29:11 PM PDT 24
Peak memory 212312 kb
Host smart-44975d8d-b297-4d42-a1b5-1d6f85275c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459837604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.459837604
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.3870913176
Short name T1322
Test name
Test status
Simulation time 484990500 ps
CPU time 4.7 seconds
Started Apr 15 03:29:01 PM PDT 24
Finished Apr 15 03:29:07 PM PDT 24
Peak memory 250572 kb
Host smart-3914fe20-f779-4c90-bceb-839c9984e9c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870913176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.3870913176
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.2365338701
Short name T48
Test name
Test status
Simulation time 2610487546 ps
CPU time 195.64 seconds
Started Apr 15 03:29:31 PM PDT 24
Finished Apr 15 03:32:47 PM PDT 24
Peak memory 825560 kb
Host smart-7327ce0c-b285-4685-85fb-97049d0fe438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365338701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.2365338701
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.2001569453
Short name T1176
Test name
Test status
Simulation time 20906977498 ps
CPU time 33.54 seconds
Started Apr 15 03:29:03 PM PDT 24
Finished Apr 15 03:29:37 PM PDT 24
Peak memory 465380 kb
Host smart-cac1af1f-d806-456b-a3a1-9026da994600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001569453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2001569453
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.2935527119
Short name T1007
Test name
Test status
Simulation time 637172843 ps
CPU time 0.94 seconds
Started Apr 15 03:29:03 PM PDT 24
Finished Apr 15 03:29:04 PM PDT 24
Peak memory 203724 kb
Host smart-aa93a71b-dcea-47ac-a965-6cb7e11564d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935527119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.2935527119
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.3411733925
Short name T1324
Test name
Test status
Simulation time 661035062 ps
CPU time 3.61 seconds
Started Apr 15 03:29:07 PM PDT 24
Finished Apr 15 03:29:12 PM PDT 24
Peak memory 203892 kb
Host smart-309e622d-878a-4ebd-8648-fabcc277bf1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411733925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
3411733925
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.1823744924
Short name T742
Test name
Test status
Simulation time 29435801825 ps
CPU time 262.05 seconds
Started Apr 15 03:29:03 PM PDT 24
Finished Apr 15 03:33:26 PM PDT 24
Peak memory 1016020 kb
Host smart-174b53a6-3f6a-468e-9c9f-c94c9fab7716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823744924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.1823744924
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.576101217
Short name T237
Test name
Test status
Simulation time 2867018581 ps
CPU time 8.83 seconds
Started Apr 15 03:29:13 PM PDT 24
Finished Apr 15 03:29:23 PM PDT 24
Peak memory 203952 kb
Host smart-8944c495-2100-4e34-9ba7-bde2e206c01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576101217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.576101217
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.176340831
Short name T348
Test name
Test status
Simulation time 8942966393 ps
CPU time 29.96 seconds
Started Apr 15 03:29:06 PM PDT 24
Finished Apr 15 03:29:37 PM PDT 24
Peak memory 347916 kb
Host smart-c1168f4d-dcab-450d-9f66-d89138243c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176340831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.176340831
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.1534934851
Short name T763
Test name
Test status
Simulation time 30694555 ps
CPU time 0.65 seconds
Started Apr 15 03:29:07 PM PDT 24
Finished Apr 15 03:29:09 PM PDT 24
Peak memory 203676 kb
Host smart-aae7b8e6-d65a-4b82-800b-e54d74a5631f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534934851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.1534934851
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.3661871911
Short name T981
Test name
Test status
Simulation time 29530263184 ps
CPU time 394.59 seconds
Started Apr 15 03:29:07 PM PDT 24
Finished Apr 15 03:35:43 PM PDT 24
Peak memory 533464 kb
Host smart-3a81057d-630d-4d82-9efb-c3c796c3cf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661871911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.3661871911
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.1124105891
Short name T908
Test name
Test status
Simulation time 5493944834 ps
CPU time 28.94 seconds
Started Apr 15 03:29:02 PM PDT 24
Finished Apr 15 03:29:32 PM PDT 24
Peak memory 316804 kb
Host smart-eaf462a8-ac1f-46d5-81e1-41d58711f462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124105891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.1124105891
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.557284817
Short name T202
Test name
Test status
Simulation time 621013841 ps
CPU time 24.32 seconds
Started Apr 15 03:29:08 PM PDT 24
Finished Apr 15 03:29:33 PM PDT 24
Peak memory 212188 kb
Host smart-88c5f2d3-e70e-4629-aac9-b180173043a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557284817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.557284817
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.2920172800
Short name T1294
Test name
Test status
Simulation time 2386951357 ps
CPU time 3.2 seconds
Started Apr 15 03:29:07 PM PDT 24
Finished Apr 15 03:29:11 PM PDT 24
Peak memory 204060 kb
Host smart-14c2e863-3ef1-4ddc-964b-2b886d42cd39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920172800 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2920172800
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2584925828
Short name T78
Test name
Test status
Simulation time 10918539249 ps
CPU time 3.63 seconds
Started Apr 15 03:29:07 PM PDT 24
Finished Apr 15 03:29:12 PM PDT 24
Peak memory 223652 kb
Host smart-bb902520-a01d-4ff4-a448-e420f3d0bfc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584925828 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2584925828
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.707065615
Short name T1283
Test name
Test status
Simulation time 10162313447 ps
CPU time 12.58 seconds
Started Apr 15 03:29:07 PM PDT 24
Finished Apr 15 03:29:21 PM PDT 24
Peak memory 297168 kb
Host smart-41197172-9c78-4d1a-9ffb-f6ef01f69e56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707065615 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_fifo_reset_tx.707065615
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.410190083
Short name T244
Test name
Test status
Simulation time 810441719 ps
CPU time 1.62 seconds
Started Apr 15 03:29:08 PM PDT 24
Finished Apr 15 03:29:11 PM PDT 24
Peak memory 204004 kb
Host smart-b64bb473-8699-4f0f-a092-f4683b3e2531
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410190083 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.i2c_target_hrst.410190083
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1708584828
Short name T1301
Test name
Test status
Simulation time 2977898136 ps
CPU time 3.92 seconds
Started Apr 15 03:29:08 PM PDT 24
Finished Apr 15 03:29:13 PM PDT 24
Peak memory 204004 kb
Host smart-7ebad884-34a6-4f31-bcf9-94694852025b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708584828 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1708584828
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.4092469716
Short name T975
Test name
Test status
Simulation time 8556284989 ps
CPU time 22.13 seconds
Started Apr 15 03:29:08 PM PDT 24
Finished Apr 15 03:29:31 PM PDT 24
Peak memory 437624 kb
Host smart-e4c11086-6f9b-4d65-9317-7041837e1799
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092469716 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.4092469716
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.3949024690
Short name T991
Test name
Test status
Simulation time 14805728654 ps
CPU time 21.57 seconds
Started Apr 15 03:29:07 PM PDT 24
Finished Apr 15 03:29:30 PM PDT 24
Peak memory 204088 kb
Host smart-7ea02bcc-15ac-4380-ae73-ea5148c54e9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949024690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.3949024690
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.1330632925
Short name T718
Test name
Test status
Simulation time 4084250419 ps
CPU time 19.15 seconds
Started Apr 15 03:29:08 PM PDT 24
Finished Apr 15 03:29:28 PM PDT 24
Peak memory 204020 kb
Host smart-120caa1f-1b96-4baf-884f-76523ce83f07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330632925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.1330632925
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.2558995428
Short name T852
Test name
Test status
Simulation time 36778501032 ps
CPU time 158.65 seconds
Started Apr 15 03:29:08 PM PDT 24
Finished Apr 15 03:31:47 PM PDT 24
Peak memory 2142468 kb
Host smart-df0dcd6b-27fa-45bc-a9cd-dde809d90b41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558995428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.2558995428
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.188545833
Short name T271
Test name
Test status
Simulation time 17713648200 ps
CPU time 837.76 seconds
Started Apr 15 03:29:08 PM PDT 24
Finished Apr 15 03:43:07 PM PDT 24
Peak memory 2008372 kb
Host smart-269b82cd-ca8f-4e6b-ac13-0d9df8492a31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188545833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_ta
rget_stretch.188545833
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.2616787281
Short name T465
Test name
Test status
Simulation time 1315999807 ps
CPU time 6.63 seconds
Started Apr 15 03:29:20 PM PDT 24
Finished Apr 15 03:29:27 PM PDT 24
Peak memory 204036 kb
Host smart-91e916d5-bf0c-4941-a8e9-a4e7afaad2d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616787281 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.2616787281
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.1274552443
Short name T643
Test name
Test status
Simulation time 45871458 ps
CPU time 0.64 seconds
Started Apr 15 03:29:19 PM PDT 24
Finished Apr 15 03:29:20 PM PDT 24
Peak memory 203588 kb
Host smart-bd54b9f5-c404-4d7d-b425-ed414a39b1bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274552443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.1274552443
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.1485118556
Short name T901
Test name
Test status
Simulation time 136924029 ps
CPU time 1.39 seconds
Started Apr 15 03:29:13 PM PDT 24
Finished Apr 15 03:29:15 PM PDT 24
Peak memory 212304 kb
Host smart-6422a34e-9853-48f8-ac58-fecaa6a1cf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485118556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.1485118556
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.4253490721
Short name T1130
Test name
Test status
Simulation time 324467577 ps
CPU time 17.12 seconds
Started Apr 15 03:29:11 PM PDT 24
Finished Apr 15 03:29:29 PM PDT 24
Peak memory 274588 kb
Host smart-26b7d0f7-14a8-4c4b-ad51-1a2a0bb99679
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253490721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.4253490721
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.1377649949
Short name T697
Test name
Test status
Simulation time 1531905252 ps
CPU time 41.62 seconds
Started Apr 15 03:29:11 PM PDT 24
Finished Apr 15 03:29:54 PM PDT 24
Peak memory 569044 kb
Host smart-358eb26b-86b1-4215-a337-fb803fd71800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377649949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.1377649949
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.871960034
Short name T102
Test name
Test status
Simulation time 1726694640 ps
CPU time 55.84 seconds
Started Apr 15 03:29:10 PM PDT 24
Finished Apr 15 03:30:06 PM PDT 24
Peak memory 601196 kb
Host smart-c1499a37-2136-43e2-b4a8-685787295eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871960034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.871960034
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.1925752556
Short name T398
Test name
Test status
Simulation time 545825099 ps
CPU time 1.23 seconds
Started Apr 15 03:29:11 PM PDT 24
Finished Apr 15 03:29:13 PM PDT 24
Peak memory 203852 kb
Host smart-a6b1afb5-89bc-4a0c-a28d-74f1964e2ab7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925752556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.1925752556
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.1736243007
Short name T505
Test name
Test status
Simulation time 127047555 ps
CPU time 7 seconds
Started Apr 15 03:29:11 PM PDT 24
Finished Apr 15 03:29:19 PM PDT 24
Peak memory 222888 kb
Host smart-8e19de0f-765a-4eb7-b2e0-b60a764e6597
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736243007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
1736243007
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.392738646
Short name T825
Test name
Test status
Simulation time 13280426805 ps
CPU time 57.66 seconds
Started Apr 15 03:29:11 PM PDT 24
Finished Apr 15 03:30:10 PM PDT 24
Peak memory 832964 kb
Host smart-b64cf264-9749-45cd-9831-4c8e62a75b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392738646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.392738646
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.2559692942
Short name T1150
Test name
Test status
Simulation time 651082423 ps
CPU time 13.24 seconds
Started Apr 15 03:29:16 PM PDT 24
Finished Apr 15 03:29:30 PM PDT 24
Peak memory 203980 kb
Host smart-e3a99eb3-00e9-4822-968c-e6fd2ef8404c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559692942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2559692942
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.2770805114
Short name T105
Test name
Test status
Simulation time 16682606093 ps
CPU time 57.46 seconds
Started Apr 15 03:29:19 PM PDT 24
Finished Apr 15 03:30:17 PM PDT 24
Peak memory 293560 kb
Host smart-f99487ef-17e6-4d57-94a6-d6f5a05fa187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770805114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.2770805114
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.545982823
Short name T390
Test name
Test status
Simulation time 27822411 ps
CPU time 0.67 seconds
Started Apr 15 03:29:11 PM PDT 24
Finished Apr 15 03:29:12 PM PDT 24
Peak memory 203640 kb
Host smart-5067c8ab-ab88-4ca0-9f98-e9e082b71154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545982823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.545982823
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.277559153
Short name T1199
Test name
Test status
Simulation time 71252867331 ps
CPU time 2150.76 seconds
Started Apr 15 03:29:11 PM PDT 24
Finished Apr 15 04:05:03 PM PDT 24
Peak memory 3590372 kb
Host smart-a78a1b11-7289-4149-8432-f1494967e5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277559153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.277559153
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.4128252558
Short name T882
Test name
Test status
Simulation time 1813316531 ps
CPU time 93.76 seconds
Started Apr 15 03:29:11 PM PDT 24
Finished Apr 15 03:30:46 PM PDT 24
Peak memory 408100 kb
Host smart-edaaa379-79c0-4224-9edb-84893858ace5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128252558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.4128252558
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.143199215
Short name T424
Test name
Test status
Simulation time 16967641214 ps
CPU time 1078.18 seconds
Started Apr 15 03:29:10 PM PDT 24
Finished Apr 15 03:47:09 PM PDT 24
Peak memory 2109608 kb
Host smart-dab30a08-ccda-4461-a5c4-4b6786409341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143199215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.143199215
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.2100927630
Short name T1149
Test name
Test status
Simulation time 1387841723 ps
CPU time 9.14 seconds
Started Apr 15 03:29:10 PM PDT 24
Finished Apr 15 03:29:20 PM PDT 24
Peak memory 215012 kb
Host smart-630accde-14cf-476f-b00a-48b0a486e7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100927630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.2100927630
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.867584406
Short name T523
Test name
Test status
Simulation time 1336746886 ps
CPU time 2.02 seconds
Started Apr 15 03:29:14 PM PDT 24
Finished Apr 15 03:29:17 PM PDT 24
Peak memory 203784 kb
Host smart-274b3b7d-446a-485b-a0bb-22a546ad510f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867584406 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.867584406
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.4066426791
Short name T1088
Test name
Test status
Simulation time 10054931022 ps
CPU time 67.15 seconds
Started Apr 15 03:29:14 PM PDT 24
Finished Apr 15 03:30:22 PM PDT 24
Peak memory 474552 kb
Host smart-c49f87ff-3758-4fae-bd7c-7a7dd0d2ffaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066426791 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.4066426791
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.898266362
Short name T1278
Test name
Test status
Simulation time 10718172339 ps
CPU time 9.29 seconds
Started Apr 15 03:29:17 PM PDT 24
Finished Apr 15 03:29:27 PM PDT 24
Peak memory 262832 kb
Host smart-0a0d10cb-fbb8-4082-b7fa-ca165863e394
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898266362 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_fifo_reset_tx.898266362
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.2500597506
Short name T543
Test name
Test status
Simulation time 337756915 ps
CPU time 1.94 seconds
Started Apr 15 03:29:17 PM PDT 24
Finished Apr 15 03:29:19 PM PDT 24
Peak memory 204012 kb
Host smart-33beeefc-160c-403e-a1ac-03111255f53e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500597506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.2500597506
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.3607956574
Short name T830
Test name
Test status
Simulation time 4592600655 ps
CPU time 5.05 seconds
Started Apr 15 03:29:15 PM PDT 24
Finished Apr 15 03:29:21 PM PDT 24
Peak memory 204032 kb
Host smart-9966ea9b-56af-497a-8057-503f228f52fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607956574 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.3607956574
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.2787125597
Short name T936
Test name
Test status
Simulation time 10736936475 ps
CPU time 62.29 seconds
Started Apr 15 03:29:17 PM PDT 24
Finished Apr 15 03:30:20 PM PDT 24
Peak memory 1067412 kb
Host smart-3a169f32-87df-4a74-9184-b468e5a11446
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787125597 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.2787125597
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.2090094680
Short name T203
Test name
Test status
Simulation time 2523731369 ps
CPU time 44.68 seconds
Started Apr 15 03:29:09 PM PDT 24
Finished Apr 15 03:29:54 PM PDT 24
Peak memory 204032 kb
Host smart-e530fc03-e012-47d4-8abf-e72635cb674d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090094680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.2090094680
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.1437198674
Short name T946
Test name
Test status
Simulation time 1071291690 ps
CPU time 41.09 seconds
Started Apr 15 03:29:16 PM PDT 24
Finished Apr 15 03:29:57 PM PDT 24
Peak memory 203976 kb
Host smart-46bce816-d8e6-4778-a5fc-cf116a989b17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437198674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.1437198674
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.3135544403
Short name T805
Test name
Test status
Simulation time 36743038919 ps
CPU time 160.68 seconds
Started Apr 15 03:29:13 PM PDT 24
Finished Apr 15 03:31:54 PM PDT 24
Peak memory 2196732 kb
Host smart-6f7f5b46-ddb9-4cd2-9149-864675412f95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135544403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.3135544403
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.2848835233
Short name T519
Test name
Test status
Simulation time 18623129120 ps
CPU time 3476.18 seconds
Started Apr 15 03:29:14 PM PDT 24
Finished Apr 15 04:27:12 PM PDT 24
Peak memory 4555364 kb
Host smart-9ba564c7-b54d-4f48-bf75-c312875a3439
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848835233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.2848835233
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.434658567
Short name T940
Test name
Test status
Simulation time 11410733820 ps
CPU time 6.61 seconds
Started Apr 15 03:29:16 PM PDT 24
Finished Apr 15 03:29:24 PM PDT 24
Peak memory 204072 kb
Host smart-c6aa6c48-67e1-4c4d-be00-4b7acc9afed9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434658567 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_timeout.434658567
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_unexp_stop.3574982148
Short name T1063
Test name
Test status
Simulation time 671301580 ps
CPU time 4.25 seconds
Started Apr 15 03:29:16 PM PDT 24
Finished Apr 15 03:29:21 PM PDT 24
Peak memory 204028 kb
Host smart-c2bc2ecc-1748-405c-a2f5-75d5fc0043b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574982148 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.i2c_target_unexp_stop.3574982148
Directory /workspace/8.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/9.i2c_alert_test.118129376
Short name T482
Test name
Test status
Simulation time 16580817 ps
CPU time 0.63 seconds
Started Apr 15 03:29:30 PM PDT 24
Finished Apr 15 03:29:31 PM PDT 24
Peak memory 203592 kb
Host smart-d81a2312-d6ce-42ae-aa07-3996246d286d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118129376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.118129376
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.2280138368
Short name T601
Test name
Test status
Simulation time 146427033 ps
CPU time 1.67 seconds
Started Apr 15 03:29:23 PM PDT 24
Finished Apr 15 03:29:25 PM PDT 24
Peak memory 212280 kb
Host smart-66780ca5-aff9-4af7-9b4e-c65b341dfc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280138368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.2280138368
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.616690217
Short name T924
Test name
Test status
Simulation time 522717753 ps
CPU time 9.45 seconds
Started Apr 15 03:29:18 PM PDT 24
Finished Apr 15 03:29:28 PM PDT 24
Peak memory 238064 kb
Host smart-40fbd1e4-c9a1-4fc5-9d8c-ce88185a57c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616690217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty
.616690217
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.1434882845
Short name T615
Test name
Test status
Simulation time 1602661969 ps
CPU time 57.55 seconds
Started Apr 15 03:29:19 PM PDT 24
Finished Apr 15 03:30:17 PM PDT 24
Peak memory 591956 kb
Host smart-1cfd0cbe-c16e-487d-9837-64d250cbe76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434882845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.1434882845
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.4079754698
Short name T1297
Test name
Test status
Simulation time 2064740756 ps
CPU time 146.89 seconds
Started Apr 15 03:29:17 PM PDT 24
Finished Apr 15 03:31:45 PM PDT 24
Peak memory 628540 kb
Host smart-2ed48d32-2dcb-4587-afd0-40c22199caa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079754698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.4079754698
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.3799907916
Short name T35
Test name
Test status
Simulation time 135096733 ps
CPU time 0.99 seconds
Started Apr 15 03:29:19 PM PDT 24
Finished Apr 15 03:29:20 PM PDT 24
Peak memory 203728 kb
Host smart-4c7819dd-47ba-4bdc-bf8c-02b927e5c039
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799907916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.3799907916
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.1340025519
Short name T1055
Test name
Test status
Simulation time 2878666299 ps
CPU time 3.69 seconds
Started Apr 15 03:29:18 PM PDT 24
Finished Apr 15 03:29:23 PM PDT 24
Peak memory 203912 kb
Host smart-d0b30d28-9a5c-4226-a4d9-2e7096b9ff6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340025519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
1340025519
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.1841638077
Short name T177
Test name
Test status
Simulation time 3269903269 ps
CPU time 51.91 seconds
Started Apr 15 03:29:16 PM PDT 24
Finished Apr 15 03:30:08 PM PDT 24
Peak memory 743456 kb
Host smart-1d4caf6f-5d1d-4a31-b216-8f160441d993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841638077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1841638077
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.2774853194
Short name T327
Test name
Test status
Simulation time 534309811 ps
CPU time 21.1 seconds
Started Apr 15 03:29:26 PM PDT 24
Finished Apr 15 03:29:48 PM PDT 24
Peak memory 203900 kb
Host smart-2fb802f2-6aba-4864-b63a-502eddfd6dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774853194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.2774853194
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.4042337352
Short name T1019
Test name
Test status
Simulation time 3748628195 ps
CPU time 44.21 seconds
Started Apr 15 03:29:25 PM PDT 24
Finished Apr 15 03:30:11 PM PDT 24
Peak memory 294172 kb
Host smart-0aa7cb65-946f-445a-8b5c-32715b4e56dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042337352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.4042337352
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.3123466609
Short name T706
Test name
Test status
Simulation time 122440898 ps
CPU time 0.64 seconds
Started Apr 15 03:29:20 PM PDT 24
Finished Apr 15 03:29:21 PM PDT 24
Peak memory 203640 kb
Host smart-cf7bcb33-3bcb-4301-a023-f50a54121018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123466609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.3123466609
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.2374453867
Short name T627
Test name
Test status
Simulation time 433365247 ps
CPU time 2.04 seconds
Started Apr 15 03:29:19 PM PDT 24
Finished Apr 15 03:29:21 PM PDT 24
Peak memory 212192 kb
Host smart-9caaa41e-d867-4147-b52c-131363c71a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374453867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2374453867
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.2861278335
Short name T1030
Test name
Test status
Simulation time 4692224926 ps
CPU time 25 seconds
Started Apr 15 03:29:17 PM PDT 24
Finished Apr 15 03:29:43 PM PDT 24
Peak memory 315888 kb
Host smart-4df8350f-6233-4b2c-a2c8-66abf841d9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861278335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2861278335
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.3506974439
Short name T90
Test name
Test status
Simulation time 26256943893 ps
CPU time 382.06 seconds
Started Apr 15 03:29:23 PM PDT 24
Finished Apr 15 03:35:45 PM PDT 24
Peak memory 1680684 kb
Host smart-a89c4052-4ce5-4e18-a326-a45abd24d4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506974439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.3506974439
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.3602872856
Short name T302
Test name
Test status
Simulation time 424992116 ps
CPU time 20.06 seconds
Started Apr 15 03:29:22 PM PDT 24
Finished Apr 15 03:29:43 PM PDT 24
Peak memory 212288 kb
Host smart-a2a296ee-c734-48ab-8d08-4ca6c81b8f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602872856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.3602872856
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.1497604130
Short name T428
Test name
Test status
Simulation time 2310839897 ps
CPU time 3.91 seconds
Started Apr 15 03:29:26 PM PDT 24
Finished Apr 15 03:29:31 PM PDT 24
Peak memory 204092 kb
Host smart-e142141f-d040-4793-92ab-2c3a8e5d7981
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497604130 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.1497604130
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.2084602160
Short name T504
Test name
Test status
Simulation time 10832599225 ps
CPU time 7.8 seconds
Started Apr 15 03:29:21 PM PDT 24
Finished Apr 15 03:29:30 PM PDT 24
Peak memory 245960 kb
Host smart-160d49d4-bd68-47ae-a160-d80e42240ab2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084602160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.2084602160
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.2510497415
Short name T1119
Test name
Test status
Simulation time 10217510659 ps
CPU time 31.02 seconds
Started Apr 15 03:29:21 PM PDT 24
Finished Apr 15 03:29:53 PM PDT 24
Peak memory 336992 kb
Host smart-15c8fe7b-77f4-4cc4-903e-79ce2f29235c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510497415 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.2510497415
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.1101303057
Short name T400
Test name
Test status
Simulation time 1688192935 ps
CPU time 2.54 seconds
Started Apr 15 03:29:21 PM PDT 24
Finished Apr 15 03:29:24 PM PDT 24
Peak memory 204008 kb
Host smart-1b92fd90-1045-41fe-9d5a-95d636fa1d67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101303057 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.1101303057
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.3538468500
Short name T1189
Test name
Test status
Simulation time 941884451 ps
CPU time 4.25 seconds
Started Apr 15 03:29:20 PM PDT 24
Finished Apr 15 03:29:25 PM PDT 24
Peak memory 204072 kb
Host smart-741d0113-2b45-4ce8-8210-d3d98f6dd181
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538468500 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.3538468500
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.527167432
Short name T1330
Test name
Test status
Simulation time 14178475055 ps
CPU time 140.24 seconds
Started Apr 15 03:29:23 PM PDT 24
Finished Apr 15 03:31:44 PM PDT 24
Peak memory 1903852 kb
Host smart-e754b5e3-46ee-48f0-8856-4aec22c877e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527167432 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.527167432
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.2929411749
Short name T1279
Test name
Test status
Simulation time 1270781815 ps
CPU time 15.53 seconds
Started Apr 15 03:29:27 PM PDT 24
Finished Apr 15 03:29:43 PM PDT 24
Peak memory 204028 kb
Host smart-06426943-a2a5-4ec9-bf45-292d2073660d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929411749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.2929411749
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.61764761
Short name T329
Test name
Test status
Simulation time 1190427934 ps
CPU time 51.63 seconds
Started Apr 15 03:29:21 PM PDT 24
Finished Apr 15 03:30:14 PM PDT 24
Peak memory 205444 kb
Host smart-3b469bc1-c8e8-4574-b6a8-281797b9383f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61764761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stress_rd.61764761
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.610744121
Short name T596
Test name
Test status
Simulation time 52669896488 ps
CPU time 1486.84 seconds
Started Apr 15 03:29:21 PM PDT 24
Finished Apr 15 03:54:09 PM PDT 24
Peak memory 8303260 kb
Host smart-f98e5490-9dae-4a9a-ad95-16a17c3ebefe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610744121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_wr.610744121
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.3331441711
Short name T363
Test name
Test status
Simulation time 4885198486 ps
CPU time 5.76 seconds
Started Apr 15 03:29:24 PM PDT 24
Finished Apr 15 03:29:31 PM PDT 24
Peak memory 204076 kb
Host smart-86e3dc9c-2d45-4831-9e92-4ed055372c86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331441711 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.3331441711
Directory /workspace/9.i2c_target_timeout/latest
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