Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	867255	1			T1	1		T2	8131		T3	2
all_values[1]	867255	1			T1	1		T2	8131		T3	2
all_values[2]	867255	1			T1	1		T2	8131		T3	2
all_values[3]	867255	1			T1	1		T2	8131		T3	2
all_values[4]	867255	1			T1	1		T2	8131		T3	2
all_values[5]	867255	1			T1	1		T2	8131		T3	2
all_values[6]	867255	1			T1	1		T2	8131		T3	2
all_values[7]	867255	1			T1	1		T2	8131		T3	2
all_values[8]	867255	1			T1	1		T2	8131		T3	2
all_values[9]	867255	1			T1	1		T2	8131		T3	2
all_values[10]	867255	1			T1	1		T2	8131		T3	2
all_values[11]	867255	1			T1	1		T2	8131		T3	2
all_values[12]	867255	1			T1	1		T2	8131		T3	2
all_values[13]	867255	1			T1	1		T2	8131		T3	2
all_values[14]	867255	1			T1	1		T2	8131		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9273593

1

T1

15

T2

84642

T3

26

auto[1]

3735232

1

T2

37323

T3

4

T4

661

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10583275

1

T1

15

T2

121965

T3

30

auto[1]

2425550

1

T42

66046

T75

9969

T83

65918

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12] , all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	80001	1			T1	1		T2	1027		T4	3
all_values[0]	auto[0]	auto[1]	11545	1			T42	325		T75	574		T83	178
all_values[0]	auto[1]	auto[0]	644894	1			T2	7104		T3	2		T4	274
all_values[0]	auto[1]	auto[1]	130815	1			T42	4123		T75	91		T83	4215
all_values[1]	auto[0]	auto[0]	724503	1			T1	1		T2	8131		T3	2
all_values[1]	auto[0]	auto[1]	142113	1			T42	4443		T75	660		T83	4393
all_values[1]	auto[1]	auto[0]	412	1			T149	1		T62	3		T63	1
all_values[1]	auto[1]	auto[1]	227	1			T42	5		T75	5		T83	2
all_values[2]	auto[0]	auto[0]	697683	1			T1	1		T2	8131		T3	2
all_values[2]	auto[0]	auto[1]	169356	1			T42	4439		T75	664		T83	4393
all_values[2]	auto[1]	auto[1]	216	1			T42	9		T75	2		T83	2
all_values[3]	auto[0]	auto[0]	697683	1			T1	1		T2	8131		T3	2
all_values[3]	auto[0]	auto[1]	169325	1			T42	4441		T75	659		T83	4393
all_values[3]	auto[1]	auto[1]	247	1			T42	6		T75	5		T83	2
all_values[4]	auto[0]	auto[0]	698344	1			T1	1		T2	8131		T3	2
all_values[4]	auto[0]	auto[1]	168682	1			T42	3775		T75	662		T83	4393
all_values[4]	auto[1]	auto[0]	14	1			T208	1		T209	1		T210	2
all_values[4]	auto[1]	auto[1]	215	1			T42	3		T75	4		T83	1
all_values[5]	auto[0]	auto[0]	697655	1			T1	1		T2	8131		T3	2
all_values[5]	auto[0]	auto[1]	169325	1			T42	4443		T75	659		T83	4395
all_values[5]	auto[1]	auto[1]	275	1			T42	5		T75	7		T167	2
all_values[6]	auto[0]	auto[0]	173285	1			T1	1		T2	1246		T3	2
all_values[6]	auto[0]	auto[1]	21581	1			T42	711		T75	657		T83	110
all_values[6]	auto[1]	auto[0]	524382	1			T2	6885		T4	9		T6	1
all_values[6]	auto[1]	auto[1]	148007	1			T42	3737		T75	8		T83	4285
all_values[7]	auto[0]	auto[0]	675537	1			T1	1		T2	8013		T3	2
all_values[7]	auto[0]	auto[1]	160209	1			T42	4170		T75	490		T83	4138
all_values[7]	auto[1]	auto[0]	27097	1			T2	118		T4	53		T6	1
all_values[7]	auto[1]	auto[1]	4412	1			T42	276		T75	170		T83	256
all_values[8]	auto[0]	auto[0]	144734	1			T1	1		T2	43		T3	2
all_values[8]	auto[0]	auto[1]	14626	1			T42	588		T75	543		T83	65
all_values[8]	auto[1]	auto[0]	554586	1			T2	8088		T4	29		T6	1
all_values[8]	auto[1]	auto[1]	153309	1			T42	3860		T75	117		T83	4330
all_values[9]	auto[0]	auto[0]	167818	1			T1	1		T2	1125		T3	2
all_values[9]	auto[0]	auto[1]	17997	1			T42	762		T75	660		T83	98
all_values[9]	auto[1]	auto[0]	532055	1			T2	7006		T4	22		T6	1
all_values[9]	auto[1]	auto[1]	149385	1			T42	3686		T75	5		T83	4297
all_values[10]	auto[0]	auto[0]	701478	1			T1	1		T2	8131		T3	2
all_values[10]	auto[0]	auto[1]	165550	1			T42	4441		T75	661		T83	4393
all_values[10]	auto[1]	auto[1]	227	1			T42	7		T75	4		T83	1
all_values[11]	auto[0]	auto[0]	2913	1			T1	1		T2	9		T4	3
all_values[11]	auto[0]	auto[1]	588	1			T42	26		T75	9		T83	48
all_values[11]	auto[1]	auto[0]	721992	1			T2	8122		T3	2		T4	274
all_values[11]	auto[1]	auto[1]	141762	1			T42	4421		T75	655		T83	4347
all_values[12]	auto[0]	auto[0]	699351	1			T1	1		T2	8131		T3	2
all_values[12]	auto[0]	auto[1]	167695	1			T42	4442		T75	660		T83	4392
all_values[12]	auto[1]	auto[1]	209	1			T42	6		T75	6		T83	1
all_values[13]	auto[0]	auto[0]	719192	1			T1	1		T2	8131		T3	2
all_values[13]	auto[0]	auto[1]	147823	1			T42	4440		T75	663		T83	4394
all_values[13]	auto[1]	auto[1]	240	1			T42	8		T75	3		T83	1
all_values[14]	auto[0]	auto[0]	697666	1			T1	1		T2	8131		T3	2
all_values[14]	auto[0]	auto[1]	169335	1			T42	4444		T75	655		T83	4394
all_values[14]	auto[1]	auto[1]	254	1			T42	4		T75	11		T83	1