Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	867255	1			T1	1		T2	8131		T3	2
all_pins[1]	867255	1			T1	1		T2	8131		T3	2
all_pins[2]	867255	1			T1	1		T2	8131		T3	2
all_pins[3]	867255	1			T1	1		T2	8131		T3	2
all_pins[4]	867255	1			T1	1		T2	8131		T3	2
all_pins[5]	867255	1			T1	1		T2	8131		T3	2
all_pins[6]	867255	1			T1	1		T2	8131		T3	2
all_pins[7]	867255	1			T1	1		T2	8131		T3	2
all_pins[8]	867255	1			T1	1		T2	8131		T3	2
all_pins[9]	867255	1			T1	1		T2	8131		T3	2
all_pins[10]	867255	1			T1	1		T2	8131		T3	2
all_pins[11]	867255	1			T1	1		T2	8131		T3	2
all_pins[12]	867255	1			T1	1		T2	8131		T3	2
all_pins[13]	867255	1			T1	1		T2	8131		T3	2
all_pins[14]	867255	1			T1	1		T2	8131		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9278200	1			T1	15		T2	84622		T3	26
values[0x1]	3730625	1			T2	37343		T3	4		T4	666
transitions[0x0=>0x1]	3007721	1			T2	30093		T3	4		T4	648
transitions[0x1=>0x0]	3006684	1			T2	30092		T3	3		T4	647

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	94551	1			T1	1		T2	1029		T4	3
all_pins[0]	values[0x1]	772704	1			T2	7102		T3	2		T4	274
all_pins[0]	transitions[0x0=>0x1]	772161	1			T2	7102		T3	2		T4	274
all_pins[0]	transitions[0x1=>0x0]	71	1			T75	1		T56	1		T176	1
all_pins[1]	values[0x0]	866641	1			T1	1		T2	8131		T3	2
all_pins[1]	values[0x1]	614	1			T42	4		T149	1		T62	3
all_pins[1]	transitions[0x0=>0x1]	586	1			T42	3		T149	1		T62	3
all_pins[1]	transitions[0x1=>0x0]	80	1			T42	2		T75	1		T176	2
all_pins[2]	values[0x0]	867147	1			T1	1		T2	8131		T3	2
all_pins[2]	values[0x1]	108	1			T42	3		T75	1		T176	2
all_pins[2]	transitions[0x0=>0x1]	84	1			T42	3		T75	1		T176	2
all_pins[2]	transitions[0x1=>0x0]	89	1			T42	1		T75	3		T176	2
all_pins[3]	values[0x0]	867142	1			T1	1		T2	8131		T3	2
all_pins[3]	values[0x1]	113	1			T42	1		T75	3		T176	2
all_pins[3]	transitions[0x0=>0x1]	96	1			T42	1		T75	3		T176	2
all_pins[3]	transitions[0x1=>0x0]	95	1			T42	1		T83	1		T167	1
all_pins[4]	values[0x0]	867143	1			T1	1		T2	8131		T3	2
all_pins[4]	values[0x1]	112	1			T42	1		T83	1		T167	1
all_pins[4]	transitions[0x0=>0x1]	95	1			T42	1		T83	1		T167	1
all_pins[4]	transitions[0x1=>0x0]	111	1			T42	5		T75	4		T176	5
all_pins[5]	values[0x0]	867127	1			T1	1		T2	8131		T3	2
all_pins[5]	values[0x1]	128	1			T42	5		T75	4		T176	5
all_pins[5]	transitions[0x0=>0x1]	94	1			T42	3		T75	3		T176	3
all_pins[5]	transitions[0x1=>0x0]	672012	1			T2	6885		T4	9		T6	1
all_pins[6]	values[0x0]	195209	1			T1	1		T2	1246		T3	2
all_pins[6]	values[0x1]	672046	1			T2	6885		T4	9		T6	1
all_pins[6]	transitions[0x0=>0x1]	651920	1			T2	6781		T4	7		T40	5
all_pins[6]	transitions[0x1=>0x0]	14812	1			T2	35		T4	55		T60	45
all_pins[7]	values[0x0]	832317	1			T1	1		T2	7992		T3	2
all_pins[7]	values[0x1]	34938	1			T2	139		T4	57		T6	1
all_pins[7]	transitions[0x0=>0x1]	12207	1			T4	47		T60	45		T40	44
all_pins[7]	transitions[0x1=>0x0]	684889	1			T2	7949		T4	20		T60	1
all_pins[8]	values[0x0]	159635	1			T1	1		T2	43		T3	2
all_pins[8]	values[0x1]	707620	1			T2	8088		T4	30		T6	1
all_pins[8]	transitions[0x0=>0x1]	28422	1			T2	1081		T4	24		T60	1
all_pins[8]	transitions[0x1=>0x0]	2167	1			T4	16		T35	1		T58	1
all_pins[9]	values[0x0]	185890	1			T1	1		T2	1124		T3	2
all_pins[9]	values[0x1]	681365	1			T2	7007		T4	22		T6	1
all_pins[9]	transitions[0x0=>0x1]	681338	1			T2	7007		T4	22		T6	1
all_pins[9]	transitions[0x1=>0x0]	85	1			T42	4		T75	2		T83	1
all_pins[10]	values[0x0]	867143	1			T1	1		T2	8131		T3	2
all_pins[10]	values[0x1]	112	1			T42	5		T75	2		T83	1
all_pins[10]	transitions[0x0=>0x1]	76	1			T42	3		T75	2		T83	1
all_pins[10]	transitions[0x1=>0x0]	860377	1			T2	8122		T3	2		T4	274
all_pins[11]	values[0x0]	6842	1			T1	1		T2	9		T4	3
all_pins[11]	values[0x1]	860413	1			T2	8122		T3	2		T4	274
all_pins[11]	transitions[0x0=>0x1]	860380	1			T2	8122		T3	2		T4	274
all_pins[11]	transitions[0x1=>0x0]	76	1			T42	1		T75	2		T167	1
all_pins[12]	values[0x0]	867146	1			T1	1		T2	8131		T3	2
all_pins[12]	values[0x1]	109	1			T42	2		T75	4		T167	1
all_pins[12]	transitions[0x0=>0x1]	90	1			T42	1		T75	3		T167	1
all_pins[12]	transitions[0x1=>0x0]	96	1			T42	3		T75	2		T167	1
all_pins[13]	values[0x0]	867140	1			T1	1		T2	8131		T3	2
all_pins[13]	values[0x1]	115	1			T42	4		T75	3		T167	1
all_pins[13]	transitions[0x0=>0x1]	85	1			T42	1		T75	1		T167	1
all_pins[13]	transitions[0x1=>0x0]	98	1			T42	1		T75	4		T83	1
all_pins[14]	values[0x0]	867127	1			T1	1		T2	8131		T3	2
all_pins[14]	values[0x1]	128	1			T42	4		T75	6		T83	1
all_pins[14]	transitions[0x0=>0x1]	87	1			T42	3		T75	4		T83	1
all_pins[14]	transitions[0x1=>0x0]	771626	1			T2	7101		T3	1		T4	273