Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	524	1			T42	11		T75	11		T83	4
all_values[1]	524	1			T42	11		T75	11		T83	4
all_values[2]	524	1			T42	11		T75	11		T83	4
all_values[3]	524	1			T42	11		T75	11		T83	4
all_values[4]	524	1			T42	11		T75	11		T83	4
all_values[5]	524	1			T42	11		T75	11		T83	4
all_values[6]	524	1			T42	11		T75	11		T83	4
all_values[7]	524	1			T42	11		T75	11		T83	4
all_values[8]	524	1			T42	11		T75	11		T83	4
all_values[9]	524	1			T42	11		T75	11		T83	4
all_values[10]	524	1			T42	11		T75	11		T83	4
all_values[11]	524	1			T42	11		T75	11		T83	4
all_values[12]	524	1			T42	11		T75	11		T83	4
all_values[13]	524	1			T42	11		T75	11		T83	4
all_values[14]	524	1			T42	11		T75	11		T83	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4049

1

T42

89

T75

74

T83

26

auto[1]

3811

1

T42

76

T75

91

T83

34

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1195

1

T42

9

T75

19

T83

7

auto[1]

6665

1

T42

156

T75

146

T83

53

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4617

1

T42

96

T75

100

T83

34

auto[1]

3243

1

T42

69

T75

65

T83

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	43	1			T167	4		T231	1		T169	2
all_values[0]	auto[0]	auto[0]	auto[1]	97	1			T42	5		T75	3		T56	1
all_values[0]	auto[0]	auto[1]	auto[0]	36	1			T75	1		T83	2		T56	2
all_values[0]	auto[0]	auto[1]	auto[1]	130	1			T42	1		T75	3		T83	1
all_values[0]	auto[1]	auto[0]	auto[1]	114	1			T42	5		T56	2		T176	1
all_values[0]	auto[1]	auto[1]	auto[1]	104	1			T75	4		T83	1		T56	2
all_values[1]	auto[0]	auto[0]	auto[0]	39	1			T46	2		T238	1		T239	2
all_values[1]	auto[0]	auto[0]	auto[1]	119	1			T42	6		T75	4		T83	1
all_values[1]	auto[0]	auto[1]	auto[0]	46	1			T75	1		T167	4		T49	1
all_values[1]	auto[0]	auto[1]	auto[1]	122	1			T42	2		T75	1		T83	1
all_values[1]	auto[1]	auto[0]	auto[1]	100	1			T42	3		T75	4		T83	1
all_values[1]	auto[1]	auto[1]	auto[1]	98	1			T75	1		T83	1		T176	1
all_values[2]	auto[0]	auto[0]	auto[0]	44	1			T176	1		T46	1		T240	1
all_values[2]	auto[0]	auto[0]	auto[1]	105	1			T42	2		T75	4		T83	2
all_values[2]	auto[0]	auto[1]	auto[0]	42	1			T167	2		T56	1		T231	1
all_values[2]	auto[0]	auto[1]	auto[1]	117	1			T75	5		T176	6		T49	5
all_values[2]	auto[1]	auto[0]	auto[1]	110	1			T42	7		T75	1		T83	1
all_values[2]	auto[1]	auto[1]	auto[1]	106	1			T42	2		T75	1		T83	1
all_values[3]	auto[0]	auto[0]	auto[0]	49	1			T42	1		T167	2		T56	1
all_values[3]	auto[0]	auto[0]	auto[1]	124	1			T42	5		T75	1		T83	1
all_values[3]	auto[0]	auto[1]	auto[0]	35	1			T75	2		T56	3		T176	2
all_values[3]	auto[0]	auto[1]	auto[1]	97	1			T75	2		T49	2		T231	2
all_values[3]	auto[1]	auto[0]	auto[1]	119	1			T42	4		T75	2		T83	2
all_values[3]	auto[1]	auto[1]	auto[1]	100	1			T42	1		T75	4		T83	1
all_values[4]	auto[0]	auto[0]	auto[0]	40	1			T176	1		T169	1		T227	1
all_values[4]	auto[0]	auto[0]	auto[1]	118	1			T42	3		T75	4		T83	1
all_values[4]	auto[0]	auto[1]	auto[0]	44	1			T42	5		T83	1		T167	1
all_values[4]	auto[0]	auto[1]	auto[1]	107	1			T75	3		T83	1		T167	2
all_values[4]	auto[1]	auto[0]	auto[1]	124	1			T42	2		T75	4		T83	1
all_values[4]	auto[1]	auto[1]	auto[1]	91	1			T42	1		T167	1		T56	5
all_values[5]	auto[0]	auto[0]	auto[0]	43	1			T167	2		T46	2		T169	1
all_values[5]	auto[0]	auto[0]	auto[1]	120	1			T42	3		T75	3		T83	1
all_values[5]	auto[0]	auto[1]	auto[0]	21	1			T49	1		T46	1		T240	1
all_values[5]	auto[0]	auto[1]	auto[1]	112	1			T42	3		T75	3		T83	1
all_values[5]	auto[1]	auto[0]	auto[1]	126	1			T75	1		T83	1		T167	1
all_values[5]	auto[1]	auto[1]	auto[1]	102	1			T42	5		T75	4		T83	1
all_values[6]	auto[0]	auto[0]	auto[0]	38	1			T75	1		T176	1		T231	2
all_values[6]	auto[0]	auto[0]	auto[1]	110	1			T42	2		T75	3		T83	2
all_values[6]	auto[0]	auto[1]	auto[0]	31	1			T46	3		T169	2		T240	2
all_values[6]	auto[0]	auto[1]	auto[1]	126	1			T42	6		T75	4		T83	1
all_values[6]	auto[1]	auto[0]	auto[1]	111	1			T42	2		T75	1		T56	4
all_values[6]	auto[1]	auto[1]	auto[1]	108	1			T42	1		T75	2		T83	1
all_values[7]	auto[0]	auto[0]	auto[0]	42	1			T42	2		T75	1		T46	2
all_values[7]	auto[0]	auto[0]	auto[1]	116	1			T42	4		T75	1		T167	1
all_values[7]	auto[0]	auto[1]	auto[0]	51	1			T75	4		T83	1		T46	3
all_values[7]	auto[0]	auto[1]	auto[1]	110	1			T42	3		T75	1		T83	1
all_values[7]	auto[1]	auto[0]	auto[1]	106	1			T42	1		T75	2		T83	2
all_values[7]	auto[1]	auto[1]	auto[1]	99	1			T42	1		T75	2		T167	1
all_values[8]	auto[0]	auto[0]	auto[0]	33	1			T75	1		T176	1		T169	2
all_values[8]	auto[0]	auto[0]	auto[1]	125	1			T42	4		T75	1		T167	1
all_values[8]	auto[0]	auto[1]	auto[0]	37	1			T75	4		T176	2		T231	2
all_values[8]	auto[0]	auto[1]	auto[1]	101	1			T42	4		T75	3		T83	1
all_values[8]	auto[1]	auto[0]	auto[1]	135	1			T42	2		T75	1		T83	1
all_values[8]	auto[1]	auto[1]	auto[1]	93	1			T42	1		T75	1		T83	2
all_values[9]	auto[0]	auto[0]	auto[0]	38	1			T75	1		T56	1		T176	1
all_values[9]	auto[0]	auto[0]	auto[1]	121	1			T42	5		T75	3		T83	1
all_values[9]	auto[0]	auto[1]	auto[0]	46	1			T49	1		T46	1		T169	1
all_values[9]	auto[0]	auto[1]	auto[1]	107	1			T42	3		T75	2		T83	2
all_values[9]	auto[1]	auto[0]	auto[1]	109	1			T42	2		T75	3		T167	2
all_values[9]	auto[1]	auto[1]	auto[1]	103	1			T42	1		T75	2		T83	1
all_values[10]	auto[0]	auto[0]	auto[0]	33	1			T56	2		T231	3		T46	1
all_values[10]	auto[0]	auto[0]	auto[1]	100	1			T75	3		T167	1		T176	5
all_values[10]	auto[0]	auto[1]	auto[0]	37	1			T75	1		T83	1		T49	2
all_values[10]	auto[0]	auto[1]	auto[1]	127	1			T42	4		T75	3		T83	2
all_values[10]	auto[1]	auto[0]	auto[1]	119	1			T42	1		T75	2		T167	1
all_values[10]	auto[1]	auto[1]	auto[1]	108	1			T42	6		T75	2		T83	1
all_values[11]	auto[0]	auto[0]	auto[0]	35	1			T42	1		T75	1		T167	2
all_values[11]	auto[0]	auto[0]	auto[1]	113	1			T42	2		T75	3		T83	3
all_values[11]	auto[0]	auto[1]	auto[0]	38	1			T75	1		T167	2		T56	1
all_values[11]	auto[0]	auto[1]	auto[1]	116	1			T42	3		T75	2		T176	2
all_values[11]	auto[1]	auto[0]	auto[1]	123	1			T42	2		T75	2		T56	3
all_values[11]	auto[1]	auto[1]	auto[1]	99	1			T42	3		T75	2		T83	1
all_values[12]	auto[0]	auto[0]	auto[0]	51	1			T83	1		T167	1		T240	3
all_values[12]	auto[0]	auto[0]	auto[1]	104	1			T42	2		T75	2		T83	1
all_values[12]	auto[0]	auto[1]	auto[0]	47	1			T83	1		T56	1		T46	1
all_values[12]	auto[0]	auto[1]	auto[1]	113	1			T42	3		T75	3		T167	1
all_values[12]	auto[1]	auto[0]	auto[1]	104	1			T42	2		T75	2		T83	1
all_values[12]	auto[1]	auto[1]	auto[1]	105	1			T42	4		T75	4		T167	1
all_values[13]	auto[0]	auto[0]	auto[0]	47	1			T56	1		T178	4		T227	3
all_values[13]	auto[0]	auto[0]	auto[1]	111	1			T42	3		T75	3		T167	2
all_values[13]	auto[0]	auto[1]	auto[0]	37	1			T178	4		T227	2		T175	1
all_values[13]	auto[0]	auto[1]	auto[1]	119	1			T42	2		T75	2		T83	1
all_values[13]	auto[1]	auto[0]	auto[1]	110	1			T42	2		T75	1		T83	1
all_values[13]	auto[1]	auto[1]	auto[1]	100	1			T42	4		T75	5		T83	2
all_values[14]	auto[0]	auto[0]	auto[0]	41	1			T167	2		T56	1		T176	1
all_values[14]	auto[0]	auto[0]	auto[1]	121	1			T42	2		T75	2		T83	1
all_values[14]	auto[0]	auto[1]	auto[0]	31	1			T56	4		T49	2		T169	1
all_values[14]	auto[0]	auto[1]	auto[1]	114	1			T42	5		T75	4		T83	1
all_values[14]	auto[1]	auto[0]	auto[1]	119	1			T42	2		T75	3		T56	1
all_values[14]	auto[1]	auto[1]	auto[1]	98	1			T42	2		T75	2		T83	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal