Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.57 97.19 91.83 97.66 83.74 94.53 98.67 91.39


Total test records in report: 1453
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html
T1300 /workspace/coverage/default/25.i2c_target_smoke.4067485243 Apr 23 01:25:14 PM PDT 24 Apr 23 01:25:44 PM PDT 24 3241880873 ps
T1301 /workspace/coverage/default/47.i2c_host_smoke.1450027930 Apr 23 01:28:13 PM PDT 24 Apr 23 01:29:00 PM PDT 24 1025979302 ps
T1302 /workspace/coverage/default/29.i2c_alert_test.548954565 Apr 23 01:25:52 PM PDT 24 Apr 23 01:25:54 PM PDT 24 27032973 ps
T1303 /workspace/coverage/default/13.i2c_target_fifo_reset_acq.1019880609 Apr 23 01:23:18 PM PDT 24 Apr 23 01:24:38 PM PDT 24 10084749482 ps
T1304 /workspace/coverage/default/40.i2c_target_bad_addr.2548557237 Apr 23 01:27:23 PM PDT 24 Apr 23 01:27:26 PM PDT 24 759515513 ps
T1305 /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2377329367 Apr 23 01:26:00 PM PDT 24 Apr 23 01:26:07 PM PDT 24 1716875757 ps
T1306 /workspace/coverage/default/35.i2c_target_smoke.4101839370 Apr 23 01:26:40 PM PDT 24 Apr 23 01:27:16 PM PDT 24 3871248732 ps
T1307 /workspace/coverage/default/28.i2c_target_smoke.1427383847 Apr 23 01:25:40 PM PDT 24 Apr 23 01:26:29 PM PDT 24 1187467823 ps
T1308 /workspace/coverage/default/26.i2c_host_stress_all.3145758864 Apr 23 01:25:19 PM PDT 24 Apr 23 01:28:32 PM PDT 24 21331479781 ps
T1309 /workspace/coverage/default/32.i2c_host_fifo_reset_rx.1011505571 Apr 23 01:26:12 PM PDT 24 Apr 23 01:26:16 PM PDT 24 2026733144 ps
T1310 /workspace/coverage/default/1.i2c_target_intr_stress_wr.3054301735 Apr 23 01:21:33 PM PDT 24 Apr 23 01:29:09 PM PDT 24 23208155166 ps
T1311 /workspace/coverage/default/49.i2c_target_timeout.1573328996 Apr 23 01:28:31 PM PDT 24 Apr 23 01:28:37 PM PDT 24 4540200303 ps
T1312 /workspace/coverage/default/2.i2c_host_fifo_watermark.3328114065 Apr 23 01:21:36 PM PDT 24 Apr 23 01:23:21 PM PDT 24 4099164630 ps
T1313 /workspace/coverage/default/36.i2c_target_intr_smoke.77902051 Apr 23 01:26:47 PM PDT 24 Apr 23 01:26:52 PM PDT 24 1146374402 ps
T1314 /workspace/coverage/default/21.i2c_host_mode_toggle.301399671 Apr 23 01:24:37 PM PDT 24 Apr 23 01:25:41 PM PDT 24 2852719622 ps
T1315 /workspace/coverage/default/3.i2c_target_fifo_reset_acq.2710644259 Apr 23 01:21:43 PM PDT 24 Apr 23 01:21:54 PM PDT 24 10216645600 ps
T1316 /workspace/coverage/default/42.i2c_host_fifo_full.3150286539 Apr 23 01:27:35 PM PDT 24 Apr 23 01:28:20 PM PDT 24 10441781986 ps
T1317 /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.1607463877 Apr 23 01:28:29 PM PDT 24 Apr 23 01:28:30 PM PDT 24 79948028 ps
T1318 /workspace/coverage/default/21.i2c_target_bad_addr.666672560 Apr 23 01:24:37 PM PDT 24 Apr 23 01:24:41 PM PDT 24 3134736993 ps
T1319 /workspace/coverage/default/38.i2c_target_bad_addr.568481620 Apr 23 01:27:08 PM PDT 24 Apr 23 01:27:13 PM PDT 24 1258239180 ps
T1320 /workspace/coverage/default/12.i2c_host_override.1860147767 Apr 23 01:23:04 PM PDT 24 Apr 23 01:23:05 PM PDT 24 147962783 ps
T1321 /workspace/coverage/default/20.i2c_target_intr_smoke.33602084 Apr 23 01:24:30 PM PDT 24 Apr 23 01:24:36 PM PDT 24 915201810 ps
T1322 /workspace/coverage/default/18.i2c_target_intr_smoke.1489199493 Apr 23 01:24:09 PM PDT 24 Apr 23 01:24:14 PM PDT 24 15277077561 ps
T1323 /workspace/coverage/default/9.i2c_target_bad_addr.1286010873 Apr 23 01:22:46 PM PDT 24 Apr 23 01:22:52 PM PDT 24 890342961 ps
T1324 /workspace/coverage/default/20.i2c_target_smoke.3922730961 Apr 23 01:24:26 PM PDT 24 Apr 23 01:24:46 PM PDT 24 5279550930 ps
T1325 /workspace/coverage/default/29.i2c_host_fifo_full.2256315300 Apr 23 01:25:51 PM PDT 24 Apr 23 01:27:28 PM PDT 24 15755280769 ps
T1326 /workspace/coverage/default/36.i2c_host_fifo_reset_rx.1140826849 Apr 23 01:26:46 PM PDT 24 Apr 23 01:26:55 PM PDT 24 338997067 ps
T1327 /workspace/coverage/default/28.i2c_host_stretch_timeout.3429070215 Apr 23 01:25:37 PM PDT 24 Apr 23 01:26:14 PM PDT 24 1571699540 ps
T1328 /workspace/coverage/default/0.i2c_host_override.2148760939 Apr 23 01:21:14 PM PDT 24 Apr 23 01:21:15 PM PDT 24 29264305 ps
T1329 /workspace/coverage/default/22.i2c_host_error_intr.2663317315 Apr 23 01:24:41 PM PDT 24 Apr 23 01:24:43 PM PDT 24 217174901 ps
T1330 /workspace/coverage/default/34.i2c_alert_test.4114268428 Apr 23 01:26:36 PM PDT 24 Apr 23 01:26:37 PM PDT 24 18639284 ps
T1331 /workspace/coverage/default/15.i2c_host_fifo_watermark.89077746 Apr 23 01:23:36 PM PDT 24 Apr 23 01:26:31 PM PDT 24 37563605591 ps
T1332 /workspace/coverage/default/11.i2c_target_fifo_reset_tx.4279503757 Apr 23 01:23:01 PM PDT 24 Apr 23 01:23:14 PM PDT 24 10056275870 ps
T1333 /workspace/coverage/default/45.i2c_host_override.381408987 Apr 23 01:27:52 PM PDT 24 Apr 23 01:27:53 PM PDT 24 55296396 ps
T1334 /workspace/coverage/default/48.i2c_host_perf.789291758 Apr 23 01:28:20 PM PDT 24 Apr 23 01:30:41 PM PDT 24 13411388173 ps
T1335 /workspace/coverage/default/0.i2c_host_fifo_watermark.914090063 Apr 23 01:21:14 PM PDT 24 Apr 23 01:22:12 PM PDT 24 2624964078 ps
T1336 /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.913273194 Apr 23 01:21:28 PM PDT 24 Apr 23 01:21:33 PM PDT 24 497020654 ps
T1337 /workspace/coverage/default/12.i2c_target_intr_smoke.1232849551 Apr 23 01:23:13 PM PDT 24 Apr 23 01:23:17 PM PDT 24 3582202076 ps
T1338 /workspace/coverage/default/7.i2c_host_stretch_timeout.3621564279 Apr 23 01:22:23 PM PDT 24 Apr 23 01:22:30 PM PDT 24 758100452 ps
T1339 /workspace/coverage/default/16.i2c_host_smoke.722058485 Apr 23 01:23:44 PM PDT 24 Apr 23 01:24:04 PM PDT 24 4407421002 ps
T1340 /workspace/coverage/default/28.i2c_host_perf.2894769861 Apr 23 01:25:38 PM PDT 24 Apr 23 01:31:35 PM PDT 24 4684998742 ps
T1341 /workspace/coverage/default/5.i2c_host_fifo_watermark.3873813293 Apr 23 01:21:59 PM PDT 24 Apr 23 01:26:55 PM PDT 24 3841668292 ps
T1342 /workspace/coverage/default/42.i2c_host_smoke.3518454642 Apr 23 01:27:30 PM PDT 24 Apr 23 01:28:03 PM PDT 24 3063721312 ps
T1343 /workspace/coverage/default/6.i2c_host_fifo_reset_rx.893969945 Apr 23 01:22:12 PM PDT 24 Apr 23 01:22:18 PM PDT 24 175164766 ps
T1344 /workspace/coverage/default/22.i2c_host_perf.3515700177 Apr 23 01:24:41 PM PDT 24 Apr 23 01:27:59 PM PDT 24 5031771329 ps
T1345 /workspace/coverage/default/18.i2c_target_stress_wr.2815168642 Apr 23 01:24:10 PM PDT 24 Apr 23 01:25:38 PM PDT 24 41237038799 ps
T1346 /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.1954303949 Apr 23 01:26:49 PM PDT 24 Apr 23 01:26:51 PM PDT 24 119673631 ps
T1347 /workspace/coverage/default/19.i2c_host_perf.2603407539 Apr 23 01:24:15 PM PDT 24 Apr 23 01:52:20 PM PDT 24 97504445673 ps
T1348 /workspace/coverage/default/7.i2c_host_fifo_reset_rx.260275734 Apr 23 01:22:22 PM PDT 24 Apr 23 01:22:26 PM PDT 24 151972060 ps
T1349 /workspace/coverage/default/38.i2c_host_perf.3621465745 Apr 23 01:27:01 PM PDT 24 Apr 23 01:28:26 PM PDT 24 7918114422 ps
T1350 /workspace/coverage/default/36.i2c_target_stretch.1908029552 Apr 23 01:26:48 PM PDT 24 Apr 23 01:28:35 PM PDT 24 8166984592 ps
T1351 /workspace/coverage/default/18.i2c_target_fifo_reset_tx.32743102 Apr 23 01:24:12 PM PDT 24 Apr 23 01:24:25 PM PDT 24 10342267996 ps
T1352 /workspace/coverage/default/14.i2c_host_override.4068612863 Apr 23 01:23:26 PM PDT 24 Apr 23 01:23:27 PM PDT 24 22994652 ps
T1353 /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2683566478 Apr 23 01:24:56 PM PDT 24 Apr 23 01:25:29 PM PDT 24 10070659599 ps
T1354 /workspace/coverage/default/28.i2c_target_timeout.2145603321 Apr 23 01:25:44 PM PDT 24 Apr 23 01:25:52 PM PDT 24 1606040979 ps
T1355 /workspace/coverage/default/30.i2c_target_intr_smoke.98070491 Apr 23 01:25:59 PM PDT 24 Apr 23 01:26:04 PM PDT 24 2121459154 ps
T1356 /workspace/coverage/default/19.i2c_target_timeout.3560691477 Apr 23 01:24:22 PM PDT 24 Apr 23 01:24:30 PM PDT 24 1410719125 ps
T1357 /workspace/coverage/default/49.i2c_host_override.736097162 Apr 23 01:28:28 PM PDT 24 Apr 23 01:28:29 PM PDT 24 57374379 ps
T1358 /workspace/coverage/default/44.i2c_host_mode_toggle.3147500528 Apr 23 01:27:53 PM PDT 24 Apr 23 01:28:11 PM PDT 24 2299998958 ps
T1359 /workspace/coverage/default/39.i2c_target_smoke.3704337666 Apr 23 01:27:10 PM PDT 24 Apr 23 01:27:23 PM PDT 24 946384886 ps
T1360 /workspace/coverage/default/41.i2c_host_mode_toggle.877827862 Apr 23 01:27:34 PM PDT 24 Apr 23 01:27:59 PM PDT 24 5900877431 ps
T118 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1109372697 Apr 23 02:06:57 PM PDT 24 Apr 23 02:06:59 PM PDT 24 124155359 ps
T80 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2583462560 Apr 23 02:07:31 PM PDT 24 Apr 23 02:07:34 PM PDT 24 156783982 ps
T81 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.584910116 Apr 23 02:07:17 PM PDT 24 Apr 23 02:07:19 PM PDT 24 46921007 ps
T1361 /workspace/coverage/cover_reg_top/0.i2c_intr_test.510301838 Apr 23 02:06:45 PM PDT 24 Apr 23 02:06:46 PM PDT 24 24593898 ps
T82 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.260639156 Apr 23 02:07:05 PM PDT 24 Apr 23 02:07:06 PM PDT 24 31439807 ps
T1362 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2469499137 Apr 23 02:06:55 PM PDT 24 Apr 23 02:06:59 PM PDT 24 1803508425 ps
T150 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2411100664 Apr 23 02:07:32 PM PDT 24 Apr 23 02:07:33 PM PDT 24 23175737 ps
T119 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.4171381057 Apr 23 02:07:35 PM PDT 24 Apr 23 02:07:36 PM PDT 24 151817862 ps
T1363 /workspace/coverage/cover_reg_top/7.i2c_intr_test.2456354816 Apr 23 02:07:26 PM PDT 24 Apr 23 02:07:28 PM PDT 24 15394551 ps
T1364 /workspace/coverage/cover_reg_top/37.i2c_intr_test.3661139593 Apr 23 02:07:45 PM PDT 24 Apr 23 02:07:46 PM PDT 24 15501174 ps
T151 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.4115800310 Apr 23 02:07:39 PM PDT 24 Apr 23 02:07:40 PM PDT 24 27108035 ps
T163 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3172230329 Apr 23 02:07:18 PM PDT 24 Apr 23 02:07:19 PM PDT 24 96420401 ps
T1365 /workspace/coverage/cover_reg_top/47.i2c_intr_test.2581785739 Apr 23 02:07:50 PM PDT 24 Apr 23 02:07:51 PM PDT 24 16412282 ps
T1366 /workspace/coverage/cover_reg_top/33.i2c_intr_test.1093562276 Apr 23 02:07:45 PM PDT 24 Apr 23 02:07:46 PM PDT 24 29122922 ps
T239 /workspace/coverage/cover_reg_top/5.i2c_intr_test.4124706503 Apr 23 02:07:08 PM PDT 24 Apr 23 02:07:10 PM PDT 24 18351644 ps
T125 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.4129004614 Apr 23 02:07:09 PM PDT 24 Apr 23 02:07:11 PM PDT 24 89239751 ps
T152 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3387859407 Apr 23 02:07:36 PM PDT 24 Apr 23 02:07:37 PM PDT 24 46396194 ps
T130 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4098841565 Apr 23 02:06:50 PM PDT 24 Apr 23 02:06:52 PM PDT 24 64720682 ps
T126 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.872979300 Apr 23 02:07:18 PM PDT 24 Apr 23 02:07:21 PM PDT 24 513524930 ps
T1367 /workspace/coverage/cover_reg_top/34.i2c_intr_test.1275316699 Apr 23 02:07:44 PM PDT 24 Apr 23 02:07:45 PM PDT 24 32875021 ps
T1368 /workspace/coverage/cover_reg_top/44.i2c_intr_test.1852045109 Apr 23 02:07:48 PM PDT 24 Apr 23 02:07:49 PM PDT 24 44916671 ps
T1369 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2885778673 Apr 23 02:06:44 PM PDT 24 Apr 23 02:06:45 PM PDT 24 168476611 ps
T164 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3245459392 Apr 23 02:07:20 PM PDT 24 Apr 23 02:07:33 PM PDT 24 13560526863 ps
T147 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2741170132 Apr 23 02:07:19 PM PDT 24 Apr 23 02:07:20 PM PDT 24 85204695 ps
T127 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2378182199 Apr 23 02:07:39 PM PDT 24 Apr 23 02:07:43 PM PDT 24 135406903 ps
T165 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2043233718 Apr 23 02:07:28 PM PDT 24 Apr 23 02:07:29 PM PDT 24 382840426 ps
T1370 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1669490717 Apr 23 02:07:00 PM PDT 24 Apr 23 02:07:06 PM PDT 24 512986504 ps
T1371 /workspace/coverage/cover_reg_top/30.i2c_intr_test.3311369877 Apr 23 02:07:40 PM PDT 24 Apr 23 02:07:41 PM PDT 24 15409235 ps
T128 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3112842885 Apr 23 02:07:30 PM PDT 24 Apr 23 02:07:32 PM PDT 24 269084887 ps
T1372 /workspace/coverage/cover_reg_top/3.i2c_intr_test.350951559 Apr 23 02:07:01 PM PDT 24 Apr 23 02:07:02 PM PDT 24 54291053 ps
T131 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3761554528 Apr 23 02:07:31 PM PDT 24 Apr 23 02:07:33 PM PDT 24 216442302 ps
T1373 /workspace/coverage/cover_reg_top/38.i2c_intr_test.2558566596 Apr 23 02:07:45 PM PDT 24 Apr 23 02:07:46 PM PDT 24 31458862 ps
T129 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1954685427 Apr 23 02:07:22 PM PDT 24 Apr 23 02:07:24 PM PDT 24 320182608 ps
T148 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2403805794 Apr 23 02:06:59 PM PDT 24 Apr 23 02:07:01 PM PDT 24 82051879 ps
T1374 /workspace/coverage/cover_reg_top/24.i2c_intr_test.1351602462 Apr 23 02:07:38 PM PDT 24 Apr 23 02:07:39 PM PDT 24 16272638 ps
T1375 /workspace/coverage/cover_reg_top/4.i2c_intr_test.596830376 Apr 23 02:07:04 PM PDT 24 Apr 23 02:07:05 PM PDT 24 18458012 ps
T1376 /workspace/coverage/cover_reg_top/25.i2c_intr_test.1345512605 Apr 23 02:07:48 PM PDT 24 Apr 23 02:07:49 PM PDT 24 23717235 ps
T133 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2549049691 Apr 23 02:07:03 PM PDT 24 Apr 23 02:07:07 PM PDT 24 239345350 ps
T153 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3307258428 Apr 23 02:07:03 PM PDT 24 Apr 23 02:07:04 PM PDT 24 79339094 ps
T138 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3148433776 Apr 23 02:07:13 PM PDT 24 Apr 23 02:07:16 PM PDT 24 145402837 ps
T1377 /workspace/coverage/cover_reg_top/35.i2c_intr_test.3766859181 Apr 23 02:07:44 PM PDT 24 Apr 23 02:07:45 PM PDT 24 41478511 ps
T1378 /workspace/coverage/cover_reg_top/22.i2c_intr_test.2509747452 Apr 23 02:07:47 PM PDT 24 Apr 23 02:07:48 PM PDT 24 27725922 ps
T132 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2294496010 Apr 23 02:07:30 PM PDT 24 Apr 23 02:07:33 PM PDT 24 359025315 ps
T1379 /workspace/coverage/cover_reg_top/12.i2c_intr_test.216113684 Apr 23 02:07:26 PM PDT 24 Apr 23 02:07:27 PM PDT 24 52385983 ps
T1380 /workspace/coverage/cover_reg_top/15.i2c_intr_test.714998848 Apr 23 02:07:30 PM PDT 24 Apr 23 02:07:31 PM PDT 24 24320231 ps
T1381 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3617477990 Apr 23 02:07:23 PM PDT 24 Apr 23 02:07:24 PM PDT 24 87964468 ps
T136 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.447158083 Apr 23 02:07:33 PM PDT 24 Apr 23 02:07:36 PM PDT 24 417365185 ps
T1382 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.501701548 Apr 23 02:07:35 PM PDT 24 Apr 23 02:07:37 PM PDT 24 30389681 ps
T1383 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1424636423 Apr 23 02:07:23 PM PDT 24 Apr 23 02:07:25 PM PDT 24 1083801509 ps
T154 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.758424093 Apr 23 02:07:26 PM PDT 24 Apr 23 02:07:27 PM PDT 24 202458603 ps
T193 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3313406722 Apr 23 02:06:53 PM PDT 24 Apr 23 02:06:56 PM PDT 24 911437988 ps
T1384 /workspace/coverage/cover_reg_top/8.i2c_intr_test.985145159 Apr 23 02:07:27 PM PDT 24 Apr 23 02:07:28 PM PDT 24 19091873 ps
T1385 /workspace/coverage/cover_reg_top/48.i2c_intr_test.516892852 Apr 23 02:07:50 PM PDT 24 Apr 23 02:07:51 PM PDT 24 27674647 ps
T1386 /workspace/coverage/cover_reg_top/41.i2c_intr_test.934970745 Apr 23 02:07:47 PM PDT 24 Apr 23 02:07:49 PM PDT 24 15212340 ps
T1387 /workspace/coverage/cover_reg_top/49.i2c_intr_test.648457328 Apr 23 02:07:50 PM PDT 24 Apr 23 02:07:51 PM PDT 24 38461555 ps
T145 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2614775238 Apr 23 02:07:18 PM PDT 24 Apr 23 02:07:20 PM PDT 24 80097770 ps
T1388 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2832501888 Apr 23 02:07:30 PM PDT 24 Apr 23 02:07:32 PM PDT 24 96377162 ps
T166 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3658182733 Apr 23 02:07:23 PM PDT 24 Apr 23 02:07:24 PM PDT 24 62254107 ps
T1389 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1102561358 Apr 23 02:06:45 PM PDT 24 Apr 23 02:06:47 PM PDT 24 108714665 ps
T142 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1952062129 Apr 23 02:07:26 PM PDT 24 Apr 23 02:07:29 PM PDT 24 54467876 ps
T155 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1437439179 Apr 23 02:06:50 PM PDT 24 Apr 23 02:06:51 PM PDT 24 41156229 ps
T1390 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1123861783 Apr 23 02:07:26 PM PDT 24 Apr 23 02:07:30 PM PDT 24 55204183 ps
T160 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2212883473 Apr 23 02:07:13 PM PDT 24 Apr 23 02:07:17 PM PDT 24 138038618 ps
T1391 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2087401810 Apr 23 02:07:33 PM PDT 24 Apr 23 02:07:36 PM PDT 24 551082852 ps
T1392 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.326825295 Apr 23 02:06:53 PM PDT 24 Apr 23 02:06:56 PM PDT 24 191937433 ps
T1393 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2336374852 Apr 23 02:07:34 PM PDT 24 Apr 23 02:07:35 PM PDT 24 73040079 ps
T156 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.593986168 Apr 23 02:06:52 PM PDT 24 Apr 23 02:06:53 PM PDT 24 31117028 ps
T141 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1762726364 Apr 23 02:07:24 PM PDT 24 Apr 23 02:07:26 PM PDT 24 265583537 ps
T1394 /workspace/coverage/cover_reg_top/45.i2c_intr_test.2178337936 Apr 23 02:07:47 PM PDT 24 Apr 23 02:07:49 PM PDT 24 20726029 ps
T244 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1221378766 Apr 23 02:06:48 PM PDT 24 Apr 23 02:06:49 PM PDT 24 105748442 ps
T1395 /workspace/coverage/cover_reg_top/9.i2c_intr_test.1231385062 Apr 23 02:07:27 PM PDT 24 Apr 23 02:07:28 PM PDT 24 29705247 ps
T1396 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3519144925 Apr 23 02:07:04 PM PDT 24 Apr 23 02:07:05 PM PDT 24 41902624 ps
T1397 /workspace/coverage/cover_reg_top/46.i2c_intr_test.3994195687 Apr 23 02:07:48 PM PDT 24 Apr 23 02:07:49 PM PDT 24 49153429 ps
T1398 /workspace/coverage/cover_reg_top/26.i2c_intr_test.693788660 Apr 23 02:07:47 PM PDT 24 Apr 23 02:07:49 PM PDT 24 92446701 ps
T157 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1885129467 Apr 23 02:06:44 PM PDT 24 Apr 23 02:06:45 PM PDT 24 34150851 ps
T1399 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3082710477 Apr 23 02:07:22 PM PDT 24 Apr 23 02:07:24 PM PDT 24 179142955 ps
T1400 /workspace/coverage/cover_reg_top/19.i2c_intr_test.107578855 Apr 23 02:07:39 PM PDT 24 Apr 23 02:07:40 PM PDT 24 17269379 ps
T1401 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3878527072 Apr 23 02:07:25 PM PDT 24 Apr 23 02:07:26 PM PDT 24 47330407 ps
T1402 /workspace/coverage/cover_reg_top/28.i2c_intr_test.4215175337 Apr 23 02:07:42 PM PDT 24 Apr 23 02:07:44 PM PDT 24 45564907 ps
T1403 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3555846616 Apr 23 02:07:30 PM PDT 24 Apr 23 02:07:31 PM PDT 24 19709861 ps
T1404 /workspace/coverage/cover_reg_top/17.i2c_intr_test.3066833519 Apr 23 02:07:46 PM PDT 24 Apr 23 02:07:47 PM PDT 24 46633077 ps
T1405 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3368724490 Apr 23 02:07:27 PM PDT 24 Apr 23 02:07:28 PM PDT 24 88334621 ps
T1406 /workspace/coverage/cover_reg_top/1.i2c_intr_test.2772882962 Apr 23 02:06:51 PM PDT 24 Apr 23 02:06:52 PM PDT 24 18827673 ps
T134 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1909026146 Apr 23 02:07:13 PM PDT 24 Apr 23 02:07:17 PM PDT 24 111237130 ps
T1407 /workspace/coverage/cover_reg_top/27.i2c_intr_test.2263158170 Apr 23 02:07:42 PM PDT 24 Apr 23 02:07:43 PM PDT 24 19919279 ps
T1408 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1508383301 Apr 23 02:06:54 PM PDT 24 Apr 23 02:06:55 PM PDT 24 61025864 ps
T1409 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1320478351 Apr 23 02:07:13 PM PDT 24 Apr 23 02:07:15 PM PDT 24 49051984 ps
T137 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1228649789 Apr 23 02:07:23 PM PDT 24 Apr 23 02:07:26 PM PDT 24 127920067 ps
T1410 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2039867284 Apr 23 02:07:47 PM PDT 24 Apr 23 02:07:48 PM PDT 24 28821379 ps
T1411 /workspace/coverage/cover_reg_top/11.i2c_intr_test.799925217 Apr 23 02:07:23 PM PDT 24 Apr 23 02:07:24 PM PDT 24 46316613 ps
T1412 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2097734649 Apr 23 02:07:25 PM PDT 24 Apr 23 02:07:27 PM PDT 24 30034695 ps
T1413 /workspace/coverage/cover_reg_top/36.i2c_intr_test.4057676329 Apr 23 02:07:44 PM PDT 24 Apr 23 02:07:45 PM PDT 24 57496308 ps
T1414 /workspace/coverage/cover_reg_top/32.i2c_intr_test.2042208554 Apr 23 02:07:47 PM PDT 24 Apr 23 02:07:49 PM PDT 24 15855466 ps
T1415 /workspace/coverage/cover_reg_top/29.i2c_intr_test.3465145029 Apr 23 02:07:53 PM PDT 24 Apr 23 02:07:54 PM PDT 24 54827673 ps
T158 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3432535623 Apr 23 02:06:55 PM PDT 24 Apr 23 02:06:58 PM PDT 24 429746659 ps
T1416 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.813502139 Apr 23 02:07:34 PM PDT 24 Apr 23 02:07:36 PM PDT 24 262803093 ps
T1417 /workspace/coverage/cover_reg_top/43.i2c_intr_test.594599540 Apr 23 02:07:47 PM PDT 24 Apr 23 02:07:49 PM PDT 24 24876434 ps
T1418 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2002629115 Apr 23 02:06:51 PM PDT 24 Apr 23 02:06:52 PM PDT 24 71784302 ps
T1419 /workspace/coverage/cover_reg_top/20.i2c_intr_test.2679689987 Apr 23 02:07:40 PM PDT 24 Apr 23 02:07:41 PM PDT 24 36644884 ps
T1420 /workspace/coverage/cover_reg_top/42.i2c_intr_test.4074475575 Apr 23 02:07:48 PM PDT 24 Apr 23 02:07:50 PM PDT 24 17996772 ps
T1421 /workspace/coverage/cover_reg_top/10.i2c_intr_test.1153079289 Apr 23 02:07:24 PM PDT 24 Apr 23 02:07:26 PM PDT 24 36445569 ps
T159 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2161595224 Apr 23 02:07:05 PM PDT 24 Apr 23 02:07:06 PM PDT 24 19254009 ps
T1422 /workspace/coverage/cover_reg_top/6.i2c_intr_test.2522357410 Apr 23 02:07:13 PM PDT 24 Apr 23 02:07:16 PM PDT 24 48388991 ps
T161 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3605598885 Apr 23 02:07:26 PM PDT 24 Apr 23 02:07:28 PM PDT 24 42375026 ps
T1423 /workspace/coverage/cover_reg_top/40.i2c_intr_test.22165186 Apr 23 02:07:48 PM PDT 24 Apr 23 02:07:49 PM PDT 24 30642867 ps
T1424 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3784020225 Apr 23 02:07:37 PM PDT 24 Apr 23 02:07:39 PM PDT 24 42104086 ps
T139 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.819696915 Apr 23 02:07:35 PM PDT 24 Apr 23 02:07:37 PM PDT 24 137026859 ps
T1425 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2764225406 Apr 23 02:07:38 PM PDT 24 Apr 23 02:07:39 PM PDT 24 25428717 ps
T1426 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1089713739 Apr 23 02:06:52 PM PDT 24 Apr 23 02:06:53 PM PDT 24 38100131 ps
T1427 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1487207545 Apr 23 02:07:04 PM PDT 24 Apr 23 02:07:06 PM PDT 24 511027869 ps
T140 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.909801271 Apr 23 02:06:45 PM PDT 24 Apr 23 02:06:47 PM PDT 24 87934173 ps
T1428 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.264801770 Apr 23 02:07:30 PM PDT 24 Apr 23 02:07:32 PM PDT 24 271268919 ps
T1429 /workspace/coverage/cover_reg_top/23.i2c_intr_test.1512396453 Apr 23 02:07:40 PM PDT 24 Apr 23 02:07:41 PM PDT 24 22424208 ps
T1430 /workspace/coverage/cover_reg_top/21.i2c_intr_test.550108710 Apr 23 02:07:47 PM PDT 24 Apr 23 02:07:49 PM PDT 24 73716488 ps
T1431 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3915186111 Apr 23 02:07:17 PM PDT 24 Apr 23 02:07:19 PM PDT 24 47248210 ps
T1432 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.971145161 Apr 23 02:07:12 PM PDT 24 Apr 23 02:07:14 PM PDT 24 58651085 ps
T1433 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1551496796 Apr 23 02:07:38 PM PDT 24 Apr 23 02:07:39 PM PDT 24 359502801 ps
T1434 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2483901 Apr 23 02:07:21 PM PDT 24 Apr 23 02:07:23 PM PDT 24 37794997 ps
T1435 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2279288358 Apr 23 02:07:32 PM PDT 24 Apr 23 02:07:33 PM PDT 24 25319118 ps
T1436 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3829906405 Apr 23 02:07:29 PM PDT 24 Apr 23 02:07:32 PM PDT 24 138291202 ps
T1437 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1886967619 Apr 23 02:07:34 PM PDT 24 Apr 23 02:07:35 PM PDT 24 19756186 ps
T143 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.4278058053 Apr 23 02:07:39 PM PDT 24 Apr 23 02:07:41 PM PDT 24 84817886 ps
T1438 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2736227242 Apr 23 02:07:32 PM PDT 24 Apr 23 02:07:34 PM PDT 24 29910229 ps
T135 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3902833976 Apr 23 02:06:49 PM PDT 24 Apr 23 02:06:51 PM PDT 24 93205409 ps
T1439 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.119944725 Apr 23 02:07:27 PM PDT 24 Apr 23 02:07:30 PM PDT 24 155928386 ps
T1440 /workspace/coverage/cover_reg_top/13.i2c_intr_test.2630209233 Apr 23 02:07:27 PM PDT 24 Apr 23 02:07:28 PM PDT 24 43191209 ps
T1441 /workspace/coverage/cover_reg_top/18.i2c_intr_test.2945920832 Apr 23 02:07:35 PM PDT 24 Apr 23 02:07:36 PM PDT 24 16827169 ps
T1442 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1822849878 Apr 23 02:07:36 PM PDT 24 Apr 23 02:07:37 PM PDT 24 23986333 ps
T211 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1848078954 Apr 23 02:07:32 PM PDT 24 Apr 23 02:07:34 PM PDT 24 221261966 ps
T1443 /workspace/coverage/cover_reg_top/39.i2c_intr_test.5131859 Apr 23 02:07:49 PM PDT 24 Apr 23 02:07:51 PM PDT 24 42607757 ps
T1444 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.260164319 Apr 23 02:06:44 PM PDT 24 Apr 23 02:06:46 PM PDT 24 64755108 ps
T1445 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2181640967 Apr 23 02:07:30 PM PDT 24 Apr 23 02:07:31 PM PDT 24 177651636 ps
T1446 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3837992922 Apr 23 02:06:45 PM PDT 24 Apr 23 02:06:51 PM PDT 24 5195742260 ps
T1447 /workspace/coverage/cover_reg_top/31.i2c_intr_test.981744532 Apr 23 02:07:44 PM PDT 24 Apr 23 02:07:45 PM PDT 24 24287959 ps
T1448 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2283163188 Apr 23 02:07:36 PM PDT 24 Apr 23 02:07:38 PM PDT 24 86518772 ps
T1449 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.4154703409 Apr 23 02:07:09 PM PDT 24 Apr 23 02:07:10 PM PDT 24 156684203 ps
T1450 /workspace/coverage/cover_reg_top/16.i2c_intr_test.2069476270 Apr 23 02:07:32 PM PDT 24 Apr 23 02:07:34 PM PDT 24 15956660 ps
T1451 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3373602460 Apr 23 02:07:09 PM PDT 24 Apr 23 02:07:12 PM PDT 24 404794712 ps
T162 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3937768233 Apr 23 02:06:53 PM PDT 24 Apr 23 02:06:56 PM PDT 24 101162682 ps
T144 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2455430046 Apr 23 02:06:50 PM PDT 24 Apr 23 02:06:53 PM PDT 24 450898266 ps
T1452 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.4260056616 Apr 23 02:07:27 PM PDT 24 Apr 23 02:07:29 PM PDT 24 32741608 ps
T1453 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3414168360 Apr 23 02:07:10 PM PDT 24 Apr 23 02:07:13 PM PDT 24 132839464 ps

Test location /workspace/coverage/default/28.i2c_host_smoke.3605509650
Short name T4
Test name
Test status
Simulation time 3279950378 ps
CPU time 29.88 seconds
Started Apr 23 01:25:36 PM PDT 24
Finished Apr 23 01:26:06 PM PDT 24
Peak memory 350864 kb
Host smart-b74e24b3-ae8b-40a5-8792-935233b0414f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605509650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.3605509650
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.1377791119
Short name T14
Test name
Test status
Simulation time 10026360524 ps
CPU time 74.77 seconds
Started Apr 23 01:25:14 PM PDT 24
Finished Apr 23 01:26:30 PM PDT 24
Peak memory 470220 kb
Host smart-b14a7528-6712-4e7a-9a8c-af7cc392c32a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377791119 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.1377791119
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.37547807
Short name T42
Test name
Test status
Simulation time 60397882338 ps
CPU time 285.43 seconds
Started Apr 23 01:21:44 PM PDT 24
Finished Apr 23 01:26:30 PM PDT 24
Peak memory 810316 kb
Host smart-ea62de33-06d6-4e64-9626-ede3c4ad4553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37547807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.37547807
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.3946969670
Short name T26
Test name
Test status
Simulation time 6200629623 ps
CPU time 8.83 seconds
Started Apr 23 01:21:33 PM PDT 24
Finished Apr 23 01:21:43 PM PDT 24
Peak memory 203996 kb
Host smart-e077b9af-fc34-4159-bdd1-75c58c68165f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946969670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.3946969670
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2583462560
Short name T80
Test name
Test status
Simulation time 156783982 ps
CPU time 2.26 seconds
Started Apr 23 02:07:31 PM PDT 24
Finished Apr 23 02:07:34 PM PDT 24
Peak memory 203768 kb
Host smart-f06e593c-f787-4ee1-9fa8-10d8bdcf1d10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583462560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2583462560
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.1544426852
Short name T75
Test name
Test status
Simulation time 88931546006 ps
CPU time 531.69 seconds
Started Apr 23 01:23:26 PM PDT 24
Finished Apr 23 01:32:19 PM PDT 24
Peak memory 2064344 kb
Host smart-b89a130b-9455-4589-acbc-c4e57a80391e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544426852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.1544426852
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_override.1088301131
Short name T8
Test name
Test status
Simulation time 27562350 ps
CPU time 0.64 seconds
Started Apr 23 01:24:48 PM PDT 24
Finished Apr 23 01:24:49 PM PDT 24
Peak memory 203328 kb
Host smart-a89deb6d-a258-4a61-a882-235f51d12b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088301131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1088301131
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.3321026584
Short name T338
Test name
Test status
Simulation time 516091642 ps
CPU time 19.89 seconds
Started Apr 23 01:21:42 PM PDT 24
Finished Apr 23 01:22:02 PM PDT 24
Peak memory 203644 kb
Host smart-8942d92b-6e8c-42ad-b114-3dd71c0d024f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321026584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.3321026584
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.2074537959
Short name T255
Test name
Test status
Simulation time 21146999202 ps
CPU time 153.55 seconds
Started Apr 23 01:23:58 PM PDT 24
Finished Apr 23 01:26:33 PM PDT 24
Peak memory 1804800 kb
Host smart-2461209f-6b4a-4e13-994d-a35f0a5c8c09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074537959 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.2074537959
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.3761554528
Short name T131
Test name
Test status
Simulation time 216442302 ps
CPU time 2.2 seconds
Started Apr 23 02:07:31 PM PDT 24
Finished Apr 23 02:07:33 PM PDT 24
Peak memory 203844 kb
Host smart-3b391595-098e-40b5-a4b6-70eb1d6cf856
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761554528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3761554528
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.2943644861
Short name T10
Test name
Test status
Simulation time 2570835384 ps
CPU time 3.45 seconds
Started Apr 23 01:24:56 PM PDT 24
Finished Apr 23 01:24:59 PM PDT 24
Peak memory 203840 kb
Host smart-1dfd0de9-2050-4fd5-8ddf-19626a1ff582
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943644861 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.2943644861
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.2916379241
Short name T120
Test name
Test status
Simulation time 275244505 ps
CPU time 0.97 seconds
Started Apr 23 01:21:27 PM PDT 24
Finished Apr 23 01:21:29 PM PDT 24
Peak memory 222072 kb
Host smart-fb204a78-aff1-410f-80b1-c8ea2ecdbe0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916379241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.2916379241
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.2117383077
Short name T172
Test name
Test status
Simulation time 44541593523 ps
CPU time 519.63 seconds
Started Apr 23 01:23:16 PM PDT 24
Finished Apr 23 01:31:56 PM PDT 24
Peak memory 1956896 kb
Host smart-94726d21-82b6-4308-85c4-3b5ec96c0e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117383077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.2117383077
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1437439179
Short name T155
Test name
Test status
Simulation time 41156229 ps
CPU time 0.68 seconds
Started Apr 23 02:06:50 PM PDT 24
Finished Apr 23 02:06:51 PM PDT 24
Peak memory 203696 kb
Host smart-64cdc8ee-a6ec-4195-a9fa-09aa6eff5bb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437439179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.1437439179
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.579297658
Short name T204
Test name
Test status
Simulation time 136544777 ps
CPU time 1.05 seconds
Started Apr 23 01:22:49 PM PDT 24
Finished Apr 23 01:22:50 PM PDT 24
Peak memory 203596 kb
Host smart-bed51130-df1f-4023-a46f-bf50784586b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579297658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fm
t.579297658
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.1617840159
Short name T46
Test name
Test status
Simulation time 14457168744 ps
CPU time 190.98 seconds
Started Apr 23 01:27:02 PM PDT 24
Finished Apr 23 01:30:14 PM PDT 24
Peak memory 474924 kb
Host smart-73b26bee-f88e-414b-8018-cc67f389456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617840159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.1617840159
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.4147161437
Short name T747
Test name
Test status
Simulation time 4999226636 ps
CPU time 247 seconds
Started Apr 23 01:24:31 PM PDT 24
Finished Apr 23 01:28:39 PM PDT 24
Peak memory 1376384 kb
Host smart-528cb851-d8c3-4482-81e6-86fc60df1b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147161437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.4147161437
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.3091396002
Short name T493
Test name
Test status
Simulation time 22039745222 ps
CPU time 24.04 seconds
Started Apr 23 01:25:35 PM PDT 24
Finished Apr 23 01:26:00 PM PDT 24
Peak memory 244700 kb
Host smart-c267b30b-9257-4306-870b-d1423f88bb38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091396002 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_stress_all.3091396002
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.1506442980
Short name T66
Test name
Test status
Simulation time 1401491560 ps
CPU time 23.74 seconds
Started Apr 23 01:25:00 PM PDT 24
Finished Apr 23 01:25:25 PM PDT 24
Peak memory 297400 kb
Host smart-d3870e60-6d81-43f2-8b22-754451c16efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506442980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.1506442980
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_alert_test.1387481582
Short name T298
Test name
Test status
Simulation time 32707566 ps
CPU time 0.61 seconds
Started Apr 23 01:21:33 PM PDT 24
Finished Apr 23 01:21:34 PM PDT 24
Peak memory 203388 kb
Host smart-fdeb365f-7b7a-4f61-9855-ab11aef1e1a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387481582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.1387481582
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.2659190132
Short name T203
Test name
Test status
Simulation time 673771788 ps
CPU time 8.55 seconds
Started Apr 23 01:23:06 PM PDT 24
Finished Apr 23 01:23:15 PM PDT 24
Peak memory 229276 kb
Host smart-64c5f1c2-50ee-43d4-901b-d616c7496467
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659190132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.2659190132
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.1041860888
Short name T242
Test name
Test status
Simulation time 10086079916 ps
CPU time 32.98 seconds
Started Apr 23 01:23:57 PM PDT 24
Finished Apr 23 01:24:31 PM PDT 24
Peak memory 370744 kb
Host smart-4e76425a-b411-4507-9470-4369090ac1bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041860888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.1041860888
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.3551242801
Short name T112
Test name
Test status
Simulation time 11694451381 ps
CPU time 623.16 seconds
Started Apr 23 01:27:49 PM PDT 24
Finished Apr 23 01:38:13 PM PDT 24
Peak memory 1902460 kb
Host smart-e1dcf260-b786-4aac-8614-276d7efea6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551242801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.3551242801
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.1138736343
Short name T50
Test name
Test status
Simulation time 65725826842 ps
CPU time 2658.38 seconds
Started Apr 23 01:26:27 PM PDT 24
Finished Apr 23 02:10:46 PM PDT 24
Peak memory 3685440 kb
Host smart-3f0675b5-6b3f-4f1b-9ae0-9d8be10e4e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138736343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.1138736343
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.3278719033
Short name T28
Test name
Test status
Simulation time 1884814634 ps
CPU time 2.84 seconds
Started Apr 23 01:24:22 PM PDT 24
Finished Apr 23 01:24:25 PM PDT 24
Peak memory 203676 kb
Host smart-2e866bd6-b311-469c-aba2-f85452011a2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278719033 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.3278719033
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1952062129
Short name T142
Test name
Test status
Simulation time 54467876 ps
CPU time 1.44 seconds
Started Apr 23 02:07:26 PM PDT 24
Finished Apr 23 02:07:29 PM PDT 24
Peak memory 203828 kb
Host smart-ccd0852a-4f2f-4a63-98c5-2e03501c536f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952062129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.1952062129
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.1852299076
Short name T71
Test name
Test status
Simulation time 17375670303 ps
CPU time 244.42 seconds
Started Apr 23 01:22:42 PM PDT 24
Finished Apr 23 01:26:47 PM PDT 24
Peak memory 803052 kb
Host smart-7bfd4d38-09ef-4a89-bb31-0e8bff29ff7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852299076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.1852299076
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.3889580883
Short name T53
Test name
Test status
Simulation time 10073337604 ps
CPU time 75.64 seconds
Started Apr 23 01:25:43 PM PDT 24
Finished Apr 23 01:27:00 PM PDT 24
Peak memory 509256 kb
Host smart-5efff536-4b33-4571-85de-617ea9c123cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889580883 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.3889580883
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3658182733
Short name T166
Test name
Test status
Simulation time 62254107 ps
CPU time 0.68 seconds
Started Apr 23 02:07:23 PM PDT 24
Finished Apr 23 02:07:24 PM PDT 24
Peak memory 203644 kb
Host smart-1bb6c23a-0786-476e-b48b-85485a1610c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658182733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3658182733
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2060338610
Short name T200
Test name
Test status
Simulation time 10097317063 ps
CPU time 68.26 seconds
Started Apr 23 01:22:55 PM PDT 24
Finished Apr 23 01:24:04 PM PDT 24
Peak memory 438956 kb
Host smart-267401b6-f338-4822-a07d-5e06f95aac3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060338610 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2060338610
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.1224222694
Short name T2
Test name
Test status
Simulation time 724288287 ps
CPU time 16.95 seconds
Started Apr 23 01:24:16 PM PDT 24
Finished Apr 23 01:24:33 PM PDT 24
Peak memory 211968 kb
Host smart-b323f10b-1cdd-4727-9f54-96737accd3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224222694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.1224222694
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.1057345459
Short name T215
Test name
Test status
Simulation time 325701235 ps
CPU time 1.51 seconds
Started Apr 23 01:24:53 PM PDT 24
Finished Apr 23 01:24:55 PM PDT 24
Peak memory 211992 kb
Host smart-41e89a65-591d-4f29-8268-80e9183f50c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057345459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.1057345459
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.41656634
Short name T207
Test name
Test status
Simulation time 155381378 ps
CPU time 1.17 seconds
Started Apr 23 01:27:16 PM PDT 24
Finished Apr 23 01:27:17 PM PDT 24
Peak memory 203652 kb
Host smart-8f5e0e4f-87a2-49bc-bd6a-316c5de68694
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41656634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fmt
.41656634
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1123861783
Short name T1390
Test name
Test status
Simulation time 55204183 ps
CPU time 2.49 seconds
Started Apr 23 02:07:26 PM PDT 24
Finished Apr 23 02:07:30 PM PDT 24
Peak memory 203812 kb
Host smart-bcb2310c-6b8c-4d32-88e3-a37f83bf7ce4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123861783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1123861783
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3902833976
Short name T135
Test name
Test status
Simulation time 93205409 ps
CPU time 1.42 seconds
Started Apr 23 02:06:49 PM PDT 24
Finished Apr 23 02:06:51 PM PDT 24
Peak memory 203848 kb
Host smart-2a2c8eba-f75c-4267-902f-4ebdd6d35f6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902833976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.3902833976
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1221378766
Short name T244
Test name
Test status
Simulation time 105748442 ps
CPU time 0.66 seconds
Started Apr 23 02:06:48 PM PDT 24
Finished Apr 23 02:06:49 PM PDT 24
Peak memory 203664 kb
Host smart-2698d15d-57a9-42e4-9fef-d3f3addab228
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221378766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1221378766
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.2232069375
Short name T229
Test name
Test status
Simulation time 15920359976 ps
CPU time 958.73 seconds
Started Apr 23 01:21:17 PM PDT 24
Finished Apr 23 01:37:16 PM PDT 24
Peak memory 1597808 kb
Host smart-763ec0e4-1099-4ecd-9b85-49a367833cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232069375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.2232069375
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.2813188782
Short name T284
Test name
Test status
Simulation time 68606701 ps
CPU time 1.34 seconds
Started Apr 23 01:21:30 PM PDT 24
Finished Apr 23 01:21:32 PM PDT 24
Peak memory 211992 kb
Host smart-1b4b82d6-5f9a-4547-9d62-8dd24c10907c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813188782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.2813188782
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.2335961919
Short name T228
Test name
Test status
Simulation time 46992640067 ps
CPU time 435.33 seconds
Started Apr 23 01:21:28 PM PDT 24
Finished Apr 23 01:28:43 PM PDT 24
Peak memory 1682664 kb
Host smart-8653b1b6-2748-422e-a28d-5ea854f9f547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335961919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.2335961919
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.2593635878
Short name T31
Test name
Test status
Simulation time 1412489503 ps
CPU time 2.39 seconds
Started Apr 23 01:23:10 PM PDT 24
Finished Apr 23 01:23:13 PM PDT 24
Peak memory 203620 kb
Host smart-a543ccca-8fa4-47cb-a878-266931034641
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593635878 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.2593635878
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.3328114065
Short name T1312
Test name
Test status
Simulation time 4099164630 ps
CPU time 104.2 seconds
Started Apr 23 01:21:36 PM PDT 24
Finished Apr 23 01:23:21 PM PDT 24
Peak memory 1193556 kb
Host smart-4ece5aeb-946a-46d4-bada-0e7f3cbb5c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328114065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.3328114065
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.1084389986
Short name T208
Test name
Test status
Simulation time 446295048 ps
CPU time 7.14 seconds
Started Apr 23 01:25:08 PM PDT 24
Finished Apr 23 01:25:16 PM PDT 24
Peak memory 203624 kb
Host smart-9a378fda-8a9b-4bc6-8d76-192d1bc3565a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084389986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.1084389986
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.3547177480
Short name T236
Test name
Test status
Simulation time 35732557037 ps
CPU time 277.12 seconds
Started Apr 23 01:25:54 PM PDT 24
Finished Apr 23 01:30:32 PM PDT 24
Peak memory 1362752 kb
Host smart-16593725-a4c3-4740-afc3-4cf9df92256a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547177480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.3547177480
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.4288895110
Short name T1217
Test name
Test status
Simulation time 13350073226 ps
CPU time 739.07 seconds
Started Apr 23 01:21:51 PM PDT 24
Finished Apr 23 01:34:11 PM PDT 24
Peak memory 3382716 kb
Host smart-d6db7823-7a7b-451f-998a-d4e3e6321c9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288895110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.4288895110
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.401439345
Short name T230
Test name
Test status
Simulation time 858000846 ps
CPU time 39.06 seconds
Started Apr 23 01:27:38 PM PDT 24
Finished Apr 23 01:28:18 PM PDT 24
Peak memory 211956 kb
Host smart-ba701d7c-8a3f-4948-b879-7acf044e7e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401439345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.401439345
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1228649789
Short name T137
Test name
Test status
Simulation time 127920067 ps
CPU time 2.37 seconds
Started Apr 23 02:07:23 PM PDT 24
Finished Apr 23 02:07:26 PM PDT 24
Peak memory 203860 kb
Host smart-7dba7bbc-1983-4dbf-b7d9-72778dbadb24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228649789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1228649789
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.3430443662
Short name T246
Test name
Test status
Simulation time 12685886587 ps
CPU time 25.91 seconds
Started Apr 23 01:23:28 PM PDT 24
Finished Apr 23 01:23:55 PM PDT 24
Peak memory 203756 kb
Host smart-2648f95d-32a4-4e39-a9bb-d9c5c30b638a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430443662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.3430443662
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2455430046
Short name T144
Test name
Test status
Simulation time 450898266 ps
CPU time 2.28 seconds
Started Apr 23 02:06:50 PM PDT 24
Finished Apr 23 02:06:53 PM PDT 24
Peak memory 203856 kb
Host smart-4617c507-4464-472c-b9b8-045ad3e63ea5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455430046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2455430046
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.1523648579
Short name T62
Test name
Test status
Simulation time 3332417575 ps
CPU time 23.84 seconds
Started Apr 23 01:21:26 PM PDT 24
Finished Apr 23 01:21:50 PM PDT 24
Peak memory 330928 kb
Host smart-82e3379b-8708-4d2b-925a-8f1889bf0bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523648579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.1523648579
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.260164319
Short name T1444
Test name
Test status
Simulation time 64755108 ps
CPU time 1.31 seconds
Started Apr 23 02:06:44 PM PDT 24
Finished Apr 23 02:06:46 PM PDT 24
Peak memory 203760 kb
Host smart-73865adc-0b47-4c0d-96c6-4ad73a2e4322
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260164319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.260164319
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3837992922
Short name T1446
Test name
Test status
Simulation time 5195742260 ps
CPU time 6.23 seconds
Started Apr 23 02:06:45 PM PDT 24
Finished Apr 23 02:06:51 PM PDT 24
Peak memory 203924 kb
Host smart-146c3aee-a7db-477c-842b-0b1c496d682b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837992922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.3837992922
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2885778673
Short name T1369
Test name
Test status
Simulation time 168476611 ps
CPU time 0.71 seconds
Started Apr 23 02:06:44 PM PDT 24
Finished Apr 23 02:06:45 PM PDT 24
Peak memory 203628 kb
Host smart-773c8a06-b344-481f-83f1-35e6ce8ae96e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885778673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2885778673
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2002629115
Short name T1418
Test name
Test status
Simulation time 71784302 ps
CPU time 0.81 seconds
Started Apr 23 02:06:51 PM PDT 24
Finished Apr 23 02:06:52 PM PDT 24
Peak memory 203656 kb
Host smart-711e2e38-5be9-4a85-a9fb-c240543fc100
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002629115 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2002629115
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1885129467
Short name T157
Test name
Test status
Simulation time 34150851 ps
CPU time 0.68 seconds
Started Apr 23 02:06:44 PM PDT 24
Finished Apr 23 02:06:45 PM PDT 24
Peak memory 203588 kb
Host smart-3750018d-a281-488d-9b3c-8496b3973dfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885129467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1885129467
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.510301838
Short name T1361
Test name
Test status
Simulation time 24593898 ps
CPU time 0.65 seconds
Started Apr 23 02:06:45 PM PDT 24
Finished Apr 23 02:06:46 PM PDT 24
Peak memory 203580 kb
Host smart-09d0a6cf-a9f5-46d5-a86d-f9f3ba0e2b12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510301838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.510301838
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1102561358
Short name T1389
Test name
Test status
Simulation time 108714665 ps
CPU time 2.02 seconds
Started Apr 23 02:06:45 PM PDT 24
Finished Apr 23 02:06:47 PM PDT 24
Peak memory 203776 kb
Host smart-c93bb6ea-34c4-4af5-bdb5-48ff2c01a4e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102561358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1102561358
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.909801271
Short name T140
Test name
Test status
Simulation time 87934173 ps
CPU time 2.09 seconds
Started Apr 23 02:06:45 PM PDT 24
Finished Apr 23 02:06:47 PM PDT 24
Peak memory 203876 kb
Host smart-8cd12831-c8ee-4fa0-8081-fd6404b98459
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909801271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.909801271
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3937768233
Short name T162
Test name
Test status
Simulation time 101162682 ps
CPU time 1.24 seconds
Started Apr 23 02:06:53 PM PDT 24
Finished Apr 23 02:06:56 PM PDT 24
Peak memory 203760 kb
Host smart-b04e04c5-35e3-4f6e-bd81-cf13836f2b2f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937768233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3937768233
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4098841565
Short name T130
Test name
Test status
Simulation time 64720682 ps
CPU time 0.76 seconds
Started Apr 23 02:06:50 PM PDT 24
Finished Apr 23 02:06:52 PM PDT 24
Peak memory 203768 kb
Host smart-ac57479d-f13c-47d0-bcca-fad2dd5e9ada
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098841565 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.4098841565
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.2772882962
Short name T1406
Test name
Test status
Simulation time 18827673 ps
CPU time 0.66 seconds
Started Apr 23 02:06:51 PM PDT 24
Finished Apr 23 02:06:52 PM PDT 24
Peak memory 203532 kb
Host smart-e7fbd5bb-98b5-440a-a874-45bf45d2f924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772882962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.2772882962
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.326825295
Short name T1392
Test name
Test status
Simulation time 191937433 ps
CPU time 1.54 seconds
Started Apr 23 02:06:53 PM PDT 24
Finished Apr 23 02:06:56 PM PDT 24
Peak memory 203880 kb
Host smart-a52a65d8-9beb-439b-98a5-da21816a5418
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326825295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.326825295
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.1153079289
Short name T1421
Test name
Test status
Simulation time 36445569 ps
CPU time 0.68 seconds
Started Apr 23 02:07:24 PM PDT 24
Finished Apr 23 02:07:26 PM PDT 24
Peak memory 203644 kb
Host smart-8de5c50a-c74c-4823-9892-f24f241514c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153079289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1153079289
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3878527072
Short name T1401
Test name
Test status
Simulation time 47330407 ps
CPU time 0.81 seconds
Started Apr 23 02:07:25 PM PDT 24
Finished Apr 23 02:07:26 PM PDT 24
Peak memory 203752 kb
Host smart-c45cb392-706e-4504-b5c4-0ba725265313
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878527072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.3878527072
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1762726364
Short name T141
Test name
Test status
Simulation time 265583537 ps
CPU time 1.46 seconds
Started Apr 23 02:07:24 PM PDT 24
Finished Apr 23 02:07:26 PM PDT 24
Peak memory 203880 kb
Host smart-ec8c5efa-1ae8-4d01-990f-91442794e472
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762726364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1762726364
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3617477990
Short name T1381
Test name
Test status
Simulation time 87964468 ps
CPU time 1.17 seconds
Started Apr 23 02:07:23 PM PDT 24
Finished Apr 23 02:07:24 PM PDT 24
Peak memory 203792 kb
Host smart-7cffa460-7289-46b8-908d-fd37efbe636b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617477990 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3617477990
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.799925217
Short name T1411
Test name
Test status
Simulation time 46316613 ps
CPU time 0.65 seconds
Started Apr 23 02:07:23 PM PDT 24
Finished Apr 23 02:07:24 PM PDT 24
Peak memory 203584 kb
Host smart-a1c3ce04-1267-42fb-8b11-445e21755cfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799925217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.799925217
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2097734649
Short name T1412
Test name
Test status
Simulation time 30034695 ps
CPU time 1.34 seconds
Started Apr 23 02:07:25 PM PDT 24
Finished Apr 23 02:07:27 PM PDT 24
Peak memory 203904 kb
Host smart-c8180275-4059-4581-9330-08f457661a6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097734649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2097734649
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3368724490
Short name T1405
Test name
Test status
Simulation time 88334621 ps
CPU time 0.83 seconds
Started Apr 23 02:07:27 PM PDT 24
Finished Apr 23 02:07:28 PM PDT 24
Peak memory 203852 kb
Host smart-ea3210d5-27c9-4bcf-9b85-6efe7afb12e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368724490 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3368724490
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.216113684
Short name T1379
Test name
Test status
Simulation time 52385983 ps
CPU time 0.73 seconds
Started Apr 23 02:07:26 PM PDT 24
Finished Apr 23 02:07:27 PM PDT 24
Peak memory 203580 kb
Host smart-f20e66a3-a3a5-48c3-bb5d-ce628373a44e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216113684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.216113684
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1424636423
Short name T1383
Test name
Test status
Simulation time 1083801509 ps
CPU time 1.64 seconds
Started Apr 23 02:07:23 PM PDT 24
Finished Apr 23 02:07:25 PM PDT 24
Peak memory 203840 kb
Host smart-eae2ba6b-819e-4883-a4ce-b265912ae298
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424636423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1424636423
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1954685427
Short name T129
Test name
Test status
Simulation time 320182608 ps
CPU time 1.54 seconds
Started Apr 23 02:07:22 PM PDT 24
Finished Apr 23 02:07:24 PM PDT 24
Peak memory 203856 kb
Host smart-2fc51938-86fe-4b0a-95fc-9a8090a44406
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954685427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.1954685427
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2736227242
Short name T1438
Test name
Test status
Simulation time 29910229 ps
CPU time 0.77 seconds
Started Apr 23 02:07:32 PM PDT 24
Finished Apr 23 02:07:34 PM PDT 24
Peak memory 203832 kb
Host smart-9e229e5b-4f07-44a1-aed2-9bce0b97d794
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736227242 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2736227242
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3605598885
Short name T161
Test name
Test status
Simulation time 42375026 ps
CPU time 0.76 seconds
Started Apr 23 02:07:26 PM PDT 24
Finished Apr 23 02:07:28 PM PDT 24
Peak memory 203768 kb
Host smart-167a8aba-e4aa-4d2f-a5aa-696a2fbdf672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605598885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.3605598885
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.2630209233
Short name T1440
Test name
Test status
Simulation time 43191209 ps
CPU time 0.65 seconds
Started Apr 23 02:07:27 PM PDT 24
Finished Apr 23 02:07:28 PM PDT 24
Peak memory 203620 kb
Host smart-7e7fe500-95f4-48db-a7a0-cbf1383b11b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630209233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2630209233
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.119944725
Short name T1439
Test name
Test status
Simulation time 155928386 ps
CPU time 2.6 seconds
Started Apr 23 02:07:27 PM PDT 24
Finished Apr 23 02:07:30 PM PDT 24
Peak memory 203860 kb
Host smart-cb16819b-5092-4aee-acda-3773fc5f21c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119944725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.119944725
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.2832501888
Short name T1388
Test name
Test status
Simulation time 96377162 ps
CPU time 0.95 seconds
Started Apr 23 02:07:30 PM PDT 24
Finished Apr 23 02:07:32 PM PDT 24
Peak memory 203716 kb
Host smart-852a5983-8676-4f01-86e9-33e3e1f68f93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832501888 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.2832501888
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3555846616
Short name T1403
Test name
Test status
Simulation time 19709861 ps
CPU time 0.66 seconds
Started Apr 23 02:07:30 PM PDT 24
Finished Apr 23 02:07:31 PM PDT 24
Peak memory 203596 kb
Host smart-83947c3a-92a7-4fcf-87ab-3e30cb2efec1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555846616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3555846616
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2043233718
Short name T165
Test name
Test status
Simulation time 382840426 ps
CPU time 1.13 seconds
Started Apr 23 02:07:28 PM PDT 24
Finished Apr 23 02:07:29 PM PDT 24
Peak memory 203776 kb
Host smart-cb414028-4c21-4318-9853-012e1334a678
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043233718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.2043233718
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2294496010
Short name T132
Test name
Test status
Simulation time 359025315 ps
CPU time 2.23 seconds
Started Apr 23 02:07:30 PM PDT 24
Finished Apr 23 02:07:33 PM PDT 24
Peak memory 203888 kb
Host smart-96353dba-7405-459b-aae7-74dcc6fc7ad8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294496010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2294496010
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3112842885
Short name T128
Test name
Test status
Simulation time 269084887 ps
CPU time 2.23 seconds
Started Apr 23 02:07:30 PM PDT 24
Finished Apr 23 02:07:32 PM PDT 24
Peak memory 203860 kb
Host smart-351a91e4-8642-4192-8f76-f2cd7a3ee86c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112842885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3112842885
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.4171381057
Short name T119
Test name
Test status
Simulation time 151817862 ps
CPU time 1.04 seconds
Started Apr 23 02:07:35 PM PDT 24
Finished Apr 23 02:07:36 PM PDT 24
Peak memory 203780 kb
Host smart-ea176a44-2e2a-4e22-ae61-b9ec7f191b04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171381057 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.4171381057
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2411100664
Short name T150
Test name
Test status
Simulation time 23175737 ps
CPU time 0.76 seconds
Started Apr 23 02:07:32 PM PDT 24
Finished Apr 23 02:07:33 PM PDT 24
Peak memory 203752 kb
Host smart-1cfd1347-6d98-4017-941a-667528213357
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411100664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2411100664
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.714998848
Short name T1380
Test name
Test status
Simulation time 24320231 ps
CPU time 0.69 seconds
Started Apr 23 02:07:30 PM PDT 24
Finished Apr 23 02:07:31 PM PDT 24
Peak memory 203552 kb
Host smart-6686c6a0-0317-4c21-b2e3-670a144abfb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714998848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.714998848
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2181640967
Short name T1445
Test name
Test status
Simulation time 177651636 ps
CPU time 0.9 seconds
Started Apr 23 02:07:30 PM PDT 24
Finished Apr 23 02:07:31 PM PDT 24
Peak memory 203680 kb
Host smart-a0717107-373e-49cf-b825-9490fe718436
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181640967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.2181640967
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.2336374852
Short name T1393
Test name
Test status
Simulation time 73040079 ps
CPU time 0.84 seconds
Started Apr 23 02:07:34 PM PDT 24
Finished Apr 23 02:07:35 PM PDT 24
Peak memory 203832 kb
Host smart-0368a7b3-7303-4545-91ef-bbc3759254e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336374852 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.2336374852
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2279288358
Short name T1435
Test name
Test status
Simulation time 25319118 ps
CPU time 0.68 seconds
Started Apr 23 02:07:32 PM PDT 24
Finished Apr 23 02:07:33 PM PDT 24
Peak memory 203652 kb
Host smart-3eabfd7a-56f8-47f8-bf59-31492ba593d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279288358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2279288358
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.2069476270
Short name T1450
Test name
Test status
Simulation time 15956660 ps
CPU time 0.78 seconds
Started Apr 23 02:07:32 PM PDT 24
Finished Apr 23 02:07:34 PM PDT 24
Peak memory 203640 kb
Host smart-d086e584-dbfa-4f05-8caf-32159439139c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069476270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2069476270
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1886967619
Short name T1437
Test name
Test status
Simulation time 19756186 ps
CPU time 0.79 seconds
Started Apr 23 02:07:34 PM PDT 24
Finished Apr 23 02:07:35 PM PDT 24
Peak memory 203648 kb
Host smart-761317b2-99b2-486b-ab6e-fc074be95940
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886967619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.1886967619
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.447158083
Short name T136
Test name
Test status
Simulation time 417365185 ps
CPU time 2.13 seconds
Started Apr 23 02:07:33 PM PDT 24
Finished Apr 23 02:07:36 PM PDT 24
Peak memory 203724 kb
Host smart-cb3058f4-d5d7-40b1-bae4-7d1ebc460c8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447158083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.447158083
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1848078954
Short name T211
Test name
Test status
Simulation time 221261966 ps
CPU time 1.4 seconds
Started Apr 23 02:07:32 PM PDT 24
Finished Apr 23 02:07:34 PM PDT 24
Peak memory 203916 kb
Host smart-555f2f57-184e-4884-9762-bfdee3f04ffe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848078954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.1848078954
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.501701548
Short name T1382
Test name
Test status
Simulation time 30389681 ps
CPU time 1.37 seconds
Started Apr 23 02:07:35 PM PDT 24
Finished Apr 23 02:07:37 PM PDT 24
Peak memory 203932 kb
Host smart-eda151db-ec29-4b45-ab8c-b389ee07d697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501701548 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.501701548
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3387859407
Short name T152
Test name
Test status
Simulation time 46396194 ps
CPU time 0.75 seconds
Started Apr 23 02:07:36 PM PDT 24
Finished Apr 23 02:07:37 PM PDT 24
Peak memory 203768 kb
Host smart-d874e159-d742-4661-866d-983a0006a0a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387859407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3387859407
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.3066833519
Short name T1404
Test name
Test status
Simulation time 46633077 ps
CPU time 0.65 seconds
Started Apr 23 02:07:46 PM PDT 24
Finished Apr 23 02:07:47 PM PDT 24
Peak memory 203508 kb
Host smart-575ca746-4b6e-4646-872a-44e3b7e557a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066833519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.3066833519
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2283163188
Short name T1448
Test name
Test status
Simulation time 86518772 ps
CPU time 1.05 seconds
Started Apr 23 02:07:36 PM PDT 24
Finished Apr 23 02:07:38 PM PDT 24
Peak memory 203876 kb
Host smart-83f88db9-4001-4c8b-82b6-0f460df70ebc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283163188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.2283163188
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2087401810
Short name T1391
Test name
Test status
Simulation time 551082852 ps
CPU time 2.93 seconds
Started Apr 23 02:07:33 PM PDT 24
Finished Apr 23 02:07:36 PM PDT 24
Peak memory 212056 kb
Host smart-9644f5a5-0cc9-4c25-8db6-283132595d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087401810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2087401810
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.813502139
Short name T1416
Test name
Test status
Simulation time 262803093 ps
CPU time 1.43 seconds
Started Apr 23 02:07:34 PM PDT 24
Finished Apr 23 02:07:36 PM PDT 24
Peak memory 203800 kb
Host smart-e2923a76-9cfd-4954-b59a-456f332f96d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813502139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.813502139
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1551496796
Short name T1433
Test name
Test status
Simulation time 359502801 ps
CPU time 1.06 seconds
Started Apr 23 02:07:38 PM PDT 24
Finished Apr 23 02:07:39 PM PDT 24
Peak memory 203856 kb
Host smart-a98a9de3-1134-4a7e-a118-8e4744b0c758
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551496796 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1551496796
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2764225406
Short name T1425
Test name
Test status
Simulation time 25428717 ps
CPU time 0.75 seconds
Started Apr 23 02:07:38 PM PDT 24
Finished Apr 23 02:07:39 PM PDT 24
Peak memory 203716 kb
Host smart-94e31c19-4564-4748-ae10-90bb934ba57e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764225406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2764225406
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.2945920832
Short name T1441
Test name
Test status
Simulation time 16827169 ps
CPU time 0.71 seconds
Started Apr 23 02:07:35 PM PDT 24
Finished Apr 23 02:07:36 PM PDT 24
Peak memory 203600 kb
Host smart-a787284e-c612-4f22-a49e-4a82f94e312f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945920832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2945920832
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1822849878
Short name T1442
Test name
Test status
Simulation time 23986333 ps
CPU time 0.9 seconds
Started Apr 23 02:07:36 PM PDT 24
Finished Apr 23 02:07:37 PM PDT 24
Peak memory 203680 kb
Host smart-77851158-b970-4c5a-978f-086c23334c04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822849878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.1822849878
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3784020225
Short name T1424
Test name
Test status
Simulation time 42104086 ps
CPU time 1.94 seconds
Started Apr 23 02:07:37 PM PDT 24
Finished Apr 23 02:07:39 PM PDT 24
Peak memory 203872 kb
Host smart-13383933-de25-47e1-a277-db7c3c957038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784020225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3784020225
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.819696915
Short name T139
Test name
Test status
Simulation time 137026859 ps
CPU time 1.48 seconds
Started Apr 23 02:07:35 PM PDT 24
Finished Apr 23 02:07:37 PM PDT 24
Peak memory 203760 kb
Host smart-8024ed0e-47dd-485e-b70d-c3e38568677a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819696915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.819696915
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2039867284
Short name T1410
Test name
Test status
Simulation time 28821379 ps
CPU time 1.27 seconds
Started Apr 23 02:07:47 PM PDT 24
Finished Apr 23 02:07:48 PM PDT 24
Peak memory 212052 kb
Host smart-40b4b45d-7668-4815-91e4-e9f81f1a2149
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039867284 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2039867284
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.4115800310
Short name T151
Test name
Test status
Simulation time 27108035 ps
CPU time 0.72 seconds
Started Apr 23 02:07:39 PM PDT 24
Finished Apr 23 02:07:40 PM PDT 24
Peak memory 203700 kb
Host smart-9f73e1f9-c114-4e96-96c4-8dd8e17cee69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115800310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.4115800310
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.107578855
Short name T1400
Test name
Test status
Simulation time 17269379 ps
CPU time 0.66 seconds
Started Apr 23 02:07:39 PM PDT 24
Finished Apr 23 02:07:40 PM PDT 24
Peak memory 203568 kb
Host smart-94f50207-7b37-4ab8-b3c8-844e4832a3fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107578855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.107578855
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2378182199
Short name T127
Test name
Test status
Simulation time 135406903 ps
CPU time 2.73 seconds
Started Apr 23 02:07:39 PM PDT 24
Finished Apr 23 02:07:43 PM PDT 24
Peak memory 203856 kb
Host smart-b45b3229-e46c-4101-96a6-7dfe934e91d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378182199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2378182199
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.4278058053
Short name T143
Test name
Test status
Simulation time 84817886 ps
CPU time 1.52 seconds
Started Apr 23 02:07:39 PM PDT 24
Finished Apr 23 02:07:41 PM PDT 24
Peak memory 203932 kb
Host smart-eb0f1162-8922-4886-9ce1-27910c371858
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278058053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.4278058053
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3432535623
Short name T158
Test name
Test status
Simulation time 429746659 ps
CPU time 2.09 seconds
Started Apr 23 02:06:55 PM PDT 24
Finished Apr 23 02:06:58 PM PDT 24
Peak memory 203868 kb
Host smart-b147a0c1-e318-48ab-9086-4d7e69321b3d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432535623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3432535623
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.2469499137
Short name T1362
Test name
Test status
Simulation time 1803508425 ps
CPU time 3.26 seconds
Started Apr 23 02:06:55 PM PDT 24
Finished Apr 23 02:06:59 PM PDT 24
Peak memory 203768 kb
Host smart-f296a1cd-8751-43b0-8f02-514853c33c3d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469499137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.2469499137
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1508383301
Short name T1408
Test name
Test status
Simulation time 61025864 ps
CPU time 0.72 seconds
Started Apr 23 02:06:54 PM PDT 24
Finished Apr 23 02:06:55 PM PDT 24
Peak memory 203804 kb
Host smart-de560dee-65c5-4f36-84f0-e4df608f0479
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508383301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1508383301
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2403805794
Short name T148
Test name
Test status
Simulation time 82051879 ps
CPU time 0.8 seconds
Started Apr 23 02:06:59 PM PDT 24
Finished Apr 23 02:07:01 PM PDT 24
Peak memory 203640 kb
Host smart-a21868e2-bb52-4096-8f82-4bbc0c8eacb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403805794 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.2403805794
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.593986168
Short name T156
Test name
Test status
Simulation time 31117028 ps
CPU time 0.66 seconds
Started Apr 23 02:06:52 PM PDT 24
Finished Apr 23 02:06:53 PM PDT 24
Peak memory 203668 kb
Host smart-2687d4bd-8d8d-432b-8a38-13c4fac61aee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593986168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.593986168
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1089713739
Short name T1426
Test name
Test status
Simulation time 38100131 ps
CPU time 0.63 seconds
Started Apr 23 02:06:52 PM PDT 24
Finished Apr 23 02:06:53 PM PDT 24
Peak memory 203560 kb
Host smart-8f73114f-c62b-454c-9031-7c709cef6e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089713739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1089713739
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.3313406722
Short name T193
Test name
Test status
Simulation time 911437988 ps
CPU time 1.74 seconds
Started Apr 23 02:06:53 PM PDT 24
Finished Apr 23 02:06:56 PM PDT 24
Peak memory 203880 kb
Host smart-491afaf6-6254-42b0-92a9-369c571e1cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313406722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3313406722
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.2679689987
Short name T1419
Test name
Test status
Simulation time 36644884 ps
CPU time 0.64 seconds
Started Apr 23 02:07:40 PM PDT 24
Finished Apr 23 02:07:41 PM PDT 24
Peak memory 203504 kb
Host smart-f52a6918-7b02-4250-95a9-8aeef3d500d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679689987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2679689987
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.550108710
Short name T1430
Test name
Test status
Simulation time 73716488 ps
CPU time 0.7 seconds
Started Apr 23 02:07:47 PM PDT 24
Finished Apr 23 02:07:49 PM PDT 24
Peak memory 203512 kb
Host smart-710ff824-516c-478e-a39c-0cdc70068a6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550108710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.550108710
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.2509747452
Short name T1378
Test name
Test status
Simulation time 27725922 ps
CPU time 0.67 seconds
Started Apr 23 02:07:47 PM PDT 24
Finished Apr 23 02:07:48 PM PDT 24
Peak memory 203516 kb
Host smart-fc7072e0-fa1f-41a2-9a27-62a74d498709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509747452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.2509747452
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.1512396453
Short name T1429
Test name
Test status
Simulation time 22424208 ps
CPU time 0.72 seconds
Started Apr 23 02:07:40 PM PDT 24
Finished Apr 23 02:07:41 PM PDT 24
Peak memory 203500 kb
Host smart-07840379-1fbb-4760-9a83-6d8b23ae3af5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512396453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1512396453
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.1351602462
Short name T1374
Test name
Test status
Simulation time 16272638 ps
CPU time 0.65 seconds
Started Apr 23 02:07:38 PM PDT 24
Finished Apr 23 02:07:39 PM PDT 24
Peak memory 203644 kb
Host smart-a9e636c9-0744-4e2c-9920-3301cad9c8c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351602462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.1351602462
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.1345512605
Short name T1376
Test name
Test status
Simulation time 23717235 ps
CPU time 0.66 seconds
Started Apr 23 02:07:48 PM PDT 24
Finished Apr 23 02:07:49 PM PDT 24
Peak memory 203416 kb
Host smart-57fa3892-eaa3-4a7c-86ad-17795bd90bb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345512605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1345512605
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.693788660
Short name T1398
Test name
Test status
Simulation time 92446701 ps
CPU time 0.65 seconds
Started Apr 23 02:07:47 PM PDT 24
Finished Apr 23 02:07:49 PM PDT 24
Peak memory 203512 kb
Host smart-e275c682-88cf-4d5a-9b56-c65043a83170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693788660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.693788660
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.2263158170
Short name T1407
Test name
Test status
Simulation time 19919279 ps
CPU time 0.66 seconds
Started Apr 23 02:07:42 PM PDT 24
Finished Apr 23 02:07:43 PM PDT 24
Peak memory 203644 kb
Host smart-dd232199-8c00-47f9-afb9-a1c8e8bd58b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263158170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2263158170
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.4215175337
Short name T1402
Test name
Test status
Simulation time 45564907 ps
CPU time 0.67 seconds
Started Apr 23 02:07:42 PM PDT 24
Finished Apr 23 02:07:44 PM PDT 24
Peak memory 203604 kb
Host smart-d8bdee7e-661a-4a3f-bb87-5fc1042ccc70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215175337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.4215175337
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.3465145029
Short name T1415
Test name
Test status
Simulation time 54827673 ps
CPU time 0.64 seconds
Started Apr 23 02:07:53 PM PDT 24
Finished Apr 23 02:07:54 PM PDT 24
Peak memory 203516 kb
Host smart-0e4efff2-49c1-4e7f-bdb5-490cbf697e59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465145029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3465145029
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1487207545
Short name T1427
Test name
Test status
Simulation time 511027869 ps
CPU time 2.05 seconds
Started Apr 23 02:07:04 PM PDT 24
Finished Apr 23 02:07:06 PM PDT 24
Peak memory 203760 kb
Host smart-a42d7a78-cff1-465a-953c-ffe8ec199af5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487207545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1487207545
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1669490717
Short name T1370
Test name
Test status
Simulation time 512986504 ps
CPU time 5.55 seconds
Started Apr 23 02:07:00 PM PDT 24
Finished Apr 23 02:07:06 PM PDT 24
Peak memory 203884 kb
Host smart-e1e2654d-e2eb-4b91-9b19-cb9fe38a7ced
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669490717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1669490717
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3307258428
Short name T153
Test name
Test status
Simulation time 79339094 ps
CPU time 0.69 seconds
Started Apr 23 02:07:03 PM PDT 24
Finished Apr 23 02:07:04 PM PDT 24
Peak memory 203728 kb
Host smart-5c69fbd9-11c1-4b5e-9108-8864b21cd903
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307258428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3307258428
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3519144925
Short name T1396
Test name
Test status
Simulation time 41902624 ps
CPU time 0.7 seconds
Started Apr 23 02:07:04 PM PDT 24
Finished Apr 23 02:07:05 PM PDT 24
Peak memory 203572 kb
Host smart-c8afbb84-594b-49c5-958b-163b7d6bed70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519144925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3519144925
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.350951559
Short name T1372
Test name
Test status
Simulation time 54291053 ps
CPU time 0.74 seconds
Started Apr 23 02:07:01 PM PDT 24
Finished Apr 23 02:07:02 PM PDT 24
Peak memory 203548 kb
Host smart-cc66a8e5-ad74-4e54-bc7d-d8a33efe4a67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350951559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.350951559
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1109372697
Short name T118
Test name
Test status
Simulation time 124155359 ps
CPU time 1.62 seconds
Started Apr 23 02:06:57 PM PDT 24
Finished Apr 23 02:06:59 PM PDT 24
Peak memory 203816 kb
Host smart-9e6550a5-9b08-4d48-821e-4a7b74e65f82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109372697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1109372697
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.3311369877
Short name T1371
Test name
Test status
Simulation time 15409235 ps
CPU time 0.65 seconds
Started Apr 23 02:07:40 PM PDT 24
Finished Apr 23 02:07:41 PM PDT 24
Peak memory 203684 kb
Host smart-5a30106c-e7a6-4d85-a060-991b52d6e352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311369877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3311369877
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.981744532
Short name T1447
Test name
Test status
Simulation time 24287959 ps
CPU time 0.68 seconds
Started Apr 23 02:07:44 PM PDT 24
Finished Apr 23 02:07:45 PM PDT 24
Peak memory 203648 kb
Host smart-8624ab6f-dc57-469e-9058-4d73c5e8a626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981744532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.981744532
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.2042208554
Short name T1414
Test name
Test status
Simulation time 15855466 ps
CPU time 0.67 seconds
Started Apr 23 02:07:47 PM PDT 24
Finished Apr 23 02:07:49 PM PDT 24
Peak memory 203568 kb
Host smart-3c41806a-d54d-411f-8896-a84a30d1cf93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042208554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2042208554
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.1093562276
Short name T1366
Test name
Test status
Simulation time 29122922 ps
CPU time 0.69 seconds
Started Apr 23 02:07:45 PM PDT 24
Finished Apr 23 02:07:46 PM PDT 24
Peak memory 203508 kb
Host smart-e0277a05-8f31-4673-86d6-22e2edeb93c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093562276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1093562276
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.1275316699
Short name T1367
Test name
Test status
Simulation time 32875021 ps
CPU time 0.68 seconds
Started Apr 23 02:07:44 PM PDT 24
Finished Apr 23 02:07:45 PM PDT 24
Peak memory 203556 kb
Host smart-d17b505e-c52a-4b1c-875b-7b5cdbc1f8d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275316699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1275316699
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.3766859181
Short name T1377
Test name
Test status
Simulation time 41478511 ps
CPU time 0.63 seconds
Started Apr 23 02:07:44 PM PDT 24
Finished Apr 23 02:07:45 PM PDT 24
Peak memory 203600 kb
Host smart-8489cc19-be4c-42d2-91d6-4b3371ce7c27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766859181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3766859181
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.4057676329
Short name T1413
Test name
Test status
Simulation time 57496308 ps
CPU time 0.64 seconds
Started Apr 23 02:07:44 PM PDT 24
Finished Apr 23 02:07:45 PM PDT 24
Peak memory 203572 kb
Host smart-62613285-e146-4881-854a-2a5f20ac5d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057676329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.4057676329
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.3661139593
Short name T1364
Test name
Test status
Simulation time 15501174 ps
CPU time 0.69 seconds
Started Apr 23 02:07:45 PM PDT 24
Finished Apr 23 02:07:46 PM PDT 24
Peak memory 203620 kb
Host smart-d8d45140-6aeb-4a51-826d-3c1adba24f55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661139593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3661139593
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.2558566596
Short name T1373
Test name
Test status
Simulation time 31458862 ps
CPU time 0.77 seconds
Started Apr 23 02:07:45 PM PDT 24
Finished Apr 23 02:07:46 PM PDT 24
Peak memory 203580 kb
Host smart-22626e82-1f09-481d-8a05-493769b0ef12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558566596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2558566596
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.5131859
Short name T1443
Test name
Test status
Simulation time 42607757 ps
CPU time 0.65 seconds
Started Apr 23 02:07:49 PM PDT 24
Finished Apr 23 02:07:51 PM PDT 24
Peak memory 203640 kb
Host smart-650ad954-2059-4077-8c49-0431c55aaaa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5131859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.5131859
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3373602460
Short name T1451
Test name
Test status
Simulation time 404794712 ps
CPU time 2.13 seconds
Started Apr 23 02:07:09 PM PDT 24
Finished Apr 23 02:07:12 PM PDT 24
Peak memory 203820 kb
Host smart-aeb4214d-adf0-4d1e-8ece-f8a5e027b3ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373602460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3373602460
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2212883473
Short name T160
Test name
Test status
Simulation time 138038618 ps
CPU time 2.92 seconds
Started Apr 23 02:07:13 PM PDT 24
Finished Apr 23 02:07:17 PM PDT 24
Peak memory 203716 kb
Host smart-7499ec55-c1a4-4214-a641-94a5fc23e4fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212883473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.2212883473
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2161595224
Short name T159
Test name
Test status
Simulation time 19254009 ps
CPU time 0.67 seconds
Started Apr 23 02:07:05 PM PDT 24
Finished Apr 23 02:07:06 PM PDT 24
Peak memory 203572 kb
Host smart-1b5625ac-199d-42f6-8e0b-bdb6ae415743
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161595224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2161595224
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.4154703409
Short name T1449
Test name
Test status
Simulation time 156684203 ps
CPU time 0.89 seconds
Started Apr 23 02:07:09 PM PDT 24
Finished Apr 23 02:07:10 PM PDT 24
Peak memory 203680 kb
Host smart-b69dbde9-778e-4a04-8a30-7e3c1466a26f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154703409 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.4154703409
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.260639156
Short name T82
Test name
Test status
Simulation time 31439807 ps
CPU time 0.66 seconds
Started Apr 23 02:07:05 PM PDT 24
Finished Apr 23 02:07:06 PM PDT 24
Peak memory 203564 kb
Host smart-2733afcc-4b6b-4b08-b900-d8fe1053db7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260639156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.260639156
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.596830376
Short name T1375
Test name
Test status
Simulation time 18458012 ps
CPU time 0.69 seconds
Started Apr 23 02:07:04 PM PDT 24
Finished Apr 23 02:07:05 PM PDT 24
Peak memory 203568 kb
Host smart-0aaf4727-7588-4062-8056-04fc03bd8222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596830376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.596830376
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2549049691
Short name T133
Test name
Test status
Simulation time 239345350 ps
CPU time 2.69 seconds
Started Apr 23 02:07:03 PM PDT 24
Finished Apr 23 02:07:07 PM PDT 24
Peak memory 203760 kb
Host smart-48ce36e7-998c-4a14-ab65-834faff45a04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549049691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2549049691
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.22165186
Short name T1423
Test name
Test status
Simulation time 30642867 ps
CPU time 0.71 seconds
Started Apr 23 02:07:48 PM PDT 24
Finished Apr 23 02:07:49 PM PDT 24
Peak memory 203564 kb
Host smart-919cbad6-4323-41d8-a211-ad355583b9de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22165186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.22165186
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.934970745
Short name T1386
Test name
Test status
Simulation time 15212340 ps
CPU time 0.64 seconds
Started Apr 23 02:07:47 PM PDT 24
Finished Apr 23 02:07:49 PM PDT 24
Peak memory 203596 kb
Host smart-c5105483-ca0b-4127-9501-da57fe710bbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934970745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.934970745
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.4074475575
Short name T1420
Test name
Test status
Simulation time 17996772 ps
CPU time 0.66 seconds
Started Apr 23 02:07:48 PM PDT 24
Finished Apr 23 02:07:50 PM PDT 24
Peak memory 203600 kb
Host smart-f24029fa-52b1-4a23-a538-62f483b026f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074475575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.4074475575
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.594599540
Short name T1417
Test name
Test status
Simulation time 24876434 ps
CPU time 0.66 seconds
Started Apr 23 02:07:47 PM PDT 24
Finished Apr 23 02:07:49 PM PDT 24
Peak memory 203556 kb
Host smart-56d7289f-40e9-4d21-902b-24ca2acebe3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594599540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.594599540
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1852045109
Short name T1368
Test name
Test status
Simulation time 44916671 ps
CPU time 0.65 seconds
Started Apr 23 02:07:48 PM PDT 24
Finished Apr 23 02:07:49 PM PDT 24
Peak memory 203504 kb
Host smart-d8a88d89-82f7-418f-9fdd-9e79c8f9083f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852045109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1852045109
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2178337936
Short name T1394
Test name
Test status
Simulation time 20726029 ps
CPU time 0.7 seconds
Started Apr 23 02:07:47 PM PDT 24
Finished Apr 23 02:07:49 PM PDT 24
Peak memory 203544 kb
Host smart-22623456-07f0-4bdc-a808-f7c85dc70bca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178337936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2178337936
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.3994195687
Short name T1397
Test name
Test status
Simulation time 49153429 ps
CPU time 0.65 seconds
Started Apr 23 02:07:48 PM PDT 24
Finished Apr 23 02:07:49 PM PDT 24
Peak memory 203512 kb
Host smart-71a516f5-f948-490f-9b7c-6fc94def89fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994195687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.3994195687
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.2581785739
Short name T1365
Test name
Test status
Simulation time 16412282 ps
CPU time 0.83 seconds
Started Apr 23 02:07:50 PM PDT 24
Finished Apr 23 02:07:51 PM PDT 24
Peak memory 203644 kb
Host smart-9678f871-8822-4851-8882-02a31e0b210c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581785739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2581785739
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.516892852
Short name T1385
Test name
Test status
Simulation time 27674647 ps
CPU time 0.66 seconds
Started Apr 23 02:07:50 PM PDT 24
Finished Apr 23 02:07:51 PM PDT 24
Peak memory 203500 kb
Host smart-b63d274e-5271-4f76-a2bc-d0ac58588835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516892852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.516892852
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.648457328
Short name T1387
Test name
Test status
Simulation time 38461555 ps
CPU time 0.69 seconds
Started Apr 23 02:07:50 PM PDT 24
Finished Apr 23 02:07:51 PM PDT 24
Peak memory 203568 kb
Host smart-cb947a2b-8e4e-40e7-b126-3ff7b6007624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648457328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.648457328
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.4129004614
Short name T125
Test name
Test status
Simulation time 89239751 ps
CPU time 0.86 seconds
Started Apr 23 02:07:09 PM PDT 24
Finished Apr 23 02:07:11 PM PDT 24
Peak memory 203772 kb
Host smart-80180d95-183b-4745-b33c-49d9d9aa17b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129004614 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.4129004614
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1320478351
Short name T1409
Test name
Test status
Simulation time 49051984 ps
CPU time 0.68 seconds
Started Apr 23 02:07:13 PM PDT 24
Finished Apr 23 02:07:15 PM PDT 24
Peak memory 203636 kb
Host smart-47afb1c5-929e-4723-93cd-54c05631553d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320478351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1320478351
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.4124706503
Short name T239
Test name
Test status
Simulation time 18351644 ps
CPU time 0.66 seconds
Started Apr 23 02:07:08 PM PDT 24
Finished Apr 23 02:07:10 PM PDT 24
Peak memory 203556 kb
Host smart-48d30af5-aaa1-46b2-8fc1-60aef658acc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124706503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.4124706503
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3414168360
Short name T1453
Test name
Test status
Simulation time 132839464 ps
CPU time 2.24 seconds
Started Apr 23 02:07:10 PM PDT 24
Finished Apr 23 02:07:13 PM PDT 24
Peak memory 203864 kb
Host smart-3838107c-ca64-4732-827e-0ecc0f1e5108
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414168360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3414168360
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.1909026146
Short name T134
Test name
Test status
Simulation time 111237130 ps
CPU time 2.19 seconds
Started Apr 23 02:07:13 PM PDT 24
Finished Apr 23 02:07:17 PM PDT 24
Peak memory 203856 kb
Host smart-be3f447c-29d2-44e7-9e5d-fb54d508e5d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909026146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1909026146
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2741170132
Short name T147
Test name
Test status
Simulation time 85204695 ps
CPU time 0.82 seconds
Started Apr 23 02:07:19 PM PDT 24
Finished Apr 23 02:07:20 PM PDT 24
Peak memory 203684 kb
Host smart-0755f664-8178-4f59-a196-fbcd04b7ecff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741170132 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.2741170132
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.2522357410
Short name T1422
Test name
Test status
Simulation time 48388991 ps
CPU time 0.62 seconds
Started Apr 23 02:07:13 PM PDT 24
Finished Apr 23 02:07:16 PM PDT 24
Peak memory 203636 kb
Host smart-9262b323-be0f-43c0-8f4f-b4656f7dab71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522357410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2522357410
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.3915186111
Short name T1431
Test name
Test status
Simulation time 47248210 ps
CPU time 1.05 seconds
Started Apr 23 02:07:17 PM PDT 24
Finished Apr 23 02:07:19 PM PDT 24
Peak memory 203812 kb
Host smart-637230c7-dc99-4286-bc56-952b7b3e5308
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915186111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.3915186111
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.971145161
Short name T1432
Test name
Test status
Simulation time 58651085 ps
CPU time 1.43 seconds
Started Apr 23 02:07:12 PM PDT 24
Finished Apr 23 02:07:14 PM PDT 24
Peak memory 203892 kb
Host smart-f155a4b4-4688-4256-b893-efe79bd83e73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971145161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.971145161
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3148433776
Short name T138
Test name
Test status
Simulation time 145402837 ps
CPU time 2.38 seconds
Started Apr 23 02:07:13 PM PDT 24
Finished Apr 23 02:07:16 PM PDT 24
Peak memory 203880 kb
Host smart-c21d6c82-5ffb-4a32-ac53-23de552de8c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148433776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.3148433776
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.758424093
Short name T154
Test name
Test status
Simulation time 202458603 ps
CPU time 0.66 seconds
Started Apr 23 02:07:26 PM PDT 24
Finished Apr 23 02:07:27 PM PDT 24
Peak memory 203792 kb
Host smart-e4784653-1095-4e42-bb4b-418ba0e2ca18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758424093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.758424093
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.2456354816
Short name T1363
Test name
Test status
Simulation time 15394551 ps
CPU time 0.7 seconds
Started Apr 23 02:07:26 PM PDT 24
Finished Apr 23 02:07:28 PM PDT 24
Peak memory 203628 kb
Host smart-910ac850-788e-4c5f-ad85-11e4a67297ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456354816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2456354816
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.584910116
Short name T81
Test name
Test status
Simulation time 46921007 ps
CPU time 1.02 seconds
Started Apr 23 02:07:17 PM PDT 24
Finished Apr 23 02:07:19 PM PDT 24
Peak memory 203832 kb
Host smart-c132c691-c48b-4641-a38b-4fe426da6f74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584910116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_out
standing.584910116
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.872979300
Short name T126
Test name
Test status
Simulation time 513524930 ps
CPU time 2.63 seconds
Started Apr 23 02:07:18 PM PDT 24
Finished Apr 23 02:07:21 PM PDT 24
Peak memory 203768 kb
Host smart-50d3fe7c-d234-4d84-a289-205d8d048233
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872979300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.872979300
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2614775238
Short name T145
Test name
Test status
Simulation time 80097770 ps
CPU time 1.5 seconds
Started Apr 23 02:07:18 PM PDT 24
Finished Apr 23 02:07:20 PM PDT 24
Peak memory 203828 kb
Host smart-477a3f84-7a6f-4adc-9be4-6a7dbe60b9b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614775238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2614775238
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2483901
Short name T1434
Test name
Test status
Simulation time 37794997 ps
CPU time 1.07 seconds
Started Apr 23 02:07:21 PM PDT 24
Finished Apr 23 02:07:23 PM PDT 24
Peak memory 203740 kb
Host smart-fcc89bdb-8470-4fb9-b5ac-d956bf68d2e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483901 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2483901
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3172230329
Short name T163
Test name
Test status
Simulation time 96420401 ps
CPU time 0.66 seconds
Started Apr 23 02:07:18 PM PDT 24
Finished Apr 23 02:07:19 PM PDT 24
Peak memory 203572 kb
Host smart-f441fc93-2a42-4a39-bed6-f86c6a8757a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172230329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.3172230329
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.985145159
Short name T1384
Test name
Test status
Simulation time 19091873 ps
CPU time 0.69 seconds
Started Apr 23 02:07:27 PM PDT 24
Finished Apr 23 02:07:28 PM PDT 24
Peak memory 203632 kb
Host smart-9ed114d5-d02d-4f20-b719-69bc882af944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985145159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.985145159
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.264801770
Short name T1428
Test name
Test status
Simulation time 271268919 ps
CPU time 1.48 seconds
Started Apr 23 02:07:30 PM PDT 24
Finished Apr 23 02:07:32 PM PDT 24
Peak memory 203760 kb
Host smart-11166b0c-4ec3-4ef3-9608-de3890d29013
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264801770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.264801770
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3829906405
Short name T1436
Test name
Test status
Simulation time 138291202 ps
CPU time 2.2 seconds
Started Apr 23 02:07:29 PM PDT 24
Finished Apr 23 02:07:32 PM PDT 24
Peak memory 203812 kb
Host smart-85b6e612-ee1f-4630-97f9-d2e57e19e942
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829906405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.3829906405
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.4260056616
Short name T1452
Test name
Test status
Simulation time 32741608 ps
CPU time 1.52 seconds
Started Apr 23 02:07:27 PM PDT 24
Finished Apr 23 02:07:29 PM PDT 24
Peak memory 211996 kb
Host smart-3d604fa2-6570-454a-86ea-4a4172f05fdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260056616 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.4260056616
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3245459392
Short name T164
Test name
Test status
Simulation time 13560526863 ps
CPU time 12.6 seconds
Started Apr 23 02:07:20 PM PDT 24
Finished Apr 23 02:07:33 PM PDT 24
Peak memory 203668 kb
Host smart-63e84620-435c-445f-8e1b-491e01987b61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245459392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.3245459392
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.1231385062
Short name T1395
Test name
Test status
Simulation time 29705247 ps
CPU time 0.69 seconds
Started Apr 23 02:07:27 PM PDT 24
Finished Apr 23 02:07:28 PM PDT 24
Peak memory 203512 kb
Host smart-ef982058-b89a-42ac-8ff0-0d28301c7364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231385062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1231385062
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3082710477
Short name T1399
Test name
Test status
Simulation time 179142955 ps
CPU time 1.29 seconds
Started Apr 23 02:07:22 PM PDT 24
Finished Apr 23 02:07:24 PM PDT 24
Peak memory 203752 kb
Host smart-88cbcdf5-c3a3-4f84-968e-1883e2370831
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082710477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3082710477
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_alert_test.675603696
Short name T494
Test name
Test status
Simulation time 18559770 ps
CPU time 0.61 seconds
Started Apr 23 01:21:25 PM PDT 24
Finished Apr 23 01:21:26 PM PDT 24
Peak memory 203400 kb
Host smart-3d0ce650-943c-431d-89fd-213fd5b6c00c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675603696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.675603696
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.1790664582
Short name T750
Test name
Test status
Simulation time 202231006 ps
CPU time 1.45 seconds
Started Apr 23 01:21:18 PM PDT 24
Finished Apr 23 01:21:20 PM PDT 24
Peak memory 211964 kb
Host smart-71524123-07fd-45e4-bd22-6ba149435794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790664582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.1790664582
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2282283737
Short name T1298
Test name
Test status
Simulation time 359979263 ps
CPU time 17.85 seconds
Started Apr 23 01:21:20 PM PDT 24
Finished Apr 23 01:21:38 PM PDT 24
Peak memory 269028 kb
Host smart-44312309-b796-486e-bdab-f20a5f0705c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282283737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.2282283737
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.318377826
Short name T780
Test name
Test status
Simulation time 8410562688 ps
CPU time 81.69 seconds
Started Apr 23 01:21:17 PM PDT 24
Finished Apr 23 01:22:39 PM PDT 24
Peak memory 705820 kb
Host smart-4e359cb2-28fb-4f93-8b3f-5a9833426c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318377826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.318377826
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.122849248
Short name T1029
Test name
Test status
Simulation time 14415470884 ps
CPU time 81.56 seconds
Started Apr 23 01:21:16 PM PDT 24
Finished Apr 23 01:22:39 PM PDT 24
Peak memory 492052 kb
Host smart-5100f595-169d-4e81-84a0-521d27bd9999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122849248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.122849248
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.3210999040
Short name T565
Test name
Test status
Simulation time 329842246 ps
CPU time 1.08 seconds
Started Apr 23 01:21:17 PM PDT 24
Finished Apr 23 01:21:19 PM PDT 24
Peak memory 203388 kb
Host smart-546399ba-19f9-4473-8f31-55e06b07e555
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210999040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.3210999040
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.2326151824
Short name T940
Test name
Test status
Simulation time 214778450 ps
CPU time 4.54 seconds
Started Apr 23 01:21:18 PM PDT 24
Finished Apr 23 01:21:23 PM PDT 24
Peak memory 203560 kb
Host smart-ee0a6462-b45a-468c-9b63-39dbed64104a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326151824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
2326151824
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.914090063
Short name T1335
Test name
Test status
Simulation time 2624964078 ps
CPU time 56.96 seconds
Started Apr 23 01:21:14 PM PDT 24
Finished Apr 23 01:22:12 PM PDT 24
Peak memory 827564 kb
Host smart-751e94ca-9884-4e1d-a5af-1c83260a1726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914090063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.914090063
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.4172083662
Short name T1181
Test name
Test status
Simulation time 873861836 ps
CPU time 6.16 seconds
Started Apr 23 01:21:25 PM PDT 24
Finished Apr 23 01:21:32 PM PDT 24
Peak memory 203696 kb
Host smart-6f2f9b63-41a0-4127-a738-d9e704cc3021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172083662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.4172083662
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_override.2148760939
Short name T1328
Test name
Test status
Simulation time 29264305 ps
CPU time 0.66 seconds
Started Apr 23 01:21:14 PM PDT 24
Finished Apr 23 01:21:15 PM PDT 24
Peak memory 203276 kb
Host smart-8b0122f6-b818-4d83-9bf9-dec14d3f061b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148760939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.2148760939
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.1520707614
Short name T380
Test name
Test status
Simulation time 7031662800 ps
CPU time 266.29 seconds
Started Apr 23 01:21:17 PM PDT 24
Finished Apr 23 01:25:44 PM PDT 24
Peak memory 951964 kb
Host smart-daee1be8-87bd-40d6-8bd3-8479e7f8ea0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520707614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.1520707614
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.2542099855
Short name T278
Test name
Test status
Simulation time 1256920839 ps
CPU time 29.8 seconds
Started Apr 23 01:21:17 PM PDT 24
Finished Apr 23 01:21:47 PM PDT 24
Peak memory 366068 kb
Host smart-dacb03ec-97ac-4b12-bdd2-8258b0850f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542099855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.2542099855
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.3205965467
Short name T410
Test name
Test status
Simulation time 1727627989 ps
CPU time 19.33 seconds
Started Apr 23 01:21:16 PM PDT 24
Finished Apr 23 01:21:36 PM PDT 24
Peak memory 211932 kb
Host smart-552a1710-e185-4639-aaa2-2a78abe0701a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205965467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.3205965467
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.3864988282
Short name T1270
Test name
Test status
Simulation time 1796799635 ps
CPU time 2.47 seconds
Started Apr 23 01:21:21 PM PDT 24
Finished Apr 23 01:21:24 PM PDT 24
Peak memory 203668 kb
Host smart-2cba8b38-4b35-4f3d-bfab-4845d4972eb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864988282 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.3864988282
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2887336679
Short name T685
Test name
Test status
Simulation time 10576333322 ps
CPU time 13.18 seconds
Started Apr 23 01:21:24 PM PDT 24
Finished Apr 23 01:21:37 PM PDT 24
Peak memory 283040 kb
Host smart-d9139a5b-646d-49b9-b619-c4a1abdc5319
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887336679 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2887336679
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.3212795804
Short name T900
Test name
Test status
Simulation time 10053062167 ps
CPU time 92.99 seconds
Started Apr 23 01:21:22 PM PDT 24
Finished Apr 23 01:22:55 PM PDT 24
Peak memory 493876 kb
Host smart-2a317d71-c249-445b-bfde-fad6d4a462ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212795804 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.3212795804
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.1798401665
Short name T27
Test name
Test status
Simulation time 7849752134 ps
CPU time 9.04 seconds
Started Apr 23 01:21:18 PM PDT 24
Finished Apr 23 01:21:27 PM PDT 24
Peak memory 203904 kb
Host smart-c53a13de-8892-4cf1-91e9-ecc6891eb653
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798401665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.1798401665
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.3124115152
Short name T538
Test name
Test status
Simulation time 351349477 ps
CPU time 1.96 seconds
Started Apr 23 01:21:24 PM PDT 24
Finished Apr 23 01:21:27 PM PDT 24
Peak memory 203644 kb
Host smart-060dd20a-d215-4e1a-86e0-e359aa2830ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124115152 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.3124115152
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.3887234991
Short name T512
Test name
Test status
Simulation time 4493706007 ps
CPU time 5.29 seconds
Started Apr 23 01:21:23 PM PDT 24
Finished Apr 23 01:21:29 PM PDT 24
Peak memory 205648 kb
Host smart-f5a68317-4d6f-448d-ba01-b7d83b06cde0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887234991 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.3887234991
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.3003112367
Short name T251
Test name
Test status
Simulation time 11486885129 ps
CPU time 24.27 seconds
Started Apr 23 01:21:22 PM PDT 24
Finished Apr 23 01:21:47 PM PDT 24
Peak memory 767200 kb
Host smart-a92293b8-950d-470e-8a90-1bc7a3cf60b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003112367 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.3003112367
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.1569690863
Short name T1031
Test name
Test status
Simulation time 1155895645 ps
CPU time 43.94 seconds
Started Apr 23 01:21:18 PM PDT 24
Finished Apr 23 01:22:02 PM PDT 24
Peak memory 203644 kb
Host smart-469d4e1f-e03e-4f72-a86e-cbd6ad3bd2f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569690863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.1569690863
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.212919043
Short name T513
Test name
Test status
Simulation time 4117469528 ps
CPU time 58 seconds
Started Apr 23 01:21:21 PM PDT 24
Finished Apr 23 01:22:19 PM PDT 24
Peak memory 205724 kb
Host smart-644bbd8b-8836-433f-b187-5372c06d2dff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212919043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_rd.212919043
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.3213596097
Short name T1028
Test name
Test status
Simulation time 62386613636 ps
CPU time 2340.82 seconds
Started Apr 23 01:21:18 PM PDT 24
Finished Apr 23 02:00:20 PM PDT 24
Peak memory 10544788 kb
Host smart-c980f103-ff2f-46ee-b92c-cb9bb2e63d6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213596097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.3213596097
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.1654115858
Short name T248
Test name
Test status
Simulation time 9547125452 ps
CPU time 43.47 seconds
Started Apr 23 01:21:21 PM PDT 24
Finished Apr 23 01:22:05 PM PDT 24
Peak memory 671992 kb
Host smart-95f00bf2-2d05-4729-a57f-5ab538b920e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654115858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.1654115858
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.4030622923
Short name T1041
Test name
Test status
Simulation time 1380249212 ps
CPU time 6.99 seconds
Started Apr 23 01:21:22 PM PDT 24
Finished Apr 23 01:21:29 PM PDT 24
Peak memory 219528 kb
Host smart-92fb4212-4bce-4088-8047-c30b32705c76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030622923 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.4030622923
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.913273194
Short name T1336
Test name
Test status
Simulation time 497020654 ps
CPU time 4.26 seconds
Started Apr 23 01:21:28 PM PDT 24
Finished Apr 23 01:21:33 PM PDT 24
Peak memory 238524 kb
Host smart-cab726d6-2ea3-4650-b4e1-f4448a9fe7d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913273194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.913273194
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.3840581408
Short name T47
Test name
Test status
Simulation time 23991467443 ps
CPU time 60.48 seconds
Started Apr 23 01:21:28 PM PDT 24
Finished Apr 23 01:22:29 PM PDT 24
Peak memory 681728 kb
Host smart-b938aec7-24d6-44ab-a9ac-0965e77e0501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840581408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.3840581408
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.1422395370
Short name T1022
Test name
Test status
Simulation time 3454427686 ps
CPU time 54.64 seconds
Started Apr 23 01:21:29 PM PDT 24
Finished Apr 23 01:22:24 PM PDT 24
Peak memory 617424 kb
Host smart-58fdf8d3-0580-4f1e-bb63-73cb9e8afc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422395370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.1422395370
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.241272382
Short name T1035
Test name
Test status
Simulation time 96052814 ps
CPU time 1.03 seconds
Started Apr 23 01:21:28 PM PDT 24
Finished Apr 23 01:21:30 PM PDT 24
Peak memory 203580 kb
Host smart-76e165ab-39b2-42df-985e-35013f2a159f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241272382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt
.241272382
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.73915351
Short name T441
Test name
Test status
Simulation time 159011855 ps
CPU time 3.25 seconds
Started Apr 23 01:21:32 PM PDT 24
Finished Apr 23 01:21:36 PM PDT 24
Peak memory 203708 kb
Host smart-f3b9cbbc-fa9b-4b67-9d6d-b25f3751d207
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73915351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.73915351
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.387325111
Short name T921
Test name
Test status
Simulation time 3159440268 ps
CPU time 228.39 seconds
Started Apr 23 01:21:28 PM PDT 24
Finished Apr 23 01:25:17 PM PDT 24
Peak memory 966164 kb
Host smart-c0f439fa-8a78-4715-9321-94580f2b266f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387325111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.387325111
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.3120037817
Short name T560
Test name
Test status
Simulation time 357758465 ps
CPU time 4.65 seconds
Started Apr 23 01:21:37 PM PDT 24
Finished Apr 23 01:21:43 PM PDT 24
Peak memory 203648 kb
Host smart-317e896c-835d-4724-9877-55c2b460aaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120037817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.3120037817
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.622800649
Short name T460
Test name
Test status
Simulation time 1269771874 ps
CPU time 22.8 seconds
Started Apr 23 01:21:38 PM PDT 24
Finished Apr 23 01:22:01 PM PDT 24
Peak memory 349788 kb
Host smart-5de7633d-8284-4791-b99d-fe2ec2b3af35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622800649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.622800649
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.1884236873
Short name T440
Test name
Test status
Simulation time 118766565 ps
CPU time 0.67 seconds
Started Apr 23 01:21:29 PM PDT 24
Finished Apr 23 01:21:31 PM PDT 24
Peak memory 203284 kb
Host smart-c81e28fd-9cd1-4a7a-988e-d65a14bbed47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884236873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1884236873
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.2766166642
Short name T499
Test name
Test status
Simulation time 6569753439 ps
CPU time 67.66 seconds
Started Apr 23 01:21:32 PM PDT 24
Finished Apr 23 01:22:41 PM PDT 24
Peak memory 216572 kb
Host smart-fce7328f-9c0d-4191-869d-f118b583da1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766166642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.2766166642
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.878132955
Short name T149
Test name
Test status
Simulation time 8537185533 ps
CPU time 18.46 seconds
Started Apr 23 01:21:27 PM PDT 24
Finished Apr 23 01:21:46 PM PDT 24
Peak memory 312904 kb
Host smart-65d87e40-643e-4a05-b8bf-41cd51cd04b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878132955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.878132955
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.1434333191
Short name T893
Test name
Test status
Simulation time 896261208 ps
CPU time 16.02 seconds
Started Apr 23 01:21:30 PM PDT 24
Finished Apr 23 01:21:46 PM PDT 24
Peak memory 228280 kb
Host smart-d581331b-65a1-4be1-ad18-ef371b7befe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434333191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.1434333191
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.3796517450
Short name T121
Test name
Test status
Simulation time 185260907 ps
CPU time 0.94 seconds
Started Apr 23 01:21:36 PM PDT 24
Finished Apr 23 01:21:38 PM PDT 24
Peak memory 222072 kb
Host smart-e4449c63-ba08-47a1-b89e-3912c816dc34
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796517450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.3796517450
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.1888577256
Short name T686
Test name
Test status
Simulation time 1763026228 ps
CPU time 4.12 seconds
Started Apr 23 01:21:33 PM PDT 24
Finished Apr 23 01:21:38 PM PDT 24
Peak memory 203736 kb
Host smart-387c2f57-e2f1-4976-8085-e255bce6210b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888577256 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.1888577256
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.27148963
Short name T628
Test name
Test status
Simulation time 10092452489 ps
CPU time 12.87 seconds
Started Apr 23 01:21:32 PM PDT 24
Finished Apr 23 01:21:45 PM PDT 24
Peak memory 275892 kb
Host smart-f43f7491-75fa-49d2-9c95-7d4c85cd5894
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27148963 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_fifo_reset_acq.27148963
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.907796464
Short name T564
Test name
Test status
Simulation time 10337961117 ps
CPU time 15.57 seconds
Started Apr 23 01:21:37 PM PDT 24
Finished Apr 23 01:21:54 PM PDT 24
Peak memory 308108 kb
Host smart-f02823db-72f7-4074-b97a-21940dbd5bf4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907796464 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_fifo_reset_tx.907796464
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.1181824635
Short name T389
Test name
Test status
Simulation time 399117602 ps
CPU time 2.36 seconds
Started Apr 23 01:21:33 PM PDT 24
Finished Apr 23 01:21:36 PM PDT 24
Peak memory 203724 kb
Host smart-5ca6df8e-01ec-4145-b1f6-076a29746e69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181824635 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.1181824635
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.2552576301
Short name T1136
Test name
Test status
Simulation time 2732532451 ps
CPU time 3.51 seconds
Started Apr 23 01:21:36 PM PDT 24
Finished Apr 23 01:21:40 PM PDT 24
Peak memory 204844 kb
Host smart-df401fe8-5d6b-4426-899e-36843c6622dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552576301 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.2552576301
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.3054301735
Short name T1310
Test name
Test status
Simulation time 23208155166 ps
CPU time 455.18 seconds
Started Apr 23 01:21:33 PM PDT 24
Finished Apr 23 01:29:09 PM PDT 24
Peak memory 5144988 kb
Host smart-2954e032-1058-4e6c-b83f-59589e91bb17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054301735 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.3054301735
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1722133356
Short name T873
Test name
Test status
Simulation time 972086296 ps
CPU time 12.29 seconds
Started Apr 23 01:21:32 PM PDT 24
Finished Apr 23 01:21:45 PM PDT 24
Peak memory 203644 kb
Host smart-ed2bb1fb-c478-4d37-aa93-6e1947246af5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722133356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1722133356
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.2187693194
Short name T978
Test name
Test status
Simulation time 3006749945 ps
CPU time 27.59 seconds
Started Apr 23 01:21:33 PM PDT 24
Finished Apr 23 01:22:01 PM PDT 24
Peak memory 221704 kb
Host smart-78d2b506-0e9b-42bb-b0c2-023b258bc780
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187693194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.2187693194
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.662935598
Short name T521
Test name
Test status
Simulation time 54123087255 ps
CPU time 1389.49 seconds
Started Apr 23 01:21:38 PM PDT 24
Finished Apr 23 01:44:49 PM PDT 24
Peak memory 8555912 kb
Host smart-25002102-ddbb-47d6-acc0-954667b71ed2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662935598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_wr.662935598
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.4102699986
Short name T833
Test name
Test status
Simulation time 8714352749 ps
CPU time 843.51 seconds
Started Apr 23 01:21:32 PM PDT 24
Finished Apr 23 01:35:36 PM PDT 24
Peak memory 2153300 kb
Host smart-e01d1ef8-bbfe-4a9b-bf4c-4b07f49f8cd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102699986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.4102699986
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.2901352016
Short name T550
Test name
Test status
Simulation time 2879489010 ps
CPU time 6.57 seconds
Started Apr 23 01:21:36 PM PDT 24
Finished Apr 23 01:21:44 PM PDT 24
Peak memory 220076 kb
Host smart-7d52cc65-956c-45a6-8346-fbc169e7bb56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901352016 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.2901352016
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.3240657603
Short name T1036
Test name
Test status
Simulation time 24652185 ps
CPU time 0.6 seconds
Started Apr 23 01:22:58 PM PDT 24
Finished Apr 23 01:22:59 PM PDT 24
Peak memory 203288 kb
Host smart-de83eb8b-3a6c-4095-952c-591ece85197b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240657603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.3240657603
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.2132267206
Short name T920
Test name
Test status
Simulation time 291757327 ps
CPU time 1.3 seconds
Started Apr 23 01:22:50 PM PDT 24
Finished Apr 23 01:22:52 PM PDT 24
Peak memory 203812 kb
Host smart-c325cc90-edf5-498f-9dfa-485d3d08cd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132267206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2132267206
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.2197931486
Short name T1293
Test name
Test status
Simulation time 1106300134 ps
CPU time 13.61 seconds
Started Apr 23 01:22:48 PM PDT 24
Finished Apr 23 01:23:02 PM PDT 24
Peak memory 242620 kb
Host smart-9830a924-3bf8-4666-a1ca-5cc3fd2dcaf0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197931486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.2197931486
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.3182984020
Short name T1192
Test name
Test status
Simulation time 9684876551 ps
CPU time 38.13 seconds
Started Apr 23 01:22:46 PM PDT 24
Finished Apr 23 01:23:25 PM PDT 24
Peak memory 475644 kb
Host smart-9a8e1da2-5bd5-4ab9-a4d1-5c11e2a55295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182984020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.3182984020
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.1558773057
Short name T88
Test name
Test status
Simulation time 2100146520 ps
CPU time 77.39 seconds
Started Apr 23 01:22:48 PM PDT 24
Finished Apr 23 01:24:06 PM PDT 24
Peak memory 712960 kb
Host smart-31621d1a-bbe9-4010-b95f-da53ddb2288a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558773057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1558773057
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1299485193
Short name T374
Test name
Test status
Simulation time 569025079 ps
CPU time 9.26 seconds
Started Apr 23 01:22:53 PM PDT 24
Finished Apr 23 01:23:03 PM PDT 24
Peak memory 232604 kb
Host smart-b490605c-0829-4f71-8335-fe7ea7f002d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299485193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1299485193
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.3237255052
Short name T171
Test name
Test status
Simulation time 3281230620 ps
CPU time 66.99 seconds
Started Apr 23 01:22:48 PM PDT 24
Finished Apr 23 01:23:56 PM PDT 24
Peak memory 878960 kb
Host smart-42b546e9-17dd-4234-b258-cdc17473b72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237255052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.3237255052
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.4157053876
Short name T857
Test name
Test status
Simulation time 320521895 ps
CPU time 4.93 seconds
Started Apr 23 01:22:57 PM PDT 24
Finished Apr 23 01:23:03 PM PDT 24
Peak memory 203748 kb
Host smart-eba3b599-bf68-4fab-889e-af1ad28db878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157053876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.4157053876
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.1430918995
Short name T65
Test name
Test status
Simulation time 1852155106 ps
CPU time 18.24 seconds
Started Apr 23 01:22:59 PM PDT 24
Finished Apr 23 01:23:17 PM PDT 24
Peak memory 281772 kb
Host smart-79e3e640-b7d1-4df4-a2d7-705611c96dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430918995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.1430918995
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.998459484
Short name T815
Test name
Test status
Simulation time 16649159 ps
CPU time 0.64 seconds
Started Apr 23 01:22:52 PM PDT 24
Finished Apr 23 01:22:53 PM PDT 24
Peak memory 203372 kb
Host smart-5e263c5b-6fd6-4db4-a2b3-6510a93d5fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998459484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.998459484
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.622518486
Short name T720
Test name
Test status
Simulation time 72705684383 ps
CPU time 718.53 seconds
Started Apr 23 01:22:50 PM PDT 24
Finished Apr 23 01:34:50 PM PDT 24
Peak memory 203724 kb
Host smart-1f9b61e3-5d7c-46d6-a98f-8f7b0a3eca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622518486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.622518486
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.3012105511
Short name T682
Test name
Test status
Simulation time 1162692259 ps
CPU time 32.21 seconds
Started Apr 23 01:22:54 PM PDT 24
Finished Apr 23 01:23:27 PM PDT 24
Peak memory 260744 kb
Host smart-8d137726-4438-4a23-9408-af23c83c8f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012105511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.3012105511
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.2458015588
Short name T503
Test name
Test status
Simulation time 33941729514 ps
CPU time 2050.31 seconds
Started Apr 23 01:22:50 PM PDT 24
Finished Apr 23 01:57:02 PM PDT 24
Peak memory 2235064 kb
Host smart-f4eba934-a2dd-4ddc-87b0-90835e5290c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458015588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.2458015588
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.1781986550
Short name T1086
Test name
Test status
Simulation time 628287627 ps
CPU time 10.35 seconds
Started Apr 23 01:22:52 PM PDT 24
Finished Apr 23 01:23:02 PM PDT 24
Peak memory 220128 kb
Host smart-0da8d59d-0db9-42f6-8ebb-8f16a7dd8ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781986550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.1781986550
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.3663507241
Short name T943
Test name
Test status
Simulation time 1049540418 ps
CPU time 2.91 seconds
Started Apr 23 01:22:55 PM PDT 24
Finished Apr 23 01:22:58 PM PDT 24
Peak memory 203672 kb
Host smart-e633ab92-91e4-445a-92eb-2b617241f5b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663507241 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.3663507241
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.2696370703
Short name T845
Test name
Test status
Simulation time 10063018555 ps
CPU time 63.02 seconds
Started Apr 23 01:22:55 PM PDT 24
Finished Apr 23 01:23:58 PM PDT 24
Peak memory 457736 kb
Host smart-fd209e70-7b8a-4942-a604-616b1c5eb6be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696370703 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.2696370703
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.3757706701
Short name T524
Test name
Test status
Simulation time 2782554254 ps
CPU time 1.88 seconds
Started Apr 23 01:22:54 PM PDT 24
Finished Apr 23 01:22:57 PM PDT 24
Peak memory 203704 kb
Host smart-aec9f880-ffb7-4d6c-b124-22f42ffd3715
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757706701 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.3757706701
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.686932142
Short name T506
Test name
Test status
Simulation time 5849976831 ps
CPU time 6.89 seconds
Started Apr 23 01:22:51 PM PDT 24
Finished Apr 23 01:22:58 PM PDT 24
Peak memory 218900 kb
Host smart-ba6a4023-83eb-47da-bab2-124478135de3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686932142 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_intr_smoke.686932142
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.1610626327
Short name T1280
Test name
Test status
Simulation time 4450087533 ps
CPU time 15.95 seconds
Started Apr 23 01:22:53 PM PDT 24
Finished Apr 23 01:23:10 PM PDT 24
Peak memory 671712 kb
Host smart-b7d2ec01-4c6a-4d36-ae79-9408156a537d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610626327 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.1610626327
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2081591322
Short name T417
Test name
Test status
Simulation time 1252143388 ps
CPU time 53.45 seconds
Started Apr 23 01:22:51 PM PDT 24
Finished Apr 23 01:23:45 PM PDT 24
Peak memory 203676 kb
Host smart-1cdddf98-588c-4501-b511-82f703b71f5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081591322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2081591322
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.2709370427
Short name T917
Test name
Test status
Simulation time 5782242289 ps
CPU time 64.78 seconds
Started Apr 23 01:22:52 PM PDT 24
Finished Apr 23 01:23:57 PM PDT 24
Peak memory 206564 kb
Host smart-b21c7c51-5cb8-4a51-8b9b-c945e272ab97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709370427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.2709370427
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.616525633
Short name T182
Test name
Test status
Simulation time 9048738021 ps
CPU time 11.67 seconds
Started Apr 23 01:22:52 PM PDT 24
Finished Apr 23 01:23:04 PM PDT 24
Peak memory 203728 kb
Host smart-0b1877d9-a05a-4057-99b9-fad9cb4d4def
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616525633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c
_target_stress_wr.616525633
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.2462509044
Short name T361
Test name
Test status
Simulation time 10227330157 ps
CPU time 112.8 seconds
Started Apr 23 01:22:52 PM PDT 24
Finished Apr 23 01:24:46 PM PDT 24
Peak memory 631316 kb
Host smart-5d9c4f76-1cad-4bed-9919-d068ef30ff65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462509044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.2462509044
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.421394486
Short name T654
Test name
Test status
Simulation time 5787366593 ps
CPU time 7.3 seconds
Started Apr 23 01:23:00 PM PDT 24
Finished Apr 23 01:23:07 PM PDT 24
Peak memory 211924 kb
Host smart-adb8671d-b4af-4abb-9660-0b3cd90835b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421394486 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_timeout.421394486
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.3118300678
Short name T391
Test name
Test status
Simulation time 37567176 ps
CPU time 0.65 seconds
Started Apr 23 01:23:04 PM PDT 24
Finished Apr 23 01:23:05 PM PDT 24
Peak memory 203400 kb
Host smart-e25b487e-ef76-401b-a9c3-05ae081ebcb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118300678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.3118300678
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.833860539
Short name T1186
Test name
Test status
Simulation time 124206324 ps
CPU time 1.45 seconds
Started Apr 23 01:23:01 PM PDT 24
Finished Apr 23 01:23:03 PM PDT 24
Peak memory 212004 kb
Host smart-2e0ba67c-025b-4565-8239-03a5c88f8651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833860539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.833860539
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.46021229
Short name T593
Test name
Test status
Simulation time 1558648918 ps
CPU time 21.61 seconds
Started Apr 23 01:22:58 PM PDT 24
Finished Apr 23 01:23:20 PM PDT 24
Peak memory 289220 kb
Host smart-cfd1ecf6-6004-4c41-ac7d-fcfaa4d1c278
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46021229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empty
.46021229
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.2424822774
Short name T422
Test name
Test status
Simulation time 1925228511 ps
CPU time 49.49 seconds
Started Apr 23 01:22:56 PM PDT 24
Finished Apr 23 01:23:46 PM PDT 24
Peak memory 362156 kb
Host smart-5ba61e80-c10c-4f10-b7e4-067c09d17e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424822774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.2424822774
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.3745111734
Short name T698
Test name
Test status
Simulation time 7740507867 ps
CPU time 41.52 seconds
Started Apr 23 01:22:55 PM PDT 24
Finished Apr 23 01:23:37 PM PDT 24
Peak memory 455112 kb
Host smart-f04734a7-52eb-4387-ac44-9edc0c389ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745111734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.3745111734
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.653922136
Short name T863
Test name
Test status
Simulation time 142711863 ps
CPU time 1.02 seconds
Started Apr 23 01:23:00 PM PDT 24
Finished Apr 23 01:23:01 PM PDT 24
Peak memory 203640 kb
Host smart-cf5fd84b-1bdc-4944-9b29-9f2addcfd875
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653922136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fm
t.653922136
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.4126519686
Short name T687
Test name
Test status
Simulation time 222169887 ps
CPU time 6.3 seconds
Started Apr 23 01:22:57 PM PDT 24
Finished Apr 23 01:23:04 PM PDT 24
Peak memory 219668 kb
Host smart-6beae76c-abdf-4532-82d6-2c0f94473d33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126519686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.4126519686
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.352042133
Short name T473
Test name
Test status
Simulation time 3276039254 ps
CPU time 92.39 seconds
Started Apr 23 01:22:58 PM PDT 24
Finished Apr 23 01:24:31 PM PDT 24
Peak memory 1016068 kb
Host smart-6742c70c-71bf-4d96-9745-bc7e7e31d5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352042133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.352042133
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.1940169858
Short name T717
Test name
Test status
Simulation time 683568460 ps
CPU time 13.96 seconds
Started Apr 23 01:23:04 PM PDT 24
Finished Apr 23 01:23:18 PM PDT 24
Peak memory 203616 kb
Host smart-6f1928da-79f8-487d-ab60-5ce69038db9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940169858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.1940169858
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.1776210899
Short name T107
Test name
Test status
Simulation time 950146940 ps
CPU time 43.81 seconds
Started Apr 23 01:23:03 PM PDT 24
Finished Apr 23 01:23:48 PM PDT 24
Peak memory 284776 kb
Host smart-b6e42665-aae4-4702-9335-923b68bc6e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776210899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.1776210899
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.2619676393
Short name T192
Test name
Test status
Simulation time 20081958 ps
CPU time 0.66 seconds
Started Apr 23 01:22:58 PM PDT 24
Finished Apr 23 01:23:00 PM PDT 24
Peak memory 203404 kb
Host smart-f99aca36-5327-4bf3-a6e2-fe8430bac2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619676393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.2619676393
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.2408466814
Short name T1191
Test name
Test status
Simulation time 13203607363 ps
CPU time 504.12 seconds
Started Apr 23 01:22:57 PM PDT 24
Finished Apr 23 01:31:22 PM PDT 24
Peak memory 203764 kb
Host smart-6515bbf6-1fdd-428e-bde5-c4cb1dd87dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408466814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.2408466814
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.1010682476
Short name T467
Test name
Test status
Simulation time 29574978023 ps
CPU time 32.97 seconds
Started Apr 23 01:22:57 PM PDT 24
Finished Apr 23 01:23:30 PM PDT 24
Peak memory 351456 kb
Host smart-a8c97f51-5f7b-407b-aeb3-76430ffe3e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010682476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.1010682476
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.109339822
Short name T180
Test name
Test status
Simulation time 16051668407 ps
CPU time 123.76 seconds
Started Apr 23 01:23:00 PM PDT 24
Finished Apr 23 01:25:04 PM PDT 24
Peak memory 638488 kb
Host smart-ef750870-4c5c-41b8-b936-72152f3723a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109339822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.109339822
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.1062876502
Short name T684
Test name
Test status
Simulation time 1367941867 ps
CPU time 12.8 seconds
Started Apr 23 01:22:57 PM PDT 24
Finished Apr 23 01:23:10 PM PDT 24
Peak memory 216348 kb
Host smart-bf8ff3e1-4f48-4a01-aa18-9d1a31b16b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062876502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.1062876502
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.1422892451
Short name T782
Test name
Test status
Simulation time 672550853 ps
CPU time 2.98 seconds
Started Apr 23 01:23:03 PM PDT 24
Finished Apr 23 01:23:06 PM PDT 24
Peak memory 203716 kb
Host smart-243aacb8-c42d-44b8-89dc-51a36cb51341
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422892451 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.1422892451
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.1226534233
Short name T52
Test name
Test status
Simulation time 10105712563 ps
CPU time 54.16 seconds
Started Apr 23 01:23:01 PM PDT 24
Finished Apr 23 01:23:56 PM PDT 24
Peak memory 488464 kb
Host smart-d7b5ae0d-7008-42f5-80f9-f4e1ad10d30d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226534233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.1226534233
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.4279503757
Short name T1332
Test name
Test status
Simulation time 10056275870 ps
CPU time 12.95 seconds
Started Apr 23 01:23:01 PM PDT 24
Finished Apr 23 01:23:14 PM PDT 24
Peak memory 270612 kb
Host smart-8f55cd1d-0533-4647-9a93-92b41502c635
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279503757 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.4279503757
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.870320122
Short name T18
Test name
Test status
Simulation time 1459999055 ps
CPU time 2.42 seconds
Started Apr 23 01:23:02 PM PDT 24
Finished Apr 23 01:23:05 PM PDT 24
Peak memory 203756 kb
Host smart-ae2ba8cd-a3b3-4bb7-a88e-e97af3eda86a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870320122 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_hrst.870320122
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.3610219113
Short name T1155
Test name
Test status
Simulation time 1608840543 ps
CPU time 4.67 seconds
Started Apr 23 01:23:00 PM PDT 24
Finished Apr 23 01:23:06 PM PDT 24
Peak memory 203680 kb
Host smart-6020120a-0cf7-4e63-bad8-c290694d879d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610219113 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.3610219113
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.1997095127
Short name T1283
Test name
Test status
Simulation time 10885671015 ps
CPU time 61.37 seconds
Started Apr 23 01:23:00 PM PDT 24
Finished Apr 23 01:24:02 PM PDT 24
Peak memory 1105924 kb
Host smart-7b758e70-de13-421f-8f13-742156d01d52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997095127 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.1997095127
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.394539449
Short name T776
Test name
Test status
Simulation time 3754369960 ps
CPU time 11.81 seconds
Started Apr 23 01:22:59 PM PDT 24
Finished Apr 23 01:23:12 PM PDT 24
Peak memory 203740 kb
Host smart-b6fc289d-fc83-4cad-8ed6-e8a8525009fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394539449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_tar
get_smoke.394539449
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.429123843
Short name T1197
Test name
Test status
Simulation time 4726312673 ps
CPU time 22.74 seconds
Started Apr 23 01:23:00 PM PDT 24
Finished Apr 23 01:23:23 PM PDT 24
Peak memory 215868 kb
Host smart-cb5b750b-b960-43b2-a3dd-21ea4ed7ea7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429123843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_rd.429123843
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.2139830503
Short name T444
Test name
Test status
Simulation time 42047687104 ps
CPU time 266.58 seconds
Started Apr 23 01:23:01 PM PDT 24
Finished Apr 23 01:27:28 PM PDT 24
Peak memory 2847592 kb
Host smart-6ba6d614-2ee8-4381-934a-ae1f8e5d19d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139830503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.2139830503
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.3326823206
Short name T1038
Test name
Test status
Simulation time 5604900815 ps
CPU time 27.15 seconds
Started Apr 23 01:23:01 PM PDT 24
Finished Apr 23 01:23:29 PM PDT 24
Peak memory 556760 kb
Host smart-4a39d862-d70b-4d53-9c2d-c6c6fedd8962
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326823206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.3326823206
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.1323968536
Short name T580
Test name
Test status
Simulation time 2855321591 ps
CPU time 6.58 seconds
Started Apr 23 01:23:02 PM PDT 24
Finished Apr 23 01:23:09 PM PDT 24
Peak memory 203856 kb
Host smart-3b3980c2-2210-4d0f-95d1-ae7a60e98592
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323968536 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.1323968536
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.2553164895
Short name T885
Test name
Test status
Simulation time 55031039 ps
CPU time 0.6 seconds
Started Apr 23 01:23:15 PM PDT 24
Finished Apr 23 01:23:17 PM PDT 24
Peak memory 203260 kb
Host smart-47002e85-0cf4-4784-9b6e-c7ce580c3f61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553164895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.2553164895
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3402802343
Short name T658
Test name
Test status
Simulation time 261717939 ps
CPU time 1.27 seconds
Started Apr 23 01:23:09 PM PDT 24
Finished Apr 23 01:23:11 PM PDT 24
Peak memory 212004 kb
Host smart-3169360c-704d-4c7c-8051-9cb614c98100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402802343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3402802343
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3929993180
Short name T1026
Test name
Test status
Simulation time 180545199 ps
CPU time 9.32 seconds
Started Apr 23 01:23:07 PM PDT 24
Finished Apr 23 01:23:17 PM PDT 24
Peak memory 238264 kb
Host smart-1e7fe7d2-92f7-424a-965d-5c8f02817c5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929993180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3929993180
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.3563629411
Short name T862
Test name
Test status
Simulation time 3486182478 ps
CPU time 60.92 seconds
Started Apr 23 01:23:10 PM PDT 24
Finished Apr 23 01:24:11 PM PDT 24
Peak memory 621664 kb
Host smart-9a14b652-1a93-4577-9bec-6abac474e058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563629411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3563629411
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.1848912807
Short name T1118
Test name
Test status
Simulation time 3556910693 ps
CPU time 38.68 seconds
Started Apr 23 01:23:07 PM PDT 24
Finished Apr 23 01:23:46 PM PDT 24
Peak memory 559000 kb
Host smart-fcd831bc-8b56-435a-b5c7-73d843097b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848912807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.1848912807
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.2916576202
Short name T1167
Test name
Test status
Simulation time 198159141 ps
CPU time 1.01 seconds
Started Apr 23 01:23:10 PM PDT 24
Finished Apr 23 01:23:11 PM PDT 24
Peak memory 203380 kb
Host smart-02d9bdc3-b7ed-4489-b330-aef5a14d8e43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916576202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.2916576202
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.1500728100
Short name T1065
Test name
Test status
Simulation time 6147803987 ps
CPU time 207.91 seconds
Started Apr 23 01:23:07 PM PDT 24
Finished Apr 23 01:26:35 PM PDT 24
Peak memory 917404 kb
Host smart-9e19d064-b890-439b-b016-01584f457f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500728100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1500728100
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.1445205573
Short name T1250
Test name
Test status
Simulation time 2806891148 ps
CPU time 14.92 seconds
Started Apr 23 01:23:15 PM PDT 24
Finished Apr 23 01:23:30 PM PDT 24
Peak memory 203780 kb
Host smart-889c8d13-8f4c-40ab-a611-d266e2b7e151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445205573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.1445205573
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.3354089974
Short name T835
Test name
Test status
Simulation time 3706869574 ps
CPU time 62.49 seconds
Started Apr 23 01:23:13 PM PDT 24
Finished Apr 23 01:24:16 PM PDT 24
Peak memory 304896 kb
Host smart-50563d37-923c-4a5a-8d2a-d1b8613263bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354089974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.3354089974
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.1860147767
Short name T1320
Test name
Test status
Simulation time 147962783 ps
CPU time 0.67 seconds
Started Apr 23 01:23:04 PM PDT 24
Finished Apr 23 01:23:05 PM PDT 24
Peak memory 203264 kb
Host smart-00144430-8630-4c3b-8f88-9db6d887da9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860147767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.1860147767
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.2624207742
Short name T993
Test name
Test status
Simulation time 7015936982 ps
CPU time 11.24 seconds
Started Apr 23 01:23:07 PM PDT 24
Finished Apr 23 01:23:19 PM PDT 24
Peak memory 232616 kb
Host smart-507053aa-e254-4597-b175-535ecdabf50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624207742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2624207742
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.1116856901
Short name T537
Test name
Test status
Simulation time 1437654653 ps
CPU time 15.46 seconds
Started Apr 23 01:23:04 PM PDT 24
Finished Apr 23 01:23:21 PM PDT 24
Peak memory 265104 kb
Host smart-80c05f7d-1d40-4a3d-bf32-5535661bd6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116856901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.1116856901
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.2927265974
Short name T1107
Test name
Test status
Simulation time 1374494910 ps
CPU time 26.26 seconds
Started Apr 23 01:23:06 PM PDT 24
Finished Apr 23 01:23:33 PM PDT 24
Peak memory 212008 kb
Host smart-eaa50e39-ce38-452f-a8cd-5dd6625ca05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927265974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.2927265974
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.3592801649
Short name T258
Test name
Test status
Simulation time 467339768 ps
CPU time 2.62 seconds
Started Apr 23 01:23:11 PM PDT 24
Finished Apr 23 01:23:14 PM PDT 24
Peak memory 203772 kb
Host smart-82d13319-490b-454c-9f6c-5cc2d89fa48d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592801649 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.3592801649
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.1848080155
Short name T832
Test name
Test status
Simulation time 10255162135 ps
CPU time 11.62 seconds
Started Apr 23 01:23:09 PM PDT 24
Finished Apr 23 01:23:22 PM PDT 24
Peak memory 255324 kb
Host smart-6f6f4f42-4504-4120-b8b1-06e970d5df91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848080155 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.1848080155
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.3873749859
Short name T1239
Test name
Test status
Simulation time 10058253675 ps
CPU time 86.35 seconds
Started Apr 23 01:23:11 PM PDT 24
Finished Apr 23 01:24:38 PM PDT 24
Peak memory 531492 kb
Host smart-1d4ae12a-bace-436a-a104-993ffddd726e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873749859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.3873749859
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.1232849551
Short name T1337
Test name
Test status
Simulation time 3582202076 ps
CPU time 3.82 seconds
Started Apr 23 01:23:13 PM PDT 24
Finished Apr 23 01:23:17 PM PDT 24
Peak memory 205004 kb
Host smart-6f673665-da25-4f2a-b8de-c1be085ebc04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232849551 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.1232849551
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.1987720458
Short name T505
Test name
Test status
Simulation time 18635987255 ps
CPU time 42.93 seconds
Started Apr 23 01:23:15 PM PDT 24
Finished Apr 23 01:23:59 PM PDT 24
Peak memory 1093640 kb
Host smart-8636d450-ca49-4ef3-b748-d7ece7120894
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987720458 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.1987720458
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.1642130510
Short name T525
Test name
Test status
Simulation time 3239853582 ps
CPU time 13.68 seconds
Started Apr 23 01:23:10 PM PDT 24
Finished Apr 23 01:23:25 PM PDT 24
Peak memory 203704 kb
Host smart-965d1e69-ee7e-4e95-931c-54516075513a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642130510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.1642130510
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.2806197103
Short name T802
Test name
Test status
Simulation time 3543417362 ps
CPU time 15.38 seconds
Started Apr 23 01:23:10 PM PDT 24
Finished Apr 23 01:23:27 PM PDT 24
Peak memory 216596 kb
Host smart-70ff17d0-c190-4a51-9157-ab030df58e17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806197103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.2806197103
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.2164637778
Short name T1099
Test name
Test status
Simulation time 55192268971 ps
CPU time 1732.77 seconds
Started Apr 23 01:23:12 PM PDT 24
Finished Apr 23 01:52:06 PM PDT 24
Peak memory 8997732 kb
Host smart-1129cfea-ebb3-4e7a-a4b8-40d561a78e0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164637778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.2164637778
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.1121110004
Short name T515
Test name
Test status
Simulation time 37490157829 ps
CPU time 245.21 seconds
Started Apr 23 01:23:12 PM PDT 24
Finished Apr 23 01:27:18 PM PDT 24
Peak memory 2134988 kb
Host smart-352f5f0e-a5a8-40db-adee-a1c8b83d6796
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121110004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.1121110004
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.2048941837
Short name T1273
Test name
Test status
Simulation time 6236571609 ps
CPU time 6.02 seconds
Started Apr 23 01:23:11 PM PDT 24
Finished Apr 23 01:23:17 PM PDT 24
Peak memory 203704 kb
Host smart-8714fc0e-9dc5-4453-9639-ad73578ac5f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048941837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.2048941837
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.1921401089
Short name T706
Test name
Test status
Simulation time 77799626 ps
CPU time 0.63 seconds
Started Apr 23 01:23:22 PM PDT 24
Finished Apr 23 01:23:23 PM PDT 24
Peak memory 203324 kb
Host smart-77c10b05-ff8f-43f9-9076-12bc04acd6a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921401089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.1921401089
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.3925155255
Short name T544
Test name
Test status
Simulation time 234162222 ps
CPU time 1.64 seconds
Started Apr 23 01:23:15 PM PDT 24
Finished Apr 23 01:23:18 PM PDT 24
Peak memory 212004 kb
Host smart-b5125676-bf21-4c42-b380-db9e43f963f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925155255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.3925155255
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.2135630830
Short name T896
Test name
Test status
Simulation time 274797771 ps
CPU time 5.94 seconds
Started Apr 23 01:23:15 PM PDT 24
Finished Apr 23 01:23:22 PM PDT 24
Peak memory 256024 kb
Host smart-99a9e5e2-0395-4dfd-9185-aa3b75ad4755
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135630830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.2135630830
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.1575872878
Short name T363
Test name
Test status
Simulation time 2488650411 ps
CPU time 80.61 seconds
Started Apr 23 01:23:15 PM PDT 24
Finished Apr 23 01:24:37 PM PDT 24
Peak memory 805296 kb
Host smart-c22d60f9-cc1d-42d6-af6c-cc67af6c796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575872878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1575872878
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.527657791
Short name T1232
Test name
Test status
Simulation time 2912568718 ps
CPU time 45.61 seconds
Started Apr 23 01:23:15 PM PDT 24
Finished Apr 23 01:24:02 PM PDT 24
Peak memory 552432 kb
Host smart-3f13ab9b-6fa9-4335-909e-4b96175cd0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527657791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.527657791
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.3748155262
Short name T205
Test name
Test status
Simulation time 663880080 ps
CPU time 0.99 seconds
Started Apr 23 01:23:16 PM PDT 24
Finished Apr 23 01:23:18 PM PDT 24
Peak memory 203608 kb
Host smart-0cf82721-3b87-4e8c-a7df-c268e2143dbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748155262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.3748155262
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.481934745
Short name T89
Test name
Test status
Simulation time 297153298 ps
CPU time 4.01 seconds
Started Apr 23 01:23:15 PM PDT 24
Finished Apr 23 01:23:20 PM PDT 24
Peak memory 203556 kb
Host smart-0cd5453e-5af3-41b1-a6f3-0bb4e0e97895
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481934745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.
481934745
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.241744305
Short name T173
Test name
Test status
Simulation time 17009647220 ps
CPU time 106.93 seconds
Started Apr 23 01:23:16 PM PDT 24
Finished Apr 23 01:25:04 PM PDT 24
Peak memory 1240604 kb
Host smart-21d7950d-693d-43e6-be4a-2f63d20fabd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241744305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.241744305
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.1004440572
Short name T817
Test name
Test status
Simulation time 639681490 ps
CPU time 13.43 seconds
Started Apr 23 01:23:21 PM PDT 24
Finished Apr 23 01:23:35 PM PDT 24
Peak memory 203652 kb
Host smart-ce8112aa-88b3-4869-b26a-f286a89070e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004440572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.1004440572
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.3634353460
Short name T1140
Test name
Test status
Simulation time 1609649199 ps
CPU time 25.1 seconds
Started Apr 23 01:23:23 PM PDT 24
Finished Apr 23 01:23:49 PM PDT 24
Peak memory 309216 kb
Host smart-043ab320-ae62-4686-a9d4-7eb53f5078cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634353460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.3634353460
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.651346008
Short name T906
Test name
Test status
Simulation time 203836746 ps
CPU time 0.68 seconds
Started Apr 23 01:23:14 PM PDT 24
Finished Apr 23 01:23:15 PM PDT 24
Peak memory 203316 kb
Host smart-ecacaa6d-c477-4a99-a438-8d4beb821a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651346008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.651346008
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.2797173987
Short name T77
Test name
Test status
Simulation time 3101969944 ps
CPU time 88.24 seconds
Started Apr 23 01:23:16 PM PDT 24
Finished Apr 23 01:24:45 PM PDT 24
Peak memory 532988 kb
Host smart-0ef95b3d-9d45-4006-9846-bfbd1a56a04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797173987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.2797173987
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.415822302
Short name T613
Test name
Test status
Simulation time 1658091288 ps
CPU time 81.56 seconds
Started Apr 23 01:23:13 PM PDT 24
Finished Apr 23 01:24:35 PM PDT 24
Peak memory 332940 kb
Host smart-6e9df610-76e3-4ea1-aa22-6d19bc22b589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415822302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.415822302
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.2040425698
Short name T725
Test name
Test status
Simulation time 551088176 ps
CPU time 10.59 seconds
Started Apr 23 01:23:15 PM PDT 24
Finished Apr 23 01:23:27 PM PDT 24
Peak memory 212000 kb
Host smart-3c3af238-ff41-402a-b141-ba146a019dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040425698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.2040425698
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.3320176727
Short name T324
Test name
Test status
Simulation time 4315225452 ps
CPU time 4.41 seconds
Started Apr 23 01:23:22 PM PDT 24
Finished Apr 23 01:23:28 PM PDT 24
Peak memory 211968 kb
Host smart-9204edb9-b096-4aae-8773-9bef67ee34e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320176727 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.3320176727
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.1019880609
Short name T1303
Test name
Test status
Simulation time 10084749482 ps
CPU time 79.11 seconds
Started Apr 23 01:23:18 PM PDT 24
Finished Apr 23 01:24:38 PM PDT 24
Peak memory 477672 kb
Host smart-7c9c5f4e-bf8a-48cd-995d-030cdfa1278f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019880609 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.1019880609
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.1317910123
Short name T909
Test name
Test status
Simulation time 10252199818 ps
CPU time 13.52 seconds
Started Apr 23 01:23:21 PM PDT 24
Finished Apr 23 01:23:35 PM PDT 24
Peak memory 282340 kb
Host smart-62c9a986-2bfa-4e58-9382-5f39e471f416
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317910123 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.1317910123
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.3873254646
Short name T17
Test name
Test status
Simulation time 352873628 ps
CPU time 2.2 seconds
Started Apr 23 01:23:19 PM PDT 24
Finished Apr 23 01:23:22 PM PDT 24
Peak memory 203676 kb
Host smart-4cbff8e7-b087-481d-aae4-fbf2ba60878d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873254646 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.3873254646
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.1127116354
Short name T707
Test name
Test status
Simulation time 10388237934 ps
CPU time 5.45 seconds
Started Apr 23 01:23:19 PM PDT 24
Finished Apr 23 01:23:25 PM PDT 24
Peak memory 218388 kb
Host smart-0dad19d3-66eb-460f-b4ea-0825c69ac91d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127116354 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.1127116354
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.3205754582
Short name T329
Test name
Test status
Simulation time 10546494429 ps
CPU time 163.4 seconds
Started Apr 23 01:23:18 PM PDT 24
Finished Apr 23 01:26:02 PM PDT 24
Peak memory 2649472 kb
Host smart-02c16856-e94a-450a-8c7b-2f8d26ac2e49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205754582 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.3205754582
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.3926228492
Short name T1237
Test name
Test status
Simulation time 3523822309 ps
CPU time 14.34 seconds
Started Apr 23 01:23:18 PM PDT 24
Finished Apr 23 01:23:33 PM PDT 24
Peak memory 203680 kb
Host smart-9c5f2b0f-58f8-442e-ac38-c38185f45007
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926228492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.3926228492
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.4249792495
Short name T1154
Test name
Test status
Simulation time 2014310427 ps
CPU time 31.56 seconds
Started Apr 23 01:23:17 PM PDT 24
Finished Apr 23 01:23:49 PM PDT 24
Peak memory 229884 kb
Host smart-1f6cd27e-9cfc-4bdb-9875-4590d4214628
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249792495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.4249792495
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.1591573296
Short name T612
Test name
Test status
Simulation time 43211346046 ps
CPU time 23.1 seconds
Started Apr 23 01:23:18 PM PDT 24
Finished Apr 23 01:23:42 PM PDT 24
Peak memory 523132 kb
Host smart-7b172cba-8b79-4579-b841-1a585be540ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591573296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.1591573296
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.1420054088
Short name T1080
Test name
Test status
Simulation time 42935536424 ps
CPU time 154.32 seconds
Started Apr 23 01:23:19 PM PDT 24
Finished Apr 23 01:25:54 PM PDT 24
Peak memory 626976 kb
Host smart-7baeb999-7b25-400a-86f1-27593d41e23d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420054088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.1420054088
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.4263423173
Short name T678
Test name
Test status
Simulation time 2636222394 ps
CPU time 6.7 seconds
Started Apr 23 01:23:18 PM PDT 24
Finished Apr 23 01:23:26 PM PDT 24
Peak memory 219988 kb
Host smart-fe490963-b7f8-4b1d-b5a0-0ae7d6bbaf8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263423173 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.4263423173
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.531530337
Short name T1040
Test name
Test status
Simulation time 16699386 ps
CPU time 0.65 seconds
Started Apr 23 01:23:35 PM PDT 24
Finished Apr 23 01:23:36 PM PDT 24
Peak memory 203328 kb
Host smart-57a63f46-97d2-4248-a0fb-890bfa18bdae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531530337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.531530337
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.3631228617
Short name T866
Test name
Test status
Simulation time 71807144 ps
CPU time 1.64 seconds
Started Apr 23 01:23:27 PM PDT 24
Finished Apr 23 01:23:29 PM PDT 24
Peak memory 211964 kb
Host smart-00f777f3-e394-4066-bb56-8ff0d3042318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631228617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.3631228617
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.2715257111
Short name T6
Test name
Test status
Simulation time 323131372 ps
CPU time 16.54 seconds
Started Apr 23 01:23:24 PM PDT 24
Finished Apr 23 01:23:42 PM PDT 24
Peak memory 267188 kb
Host smart-4cd56f7c-d841-4b66-808f-0996a90b8716
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715257111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.2715257111
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.2907954384
Short name T341
Test name
Test status
Simulation time 1563553736 ps
CPU time 41.8 seconds
Started Apr 23 01:23:24 PM PDT 24
Finished Apr 23 01:24:06 PM PDT 24
Peak memory 505472 kb
Host smart-d1613790-f0aa-4f33-b827-54286df8eff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907954384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.2907954384
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.4284911096
Short name T1034
Test name
Test status
Simulation time 1133784569 ps
CPU time 31.2 seconds
Started Apr 23 01:23:24 PM PDT 24
Finished Apr 23 01:23:56 PM PDT 24
Peak memory 454844 kb
Host smart-c68d30b9-3d9d-45b7-8bce-3614016c1b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284911096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.4284911096
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.1674257768
Short name T898
Test name
Test status
Simulation time 112032095 ps
CPU time 0.99 seconds
Started Apr 23 01:23:24 PM PDT 24
Finished Apr 23 01:23:25 PM PDT 24
Peak memory 203344 kb
Host smart-bb66072a-a985-4993-a287-2bb918672455
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674257768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.1674257768
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.2663784556
Short name T311
Test name
Test status
Simulation time 153932624 ps
CPU time 8.71 seconds
Started Apr 23 01:23:26 PM PDT 24
Finished Apr 23 01:23:36 PM PDT 24
Peak memory 231868 kb
Host smart-ce77a48a-9360-4b1c-838c-b2504aef468e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663784556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.2663784556
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.91268398
Short name T934
Test name
Test status
Simulation time 13478921816 ps
CPU time 129.56 seconds
Started Apr 23 01:23:24 PM PDT 24
Finished Apr 23 01:25:34 PM PDT 24
Peak memory 1161408 kb
Host smart-ecbaf030-4c9b-47f7-b23d-e2729b7ce35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91268398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.91268398
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.2885571408
Short name T1235
Test name
Test status
Simulation time 408976889 ps
CPU time 17.91 seconds
Started Apr 23 01:23:33 PM PDT 24
Finished Apr 23 01:23:52 PM PDT 24
Peak memory 203660 kb
Host smart-638f4615-e2bd-4003-bfd2-2b3e15863b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885571408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2885571408
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.1570247795
Short name T1033
Test name
Test status
Simulation time 8078679113 ps
CPU time 33.24 seconds
Started Apr 23 01:23:33 PM PDT 24
Finished Apr 23 01:24:07 PM PDT 24
Peak memory 402176 kb
Host smart-3a40decc-59fe-406a-9bcd-270b60db4679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570247795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.1570247795
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.4068612863
Short name T1352
Test name
Test status
Simulation time 22994652 ps
CPU time 0.65 seconds
Started Apr 23 01:23:26 PM PDT 24
Finished Apr 23 01:23:27 PM PDT 24
Peak memory 203360 kb
Host smart-3a651567-3836-4521-9962-105355b62571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068612863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.4068612863
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.2436560605
Short name T788
Test name
Test status
Simulation time 2860715126 ps
CPU time 12.6 seconds
Started Apr 23 01:23:25 PM PDT 24
Finished Apr 23 01:23:38 PM PDT 24
Peak memory 220428 kb
Host smart-365c1fc0-58fe-41e1-ae01-7d7fec585e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436560605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.2436560605
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.524033165
Short name T903
Test name
Test status
Simulation time 4194020471 ps
CPU time 21.45 seconds
Started Apr 23 01:23:21 PM PDT 24
Finished Apr 23 01:23:43 PM PDT 24
Peak memory 317112 kb
Host smart-7d0b6a35-b558-44e1-9871-35f4a027c15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524033165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.524033165
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.2793563191
Short name T1156
Test name
Test status
Simulation time 1283756557 ps
CPU time 15.91 seconds
Started Apr 23 01:23:26 PM PDT 24
Finished Apr 23 01:23:43 PM PDT 24
Peak memory 220128 kb
Host smart-f1981c4c-1345-4db6-9e92-23f25c654f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793563191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.2793563191
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.2647325957
Short name T1020
Test name
Test status
Simulation time 897270071 ps
CPU time 4.23 seconds
Started Apr 23 01:23:35 PM PDT 24
Finished Apr 23 01:23:40 PM PDT 24
Peak memory 211960 kb
Host smart-08aaa10d-f0df-4d9f-a417-3aa07056dfc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647325957 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.2647325957
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.105220076
Short name T1113
Test name
Test status
Simulation time 10127583231 ps
CPU time 30.64 seconds
Started Apr 23 01:23:31 PM PDT 24
Finished Apr 23 01:24:02 PM PDT 24
Peak memory 349668 kb
Host smart-fb8f6f76-1d76-4d84-ab11-753e13238248
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105220076 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_acq.105220076
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.1387286886
Short name T1291
Test name
Test status
Simulation time 10159805573 ps
CPU time 30.62 seconds
Started Apr 23 01:23:32 PM PDT 24
Finished Apr 23 01:24:03 PM PDT 24
Peak memory 309508 kb
Host smart-b3771036-041f-4b88-9a09-d39ec2507a11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387286886 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.1387286886
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.906495836
Short name T1251
Test name
Test status
Simulation time 3223664050 ps
CPU time 2.8 seconds
Started Apr 23 01:23:32 PM PDT 24
Finished Apr 23 01:23:36 PM PDT 24
Peak memory 203828 kb
Host smart-d27eb336-f4b7-4a4c-ba80-abe703a58410
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906495836 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.i2c_target_hrst.906495836
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.2962781003
Short name T908
Test name
Test status
Simulation time 1934572038 ps
CPU time 4.51 seconds
Started Apr 23 01:23:29 PM PDT 24
Finished Apr 23 01:23:34 PM PDT 24
Peak memory 204264 kb
Host smart-c2e5a037-b7fe-480b-b7f7-50d465084d0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962781003 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.2962781003
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.553149466
Short name T814
Test name
Test status
Simulation time 19379086464 ps
CPU time 86.5 seconds
Started Apr 23 01:23:27 PM PDT 24
Finished Apr 23 01:24:54 PM PDT 24
Peak memory 1793344 kb
Host smart-49834086-2e2c-4b1a-87af-b09129c2be49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553149466 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.553149466
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.3551591983
Short name T926
Test name
Test status
Simulation time 745258753 ps
CPU time 27.99 seconds
Started Apr 23 01:23:28 PM PDT 24
Finished Apr 23 01:23:56 PM PDT 24
Peak memory 203704 kb
Host smart-bf37001b-2d99-4c09-b2b9-e43d953e0a54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551591983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.3551591983
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.1381525379
Short name T1070
Test name
Test status
Simulation time 5246461345 ps
CPU time 46.87 seconds
Started Apr 23 01:23:30 PM PDT 24
Finished Apr 23 01:24:17 PM PDT 24
Peak memory 205836 kb
Host smart-cfdfb784-4638-471e-b6a4-844542c01c13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381525379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.1381525379
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1616665097
Short name T583
Test name
Test status
Simulation time 14630381357 ps
CPU time 211.31 seconds
Started Apr 23 01:23:30 PM PDT 24
Finished Apr 23 01:27:02 PM PDT 24
Peak memory 1611168 kb
Host smart-27620bff-6778-49e2-9852-c6760e9612cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616665097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1616665097
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.3353042035
Short name T913
Test name
Test status
Simulation time 5764215984 ps
CPU time 7.4 seconds
Started Apr 23 01:23:29 PM PDT 24
Finished Apr 23 01:23:36 PM PDT 24
Peak memory 210432 kb
Host smart-c09a9d3c-ce42-489b-9055-eb783f80f33f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353042035 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.3353042035
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.124097550
Short name T1008
Test name
Test status
Simulation time 35582222 ps
CPU time 0.66 seconds
Started Apr 23 01:23:42 PM PDT 24
Finished Apr 23 01:23:43 PM PDT 24
Peak memory 203236 kb
Host smart-b664fe34-6b24-4587-80e6-1d8a6f3e6031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124097550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.124097550
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.198692620
Short name T1024
Test name
Test status
Simulation time 99237184 ps
CPU time 1.49 seconds
Started Apr 23 01:23:38 PM PDT 24
Finished Apr 23 01:23:40 PM PDT 24
Peak memory 212000 kb
Host smart-420c1a38-2243-42c0-a4e9-133566147c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198692620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.198692620
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.3173827278
Short name T349
Test name
Test status
Simulation time 746146040 ps
CPU time 2.58 seconds
Started Apr 23 01:23:38 PM PDT 24
Finished Apr 23 01:23:41 PM PDT 24
Peak memory 209408 kb
Host smart-cdcb6694-ddc6-4c4c-b996-f34e34164746
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173827278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.3173827278
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.614215606
Short name T883
Test name
Test status
Simulation time 3702590959 ps
CPU time 46.98 seconds
Started Apr 23 01:23:43 PM PDT 24
Finished Apr 23 01:24:30 PM PDT 24
Peak memory 520520 kb
Host smart-72be645b-7b4b-445b-9b6c-c547798acb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614215606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.614215606
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.3104503467
Short name T1138
Test name
Test status
Simulation time 6209771906 ps
CPU time 97.04 seconds
Started Apr 23 01:23:37 PM PDT 24
Finished Apr 23 01:25:14 PM PDT 24
Peak memory 517920 kb
Host smart-ad67dfed-1d4a-4bf3-b5bb-988ef3069af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104503467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.3104503467
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.2144504933
Short name T1274
Test name
Test status
Simulation time 133672649 ps
CPU time 1.16 seconds
Started Apr 23 01:23:37 PM PDT 24
Finished Apr 23 01:23:39 PM PDT 24
Peak memory 203580 kb
Host smart-8045cbcb-9bf8-44bc-b027-cbd429df1fac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144504933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.2144504933
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3015325619
Short name T1083
Test name
Test status
Simulation time 400795745 ps
CPU time 5.52 seconds
Started Apr 23 01:23:36 PM PDT 24
Finished Apr 23 01:23:42 PM PDT 24
Peak memory 216852 kb
Host smart-f06dd80e-4b71-496a-9b9b-47e511c6f35e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015325619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.3015325619
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.89077746
Short name T1331
Test name
Test status
Simulation time 37563605591 ps
CPU time 174.01 seconds
Started Apr 23 01:23:36 PM PDT 24
Finished Apr 23 01:26:31 PM PDT 24
Peak memory 827924 kb
Host smart-7250a2b4-dd7e-45f2-a9a8-9214f0e7c767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89077746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.89077746
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.1271187284
Short name T70
Test name
Test status
Simulation time 339408596 ps
CPU time 5.19 seconds
Started Apr 23 01:23:44 PM PDT 24
Finished Apr 23 01:23:50 PM PDT 24
Peak memory 203564 kb
Host smart-66c28309-13c1-4359-aab6-15eadb15c3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271187284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1271187284
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.1191008414
Short name T541
Test name
Test status
Simulation time 1676455403 ps
CPU time 41.98 seconds
Started Apr 23 01:23:43 PM PDT 24
Finished Apr 23 01:24:25 PM PDT 24
Peak memory 310816 kb
Host smart-654a11fa-86d7-43a4-b4e1-f2f1110d2cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191008414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.1191008414
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.3892867106
Short name T573
Test name
Test status
Simulation time 24961080 ps
CPU time 0.68 seconds
Started Apr 23 01:23:34 PM PDT 24
Finished Apr 23 01:23:36 PM PDT 24
Peak memory 203308 kb
Host smart-0ceab770-0235-49d5-b3c5-4426c43f9030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892867106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.3892867106
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.1445778637
Short name T1244
Test name
Test status
Simulation time 17938140051 ps
CPU time 183.36 seconds
Started Apr 23 01:23:36 PM PDT 24
Finished Apr 23 01:26:40 PM PDT 24
Peak memory 211984 kb
Host smart-2d53dc1d-4ee7-4197-ba95-366de1e91822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445778637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.1445778637
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.3934315375
Short name T264
Test name
Test status
Simulation time 18532165232 ps
CPU time 72.67 seconds
Started Apr 23 01:23:34 PM PDT 24
Finished Apr 23 01:24:48 PM PDT 24
Peak memory 315088 kb
Host smart-1627bd94-a61c-4b3b-a9a3-4eb943f27d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934315375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.3934315375
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.3990136317
Short name T1130
Test name
Test status
Simulation time 13490660593 ps
CPU time 855 seconds
Started Apr 23 01:23:38 PM PDT 24
Finished Apr 23 01:37:54 PM PDT 24
Peak memory 2757916 kb
Host smart-c4f430b6-45cd-4faa-b19b-49d4dfcdd9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990136317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.3990136317
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.4029301898
Short name T296
Test name
Test status
Simulation time 827144649 ps
CPU time 16.11 seconds
Started Apr 23 01:23:37 PM PDT 24
Finished Apr 23 01:23:54 PM PDT 24
Peak memory 217572 kb
Host smart-980b72f7-9aaf-488c-9bb4-4354a6c55abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029301898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.4029301898
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.4172646179
Short name T695
Test name
Test status
Simulation time 1438445619 ps
CPU time 3.45 seconds
Started Apr 23 01:23:45 PM PDT 24
Finished Apr 23 01:23:49 PM PDT 24
Peak memory 211988 kb
Host smart-22b4b540-74d1-4b06-b9d7-b4bb79613f89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172646179 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.4172646179
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.675946212
Short name T1088
Test name
Test status
Simulation time 10248866431 ps
CPU time 10.78 seconds
Started Apr 23 01:23:38 PM PDT 24
Finished Apr 23 01:23:49 PM PDT 24
Peak memory 258556 kb
Host smart-0e337253-4b0d-4969-980e-44fee10b1e35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675946212 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_acq.675946212
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.2075570738
Short name T576
Test name
Test status
Simulation time 10540769319 ps
CPU time 9.94 seconds
Started Apr 23 01:23:41 PM PDT 24
Finished Apr 23 01:23:52 PM PDT 24
Peak memory 252748 kb
Host smart-b57de39a-0503-49de-bed6-4a5c805403b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075570738 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.2075570738
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.2194345002
Short name T666
Test name
Test status
Simulation time 607915209 ps
CPU time 2.96 seconds
Started Apr 23 01:23:45 PM PDT 24
Finished Apr 23 01:23:48 PM PDT 24
Peak memory 203768 kb
Host smart-e3185952-0af2-457b-bdb6-35ea0f16a28f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194345002 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.2194345002
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.3060574046
Short name T1037
Test name
Test status
Simulation time 2698497031 ps
CPU time 3.94 seconds
Started Apr 23 01:23:38 PM PDT 24
Finished Apr 23 01:23:43 PM PDT 24
Peak memory 203760 kb
Host smart-8b62b665-0328-4ec0-88f9-24d23f7f1f99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060574046 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.3060574046
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.53903142
Short name T804
Test name
Test status
Simulation time 16337523993 ps
CPU time 315.82 seconds
Started Apr 23 01:23:37 PM PDT 24
Finished Apr 23 01:28:53 PM PDT 24
Peak memory 3840420 kb
Host smart-537abe1b-b0e2-4e59-ae5e-292d806440b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53903142 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.53903142
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.3771382264
Short name T1126
Test name
Test status
Simulation time 1525573491 ps
CPU time 29.7 seconds
Started Apr 23 01:23:39 PM PDT 24
Finished Apr 23 01:24:09 PM PDT 24
Peak memory 203688 kb
Host smart-060acd0f-a542-4062-8d0e-fd78b1553029
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771382264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.3771382264
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.1166251782
Short name T958
Test name
Test status
Simulation time 729070342 ps
CPU time 12.1 seconds
Started Apr 23 01:23:35 PM PDT 24
Finished Apr 23 01:23:48 PM PDT 24
Peak memory 207620 kb
Host smart-5d728420-726d-4857-8efb-95a100b98b3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166251782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.1166251782
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.1267004484
Short name T768
Test name
Test status
Simulation time 55954353914 ps
CPU time 191.53 seconds
Started Apr 23 01:23:38 PM PDT 24
Finished Apr 23 01:26:50 PM PDT 24
Peak memory 2326772 kb
Host smart-a956633c-32c5-4990-b872-c550c36c7a66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267004484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.1267004484
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.242252900
Short name T1060
Test name
Test status
Simulation time 16028584886 ps
CPU time 299.12 seconds
Started Apr 23 01:23:37 PM PDT 24
Finished Apr 23 01:28:37 PM PDT 24
Peak memory 1054356 kb
Host smart-9c92c794-1493-4504-bdaf-d3c991d885e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242252900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_t
arget_stretch.242252900
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.3605969078
Short name T964
Test name
Test status
Simulation time 2338357723 ps
CPU time 6.49 seconds
Started Apr 23 01:23:35 PM PDT 24
Finished Apr 23 01:23:42 PM PDT 24
Peak memory 219916 kb
Host smart-b2950451-0f19-4e1b-9b68-b76ade20eb07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605969078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.3605969078
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.1113020433
Short name T937
Test name
Test status
Simulation time 38557198 ps
CPU time 0.6 seconds
Started Apr 23 01:23:54 PM PDT 24
Finished Apr 23 01:23:55 PM PDT 24
Peak memory 203376 kb
Host smart-14452287-de3a-4333-8447-687346d6d9ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113020433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.1113020433
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.2452009919
Short name T1084
Test name
Test status
Simulation time 265590525 ps
CPU time 1.36 seconds
Started Apr 23 01:23:52 PM PDT 24
Finished Apr 23 01:23:54 PM PDT 24
Peak memory 212000 kb
Host smart-3b9de8b3-bb64-42fb-b456-0810a820b476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452009919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.2452009919
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.4240310663
Short name T435
Test name
Test status
Simulation time 225424895 ps
CPU time 11.05 seconds
Started Apr 23 01:23:51 PM PDT 24
Finished Apr 23 01:24:02 PM PDT 24
Peak memory 228960 kb
Host smart-2bce925c-e3d3-4d2e-8cb0-755501692ff6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240310663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.4240310663
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2605834082
Short name T595
Test name
Test status
Simulation time 8169679448 ps
CPU time 52.66 seconds
Started Apr 23 01:23:50 PM PDT 24
Finished Apr 23 01:24:43 PM PDT 24
Peak memory 493112 kb
Host smart-12d6ea6d-de07-4408-b93d-3c64813c6c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605834082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2605834082
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.201198625
Short name T353
Test name
Test status
Simulation time 4723987226 ps
CPU time 64.33 seconds
Started Apr 23 01:23:45 PM PDT 24
Finished Apr 23 01:24:50 PM PDT 24
Peak memory 742272 kb
Host smart-7029cc59-fd7a-48cc-a77d-ab134748a828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201198625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.201198625
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.1403310924
Short name T852
Test name
Test status
Simulation time 320596819 ps
CPU time 1.12 seconds
Started Apr 23 01:23:51 PM PDT 24
Finished Apr 23 01:23:53 PM PDT 24
Peak memory 203368 kb
Host smart-02c127a5-468e-482b-81e0-ad5c940e03a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403310924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.1403310924
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.2961686842
Short name T1234
Test name
Test status
Simulation time 163263331 ps
CPU time 3.52 seconds
Started Apr 23 01:23:47 PM PDT 24
Finished Apr 23 01:23:51 PM PDT 24
Peak memory 203660 kb
Host smart-2ff0728b-4b23-4202-a99c-e7168d404724
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961686842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.2961686842
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.372919247
Short name T800
Test name
Test status
Simulation time 10974996293 ps
CPU time 66.4 seconds
Started Apr 23 01:23:46 PM PDT 24
Finished Apr 23 01:24:53 PM PDT 24
Peak memory 885432 kb
Host smart-bace3d49-c552-4cfa-bc0f-35315c5a7e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372919247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.372919247
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.2137246269
Short name T610
Test name
Test status
Simulation time 794159665 ps
CPU time 7.05 seconds
Started Apr 23 01:23:55 PM PDT 24
Finished Apr 23 01:24:02 PM PDT 24
Peak memory 203640 kb
Host smart-bdb1cfaf-f155-47d3-812d-d72ce364d0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137246269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.2137246269
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.1594080642
Short name T1017
Test name
Test status
Simulation time 1725578152 ps
CPU time 34.49 seconds
Started Apr 23 01:23:53 PM PDT 24
Finished Apr 23 01:24:28 PM PDT 24
Peak memory 347836 kb
Host smart-adf9d275-befa-4ed8-bf6b-bce8371bb4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594080642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.1594080642
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.81396685
Short name T190
Test name
Test status
Simulation time 136170821 ps
CPU time 0.68 seconds
Started Apr 23 01:23:44 PM PDT 24
Finished Apr 23 01:23:45 PM PDT 24
Peak memory 203420 kb
Host smart-28b893b2-41e8-4249-8651-899eda1fa8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81396685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.81396685
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.411260939
Short name T197
Test name
Test status
Simulation time 1501134383 ps
CPU time 1.52 seconds
Started Apr 23 01:23:46 PM PDT 24
Finished Apr 23 01:23:48 PM PDT 24
Peak memory 211864 kb
Host smart-cb2b41c1-96a3-4cf0-aabf-e6a2715e271d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411260939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.411260939
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.722058485
Short name T1339
Test name
Test status
Simulation time 4407421002 ps
CPU time 19.71 seconds
Started Apr 23 01:23:44 PM PDT 24
Finished Apr 23 01:24:04 PM PDT 24
Peak memory 315128 kb
Host smart-d23c81bc-456c-473e-9391-5a367e267398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722058485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.722058485
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.2816288249
Short name T1258
Test name
Test status
Simulation time 49755255240 ps
CPU time 936.48 seconds
Started Apr 23 01:23:49 PM PDT 24
Finished Apr 23 01:39:26 PM PDT 24
Peak memory 1004736 kb
Host smart-f1964177-6bda-4cdf-9089-d908325a9938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816288249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2816288249
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.1013087435
Short name T300
Test name
Test status
Simulation time 655917122 ps
CPU time 11.34 seconds
Started Apr 23 01:23:45 PM PDT 24
Finished Apr 23 01:23:57 PM PDT 24
Peak memory 220020 kb
Host smart-f5277c4c-7906-44cb-8d9f-835b67525b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013087435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.1013087435
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.2331365410
Short name T1173
Test name
Test status
Simulation time 1235760760 ps
CPU time 3.69 seconds
Started Apr 23 01:23:49 PM PDT 24
Finished Apr 23 01:23:54 PM PDT 24
Peak memory 211888 kb
Host smart-448204ab-b4cf-4fd6-ad9a-5f4f988e268e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331365410 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.2331365410
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.1178608036
Short name T1019
Test name
Test status
Simulation time 10127913009 ps
CPU time 67.87 seconds
Started Apr 23 01:23:52 PM PDT 24
Finished Apr 23 01:25:00 PM PDT 24
Peak memory 410024 kb
Host smart-25aced76-3e70-47f6-978b-d54355c037d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178608036 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.1178608036
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.1048770222
Short name T108
Test name
Test status
Simulation time 10166771173 ps
CPU time 12.6 seconds
Started Apr 23 01:23:51 PM PDT 24
Finished Apr 23 01:24:04 PM PDT 24
Peak memory 250680 kb
Host smart-f0290b6f-77dd-4379-a86b-17f7fa92b1ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048770222 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.1048770222
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.4116397872
Short name T954
Test name
Test status
Simulation time 816694651 ps
CPU time 2.44 seconds
Started Apr 23 01:23:54 PM PDT 24
Finished Apr 23 01:23:57 PM PDT 24
Peak memory 203684 kb
Host smart-a8ce3413-1a7c-4b5e-a43a-262efced0455
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116397872 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.4116397872
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.2348537233
Short name T876
Test name
Test status
Simulation time 4506081927 ps
CPU time 4.82 seconds
Started Apr 23 01:23:52 PM PDT 24
Finished Apr 23 01:23:57 PM PDT 24
Peak memory 203804 kb
Host smart-e81a751c-101f-4c88-a0ea-acce4f45011d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348537233 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.2348537233
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.1686968855
Short name T899
Test name
Test status
Simulation time 17668499053 ps
CPU time 29.46 seconds
Started Apr 23 01:23:56 PM PDT 24
Finished Apr 23 01:24:26 PM PDT 24
Peak memory 604856 kb
Host smart-6a5764a3-476a-466c-9333-a8e008eed6db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686968855 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.1686968855
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.666880935
Short name T1116
Test name
Test status
Simulation time 5994169332 ps
CPU time 63.44 seconds
Started Apr 23 01:23:51 PM PDT 24
Finished Apr 23 01:24:55 PM PDT 24
Peak memory 203760 kb
Host smart-ba289663-ef95-43d4-b54a-fafeab0f8bff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666880935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_tar
get_smoke.666880935
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.1522838801
Short name T223
Test name
Test status
Simulation time 752272190 ps
CPU time 14.69 seconds
Started Apr 23 01:23:50 PM PDT 24
Finished Apr 23 01:24:05 PM PDT 24
Peak memory 211964 kb
Host smart-197e7354-c724-47de-b089-6310405838e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522838801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.1522838801
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.1468712920
Short name T1131
Test name
Test status
Simulation time 16733332604 ps
CPU time 8.18 seconds
Started Apr 23 01:23:52 PM PDT 24
Finished Apr 23 01:24:00 PM PDT 24
Peak memory 203752 kb
Host smart-b8eba72c-12a1-43c9-96c0-bf11dc5746e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468712920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.1468712920
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.451890308
Short name T221
Test name
Test status
Simulation time 28381356647 ps
CPU time 48.67 seconds
Started Apr 23 01:23:49 PM PDT 24
Finished Apr 23 01:24:39 PM PDT 24
Peak memory 614772 kb
Host smart-7520b7f6-5d52-4b0f-a6be-053241c7bf5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451890308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_t
arget_stretch.451890308
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.3852642399
Short name T839
Test name
Test status
Simulation time 1615441650 ps
CPU time 7.27 seconds
Started Apr 23 01:23:51 PM PDT 24
Finished Apr 23 01:23:59 PM PDT 24
Peak memory 211892 kb
Host smart-37cfbeeb-edec-4d3c-a229-b18ac5d47557
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852642399 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.3852642399
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.2769560727
Short name T559
Test name
Test status
Simulation time 16616509 ps
CPU time 0.63 seconds
Started Apr 23 01:24:02 PM PDT 24
Finished Apr 23 01:24:03 PM PDT 24
Peak memory 203328 kb
Host smart-06d15c77-9a6a-4ac4-b552-8d080ae1d314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769560727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2769560727
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.2233507875
Short name T786
Test name
Test status
Simulation time 187977277 ps
CPU time 1.69 seconds
Started Apr 23 01:23:55 PM PDT 24
Finished Apr 23 01:23:58 PM PDT 24
Peak memory 212072 kb
Host smart-f78ec90e-3d66-4e52-8111-3dbff605fb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233507875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.2233507875
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.2939029300
Short name T509
Test name
Test status
Simulation time 414388194 ps
CPU time 11.02 seconds
Started Apr 23 01:23:55 PM PDT 24
Finished Apr 23 01:24:06 PM PDT 24
Peak memory 244084 kb
Host smart-fc2a3e36-2ba5-4d58-991a-e03a39edbe2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939029300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.2939029300
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.987548064
Short name T390
Test name
Test status
Simulation time 10883766248 ps
CPU time 83.07 seconds
Started Apr 23 01:23:55 PM PDT 24
Finished Apr 23 01:25:19 PM PDT 24
Peak memory 695916 kb
Host smart-331cfda1-89f7-4b8f-bb2c-17bcec17d399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987548064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.987548064
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.4185741776
Short name T621
Test name
Test status
Simulation time 5853046490 ps
CPU time 36.11 seconds
Started Apr 23 01:23:56 PM PDT 24
Finished Apr 23 01:24:33 PM PDT 24
Peak memory 459904 kb
Host smart-b65d68b7-2fc7-4f83-a3fb-489c3378695d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185741776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.4185741776
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.1599915753
Short name T346
Test name
Test status
Simulation time 158689288 ps
CPU time 1.29 seconds
Started Apr 23 01:23:54 PM PDT 24
Finished Apr 23 01:23:56 PM PDT 24
Peak memory 203632 kb
Host smart-38f061d9-a88f-4c56-88b3-41c2170b71e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599915753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.1599915753
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.3719151724
Short name T673
Test name
Test status
Simulation time 746816170 ps
CPU time 7.43 seconds
Started Apr 23 01:23:57 PM PDT 24
Finished Apr 23 01:24:05 PM PDT 24
Peak memory 203604 kb
Host smart-215991dc-6cf6-40ef-9497-431fe1a423bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719151724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.3719151724
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.2918572511
Short name T807
Test name
Test status
Simulation time 5034721087 ps
CPU time 160.69 seconds
Started Apr 23 01:23:54 PM PDT 24
Finished Apr 23 01:26:35 PM PDT 24
Peak memory 802636 kb
Host smart-e2141e24-f0b3-42a1-be17-518b16ae4f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918572511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2918572511
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.4202920496
Short name T1142
Test name
Test status
Simulation time 1780006535 ps
CPU time 5.65 seconds
Started Apr 23 01:24:03 PM PDT 24
Finished Apr 23 01:24:09 PM PDT 24
Peak memory 203572 kb
Host smart-44a6a1c8-c732-4d89-ab6c-4fe7a039e35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202920496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.4202920496
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.2000614080
Short name T461
Test name
Test status
Simulation time 1284556053 ps
CPU time 18.42 seconds
Started Apr 23 01:24:01 PM PDT 24
Finished Apr 23 01:24:19 PM PDT 24
Peak memory 298200 kb
Host smart-4c1c2e46-cde1-4f84-a491-0e20091561c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000614080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.2000614080
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.324072512
Short name T1206
Test name
Test status
Simulation time 58999829 ps
CPU time 0.67 seconds
Started Apr 23 01:23:53 PM PDT 24
Finished Apr 23 01:23:54 PM PDT 24
Peak memory 203340 kb
Host smart-c867ea1d-881a-453f-a06c-a7325d85b972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324072512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.324072512
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.2978480600
Short name T762
Test name
Test status
Simulation time 479640696 ps
CPU time 8.04 seconds
Started Apr 23 01:23:57 PM PDT 24
Finished Apr 23 01:24:06 PM PDT 24
Peak memory 298944 kb
Host smart-9d858c7a-8f1c-495d-a92f-7a07793b3333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978480600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.2978480600
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.4102497426
Short name T362
Test name
Test status
Simulation time 8805509843 ps
CPU time 70.24 seconds
Started Apr 23 01:23:55 PM PDT 24
Finished Apr 23 01:25:06 PM PDT 24
Peak memory 310136 kb
Host smart-c4f6b7f4-efce-41df-a5ff-15e1d96d797e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102497426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.4102497426
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.1786761337
Short name T83
Test name
Test status
Simulation time 68315496202 ps
CPU time 257.69 seconds
Started Apr 23 01:23:58 PM PDT 24
Finished Apr 23 01:28:16 PM PDT 24
Peak memory 1339484 kb
Host smart-35713933-458c-4e1a-8c00-0e55ce07421a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786761337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.1786761337
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.3459720356
Short name T645
Test name
Test status
Simulation time 3030501979 ps
CPU time 11.43 seconds
Started Apr 23 01:23:58 PM PDT 24
Finished Apr 23 01:24:10 PM PDT 24
Peak memory 228400 kb
Host smart-65ac3384-9ef9-480a-944e-ed4b422a78a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459720356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.3459720356
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.802526448
Short name T32
Test name
Test status
Simulation time 2544918969 ps
CPU time 3.16 seconds
Started Apr 23 01:24:04 PM PDT 24
Finished Apr 23 01:24:07 PM PDT 24
Peak memory 203716 kb
Host smart-5a9925b3-ede2-4137-ac26-adac00a3fc88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802526448 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.802526448
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.3282352292
Short name T912
Test name
Test status
Simulation time 10141052530 ps
CPU time 78.48 seconds
Started Apr 23 01:23:57 PM PDT 24
Finished Apr 23 01:25:16 PM PDT 24
Peak memory 490720 kb
Host smart-070f544c-ca11-4cb2-af5b-4fdd199767c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282352292 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.3282352292
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.2361134913
Short name T950
Test name
Test status
Simulation time 355293416 ps
CPU time 2.19 seconds
Started Apr 23 01:24:01 PM PDT 24
Finished Apr 23 01:24:04 PM PDT 24
Peak memory 203676 kb
Host smart-931c4f60-aad6-4ede-90d3-60f05942dfb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361134913 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.2361134913
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.1145725597
Short name T528
Test name
Test status
Simulation time 2523255663 ps
CPU time 5.96 seconds
Started Apr 23 01:23:57 PM PDT 24
Finished Apr 23 01:24:03 PM PDT 24
Peak memory 219320 kb
Host smart-814cc8f2-cc91-4d45-b422-18b390a3a56c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145725597 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.1145725597
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.2887719660
Short name T986
Test name
Test status
Simulation time 4095384982 ps
CPU time 12.75 seconds
Started Apr 23 01:23:58 PM PDT 24
Finished Apr 23 01:24:12 PM PDT 24
Peak memory 203756 kb
Host smart-63042880-c2bf-41ce-a688-2cfbf7080fba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887719660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.2887719660
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.1539673524
Short name T527
Test name
Test status
Simulation time 4097923924 ps
CPU time 49.07 seconds
Started Apr 23 01:24:00 PM PDT 24
Finished Apr 23 01:24:49 PM PDT 24
Peak memory 203844 kb
Host smart-994b2ef5-31bf-4380-97d2-e4b1e6c45fbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539673524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.1539673524
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.2590650942
Short name T1266
Test name
Test status
Simulation time 56578740386 ps
CPU time 1500.68 seconds
Started Apr 23 01:23:58 PM PDT 24
Finished Apr 23 01:48:59 PM PDT 24
Peak memory 8852364 kb
Host smart-385c7ccd-e37d-4e93-8a01-3ca89a77fadb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590650942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.2590650942
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.3036264111
Short name T402
Test name
Test status
Simulation time 29583126421 ps
CPU time 544.69 seconds
Started Apr 23 01:23:57 PM PDT 24
Finished Apr 23 01:33:02 PM PDT 24
Peak memory 1648140 kb
Host smart-7d64ba48-cd02-4913-a4cd-fb877af0fe75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036264111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.3036264111
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.3311344051
Short name T911
Test name
Test status
Simulation time 18012261136 ps
CPU time 7.07 seconds
Started Apr 23 01:23:57 PM PDT 24
Finished Apr 23 01:24:05 PM PDT 24
Peak memory 216524 kb
Host smart-b35a5ed3-0a72-4811-a2ce-b8adb44931e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311344051 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.3311344051
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.3601698004
Short name T623
Test name
Test status
Simulation time 15638716 ps
CPU time 0.61 seconds
Started Apr 23 01:24:12 PM PDT 24
Finished Apr 23 01:24:13 PM PDT 24
Peak memory 203376 kb
Host smart-cd647b60-386e-4d34-9db8-3ac9f8eb61a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601698004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3601698004
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.2838265147
Short name T429
Test name
Test status
Simulation time 448779134 ps
CPU time 1.24 seconds
Started Apr 23 01:24:10 PM PDT 24
Finished Apr 23 01:24:11 PM PDT 24
Peak memory 212000 kb
Host smart-872884f8-c0d6-4b76-9403-386332741717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838265147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.2838265147
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.1241328123
Short name T779
Test name
Test status
Simulation time 816525936 ps
CPU time 15.67 seconds
Started Apr 23 01:24:05 PM PDT 24
Finished Apr 23 01:24:21 PM PDT 24
Peak memory 267488 kb
Host smart-e759a52d-b5c5-482a-a0ac-b0d046407af0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241328123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.1241328123
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.3183716937
Short name T584
Test name
Test status
Simulation time 9058415264 ps
CPU time 84.86 seconds
Started Apr 23 01:24:05 PM PDT 24
Finished Apr 23 01:25:30 PM PDT 24
Peak memory 750264 kb
Host smart-6d36c80d-68f1-484b-8b1b-640c071fe3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183716937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.3183716937
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.3608411257
Short name T331
Test name
Test status
Simulation time 8760192569 ps
CPU time 82.47 seconds
Started Apr 23 01:24:05 PM PDT 24
Finished Apr 23 01:25:28 PM PDT 24
Peak memory 729328 kb
Host smart-4339eaa8-3465-4db8-bc09-83b8b1d92363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608411257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.3608411257
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.202904793
Short name T855
Test name
Test status
Simulation time 178680584 ps
CPU time 0.87 seconds
Started Apr 23 01:24:04 PM PDT 24
Finished Apr 23 01:24:06 PM PDT 24
Peak memory 203404 kb
Host smart-c6954742-1e72-44b2-8df7-791fedfc433c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202904793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fm
t.202904793
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.3466516627
Short name T453
Test name
Test status
Simulation time 326538376 ps
CPU time 4.66 seconds
Started Apr 23 01:24:04 PM PDT 24
Finished Apr 23 01:24:09 PM PDT 24
Peak memory 231200 kb
Host smart-dd0e7568-a225-48e7-a2ac-2ffeb9653046
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466516627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.3466516627
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.3535908447
Short name T714
Test name
Test status
Simulation time 4495533651 ps
CPU time 312.52 seconds
Started Apr 23 01:24:05 PM PDT 24
Finished Apr 23 01:29:18 PM PDT 24
Peak memory 1137716 kb
Host smart-5c82b132-0bb5-4517-ac07-7546bf495a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535908447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3535908447
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.4217777351
Short name T214
Test name
Test status
Simulation time 723053475 ps
CPU time 14.32 seconds
Started Apr 23 01:24:11 PM PDT 24
Finished Apr 23 01:24:26 PM PDT 24
Peak memory 203584 kb
Host smart-aa10a329-5177-4857-bbd9-0c7d9bec7c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217777351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.4217777351
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.1991300364
Short name T656
Test name
Test status
Simulation time 6515190602 ps
CPU time 16.6 seconds
Started Apr 23 01:24:13 PM PDT 24
Finished Apr 23 01:24:30 PM PDT 24
Peak memory 267420 kb
Host smart-40c7f2bc-3a1a-42b6-8b58-3fa5bca011d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991300364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.1991300364
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.970372535
Short name T393
Test name
Test status
Simulation time 17716922 ps
CPU time 0.67 seconds
Started Apr 23 01:24:03 PM PDT 24
Finished Apr 23 01:24:04 PM PDT 24
Peak memory 203320 kb
Host smart-7594ca1c-3fab-446c-a77d-f4adda87fa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970372535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.970372535
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.879315102
Short name T347
Test name
Test status
Simulation time 566674554 ps
CPU time 4 seconds
Started Apr 23 01:24:10 PM PDT 24
Finished Apr 23 01:24:14 PM PDT 24
Peak memory 203652 kb
Host smart-75bf657a-32e3-4e72-ad17-891de483f71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879315102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.879315102
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.2327087535
Short name T915
Test name
Test status
Simulation time 1021167509 ps
CPU time 20.37 seconds
Started Apr 23 01:24:02 PM PDT 24
Finished Apr 23 01:24:23 PM PDT 24
Peak memory 292644 kb
Host smart-7e84e135-e0e2-4f79-aabe-9ed3aef82fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327087535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2327087535
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.536417097
Short name T178
Test name
Test status
Simulation time 47069726162 ps
CPU time 675.04 seconds
Started Apr 23 01:24:09 PM PDT 24
Finished Apr 23 01:35:25 PM PDT 24
Peak memory 2094224 kb
Host smart-7169a4cd-6e76-42f6-aa56-2524a4a6c9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536417097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.536417097
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.3246184175
Short name T1133
Test name
Test status
Simulation time 834074478 ps
CPU time 33.65 seconds
Started Apr 23 01:24:09 PM PDT 24
Finished Apr 23 01:24:43 PM PDT 24
Peak memory 212964 kb
Host smart-8d669910-2f03-4d1f-920c-be46f0decc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246184175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.3246184175
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.3435722913
Short name T733
Test name
Test status
Simulation time 1514009748 ps
CPU time 4.24 seconds
Started Apr 23 01:24:12 PM PDT 24
Finished Apr 23 01:24:17 PM PDT 24
Peak memory 211852 kb
Host smart-1390354f-2a36-43b2-bd46-2a937c75e930
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435722913 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.3435722913
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.1285282189
Short name T749
Test name
Test status
Simulation time 10376350805 ps
CPU time 14.78 seconds
Started Apr 23 01:24:08 PM PDT 24
Finished Apr 23 01:24:24 PM PDT 24
Peak memory 269264 kb
Host smart-672ecb2c-b565-4f44-a676-5ebcc514751e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285282189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.1285282189
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.32743102
Short name T1351
Test name
Test status
Simulation time 10342267996 ps
CPU time 12.53 seconds
Started Apr 23 01:24:12 PM PDT 24
Finished Apr 23 01:24:25 PM PDT 24
Peak memory 299220 kb
Host smart-5cbd0434-2f59-4535-a139-8502ff0ed222
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32743102 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.i2c_target_fifo_reset_tx.32743102
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.3459003711
Short name T901
Test name
Test status
Simulation time 1752057674 ps
CPU time 2.33 seconds
Started Apr 23 01:24:13 PM PDT 24
Finished Apr 23 01:24:16 PM PDT 24
Peak memory 203736 kb
Host smart-8bfd857a-c6a0-4151-9b2f-253603cee969
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459003711 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.3459003711
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.1489199493
Short name T1322
Test name
Test status
Simulation time 15277077561 ps
CPU time 5.06 seconds
Started Apr 23 01:24:09 PM PDT 24
Finished Apr 23 01:24:14 PM PDT 24
Peak memory 207560 kb
Host smart-f1e12624-f44e-446a-983c-de3549650b6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489199493 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.1489199493
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.3178830703
Short name T633
Test name
Test status
Simulation time 11256108318 ps
CPU time 65.16 seconds
Started Apr 23 01:24:08 PM PDT 24
Finished Apr 23 01:25:13 PM PDT 24
Peak memory 1132596 kb
Host smart-8e8dee15-66ad-4754-9140-23cbbdd98611
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178830703 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.3178830703
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.2806129781
Short name T276
Test name
Test status
Simulation time 4910108040 ps
CPU time 19.69 seconds
Started Apr 23 01:24:12 PM PDT 24
Finished Apr 23 01:24:33 PM PDT 24
Peak memory 203792 kb
Host smart-9d7da675-078c-48d0-bc5e-450b33a0296d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806129781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.2806129781
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.161215703
Short name T551
Test name
Test status
Simulation time 1882016310 ps
CPU time 8.71 seconds
Started Apr 23 01:24:12 PM PDT 24
Finished Apr 23 01:24:22 PM PDT 24
Peak memory 203804 kb
Host smart-44543be6-ad1c-42bc-a1ae-6bc6f60426ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161215703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_rd.161215703
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.2815168642
Short name T1345
Test name
Test status
Simulation time 41237038799 ps
CPU time 87.33 seconds
Started Apr 23 01:24:10 PM PDT 24
Finished Apr 23 01:25:38 PM PDT 24
Peak memory 1344232 kb
Host smart-93c19fdc-3ea9-441e-bc27-5babc5011df8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815168642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.2815168642
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.3037625431
Short name T334
Test name
Test status
Simulation time 18068838206 ps
CPU time 94.34 seconds
Started Apr 23 01:24:09 PM PDT 24
Finished Apr 23 01:25:44 PM PDT 24
Peak memory 933056 kb
Host smart-dbf3d2b4-93eb-431c-a876-00aedc38ea3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037625431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.3037625431
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.1660170509
Short name T753
Test name
Test status
Simulation time 14742636625 ps
CPU time 6.9 seconds
Started Apr 23 01:24:09 PM PDT 24
Finished Apr 23 01:24:17 PM PDT 24
Peak memory 218936 kb
Host smart-a6388a36-730e-4e20-a531-959ccbf3696e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660170509 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.1660170509
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.748761068
Short name T1265
Test name
Test status
Simulation time 51686255 ps
CPU time 0.63 seconds
Started Apr 23 01:24:21 PM PDT 24
Finished Apr 23 01:24:22 PM PDT 24
Peak memory 203324 kb
Host smart-92ff62ef-bdca-4321-8924-5c4a930418ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748761068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.748761068
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.1501092653
Short name T497
Test name
Test status
Simulation time 296383897 ps
CPU time 1.38 seconds
Started Apr 23 01:24:18 PM PDT 24
Finished Apr 23 01:24:19 PM PDT 24
Peak memory 211964 kb
Host smart-2256b1f1-10a7-48c7-9a65-811508fc77e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501092653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.1501092653
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3816164613
Short name T281
Test name
Test status
Simulation time 2769005398 ps
CPU time 5.27 seconds
Started Apr 23 01:24:15 PM PDT 24
Finished Apr 23 01:24:21 PM PDT 24
Peak memory 250560 kb
Host smart-5cf2dec3-4d10-4809-a949-f20ef9ed4f2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816164613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.3816164613
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.1752035900
Short name T754
Test name
Test status
Simulation time 2525712612 ps
CPU time 48.41 seconds
Started Apr 23 01:24:16 PM PDT 24
Finished Apr 23 01:25:04 PM PDT 24
Peak memory 568712 kb
Host smart-815a6577-bb7f-4bc1-ad78-f75c281dab73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752035900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.1752035900
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.1013961491
Short name T470
Test name
Test status
Simulation time 4073773878 ps
CPU time 70.98 seconds
Started Apr 23 01:24:15 PM PDT 24
Finished Apr 23 01:25:26 PM PDT 24
Peak memory 656592 kb
Host smart-32afa3a3-4c56-4bdb-a066-15e5a5f202cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013961491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.1013961491
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.2466837471
Short name T533
Test name
Test status
Simulation time 515928001 ps
CPU time 1.2 seconds
Started Apr 23 01:24:17 PM PDT 24
Finished Apr 23 01:24:18 PM PDT 24
Peak memory 203604 kb
Host smart-34e4b8a8-6a6a-4c3a-b873-4d6aeada030e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466837471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.2466837471
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.1898365335
Short name T485
Test name
Test status
Simulation time 114581464 ps
CPU time 2.77 seconds
Started Apr 23 01:24:17 PM PDT 24
Finished Apr 23 01:24:20 PM PDT 24
Peak memory 217728 kb
Host smart-c2e53a36-4114-4a6b-b086-f2b2561db9d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898365335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.1898365335
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.3225687009
Short name T305
Test name
Test status
Simulation time 3630151918 ps
CPU time 113.32 seconds
Started Apr 23 01:24:13 PM PDT 24
Finished Apr 23 01:26:07 PM PDT 24
Peak memory 1088844 kb
Host smart-b0514d05-3871-41a9-b226-a89be34661d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225687009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3225687009
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.350850041
Short name T545
Test name
Test status
Simulation time 190744321 ps
CPU time 7.14 seconds
Started Apr 23 01:24:30 PM PDT 24
Finished Apr 23 01:24:37 PM PDT 24
Peak memory 203620 kb
Host smart-67a49b8e-8376-43cb-979b-de9ffecd330a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350850041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.350850041
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.216170247
Short name T529
Test name
Test status
Simulation time 1207877412 ps
CPU time 20.71 seconds
Started Apr 23 01:24:23 PM PDT 24
Finished Apr 23 01:24:44 PM PDT 24
Peak memory 348868 kb
Host smart-c91bbbbf-0309-47a2-b07d-f7b1c3b90b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216170247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.216170247
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.3007639029
Short name T189
Test name
Test status
Simulation time 28971705 ps
CPU time 0.69 seconds
Started Apr 23 01:24:11 PM PDT 24
Finished Apr 23 01:24:12 PM PDT 24
Peak memory 203368 kb
Host smart-416eef58-3e9b-4d5d-be11-3ed99b5ff2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007639029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.3007639029
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.2603407539
Short name T1347
Test name
Test status
Simulation time 97504445673 ps
CPU time 1685.13 seconds
Started Apr 23 01:24:15 PM PDT 24
Finished Apr 23 01:52:20 PM PDT 24
Peak memory 1612576 kb
Host smart-6376e100-4979-4a7e-9596-07322e591a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603407539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.2603407539
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2295897478
Short name T310
Test name
Test status
Simulation time 1692767853 ps
CPU time 90.8 seconds
Started Apr 23 01:24:11 PM PDT 24
Finished Apr 23 01:25:42 PM PDT 24
Peak memory 378588 kb
Host smart-99c7df4d-dc5c-41b3-b465-f72a45904f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295897478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2295897478
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.2010565337
Short name T953
Test name
Test status
Simulation time 18026601184 ps
CPU time 572.89 seconds
Started Apr 23 01:24:18 PM PDT 24
Finished Apr 23 01:33:52 PM PDT 24
Peak memory 2553416 kb
Host smart-02c82598-aaae-4f1a-94c5-0ecfe628b3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010565337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.2010565337
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.1076185018
Short name T1180
Test name
Test status
Simulation time 5153260723 ps
CPU time 4.06 seconds
Started Apr 23 01:24:22 PM PDT 24
Finished Apr 23 01:24:26 PM PDT 24
Peak memory 211912 kb
Host smart-aa74e856-dbc5-4323-ad3f-3d96c5dade00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076185018 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.1076185018
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.532252242
Short name T412
Test name
Test status
Simulation time 10042617988 ps
CPU time 77.3 seconds
Started Apr 23 01:24:19 PM PDT 24
Finished Apr 23 01:25:37 PM PDT 24
Peak memory 536748 kb
Host smart-10cc0064-b0b2-4658-bdc5-c56f7d673fde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532252242 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_acq.532252242
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.2808623859
Short name T553
Test name
Test status
Simulation time 10191991042 ps
CPU time 13.42 seconds
Started Apr 23 01:24:22 PM PDT 24
Finished Apr 23 01:24:36 PM PDT 24
Peak memory 263428 kb
Host smart-c01e1b2e-ef97-40ff-be50-453214c7e963
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808623859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.2808623859
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.2560787110
Short name T1209
Test name
Test status
Simulation time 1872981308 ps
CPU time 4.35 seconds
Started Apr 23 01:24:17 PM PDT 24
Finished Apr 23 01:24:22 PM PDT 24
Peak memory 206624 kb
Host smart-5073cdfc-a8c0-4860-a35e-a6ba4e94663e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560787110 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.2560787110
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.2238066342
Short name T318
Test name
Test status
Simulation time 8685983566 ps
CPU time 114.42 seconds
Started Apr 23 01:24:20 PM PDT 24
Finished Apr 23 01:26:15 PM PDT 24
Peak memory 2237932 kb
Host smart-265adfde-a3d5-4690-8034-0449ce469bf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238066342 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.2238066342
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.3045789562
Short name T372
Test name
Test status
Simulation time 548267084 ps
CPU time 7.17 seconds
Started Apr 23 01:24:17 PM PDT 24
Finished Apr 23 01:24:24 PM PDT 24
Peak memory 203668 kb
Host smart-65793968-0f08-4b5c-8f4e-4ce40ce8c41e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045789562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.3045789562
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.4092516980
Short name T985
Test name
Test status
Simulation time 2413637996 ps
CPU time 20.23 seconds
Started Apr 23 01:24:18 PM PDT 24
Finished Apr 23 01:24:39 PM PDT 24
Peak memory 219952 kb
Host smart-264fd908-647f-4010-9eb6-ffef821bedef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092516980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.4092516980
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.482093393
Short name T34
Test name
Test status
Simulation time 37922825156 ps
CPU time 45.95 seconds
Started Apr 23 01:24:14 PM PDT 24
Finished Apr 23 01:25:00 PM PDT 24
Peak memory 924788 kb
Host smart-9dd2c874-b102-4bf2-adc3-159faaa058bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482093393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c
_target_stress_wr.482093393
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.3749568436
Short name T1125
Test name
Test status
Simulation time 27132357254 ps
CPU time 1930.52 seconds
Started Apr 23 01:24:18 PM PDT 24
Finished Apr 23 01:56:29 PM PDT 24
Peak memory 6305344 kb
Host smart-8890decd-ea07-43c9-bff4-39db7255fc93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749568436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.3749568436
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.3560691477
Short name T1356
Test name
Test status
Simulation time 1410719125 ps
CPU time 7.21 seconds
Started Apr 23 01:24:22 PM PDT 24
Finished Apr 23 01:24:30 PM PDT 24
Peak memory 219980 kb
Host smart-9f73644f-6279-4a54-8530-1b875510224f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560691477 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.3560691477
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.386824512
Short name T662
Test name
Test status
Simulation time 20248236 ps
CPU time 0.68 seconds
Started Apr 23 01:21:42 PM PDT 24
Finished Apr 23 01:21:44 PM PDT 24
Peak memory 203400 kb
Host smart-cc87e33f-0ebc-4c2a-8712-fd1d29057586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386824512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.386824512
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1726439471
Short name T357
Test name
Test status
Simulation time 87317489 ps
CPU time 1.2 seconds
Started Apr 23 01:21:36 PM PDT 24
Finished Apr 23 01:21:38 PM PDT 24
Peak memory 212076 kb
Host smart-5f45ab1b-9acc-44e7-8feb-84143d35fd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726439471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1726439471
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.4189636329
Short name T667
Test name
Test status
Simulation time 264456005 ps
CPU time 4.79 seconds
Started Apr 23 01:21:36 PM PDT 24
Finished Apr 23 01:21:42 PM PDT 24
Peak memory 257416 kb
Host smart-8a4103e4-b616-47ac-aad8-97d3c613d746
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189636329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.4189636329
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.2915981696
Short name T1124
Test name
Test status
Simulation time 7998567998 ps
CPU time 116.91 seconds
Started Apr 23 01:21:36 PM PDT 24
Finished Apr 23 01:23:34 PM PDT 24
Peak memory 621068 kb
Host smart-a68489ba-583f-49ce-ade2-3162a8ee92d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915981696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.2915981696
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3405527215
Short name T765
Test name
Test status
Simulation time 2816523977 ps
CPU time 36.4 seconds
Started Apr 23 01:21:38 PM PDT 24
Finished Apr 23 01:22:15 PM PDT 24
Peak memory 515492 kb
Host smart-4c552700-bacc-4964-afe9-06904cbca3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405527215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3405527215
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.565639334
Short name T469
Test name
Test status
Simulation time 162964287 ps
CPU time 1.08 seconds
Started Apr 23 01:21:32 PM PDT 24
Finished Apr 23 01:21:33 PM PDT 24
Peak memory 203544 kb
Host smart-c2ecc692-1bc8-4b8b-b2d6-c865da0431a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565639334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt
.565639334
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.2372481099
Short name T1204
Test name
Test status
Simulation time 450126571 ps
CPU time 2.97 seconds
Started Apr 23 01:21:36 PM PDT 24
Finished Apr 23 01:21:40 PM PDT 24
Peak memory 203632 kb
Host smart-a7f80403-58ee-435b-969f-91531fd4416c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372481099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
2372481099
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.4245237475
Short name T491
Test name
Test status
Simulation time 1465702223 ps
CPU time 21.84 seconds
Started Apr 23 01:21:40 PM PDT 24
Finished Apr 23 01:22:03 PM PDT 24
Peak memory 297732 kb
Host smart-9958f98e-4cca-4b12-8e12-4cd5a2271d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245237475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.4245237475
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.1503507203
Short name T675
Test name
Test status
Simulation time 48037984 ps
CPU time 0.71 seconds
Started Apr 23 01:21:37 PM PDT 24
Finished Apr 23 01:21:39 PM PDT 24
Peak memory 203320 kb
Host smart-5f6c3a0d-3293-44da-8e5c-7b46edb5218e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503507203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1503507203
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.1953147215
Short name T79
Test name
Test status
Simulation time 7493259365 ps
CPU time 52.4 seconds
Started Apr 23 01:21:37 PM PDT 24
Finished Apr 23 01:22:30 PM PDT 24
Peak memory 253380 kb
Host smart-37e87663-ea4e-487a-a800-28aacffe0378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953147215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.1953147215
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.3403725386
Short name T1296
Test name
Test status
Simulation time 4261258793 ps
CPU time 27.26 seconds
Started Apr 23 01:21:35 PM PDT 24
Finished Apr 23 01:22:03 PM PDT 24
Peak memory 373116 kb
Host smart-efdad45c-b08e-498f-8bb2-a6020b0429f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403725386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.3403725386
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.363822055
Short name T179
Test name
Test status
Simulation time 35896147347 ps
CPU time 823.7 seconds
Started Apr 23 01:21:35 PM PDT 24
Finished Apr 23 01:35:20 PM PDT 24
Peak memory 2716024 kb
Host smart-af421dbc-d7d4-4fec-96bc-17424dde0031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363822055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.363822055
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.630909556
Short name T297
Test name
Test status
Simulation time 2961115560 ps
CPU time 11.39 seconds
Started Apr 23 01:21:39 PM PDT 24
Finished Apr 23 01:21:51 PM PDT 24
Peak memory 220252 kb
Host smart-b15da795-1c60-4a0f-9cee-58f2ba06b8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630909556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.630909556
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2107539691
Short name T122
Test name
Test status
Simulation time 254253197 ps
CPU time 0.92 seconds
Started Apr 23 01:21:39 PM PDT 24
Finished Apr 23 01:21:41 PM PDT 24
Peak memory 222108 kb
Host smart-473ad600-2a86-44e6-b04d-e032e24665f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107539691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2107539691
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.2800845991
Short name T407
Test name
Test status
Simulation time 2449007547 ps
CPU time 3.07 seconds
Started Apr 23 01:21:40 PM PDT 24
Finished Apr 23 01:21:44 PM PDT 24
Peak memory 203816 kb
Host smart-45e15e96-f814-4172-9442-b799ef3ffb55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800845991 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.2800845991
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.2933623285
Short name T840
Test name
Test status
Simulation time 10072235639 ps
CPU time 61.37 seconds
Started Apr 23 01:21:35 PM PDT 24
Finished Apr 23 01:22:37 PM PDT 24
Peak memory 454768 kb
Host smart-83654c1c-3f4d-4752-97d8-a95d90f6bd19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933623285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.2933623285
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.357853216
Short name T57
Test name
Test status
Simulation time 10098644049 ps
CPU time 64.15 seconds
Started Apr 23 01:21:37 PM PDT 24
Finished Apr 23 01:22:42 PM PDT 24
Peak memory 574388 kb
Host smart-af87b62a-817f-46a9-8e59-8098bef7792e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357853216 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_fifo_reset_tx.357853216
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.3152054136
Short name T752
Test name
Test status
Simulation time 771569202 ps
CPU time 2.39 seconds
Started Apr 23 01:21:39 PM PDT 24
Finished Apr 23 01:21:42 PM PDT 24
Peak memory 203792 kb
Host smart-650103c1-d9e3-464a-ab85-e6acb9cf4b68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152054136 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.3152054136
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.1684600856
Short name T660
Test name
Test status
Simulation time 701329280 ps
CPU time 3.86 seconds
Started Apr 23 01:21:36 PM PDT 24
Finished Apr 23 01:21:41 PM PDT 24
Peak memory 203732 kb
Host smart-6d9b7279-0fd9-4a5a-9b59-1edb86e7bb2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684600856 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.1684600856
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.3775756481
Short name T220
Test name
Test status
Simulation time 14550124198 ps
CPU time 36.62 seconds
Started Apr 23 01:21:37 PM PDT 24
Finished Apr 23 01:22:15 PM PDT 24
Peak memory 941192 kb
Host smart-1eb9f05b-86cb-4cd1-adf1-e064dab71dc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775756481 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.3775756481
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.3215557958
Short name T748
Test name
Test status
Simulation time 1993312769 ps
CPU time 13.97 seconds
Started Apr 23 01:21:37 PM PDT 24
Finished Apr 23 01:21:52 PM PDT 24
Peak memory 203696 kb
Host smart-400083f9-5063-4256-b2e6-cf5ada0110dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215557958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.3215557958
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.872469007
Short name T801
Test name
Test status
Simulation time 300741758 ps
CPU time 4.42 seconds
Started Apr 23 01:21:37 PM PDT 24
Finished Apr 23 01:21:42 PM PDT 24
Peak memory 203716 kb
Host smart-21da3149-b865-44fe-8a1b-1b318265f17e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872469007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_rd.872469007
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.2451160785
Short name T849
Test name
Test status
Simulation time 16047088191 ps
CPU time 8.93 seconds
Started Apr 23 01:21:41 PM PDT 24
Finished Apr 23 01:21:50 PM PDT 24
Peak memory 203700 kb
Host smart-1ff4f539-3aa5-4070-9087-9a5525dc8a97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451160785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.2451160785
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.1675176611
Short name T414
Test name
Test status
Simulation time 25775090002 ps
CPU time 186.99 seconds
Started Apr 23 01:21:38 PM PDT 24
Finished Apr 23 01:24:46 PM PDT 24
Peak memory 1404152 kb
Host smart-c6193c30-2e95-4053-8078-3c82ccdffe00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675176611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.1675176611
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.2856642552
Short name T1233
Test name
Test status
Simulation time 5896052982 ps
CPU time 7.01 seconds
Started Apr 23 01:21:38 PM PDT 24
Finished Apr 23 01:21:46 PM PDT 24
Peak memory 212020 kb
Host smart-55b8d7f6-b412-4dd9-9c93-2fe892d0ad78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856642552 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.2856642552
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.290126911
Short name T1157
Test name
Test status
Simulation time 18029049 ps
CPU time 0.64 seconds
Started Apr 23 01:24:37 PM PDT 24
Finished Apr 23 01:24:39 PM PDT 24
Peak memory 203256 kb
Host smart-85c881db-a7e0-4017-b2a3-6055a1b37040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290126911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.290126911
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.30948866
Short name T1082
Test name
Test status
Simulation time 87544417 ps
CPU time 1.85 seconds
Started Apr 23 01:24:27 PM PDT 24
Finished Apr 23 01:24:29 PM PDT 24
Peak memory 212048 kb
Host smart-98110d4d-6d3d-4032-a190-e8155c9f15fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30948866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.30948866
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.4151573777
Short name T905
Test name
Test status
Simulation time 282914406 ps
CPU time 6.07 seconds
Started Apr 23 01:24:24 PM PDT 24
Finished Apr 23 01:24:30 PM PDT 24
Peak memory 255920 kb
Host smart-1ae32c79-9d0f-40ed-8885-6414720328ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151573777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.4151573777
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.2396963637
Short name T91
Test name
Test status
Simulation time 5379658459 ps
CPU time 73.95 seconds
Started Apr 23 01:24:29 PM PDT 24
Finished Apr 23 01:25:43 PM PDT 24
Peak memory 712092 kb
Host smart-ad18f1fb-f466-4c89-af5f-258c999e036f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396963637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.2396963637
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.3883582562
Short name T434
Test name
Test status
Simulation time 2963481199 ps
CPU time 69.44 seconds
Started Apr 23 01:24:27 PM PDT 24
Finished Apr 23 01:25:37 PM PDT 24
Peak memory 750796 kb
Host smart-0ca9e908-7841-4aab-8283-db1ff3e7b957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883582562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3883582562
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.1916227380
Short name T101
Test name
Test status
Simulation time 98391776 ps
CPU time 0.84 seconds
Started Apr 23 01:24:28 PM PDT 24
Finished Apr 23 01:24:30 PM PDT 24
Peak memory 203368 kb
Host smart-e8b5cd53-8999-4ed7-81e7-63e3515cd2f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916227380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.1916227380
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.579717472
Short name T1016
Test name
Test status
Simulation time 309354304 ps
CPU time 4.77 seconds
Started Apr 23 01:24:23 PM PDT 24
Finished Apr 23 01:24:28 PM PDT 24
Peak memory 230916 kb
Host smart-28b6eed0-34ed-489c-b6c7-b4f7d60f07f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579717472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.
579717472
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.2652661648
Short name T581
Test name
Test status
Simulation time 12137300189 ps
CPU time 151.91 seconds
Started Apr 23 01:24:28 PM PDT 24
Finished Apr 23 01:27:01 PM PDT 24
Peak memory 752356 kb
Host smart-838e9edc-509d-4391-9bca-6e64c465edc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652661648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.2652661648
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.2320120917
Short name T67
Test name
Test status
Simulation time 554817600 ps
CPU time 11.92 seconds
Started Apr 23 01:24:35 PM PDT 24
Finished Apr 23 01:24:48 PM PDT 24
Peak memory 203620 kb
Host smart-4666db3e-2959-4883-bf5e-805354320c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320120917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.2320120917
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.1713207566
Short name T63
Test name
Test status
Simulation time 1056814450 ps
CPU time 49.88 seconds
Started Apr 23 01:24:35 PM PDT 24
Finished Apr 23 01:25:26 PM PDT 24
Peak memory 298092 kb
Host smart-670b413f-12c3-4cb9-b9b1-35bf723ea9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713207566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.1713207566
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.928726440
Short name T939
Test name
Test status
Simulation time 93301517 ps
CPU time 0.65 seconds
Started Apr 23 01:24:23 PM PDT 24
Finished Apr 23 01:24:24 PM PDT 24
Peak memory 203324 kb
Host smart-8c735a18-fb1f-478b-ad48-a1e892297568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928726440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.928726440
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.3666907515
Short name T1027
Test name
Test status
Simulation time 1075324944 ps
CPU time 44.01 seconds
Started Apr 23 01:24:28 PM PDT 24
Finished Apr 23 01:25:13 PM PDT 24
Peak memory 219084 kb
Host smart-860cf38c-5ac6-4a75-97c0-fb73f5a74831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666907515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.3666907515
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.2367598816
Short name T874
Test name
Test status
Simulation time 5758008358 ps
CPU time 28.12 seconds
Started Apr 23 01:24:28 PM PDT 24
Finished Apr 23 01:24:57 PM PDT 24
Peak memory 332736 kb
Host smart-5c64cfe1-5568-45a4-b08d-954ed7e7bcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367598816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.2367598816
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.1465231917
Short name T238
Test name
Test status
Simulation time 48013031543 ps
CPU time 1601.42 seconds
Started Apr 23 01:24:29 PM PDT 24
Finished Apr 23 01:51:11 PM PDT 24
Peak memory 2878400 kb
Host smart-589c0d63-08bd-456e-9ba9-970e7cbaea41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465231917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.1465231917
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.587381322
Short name T322
Test name
Test status
Simulation time 2757945825 ps
CPU time 8.61 seconds
Started Apr 23 01:24:28 PM PDT 24
Finished Apr 23 01:24:37 PM PDT 24
Peak memory 217944 kb
Host smart-c0ec2a68-89c9-4037-8de8-6aa620e0c0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587381322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.587381322
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.3093701995
Short name T602
Test name
Test status
Simulation time 2753931114 ps
CPU time 3.6 seconds
Started Apr 23 01:24:30 PM PDT 24
Finished Apr 23 01:24:34 PM PDT 24
Peak memory 211956 kb
Host smart-da0c7a70-765b-4283-a4ab-b84a5600dcaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093701995 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3093701995
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.1776467566
Short name T562
Test name
Test status
Simulation time 10430667278 ps
CPU time 11.94 seconds
Started Apr 23 01:24:29 PM PDT 24
Finished Apr 23 01:24:42 PM PDT 24
Peak memory 269476 kb
Host smart-0c524108-5e11-4c48-8100-7674ec14d6a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776467566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.1776467566
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.2714654994
Short name T941
Test name
Test status
Simulation time 10238346235 ps
CPU time 12.95 seconds
Started Apr 23 01:24:32 PM PDT 24
Finished Apr 23 01:24:46 PM PDT 24
Peak memory 281712 kb
Host smart-b55ad759-7a2b-4861-a94a-f634774771da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714654994 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.2714654994
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.865890559
Short name T1220
Test name
Test status
Simulation time 1678792924 ps
CPU time 2.65 seconds
Started Apr 23 01:24:35 PM PDT 24
Finished Apr 23 01:24:38 PM PDT 24
Peak memory 203712 kb
Host smart-b38d0873-1a36-4844-b56f-6ae9622abf8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865890559 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.i2c_target_hrst.865890559
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.33602084
Short name T1321
Test name
Test status
Simulation time 915201810 ps
CPU time 4.83 seconds
Started Apr 23 01:24:30 PM PDT 24
Finished Apr 23 01:24:36 PM PDT 24
Peak memory 203712 kb
Host smart-7e970840-ab3e-426f-bf67-fabb0d80ced5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33602084 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.33602084
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.4217262176
Short name T5
Test name
Test status
Simulation time 8447457742 ps
CPU time 108.9 seconds
Started Apr 23 01:24:29 PM PDT 24
Finished Apr 23 01:26:18 PM PDT 24
Peak memory 2164928 kb
Host smart-afd86740-f13b-4b6b-b727-04b8461ab6cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217262176 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.4217262176
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.3922730961
Short name T1324
Test name
Test status
Simulation time 5279550930 ps
CPU time 18.57 seconds
Started Apr 23 01:24:26 PM PDT 24
Finished Apr 23 01:24:46 PM PDT 24
Peak memory 203716 kb
Host smart-6b91d6c9-a9cf-4929-873c-a339ec163800
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922730961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.3922730961
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.2399360686
Short name T1144
Test name
Test status
Simulation time 1496368266 ps
CPU time 6.31 seconds
Started Apr 23 01:24:32 PM PDT 24
Finished Apr 23 01:24:39 PM PDT 24
Peak memory 203680 kb
Host smart-80773639-00ee-4699-814d-7a7109561325
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399360686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.2399360686
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.3075333842
Short name T738
Test name
Test status
Simulation time 29757759403 ps
CPU time 31.41 seconds
Started Apr 23 01:24:32 PM PDT 24
Finished Apr 23 01:25:04 PM PDT 24
Peak memory 669576 kb
Host smart-4cdbba1d-c9ad-4979-9657-393634766519
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075333842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.3075333842
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.3731216338
Short name T442
Test name
Test status
Simulation time 10945714153 ps
CPU time 1238.91 seconds
Started Apr 23 01:24:28 PM PDT 24
Finished Apr 23 01:45:07 PM PDT 24
Peak memory 2713916 kb
Host smart-b60ecbc9-e195-4792-8f9d-89035f9d5c5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731216338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.3731216338
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.641408663
Short name T693
Test name
Test status
Simulation time 3205837169 ps
CPU time 6.7 seconds
Started Apr 23 01:24:30 PM PDT 24
Finished Apr 23 01:24:37 PM PDT 24
Peak memory 211980 kb
Host smart-1bcc07bb-7cd1-4f8d-a872-bdd9c7c65a1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641408663 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.641408663
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.1976140564
Short name T794
Test name
Test status
Simulation time 26614280 ps
CPU time 0.63 seconds
Started Apr 23 01:24:38 PM PDT 24
Finished Apr 23 01:24:40 PM PDT 24
Peak memory 203304 kb
Host smart-a03fb0e9-f9b5-4225-95fe-f94ed03a6941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976140564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.1976140564
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.714453841
Short name T257
Test name
Test status
Simulation time 582067079 ps
CPU time 1.44 seconds
Started Apr 23 01:24:33 PM PDT 24
Finished Apr 23 01:24:35 PM PDT 24
Peak memory 211996 kb
Host smart-4da9ae75-cada-4edd-87ee-f14a3531f585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714453841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.714453841
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2284657618
Short name T396
Test name
Test status
Simulation time 177883151 ps
CPU time 8.53 seconds
Started Apr 23 01:24:32 PM PDT 24
Finished Apr 23 01:24:41 PM PDT 24
Peak memory 218696 kb
Host smart-e0eb5c30-30ea-4264-bbcf-9f62d2bebc6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284657618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2284657618
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.2796479070
Short name T785
Test name
Test status
Simulation time 1757043016 ps
CPU time 30.8 seconds
Started Apr 23 01:24:36 PM PDT 24
Finished Apr 23 01:25:08 PM PDT 24
Peak memory 461424 kb
Host smart-23636550-6cf6-4c88-a0bc-9159cd166869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796479070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.2796479070
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.3785899300
Short name T1182
Test name
Test status
Simulation time 8543817437 ps
CPU time 60.89 seconds
Started Apr 23 01:24:35 PM PDT 24
Finished Apr 23 01:25:37 PM PDT 24
Peak memory 593324 kb
Host smart-fbbd4b0f-b874-4d49-a3c8-c8cfe8d321c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785899300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.3785899300
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.1440332442
Short name T744
Test name
Test status
Simulation time 349555429 ps
CPU time 0.82 seconds
Started Apr 23 01:24:31 PM PDT 24
Finished Apr 23 01:24:32 PM PDT 24
Peak memory 203412 kb
Host smart-cbfd2b56-0cad-4c6f-8d11-7db063128b02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440332442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.1440332442
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.2173388432
Short name T471
Test name
Test status
Simulation time 584778386 ps
CPU time 3.23 seconds
Started Apr 23 01:24:31 PM PDT 24
Finished Apr 23 01:24:35 PM PDT 24
Peak memory 223604 kb
Host smart-9365d2cb-960c-499c-81c5-5e52b85c61e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173388432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.2173388432
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.1417600530
Short name T757
Test name
Test status
Simulation time 22647804177 ps
CPU time 145.4 seconds
Started Apr 23 01:24:30 PM PDT 24
Finished Apr 23 01:26:56 PM PDT 24
Peak memory 768640 kb
Host smart-8ac7739c-0d28-4f7e-83c9-c0d32ac7f884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417600530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.1417600530
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.3773784557
Short name T379
Test name
Test status
Simulation time 315091799 ps
CPU time 5.09 seconds
Started Apr 23 01:24:38 PM PDT 24
Finished Apr 23 01:24:44 PM PDT 24
Peak memory 203672 kb
Host smart-c0bb68d5-f0e8-44f8-8a14-ed740cb0a005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773784557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.3773784557
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.301399671
Short name T1314
Test name
Test status
Simulation time 2852719622 ps
CPU time 62.99 seconds
Started Apr 23 01:24:37 PM PDT 24
Finished Apr 23 01:25:41 PM PDT 24
Peak memory 285168 kb
Host smart-6f535685-b818-4e14-b1a4-5870428d5cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301399671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.301399671
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.3805626938
Short name T1013
Test name
Test status
Simulation time 87640802 ps
CPU time 0.68 seconds
Started Apr 23 01:24:36 PM PDT 24
Finished Apr 23 01:24:37 PM PDT 24
Peak memory 203272 kb
Host smart-2c8d17c9-40ea-4076-b07a-7a3c5eb6b66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805626938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.3805626938
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.1214145676
Short name T741
Test name
Test status
Simulation time 3228209999 ps
CPU time 40.7 seconds
Started Apr 23 01:24:35 PM PDT 24
Finished Apr 23 01:25:16 PM PDT 24
Peak memory 373308 kb
Host smart-9856567a-e196-4ec1-9e0b-d1edd60dbbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214145676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.1214145676
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.3562955449
Short name T421
Test name
Test status
Simulation time 7992478509 ps
CPU time 45.96 seconds
Started Apr 23 01:24:31 PM PDT 24
Finished Apr 23 01:25:18 PM PDT 24
Peak memory 487080 kb
Host smart-5960f484-30a6-4062-9276-67fc7365fee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562955449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.3562955449
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.2273671819
Short name T947
Test name
Test status
Simulation time 2090567436 ps
CPU time 25.12 seconds
Started Apr 23 01:24:33 PM PDT 24
Finished Apr 23 01:24:59 PM PDT 24
Peak memory 212000 kb
Host smart-6f0df421-60d1-494e-9e68-afc77ed17e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273671819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.2273671819
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.666672560
Short name T1318
Test name
Test status
Simulation time 3134736993 ps
CPU time 3 seconds
Started Apr 23 01:24:37 PM PDT 24
Finished Apr 23 01:24:41 PM PDT 24
Peak memory 203832 kb
Host smart-52abbea0-1e30-42aa-90dc-80170f905f0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666672560 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.666672560
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.240876039
Short name T526
Test name
Test status
Simulation time 10083302673 ps
CPU time 31.53 seconds
Started Apr 23 01:24:38 PM PDT 24
Finished Apr 23 01:25:11 PM PDT 24
Peak memory 313884 kb
Host smart-865c1e61-2593-4b59-98c1-f9fe82672aee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240876039 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_acq.240876039
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3708516859
Short name T721
Test name
Test status
Simulation time 10281941280 ps
CPU time 11.1 seconds
Started Apr 23 01:24:37 PM PDT 24
Finished Apr 23 01:24:50 PM PDT 24
Peak memory 251532 kb
Host smart-50d22002-a036-4ae8-a578-25e9b2e87cde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708516859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3708516859
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.829329227
Short name T419
Test name
Test status
Simulation time 262266669 ps
CPU time 2.06 seconds
Started Apr 23 01:24:39 PM PDT 24
Finished Apr 23 01:24:42 PM PDT 24
Peak memory 203740 kb
Host smart-bae3e6b1-8a48-42c8-843e-93db05b08525
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829329227 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.i2c_target_hrst.829329227
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.3571705835
Short name T360
Test name
Test status
Simulation time 1884881392 ps
CPU time 5.76 seconds
Started Apr 23 01:24:34 PM PDT 24
Finished Apr 23 01:24:40 PM PDT 24
Peak memory 217452 kb
Host smart-1f94ce63-a9a7-45ef-bb0a-cc8bf8aa8a28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571705835 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.3571705835
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.2230838061
Short name T713
Test name
Test status
Simulation time 13426873963 ps
CPU time 93.93 seconds
Started Apr 23 01:24:32 PM PDT 24
Finished Apr 23 01:26:07 PM PDT 24
Peak memory 1536872 kb
Host smart-47a98411-8a5b-4545-aeb1-588e8b9de0e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230838061 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.2230838061
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.386394332
Short name T1165
Test name
Test status
Simulation time 2581549018 ps
CPU time 11.18 seconds
Started Apr 23 01:24:33 PM PDT 24
Finished Apr 23 01:24:45 PM PDT 24
Peak memory 203764 kb
Host smart-5a9d1b95-6599-4458-b4d1-e8064d956681
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386394332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_tar
get_smoke.386394332
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.2953847397
Short name T829
Test name
Test status
Simulation time 296312498 ps
CPU time 11.96 seconds
Started Apr 23 01:24:34 PM PDT 24
Finished Apr 23 01:24:47 PM PDT 24
Peak memory 203648 kb
Host smart-7158aa70-73a2-40cf-aaa3-70bedb2c3658
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953847397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.2953847397
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.2031105475
Short name T342
Test name
Test status
Simulation time 23474674822 ps
CPU time 30.45 seconds
Started Apr 23 01:24:33 PM PDT 24
Finished Apr 23 01:25:04 PM PDT 24
Peak memory 536088 kb
Host smart-da2973fb-fbe3-4422-b9c8-4530d6544e4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031105475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.2031105475
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.1221994301
Short name T818
Test name
Test status
Simulation time 38334702514 ps
CPU time 791.56 seconds
Started Apr 23 01:24:35 PM PDT 24
Finished Apr 23 01:37:47 PM PDT 24
Peak memory 2096424 kb
Host smart-79e8a9dd-ec1e-4009-a921-d8f3936a7a6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221994301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.1221994301
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.1899808273
Short name T455
Test name
Test status
Simulation time 3841259269 ps
CPU time 6.1 seconds
Started Apr 23 01:24:33 PM PDT 24
Finished Apr 23 01:24:39 PM PDT 24
Peak memory 203804 kb
Host smart-09d7bf0e-d7ac-4104-8436-883544096ff6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899808273 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.1899808273
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1153993158
Short name T1260
Test name
Test status
Simulation time 39099514 ps
CPU time 0.61 seconds
Started Apr 23 01:24:56 PM PDT 24
Finished Apr 23 01:24:57 PM PDT 24
Peak memory 203384 kb
Host smart-0e400ad3-9bf5-455a-9987-69587eae93df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153993158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1153993158
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.2663317315
Short name T1329
Test name
Test status
Simulation time 217174901 ps
CPU time 1.34 seconds
Started Apr 23 01:24:41 PM PDT 24
Finished Apr 23 01:24:43 PM PDT 24
Peak memory 203756 kb
Host smart-96f9889f-987f-4653-814c-35990f573eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663317315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.2663317315
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.3479956776
Short name T1066
Test name
Test status
Simulation time 324883051 ps
CPU time 17 seconds
Started Apr 23 01:24:37 PM PDT 24
Finished Apr 23 01:24:55 PM PDT 24
Peak memory 270040 kb
Host smart-b07cbe4f-670e-42d4-b1e9-781d0c0b2bfa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479956776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.3479956776
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.2313383972
Short name T458
Test name
Test status
Simulation time 10158145578 ps
CPU time 40.59 seconds
Started Apr 23 01:24:39 PM PDT 24
Finished Apr 23 01:25:20 PM PDT 24
Peak memory 481872 kb
Host smart-828f5ae9-9884-42b7-9dfd-d1756bd4b544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313383972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2313383972
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.3079947378
Short name T700
Test name
Test status
Simulation time 1928596761 ps
CPU time 144.69 seconds
Started Apr 23 01:24:40 PM PDT 24
Finished Apr 23 01:27:05 PM PDT 24
Peak memory 661368 kb
Host smart-e6ed7aa0-7d86-44aa-b272-b2f39f367861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079947378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.3079947378
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.1662490702
Short name T882
Test name
Test status
Simulation time 160756237 ps
CPU time 1.06 seconds
Started Apr 23 01:24:39 PM PDT 24
Finished Apr 23 01:24:41 PM PDT 24
Peak memory 203400 kb
Host smart-adc4216b-9574-459b-8b2c-519f75fb6cfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662490702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.1662490702
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.256545018
Short name T813
Test name
Test status
Simulation time 145279820 ps
CPU time 7.85 seconds
Started Apr 23 01:24:37 PM PDT 24
Finished Apr 23 01:24:46 PM PDT 24
Peak memory 203608 kb
Host smart-200e426c-23a4-4a67-a249-efbf34c6fc08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256545018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.
256545018
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.1893710571
Short name T981
Test name
Test status
Simulation time 3542513313 ps
CPU time 236.42 seconds
Started Apr 23 01:24:38 PM PDT 24
Finished Apr 23 01:28:35 PM PDT 24
Peak memory 941264 kb
Host smart-19e62e6e-a9ba-4ab5-855b-0c98af642029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893710571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.1893710571
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.1825928581
Short name T69
Test name
Test status
Simulation time 1079255088 ps
CPU time 8.79 seconds
Started Apr 23 01:24:48 PM PDT 24
Finished Apr 23 01:24:57 PM PDT 24
Peak memory 203616 kb
Host smart-a5e0aa4c-edc0-4aab-9c3c-44ba1812a618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825928581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.1825928581
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.2117932953
Short name T1134
Test name
Test status
Simulation time 30897300383 ps
CPU time 109.93 seconds
Started Apr 23 01:24:57 PM PDT 24
Finished Apr 23 01:26:48 PM PDT 24
Peak memory 419444 kb
Host smart-f40458a4-acb4-47c6-afea-496414d8ca47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117932953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.2117932953
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.2457349050
Short name T936
Test name
Test status
Simulation time 223723159 ps
CPU time 0.71 seconds
Started Apr 23 01:24:40 PM PDT 24
Finished Apr 23 01:24:41 PM PDT 24
Peak memory 203412 kb
Host smart-7d7f1d6a-9812-4518-90e2-55b2c7aad48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457349050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2457349050
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.3515700177
Short name T1344
Test name
Test status
Simulation time 5031771329 ps
CPU time 196.68 seconds
Started Apr 23 01:24:41 PM PDT 24
Finished Apr 23 01:27:59 PM PDT 24
Peak memory 223804 kb
Host smart-e1a80859-26ad-468f-99ba-56c689af81c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515700177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.3515700177
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.439524664
Short name T367
Test name
Test status
Simulation time 8218724040 ps
CPU time 31.21 seconds
Started Apr 23 01:24:37 PM PDT 24
Finished Apr 23 01:25:09 PM PDT 24
Peak memory 333100 kb
Host smart-ce967651-1683-4024-af85-eef10daf6435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439524664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.439524664
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.3035782353
Short name T78
Test name
Test status
Simulation time 33980553143 ps
CPU time 603.42 seconds
Started Apr 23 01:24:41 PM PDT 24
Finished Apr 23 01:34:45 PM PDT 24
Peak memory 1076268 kb
Host smart-22d83ca1-6116-4ea8-a04f-26a979449408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035782353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.3035782353
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.3091574296
Short name T918
Test name
Test status
Simulation time 288450334 ps
CPU time 5.75 seconds
Started Apr 23 01:24:42 PM PDT 24
Finished Apr 23 01:24:48 PM PDT 24
Peak memory 211820 kb
Host smart-a55e2f2c-a2f1-430d-b551-46d4075f7733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091574296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.3091574296
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.2004057556
Short name T199
Test name
Test status
Simulation time 10110125553 ps
CPU time 42.36 seconds
Started Apr 23 01:24:45 PM PDT 24
Finished Apr 23 01:25:28 PM PDT 24
Peak memory 404020 kb
Host smart-4b94c024-1b26-401d-aec4-7233383e6aeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004057556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.2004057556
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.3922338405
Short name T37
Test name
Test status
Simulation time 10040946346 ps
CPU time 72.11 seconds
Started Apr 23 01:24:45 PM PDT 24
Finished Apr 23 01:25:58 PM PDT 24
Peak memory 542344 kb
Host smart-0d846ba7-e495-4326-882d-ba3de8556b36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922338405 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.3922338405
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.4126609780
Short name T514
Test name
Test status
Simulation time 511724688 ps
CPU time 2.8 seconds
Started Apr 23 01:24:47 PM PDT 24
Finished Apr 23 01:24:51 PM PDT 24
Peak memory 203668 kb
Host smart-4325e2df-6b75-462e-bbc7-dabee5eacb4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126609780 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.4126609780
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.242451373
Short name T1085
Test name
Test status
Simulation time 2274981391 ps
CPU time 5.68 seconds
Started Apr 23 01:24:46 PM PDT 24
Finished Apr 23 01:24:52 PM PDT 24
Peak memory 217376 kb
Host smart-dbbe7aab-3f19-4f97-a6cc-39645464295a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242451373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_intr_smoke.242451373
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.4166972355
Short name T406
Test name
Test status
Simulation time 8840492152 ps
CPU time 6.48 seconds
Started Apr 23 01:24:46 PM PDT 24
Finished Apr 23 01:24:53 PM PDT 24
Peak memory 203740 kb
Host smart-73435afb-5247-4e1b-a7a3-c2f469679a7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166972355 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.4166972355
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.791604759
Short name T1039
Test name
Test status
Simulation time 3521339513 ps
CPU time 29.93 seconds
Started Apr 23 01:24:41 PM PDT 24
Finished Apr 23 01:25:11 PM PDT 24
Peak memory 203672 kb
Host smart-ddaa5d63-c564-4a0a-81f3-4cbff5e3b496
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791604759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.791604759
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.2673087341
Short name T570
Test name
Test status
Simulation time 1086767649 ps
CPU time 11.56 seconds
Started Apr 23 01:24:48 PM PDT 24
Finished Apr 23 01:25:00 PM PDT 24
Peak memory 203704 kb
Host smart-b04c1a35-134c-4500-8492-185e7106b276
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673087341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.2673087341
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.314812764
Short name T962
Test name
Test status
Simulation time 28441294569 ps
CPU time 23.87 seconds
Started Apr 23 01:24:47 PM PDT 24
Finished Apr 23 01:25:11 PM PDT 24
Peak memory 569916 kb
Host smart-f9653165-757d-4422-aa8e-34cd94b8a2ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314812764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_wr.314812764
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.2454072878
Short name T385
Test name
Test status
Simulation time 45891788073 ps
CPU time 72.26 seconds
Started Apr 23 01:24:45 PM PDT 24
Finished Apr 23 01:25:58 PM PDT 24
Peak memory 696332 kb
Host smart-dc519048-062e-433d-a8c7-86d3fa9d8a44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454072878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.2454072878
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.2449989827
Short name T398
Test name
Test status
Simulation time 1364034727 ps
CPU time 7.19 seconds
Started Apr 23 01:24:43 PM PDT 24
Finished Apr 23 01:24:51 PM PDT 24
Peak memory 220040 kb
Host smart-a9ea6ff2-580b-4afe-a960-6616faf81a65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449989827 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.2449989827
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_unexp_stop.492236378
Short name T22
Test name
Test status
Simulation time 3907836728 ps
CPU time 5.24 seconds
Started Apr 23 01:24:44 PM PDT 24
Finished Apr 23 01:24:50 PM PDT 24
Peak memory 204256 kb
Host smart-4b561012-1bcd-4955-bae7-d217c0eb7df8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492236378 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_unexp_stop.492236378
Directory /workspace/22.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/23.i2c_alert_test.15505023
Short name T1238
Test name
Test status
Simulation time 17794901 ps
CPU time 0.63 seconds
Started Apr 23 01:25:00 PM PDT 24
Finished Apr 23 01:25:01 PM PDT 24
Peak memory 203392 kb
Host smart-a3338148-feaf-4a90-a56c-5326807e9cce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15505023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.15505023
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.3758582670
Short name T1247
Test name
Test status
Simulation time 232272309 ps
CPU time 12.38 seconds
Started Apr 23 01:24:53 PM PDT 24
Finished Apr 23 01:25:06 PM PDT 24
Peak memory 250936 kb
Host smart-3c1758b8-4d04-46f5-8d5c-fda0377660a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758582670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.3758582670
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.1924743700
Short name T366
Test name
Test status
Simulation time 1507798412 ps
CPU time 39.21 seconds
Started Apr 23 01:24:52 PM PDT 24
Finished Apr 23 01:25:32 PM PDT 24
Peak memory 496044 kb
Host smart-5585761a-cd2c-420e-badb-fdfaf384e261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924743700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1924743700
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.2895409738
Short name T477
Test name
Test status
Simulation time 2153445691 ps
CPU time 76.12 seconds
Started Apr 23 01:24:52 PM PDT 24
Finished Apr 23 01:26:09 PM PDT 24
Peak memory 729100 kb
Host smart-9d296351-7f99-45a0-a72c-37b7e90ee222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895409738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.2895409738
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.1460388662
Short name T1063
Test name
Test status
Simulation time 122917493 ps
CPU time 1.18 seconds
Started Apr 23 01:24:53 PM PDT 24
Finished Apr 23 01:24:55 PM PDT 24
Peak memory 203556 kb
Host smart-2c0107fc-2800-4c66-94d7-fe99fb836288
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460388662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.1460388662
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1369548611
Short name T1196
Test name
Test status
Simulation time 569318360 ps
CPU time 6.29 seconds
Started Apr 23 01:24:52 PM PDT 24
Finished Apr 23 01:24:59 PM PDT 24
Peak memory 203656 kb
Host smart-39734c1a-abb5-4b50-88a3-0c508d049e48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369548611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.1369548611
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.2355711108
Short name T574
Test name
Test status
Simulation time 2941174730 ps
CPU time 77.81 seconds
Started Apr 23 01:24:54 PM PDT 24
Finished Apr 23 01:26:12 PM PDT 24
Peak memory 851704 kb
Host smart-955681c6-ed04-459b-bcb6-e3c6740b8c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355711108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.2355711108
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.1789350844
Short name T352
Test name
Test status
Simulation time 378402769 ps
CPU time 15.7 seconds
Started Apr 23 01:24:59 PM PDT 24
Finished Apr 23 01:25:15 PM PDT 24
Peak memory 203708 kb
Host smart-8632e0d4-07b8-47c5-9f4a-bf6cf03219a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789350844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.1789350844
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_perf.1582304225
Short name T60
Test name
Test status
Simulation time 3931917277 ps
CPU time 61.31 seconds
Started Apr 23 01:24:57 PM PDT 24
Finished Apr 23 01:25:59 PM PDT 24
Peak memory 439676 kb
Host smart-c1c7d684-86a0-4a0b-a61c-ee8393a6a79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582304225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.1582304225
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3923883945
Short name T1079
Test name
Test status
Simulation time 2942004578 ps
CPU time 75.93 seconds
Started Apr 23 01:24:48 PM PDT 24
Finished Apr 23 01:26:05 PM PDT 24
Peak memory 373220 kb
Host smart-5530f186-d31f-43ca-be86-6f3785a0ae90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923883945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3923883945
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.2784020750
Short name T1103
Test name
Test status
Simulation time 45470380555 ps
CPU time 1314.65 seconds
Started Apr 23 01:24:56 PM PDT 24
Finished Apr 23 01:46:52 PM PDT 24
Peak memory 1177440 kb
Host smart-bb3008aa-f064-425b-8652-9b785ee92de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784020750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.2784020750
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.3013599857
Short name T146
Test name
Test status
Simulation time 1229088571 ps
CPU time 11.25 seconds
Started Apr 23 01:24:51 PM PDT 24
Finished Apr 23 01:25:03 PM PDT 24
Peak memory 227940 kb
Host smart-b6f00bc1-2c28-4e96-aeb0-36373d3bb1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013599857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.3013599857
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.3471485308
Short name T268
Test name
Test status
Simulation time 421522227 ps
CPU time 2.39 seconds
Started Apr 23 01:24:55 PM PDT 24
Finished Apr 23 01:24:58 PM PDT 24
Peak memory 203860 kb
Host smart-e301594b-f4cd-43b6-92ef-694a334a7f24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471485308 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.3471485308
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2683566478
Short name T1353
Test name
Test status
Simulation time 10070659599 ps
CPU time 32.51 seconds
Started Apr 23 01:24:56 PM PDT 24
Finished Apr 23 01:25:29 PM PDT 24
Peak memory 317880 kb
Host smart-8c99c953-e262-491b-b562-faf7ca74420a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683566478 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2683566478
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.888952283
Short name T907
Test name
Test status
Simulation time 10116700081 ps
CPU time 26.63 seconds
Started Apr 23 01:24:55 PM PDT 24
Finished Apr 23 01:25:22 PM PDT 24
Peak memory 335392 kb
Host smart-6c2f6d64-d44f-4563-86d1-f75edc030238
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888952283 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_fifo_reset_tx.888952283
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.3754285345
Short name T949
Test name
Test status
Simulation time 474782468 ps
CPU time 2.88 seconds
Started Apr 23 01:25:01 PM PDT 24
Finished Apr 23 01:25:04 PM PDT 24
Peak memory 203768 kb
Host smart-d67036b0-a586-4d3d-81be-380e2fe032c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754285345 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.3754285345
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.2925350670
Short name T851
Test name
Test status
Simulation time 989855789 ps
CPU time 5.64 seconds
Started Apr 23 01:24:55 PM PDT 24
Finished Apr 23 01:25:01 PM PDT 24
Peak memory 207240 kb
Host smart-a141f9c3-f5b6-4914-bd70-653b61d2be74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925350670 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.2925350670
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.4078947292
Short name T728
Test name
Test status
Simulation time 3356597449 ps
CPU time 2.4 seconds
Started Apr 23 01:25:02 PM PDT 24
Finished Apr 23 01:25:05 PM PDT 24
Peak memory 203828 kb
Host smart-3097b9c0-eae7-4149-95c0-6a2e805596e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078947292 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.4078947292
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.577162581
Short name T376
Test name
Test status
Simulation time 7788134146 ps
CPU time 32.56 seconds
Started Apr 23 01:24:55 PM PDT 24
Finished Apr 23 01:25:28 PM PDT 24
Peak memory 203728 kb
Host smart-d77fe90c-69cd-4038-a69b-6b0c8921fe9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577162581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_tar
get_smoke.577162581
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.3216081131
Short name T919
Test name
Test status
Simulation time 865922844 ps
CPU time 12.24 seconds
Started Apr 23 01:24:53 PM PDT 24
Finished Apr 23 01:25:06 PM PDT 24
Peak memory 216832 kb
Host smart-11d71d10-1066-4665-8dda-a6133f87b3c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216081131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.3216081131
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.245366070
Short name T33
Test name
Test status
Simulation time 47747999388 ps
CPU time 85.06 seconds
Started Apr 23 01:24:56 PM PDT 24
Finished Apr 23 01:26:22 PM PDT 24
Peak memory 1310388 kb
Host smart-301806a6-c19a-4b3a-99fe-283590c34efd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245366070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c
_target_stress_wr.245366070
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.1414174096
Short name T1141
Test name
Test status
Simulation time 22948237703 ps
CPU time 504.14 seconds
Started Apr 23 01:24:56 PM PDT 24
Finished Apr 23 01:33:20 PM PDT 24
Peak memory 1390308 kb
Host smart-50de275c-83bf-4665-b2f8-103f5a559c9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414174096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.1414174096
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.821093117
Short name T13
Test name
Test status
Simulation time 1461020158 ps
CPU time 6.6 seconds
Started Apr 23 01:24:58 PM PDT 24
Finished Apr 23 01:25:05 PM PDT 24
Peak memory 203780 kb
Host smart-a77e50bb-20d8-40a4-b6da-2b1a626797d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821093117 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_timeout.821093117
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.3121190800
Short name T945
Test name
Test status
Simulation time 58666444 ps
CPU time 0.64 seconds
Started Apr 23 01:25:09 PM PDT 24
Finished Apr 23 01:25:10 PM PDT 24
Peak memory 203268 kb
Host smart-fb117206-29f3-4a4d-9d5c-b92769d48a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121190800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.3121190800
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.4109432773
Short name T265
Test name
Test status
Simulation time 220026061 ps
CPU time 1.08 seconds
Started Apr 23 01:25:04 PM PDT 24
Finished Apr 23 01:25:06 PM PDT 24
Peak memory 211944 kb
Host smart-df148abd-1e60-46d6-bfa5-ef2666e5639b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109432773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.4109432773
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.1897826832
Short name T618
Test name
Test status
Simulation time 249226101 ps
CPU time 4.38 seconds
Started Apr 23 01:25:04 PM PDT 24
Finished Apr 23 01:25:10 PM PDT 24
Peak memory 243780 kb
Host smart-c6e92ac8-3498-44ee-ad71-e29dbaf9aef7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897826832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.1897826832
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.3788542810
Short name T113
Test name
Test status
Simulation time 2414359483 ps
CPU time 35.29 seconds
Started Apr 23 01:25:06 PM PDT 24
Finished Apr 23 01:25:42 PM PDT 24
Peak memory 471708 kb
Host smart-034d2d65-51a5-4ebe-a2ac-21e039563d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788542810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.3788542810
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.611190859
Short name T87
Test name
Test status
Simulation time 6682585007 ps
CPU time 48.87 seconds
Started Apr 23 01:25:03 PM PDT 24
Finished Apr 23 01:25:53 PM PDT 24
Peak memory 568672 kb
Host smart-b5def463-aadc-4ccd-bf1c-fc9dd441e19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611190859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.611190859
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.2076020145
Short name T726
Test name
Test status
Simulation time 298854470 ps
CPU time 0.9 seconds
Started Apr 23 01:25:03 PM PDT 24
Finished Apr 23 01:25:06 PM PDT 24
Peak memory 203368 kb
Host smart-e69821fc-633e-4693-ac47-6bcb5475c2ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076020145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.2076020145
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.2499735266
Short name T1005
Test name
Test status
Simulation time 347386911 ps
CPU time 4.94 seconds
Started Apr 23 01:25:04 PM PDT 24
Finished Apr 23 01:25:10 PM PDT 24
Peak memory 234008 kb
Host smart-07d1528f-a773-4b56-8f33-83c1103f59e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499735266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.2499735266
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.3447313455
Short name T43
Test name
Test status
Simulation time 2556978965 ps
CPU time 58.9 seconds
Started Apr 23 01:24:59 PM PDT 24
Finished Apr 23 01:25:59 PM PDT 24
Peak memory 804260 kb
Host smart-a90abf1a-e796-4773-9286-ebc13a9c0991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447313455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.3447313455
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.3350491541
Short name T763
Test name
Test status
Simulation time 1586080872 ps
CPU time 82.28 seconds
Started Apr 23 01:25:10 PM PDT 24
Finished Apr 23 01:26:32 PM PDT 24
Peak memory 368616 kb
Host smart-403bb8c3-537f-41be-879d-4fbc6ac9fbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350491541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.3350491541
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.2948941011
Short name T191
Test name
Test status
Simulation time 43150165 ps
CPU time 0.67 seconds
Started Apr 23 01:25:01 PM PDT 24
Finished Apr 23 01:25:02 PM PDT 24
Peak memory 203408 kb
Host smart-b4ce68c5-0f93-4045-9f28-40e5e1800066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948941011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.2948941011
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.4007056327
Short name T542
Test name
Test status
Simulation time 5312715073 ps
CPU time 66.26 seconds
Started Apr 23 01:25:04 PM PDT 24
Finished Apr 23 01:26:11 PM PDT 24
Peak memory 220576 kb
Host smart-d731dada-16eb-467b-81b5-832f1898539a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007056327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.4007056327
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.684167714
Short name T767
Test name
Test status
Simulation time 2239200103 ps
CPU time 49.22 seconds
Started Apr 23 01:25:01 PM PDT 24
Finished Apr 23 01:25:51 PM PDT 24
Peak memory 282232 kb
Host smart-55d03c85-53c8-4a45-952d-11a61d62d960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684167714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.684167714
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.1350775295
Short name T49
Test name
Test status
Simulation time 28435433130 ps
CPU time 567.41 seconds
Started Apr 23 01:25:03 PM PDT 24
Finished Apr 23 01:34:31 PM PDT 24
Peak memory 1026628 kb
Host smart-96d21282-c88e-4a3c-816b-43412bd142f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350775295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.1350775295
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.3838854703
Short name T928
Test name
Test status
Simulation time 824902859 ps
CPU time 36.64 seconds
Started Apr 23 01:25:04 PM PDT 24
Finished Apr 23 01:25:42 PM PDT 24
Peak memory 211928 kb
Host smart-942eae06-7bb7-4f50-97d1-f7606b0e87d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838854703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3838854703
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.1381449350
Short name T1299
Test name
Test status
Simulation time 7965266805 ps
CPU time 4.35 seconds
Started Apr 23 01:25:11 PM PDT 24
Finished Apr 23 01:25:16 PM PDT 24
Peak memory 211948 kb
Host smart-2241edfe-c6c9-4283-912a-b8a503a8f198
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381449350 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.1381449350
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.1590319216
Short name T1058
Test name
Test status
Simulation time 10084748477 ps
CPU time 28.15 seconds
Started Apr 23 01:25:08 PM PDT 24
Finished Apr 23 01:25:37 PM PDT 24
Peak memory 341892 kb
Host smart-ebde2a8f-d40a-4328-8db9-fa9f8d3f1c92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590319216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.1590319216
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.2284378558
Short name T109
Test name
Test status
Simulation time 10258199812 ps
CPU time 7.51 seconds
Started Apr 23 01:25:08 PM PDT 24
Finished Apr 23 01:25:16 PM PDT 24
Peak memory 255768 kb
Host smart-55da4b2e-4f14-43dd-a7bd-68ebe2f37ed1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284378558 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.2284378558
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.3712684975
Short name T219
Test name
Test status
Simulation time 1594781950 ps
CPU time 2.54 seconds
Started Apr 23 01:25:09 PM PDT 24
Finished Apr 23 01:25:13 PM PDT 24
Peak memory 203816 kb
Host smart-21d485f8-592a-4911-8262-c3a927d74530
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712684975 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.3712684975
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.416845913
Short name T487
Test name
Test status
Simulation time 2355225474 ps
CPU time 4.02 seconds
Started Apr 23 01:25:03 PM PDT 24
Finished Apr 23 01:25:08 PM PDT 24
Peak memory 203820 kb
Host smart-24098347-702b-4963-9635-263320a4c9e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416845913 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_intr_smoke.416845913
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.792779797
Short name T23
Test name
Test status
Simulation time 11127209853 ps
CPU time 23.32 seconds
Started Apr 23 01:25:08 PM PDT 24
Finished Apr 23 01:25:33 PM PDT 24
Peak memory 531096 kb
Host smart-dc248bf4-8b6b-4a76-9edb-9e2058cc2d30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792779797 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.792779797
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.1542885235
Short name T510
Test name
Test status
Simulation time 2673915716 ps
CPU time 26.38 seconds
Started Apr 23 01:25:03 PM PDT 24
Finished Apr 23 01:25:30 PM PDT 24
Peak memory 203676 kb
Host smart-8b97fd6e-309f-4c0a-8ff5-5ae0e2c4f960
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542885235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.1542885235
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.249885997
Short name T247
Test name
Test status
Simulation time 1235802226 ps
CPU time 52.17 seconds
Started Apr 23 01:25:04 PM PDT 24
Finished Apr 23 01:25:57 PM PDT 24
Peak memory 203712 kb
Host smart-6f1dee22-ac52-4d0a-bfcb-6451b1baa558
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249885997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_rd.249885997
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.712218450
Short name T968
Test name
Test status
Simulation time 22864061641 ps
CPU time 4.04 seconds
Started Apr 23 01:25:03 PM PDT 24
Finished Apr 23 01:25:08 PM PDT 24
Peak memory 203848 kb
Host smart-51f0bf84-342e-411a-bffa-3f986f64f0ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712218450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_wr.712218450
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.1702839979
Short name T382
Test name
Test status
Simulation time 20411737112 ps
CPU time 1302.06 seconds
Started Apr 23 01:25:05 PM PDT 24
Finished Apr 23 01:46:48 PM PDT 24
Peak memory 2582616 kb
Host smart-1ef268c3-2a5c-49e7-91a4-6d0c037356a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702839979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.1702839979
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.535154583
Short name T600
Test name
Test status
Simulation time 1069624821 ps
CPU time 6.86 seconds
Started Apr 23 01:25:07 PM PDT 24
Finished Apr 23 01:25:14 PM PDT 24
Peak memory 218804 kb
Host smart-089c54af-7228-43d1-afd8-78ac0c58e2d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535154583 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_timeout.535154583
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.2180476318
Short name T816
Test name
Test status
Simulation time 27304300 ps
CPU time 0.61 seconds
Started Apr 23 01:25:15 PM PDT 24
Finished Apr 23 01:25:16 PM PDT 24
Peak memory 203284 kb
Host smart-f5796214-c5d1-4ee1-bef8-a8594790025a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180476318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.2180476318
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.274139022
Short name T1201
Test name
Test status
Simulation time 85622399 ps
CPU time 1.2 seconds
Started Apr 23 01:25:11 PM PDT 24
Finished Apr 23 01:25:13 PM PDT 24
Peak memory 220160 kb
Host smart-993500e7-c73e-463d-9037-b7233b2f9e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274139022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.274139022
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.3616320844
Short name T84
Test name
Test status
Simulation time 1426732355 ps
CPU time 17.59 seconds
Started Apr 23 01:25:11 PM PDT 24
Finished Apr 23 01:25:29 PM PDT 24
Peak memory 264480 kb
Host smart-75b52cb7-a12b-4de1-8b39-340e56fcce35
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616320844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.3616320844
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.3159142954
Short name T44
Test name
Test status
Simulation time 13901685306 ps
CPU time 61.76 seconds
Started Apr 23 01:25:13 PM PDT 24
Finished Apr 23 01:26:15 PM PDT 24
Peak memory 597544 kb
Host smart-5ed0c67d-d976-4a43-a478-cdc747ccd99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159142954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.3159142954
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.9728303
Short name T371
Test name
Test status
Simulation time 5365759085 ps
CPU time 46.48 seconds
Started Apr 23 01:25:12 PM PDT 24
Finished Apr 23 01:25:59 PM PDT 24
Peak memory 538672 kb
Host smart-4be83fce-b8a6-4729-9ee0-f58c7aa2acd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9728303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.9728303
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.2269590317
Short name T206
Test name
Test status
Simulation time 135973676 ps
CPU time 1.09 seconds
Started Apr 23 01:25:11 PM PDT 24
Finished Apr 23 01:25:13 PM PDT 24
Peak memory 203392 kb
Host smart-7bbbb86f-8a2e-44ec-bdc0-8d00beeabf4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269590317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.2269590317
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.1840223898
Short name T1207
Test name
Test status
Simulation time 116804166 ps
CPU time 2.77 seconds
Started Apr 23 01:25:11 PM PDT 24
Finished Apr 23 01:25:15 PM PDT 24
Peak memory 203724 kb
Host smart-0c85d6a8-9971-46a8-be00-a75e7c888783
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840223898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.1840223898
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.3609461498
Short name T489
Test name
Test status
Simulation time 30198512241 ps
CPU time 163.39 seconds
Started Apr 23 01:25:15 PM PDT 24
Finished Apr 23 01:27:59 PM PDT 24
Peak memory 1304088 kb
Host smart-82e3f19a-ca7c-41eb-a755-a7de3713be05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609461498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3609461498
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.2177024043
Short name T209
Test name
Test status
Simulation time 1937523579 ps
CPU time 17.45 seconds
Started Apr 23 01:25:13 PM PDT 24
Finished Apr 23 01:25:31 PM PDT 24
Peak memory 203648 kb
Host smart-ae46eb31-185c-4dec-9d2f-71d39624ede6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177024043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.2177024043
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.706560101
Short name T500
Test name
Test status
Simulation time 6384534294 ps
CPU time 28.76 seconds
Started Apr 23 01:25:15 PM PDT 24
Finished Apr 23 01:25:44 PM PDT 24
Peak memory 288428 kb
Host smart-e9d89e38-ae86-4bb9-ba0e-62a51baa7831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706560101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.706560101
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.898102658
Short name T1272
Test name
Test status
Simulation time 29428984 ps
CPU time 0.67 seconds
Started Apr 23 01:25:12 PM PDT 24
Finished Apr 23 01:25:13 PM PDT 24
Peak memory 203360 kb
Host smart-3fa3d349-b72e-4dd6-90c1-5a0c6faea158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898102658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.898102658
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.2766366661
Short name T1199
Test name
Test status
Simulation time 8800128359 ps
CPU time 383.08 seconds
Started Apr 23 01:25:12 PM PDT 24
Finished Apr 23 01:31:36 PM PDT 24
Peak memory 1094828 kb
Host smart-a0803ead-5362-4a7c-89c0-b6cbc9db76fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766366661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.2766366661
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.288572684
Short name T495
Test name
Test status
Simulation time 1149803016 ps
CPU time 53.29 seconds
Started Apr 23 01:25:15 PM PDT 24
Finished Apr 23 01:26:09 PM PDT 24
Peak memory 268780 kb
Host smart-ac1758ce-c512-4f7d-935d-86baa3ff560e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288572684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.288572684
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.2870402197
Short name T181
Test name
Test status
Simulation time 49330197343 ps
CPU time 495.43 seconds
Started Apr 23 01:25:13 PM PDT 24
Finished Apr 23 01:33:29 PM PDT 24
Peak memory 1948072 kb
Host smart-751ec3bb-d036-4b12-859a-16e4c207e987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870402197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.2870402197
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.3003970410
Short name T1152
Test name
Test status
Simulation time 1366364681 ps
CPU time 6.21 seconds
Started Apr 23 01:25:13 PM PDT 24
Finished Apr 23 01:25:20 PM PDT 24
Peak memory 211968 kb
Host smart-22ebe75f-cb3e-4552-9235-b61218ba9873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003970410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.3003970410
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.1158251195
Short name T355
Test name
Test status
Simulation time 1458560522 ps
CPU time 3.82 seconds
Started Apr 23 01:25:13 PM PDT 24
Finished Apr 23 01:25:18 PM PDT 24
Peak memory 203780 kb
Host smart-bceffb56-6b3d-452c-8dfc-2868f379e9c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158251195 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.1158251195
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.3122373784
Short name T243
Test name
Test status
Simulation time 10095334172 ps
CPU time 62.65 seconds
Started Apr 23 01:25:11 PM PDT 24
Finished Apr 23 01:26:14 PM PDT 24
Peak memory 466820 kb
Host smart-a85ebc67-c6a2-45df-9b14-38f5ff30280d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122373784 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.3122373784
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.4116423464
Short name T931
Test name
Test status
Simulation time 878666064 ps
CPU time 2.4 seconds
Started Apr 23 01:25:16 PM PDT 24
Finished Apr 23 01:25:19 PM PDT 24
Peak memory 203740 kb
Host smart-68078b3b-dc95-4895-a929-9f10cca30a25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116423464 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.4116423464
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.111279925
Short name T674
Test name
Test status
Simulation time 1684766134 ps
CPU time 4.14 seconds
Started Apr 23 01:25:15 PM PDT 24
Finished Apr 23 01:25:19 PM PDT 24
Peak memory 203768 kb
Host smart-86e2eb1d-7a4b-4075-ba3c-169ee081550c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111279925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_intr_smoke.111279925
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.3373414109
Short name T773
Test name
Test status
Simulation time 17832427993 ps
CPU time 5.32 seconds
Started Apr 23 01:25:13 PM PDT 24
Finished Apr 23 01:25:19 PM PDT 24
Peak memory 203800 kb
Host smart-7b0caa64-7699-49ea-90bd-8fd0010dba90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373414109 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.3373414109
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.4067485243
Short name T1300
Test name
Test status
Simulation time 3241880873 ps
CPU time 29.27 seconds
Started Apr 23 01:25:14 PM PDT 24
Finished Apr 23 01:25:44 PM PDT 24
Peak memory 203832 kb
Host smart-2062c2d9-b77c-4bc3-acb4-742327075df8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067485243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.4067485243
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.2487684496
Short name T427
Test name
Test status
Simulation time 1327737984 ps
CPU time 11.96 seconds
Started Apr 23 01:25:13 PM PDT 24
Finished Apr 23 01:25:26 PM PDT 24
Peak memory 203684 kb
Host smart-a8b5a8ae-409d-44a2-8ec8-4b8181ccbbb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487684496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.2487684496
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.637022639
Short name T677
Test name
Test status
Simulation time 10212314405 ps
CPU time 6.57 seconds
Started Apr 23 01:25:12 PM PDT 24
Finished Apr 23 01:25:19 PM PDT 24
Peak memory 203824 kb
Host smart-3d22fc0b-edd9-447f-a9e2-08e0337c8099
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637022639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_wr.637022639
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.1763980003
Short name T35
Test name
Test status
Simulation time 28983342900 ps
CPU time 3564.6 seconds
Started Apr 23 01:25:13 PM PDT 24
Finished Apr 23 02:24:39 PM PDT 24
Peak memory 5128156 kb
Host smart-77077a24-f73f-4247-b003-6bfddab12564
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763980003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.1763980003
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.3975648308
Short name T1276
Test name
Test status
Simulation time 1523742088 ps
CPU time 6.81 seconds
Started Apr 23 01:25:15 PM PDT 24
Finished Apr 23 01:25:22 PM PDT 24
Peak memory 212248 kb
Host smart-7ed630ab-7722-488c-a88f-f9febd3b3036
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975648308 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.3975648308
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.3258666699
Short name T117
Test name
Test status
Simulation time 69271835 ps
CPU time 0.65 seconds
Started Apr 23 01:25:26 PM PDT 24
Finished Apr 23 01:25:27 PM PDT 24
Peak memory 203380 kb
Host smart-6fd59a4f-d55a-4272-ac54-d8e616eafc05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258666699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.3258666699
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.95035605
Short name T697
Test name
Test status
Simulation time 105372022 ps
CPU time 1.34 seconds
Started Apr 23 01:25:17 PM PDT 24
Finished Apr 23 01:25:19 PM PDT 24
Peak memory 212104 kb
Host smart-09d4398d-c3c8-4eb8-b0c9-82b2432aa790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95035605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.95035605
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.1826005741
Short name T1003
Test name
Test status
Simulation time 1025913378 ps
CPU time 3.46 seconds
Started Apr 23 01:25:18 PM PDT 24
Finished Apr 23 01:25:22 PM PDT 24
Peak memory 233308 kb
Host smart-5a6c8e6c-b72f-4a45-9b8a-c13b0b87dad8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826005741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.1826005741
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2828266150
Short name T522
Test name
Test status
Simulation time 1809192685 ps
CPU time 134.05 seconds
Started Apr 23 01:25:19 PM PDT 24
Finished Apr 23 01:27:34 PM PDT 24
Peak memory 652976 kb
Host smart-cb6ac40f-83f2-4341-ac9c-2c6b7e1eac39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828266150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2828266150
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.2357976362
Short name T519
Test name
Test status
Simulation time 5230086531 ps
CPU time 75.37 seconds
Started Apr 23 01:25:17 PM PDT 24
Finished Apr 23 01:26:33 PM PDT 24
Peak memory 695488 kb
Host smart-e8691858-d624-41f3-ab86-ffea872748de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357976362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.2357976362
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.347007885
Short name T105
Test name
Test status
Simulation time 524561114 ps
CPU time 1.08 seconds
Started Apr 23 01:25:19 PM PDT 24
Finished Apr 23 01:25:20 PM PDT 24
Peak memory 203696 kb
Host smart-1f26e905-686d-4d19-889c-a2fb776c2e9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347007885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fm
t.347007885
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.2909697221
Short name T902
Test name
Test status
Simulation time 160675491 ps
CPU time 8.04 seconds
Started Apr 23 01:25:17 PM PDT 24
Finished Apr 23 01:25:26 PM PDT 24
Peak memory 203548 kb
Host smart-46a6d78e-6f93-4a21-83f5-353c9ac7400f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909697221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.2909697221
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.3842530893
Short name T1175
Test name
Test status
Simulation time 17433994874 ps
CPU time 117.32 seconds
Started Apr 23 01:25:18 PM PDT 24
Finished Apr 23 01:27:16 PM PDT 24
Peak memory 1225724 kb
Host smart-dfab699b-b9e8-45f6-8511-b6ff3eb7619d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842530893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.3842530893
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.2695305735
Short name T1149
Test name
Test status
Simulation time 508108391 ps
CPU time 20.63 seconds
Started Apr 23 01:25:21 PM PDT 24
Finished Apr 23 01:25:43 PM PDT 24
Peak memory 203684 kb
Host smart-6faf20ef-8403-42bd-9cab-4cc6c2bd465b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695305735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.2695305735
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.2248995635
Short name T987
Test name
Test status
Simulation time 25322034449 ps
CPU time 32.42 seconds
Started Apr 23 01:25:22 PM PDT 24
Finished Apr 23 01:25:55 PM PDT 24
Peak memory 380020 kb
Host smart-9fa6969d-8946-4529-add8-7229b405836b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248995635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.2248995635
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.2951066308
Short name T1114
Test name
Test status
Simulation time 16463300 ps
CPU time 0.66 seconds
Started Apr 23 01:25:14 PM PDT 24
Finished Apr 23 01:25:15 PM PDT 24
Peak memory 203424 kb
Host smart-ccd73930-e0bd-4619-b610-44c04fd152cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951066308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.2951066308
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.2661555798
Short name T772
Test name
Test status
Simulation time 5314875222 ps
CPU time 293.87 seconds
Started Apr 23 01:25:16 PM PDT 24
Finished Apr 23 01:30:11 PM PDT 24
Peak memory 857184 kb
Host smart-5ee05907-dd88-4b95-b7ce-9968958b1955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661555798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2661555798
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.3998725717
Short name T587
Test name
Test status
Simulation time 3605475389 ps
CPU time 45 seconds
Started Apr 23 01:25:15 PM PDT 24
Finished Apr 23 01:26:01 PM PDT 24
Peak memory 308552 kb
Host smart-7b1fdbc1-edcc-4a17-ad6b-e4e203cce626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998725717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.3998725717
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.3145758864
Short name T1308
Test name
Test status
Simulation time 21331479781 ps
CPU time 192.13 seconds
Started Apr 23 01:25:19 PM PDT 24
Finished Apr 23 01:28:32 PM PDT 24
Peak memory 1212332 kb
Host smart-bf5dc7d3-1adf-4681-a440-791908629aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145758864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.3145758864
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.3363705641
Short name T890
Test name
Test status
Simulation time 647010653 ps
CPU time 9.85 seconds
Started Apr 23 01:25:18 PM PDT 24
Finished Apr 23 01:25:29 PM PDT 24
Peak memory 228312 kb
Host smart-406d6e71-7907-4226-b177-68b6d29b6b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363705641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3363705641
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.2136868877
Short name T283
Test name
Test status
Simulation time 1147475096 ps
CPU time 5.28 seconds
Started Apr 23 01:25:23 PM PDT 24
Finished Apr 23 01:25:29 PM PDT 24
Peak memory 212820 kb
Host smart-c1eed024-8563-4dd2-a43f-ca94fad6b631
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136868877 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.2136868877
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.3986985767
Short name T36
Test name
Test status
Simulation time 10403465551 ps
CPU time 12.34 seconds
Started Apr 23 01:25:24 PM PDT 24
Finished Apr 23 01:25:37 PM PDT 24
Peak memory 282896 kb
Host smart-75899f26-e41a-48aa-a43e-2e39f8d3a45b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986985767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.3986985767
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.988478009
Short name T946
Test name
Test status
Simulation time 10092271556 ps
CPU time 82.08 seconds
Started Apr 23 01:25:23 PM PDT 24
Finished Apr 23 01:26:45 PM PDT 24
Peak memory 505512 kb
Host smart-4e1aef6c-e2cc-4489-9cf6-d5db2dc8bba9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988478009 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_fifo_reset_tx.988478009
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.4045622743
Short name T482
Test name
Test status
Simulation time 292856644 ps
CPU time 1.86 seconds
Started Apr 23 01:25:23 PM PDT 24
Finished Apr 23 01:25:25 PM PDT 24
Peak memory 203712 kb
Host smart-e11d82ad-e417-410a-86a7-8b3a848ab961
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045622743 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.4045622743
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.1595351364
Short name T1068
Test name
Test status
Simulation time 3123421006 ps
CPU time 4 seconds
Started Apr 23 01:25:23 PM PDT 24
Finished Apr 23 01:25:27 PM PDT 24
Peak memory 203740 kb
Host smart-2c75bbb4-1112-4af9-94d3-4bfa3dec7437
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595351364 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.1595351364
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.73788431
Short name T889
Test name
Test status
Simulation time 16854622506 ps
CPU time 90.65 seconds
Started Apr 23 01:25:22 PM PDT 24
Finished Apr 23 01:26:54 PM PDT 24
Peak memory 1301960 kb
Host smart-ed18d47a-dcce-4489-878b-721267840a41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73788431 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.73788431
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.4045181721
Short name T837
Test name
Test status
Simulation time 3328207496 ps
CPU time 23.45 seconds
Started Apr 23 01:25:17 PM PDT 24
Finished Apr 23 01:25:41 PM PDT 24
Peak memory 203720 kb
Host smart-86c3e910-521f-44d2-b097-8e7062f03734
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045181721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.4045181721
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.1763965164
Short name T1030
Test name
Test status
Simulation time 22590901307 ps
CPU time 21.74 seconds
Started Apr 23 01:25:19 PM PDT 24
Finished Apr 23 01:25:41 PM PDT 24
Peak memory 230536 kb
Host smart-c80a5d3a-3dc3-46fe-bd4b-1de9de9673be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763965164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.1763965164
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.1625794052
Short name T1215
Test name
Test status
Simulation time 10793515930 ps
CPU time 2.84 seconds
Started Apr 23 01:25:19 PM PDT 24
Finished Apr 23 01:25:22 PM PDT 24
Peak memory 203740 kb
Host smart-431de9f0-a1e0-4b2a-8817-a5908afed863
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625794052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.1625794052
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.4199453908
Short name T277
Test name
Test status
Simulation time 17190388895 ps
CPU time 71.75 seconds
Started Apr 23 01:25:24 PM PDT 24
Finished Apr 23 01:26:36 PM PDT 24
Peak memory 767604 kb
Host smart-c27e580b-5a4a-40e1-bd5d-9d1e8b954988
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199453908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.4199453908
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.3254440793
Short name T719
Test name
Test status
Simulation time 1709285966 ps
CPU time 6.52 seconds
Started Apr 23 01:25:23 PM PDT 24
Finished Apr 23 01:25:30 PM PDT 24
Peak memory 210384 kb
Host smart-f9edcf35-70bb-42bd-a7ab-b339ac5aedd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254440793 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.3254440793
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_unexp_stop.932759743
Short name T21
Test name
Test status
Simulation time 1368561778 ps
CPU time 6.58 seconds
Started Apr 23 01:25:21 PM PDT 24
Finished Apr 23 01:25:28 PM PDT 24
Peak memory 211840 kb
Host smart-5480ce5d-531e-48d4-a6e6-a8c12789ae0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932759743 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_unexp_stop.932759743
Directory /workspace/26.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3668050035
Short name T1112
Test name
Test status
Simulation time 115147691 ps
CPU time 0.64 seconds
Started Apr 23 01:25:38 PM PDT 24
Finished Apr 23 01:25:40 PM PDT 24
Peak memory 203316 kb
Host smart-8b18c7f7-bd1b-4604-9b2c-b328192e6c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668050035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3668050035
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.1073823588
Short name T456
Test name
Test status
Simulation time 161105411 ps
CPU time 1.6 seconds
Started Apr 23 01:25:28 PM PDT 24
Finished Apr 23 01:25:30 PM PDT 24
Peak memory 220140 kb
Host smart-b1e3ceaf-984f-4c08-89d1-eec3bf1e017b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073823588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.1073823588
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.2514195383
Short name T672
Test name
Test status
Simulation time 287674956 ps
CPU time 6.41 seconds
Started Apr 23 01:25:28 PM PDT 24
Finished Apr 23 01:25:35 PM PDT 24
Peak memory 259732 kb
Host smart-232ca71b-42ca-4e31-ab0c-5e86b884a539
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514195383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.2514195383
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.2291864757
Short name T770
Test name
Test status
Simulation time 8089316673 ps
CPU time 50.66 seconds
Started Apr 23 01:25:31 PM PDT 24
Finished Apr 23 01:26:22 PM PDT 24
Peak memory 468260 kb
Host smart-f54ff465-c5d8-42bb-b37d-d9a1e08a93ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291864757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.2291864757
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.1592238568
Short name T967
Test name
Test status
Simulation time 9142573291 ps
CPU time 136.08 seconds
Started Apr 23 01:25:25 PM PDT 24
Finished Apr 23 01:27:42 PM PDT 24
Peak memory 660256 kb
Host smart-8689b90d-dc5a-4bd0-b8f9-4d655a3da466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592238568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.1592238568
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.3549347515
Short name T783
Test name
Test status
Simulation time 197259567 ps
CPU time 1.05 seconds
Started Apr 23 01:25:25 PM PDT 24
Finished Apr 23 01:25:26 PM PDT 24
Peak memory 203620 kb
Host smart-73cd7498-c629-4189-bab6-9a6dac746888
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549347515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.3549347515
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.325266851
Short name T299
Test name
Test status
Simulation time 171884023 ps
CPU time 4.06 seconds
Started Apr 23 01:25:28 PM PDT 24
Finished Apr 23 01:25:32 PM PDT 24
Peak memory 203676 kb
Host smart-b24e9c89-7da8-4eb8-9591-b5ad1d256dd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325266851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.
325266851
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3361807648
Short name T637
Test name
Test status
Simulation time 3637226624 ps
CPU time 261.62 seconds
Started Apr 23 01:25:25 PM PDT 24
Finished Apr 23 01:29:47 PM PDT 24
Peak memory 1034348 kb
Host smart-98690d97-a1c5-4c27-bc58-2b6fe0d600a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361807648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3361807648
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.166582149
Short name T607
Test name
Test status
Simulation time 599065766 ps
CPU time 8.06 seconds
Started Apr 23 01:25:38 PM PDT 24
Finished Apr 23 01:25:46 PM PDT 24
Peak memory 203616 kb
Host smart-de688161-5f6d-4403-9abd-cd589e2ea8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166582149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.166582149
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.2641616771
Short name T40
Test name
Test status
Simulation time 3100187158 ps
CPU time 35.41 seconds
Started Apr 23 01:25:36 PM PDT 24
Finished Apr 23 01:26:12 PM PDT 24
Peak memory 423760 kb
Host smart-51e6e9b5-5bc4-49c7-b91a-08d2da76df88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641616771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.2641616771
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.1258030416
Short name T394
Test name
Test status
Simulation time 19836323 ps
CPU time 0.62 seconds
Started Apr 23 01:25:26 PM PDT 24
Finished Apr 23 01:25:27 PM PDT 24
Peak memory 203280 kb
Host smart-60570dc0-219d-45e4-b52d-1e027d8c6f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258030416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.1258030416
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.3786680969
Short name T1050
Test name
Test status
Simulation time 53479830210 ps
CPU time 2450.47 seconds
Started Apr 23 01:25:28 PM PDT 24
Finished Apr 23 02:06:19 PM PDT 24
Peak memory 912392 kb
Host smart-efcd0d5a-7d8f-42f3-9eff-17ecf02cfd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786680969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.3786680969
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.2248929380
Short name T289
Test name
Test status
Simulation time 3432303307 ps
CPU time 16.43 seconds
Started Apr 23 01:25:25 PM PDT 24
Finished Apr 23 01:25:41 PM PDT 24
Peak memory 349924 kb
Host smart-80351954-26da-43ed-b94b-9384dfdfd598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248929380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.2248929380
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.1466443482
Short name T176
Test name
Test status
Simulation time 18746570741 ps
CPU time 52 seconds
Started Apr 23 01:25:31 PM PDT 24
Finished Apr 23 01:26:23 PM PDT 24
Peak memory 431036 kb
Host smart-452c21de-3879-46f7-a79a-61b93016d9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466443482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.1466443482
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3161686978
Short name T680
Test name
Test status
Simulation time 561869907 ps
CPU time 10.52 seconds
Started Apr 23 01:25:30 PM PDT 24
Finished Apr 23 01:25:41 PM PDT 24
Peak memory 212092 kb
Host smart-4994dedd-78d4-47cb-a216-a686b82b7e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161686978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3161686978
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.682355190
Short name T975
Test name
Test status
Simulation time 5395825131 ps
CPU time 3.97 seconds
Started Apr 23 01:25:37 PM PDT 24
Finished Apr 23 01:25:42 PM PDT 24
Peak memory 211976 kb
Host smart-2ca08626-1af4-4068-b98c-fa2b6a6d930f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682355190 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.682355190
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.1942650186
Short name T55
Test name
Test status
Simulation time 10042413986 ps
CPU time 30.56 seconds
Started Apr 23 01:25:33 PM PDT 24
Finished Apr 23 01:26:04 PM PDT 24
Peak memory 321084 kb
Host smart-e71a6cc1-c90a-46ce-8f95-0b2cdaee973b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942650186 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.1942650186
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.2885877162
Short name T567
Test name
Test status
Simulation time 10145827808 ps
CPU time 13.68 seconds
Started Apr 23 01:25:34 PM PDT 24
Finished Apr 23 01:25:48 PM PDT 24
Peak memory 270568 kb
Host smart-ccaf3653-c973-48f0-bc94-076ec0131b9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885877162 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.2885877162
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.1287530155
Short name T16
Test name
Test status
Simulation time 432209806 ps
CPU time 2.67 seconds
Started Apr 23 01:25:39 PM PDT 24
Finished Apr 23 01:25:42 PM PDT 24
Peak memory 203716 kb
Host smart-27bcfb28-0fa4-4ad7-9854-33f1e7c1ee66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287530155 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.1287530155
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.3992987879
Short name T979
Test name
Test status
Simulation time 2196743641 ps
CPU time 5.37 seconds
Started Apr 23 01:25:35 PM PDT 24
Finished Apr 23 01:25:40 PM PDT 24
Peak memory 205072 kb
Host smart-d67d7edf-e682-41ff-9f47-c6286874760a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992987879 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.3992987879
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.1741640956
Short name T333
Test name
Test status
Simulation time 6183807762 ps
CPU time 13.23 seconds
Started Apr 23 01:25:33 PM PDT 24
Finished Apr 23 01:25:47 PM PDT 24
Peak memory 203776 kb
Host smart-d8741407-f1fd-4e1a-abce-9a81bb503878
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741640956 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.1741640956
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.2363291402
Short name T1023
Test name
Test status
Simulation time 858604362 ps
CPU time 27.44 seconds
Started Apr 23 01:25:30 PM PDT 24
Finished Apr 23 01:25:58 PM PDT 24
Peak memory 203760 kb
Host smart-405156a9-a6b3-4b46-8e4f-006d212ff2a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363291402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.2363291402
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.4209228461
Short name T664
Test name
Test status
Simulation time 5104610466 ps
CPU time 55.56 seconds
Started Apr 23 01:25:29 PM PDT 24
Finished Apr 23 01:26:25 PM PDT 24
Peak memory 203832 kb
Host smart-1954d255-a600-4330-8fc2-e5a3b2767aaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209228461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.4209228461
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.2501435872
Short name T1219
Test name
Test status
Simulation time 32859443478 ps
CPU time 44.18 seconds
Started Apr 23 01:25:28 PM PDT 24
Finished Apr 23 01:26:13 PM PDT 24
Peak memory 866820 kb
Host smart-f9cd5abc-4d47-4e31-8fd4-35ec51bb89ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501435872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.2501435872
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.3151351194
Short name T615
Test name
Test status
Simulation time 21954481413 ps
CPU time 51.19 seconds
Started Apr 23 01:25:35 PM PDT 24
Finished Apr 23 01:26:27 PM PDT 24
Peak memory 694608 kb
Host smart-fbff1785-d899-4825-b5f1-e71a153d9457
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151351194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.3151351194
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3171121598
Short name T557
Test name
Test status
Simulation time 7278818044 ps
CPU time 7.13 seconds
Started Apr 23 01:25:33 PM PDT 24
Finished Apr 23 01:25:40 PM PDT 24
Peak memory 219924 kb
Host smart-48c331e2-52c9-4b6e-be45-fb0099f92dfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171121598 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3171121598
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.3349861564
Short name T1089
Test name
Test status
Simulation time 42514463 ps
CPU time 0.69 seconds
Started Apr 23 01:25:50 PM PDT 24
Finished Apr 23 01:25:51 PM PDT 24
Peak memory 203356 kb
Host smart-12ae9d04-3d0a-485f-82f1-e0bfcd9086bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349861564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.3349861564
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.2940834013
Short name T796
Test name
Test status
Simulation time 133751604 ps
CPU time 1.47 seconds
Started Apr 23 01:25:40 PM PDT 24
Finished Apr 23 01:25:42 PM PDT 24
Peak memory 212000 kb
Host smart-1fcf14d7-54b8-4df2-adfa-255c35918a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940834013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.2940834013
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2208577065
Short name T1121
Test name
Test status
Simulation time 842765153 ps
CPU time 11.47 seconds
Started Apr 23 01:25:36 PM PDT 24
Finished Apr 23 01:25:48 PM PDT 24
Peak memory 243040 kb
Host smart-2fa03108-64b6-486d-b739-33cacc3708ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208577065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2208577065
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.4067514530
Short name T819
Test name
Test status
Simulation time 1445211721 ps
CPU time 73.52 seconds
Started Apr 23 01:25:37 PM PDT 24
Finished Apr 23 01:26:51 PM PDT 24
Peak memory 211820 kb
Host smart-47a5b884-1975-4cca-a9ba-0ff45af81759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067514530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.4067514530
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.4206380010
Short name T1284
Test name
Test status
Simulation time 2148442892 ps
CPU time 59.18 seconds
Started Apr 23 01:25:37 PM PDT 24
Finished Apr 23 01:26:37 PM PDT 24
Peak memory 663736 kb
Host smart-2859b88d-cdf7-4496-b120-25d404c9bed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206380010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.4206380010
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.1388619562
Short name T688
Test name
Test status
Simulation time 138341764 ps
CPU time 0.95 seconds
Started Apr 23 01:25:38 PM PDT 24
Finished Apr 23 01:25:40 PM PDT 24
Peak memory 203396 kb
Host smart-a1e12c9c-d1dd-4f06-bf18-588899aceef0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388619562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.1388619562
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.3172519903
Short name T879
Test name
Test status
Simulation time 184757158 ps
CPU time 4.45 seconds
Started Apr 23 01:25:37 PM PDT 24
Finished Apr 23 01:25:42 PM PDT 24
Peak memory 203588 kb
Host smart-0e300e6d-ad0c-4c50-ba84-22ef8a9b8983
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172519903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.3172519903
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.2161754904
Short name T492
Test name
Test status
Simulation time 11978088967 ps
CPU time 89.79 seconds
Started Apr 23 01:25:37 PM PDT 24
Finished Apr 23 01:27:07 PM PDT 24
Peak memory 947840 kb
Host smart-44ed8fb7-4cd9-47b7-90b0-562ec5a86d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161754904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.2161754904
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.3352913539
Short name T1077
Test name
Test status
Simulation time 477802272 ps
CPU time 7.98 seconds
Started Apr 23 01:25:44 PM PDT 24
Finished Apr 23 01:25:52 PM PDT 24
Peak memory 203640 kb
Host smart-d859c0df-e299-440d-a688-d07c56770518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352913539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.3352913539
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.1646636378
Short name T1163
Test name
Test status
Simulation time 1706842449 ps
CPU time 83.53 seconds
Started Apr 23 01:25:44 PM PDT 24
Finished Apr 23 01:27:08 PM PDT 24
Peak memory 377064 kb
Host smart-f3278b81-f51a-4221-b5b2-8eca04277e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646636378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.1646636378
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.1843256061
Short name T185
Test name
Test status
Simulation time 51300054 ps
CPU time 0.7 seconds
Started Apr 23 01:25:38 PM PDT 24
Finished Apr 23 01:25:39 PM PDT 24
Peak memory 203340 kb
Host smart-f933bc3c-c529-4d23-9f6d-efdc1e3c09c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843256061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1843256061
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.2894769861
Short name T1340
Test name
Test status
Simulation time 4684998742 ps
CPU time 356.23 seconds
Started Apr 23 01:25:38 PM PDT 24
Finished Apr 23 01:31:35 PM PDT 24
Peak memory 917476 kb
Host smart-4adbe35a-6358-4a19-8bb6-ac70c4f6c147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894769861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.2894769861
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.1201917600
Short name T194
Test name
Test status
Simulation time 60862894332 ps
CPU time 3476.79 seconds
Started Apr 23 01:25:40 PM PDT 24
Finished Apr 23 02:23:38 PM PDT 24
Peak memory 6310652 kb
Host smart-3ed0052d-2cc4-4d18-9d7f-0da0ab8431a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201917600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.1201917600
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.3429070215
Short name T1327
Test name
Test status
Simulation time 1571699540 ps
CPU time 35.93 seconds
Started Apr 23 01:25:37 PM PDT 24
Finished Apr 23 01:26:14 PM PDT 24
Peak memory 211832 kb
Host smart-7238411f-45b9-4822-81e7-d2672ef9888c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429070215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.3429070215
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.3766017318
Short name T335
Test name
Test status
Simulation time 5453661593 ps
CPU time 3.41 seconds
Started Apr 23 01:25:45 PM PDT 24
Finished Apr 23 01:25:48 PM PDT 24
Peak memory 203876 kb
Host smart-536cf6b2-c1f7-48d8-8e8a-034536777442
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766017318 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.3766017318
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.994104236
Short name T555
Test name
Test status
Simulation time 10181337207 ps
CPU time 14.28 seconds
Started Apr 23 01:25:44 PM PDT 24
Finished Apr 23 01:25:59 PM PDT 24
Peak memory 275436 kb
Host smart-93bc44da-23e4-41e5-990d-d46dd63db721
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994104236 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_fifo_reset_tx.994104236
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.1229745479
Short name T989
Test name
Test status
Simulation time 7870847598 ps
CPU time 2.5 seconds
Started Apr 23 01:25:45 PM PDT 24
Finished Apr 23 01:25:48 PM PDT 24
Peak memory 203780 kb
Host smart-c1cbcd47-36e6-4cc2-a0a9-c8125833ba17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229745479 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.1229745479
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.1632951101
Short name T267
Test name
Test status
Simulation time 1074612743 ps
CPU time 5.19 seconds
Started Apr 23 01:25:44 PM PDT 24
Finished Apr 23 01:25:50 PM PDT 24
Peak memory 219696 kb
Host smart-fcc74877-015a-49ba-ba7e-19a978cf401f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632951101 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.1632951101
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.2169101842
Short name T1151
Test name
Test status
Simulation time 16195487902 ps
CPU time 312.75 seconds
Started Apr 23 01:25:43 PM PDT 24
Finished Apr 23 01:30:57 PM PDT 24
Peak memory 3866012 kb
Host smart-c49e3fae-34e8-4b30-b61a-283f432f7273
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169101842 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.2169101842
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1427383847
Short name T1307
Test name
Test status
Simulation time 1187467823 ps
CPU time 48.83 seconds
Started Apr 23 01:25:40 PM PDT 24
Finished Apr 23 01:26:29 PM PDT 24
Peak memory 203660 kb
Host smart-d07ebe18-fb3c-4405-8cea-9de5a864dcd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427383847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1427383847
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.2141514513
Short name T104
Test name
Test status
Simulation time 1302608727 ps
CPU time 13.88 seconds
Started Apr 23 01:25:40 PM PDT 24
Finished Apr 23 01:25:54 PM PDT 24
Peak memory 203760 kb
Host smart-158b1d4c-1584-4d9b-9265-8d0d642657b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141514513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.2141514513
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.2477507785
Short name T641
Test name
Test status
Simulation time 51130807231 ps
CPU time 1285.55 seconds
Started Apr 23 01:25:38 PM PDT 24
Finished Apr 23 01:47:05 PM PDT 24
Peak memory 7892576 kb
Host smart-627d21c6-c244-445b-a6a8-efc7e9c6b046
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477507785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.2477507785
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.2145603321
Short name T1354
Test name
Test status
Simulation time 1606040979 ps
CPU time 7.78 seconds
Started Apr 23 01:25:44 PM PDT 24
Finished Apr 23 01:25:52 PM PDT 24
Peak memory 219952 kb
Host smart-6b3cdaeb-8e37-43f1-8e30-7c6dfc7f383f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145603321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.2145603321
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.548954565
Short name T1302
Test name
Test status
Simulation time 27032973 ps
CPU time 0.63 seconds
Started Apr 23 01:25:52 PM PDT 24
Finished Apr 23 01:25:54 PM PDT 24
Peak memory 203300 kb
Host smart-89cd6c07-ceae-4100-91cf-5c4dcc606cfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548954565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.548954565
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.2136087880
Short name T1168
Test name
Test status
Simulation time 929963919 ps
CPU time 2.07 seconds
Started Apr 23 01:25:46 PM PDT 24
Finished Apr 23 01:25:49 PM PDT 24
Peak memory 211936 kb
Host smart-2ad1ca33-deb9-4882-9ce5-4128bbf6aff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136087880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.2136087880
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.461615989
Short name T634
Test name
Test status
Simulation time 244441939 ps
CPU time 12.06 seconds
Started Apr 23 01:25:51 PM PDT 24
Finished Apr 23 01:26:04 PM PDT 24
Peak memory 251640 kb
Host smart-4d101305-d6bd-4ad5-990a-7d84fd4c33b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461615989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empt
y.461615989
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.2256315300
Short name T1325
Test name
Test status
Simulation time 15755280769 ps
CPU time 96.35 seconds
Started Apr 23 01:25:51 PM PDT 24
Finished Apr 23 01:27:28 PM PDT 24
Peak memory 792328 kb
Host smart-93455d1d-0c41-4f1d-86d5-1fb4e8a5b48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256315300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.2256315300
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.221305729
Short name T774
Test name
Test status
Simulation time 1253616774 ps
CPU time 38.22 seconds
Started Apr 23 01:25:46 PM PDT 24
Finished Apr 23 01:26:25 PM PDT 24
Peak memory 480208 kb
Host smart-8905015e-a405-405f-9be5-687d2db91248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221305729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.221305729
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.3994809356
Short name T466
Test name
Test status
Simulation time 348754006 ps
CPU time 0.89 seconds
Started Apr 23 01:25:49 PM PDT 24
Finished Apr 23 01:25:50 PM PDT 24
Peak memory 203388 kb
Host smart-57e1e285-e990-4864-8f42-5028c91b12e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994809356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.3994809356
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.2887710457
Short name T1110
Test name
Test status
Simulation time 843111419 ps
CPU time 5.94 seconds
Started Apr 23 01:25:50 PM PDT 24
Finished Apr 23 01:25:56 PM PDT 24
Peak memory 245140 kb
Host smart-48ad8f3e-69bf-4413-92bf-33d97f6f5ad4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887710457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.2887710457
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.346222729
Short name T323
Test name
Test status
Simulation time 20397794789 ps
CPU time 344.54 seconds
Started Apr 23 01:25:47 PM PDT 24
Finished Apr 23 01:31:32 PM PDT 24
Peak memory 1268708 kb
Host smart-07645b2a-d472-4eb4-a83d-cd340caa0e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346222729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.346222729
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.865504796
Short name T496
Test name
Test status
Simulation time 707639820 ps
CPU time 2.99 seconds
Started Apr 23 01:25:49 PM PDT 24
Finished Apr 23 01:25:53 PM PDT 24
Peak memory 203620 kb
Host smart-ceb41458-445b-4304-ad93-df103d7ffb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865504796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.865504796
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.4072054698
Short name T433
Test name
Test status
Simulation time 13550964458 ps
CPU time 68.46 seconds
Started Apr 23 01:25:51 PM PDT 24
Finished Apr 23 01:27:00 PM PDT 24
Peak memory 287920 kb
Host smart-39502224-ef16-46d0-a3f0-4721e8a8e1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072054698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.4072054698
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.2853313524
Short name T1011
Test name
Test status
Simulation time 17221864 ps
CPU time 0.66 seconds
Started Apr 23 01:25:51 PM PDT 24
Finished Apr 23 01:25:52 PM PDT 24
Peak memory 203404 kb
Host smart-f33c0712-44a3-432b-8288-8ed196137a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853313524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.2853313524
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.80051741
Short name T591
Test name
Test status
Simulation time 24404229775 ps
CPU time 521.49 seconds
Started Apr 23 01:25:47 PM PDT 24
Finished Apr 23 01:34:29 PM PDT 24
Peak memory 1286492 kb
Host smart-3e64a63d-4990-46c7-9796-3ad02774952b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80051741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.80051741
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.1431447081
Short name T373
Test name
Test status
Simulation time 6279722329 ps
CPU time 23.82 seconds
Started Apr 23 01:25:49 PM PDT 24
Finished Apr 23 01:26:13 PM PDT 24
Peak memory 300120 kb
Host smart-f281b04e-2119-4150-96a5-a3d97c01ac90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431447081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.1431447081
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.3116092540
Short name T175
Test name
Test status
Simulation time 26409479818 ps
CPU time 341.12 seconds
Started Apr 23 01:25:52 PM PDT 24
Finished Apr 23 01:31:34 PM PDT 24
Peak memory 1794804 kb
Host smart-fb29f76d-5639-48c4-8e58-afe25bf6a8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116092540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.3116092540
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.1529512907
Short name T1061
Test name
Test status
Simulation time 493346071 ps
CPU time 7.49 seconds
Started Apr 23 01:25:50 PM PDT 24
Finished Apr 23 01:25:58 PM PDT 24
Peak memory 217600 kb
Host smart-c3097391-4109-4efb-bea1-d37737d0e233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529512907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.1529512907
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.12081760
Short name T681
Test name
Test status
Simulation time 3160257415 ps
CPU time 3.86 seconds
Started Apr 23 01:25:53 PM PDT 24
Finished Apr 23 01:25:57 PM PDT 24
Peak memory 211924 kb
Host smart-9f6454a4-6b75-429e-bc7a-b91b4282de3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12081760 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_bad_addr.12081760
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.2749716183
Short name T1090
Test name
Test status
Simulation time 10718851080 ps
CPU time 8.76 seconds
Started Apr 23 01:25:50 PM PDT 24
Finished Apr 23 01:25:59 PM PDT 24
Peak memory 237436 kb
Host smart-0899186c-376e-4346-b6a7-c2d62a088f50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749716183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.2749716183
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3853799079
Short name T611
Test name
Test status
Simulation time 10149496864 ps
CPU time 13.53 seconds
Started Apr 23 01:25:52 PM PDT 24
Finished Apr 23 01:26:06 PM PDT 24
Peak memory 291876 kb
Host smart-1003dd8c-4437-4176-85af-223e889186ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853799079 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3853799079
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.927509837
Short name T864
Test name
Test status
Simulation time 466927242 ps
CPU time 2.96 seconds
Started Apr 23 01:25:52 PM PDT 24
Finished Apr 23 01:25:55 PM PDT 24
Peak memory 203676 kb
Host smart-048fd2be-6cd4-48d3-a50a-4cf03fedefe4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927509837 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.i2c_target_hrst.927509837
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.119815083
Short name T1216
Test name
Test status
Simulation time 706640311 ps
CPU time 3.62 seconds
Started Apr 23 01:25:53 PM PDT 24
Finished Apr 23 01:25:57 PM PDT 24
Peak memory 203768 kb
Host smart-051d0998-4500-41ac-9bd6-3fbe30a3673a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119815083 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_intr_smoke.119815083
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.2593029105
Short name T359
Test name
Test status
Simulation time 20924229374 ps
CPU time 404.92 seconds
Started Apr 23 01:25:48 PM PDT 24
Finished Apr 23 01:32:34 PM PDT 24
Peak memory 3584512 kb
Host smart-191bf9ad-6235-49f4-bd07-c8f6f0cba03f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593029105 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.2593029105
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.1937245840
Short name T1164
Test name
Test status
Simulation time 656728091 ps
CPU time 9.25 seconds
Started Apr 23 01:25:52 PM PDT 24
Finished Apr 23 01:26:02 PM PDT 24
Peak memory 203776 kb
Host smart-35a1de66-c8fa-4acb-acc7-7465dbfbf6af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937245840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.1937245840
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.569561950
Short name T535
Test name
Test status
Simulation time 1584350662 ps
CPU time 65.02 seconds
Started Apr 23 01:25:54 PM PDT 24
Finished Apr 23 01:27:00 PM PDT 24
Peak memory 206600 kb
Host smart-beed1efe-d23e-4b64-9a45-8ed4fc45506c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569561950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_rd.569561950
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.946129401
Short name T1253
Test name
Test status
Simulation time 13288318769 ps
CPU time 13.5 seconds
Started Apr 23 01:25:51 PM PDT 24
Finished Apr 23 01:26:05 PM PDT 24
Peak memory 203748 kb
Host smart-04c58b6f-9902-4d68-8e7d-bda15b2e4336
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946129401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_wr.946129401
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.166837738
Short name T301
Test name
Test status
Simulation time 13474510761 ps
CPU time 14.44 seconds
Started Apr 23 01:25:49 PM PDT 24
Finished Apr 23 01:26:04 PM PDT 24
Peak memory 329676 kb
Host smart-1bdc0a0d-5ce3-489a-99d2-a3185dab3e03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166837738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_t
arget_stretch.166837738
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.241497666
Short name T760
Test name
Test status
Simulation time 5003980643 ps
CPU time 6.33 seconds
Started Apr 23 01:25:53 PM PDT 24
Finished Apr 23 01:26:00 PM PDT 24
Peak memory 211980 kb
Host smart-31553487-ea99-4c1b-aa69-883ac89632a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241497666 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_timeout.241497666
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_unexp_stop.4180493726
Short name T476
Test name
Test status
Simulation time 944690643 ps
CPU time 5.89 seconds
Started Apr 23 01:25:52 PM PDT 24
Finished Apr 23 01:25:58 PM PDT 24
Peak memory 203644 kb
Host smart-a6e8f2bd-fc4f-4203-8e71-6141724cd5f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180493726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.i2c_target_unexp_stop.4180493726
Directory /workspace/29.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/3.i2c_alert_test.1887892036
Short name T1268
Test name
Test status
Simulation time 44274424 ps
CPU time 0.6 seconds
Started Apr 23 01:21:50 PM PDT 24
Finished Apr 23 01:21:51 PM PDT 24
Peak memory 203396 kb
Host smart-3340d5eb-b935-4e44-98da-54451f2ebe8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887892036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.1887892036
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3364872268
Short name T617
Test name
Test status
Simulation time 263815809 ps
CPU time 1.17 seconds
Started Apr 23 01:21:43 PM PDT 24
Finished Apr 23 01:21:45 PM PDT 24
Peak memory 211968 kb
Host smart-b6498685-6846-43e8-b020-65eb6acb788e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364872268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3364872268
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.152549658
Short name T1171
Test name
Test status
Simulation time 317529205 ps
CPU time 2.99 seconds
Started Apr 23 01:21:40 PM PDT 24
Finished Apr 23 01:21:44 PM PDT 24
Peak memory 229296 kb
Host smart-ff39fd32-57e7-43c5-8e36-454d01d184b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152549658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty
.152549658
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3795260842
Short name T92
Test name
Test status
Simulation time 10987299012 ps
CPU time 39.84 seconds
Started Apr 23 01:21:42 PM PDT 24
Finished Apr 23 01:22:22 PM PDT 24
Peak memory 472692 kb
Host smart-e762c309-1a24-441c-ac85-cfd80f18c96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795260842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3795260842
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.2420171255
Short name T309
Test name
Test status
Simulation time 5583842547 ps
CPU time 73.25 seconds
Started Apr 23 01:21:42 PM PDT 24
Finished Apr 23 01:22:55 PM PDT 24
Peak memory 445452 kb
Host smart-f9a4c75a-38d1-4144-92bc-69db839793a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420171255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.2420171255
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.2510342890
Short name T1137
Test name
Test status
Simulation time 243384972 ps
CPU time 1.16 seconds
Started Apr 23 01:21:40 PM PDT 24
Finished Apr 23 01:21:42 PM PDT 24
Peak memory 203592 kb
Host smart-79bf0290-77a1-4311-9c3c-b0d91026b4a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510342890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.2510342890
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.2632773548
Short name T844
Test name
Test status
Simulation time 196172090 ps
CPU time 2.68 seconds
Started Apr 23 01:21:41 PM PDT 24
Finished Apr 23 01:21:44 PM PDT 24
Peak memory 216852 kb
Host smart-8d1dc31f-48c3-4024-ae44-9c186cc9d62b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632773548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
2632773548
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.2520957625
Short name T820
Test name
Test status
Simulation time 23255252167 ps
CPU time 60.65 seconds
Started Apr 23 01:21:39 PM PDT 24
Finished Apr 23 01:22:40 PM PDT 24
Peak memory 806036 kb
Host smart-30f1557d-bcc3-4db1-b112-4d130aa17ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520957625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.2520957625
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.991102488
Short name T1211
Test name
Test status
Simulation time 1653284715 ps
CPU time 17.38 seconds
Started Apr 23 01:21:47 PM PDT 24
Finished Apr 23 01:22:05 PM PDT 24
Peak memory 203764 kb
Host smart-e7751626-b2df-4d27-94f7-27b40d831228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991102488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.991102488
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.535628302
Short name T793
Test name
Test status
Simulation time 6984636218 ps
CPU time 71.1 seconds
Started Apr 23 01:21:51 PM PDT 24
Finished Apr 23 01:23:02 PM PDT 24
Peak memory 310224 kb
Host smart-6ff41b13-5b8e-4741-b8c4-def65e877a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535628302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.535628302
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.564411376
Short name T186
Test name
Test status
Simulation time 106756269 ps
CPU time 0.71 seconds
Started Apr 23 01:21:39 PM PDT 24
Finished Apr 23 01:21:40 PM PDT 24
Peak memory 203332 kb
Host smart-864e3e62-3427-46e9-a29d-1890fa12f84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564411376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.564411376
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.1076224724
Short name T858
Test name
Test status
Simulation time 25494058921 ps
CPU time 281.76 seconds
Started Apr 23 01:21:52 PM PDT 24
Finished Apr 23 01:26:34 PM PDT 24
Peak memory 255924 kb
Host smart-9a4ca681-ec48-431a-8891-c88d0f5a234b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076224724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.1076224724
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.2845965323
Short name T472
Test name
Test status
Simulation time 970978842 ps
CPU time 43.68 seconds
Started Apr 23 01:21:42 PM PDT 24
Finished Apr 23 01:22:26 PM PDT 24
Peak memory 308192 kb
Host smart-d789612e-6c90-4b13-9696-b4b3dc8f9f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845965323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.2845965323
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.2744243464
Short name T184
Test name
Test status
Simulation time 905606634 ps
CPU time 42.21 seconds
Started Apr 23 01:21:45 PM PDT 24
Finished Apr 23 01:22:28 PM PDT 24
Peak memory 212716 kb
Host smart-d269d1f1-cea7-4c86-8283-ef63cdaf248b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744243464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.2744243464
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.979006358
Short name T123
Test name
Test status
Simulation time 376626068 ps
CPU time 0.89 seconds
Started Apr 23 01:21:46 PM PDT 24
Finished Apr 23 01:21:47 PM PDT 24
Peak memory 222116 kb
Host smart-a6b86405-120e-4ca6-a77e-8c9766aa1285
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979006358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.979006358
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.4183336870
Short name T1295
Test name
Test status
Simulation time 4575234724 ps
CPU time 2.72 seconds
Started Apr 23 01:21:46 PM PDT 24
Finished Apr 23 01:21:49 PM PDT 24
Peak memory 203848 kb
Host smart-8d06324f-01a7-428c-b67e-0f7cf4ae0c04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183336870 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.4183336870
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.2710644259
Short name T1315
Test name
Test status
Simulation time 10216645600 ps
CPU time 10.74 seconds
Started Apr 23 01:21:43 PM PDT 24
Finished Apr 23 01:21:54 PM PDT 24
Peak memory 274900 kb
Host smart-ef33a674-fd20-438b-aa34-78f2a9b04cdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710644259 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.2710644259
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.3171976205
Short name T643
Test name
Test status
Simulation time 10268514396 ps
CPU time 17.14 seconds
Started Apr 23 01:21:54 PM PDT 24
Finished Apr 23 01:22:12 PM PDT 24
Peak memory 317644 kb
Host smart-51056d20-b4c3-4487-91e7-6c011b0b83ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171976205 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.3171976205
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.422804886
Short name T30
Test name
Test status
Simulation time 536033633 ps
CPU time 2.84 seconds
Started Apr 23 01:21:44 PM PDT 24
Finished Apr 23 01:21:47 PM PDT 24
Peak memory 203800 kb
Host smart-328295c3-9a8d-4f54-bf8b-882bae256db3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422804886 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.i2c_target_hrst.422804886
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.2189769784
Short name T716
Test name
Test status
Simulation time 725559677 ps
CPU time 4.36 seconds
Started Apr 23 01:21:43 PM PDT 24
Finished Apr 23 01:21:48 PM PDT 24
Peak memory 204112 kb
Host smart-dfd264ff-1b52-4ee7-9649-211074416851
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189769784 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.2189769784
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.1001675025
Short name T15
Test name
Test status
Simulation time 10497330511 ps
CPU time 153.59 seconds
Started Apr 23 01:21:40 PM PDT 24
Finished Apr 23 01:24:15 PM PDT 24
Peak memory 2550580 kb
Host smart-13c14066-eb97-49b2-8b22-aa75f9c5a910
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001675025 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.1001675025
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.2339187599
Short name T1159
Test name
Test status
Simulation time 7502255373 ps
CPU time 29.27 seconds
Started Apr 23 01:21:43 PM PDT 24
Finished Apr 23 01:22:13 PM PDT 24
Peak memory 203732 kb
Host smart-0652485e-5ca0-4f98-b755-9e57ef6722e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339187599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.2339187599
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.2141241998
Short name T1169
Test name
Test status
Simulation time 5454088415 ps
CPU time 24.35 seconds
Started Apr 23 01:21:43 PM PDT 24
Finished Apr 23 01:22:08 PM PDT 24
Peak memory 215752 kb
Host smart-36acefe7-d6f6-47a2-9abf-fecab87dc687
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141241998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.2141241998
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.3829845183
Short name T722
Test name
Test status
Simulation time 28125059912 ps
CPU time 9.22 seconds
Started Apr 23 01:21:43 PM PDT 24
Finished Apr 23 01:21:53 PM PDT 24
Peak memory 279212 kb
Host smart-f82c31e8-f7bd-43a4-b89f-6476ca85b4a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829845183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.3829845183
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.1912147487
Short name T1213
Test name
Test status
Simulation time 14438849661 ps
CPU time 2040.27 seconds
Started Apr 23 01:21:45 PM PDT 24
Finished Apr 23 01:55:46 PM PDT 24
Peak memory 3432036 kb
Host smart-1d6077b1-bec4-4f11-bd16-97026f861bd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912147487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.1912147487
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.3349980078
Short name T1055
Test name
Test status
Simulation time 2192030889 ps
CPU time 5.98 seconds
Started Apr 23 01:21:53 PM PDT 24
Finished Apr 23 01:21:59 PM PDT 24
Peak memory 216080 kb
Host smart-39ef19fd-9b8d-4418-b3b8-9761189cb228
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349980078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.3349980078
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.3679397803
Short name T649
Test name
Test status
Simulation time 17320101 ps
CPU time 0.64 seconds
Started Apr 23 01:26:04 PM PDT 24
Finished Apr 23 01:26:05 PM PDT 24
Peak memory 203324 kb
Host smart-6b55b2c7-805d-4a5b-b5d0-472724eb3c69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679397803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.3679397803
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.1792815997
Short name T569
Test name
Test status
Simulation time 313110222 ps
CPU time 1.65 seconds
Started Apr 23 01:25:54 PM PDT 24
Finished Apr 23 01:25:56 PM PDT 24
Peak memory 212004 kb
Host smart-492a2554-254b-4a76-92db-92424386c2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792815997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.1792815997
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.2159791144
Short name T269
Test name
Test status
Simulation time 397728864 ps
CPU time 8.91 seconds
Started Apr 23 01:25:50 PM PDT 24
Finished Apr 23 01:26:00 PM PDT 24
Peak memory 289180 kb
Host smart-446fd445-881a-4afb-b68f-34d50799e13a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159791144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.2159791144
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.2554938329
Short name T1004
Test name
Test status
Simulation time 5723409594 ps
CPU time 43.9 seconds
Started Apr 23 01:25:55 PM PDT 24
Finished Apr 23 01:26:39 PM PDT 24
Peak memory 558988 kb
Host smart-0e4947d0-4818-4259-bea4-1392981226db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554938329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.2554938329
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.2162388596
Short name T317
Test name
Test status
Simulation time 9659651159 ps
CPU time 87.12 seconds
Started Apr 23 01:25:53 PM PDT 24
Finished Apr 23 01:27:21 PM PDT 24
Peak memory 780620 kb
Host smart-99e17406-031e-4973-b956-083dee69fb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162388596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.2162388596
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.3842322553
Short name T996
Test name
Test status
Simulation time 610930816 ps
CPU time 0.76 seconds
Started Apr 23 01:25:52 PM PDT 24
Finished Apr 23 01:25:54 PM PDT 24
Peak memory 203444 kb
Host smart-5431a127-b0ce-4ede-b0b6-4bd71d18956f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842322553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.3842322553
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.2293716451
Short name T409
Test name
Test status
Simulation time 664333064 ps
CPU time 3.56 seconds
Started Apr 23 01:25:56 PM PDT 24
Finished Apr 23 01:26:00 PM PDT 24
Peak memory 203680 kb
Host smart-8869eeb5-5b67-4f6d-ae13-b9e9b845f63e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293716451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.2293716451
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.3574936253
Short name T168
Test name
Test status
Simulation time 8794948846 ps
CPU time 111.99 seconds
Started Apr 23 01:25:56 PM PDT 24
Finished Apr 23 01:27:48 PM PDT 24
Peak memory 1247300 kb
Host smart-fb089382-b58d-4fae-a57d-a7d12eb11eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574936253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3574936253
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.3623650519
Short name T392
Test name
Test status
Simulation time 2433574307 ps
CPU time 4.19 seconds
Started Apr 23 01:26:03 PM PDT 24
Finished Apr 23 01:26:07 PM PDT 24
Peak memory 203664 kb
Host smart-2906b8b5-b68f-4e12-95c5-4f6ec49b11ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623650519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.3623650519
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.1207379703
Short name T838
Test name
Test status
Simulation time 1481342493 ps
CPU time 66.36 seconds
Started Apr 23 01:26:04 PM PDT 24
Finished Apr 23 01:27:11 PM PDT 24
Peak memory 260640 kb
Host smart-83c0f0d3-9246-4adc-882f-5a9eaefb6461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207379703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.1207379703
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.3465834289
Short name T307
Test name
Test status
Simulation time 126154369 ps
CPU time 0.7 seconds
Started Apr 23 01:25:50 PM PDT 24
Finished Apr 23 01:25:52 PM PDT 24
Peak memory 203412 kb
Host smart-cf7ddf5a-e577-497f-b0e4-0e45b294f217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465834289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3465834289
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.2330975265
Short name T306
Test name
Test status
Simulation time 4945571384 ps
CPU time 209.34 seconds
Started Apr 23 01:25:55 PM PDT 24
Finished Apr 23 01:29:24 PM PDT 24
Peak memory 211956 kb
Host smart-703925b3-fedc-4a39-bd2d-03220ef2fab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330975265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.2330975265
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.2409057741
Short name T1095
Test name
Test status
Simulation time 5171840801 ps
CPU time 69.25 seconds
Started Apr 23 01:25:52 PM PDT 24
Finished Apr 23 01:27:02 PM PDT 24
Peak memory 283740 kb
Host smart-ce02c695-ae6b-4ce8-9d5e-1959d05e0d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409057741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.2409057741
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.442623253
Short name T884
Test name
Test status
Simulation time 651536117 ps
CPU time 11.53 seconds
Started Apr 23 01:25:53 PM PDT 24
Finished Apr 23 01:26:06 PM PDT 24
Peak memory 220108 kb
Host smart-6fcfdb04-7327-425f-b4c0-19a44eb21e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442623253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.442623253
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.3344354787
Short name T423
Test name
Test status
Simulation time 881756562 ps
CPU time 4.54 seconds
Started Apr 23 01:26:03 PM PDT 24
Finished Apr 23 01:26:08 PM PDT 24
Peak memory 203752 kb
Host smart-85f168c8-83f1-45a6-99fc-44972e6e0418
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344354787 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3344354787
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.3546973460
Short name T354
Test name
Test status
Simulation time 10449687762 ps
CPU time 10.3 seconds
Started Apr 23 01:25:58 PM PDT 24
Finished Apr 23 01:26:09 PM PDT 24
Peak memory 253760 kb
Host smart-78e4166c-50d4-446d-b0ae-e86d1ea87f99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546973460 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.3546973460
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2976845643
Short name T340
Test name
Test status
Simulation time 10128750270 ps
CPU time 79.77 seconds
Started Apr 23 01:25:59 PM PDT 24
Finished Apr 23 01:27:19 PM PDT 24
Peak memory 472748 kb
Host smart-4f833a42-e2d5-40d2-97a5-110b72c4d16f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976845643 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2976845643
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.2469823865
Short name T218
Test name
Test status
Simulation time 382682012 ps
CPU time 2.45 seconds
Started Apr 23 01:26:04 PM PDT 24
Finished Apr 23 01:26:07 PM PDT 24
Peak memory 203576 kb
Host smart-0599eec7-1c02-4b3c-8093-4f33fde20098
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469823865 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.2469823865
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.98070491
Short name T1355
Test name
Test status
Simulation time 2121459154 ps
CPU time 5.42 seconds
Started Apr 23 01:25:59 PM PDT 24
Finished Apr 23 01:26:04 PM PDT 24
Peak memory 214236 kb
Host smart-80583332-ce13-4f0a-8609-1d0b2a049db3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98070491 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.98070491
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.1407290808
Short name T343
Test name
Test status
Simulation time 21546757255 ps
CPU time 448.65 seconds
Started Apr 23 01:25:59 PM PDT 24
Finished Apr 23 01:33:28 PM PDT 24
Peak memory 3752360 kb
Host smart-1a9bc8f9-4052-419a-b1fb-cc622d2c166f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407290808 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.1407290808
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.1086197560
Short name T572
Test name
Test status
Simulation time 5789096438 ps
CPU time 51.54 seconds
Started Apr 23 01:25:57 PM PDT 24
Finished Apr 23 01:26:49 PM PDT 24
Peak memory 203788 kb
Host smart-bcf37836-feb8-41f8-860d-ace67fd4a1f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086197560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.1086197560
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.2692028750
Short name T465
Test name
Test status
Simulation time 1321879884 ps
CPU time 16.62 seconds
Started Apr 23 01:25:58 PM PDT 24
Finished Apr 23 01:26:15 PM PDT 24
Peak memory 212900 kb
Host smart-4adf29ad-5d51-4673-bed8-4a9d8e8e56e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692028750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.2692028750
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.2471431151
Short name T991
Test name
Test status
Simulation time 26933329420 ps
CPU time 47.15 seconds
Started Apr 23 01:25:57 PM PDT 24
Finished Apr 23 01:26:45 PM PDT 24
Peak memory 904848 kb
Host smart-ae15ac03-713f-4a38-ab72-a0d9001ba4d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471431151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.2471431151
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.3890849193
Short name T272
Test name
Test status
Simulation time 28423746657 ps
CPU time 406.61 seconds
Started Apr 23 01:25:58 PM PDT 24
Finished Apr 23 01:32:46 PM PDT 24
Peak memory 1266300 kb
Host smart-83842da2-85dd-4ec0-82b4-bdcc175c44d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890849193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.3890849193
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.1704533440
Short name T930
Test name
Test status
Simulation time 1233694799 ps
CPU time 6.79 seconds
Started Apr 23 01:25:57 PM PDT 24
Finished Apr 23 01:26:04 PM PDT 24
Peak memory 219980 kb
Host smart-95d104e4-9d03-45d3-ab13-23dce8ef4ffa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704533440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.1704533440
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_unexp_stop.4028683461
Short name T20
Test name
Test status
Simulation time 2650992716 ps
CPU time 6.65 seconds
Started Apr 23 01:25:58 PM PDT 24
Finished Apr 23 01:26:05 PM PDT 24
Peak memory 208476 kb
Host smart-9e202a83-9937-4749-aa29-6b99c66bab69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028683461 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.i2c_target_unexp_stop.4028683461
Directory /workspace/30.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/31.i2c_alert_test.3100663465
Short name T877
Test name
Test status
Simulation time 24784128 ps
CPU time 0.62 seconds
Started Apr 23 01:26:09 PM PDT 24
Finished Apr 23 01:26:10 PM PDT 24
Peak memory 203404 kb
Host smart-5c3ed9fa-1841-4695-a4fd-3856bafd2bbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100663465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.3100663465
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.1048519892
Short name T9
Test name
Test status
Simulation time 196702670 ps
CPU time 1.32 seconds
Started Apr 23 01:26:01 PM PDT 24
Finished Apr 23 01:26:03 PM PDT 24
Peak memory 212016 kb
Host smart-7dc873f5-1a16-400a-b818-ca8c18a363d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048519892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.1048519892
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2377329367
Short name T1305
Test name
Test status
Simulation time 1716875757 ps
CPU time 6.58 seconds
Started Apr 23 01:26:00 PM PDT 24
Finished Apr 23 01:26:07 PM PDT 24
Peak memory 271916 kb
Host smart-1f928759-123a-448e-8f79-fb1defa76051
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377329367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.2377329367
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.3564581514
Short name T652
Test name
Test status
Simulation time 11308501684 ps
CPU time 146.43 seconds
Started Apr 23 01:26:04 PM PDT 24
Finished Apr 23 01:28:31 PM PDT 24
Peak memory 681236 kb
Host smart-22bcf9ff-df13-449f-9943-80656d1954b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564581514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.3564581514
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.2238310677
Short name T592
Test name
Test status
Simulation time 18546565620 ps
CPU time 65.79 seconds
Started Apr 23 01:26:01 PM PDT 24
Finished Apr 23 01:27:07 PM PDT 24
Peak memory 597352 kb
Host smart-e69eaa89-9724-4a08-8e5d-4643459892b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238310677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.2238310677
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.956593611
Short name T848
Test name
Test status
Simulation time 95313964 ps
CPU time 0.98 seconds
Started Apr 23 01:26:04 PM PDT 24
Finished Apr 23 01:26:06 PM PDT 24
Peak memory 203464 kb
Host smart-61198a38-6dcb-45b6-9732-e10a2273f630
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956593611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fm
t.956593611
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.1208394844
Short name T704
Test name
Test status
Simulation time 925484910 ps
CPU time 4.68 seconds
Started Apr 23 01:26:02 PM PDT 24
Finished Apr 23 01:26:07 PM PDT 24
Peak memory 238408 kb
Host smart-f02c84a4-72ec-4cda-bb99-4c10ab3adf6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208394844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.1208394844
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.4050382209
Short name T1106
Test name
Test status
Simulation time 9615468507 ps
CPU time 68.94 seconds
Started Apr 23 01:26:00 PM PDT 24
Finished Apr 23 01:27:09 PM PDT 24
Peak memory 803012 kb
Host smart-4fa34c2b-8d2e-46ab-95bc-e6decb82200e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050382209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.4050382209
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.948593952
Short name T558
Test name
Test status
Simulation time 3030507505 ps
CPU time 6.97 seconds
Started Apr 23 01:26:15 PM PDT 24
Finished Apr 23 01:26:22 PM PDT 24
Peak memory 203652 kb
Host smart-7fec817a-be25-4c63-9775-3b0c9bd91ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948593952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.948593952
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.693048535
Short name T387
Test name
Test status
Simulation time 3953084396 ps
CPU time 15.59 seconds
Started Apr 23 01:26:11 PM PDT 24
Finished Apr 23 01:26:26 PM PDT 24
Peak memory 243864 kb
Host smart-821c8609-ede5-484d-914b-22ddd4e33ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693048535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.693048535
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.750012610
Short name T1194
Test name
Test status
Simulation time 87785105 ps
CPU time 0.69 seconds
Started Apr 23 01:26:01 PM PDT 24
Finished Apr 23 01:26:03 PM PDT 24
Peak memory 203416 kb
Host smart-13ea9462-4c57-4b21-9916-8cf8cb9c9c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750012610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.750012610
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.214322151
Short name T196
Test name
Test status
Simulation time 5582521839 ps
CPU time 42.85 seconds
Started Apr 23 01:26:04 PM PDT 24
Finished Apr 23 01:26:47 PM PDT 24
Peak memory 553296 kb
Host smart-a0e544e9-1a51-4e6a-bbfb-08c7c91197e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214322151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.214322151
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.1357932335
Short name T313
Test name
Test status
Simulation time 2485578264 ps
CPU time 60.23 seconds
Started Apr 23 01:26:03 PM PDT 24
Finished Apr 23 01:27:04 PM PDT 24
Peak memory 293308 kb
Host smart-0bcac741-8ff2-48c6-b692-52bfc1698c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357932335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.1357932335
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.3964763183
Short name T56
Test name
Test status
Simulation time 16178440319 ps
CPU time 506.34 seconds
Started Apr 23 01:26:02 PM PDT 24
Finished Apr 23 01:34:29 PM PDT 24
Peak memory 701004 kb
Host smart-fe2188c0-3e07-473a-95e5-e3de8a85dbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964763183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.3964763183
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.3020112124
Short name T388
Test name
Test status
Simulation time 699106608 ps
CPU time 12.17 seconds
Started Apr 23 01:26:02 PM PDT 24
Finished Apr 23 01:26:14 PM PDT 24
Peak memory 220020 kb
Host smart-50cbb066-f078-4bbe-946b-03185c856aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020112124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.3020112124
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.2259386876
Short name T536
Test name
Test status
Simulation time 996645438 ps
CPU time 2.61 seconds
Started Apr 23 01:26:13 PM PDT 24
Finished Apr 23 01:26:16 PM PDT 24
Peak memory 203692 kb
Host smart-d87ba4a1-b02e-46e6-aeda-b53847f75229
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259386876 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.2259386876
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.705950973
Short name T484
Test name
Test status
Simulation time 10133491212 ps
CPU time 73.36 seconds
Started Apr 23 01:26:10 PM PDT 24
Finished Apr 23 01:27:24 PM PDT 24
Peak memory 421576 kb
Host smart-7f4d0a2e-d17b-4657-9e08-3d876742127f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705950973 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_acq.705950973
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.2706121287
Short name T601
Test name
Test status
Simulation time 11208876346 ps
CPU time 3.14 seconds
Started Apr 23 01:26:10 PM PDT 24
Finished Apr 23 01:26:14 PM PDT 24
Peak memory 226236 kb
Host smart-a142e925-2b3a-441d-bcd6-7c27d204c84f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706121287 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.2706121287
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.11027067
Short name T1218
Test name
Test status
Simulation time 502153761 ps
CPU time 2.8 seconds
Started Apr 23 01:26:09 PM PDT 24
Finished Apr 23 01:26:12 PM PDT 24
Peak memory 203616 kb
Host smart-66701f71-5878-4bbc-be37-472cab8bb7bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11027067 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.i2c_target_hrst.11027067
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.1966978444
Short name T1178
Test name
Test status
Simulation time 3666700956 ps
CPU time 5.48 seconds
Started Apr 23 01:26:06 PM PDT 24
Finished Apr 23 01:26:12 PM PDT 24
Peak memory 208336 kb
Host smart-53e350ac-5506-4017-a249-e68182b34901
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966978444 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.1966978444
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.2193254630
Short name T554
Test name
Test status
Simulation time 8445869350 ps
CPU time 26.22 seconds
Started Apr 23 01:26:06 PM PDT 24
Finished Apr 23 01:26:32 PM PDT 24
Peak memory 544736 kb
Host smart-35a10ce4-a225-4356-a42c-1f913e551794
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193254630 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.2193254630
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.3818199139
Short name T111
Test name
Test status
Simulation time 1057184929 ps
CPU time 39.67 seconds
Started Apr 23 01:26:06 PM PDT 24
Finished Apr 23 01:26:46 PM PDT 24
Peak memory 203652 kb
Host smart-ce74c235-b603-4b99-b00b-39c0fe507fac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818199139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.3818199139
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.582837645
Short name T806
Test name
Test status
Simulation time 2086896168 ps
CPU time 20.33 seconds
Started Apr 23 01:26:06 PM PDT 24
Finished Apr 23 01:26:27 PM PDT 24
Peak memory 203648 kb
Host smart-b76c2f7e-b9b1-48fb-9a3b-14e1ced2f67f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582837645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c
_target_stress_rd.582837645
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.3253299567
Short name T314
Test name
Test status
Simulation time 53635087728 ps
CPU time 434.28 seconds
Started Apr 23 01:26:06 PM PDT 24
Finished Apr 23 01:33:21 PM PDT 24
Peak memory 4159616 kb
Host smart-5d05025a-c6d1-4bd0-9925-195a6e9f674a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253299567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.3253299567
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.536883072
Short name T836
Test name
Test status
Simulation time 8763411609 ps
CPU time 41.72 seconds
Started Apr 23 01:26:05 PM PDT 24
Finished Apr 23 01:26:47 PM PDT 24
Peak memory 336468 kb
Host smart-6a8f1282-61b6-4e65-a444-5f3813beb80d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536883072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_t
arget_stretch.536883072
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.3166408840
Short name T642
Test name
Test status
Simulation time 2450837211 ps
CPU time 5.77 seconds
Started Apr 23 01:26:06 PM PDT 24
Finished Apr 23 01:26:13 PM PDT 24
Peak memory 211924 kb
Host smart-8d017a04-3961-47da-a790-1da37751672f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166408840 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.3166408840
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.42889469
Short name T304
Test name
Test status
Simulation time 40087403 ps
CPU time 0.62 seconds
Started Apr 23 01:26:18 PM PDT 24
Finished Apr 23 01:26:19 PM PDT 24
Peak memory 203348 kb
Host smart-3b1f8466-e60f-4d4e-9abb-0114fbd972a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42889469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.42889469
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.2676894169
Short name T1172
Test name
Test status
Simulation time 194053571 ps
CPU time 2.02 seconds
Started Apr 23 01:26:12 PM PDT 24
Finished Apr 23 01:26:15 PM PDT 24
Peak memory 211972 kb
Host smart-79cf297a-b4b8-4a1e-9fd3-c88f0255335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676894169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.2676894169
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.4190297110
Short name T701
Test name
Test status
Simulation time 1756217885 ps
CPU time 22.77 seconds
Started Apr 23 01:26:13 PM PDT 24
Finished Apr 23 01:26:36 PM PDT 24
Peak memory 270108 kb
Host smart-469f9f5b-2bed-4a93-89ee-661a3eabca9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190297110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.4190297110
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.1838152820
Short name T1227
Test name
Test status
Simulation time 8240349638 ps
CPU time 70 seconds
Started Apr 23 01:26:14 PM PDT 24
Finished Apr 23 01:27:25 PM PDT 24
Peak memory 718740 kb
Host smart-25219056-91d9-4f6a-9e40-677092fb26e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838152820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.1838152820
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.1504080052
Short name T1048
Test name
Test status
Simulation time 3899626108 ps
CPU time 135.03 seconds
Started Apr 23 01:26:14 PM PDT 24
Finished Apr 23 01:28:30 PM PDT 24
Peak memory 639560 kb
Host smart-cb3e6637-05e1-47de-b900-cbe2ee964d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504080052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1504080052
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.4017917469
Short name T746
Test name
Test status
Simulation time 2503985676 ps
CPU time 1.14 seconds
Started Apr 23 01:26:12 PM PDT 24
Finished Apr 23 01:26:14 PM PDT 24
Peak memory 203740 kb
Host smart-1ce687df-400d-4351-9307-c0b0a30346c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017917469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.4017917469
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.1011505571
Short name T1309
Test name
Test status
Simulation time 2026733144 ps
CPU time 4.07 seconds
Started Apr 23 01:26:12 PM PDT 24
Finished Apr 23 01:26:16 PM PDT 24
Peak memory 203740 kb
Host smart-caa35128-1025-4c8b-986d-30a4a48fe005
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011505571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.1011505571
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.3866468672
Short name T603
Test name
Test status
Simulation time 10871237235 ps
CPU time 188.52 seconds
Started Apr 23 01:26:11 PM PDT 24
Finished Apr 23 01:29:20 PM PDT 24
Peak memory 881180 kb
Host smart-50d833ae-7297-4eec-a056-1e3e98f89b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866468672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.3866468672
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.954381492
Short name T766
Test name
Test status
Simulation time 1850786546 ps
CPU time 5.55 seconds
Started Apr 23 01:26:17 PM PDT 24
Finished Apr 23 01:26:23 PM PDT 24
Peak memory 203676 kb
Host smart-cc92a7f2-6deb-4472-8425-fa9c0d954d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954381492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.954381492
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.2196225572
Short name T683
Test name
Test status
Simulation time 1471982476 ps
CPU time 66.64 seconds
Started Apr 23 01:26:18 PM PDT 24
Finished Apr 23 01:27:25 PM PDT 24
Peak memory 277892 kb
Host smart-9049579b-bbe0-42de-8de1-8deb43c3c916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196225572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.2196225572
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.3816938550
Short name T871
Test name
Test status
Simulation time 314444732 ps
CPU time 0.74 seconds
Started Apr 23 01:26:13 PM PDT 24
Finished Apr 23 01:26:15 PM PDT 24
Peak memory 203340 kb
Host smart-eb9b34ee-5c81-4522-8659-fd15b713a965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816938550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3816938550
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1349328989
Short name T644
Test name
Test status
Simulation time 18738047792 ps
CPU time 645.68 seconds
Started Apr 23 01:26:14 PM PDT 24
Finished Apr 23 01:37:01 PM PDT 24
Peak memory 938324 kb
Host smart-06fae64d-24e7-4989-ad2f-20d2fe3592d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349328989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1349328989
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.3852684460
Short name T1158
Test name
Test status
Simulation time 2221766840 ps
CPU time 24.15 seconds
Started Apr 23 01:26:14 PM PDT 24
Finished Apr 23 01:26:38 PM PDT 24
Peak memory 348384 kb
Host smart-76c633c9-40d5-4845-9093-da77dfb72ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852684460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.3852684460
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.3838962730
Short name T1275
Test name
Test status
Simulation time 20144091585 ps
CPU time 1099.84 seconds
Started Apr 23 01:26:15 PM PDT 24
Finished Apr 23 01:44:35 PM PDT 24
Peak memory 1229004 kb
Host smart-a09869fc-f2f9-402e-a77f-ae9200f389a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838962730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.3838962730
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.2700083335
Short name T1269
Test name
Test status
Simulation time 2415331687 ps
CPU time 28.49 seconds
Started Apr 23 01:26:12 PM PDT 24
Finished Apr 23 01:26:41 PM PDT 24
Peak memory 211988 kb
Host smart-380f438c-0cb3-4c9d-b82e-1ec5bbd05df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700083335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.2700083335
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.1213302227
Short name T1243
Test name
Test status
Simulation time 562497584 ps
CPU time 2.79 seconds
Started Apr 23 01:26:17 PM PDT 24
Finished Apr 23 01:26:20 PM PDT 24
Peak memory 203740 kb
Host smart-aad5f705-25c2-4099-a596-5c1aefc4c409
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213302227 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.1213302227
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.3188201864
Short name T1074
Test name
Test status
Simulation time 10064577140 ps
CPU time 28.68 seconds
Started Apr 23 01:26:18 PM PDT 24
Finished Apr 23 01:26:47 PM PDT 24
Peak memory 337676 kb
Host smart-8573c927-87f4-41e6-b6ca-61952466032d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188201864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.3188201864
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.3372837680
Short name T523
Test name
Test status
Simulation time 10429827938 ps
CPU time 14.13 seconds
Started Apr 23 01:26:17 PM PDT 24
Finished Apr 23 01:26:32 PM PDT 24
Peak memory 268472 kb
Host smart-b8d88bd9-c060-438d-8173-63b2af88fa28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372837680 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.3372837680
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.1648969191
Short name T1051
Test name
Test status
Simulation time 1221584593 ps
CPU time 2.05 seconds
Started Apr 23 01:26:19 PM PDT 24
Finished Apr 23 01:26:21 PM PDT 24
Peak memory 203708 kb
Host smart-bb1dd89a-e742-4b2c-96f3-d2028e5da723
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648969191 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.1648969191
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.939671728
Short name T292
Test name
Test status
Simulation time 20828799571 ps
CPU time 7.66 seconds
Started Apr 23 01:26:14 PM PDT 24
Finished Apr 23 01:26:23 PM PDT 24
Peak memory 218708 kb
Host smart-697c3563-09d9-461b-b0c9-c6f905d196dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939671728 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_intr_smoke.939671728
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.2180242439
Short name T1062
Test name
Test status
Simulation time 20351184225 ps
CPU time 79.03 seconds
Started Apr 23 01:26:14 PM PDT 24
Finished Apr 23 01:27:34 PM PDT 24
Peak memory 1203840 kb
Host smart-74b4c69b-fdd9-45e7-8c58-2a9abe1b1fae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180242439 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.2180242439
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.2421942331
Short name T670
Test name
Test status
Simulation time 4157992725 ps
CPU time 40.6 seconds
Started Apr 23 01:26:14 PM PDT 24
Finished Apr 23 01:26:55 PM PDT 24
Peak memory 203732 kb
Host smart-f213a09a-9ffb-49d0-b1c0-3b4edeef773b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421942331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.2421942331
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.520689713
Short name T740
Test name
Test status
Simulation time 1181882510 ps
CPU time 5.52 seconds
Started Apr 23 01:26:12 PM PDT 24
Finished Apr 23 01:26:18 PM PDT 24
Peak memory 203724 kb
Host smart-28b1425c-198c-40df-8f77-843b6aed528c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520689713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c
_target_stress_rd.520689713
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.21644111
Short name T743
Test name
Test status
Simulation time 57219330960 ps
CPU time 857.2 seconds
Started Apr 23 01:26:13 PM PDT 24
Finished Apr 23 01:40:31 PM PDT 24
Peak memory 6420652 kb
Host smart-cb2d7485-4420-4913-a49e-51e44ab9ca37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21644111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stress_wr.21644111
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.3062798024
Short name T386
Test name
Test status
Simulation time 33434127959 ps
CPU time 207.33 seconds
Started Apr 23 01:26:13 PM PDT 24
Finished Apr 23 01:29:41 PM PDT 24
Peak memory 1788108 kb
Host smart-88b8c478-0d4b-487b-97e1-923b4f870309
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062798024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.3062798024
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.2834336402
Short name T1288
Test name
Test status
Simulation time 1203805803 ps
CPU time 6.41 seconds
Started Apr 23 01:26:12 PM PDT 24
Finished Apr 23 01:26:19 PM PDT 24
Peak memory 210936 kb
Host smart-acf9d49d-331a-496c-807e-c1fbc18f116c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834336402 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.2834336402
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.1082803627
Short name T694
Test name
Test status
Simulation time 13960895 ps
CPU time 0.61 seconds
Started Apr 23 01:26:32 PM PDT 24
Finished Apr 23 01:26:33 PM PDT 24
Peak memory 203364 kb
Host smart-61c7b109-86a7-4626-a872-c8e15552beec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082803627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.1082803627
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.195835076
Short name T708
Test name
Test status
Simulation time 272951878 ps
CPU time 1.3 seconds
Started Apr 23 01:26:24 PM PDT 24
Finished Apr 23 01:26:26 PM PDT 24
Peak memory 220160 kb
Host smart-202850a4-d07d-4ab4-9451-bd4582cef54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195835076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.195835076
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.4154564765
Short name T998
Test name
Test status
Simulation time 336474954 ps
CPU time 7.84 seconds
Started Apr 23 01:26:22 PM PDT 24
Finished Apr 23 01:26:30 PM PDT 24
Peak memory 274660 kb
Host smart-7fc4ef77-ca07-4ec9-9767-fe255a86b974
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154564765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.4154564765
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.1931891460
Short name T319
Test name
Test status
Simulation time 4658741665 ps
CPU time 38.12 seconds
Started Apr 23 01:26:23 PM PDT 24
Finished Apr 23 01:27:01 PM PDT 24
Peak memory 483540 kb
Host smart-53d032f3-be37-42c0-834b-a5405e10e1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931891460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.1931891460
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.4174545697
Short name T648
Test name
Test status
Simulation time 5511849488 ps
CPU time 114.04 seconds
Started Apr 23 01:26:20 PM PDT 24
Finished Apr 23 01:28:15 PM PDT 24
Peak memory 599808 kb
Host smart-5a8868e2-fd54-440b-9e85-460cbb4c9dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174545697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.4174545697
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.131106351
Short name T1127
Test name
Test status
Simulation time 140654739 ps
CPU time 1.02 seconds
Started Apr 23 01:26:19 PM PDT 24
Finished Apr 23 01:26:21 PM PDT 24
Peak memory 203332 kb
Host smart-6cbea91a-f8af-4cba-b6b8-ad5e3c095664
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131106351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fm
t.131106351
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.3839886095
Short name T201
Test name
Test status
Simulation time 515269113 ps
CPU time 3.7 seconds
Started Apr 23 01:26:20 PM PDT 24
Finished Apr 23 01:26:24 PM PDT 24
Peak memory 203680 kb
Host smart-b4b8df19-e2b7-4445-b286-4c31e7d679d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839886095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.3839886095
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.494286534
Short name T232
Test name
Test status
Simulation time 5873691969 ps
CPU time 103.44 seconds
Started Apr 23 01:26:22 PM PDT 24
Finished Apr 23 01:28:06 PM PDT 24
Peak memory 1018984 kb
Host smart-be545edb-5c01-40e8-aedf-2adc1567d06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494286534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.494286534
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.3593101154
Short name T217
Test name
Test status
Simulation time 360265175 ps
CPU time 5.46 seconds
Started Apr 23 01:26:30 PM PDT 24
Finished Apr 23 01:26:36 PM PDT 24
Peak memory 203640 kb
Host smart-2bac0b8b-7906-491a-b81f-6a7625ce5ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593101154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.3593101154
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.3786986839
Short name T1212
Test name
Test status
Simulation time 5566341806 ps
CPU time 68.87 seconds
Started Apr 23 01:26:30 PM PDT 24
Finished Apr 23 01:27:40 PM PDT 24
Peak memory 301272 kb
Host smart-8b89665a-0014-4a74-9817-1322445a2e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786986839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.3786986839
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.661996667
Short name T438
Test name
Test status
Simulation time 122536971 ps
CPU time 0.65 seconds
Started Apr 23 01:26:20 PM PDT 24
Finished Apr 23 01:26:21 PM PDT 24
Peak memory 203304 kb
Host smart-1bd68fc2-37a2-461f-8aa7-7e303e4c1481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661996667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.661996667
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.459227561
Short name T76
Test name
Test status
Simulation time 32972213245 ps
CPU time 18.01 seconds
Started Apr 23 01:26:22 PM PDT 24
Finished Apr 23 01:26:40 PM PDT 24
Peak memory 203740 kb
Host smart-9857793d-bffd-4795-8e15-5c36cf3ffb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459227561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.459227561
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.970105689
Short name T792
Test name
Test status
Simulation time 4651576876 ps
CPU time 40.34 seconds
Started Apr 23 01:26:22 PM PDT 24
Finished Apr 23 01:27:03 PM PDT 24
Peak memory 349436 kb
Host smart-9f385932-914d-413c-b65d-69cde24cb89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970105689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.970105689
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.1956828300
Short name T1059
Test name
Test status
Simulation time 1991458365 ps
CPU time 9.92 seconds
Started Apr 23 01:26:21 PM PDT 24
Finished Apr 23 01:26:31 PM PDT 24
Peak memory 215236 kb
Host smart-2b2163d2-ffe4-4515-ae95-6e33cbc72de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956828300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.1956828300
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3049269432
Short name T1018
Test name
Test status
Simulation time 683601712 ps
CPU time 3.36 seconds
Started Apr 23 01:26:29 PM PDT 24
Finished Apr 23 01:26:32 PM PDT 24
Peak memory 203808 kb
Host smart-5d1a27a7-498c-4e68-802e-08347c512ffd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049269432 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3049269432
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.220356823
Short name T1236
Test name
Test status
Simulation time 10107563958 ps
CPU time 31.03 seconds
Started Apr 23 01:26:25 PM PDT 24
Finished Apr 23 01:26:57 PM PDT 24
Peak memory 315280 kb
Host smart-c877203a-a41d-437f-9951-eb011b9ef6f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220356823 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_acq.220356823
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.2263258864
Short name T734
Test name
Test status
Simulation time 10077908554 ps
CPU time 73.73 seconds
Started Apr 23 01:26:29 PM PDT 24
Finished Apr 23 01:27:43 PM PDT 24
Peak memory 557596 kb
Host smart-4f7023d9-69e5-4c0d-b5e3-a28e1a0dcdfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263258864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.2263258864
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.1456260999
Short name T1092
Test name
Test status
Simulation time 2094246169 ps
CPU time 2.54 seconds
Started Apr 23 01:26:27 PM PDT 24
Finished Apr 23 01:26:30 PM PDT 24
Peak memory 203732 kb
Host smart-bab49a06-87ee-4302-9f48-ea982bdfabcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456260999 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.1456260999
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.1520422631
Short name T692
Test name
Test status
Simulation time 704352159 ps
CPU time 4.01 seconds
Started Apr 23 01:26:25 PM PDT 24
Finished Apr 23 01:26:29 PM PDT 24
Peak memory 203820 kb
Host smart-85437ee9-6fb6-4854-a38d-2bdf4df4fe30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520422631 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.1520422631
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.918093988
Short name T93
Test name
Test status
Simulation time 20768803493 ps
CPU time 52.49 seconds
Started Apr 23 01:26:25 PM PDT 24
Finished Apr 23 01:27:18 PM PDT 24
Peak memory 1096116 kb
Host smart-746d15fe-1653-478b-a7f3-acc21141e916
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918093988 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.918093988
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.1342957594
Short name T797
Test name
Test status
Simulation time 4722971425 ps
CPU time 16.78 seconds
Started Apr 23 01:26:25 PM PDT 24
Finished Apr 23 01:26:42 PM PDT 24
Peak memory 203696 kb
Host smart-964098e5-76d6-4500-8b02-8f12cd5b4b72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342957594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.1342957594
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.3973830325
Short name T599
Test name
Test status
Simulation time 5799632838 ps
CPU time 20.01 seconds
Started Apr 23 01:26:24 PM PDT 24
Finished Apr 23 01:26:45 PM PDT 24
Peak memory 213868 kb
Host smart-43978c6f-5993-4f83-9427-fb1b112de42a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973830325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.3973830325
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.2439717824
Short name T350
Test name
Test status
Simulation time 25436849497 ps
CPU time 16.26 seconds
Started Apr 23 01:26:24 PM PDT 24
Finished Apr 23 01:26:41 PM PDT 24
Peak memory 373936 kb
Host smart-45a1d309-7d53-48a9-bd55-066adb22b6a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439717824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.2439717824
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.1629587046
Short name T256
Test name
Test status
Simulation time 16670561428 ps
CPU time 290.89 seconds
Started Apr 23 01:26:24 PM PDT 24
Finished Apr 23 01:31:16 PM PDT 24
Peak memory 1896360 kb
Host smart-6c15bdf8-5fe7-41b7-becc-a966970c160f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629587046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.1629587046
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.377810665
Short name T1161
Test name
Test status
Simulation time 5674786747 ps
CPU time 6.19 seconds
Started Apr 23 01:26:25 PM PDT 24
Finished Apr 23 01:26:32 PM PDT 24
Peak memory 211988 kb
Host smart-fee9c3b1-9c10-46f8-95c0-469466db8682
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377810665 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_timeout.377810665
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.4114268428
Short name T1330
Test name
Test status
Simulation time 18639284 ps
CPU time 0.62 seconds
Started Apr 23 01:26:36 PM PDT 24
Finished Apr 23 01:26:37 PM PDT 24
Peak memory 203392 kb
Host smart-a8a2297a-d045-420d-b13a-a27eb6b52cdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114268428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.4114268428
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.881771661
Short name T213
Test name
Test status
Simulation time 98659105 ps
CPU time 1.55 seconds
Started Apr 23 01:26:32 PM PDT 24
Finished Apr 23 01:26:34 PM PDT 24
Peak memory 211996 kb
Host smart-c3b2f0e8-ad0b-4b53-bec7-e137995d767b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881771661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.881771661
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.2057586965
Short name T98
Test name
Test status
Simulation time 556982435 ps
CPU time 5.75 seconds
Started Apr 23 01:26:35 PM PDT 24
Finished Apr 23 01:26:41 PM PDT 24
Peak memory 248364 kb
Host smart-942bb609-5af9-4c4b-ae21-53a159deaafd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057586965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.2057586965
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.2840177521
Short name T1139
Test name
Test status
Simulation time 3105739890 ps
CPU time 56.7 seconds
Started Apr 23 01:26:34 PM PDT 24
Finished Apr 23 01:27:31 PM PDT 24
Peak memory 630716 kb
Host smart-d6ed8bfe-fea0-4786-81a7-e333917725d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840177521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.2840177521
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.3903002272
Short name T853
Test name
Test status
Simulation time 4776174505 ps
CPU time 32.62 seconds
Started Apr 23 01:26:32 PM PDT 24
Finished Apr 23 01:27:05 PM PDT 24
Peak memory 440000 kb
Host smart-6cb6d95a-718d-4236-ae54-48f7a1297cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903002272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3903002272
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.4240751477
Short name T41
Test name
Test status
Simulation time 345724768 ps
CPU time 0.92 seconds
Started Apr 23 01:26:35 PM PDT 24
Finished Apr 23 01:26:36 PM PDT 24
Peak memory 203376 kb
Host smart-e0efdaa8-ef9d-4d64-95a8-a39823196e76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240751477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.4240751477
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.2537599357
Short name T1231
Test name
Test status
Simulation time 101552381 ps
CPU time 2.39 seconds
Started Apr 23 01:26:34 PM PDT 24
Finished Apr 23 01:26:37 PM PDT 24
Peak memory 203676 kb
Host smart-d90f9abb-f299-49a3-bc5d-39679bc1d6af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537599357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.2537599357
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.1287709641
Short name T1187
Test name
Test status
Simulation time 3085650751 ps
CPU time 208.41 seconds
Started Apr 23 01:26:32 PM PDT 24
Finished Apr 23 01:30:01 PM PDT 24
Peak memory 904580 kb
Host smart-4179894e-b126-4a9c-a2a1-9abdb4144e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287709641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.1287709641
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.414953439
Short name T1069
Test name
Test status
Simulation time 1581401437 ps
CPU time 5.19 seconds
Started Apr 23 01:26:37 PM PDT 24
Finished Apr 23 01:26:42 PM PDT 24
Peak memory 203616 kb
Host smart-2a812812-8153-411d-b026-165dc2a7c53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414953439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.414953439
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.2676847896
Short name T275
Test name
Test status
Simulation time 1900438074 ps
CPU time 90.9 seconds
Started Apr 23 01:26:36 PM PDT 24
Finished Apr 23 01:28:08 PM PDT 24
Peak memory 382100 kb
Host smart-b3ec380a-56a6-44ee-b30b-a9960839439b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676847896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.2676847896
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.3502746372
Short name T282
Test name
Test status
Simulation time 45176358 ps
CPU time 0.67 seconds
Started Apr 23 01:26:32 PM PDT 24
Finished Apr 23 01:26:33 PM PDT 24
Peak memory 203340 kb
Host smart-98b85e33-db6d-4f83-a750-a76ed758b611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502746372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.3502746372
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.939144841
Short name T1129
Test name
Test status
Simulation time 26893510936 ps
CPU time 290.83 seconds
Started Apr 23 01:26:31 PM PDT 24
Finished Apr 23 01:31:23 PM PDT 24
Peak memory 211984 kb
Host smart-4c3dc645-c50c-4676-ab87-4489e14eeb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939144841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.939144841
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.1192172239
Short name T1248
Test name
Test status
Simulation time 4587266569 ps
CPU time 21.13 seconds
Started Apr 23 01:26:32 PM PDT 24
Finished Apr 23 01:26:54 PM PDT 24
Peak memory 242216 kb
Host smart-68ba195f-6a34-479f-a36d-c6f02c39192d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192172239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.1192172239
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.1933445286
Short name T231
Test name
Test status
Simulation time 17009543343 ps
CPU time 1814.79 seconds
Started Apr 23 01:26:33 PM PDT 24
Finished Apr 23 01:56:49 PM PDT 24
Peak memory 2372268 kb
Host smart-c828013b-cc3e-477a-8fdc-cd3e81cab147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933445286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.1933445286
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.3343886535
Short name T539
Test name
Test status
Simulation time 2153606778 ps
CPU time 29.92 seconds
Started Apr 23 01:26:33 PM PDT 24
Finished Apr 23 01:27:03 PM PDT 24
Peak memory 212044 kb
Host smart-efc68ae2-bef5-47d8-ae25-0b1d3f3f83fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343886535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3343886535
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.1801881018
Short name T568
Test name
Test status
Simulation time 638819576 ps
CPU time 3.43 seconds
Started Apr 23 01:26:36 PM PDT 24
Finished Apr 23 01:26:40 PM PDT 24
Peak memory 203724 kb
Host smart-0d4fdc31-5464-4fd7-8ae0-00cf243ffcd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801881018 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.1801881018
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.3361204474
Short name T630
Test name
Test status
Simulation time 10030128426 ps
CPU time 68.44 seconds
Started Apr 23 01:26:36 PM PDT 24
Finished Apr 23 01:27:45 PM PDT 24
Peak memory 477176 kb
Host smart-b988a92d-ca26-4624-a9d0-2c9d36d45068
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361204474 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.3361204474
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.4170643733
Short name T280
Test name
Test status
Simulation time 10180761722 ps
CPU time 15.27 seconds
Started Apr 23 01:26:35 PM PDT 24
Finished Apr 23 01:26:51 PM PDT 24
Peak memory 278828 kb
Host smart-6c76207a-3f65-4cc1-a73a-2a10151f69c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170643733 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.4170643733
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.2054647989
Short name T1177
Test name
Test status
Simulation time 249700422 ps
CPU time 1.91 seconds
Started Apr 23 01:26:36 PM PDT 24
Finished Apr 23 01:26:38 PM PDT 24
Peak memory 203684 kb
Host smart-c09989b2-28c7-4866-8a8c-06bfbfbb9523
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054647989 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.2054647989
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.2378421349
Short name T556
Test name
Test status
Simulation time 2491851847 ps
CPU time 3.38 seconds
Started Apr 23 01:26:34 PM PDT 24
Finished Apr 23 01:26:38 PM PDT 24
Peak memory 205300 kb
Host smart-e733645c-e801-4454-ad7f-f182eb8cb0bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378421349 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.2378421349
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.1043440654
Short name T426
Test name
Test status
Simulation time 21111547194 ps
CPU time 516.21 seconds
Started Apr 23 01:26:34 PM PDT 24
Finished Apr 23 01:35:11 PM PDT 24
Peak memory 5130200 kb
Host smart-3a0575bd-230c-4b1e-a05d-b527a34c8a0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043440654 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.1043440654
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.1349714286
Short name T823
Test name
Test status
Simulation time 4789513894 ps
CPU time 19.52 seconds
Started Apr 23 01:26:33 PM PDT 24
Finished Apr 23 01:26:53 PM PDT 24
Peak memory 203704 kb
Host smart-13996774-fd13-41ff-8fa0-e3db72d3c912
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349714286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.1349714286
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.938392067
Short name T1282
Test name
Test status
Simulation time 1876629101 ps
CPU time 30.69 seconds
Started Apr 23 01:26:32 PM PDT 24
Finished Apr 23 01:27:04 PM PDT 24
Peak memory 221544 kb
Host smart-63d364c6-4399-4601-b318-67f7006593c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938392067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_rd.938392067
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.3557605139
Short name T1225
Test name
Test status
Simulation time 11959916538 ps
CPU time 11.79 seconds
Started Apr 23 01:26:34 PM PDT 24
Finished Apr 23 01:26:46 PM PDT 24
Peak memory 203788 kb
Host smart-5ac7e699-6336-4813-9126-3e5c798dd3b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557605139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.3557605139
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.1187812675
Short name T405
Test name
Test status
Simulation time 8413678836 ps
CPU time 76.48 seconds
Started Apr 23 01:26:34 PM PDT 24
Finished Apr 23 01:27:51 PM PDT 24
Peak memory 907724 kb
Host smart-90545aca-5831-476b-988a-450eeb986d90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187812675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.1187812675
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.3363553395
Short name T724
Test name
Test status
Simulation time 3236037504 ps
CPU time 8.07 seconds
Started Apr 23 01:26:33 PM PDT 24
Finished Apr 23 01:26:42 PM PDT 24
Peak memory 220020 kb
Host smart-cddbc8ba-0ad0-44e1-b94e-73e722f9ad9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363553395 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.3363553395
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.3292700937
Short name T830
Test name
Test status
Simulation time 60888083 ps
CPU time 0.61 seconds
Started Apr 23 01:26:45 PM PDT 24
Finished Apr 23 01:26:46 PM PDT 24
Peak memory 203404 kb
Host smart-5d7e1636-e7d1-4554-b71b-95dda7255640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292700937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.3292700937
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.4067079415
Short name T446
Test name
Test status
Simulation time 976097727 ps
CPU time 1.4 seconds
Started Apr 23 01:26:41 PM PDT 24
Finished Apr 23 01:26:42 PM PDT 24
Peak memory 212024 kb
Host smart-949a5944-7a0d-4f95-8599-97f681516fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067079415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.4067079415
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.4254705279
Short name T97
Test name
Test status
Simulation time 728646080 ps
CPU time 22.15 seconds
Started Apr 23 01:26:40 PM PDT 24
Finished Apr 23 01:27:03 PM PDT 24
Peak memory 293680 kb
Host smart-c196c91b-6da6-4fc1-9443-1b65ea02da3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254705279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.4254705279
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.2863348281
Short name T887
Test name
Test status
Simulation time 4897694055 ps
CPU time 71.35 seconds
Started Apr 23 01:26:41 PM PDT 24
Finished Apr 23 01:27:53 PM PDT 24
Peak memory 379208 kb
Host smart-76ff7e84-bcd6-4a1a-8650-b987e627fc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863348281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.2863348281
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.3687195113
Short name T620
Test name
Test status
Simulation time 3942089207 ps
CPU time 154.6 seconds
Started Apr 23 01:26:39 PM PDT 24
Finished Apr 23 01:29:14 PM PDT 24
Peak memory 693500 kb
Host smart-6c1bf4f8-6bcd-4591-b38e-2589980a55a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687195113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3687195113
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.3941654140
Short name T351
Test name
Test status
Simulation time 509861706 ps
CPU time 0.91 seconds
Started Apr 23 01:26:40 PM PDT 24
Finished Apr 23 01:26:42 PM PDT 24
Peak memory 203496 kb
Host smart-85c0c70a-0296-4b88-a473-9fdd56349b28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941654140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.3941654140
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.1436514502
Short name T1091
Test name
Test status
Simulation time 518087055 ps
CPU time 3.17 seconds
Started Apr 23 01:26:39 PM PDT 24
Finished Apr 23 01:26:42 PM PDT 24
Peak memory 224132 kb
Host smart-62f8d981-158b-4ffa-97e6-7420d3759e86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436514502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.1436514502
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.753782739
Short name T233
Test name
Test status
Simulation time 4275605042 ps
CPU time 140.32 seconds
Started Apr 23 01:26:41 PM PDT 24
Finished Apr 23 01:29:01 PM PDT 24
Peak memory 1267476 kb
Host smart-0bbe3f75-feac-4c2f-90b6-262123c7ad56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753782739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.753782739
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.1831576012
Short name T397
Test name
Test status
Simulation time 345987618 ps
CPU time 9.55 seconds
Started Apr 23 01:26:55 PM PDT 24
Finished Apr 23 01:27:05 PM PDT 24
Peak memory 203728 kb
Host smart-f450cf8c-4ce2-4aa9-b640-ac1914fc1a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831576012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.1831576012
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.1122399985
Short name T932
Test name
Test status
Simulation time 8512620504 ps
CPU time 98.47 seconds
Started Apr 23 01:26:47 PM PDT 24
Finished Apr 23 01:28:26 PM PDT 24
Peak memory 374436 kb
Host smart-129a3941-04bc-4d00-b70e-c3ee8c5b6db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122399985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.1122399985
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.1287496590
Short name T250
Test name
Test status
Simulation time 17599965 ps
CPU time 0.66 seconds
Started Apr 23 01:26:38 PM PDT 24
Finished Apr 23 01:26:39 PM PDT 24
Peak memory 203308 kb
Host smart-5b431bd7-c7f4-4a69-9a86-3042871a6478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287496590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.1287496590
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.1098174927
Short name T490
Test name
Test status
Simulation time 14060833785 ps
CPU time 130.37 seconds
Started Apr 23 01:26:39 PM PDT 24
Finished Apr 23 01:28:50 PM PDT 24
Peak memory 211908 kb
Host smart-3ba7f04f-7d16-4cc3-9c09-eba6b9bcf905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098174927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.1098174927
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.1169962664
Short name T415
Test name
Test status
Simulation time 2788141221 ps
CPU time 21.7 seconds
Started Apr 23 01:26:36 PM PDT 24
Finished Apr 23 01:26:58 PM PDT 24
Peak memory 300492 kb
Host smart-5dc87b76-f3e9-4cb3-bb8a-eea8f0dc8dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169962664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.1169962664
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.1676453224
Short name T177
Test name
Test status
Simulation time 11439915844 ps
CPU time 561.41 seconds
Started Apr 23 01:26:39 PM PDT 24
Finished Apr 23 01:36:01 PM PDT 24
Peak memory 1913684 kb
Host smart-fcb3f5e1-58a8-4d69-89a0-619a415c430e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676453224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.1676453224
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.759487063
Short name T459
Test name
Test status
Simulation time 809820097 ps
CPU time 7.07 seconds
Started Apr 23 01:26:38 PM PDT 24
Finished Apr 23 01:26:46 PM PDT 24
Peak memory 211892 kb
Host smart-b0d203c3-b121-463e-a276-3babfbab8689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759487063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.759487063
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.1607562191
Short name T952
Test name
Test status
Simulation time 832401934 ps
CPU time 4.25 seconds
Started Apr 23 01:26:44 PM PDT 24
Finished Apr 23 01:26:49 PM PDT 24
Peak memory 203804 kb
Host smart-e78efca6-ab6b-4c2f-8108-0d0a0f579758
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607562191 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.1607562191
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.3204249971
Short name T1188
Test name
Test status
Simulation time 10102037270 ps
CPU time 74.12 seconds
Started Apr 23 01:26:43 PM PDT 24
Finished Apr 23 01:27:57 PM PDT 24
Peak memory 428688 kb
Host smart-d718dcd4-e2c8-4604-8cd9-29c760d39811
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204249971 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.3204249971
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.3087275019
Short name T1007
Test name
Test status
Simulation time 10369634922 ps
CPU time 12.4 seconds
Started Apr 23 01:26:46 PM PDT 24
Finished Apr 23 01:26:58 PM PDT 24
Peak memory 265712 kb
Host smart-14f4c693-ada4-4b78-85aa-30ab93915cc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087275019 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.3087275019
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.1668790136
Short name T579
Test name
Test status
Simulation time 4912521023 ps
CPU time 2.64 seconds
Started Apr 23 01:26:44 PM PDT 24
Finished Apr 23 01:26:47 PM PDT 24
Peak memory 203860 kb
Host smart-3eb860e4-318c-4975-92ab-25121764b8f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668790136 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.1668790136
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.3419750079
Short name T1259
Test name
Test status
Simulation time 1115272856 ps
CPU time 5.54 seconds
Started Apr 23 01:26:40 PM PDT 24
Finished Apr 23 01:26:46 PM PDT 24
Peak memory 214704 kb
Host smart-80bb4a13-b7eb-4ed0-b7c7-0ef088a61e5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419750079 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.3419750079
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.985349273
Short name T1195
Test name
Test status
Simulation time 14933152724 ps
CPU time 35.79 seconds
Started Apr 23 01:26:44 PM PDT 24
Finished Apr 23 01:27:20 PM PDT 24
Peak memory 932624 kb
Host smart-047c5016-f887-45da-b3bc-61c09df854f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985349273 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.985349273
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.4101839370
Short name T1306
Test name
Test status
Simulation time 3871248732 ps
CPU time 35.86 seconds
Started Apr 23 01:26:40 PM PDT 24
Finished Apr 23 01:27:16 PM PDT 24
Peak memory 203704 kb
Host smart-80e54792-9f18-4f12-9a91-edb2bcfb3811
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101839370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.4101839370
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.3569686691
Short name T1146
Test name
Test status
Simulation time 5616309317 ps
CPU time 16.05 seconds
Started Apr 23 01:26:41 PM PDT 24
Finished Apr 23 01:26:57 PM PDT 24
Peak memory 217276 kb
Host smart-58b568d0-950b-4641-96cd-b3633f73ff64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569686691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.3569686691
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.1662648032
Short name T671
Test name
Test status
Simulation time 21258619290 ps
CPU time 10.47 seconds
Started Apr 23 01:26:39 PM PDT 24
Finished Apr 23 01:26:50 PM PDT 24
Peak memory 203772 kb
Host smart-fd6080f5-bfa3-4571-a71a-68bef7ac5c8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662648032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.1662648032
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2948887816
Short name T727
Test name
Test status
Simulation time 20792452567 ps
CPU time 1015.17 seconds
Started Apr 23 01:26:39 PM PDT 24
Finished Apr 23 01:43:34 PM PDT 24
Peak memory 4856164 kb
Host smart-fb27556b-a466-4e04-8465-74d7d4426459
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948887816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2948887816
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.1158520937
Short name T531
Test name
Test status
Simulation time 2920063778 ps
CPU time 7.31 seconds
Started Apr 23 01:26:44 PM PDT 24
Finished Apr 23 01:26:52 PM PDT 24
Peak memory 219108 kb
Host smart-2101e4ba-1029-41a5-8c6a-88afccadc9b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158520937 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.1158520937
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.3759667769
Short name T825
Test name
Test status
Simulation time 16627008 ps
CPU time 0.63 seconds
Started Apr 23 01:26:53 PM PDT 24
Finished Apr 23 01:26:54 PM PDT 24
Peak memory 203396 kb
Host smart-23fce851-20fd-4c20-937f-a855001fe5e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759667769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.3759667769
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.1723752634
Short name T1297
Test name
Test status
Simulation time 86011826 ps
CPU time 1.26 seconds
Started Apr 23 01:26:45 PM PDT 24
Finished Apr 23 01:26:47 PM PDT 24
Peak memory 212096 kb
Host smart-22ed02f6-e2ed-4264-be4a-22fdc9d227bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723752634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.1723752634
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.1193249499
Short name T1277
Test name
Test status
Simulation time 177586713 ps
CPU time 4.12 seconds
Started Apr 23 01:26:46 PM PDT 24
Finished Apr 23 01:26:51 PM PDT 24
Peak memory 237324 kb
Host smart-979f8d88-3315-4217-8e68-ff7b29b90491
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193249499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.1193249499
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.935802470
Short name T1012
Test name
Test status
Simulation time 10616059819 ps
CPU time 87.26 seconds
Started Apr 23 01:26:48 PM PDT 24
Finished Apr 23 01:28:16 PM PDT 24
Peak memory 522636 kb
Host smart-feae441f-2dc9-486d-a7b7-62d0b4fbfa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935802470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.935802470
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.840835406
Short name T475
Test name
Test status
Simulation time 1700325809 ps
CPU time 121.61 seconds
Started Apr 23 01:26:48 PM PDT 24
Finished Apr 23 01:28:50 PM PDT 24
Peak memory 608920 kb
Host smart-813ed97b-4baa-4f0b-85a1-55b1e9acdda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840835406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.840835406
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.1954303949
Short name T1346
Test name
Test status
Simulation time 119673631 ps
CPU time 1.02 seconds
Started Apr 23 01:26:49 PM PDT 24
Finished Apr 23 01:26:51 PM PDT 24
Peak memory 203460 kb
Host smart-8c7c94b8-c989-438f-af38-6b7a9cbabed5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954303949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.1954303949
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.1140826849
Short name T1326
Test name
Test status
Simulation time 338997067 ps
CPU time 8.5 seconds
Started Apr 23 01:26:46 PM PDT 24
Finished Apr 23 01:26:55 PM PDT 24
Peak memory 203676 kb
Host smart-dfbe2288-0857-459e-ba03-45a89a17b9ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140826849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.1140826849
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.1792842037
Short name T691
Test name
Test status
Simulation time 12418940287 ps
CPU time 67.72 seconds
Started Apr 23 01:26:48 PM PDT 24
Finished Apr 23 01:27:56 PM PDT 24
Peak memory 859188 kb
Host smart-c88a9368-0cb4-4e7e-b317-e096b2970c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792842037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.1792842037
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.3684568330
Short name T1015
Test name
Test status
Simulation time 1948601662 ps
CPU time 8.28 seconds
Started Apr 23 01:26:53 PM PDT 24
Finished Apr 23 01:27:02 PM PDT 24
Peak memory 203732 kb
Host smart-729d88f7-e524-4b4d-82bd-72acab3323f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684568330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.3684568330
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.454672668
Short name T249
Test name
Test status
Simulation time 3973658930 ps
CPU time 18.61 seconds
Started Apr 23 01:26:53 PM PDT 24
Finished Apr 23 01:27:12 PM PDT 24
Peak memory 325772 kb
Host smart-d4e7127e-35b4-4b30-84b0-a2743edaec01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454672668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.454672668
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.3558747558
Short name T756
Test name
Test status
Simulation time 27752127 ps
CPU time 0.68 seconds
Started Apr 23 01:26:49 PM PDT 24
Finished Apr 23 01:26:51 PM PDT 24
Peak memory 202904 kb
Host smart-6ea7ca78-048c-40f3-bc1f-2e527f07a416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558747558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.3558747558
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3731305915
Short name T64
Test name
Test status
Simulation time 5114229801 ps
CPU time 132.07 seconds
Started Apr 23 01:26:45 PM PDT 24
Finished Apr 23 01:28:58 PM PDT 24
Peak memory 788916 kb
Host smart-f12404be-c495-4950-bdb9-fa979b642950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731305915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3731305915
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.2579071517
Short name T597
Test name
Test status
Simulation time 1171553217 ps
CPU time 53.78 seconds
Started Apr 23 01:26:48 PM PDT 24
Finished Apr 23 01:27:42 PM PDT 24
Peak memory 277904 kb
Host smart-041371ad-dbf6-4472-909e-5a2f1ab3cca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579071517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.2579071517
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.3101980770
Short name T758
Test name
Test status
Simulation time 15564233105 ps
CPU time 430.36 seconds
Started Apr 23 01:26:46 PM PDT 24
Finished Apr 23 01:33:57 PM PDT 24
Peak memory 1375584 kb
Host smart-05803d8e-c04f-4482-b871-8f43b5f93a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101980770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.3101980770
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.41702509
Short name T1193
Test name
Test status
Simulation time 4055777262 ps
CPU time 11.48 seconds
Started Apr 23 01:26:47 PM PDT 24
Finished Apr 23 01:26:59 PM PDT 24
Peak memory 228152 kb
Host smart-4b84add4-3436-496b-ae31-37762a7fba25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41702509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.41702509
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.2726792343
Short name T822
Test name
Test status
Simulation time 970345459 ps
CPU time 4.47 seconds
Started Apr 23 01:26:50 PM PDT 24
Finished Apr 23 01:26:55 PM PDT 24
Peak memory 203760 kb
Host smart-26960838-0f84-4f55-abba-857beb25a67d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726792343 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2726792343
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.1985858764
Short name T504
Test name
Test status
Simulation time 10083545031 ps
CPU time 67.31 seconds
Started Apr 23 01:26:50 PM PDT 24
Finished Apr 23 01:27:58 PM PDT 24
Peak memory 481548 kb
Host smart-0b162296-b5e5-456d-b623-0a0d5bb6f1ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985858764 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.1985858764
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.809605183
Short name T1166
Test name
Test status
Simulation time 10055621549 ps
CPU time 66.53 seconds
Started Apr 23 01:26:50 PM PDT 24
Finished Apr 23 01:27:58 PM PDT 24
Peak memory 564264 kb
Host smart-af3d760e-5d8c-4aa8-bbc6-783875051dd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809605183 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_fifo_reset_tx.809605183
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.1887758028
Short name T462
Test name
Test status
Simulation time 869295947 ps
CPU time 2.54 seconds
Started Apr 23 01:26:52 PM PDT 24
Finished Apr 23 01:26:55 PM PDT 24
Peak memory 203712 kb
Host smart-7a043335-5b70-477f-9b3a-212982f4377d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887758028 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.1887758028
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.77902051
Short name T1313
Test name
Test status
Simulation time 1146374402 ps
CPU time 5.18 seconds
Started Apr 23 01:26:47 PM PDT 24
Finished Apr 23 01:26:52 PM PDT 24
Peak memory 212740 kb
Host smart-bce215ab-d50c-45aa-aed0-dbb5ffcaa3e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77902051 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_intr_smoke.77902051
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.2055980568
Short name T586
Test name
Test status
Simulation time 5319720727 ps
CPU time 12.34 seconds
Started Apr 23 01:26:46 PM PDT 24
Finished Apr 23 01:26:59 PM PDT 24
Peak memory 203760 kb
Host smart-776d87e9-1fc4-4307-826c-d06a5ce9e3ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055980568 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.2055980568
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.3171241152
Short name T984
Test name
Test status
Simulation time 4004281565 ps
CPU time 15.12 seconds
Started Apr 23 01:26:46 PM PDT 24
Finished Apr 23 01:27:02 PM PDT 24
Peak memory 203740 kb
Host smart-b26f59d0-752d-43b1-a725-c35c0c34894e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171241152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.3171241152
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.2168274665
Short name T291
Test name
Test status
Simulation time 1297570062 ps
CPU time 52.48 seconds
Started Apr 23 01:26:49 PM PDT 24
Finished Apr 23 01:27:42 PM PDT 24
Peak memory 204304 kb
Host smart-2c4bd8cb-1669-4c27-82b7-a7090f0e7091
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168274665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.2168274665
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.3012337825
Short name T1135
Test name
Test status
Simulation time 40182349092 ps
CPU time 216.37 seconds
Started Apr 23 01:26:47 PM PDT 24
Finished Apr 23 01:30:24 PM PDT 24
Peak memory 2606060 kb
Host smart-76b07b1d-720d-4417-a539-24993a4feb5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012337825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.3012337825
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.1908029552
Short name T1350
Test name
Test status
Simulation time 8166984592 ps
CPU time 106.1 seconds
Started Apr 23 01:26:48 PM PDT 24
Finished Apr 23 01:28:35 PM PDT 24
Peak memory 1262068 kb
Host smart-bb7136b6-23cf-407a-b5b1-74ebd3a4a5e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908029552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.1908029552
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.3253635791
Short name T431
Test name
Test status
Simulation time 7081890997 ps
CPU time 7.54 seconds
Started Apr 23 01:26:47 PM PDT 24
Finished Apr 23 01:26:55 PM PDT 24
Peak memory 218020 kb
Host smart-e73fccab-7e71-4b68-a12b-49d6c3cc0365
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253635791 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.3253635791
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_unexp_stop.1712956449
Short name T1115
Test name
Test status
Simulation time 19849594598 ps
CPU time 6.89 seconds
Started Apr 23 01:26:49 PM PDT 24
Finished Apr 23 01:26:56 PM PDT 24
Peak memory 212208 kb
Host smart-5088319c-901c-4332-8f1a-2977565acae4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712956449 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.i2c_target_unexp_stop.1712956449
Directory /workspace/36.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/37.i2c_alert_test.4152539160
Short name T1285
Test name
Test status
Simulation time 17191314 ps
CPU time 0.62 seconds
Started Apr 23 01:27:01 PM PDT 24
Finished Apr 23 01:27:03 PM PDT 24
Peak memory 203292 kb
Host smart-41f9b009-eae6-4058-a85a-a9839a2fc54c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152539160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.4152539160
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.1432494282
Short name T1122
Test name
Test status
Simulation time 279592002 ps
CPU time 1.64 seconds
Started Apr 23 01:26:56 PM PDT 24
Finished Apr 23 01:26:58 PM PDT 24
Peak memory 203884 kb
Host smart-b23dde41-ed44-4fd6-b450-28def6e049b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432494282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.1432494282
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.180116061
Short name T370
Test name
Test status
Simulation time 721130525 ps
CPU time 18.31 seconds
Started Apr 23 01:26:54 PM PDT 24
Finished Apr 23 01:27:13 PM PDT 24
Peak memory 280868 kb
Host smart-22ff8a19-9ec9-48d3-9038-1b21c91c985a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180116061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empt
y.180116061
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.170633650
Short name T99
Test name
Test status
Simulation time 8651934055 ps
CPU time 159.86 seconds
Started Apr 23 01:26:53 PM PDT 24
Finished Apr 23 01:29:34 PM PDT 24
Peak memory 711192 kb
Host smart-9690e1bb-b866-4f1c-976a-1c65ef74bf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170633650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.170633650
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.3624653628
Short name T439
Test name
Test status
Simulation time 5753374506 ps
CPU time 47.63 seconds
Started Apr 23 01:26:54 PM PDT 24
Finished Apr 23 01:27:42 PM PDT 24
Peak memory 548944 kb
Host smart-489adafc-9dce-4eeb-8e29-d8b1dc088994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624653628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.3624653628
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.2650640232
Short name T880
Test name
Test status
Simulation time 589304296 ps
CPU time 1.04 seconds
Started Apr 23 01:26:53 PM PDT 24
Finished Apr 23 01:26:54 PM PDT 24
Peak memory 203372 kb
Host smart-82169a05-cf94-4145-9bea-aa2baf75a170
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650640232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.2650640232
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.2133127202
Short name T430
Test name
Test status
Simulation time 203928162 ps
CPU time 3.31 seconds
Started Apr 23 01:26:54 PM PDT 24
Finished Apr 23 01:26:58 PM PDT 24
Peak memory 219084 kb
Host smart-d516a4a1-bcb1-4f7a-9ad7-d2180f9ee48c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133127202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.2133127202
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1369283246
Short name T1101
Test name
Test status
Simulation time 14240272468 ps
CPU time 122.35 seconds
Started Apr 23 01:26:53 PM PDT 24
Finished Apr 23 01:28:56 PM PDT 24
Peak memory 1230352 kb
Host smart-a9c4ff16-e3b6-4531-89c9-32874f86481f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369283246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1369283246
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.3232487386
Short name T1021
Test name
Test status
Simulation time 1713734112 ps
CPU time 5.03 seconds
Started Apr 23 01:27:00 PM PDT 24
Finished Apr 23 01:27:07 PM PDT 24
Peak memory 203648 kb
Host smart-177d3a7c-c58d-4737-ba8f-4ea8995989f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232487386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.3232487386
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.1685827529
Short name T960
Test name
Test status
Simulation time 1423933250 ps
CPU time 26.76 seconds
Started Apr 23 01:26:59 PM PDT 24
Finished Apr 23 01:27:28 PM PDT 24
Peak memory 284908 kb
Host smart-6b0dd7d7-f84a-4c34-af66-9739aaababec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685827529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.1685827529
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.1610926707
Short name T187
Test name
Test status
Simulation time 28450078 ps
CPU time 0.67 seconds
Started Apr 23 01:26:53 PM PDT 24
Finished Apr 23 01:26:54 PM PDT 24
Peak memory 203308 kb
Host smart-b6cf2a93-a64c-4dbf-9207-534a2d8e76cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610926707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.1610926707
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.1848424497
Short name T665
Test name
Test status
Simulation time 48766161605 ps
CPU time 3241.09 seconds
Started Apr 23 01:26:52 PM PDT 24
Finished Apr 23 02:20:54 PM PDT 24
Peak memory 4167740 kb
Host smart-7e5a7ac5-35b3-4677-88c7-f704401b4bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848424497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.1848424497
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.1332162179
Short name T929
Test name
Test status
Simulation time 1339811825 ps
CPU time 26.87 seconds
Started Apr 23 01:26:52 PM PDT 24
Finished Apr 23 01:27:20 PM PDT 24
Peak memory 310532 kb
Host smart-60c6837b-2e0b-4115-adc8-927698506ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332162179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.1332162179
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.963584053
Short name T1081
Test name
Test status
Simulation time 16884293112 ps
CPU time 728.67 seconds
Started Apr 23 01:26:55 PM PDT 24
Finished Apr 23 01:39:05 PM PDT 24
Peak memory 2351624 kb
Host smart-f8a76614-038d-4693-83fd-e3175be7c4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963584053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.963584053
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.2912663864
Short name T575
Test name
Test status
Simulation time 1189566117 ps
CPU time 11.05 seconds
Started Apr 23 01:26:53 PM PDT 24
Finished Apr 23 01:27:05 PM PDT 24
Peak memory 220048 kb
Host smart-a1dee81c-d308-4bac-88aa-2df724c39097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912663864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.2912663864
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.3305788831
Short name T582
Test name
Test status
Simulation time 2456791246 ps
CPU time 2.95 seconds
Started Apr 23 01:27:00 PM PDT 24
Finished Apr 23 01:27:05 PM PDT 24
Peak memory 203776 kb
Host smart-c3b8a92c-64b0-4a08-b9a8-51df2efa7ed2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305788831 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.3305788831
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.1659234282
Short name T1246
Test name
Test status
Simulation time 10539924912 ps
CPU time 13.12 seconds
Started Apr 23 01:26:57 PM PDT 24
Finished Apr 23 01:27:11 PM PDT 24
Peak memory 240428 kb
Host smart-e585b794-3f56-4279-a5fb-25dd1ad6b8a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659234282 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.1659234282
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.4184083052
Short name T1185
Test name
Test status
Simulation time 10141300436 ps
CPU time 11.76 seconds
Started Apr 23 01:26:58 PM PDT 24
Finished Apr 23 01:27:10 PM PDT 24
Peak memory 262800 kb
Host smart-1df6b553-f7d8-43c1-b7a0-3d8faa4946a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184083052 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.4184083052
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.3621507188
Short name T632
Test name
Test status
Simulation time 328174163 ps
CPU time 2.11 seconds
Started Apr 23 01:26:59 PM PDT 24
Finished Apr 23 01:27:03 PM PDT 24
Peak memory 203768 kb
Host smart-65edf19b-7987-47e5-803f-28ec10bb1da5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621507188 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.3621507188
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.3689230721
Short name T413
Test name
Test status
Simulation time 4143773616 ps
CPU time 5.89 seconds
Started Apr 23 01:26:57 PM PDT 24
Finished Apr 23 01:27:04 PM PDT 24
Peak memory 214508 kb
Host smart-5ddbd45d-9bd2-48bc-94dd-935628b8a4aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689230721 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.3689230721
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.3944763001
Short name T679
Test name
Test status
Simulation time 18576397456 ps
CPU time 48.96 seconds
Started Apr 23 01:26:56 PM PDT 24
Finished Apr 23 01:27:45 PM PDT 24
Peak memory 812164 kb
Host smart-87183543-07d4-4706-88ba-f51dc19f9ee9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944763001 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.3944763001
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.1041938042
Short name T222
Test name
Test status
Simulation time 692857535 ps
CPU time 10.82 seconds
Started Apr 23 01:26:57 PM PDT 24
Finished Apr 23 01:27:08 PM PDT 24
Peak memory 203684 kb
Host smart-e86cd399-6f15-4cfc-bba0-9c0829155207
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041938042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.1041938042
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.3479848147
Short name T1000
Test name
Test status
Simulation time 1557921279 ps
CPU time 67.1 seconds
Started Apr 23 01:26:55 PM PDT 24
Finished Apr 23 01:28:03 PM PDT 24
Peak memory 208536 kb
Host smart-9829355c-9830-44bd-ad41-85322d68b77f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479848147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.3479848147
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.37042655
Short name T464
Test name
Test status
Simulation time 55519107158 ps
CPU time 185.94 seconds
Started Apr 23 01:26:55 PM PDT 24
Finished Apr 23 01:30:01 PM PDT 24
Peak memory 2259360 kb
Host smart-73f3b637-3595-4a1f-9f49-8981e504e6d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37042655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stress_wr.37042655
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.1650677132
Short name T437
Test name
Test status
Simulation time 42625145616 ps
CPU time 939.12 seconds
Started Apr 23 01:26:58 PM PDT 24
Finished Apr 23 01:42:37 PM PDT 24
Peak memory 4703168 kb
Host smart-9fecc3c4-4750-4d65-b172-9041ccdfe933
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650677132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.1650677132
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.868163327
Short name T1240
Test name
Test status
Simulation time 1071993932 ps
CPU time 5.76 seconds
Started Apr 23 01:26:57 PM PDT 24
Finished Apr 23 01:27:03 PM PDT 24
Peak memory 211936 kb
Host smart-e000166f-4fec-42bb-8c91-b26c1bd69814
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868163327 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_timeout.868163327
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.286899954
Short name T1278
Test name
Test status
Simulation time 17852848 ps
CPU time 0.62 seconds
Started Apr 23 01:27:09 PM PDT 24
Finished Apr 23 01:27:10 PM PDT 24
Peak memory 203348 kb
Host smart-77ff28cc-d9ed-4daf-9c81-36253a26522a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286899954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.286899954
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.2888862701
Short name T330
Test name
Test status
Simulation time 245690652 ps
CPU time 1.26 seconds
Started Apr 23 01:27:03 PM PDT 24
Finished Apr 23 01:27:05 PM PDT 24
Peak memory 212052 kb
Host smart-9881c6e3-43fa-4962-8224-21ce50566737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888862701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.2888862701
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.244446389
Short name T865
Test name
Test status
Simulation time 216025476 ps
CPU time 4.07 seconds
Started Apr 23 01:27:04 PM PDT 24
Finished Apr 23 01:27:08 PM PDT 24
Peak memory 242172 kb
Host smart-3efcc7d1-ef4c-4c1a-8b1d-9163856c1390
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244446389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empt
y.244446389
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.3149766355
Short name T1221
Test name
Test status
Simulation time 1914186047 ps
CPU time 64.83 seconds
Started Apr 23 01:27:04 PM PDT 24
Finished Apr 23 01:28:09 PM PDT 24
Peak memory 660932 kb
Host smart-d23c7139-f5b5-4384-a94c-0174c440ed44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149766355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.3149766355
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.791084038
Short name T546
Test name
Test status
Simulation time 1924523808 ps
CPU time 60.78 seconds
Started Apr 23 01:27:03 PM PDT 24
Finished Apr 23 01:28:04 PM PDT 24
Peak memory 599204 kb
Host smart-7f2fabf7-1ee7-43e9-acdf-5443c1ac1818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791084038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.791084038
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.2853227837
Short name T997
Test name
Test status
Simulation time 356067738 ps
CPU time 0.93 seconds
Started Apr 23 01:27:03 PM PDT 24
Finished Apr 23 01:27:05 PM PDT 24
Peak memory 203344 kb
Host smart-1f3b587d-4f6a-4146-b972-2dca9a5414f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853227837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.2853227837
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.4111974202
Short name T345
Test name
Test status
Simulation time 318484522 ps
CPU time 3.65 seconds
Started Apr 23 01:27:05 PM PDT 24
Finished Apr 23 01:27:09 PM PDT 24
Peak memory 203668 kb
Host smart-f63548c5-f652-4891-a257-13cdf81c4d36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111974202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.4111974202
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.2438012616
Short name T174
Test name
Test status
Simulation time 4137343593 ps
CPU time 115.21 seconds
Started Apr 23 01:27:02 PM PDT 24
Finished Apr 23 01:28:58 PM PDT 24
Peak memory 1231128 kb
Host smart-852edda9-956d-43ad-9adf-b6f08301c4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438012616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.2438012616
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.2953869360
Short name T759
Test name
Test status
Simulation time 655680338 ps
CPU time 5.08 seconds
Started Apr 23 01:27:09 PM PDT 24
Finished Apr 23 01:27:14 PM PDT 24
Peak memory 203636 kb
Host smart-eff11787-c820-4a0b-848e-4507584283de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953869360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.2953869360
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.630740480
Short name T854
Test name
Test status
Simulation time 16056864856 ps
CPU time 57 seconds
Started Apr 23 01:27:08 PM PDT 24
Finished Apr 23 01:28:06 PM PDT 24
Peak memory 331452 kb
Host smart-2f601e69-4b90-48b7-8737-59af86aa1962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630740480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.630740480
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.1836706182
Short name T1
Test name
Test status
Simulation time 31628100 ps
CPU time 0.69 seconds
Started Apr 23 01:27:03 PM PDT 24
Finished Apr 23 01:27:05 PM PDT 24
Peak memory 203308 kb
Host smart-9f4debc0-70cd-4a72-9e13-f66b0a103531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836706182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1836706182
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.3621465745
Short name T1349
Test name
Test status
Simulation time 7918114422 ps
CPU time 84.25 seconds
Started Apr 23 01:27:01 PM PDT 24
Finished Apr 23 01:28:26 PM PDT 24
Peak memory 203652 kb
Host smart-e7fc6db5-566e-44f7-8b54-87f220990f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621465745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.3621465745
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.3099736388
Short name T328
Test name
Test status
Simulation time 5107649800 ps
CPU time 21.84 seconds
Started Apr 23 01:27:01 PM PDT 24
Finished Apr 23 01:27:24 PM PDT 24
Peak memory 273040 kb
Host smart-1263efae-feab-4449-8b2d-16b4161cf054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099736388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.3099736388
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.262059450
Short name T286
Test name
Test status
Simulation time 321266198 ps
CPU time 15.09 seconds
Started Apr 23 01:27:04 PM PDT 24
Finished Apr 23 01:27:20 PM PDT 24
Peak memory 211920 kb
Host smart-c5702928-43f0-4d92-ab65-e65e82f996d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262059450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.262059450
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.568481620
Short name T1319
Test name
Test status
Simulation time 1258239180 ps
CPU time 5.19 seconds
Started Apr 23 01:27:08 PM PDT 24
Finished Apr 23 01:27:13 PM PDT 24
Peak memory 211948 kb
Host smart-5e6b4253-1f17-4f68-8da1-5ff625a5de5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568481620 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.568481620
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.882288973
Short name T1053
Test name
Test status
Simulation time 10549039141 ps
CPU time 13.67 seconds
Started Apr 23 01:27:08 PM PDT 24
Finished Apr 23 01:27:22 PM PDT 24
Peak memory 249936 kb
Host smart-76277df4-d205-429b-8a32-60fbbfe0985f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882288973 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_acq.882288973
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.1632211645
Short name T436
Test name
Test status
Simulation time 10048930270 ps
CPU time 75.55 seconds
Started Apr 23 01:27:07 PM PDT 24
Finished Apr 23 01:28:23 PM PDT 24
Peak memory 472100 kb
Host smart-98311401-9159-4acf-b4e3-297a642ba295
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632211645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.1632211645
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.488756163
Short name T651
Test name
Test status
Simulation time 477471298 ps
CPU time 2.82 seconds
Started Apr 23 01:27:05 PM PDT 24
Finished Apr 23 01:27:08 PM PDT 24
Peak memory 203684 kb
Host smart-6abc8c24-1833-418e-a392-a41451207a8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488756163 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.i2c_target_hrst.488756163
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.1888659304
Short name T253
Test name
Test status
Simulation time 2432743064 ps
CPU time 4.02 seconds
Started Apr 23 01:27:07 PM PDT 24
Finished Apr 23 01:27:12 PM PDT 24
Peak memory 203780 kb
Host smart-57b18baa-c297-45e2-b54c-26d6ea2a703c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888659304 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.1888659304
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.2772517139
Short name T295
Test name
Test status
Simulation time 12520552578 ps
CPU time 89.06 seconds
Started Apr 23 01:27:08 PM PDT 24
Finished Apr 23 01:28:38 PM PDT 24
Peak memory 1445972 kb
Host smart-52d72bca-48d6-4c82-9e7d-449fef94363b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772517139 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.2772517139
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.1310859082
Short name T737
Test name
Test status
Simulation time 1089793759 ps
CPU time 16.21 seconds
Started Apr 23 01:27:02 PM PDT 24
Finished Apr 23 01:27:19 PM PDT 24
Peak memory 203744 kb
Host smart-9008e277-c1cb-4add-9e44-1954026ae536
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310859082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.1310859082
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.396892126
Short name T420
Test name
Test status
Simulation time 3338667215 ps
CPU time 35.85 seconds
Started Apr 23 01:27:01 PM PDT 24
Finished Apr 23 01:27:38 PM PDT 24
Peak memory 203664 kb
Host smart-2ebfa1e6-bb95-48b0-8ec5-b2f4543a686a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396892126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_rd.396892126
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.3186220835
Short name T432
Test name
Test status
Simulation time 22691246403 ps
CPU time 13.08 seconds
Started Apr 23 01:27:02 PM PDT 24
Finished Apr 23 01:27:15 PM PDT 24
Peak memory 255256 kb
Host smart-83ee4ea6-7f06-480b-a0d0-05129cb8f363
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186220835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.3186220835
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.1916233480
Short name T290
Test name
Test status
Simulation time 23277584168 ps
CPU time 1372.59 seconds
Started Apr 23 01:27:02 PM PDT 24
Finished Apr 23 01:49:56 PM PDT 24
Peak memory 2857748 kb
Host smart-ff10bd8d-0ffc-4712-a26c-dc815e1f8ea9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916233480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.1916233480
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.2743778165
Short name T451
Test name
Test status
Simulation time 1396762545 ps
CPU time 7.15 seconds
Started Apr 23 01:27:07 PM PDT 24
Finished Apr 23 01:27:15 PM PDT 24
Peak memory 212164 kb
Host smart-24c25941-0949-401a-adcc-b0b2cc6b93e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743778165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.2743778165
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.3899255201
Short name T1263
Test name
Test status
Simulation time 15608743 ps
CPU time 0.61 seconds
Started Apr 23 01:27:18 PM PDT 24
Finished Apr 23 01:27:19 PM PDT 24
Peak memory 203308 kb
Host smart-2142d1ee-b6bf-484b-a4d1-bc16e0d9fd6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899255201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3899255201
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.433016761
Short name T604
Test name
Test status
Simulation time 208058863 ps
CPU time 1.33 seconds
Started Apr 23 01:27:10 PM PDT 24
Finished Apr 23 01:27:12 PM PDT 24
Peak memory 212096 kb
Host smart-4d589e38-1bec-4233-8451-a8060458b6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433016761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.433016761
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.425244580
Short name T561
Test name
Test status
Simulation time 3066401534 ps
CPU time 15.42 seconds
Started Apr 23 01:27:09 PM PDT 24
Finished Apr 23 01:27:25 PM PDT 24
Peak memory 265088 kb
Host smart-2a5f8ec5-06e5-4360-b788-e59fd71f052a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425244580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empt
y.425244580
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.365356731
Short name T894
Test name
Test status
Simulation time 3789380342 ps
CPU time 128.22 seconds
Started Apr 23 01:27:10 PM PDT 24
Finished Apr 23 01:29:19 PM PDT 24
Peak memory 657760 kb
Host smart-12341027-3a6d-487d-b0cf-5e0c5b142cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365356731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.365356731
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.2294040861
Short name T7
Test name
Test status
Simulation time 7543420459 ps
CPU time 49.04 seconds
Started Apr 23 01:27:11 PM PDT 24
Finished Apr 23 01:28:01 PM PDT 24
Peak memory 562036 kb
Host smart-d7c8b04b-5e30-408d-a59b-977b69cf917d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294040861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2294040861
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.2088474138
Short name T1271
Test name
Test status
Simulation time 607970244 ps
CPU time 0.99 seconds
Started Apr 23 01:27:11 PM PDT 24
Finished Apr 23 01:27:13 PM PDT 24
Peak memory 203652 kb
Host smart-65a7d511-a400-4f48-96a6-9f8ce7b30b9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088474138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.2088474138
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.2684134291
Short name T1170
Test name
Test status
Simulation time 346980097 ps
CPU time 4.23 seconds
Started Apr 23 01:27:09 PM PDT 24
Finished Apr 23 01:27:14 PM PDT 24
Peak memory 203620 kb
Host smart-612b57a5-9a46-4b50-ae58-bbc86d55fbcd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684134291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.2684134291
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.2203532556
Short name T1210
Test name
Test status
Simulation time 4347201390 ps
CPU time 127.9 seconds
Started Apr 23 01:27:09 PM PDT 24
Finished Apr 23 01:29:18 PM PDT 24
Peak memory 1186924 kb
Host smart-b006fc3a-a792-4f7c-bfc0-570ff3201cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203532556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.2203532556
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.3327084478
Short name T957
Test name
Test status
Simulation time 657708022 ps
CPU time 6.35 seconds
Started Apr 23 01:27:12 PM PDT 24
Finished Apr 23 01:27:19 PM PDT 24
Peak memory 203740 kb
Host smart-1a953137-15dc-4601-a7b0-c88c76e1e89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327084478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.3327084478
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.1318004480
Short name T712
Test name
Test status
Simulation time 1672195403 ps
CPU time 26.17 seconds
Started Apr 23 01:27:17 PM PDT 24
Finished Apr 23 01:27:44 PM PDT 24
Peak memory 316728 kb
Host smart-fffb1b8d-3057-4afd-a418-8a0ca8d24f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318004480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.1318004480
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.2395419778
Short name T516
Test name
Test status
Simulation time 27813955 ps
CPU time 0.7 seconds
Started Apr 23 01:27:15 PM PDT 24
Finished Apr 23 01:27:16 PM PDT 24
Peak memory 203320 kb
Host smart-dc6b7651-63d4-4c8d-ab86-3d0ef53b8a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395419778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.2395419778
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.1122345274
Short name T377
Test name
Test status
Simulation time 7081963944 ps
CPU time 297.91 seconds
Started Apr 23 01:27:09 PM PDT 24
Finished Apr 23 01:32:07 PM PDT 24
Peak memory 228284 kb
Host smart-49c80d64-57f0-4225-961d-6bf90bb88a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122345274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.1122345274
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.197391309
Short name T831
Test name
Test status
Simulation time 1528636197 ps
CPU time 27.97 seconds
Started Apr 23 01:27:10 PM PDT 24
Finished Apr 23 01:27:39 PM PDT 24
Peak memory 319176 kb
Host smart-fa3951b4-6649-4f76-a161-2e38520a53c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197391309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.197391309
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.226866908
Short name T169
Test name
Test status
Simulation time 15123845383 ps
CPU time 189.13 seconds
Started Apr 23 01:27:10 PM PDT 24
Finished Apr 23 01:30:20 PM PDT 24
Peak memory 1248732 kb
Host smart-cee2ff64-1725-429d-ac36-914f20f84ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226866908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.226866908
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.2466122964
Short name T237
Test name
Test status
Simulation time 1466621452 ps
CPU time 34.89 seconds
Started Apr 23 01:27:09 PM PDT 24
Finished Apr 23 01:27:45 PM PDT 24
Peak memory 211900 kb
Host smart-35048c40-41e9-45dc-b9cd-ba10a1595e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466122964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.2466122964
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.1960236445
Short name T96
Test name
Test status
Simulation time 800830076 ps
CPU time 3.44 seconds
Started Apr 23 01:27:12 PM PDT 24
Finished Apr 23 01:27:16 PM PDT 24
Peak memory 203840 kb
Host smart-e02a0d34-388e-4509-a575-c9b6f38b01d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960236445 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1960236445
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2091999405
Short name T400
Test name
Test status
Simulation time 10113604141 ps
CPU time 26.5 seconds
Started Apr 23 01:27:12 PM PDT 24
Finished Apr 23 01:27:39 PM PDT 24
Peak memory 330164 kb
Host smart-4dc6fcb4-fc8a-47b9-a585-3a7637dd5b24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091999405 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.2091999405
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.337182455
Short name T106
Test name
Test status
Simulation time 10049693382 ps
CPU time 80.38 seconds
Started Apr 23 01:27:13 PM PDT 24
Finished Apr 23 01:28:34 PM PDT 24
Peak memory 469944 kb
Host smart-10b5f08f-2180-428a-ab47-fef559c7fda5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337182455 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_fifo_reset_tx.337182455
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.700037096
Short name T1111
Test name
Test status
Simulation time 1032508004 ps
CPU time 3 seconds
Started Apr 23 01:27:17 PM PDT 24
Finished Apr 23 01:27:20 PM PDT 24
Peak memory 203712 kb
Host smart-8ed70ece-ecdf-43a6-8ba0-daba2004e78a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700037096 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.i2c_target_hrst.700037096
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.1648215909
Short name T1010
Test name
Test status
Simulation time 1927547059 ps
CPU time 3.18 seconds
Started Apr 23 01:27:13 PM PDT 24
Finished Apr 23 01:27:17 PM PDT 24
Peak memory 203660 kb
Host smart-1919743d-6ce8-4695-a006-83a2cfc1468c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648215909 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.1648215909
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.2351338107
Short name T629
Test name
Test status
Simulation time 11125039542 ps
CPU time 64.08 seconds
Started Apr 23 01:27:14 PM PDT 24
Finished Apr 23 01:28:19 PM PDT 24
Peak memory 1080204 kb
Host smart-c0de44ff-3f7c-484f-8cd0-5535582274fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351338107 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.2351338107
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.3704337666
Short name T1359
Test name
Test status
Simulation time 946384886 ps
CPU time 12.36 seconds
Started Apr 23 01:27:10 PM PDT 24
Finished Apr 23 01:27:23 PM PDT 24
Peak memory 203648 kb
Host smart-149249cc-9743-4034-95fe-73a2c2c84037
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704337666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.3704337666
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.1936686379
Short name T102
Test name
Test status
Simulation time 759089211 ps
CPU time 4.1 seconds
Started Apr 23 01:27:14 PM PDT 24
Finished Apr 23 01:27:19 PM PDT 24
Peak memory 203772 kb
Host smart-e0d5c1f6-9244-4896-b6a0-9511b8f843f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936686379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.1936686379
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.2576208375
Short name T262
Test name
Test status
Simulation time 55951271719 ps
CPU time 192.64 seconds
Started Apr 23 01:27:12 PM PDT 24
Finished Apr 23 01:30:25 PM PDT 24
Peak memory 2207756 kb
Host smart-493d87b1-852e-4a64-b9fd-f95b3b91ef3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576208375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.2576208375
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.1331261407
Short name T259
Test name
Test status
Simulation time 14568209077 ps
CPU time 211 seconds
Started Apr 23 01:27:11 PM PDT 24
Finished Apr 23 01:30:43 PM PDT 24
Peak memory 889936 kb
Host smart-334cab6a-d341-4c05-ba43-3baa8db5339d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331261407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.1331261407
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.1443094566
Short name T1064
Test name
Test status
Simulation time 2373917627 ps
CPU time 6.33 seconds
Started Apr 23 01:27:12 PM PDT 24
Finished Apr 23 01:27:19 PM PDT 24
Peak memory 208968 kb
Host smart-9f2ad011-d0f6-4ed4-a0d3-fc8795a311a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443094566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.1443094566
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.366036005
Short name T404
Test name
Test status
Simulation time 26116781 ps
CPU time 0.65 seconds
Started Apr 23 01:21:58 PM PDT 24
Finished Apr 23 01:21:59 PM PDT 24
Peak memory 203256 kb
Host smart-235f9728-4391-40ab-8809-565e49478eee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366036005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.366036005
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.4258140588
Short name T729
Test name
Test status
Simulation time 1603844339 ps
CPU time 1.88 seconds
Started Apr 23 01:21:47 PM PDT 24
Finished Apr 23 01:21:49 PM PDT 24
Peak memory 211904 kb
Host smart-da993d7e-b9bd-41f3-98f3-098e91af95ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258140588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.4258140588
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.3481107341
Short name T1176
Test name
Test status
Simulation time 1449771814 ps
CPU time 8.04 seconds
Started Apr 23 01:21:46 PM PDT 24
Finished Apr 23 01:21:55 PM PDT 24
Peak memory 279064 kb
Host smart-53cca5f1-5abe-42b1-b954-0c046ea1491e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481107341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.3481107341
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.1754736931
Short name T408
Test name
Test status
Simulation time 2135946457 ps
CPU time 140.88 seconds
Started Apr 23 01:21:45 PM PDT 24
Finished Apr 23 01:24:06 PM PDT 24
Peak memory 598820 kb
Host smart-88cd472b-67c8-469b-b0b3-e253f4a8f23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754736931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.1754736931
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.1878005333
Short name T955
Test name
Test status
Simulation time 2210990113 ps
CPU time 153.86 seconds
Started Apr 23 01:21:45 PM PDT 24
Finished Apr 23 01:24:20 PM PDT 24
Peak memory 654036 kb
Host smart-0524c5c6-bb8b-49c9-8fe1-58587b7559c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878005333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.1878005333
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.4224716891
Short name T375
Test name
Test status
Simulation time 480183543 ps
CPU time 1 seconds
Started Apr 23 01:21:48 PM PDT 24
Finished Apr 23 01:21:50 PM PDT 24
Peak memory 203372 kb
Host smart-f8ef2129-4422-485d-9aa5-33f8ec5bf6ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224716891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.4224716891
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.3717845218
Short name T202
Test name
Test status
Simulation time 119888547 ps
CPU time 3.54 seconds
Started Apr 23 01:21:48 PM PDT 24
Finished Apr 23 01:21:52 PM PDT 24
Peak memory 222048 kb
Host smart-6eec4667-762e-4181-9f9a-c9ccd1eb96c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717845218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
3717845218
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.2615336851
Short name T45
Test name
Test status
Simulation time 4869218063 ps
CPU time 151.69 seconds
Started Apr 23 01:21:47 PM PDT 24
Finished Apr 23 01:24:20 PM PDT 24
Peak memory 785304 kb
Host smart-20a83ede-88e0-4c6f-aa3e-f7e22dbc8006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615336851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.2615336851
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.1946708754
Short name T210
Test name
Test status
Simulation time 810136926 ps
CPU time 5.15 seconds
Started Apr 23 01:22:00 PM PDT 24
Finished Apr 23 01:22:06 PM PDT 24
Peak memory 203680 kb
Host smart-8da3563e-3eae-41ee-b8a4-d3b7f9cf45c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946708754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.1946708754
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.642592235
Short name T1094
Test name
Test status
Simulation time 12097039998 ps
CPU time 62.69 seconds
Started Apr 23 01:21:55 PM PDT 24
Finished Apr 23 01:22:58 PM PDT 24
Peak memory 374844 kb
Host smart-b14a9835-24fb-4f64-8427-80318fdba4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642592235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.642592235
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.914654397
Short name T791
Test name
Test status
Simulation time 16304634 ps
CPU time 0.67 seconds
Started Apr 23 01:21:48 PM PDT 24
Finished Apr 23 01:21:49 PM PDT 24
Peak memory 203316 kb
Host smart-219fcde4-f2d1-4ff6-8add-6a594b36f461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914654397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.914654397
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.284614385
Short name T922
Test name
Test status
Simulation time 56345682641 ps
CPU time 535.86 seconds
Started Apr 23 01:21:46 PM PDT 24
Finished Apr 23 01:30:43 PM PDT 24
Peak memory 1712744 kb
Host smart-9ebcabbf-979e-4d95-bd7e-7078ae523775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284614385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.284614385
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.526374442
Short name T824
Test name
Test status
Simulation time 3096900392 ps
CPU time 37.26 seconds
Started Apr 23 01:21:47 PM PDT 24
Finished Apr 23 01:22:25 PM PDT 24
Peak memory 294192 kb
Host smart-d698a3a2-bbbf-4eb3-845a-e26e34da67e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526374442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.526374442
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.2464725139
Short name T48
Test name
Test status
Simulation time 7202362751 ps
CPU time 332.59 seconds
Started Apr 23 01:21:45 PM PDT 24
Finished Apr 23 01:27:18 PM PDT 24
Peak memory 1575460 kb
Host smart-6bcf18c4-38cc-4db8-b549-86c013c6f7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464725139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.2464725139
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.123745663
Short name T1290
Test name
Test status
Simulation time 652589059 ps
CPU time 9.88 seconds
Started Apr 23 01:21:54 PM PDT 24
Finished Apr 23 01:22:04 PM PDT 24
Peak memory 219952 kb
Host smart-a76f5535-c5bc-4586-908a-e3f47bd6d694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123745663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.123745663
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.3703839769
Short name T61
Test name
Test status
Simulation time 84680717 ps
CPU time 0.91 seconds
Started Apr 23 01:21:58 PM PDT 24
Finished Apr 23 01:21:59 PM PDT 24
Peak memory 222060 kb
Host smart-f7e80e46-69bc-4776-b20a-f81f3eb64076
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703839769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.3703839769
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.991135748
Short name T935
Test name
Test status
Simulation time 1189410831 ps
CPU time 3.16 seconds
Started Apr 23 01:21:52 PM PDT 24
Finished Apr 23 01:21:55 PM PDT 24
Peak memory 203716 kb
Host smart-9b2a5613-38d6-4255-ae5c-85e4db878e3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991135748 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.991135748
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3965941806
Short name T501
Test name
Test status
Simulation time 10103841342 ps
CPU time 31.14 seconds
Started Apr 23 01:21:51 PM PDT 24
Finished Apr 23 01:22:23 PM PDT 24
Peak memory 352384 kb
Host smart-ad016788-e60e-4a75-9c27-8bb70bfc62a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965941806 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.3965941806
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.3534944551
Short name T110
Test name
Test status
Simulation time 10246183377 ps
CPU time 5.11 seconds
Started Apr 23 01:21:51 PM PDT 24
Finished Apr 23 01:21:57 PM PDT 24
Peak memory 229116 kb
Host smart-3e2e751a-4483-4b26-8818-f270c5d56111
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534944551 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.3534944551
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.4222909694
Short name T261
Test name
Test status
Simulation time 326744156 ps
CPU time 2.1 seconds
Started Apr 23 01:21:49 PM PDT 24
Finished Apr 23 01:21:52 PM PDT 24
Peak memory 203644 kb
Host smart-0039b7b5-58b1-49b0-9fd6-c31bf899083b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222909694 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.4222909694
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.1562670715
Short name T511
Test name
Test status
Simulation time 4095669005 ps
CPU time 5.57 seconds
Started Apr 23 01:21:52 PM PDT 24
Finished Apr 23 01:21:58 PM PDT 24
Peak memory 219428 kb
Host smart-c34172ef-d499-4fc7-b451-12ef37322eac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562670715 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.1562670715
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.4060356899
Short name T1147
Test name
Test status
Simulation time 17923320090 ps
CPU time 220.65 seconds
Started Apr 23 01:21:49 PM PDT 24
Finished Apr 23 01:25:30 PM PDT 24
Peak memory 2822132 kb
Host smart-b2998c37-a78f-44a8-8c42-d5304ab7e289
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060356899 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.4060356899
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.920628174
Short name T588
Test name
Test status
Simulation time 7125449741 ps
CPU time 13.05 seconds
Started Apr 23 01:21:48 PM PDT 24
Finished Apr 23 01:22:02 PM PDT 24
Peak memory 203704 kb
Host smart-cd71782e-0f6c-4120-9abe-2bbaf86a123f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920628174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_targ
et_smoke.920628174
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.1325016358
Short name T534
Test name
Test status
Simulation time 224410003 ps
CPU time 9.43 seconds
Started Apr 23 01:21:46 PM PDT 24
Finished Apr 23 01:21:56 PM PDT 24
Peak memory 203648 kb
Host smart-8fdb6422-15b1-4239-9b8b-e1381c6b869b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325016358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.1325016358
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2160128397
Short name T769
Test name
Test status
Simulation time 52030689790 ps
CPU time 164.97 seconds
Started Apr 23 01:21:47 PM PDT 24
Finished Apr 23 01:24:33 PM PDT 24
Peak memory 2071892 kb
Host smart-dc14c854-b6e0-460d-9d2a-4befd1839a7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160128397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2160128397
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.2845874116
Short name T1009
Test name
Test status
Simulation time 13464447450 ps
CPU time 6.72 seconds
Started Apr 23 01:21:53 PM PDT 24
Finished Apr 23 01:22:00 PM PDT 24
Peak memory 203824 kb
Host smart-b5e4f165-517b-4d5c-a6d4-ff25bd5d41c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845874116 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.2845874116
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.3277166345
Short name T418
Test name
Test status
Simulation time 22679184 ps
CPU time 0.63 seconds
Started Apr 23 01:27:23 PM PDT 24
Finished Apr 23 01:27:24 PM PDT 24
Peak memory 203308 kb
Host smart-497e818c-0909-4550-b7a2-2b74f6f93674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277166345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.3277166345
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.1734299004
Short name T216
Test name
Test status
Simulation time 118949878 ps
CPU time 1.66 seconds
Started Apr 23 01:27:20 PM PDT 24
Finished Apr 23 01:27:22 PM PDT 24
Peak memory 215552 kb
Host smart-b2ab0916-4045-496d-88b3-d79eb1423e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734299004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.1734299004
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.1578943632
Short name T755
Test name
Test status
Simulation time 398554398 ps
CPU time 19.11 seconds
Started Apr 23 01:27:16 PM PDT 24
Finished Apr 23 01:27:36 PM PDT 24
Peak memory 267636 kb
Host smart-e027ba62-547f-44c2-b2f3-2216eccf9f56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578943632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.1578943632
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.4138602838
Short name T777
Test name
Test status
Simulation time 1318621307 ps
CPU time 34.01 seconds
Started Apr 23 01:27:17 PM PDT 24
Finished Apr 23 01:27:51 PM PDT 24
Peak memory 349108 kb
Host smart-435727fb-ff6c-4583-9d42-372362fc3370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138602838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.4138602838
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.3708964810
Short name T114
Test name
Test status
Simulation time 2986085130 ps
CPU time 122.22 seconds
Started Apr 23 01:27:17 PM PDT 24
Finished Apr 23 01:29:20 PM PDT 24
Peak memory 596992 kb
Host smart-991308a2-beaa-48e9-bc3f-9b68938061af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708964810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.3708964810
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1365907034
Short name T841
Test name
Test status
Simulation time 184158761 ps
CPU time 4.67 seconds
Started Apr 23 01:27:18 PM PDT 24
Finished Apr 23 01:27:23 PM PDT 24
Peak memory 236248 kb
Host smart-e57ccf8b-c33f-4b72-9421-364b253c07a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365907034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1365907034
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.2973970024
Short name T401
Test name
Test status
Simulation time 3046747059 ps
CPU time 89.53 seconds
Started Apr 23 01:27:18 PM PDT 24
Finished Apr 23 01:28:48 PM PDT 24
Peak memory 958744 kb
Host smart-a1d3572e-549e-4c1b-b3ed-175270217525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973970024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.2973970024
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.2591664690
Short name T910
Test name
Test status
Simulation time 397318430 ps
CPU time 4.79 seconds
Started Apr 23 01:27:23 PM PDT 24
Finished Apr 23 01:27:28 PM PDT 24
Peak memory 203744 kb
Host smart-655f6cd6-a36f-44c0-b152-1ca93b4df0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591664690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.2591664690
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.2929170588
Short name T571
Test name
Test status
Simulation time 2748919330 ps
CPU time 34.72 seconds
Started Apr 23 01:27:22 PM PDT 24
Finished Apr 23 01:27:58 PM PDT 24
Peak memory 375384 kb
Host smart-28799b9a-416a-4e7f-b062-4b720fb65949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929170588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.2929170588
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.3868243308
Short name T188
Test name
Test status
Simulation time 33063572 ps
CPU time 0.69 seconds
Started Apr 23 01:27:19 PM PDT 24
Finished Apr 23 01:27:20 PM PDT 24
Peak memory 203336 kb
Host smart-88ef90b0-8b4c-4123-83f3-d3cbb246fc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868243308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3868243308
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.590755516
Short name T321
Test name
Test status
Simulation time 12487109093 ps
CPU time 177.09 seconds
Started Apr 23 01:27:15 PM PDT 24
Finished Apr 23 01:30:13 PM PDT 24
Peak memory 203800 kb
Host smart-5297b8fe-005c-49ed-bce8-b09595aa181d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590755516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.590755516
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.2833946958
Short name T730
Test name
Test status
Simulation time 3427692796 ps
CPU time 36.62 seconds
Started Apr 23 01:27:16 PM PDT 24
Finished Apr 23 01:27:54 PM PDT 24
Peak memory 381400 kb
Host smart-c3910cbe-bb9b-45ef-b697-bac7138d3327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833946958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2833946958
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.2875583549
Short name T167
Test name
Test status
Simulation time 36290062800 ps
CPU time 948.96 seconds
Started Apr 23 01:27:21 PM PDT 24
Finished Apr 23 01:43:11 PM PDT 24
Peak memory 1211928 kb
Host smart-ffb339d2-fc01-4855-b9f0-ae9baaae249c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875583549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.2875583549
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.2605330769
Short name T293
Test name
Test status
Simulation time 699287427 ps
CPU time 32.74 seconds
Started Apr 23 01:27:22 PM PDT 24
Finished Apr 23 01:27:55 PM PDT 24
Peak memory 211924 kb
Host smart-708757f7-3e53-452a-886b-680c448f044c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605330769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.2605330769
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.2548557237
Short name T1304
Test name
Test status
Simulation time 759515513 ps
CPU time 2.1 seconds
Started Apr 23 01:27:23 PM PDT 24
Finished Apr 23 01:27:26 PM PDT 24
Peak memory 203732 kb
Host smart-8af584d2-6dd3-42e2-902c-cb0dd689ad1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548557237 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.2548557237
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.1530501673
Short name T1202
Test name
Test status
Simulation time 10040172029 ps
CPU time 80.89 seconds
Started Apr 23 01:27:19 PM PDT 24
Finished Apr 23 01:28:41 PM PDT 24
Peak memory 457476 kb
Host smart-61fb63fc-bb3c-428c-8c59-a71348715185
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530501673 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.1530501673
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.3417762761
Short name T710
Test name
Test status
Simulation time 10301471835 ps
CPU time 26.78 seconds
Started Apr 23 01:27:19 PM PDT 24
Finished Apr 23 01:27:46 PM PDT 24
Peak memory 317776 kb
Host smart-546d3e12-c128-413d-83e1-15fa507c2c97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417762761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.3417762761
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.2268406989
Short name T709
Test name
Test status
Simulation time 330067785 ps
CPU time 2.09 seconds
Started Apr 23 01:27:23 PM PDT 24
Finished Apr 23 01:27:26 PM PDT 24
Peak memory 203744 kb
Host smart-274e8644-ad3c-4ad2-b825-e90b054e701f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268406989 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.2268406989
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.715205582
Short name T916
Test name
Test status
Simulation time 876861398 ps
CPU time 4 seconds
Started Apr 23 01:27:21 PM PDT 24
Finished Apr 23 01:27:26 PM PDT 24
Peak memory 203644 kb
Host smart-fa9167ed-a4f4-486a-bc69-dd52e1847a46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715205582 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_intr_smoke.715205582
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.3561932535
Short name T481
Test name
Test status
Simulation time 5687429547 ps
CPU time 12.01 seconds
Started Apr 23 01:27:21 PM PDT 24
Finished Apr 23 01:27:34 PM PDT 24
Peak memory 203820 kb
Host smart-1e272dec-9017-4328-8a59-031031d1cfb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561932535 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.3561932535
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.1211287304
Short name T739
Test name
Test status
Simulation time 1645032333 ps
CPU time 12.61 seconds
Started Apr 23 01:27:19 PM PDT 24
Finished Apr 23 01:27:33 PM PDT 24
Peak memory 203668 kb
Host smart-d84a6f0e-e865-4273-b739-9be5f6d4bbe3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211287304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.1211287304
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.3367904278
Short name T1076
Test name
Test status
Simulation time 6579934248 ps
CPU time 23.75 seconds
Started Apr 23 01:27:22 PM PDT 24
Finished Apr 23 01:27:46 PM PDT 24
Peak memory 231704 kb
Host smart-b1413129-db0a-4eea-b991-066dae5c25e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367904278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.3367904278
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.3634376859
Short name T826
Test name
Test status
Simulation time 38597128005 ps
CPU time 66.62 seconds
Started Apr 23 01:27:20 PM PDT 24
Finished Apr 23 01:28:27 PM PDT 24
Peak memory 1219928 kb
Host smart-be415dc5-362b-4b0f-9380-1a2ebaa7dc64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634376859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.3634376859
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1837985808
Short name T638
Test name
Test status
Simulation time 18792256014 ps
CPU time 853.57 seconds
Started Apr 23 01:27:19 PM PDT 24
Finished Apr 23 01:41:33 PM PDT 24
Peak memory 4015516 kb
Host smart-054a32fd-47c3-4d64-8623-9678f13db476
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837985808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1837985808
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.548348599
Short name T12
Test name
Test status
Simulation time 1952000115 ps
CPU time 6.66 seconds
Started Apr 23 01:27:22 PM PDT 24
Finished Apr 23 01:27:30 PM PDT 24
Peak memory 219360 kb
Host smart-28944bc0-be3f-4d55-ae0e-88263d0d7df0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548348599 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_timeout.548348599
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.3666839772
Short name T1001
Test name
Test status
Simulation time 22479888 ps
CPU time 0.62 seconds
Started Apr 23 01:27:31 PM PDT 24
Finished Apr 23 01:27:33 PM PDT 24
Peak memory 203324 kb
Host smart-e2f5616a-8b41-4d48-bf3f-85f8b3c4e120
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666839772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3666839772
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.1246489060
Short name T270
Test name
Test status
Simulation time 91829091 ps
CPU time 1.46 seconds
Started Apr 23 01:27:38 PM PDT 24
Finished Apr 23 01:27:40 PM PDT 24
Peak memory 212160 kb
Host smart-fd0342c4-2aac-4c1d-a63a-473b307fc6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246489060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.1246489060
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.1561576910
Short name T808
Test name
Test status
Simulation time 355605797 ps
CPU time 3.09 seconds
Started Apr 23 01:27:27 PM PDT 24
Finished Apr 23 01:27:31 PM PDT 24
Peak memory 223976 kb
Host smart-e8684999-74ac-4257-a0ea-97b81c607359
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561576910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.1561576910
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.4140944160
Short name T976
Test name
Test status
Simulation time 4397404666 ps
CPU time 79.59 seconds
Started Apr 23 01:27:27 PM PDT 24
Finished Apr 23 01:28:47 PM PDT 24
Peak memory 719596 kb
Host smart-80f0abe8-f1e4-4a54-98f3-8d4b3458a606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140944160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.4140944160
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.2691383451
Short name T646
Test name
Test status
Simulation time 4108137565 ps
CPU time 73.33 seconds
Started Apr 23 01:27:28 PM PDT 24
Finished Apr 23 01:28:42 PM PDT 24
Peak memory 713784 kb
Host smart-8166b486-9e6a-40ca-a25c-3079e18f504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691383451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.2691383451
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.4002671180
Short name T365
Test name
Test status
Simulation time 101889576 ps
CPU time 0.95 seconds
Started Apr 23 01:27:22 PM PDT 24
Finished Apr 23 01:27:24 PM PDT 24
Peak memory 203464 kb
Host smart-3d85b45f-2d8a-4c33-b063-2b6bc52ea13e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002671180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.4002671180
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.965353866
Short name T1223
Test name
Test status
Simulation time 453743296 ps
CPU time 5.82 seconds
Started Apr 23 01:27:27 PM PDT 24
Finished Apr 23 01:27:33 PM PDT 24
Peak memory 203724 kb
Host smart-008bb975-8018-40c0-98a6-74be45e71ccd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965353866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.
965353866
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.156772812
Short name T661
Test name
Test status
Simulation time 7868703340 ps
CPU time 324.33 seconds
Started Apr 23 01:27:22 PM PDT 24
Finished Apr 23 01:32:47 PM PDT 24
Peak memory 1220696 kb
Host smart-1dfabe34-26de-4d0f-a03d-53b0f98b74d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156772812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.156772812
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.3941468401
Short name T1254
Test name
Test status
Simulation time 605918679 ps
CPU time 10.15 seconds
Started Apr 23 01:27:32 PM PDT 24
Finished Apr 23 01:27:43 PM PDT 24
Peak memory 203712 kb
Host smart-dd3167c0-7780-436b-b730-8243aed4793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941468401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.3941468401
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.877827862
Short name T1360
Test name
Test status
Simulation time 5900877431 ps
CPU time 24.43 seconds
Started Apr 23 01:27:34 PM PDT 24
Finished Apr 23 01:27:59 PM PDT 24
Peak memory 309980 kb
Host smart-34315e60-271f-4a4e-8e85-17808716ec17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877827862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.877827862
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.1239719834
Short name T1100
Test name
Test status
Simulation time 38274650 ps
CPU time 0.64 seconds
Started Apr 23 01:27:23 PM PDT 24
Finished Apr 23 01:27:25 PM PDT 24
Peak memory 203268 kb
Host smart-fa880e63-b61a-4cfa-99ce-fe15bc5e88af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239719834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.1239719834
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.3745896897
Short name T598
Test name
Test status
Simulation time 5869706277 ps
CPU time 20.04 seconds
Started Apr 23 01:27:30 PM PDT 24
Finished Apr 23 01:27:51 PM PDT 24
Peak memory 220100 kb
Host smart-9d5cf17f-9182-4d0a-94f2-bf6d70112eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745896897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.3745896897
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.3385713704
Short name T279
Test name
Test status
Simulation time 6833593142 ps
CPU time 38.07 seconds
Started Apr 23 01:27:23 PM PDT 24
Finished Apr 23 01:28:02 PM PDT 24
Peak memory 349540 kb
Host smart-1ef71844-0b9f-4505-a4e2-3d6657bb7725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385713704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.3385713704
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.2301729920
Short name T676
Test name
Test status
Simulation time 9923141387 ps
CPU time 862.72 seconds
Started Apr 23 01:27:29 PM PDT 24
Finished Apr 23 01:41:52 PM PDT 24
Peak memory 1565832 kb
Host smart-c20c7dc8-7315-4dc9-a49d-ba5a46ec2221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301729920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.2301729920
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.3515883853
Short name T812
Test name
Test status
Simulation time 1158680639 ps
CPU time 26.85 seconds
Started Apr 23 01:27:38 PM PDT 24
Finished Apr 23 01:28:06 PM PDT 24
Peak memory 212064 kb
Host smart-7eeebef7-9b24-4504-981a-f11425a56ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515883853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3515883853
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.3576108534
Short name T19
Test name
Test status
Simulation time 2648939465 ps
CPU time 3.44 seconds
Started Apr 23 01:27:31 PM PDT 24
Finished Apr 23 01:27:35 PM PDT 24
Peak memory 203788 kb
Host smart-e3ce4fb9-2326-400d-97f1-e67105889416
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576108534 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.3576108534
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.841819526
Short name T198
Test name
Test status
Simulation time 10268922447 ps
CPU time 14.75 seconds
Started Apr 23 01:27:28 PM PDT 24
Finished Apr 23 01:27:43 PM PDT 24
Peak memory 272644 kb
Host smart-f76602b3-feb0-44dc-8b22-e92356ea1da1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841819526 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.841819526
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.766531652
Short name T403
Test name
Test status
Simulation time 10092486444 ps
CPU time 10.41 seconds
Started Apr 23 01:27:31 PM PDT 24
Finished Apr 23 01:27:42 PM PDT 24
Peak memory 243804 kb
Host smart-62c34862-4494-486f-a737-02eb2c78d36d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766531652 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_fifo_reset_tx.766531652
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.2524896572
Short name T810
Test name
Test status
Simulation time 1438245287 ps
CPU time 2.44 seconds
Started Apr 23 01:27:31 PM PDT 24
Finished Apr 23 01:27:34 PM PDT 24
Peak memory 203676 kb
Host smart-fec6dcb5-de8a-48ed-97c7-2d932b8d5e93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524896572 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.2524896572
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.4089638810
Short name T271
Test name
Test status
Simulation time 11161620253 ps
CPU time 5.9 seconds
Started Apr 23 01:27:29 PM PDT 24
Finished Apr 23 01:27:36 PM PDT 24
Peak memory 220064 kb
Host smart-6c520efb-6aed-4b03-ad72-3617b6acfc13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089638810 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.4089638810
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.391677676
Short name T847
Test name
Test status
Simulation time 22322170825 ps
CPU time 66.91 seconds
Started Apr 23 01:27:28 PM PDT 24
Finished Apr 23 01:28:35 PM PDT 24
Peak memory 1311696 kb
Host smart-98bb558a-3616-44b4-b13a-3ac947bd2e12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391677676 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.391677676
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.2808908257
Short name T1160
Test name
Test status
Simulation time 3931151413 ps
CPU time 17.14 seconds
Started Apr 23 01:27:30 PM PDT 24
Finished Apr 23 01:27:48 PM PDT 24
Peak memory 203512 kb
Host smart-3850bb25-5514-47ea-8cf9-cc82bd03645a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808908257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.2808908257
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.3137243948
Short name T745
Test name
Test status
Simulation time 15386345792 ps
CPU time 75.01 seconds
Started Apr 23 01:27:27 PM PDT 24
Finished Apr 23 01:28:42 PM PDT 24
Peak memory 209028 kb
Host smart-9185508f-4e6a-4c5f-8825-9a40b21283c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137243948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.3137243948
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.2548829399
Short name T990
Test name
Test status
Simulation time 21168007073 ps
CPU time 42.6 seconds
Started Apr 23 01:27:26 PM PDT 24
Finished Apr 23 01:28:09 PM PDT 24
Peak memory 448292 kb
Host smart-fcd05dc9-1c2e-4b71-88f1-b4606a8d7b26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548829399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.2548829399
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.2974614648
Short name T508
Test name
Test status
Simulation time 26701768138 ps
CPU time 537.78 seconds
Started Apr 23 01:27:28 PM PDT 24
Finished Apr 23 01:36:26 PM PDT 24
Peak memory 2870152 kb
Host smart-2a62cdb3-bce6-4a5d-b90b-dd363fcc9bfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974614648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.2974614648
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.4271900963
Short name T589
Test name
Test status
Simulation time 2607263272 ps
CPU time 7.32 seconds
Started Apr 23 01:27:38 PM PDT 24
Finished Apr 23 01:27:46 PM PDT 24
Peak memory 220252 kb
Host smart-0f3a0350-f749-47b9-8ad3-077e2823c1fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271900963 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.4271900963
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_unexp_stop.1550146093
Short name T1190
Test name
Test status
Simulation time 7081517096 ps
CPU time 6.15 seconds
Started Apr 23 01:27:36 PM PDT 24
Finished Apr 23 01:27:43 PM PDT 24
Peak memory 203912 kb
Host smart-f74683af-93b1-409c-b357-84f6d5235900
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550146093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.i2c_target_unexp_stop.1550146093
Directory /workspace/41.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/42.i2c_alert_test.1530356586
Short name T1255
Test name
Test status
Simulation time 164658902 ps
CPU time 0.62 seconds
Started Apr 23 01:27:40 PM PDT 24
Finished Apr 23 01:27:41 PM PDT 24
Peak memory 203280 kb
Host smart-0ca66616-9f30-4dd1-82c2-c1684637bda4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530356586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.1530356586
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.547231528
Short name T399
Test name
Test status
Simulation time 45509285 ps
CPU time 1.31 seconds
Started Apr 23 01:27:33 PM PDT 24
Finished Apr 23 01:27:35 PM PDT 24
Peak memory 212016 kb
Host smart-90cd3bc5-c3e2-412e-9ea5-3538c21e6d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547231528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.547231528
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.162121922
Short name T927
Test name
Test status
Simulation time 370558192 ps
CPU time 19.77 seconds
Started Apr 23 01:27:33 PM PDT 24
Finished Apr 23 01:27:53 PM PDT 24
Peak memory 282424 kb
Host smart-3c342899-7631-4848-b537-c15ee14122c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162121922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt
y.162121922
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3150286539
Short name T1316
Test name
Test status
Simulation time 10441781986 ps
CPU time 44.2 seconds
Started Apr 23 01:27:35 PM PDT 24
Finished Apr 23 01:28:20 PM PDT 24
Peak memory 542236 kb
Host smart-c63e6281-113a-45e2-afc3-86b5a0551d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150286539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3150286539
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.3419256953
Short name T663
Test name
Test status
Simulation time 2420426736 ps
CPU time 37.53 seconds
Started Apr 23 01:27:30 PM PDT 24
Finished Apr 23 01:28:08 PM PDT 24
Peak memory 496408 kb
Host smart-d6e99256-8f3e-48fd-bdd8-5163e6a50086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419256953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.3419256953
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.1116836824
Short name T1267
Test name
Test status
Simulation time 337947732 ps
CPU time 0.92 seconds
Started Apr 23 01:27:40 PM PDT 24
Finished Apr 23 01:27:41 PM PDT 24
Peak memory 203548 kb
Host smart-42693a45-8ca7-4572-9149-e40a0e979583
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116836824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.1116836824
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3864048448
Short name T948
Test name
Test status
Simulation time 640978769 ps
CPU time 8.52 seconds
Started Apr 23 01:27:31 PM PDT 24
Finished Apr 23 01:27:40 PM PDT 24
Peak memory 203688 kb
Host smart-b3530622-a8a4-4e77-af6a-c520e8d4a3cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864048448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.3864048448
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.3529414149
Short name T337
Test name
Test status
Simulation time 13976437214 ps
CPU time 233.67 seconds
Started Apr 23 01:27:31 PM PDT 24
Finished Apr 23 01:31:26 PM PDT 24
Peak memory 931608 kb
Host smart-ed4865c1-3199-4968-a9f4-8cae5774020a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529414149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3529414149
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.2307898159
Short name T1046
Test name
Test status
Simulation time 390421490 ps
CPU time 3.29 seconds
Started Apr 23 01:27:36 PM PDT 24
Finished Apr 23 01:27:40 PM PDT 24
Peak memory 203644 kb
Host smart-9d9e1011-7d99-4495-86b2-74f275370e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307898159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.2307898159
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.3057085364
Short name T827
Test name
Test status
Simulation time 4211472219 ps
CPU time 50.74 seconds
Started Apr 23 01:27:39 PM PDT 24
Finished Apr 23 01:28:31 PM PDT 24
Peak memory 300140 kb
Host smart-b94b495e-ba32-4ce4-a688-d4d7401c6a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057085364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.3057085364
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.2931415657
Short name T723
Test name
Test status
Simulation time 115234944 ps
CPU time 0.7 seconds
Started Apr 23 01:27:30 PM PDT 24
Finished Apr 23 01:27:31 PM PDT 24
Peak memory 203352 kb
Host smart-10f40962-8d7e-4166-862e-294a9bc8a8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931415657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2931415657
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.2740231012
Short name T1179
Test name
Test status
Simulation time 6607280721 ps
CPU time 85.61 seconds
Started Apr 23 01:27:34 PM PDT 24
Finished Apr 23 01:29:01 PM PDT 24
Peak memory 211936 kb
Host smart-3d6b14f8-282d-4e90-9035-512e54a37806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740231012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2740231012
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.3518454642
Short name T1342
Test name
Test status
Simulation time 3063721312 ps
CPU time 32.07 seconds
Started Apr 23 01:27:30 PM PDT 24
Finished Apr 23 01:28:03 PM PDT 24
Peak memory 363812 kb
Host smart-f21fa965-defd-4a9b-8ff4-6a4cc82ea573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518454642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.3518454642
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.3727982846
Short name T803
Test name
Test status
Simulation time 91661428900 ps
CPU time 1809.69 seconds
Started Apr 23 01:27:39 PM PDT 24
Finished Apr 23 01:57:50 PM PDT 24
Peak memory 5271116 kb
Host smart-af6afc95-3bdb-4aaf-a2b7-28d4ed1e38cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727982846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.3727982846
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.4279724947
Short name T846
Test name
Test status
Simulation time 5053574993 ps
CPU time 9.71 seconds
Started Apr 23 01:27:36 PM PDT 24
Finished Apr 23 01:27:46 PM PDT 24
Peak memory 217276 kb
Host smart-8ea42fe2-094f-401d-bf75-f1d05cc803b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279724947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.4279724947
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.993669606
Short name T636
Test name
Test status
Simulation time 2091410852 ps
CPU time 2.73 seconds
Started Apr 23 01:27:34 PM PDT 24
Finished Apr 23 01:27:38 PM PDT 24
Peak memory 203768 kb
Host smart-e146f83a-a3b3-4bb0-80a1-aa9a71af33fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993669606 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.993669606
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1215417864
Short name T961
Test name
Test status
Simulation time 10252161226 ps
CPU time 30.03 seconds
Started Apr 23 01:27:34 PM PDT 24
Finished Apr 23 01:28:04 PM PDT 24
Peak memory 336600 kb
Host smart-9fa154eb-1853-408b-80f9-bd13a6556b23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215417864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1215417864
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.1788728112
Short name T619
Test name
Test status
Simulation time 10056626843 ps
CPU time 71.17 seconds
Started Apr 23 01:27:38 PM PDT 24
Finished Apr 23 01:28:50 PM PDT 24
Peak memory 528712 kb
Host smart-7bcd8e9c-dcaa-4fa0-8c38-13e9ec238cd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788728112 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.1788728112
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.1554899544
Short name T1257
Test name
Test status
Simulation time 2168717213 ps
CPU time 2.1 seconds
Started Apr 23 01:27:39 PM PDT 24
Finished Apr 23 01:27:41 PM PDT 24
Peak memory 203460 kb
Host smart-03f943de-fcab-4e8f-85f6-76f3133368ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554899544 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.1554899544
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.272102685
Short name T699
Test name
Test status
Simulation time 3328636810 ps
CPU time 4.49 seconds
Started Apr 23 01:27:36 PM PDT 24
Finished Apr 23 01:27:42 PM PDT 24
Peak memory 203744 kb
Host smart-86db79c5-2158-43df-8727-8ab0ba6f88fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272102685 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_intr_smoke.272102685
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.1117336534
Short name T972
Test name
Test status
Simulation time 16640296285 ps
CPU time 38.25 seconds
Started Apr 23 01:27:33 PM PDT 24
Finished Apr 23 01:28:12 PM PDT 24
Peak memory 926864 kb
Host smart-5cb25697-76cb-4bde-b586-3b40209d4982
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117336534 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.1117336534
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.3319879032
Short name T445
Test name
Test status
Simulation time 1449385075 ps
CPU time 27.86 seconds
Started Apr 23 01:27:35 PM PDT 24
Finished Apr 23 01:28:04 PM PDT 24
Peak memory 203672 kb
Host smart-c67f7048-492f-4bc8-a870-6b0677e20e5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319879032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.3319879032
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.960935373
Short name T326
Test name
Test status
Simulation time 298228446 ps
CPU time 12.58 seconds
Started Apr 23 01:27:33 PM PDT 24
Finished Apr 23 01:27:46 PM PDT 24
Peak memory 203652 kb
Host smart-7873b498-c13b-49fe-bde7-95d8a826453f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960935373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_rd.960935373
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.2820228393
Short name T58
Test name
Test status
Simulation time 22285019706 ps
CPU time 11.49 seconds
Started Apr 23 01:27:36 PM PDT 24
Finished Apr 23 01:27:48 PM PDT 24
Peak memory 203704 kb
Host smart-34b1d044-e46f-43bd-a423-074cae610b76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820228393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.2820228393
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.2987692820
Short name T474
Test name
Test status
Simulation time 16838654217 ps
CPU time 232.33 seconds
Started Apr 23 01:27:34 PM PDT 24
Finished Apr 23 01:31:27 PM PDT 24
Peak memory 2021812 kb
Host smart-72f17c2a-a70a-4dfe-ab4d-83c8229b5f2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987692820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.2987692820
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.2960790176
Short name T452
Test name
Test status
Simulation time 1217029870 ps
CPU time 6.22 seconds
Started Apr 23 01:27:34 PM PDT 24
Finished Apr 23 01:27:41 PM PDT 24
Peak memory 219856 kb
Host smart-d9028781-3e78-4059-8ae8-147d5d62aaf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960790176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.2960790176
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.1179077239
Short name T344
Test name
Test status
Simulation time 19027120 ps
CPU time 0.63 seconds
Started Apr 23 01:27:45 PM PDT 24
Finished Apr 23 01:27:47 PM PDT 24
Peak memory 203296 kb
Host smart-025037b4-913f-4348-bc67-ddec6d253a26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179077239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1179077239
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.1238336331
Short name T775
Test name
Test status
Simulation time 56317781 ps
CPU time 1.26 seconds
Started Apr 23 01:27:37 PM PDT 24
Finished Apr 23 01:27:39 PM PDT 24
Peak memory 211976 kb
Host smart-acf5f244-d6f1-4c79-824f-d7ea5cc3ea5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238336331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1238336331
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.4218302012
Short name T718
Test name
Test status
Simulation time 2324132999 ps
CPU time 20.33 seconds
Started Apr 23 01:27:37 PM PDT 24
Finished Apr 23 01:27:58 PM PDT 24
Peak memory 277992 kb
Host smart-adbfdcdc-66d1-40a0-be29-5c1f03daaefa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218302012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.4218302012
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.3222196547
Short name T480
Test name
Test status
Simulation time 1297801251 ps
CPU time 71.84 seconds
Started Apr 23 01:27:37 PM PDT 24
Finished Apr 23 01:28:50 PM PDT 24
Peak memory 331688 kb
Host smart-4a24cdf3-e321-49fc-9205-c6d327863b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222196547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.3222196547
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.1920963874
Short name T951
Test name
Test status
Simulation time 5141384505 ps
CPU time 40.63 seconds
Started Apr 23 01:27:39 PM PDT 24
Finished Apr 23 01:28:21 PM PDT 24
Peak memory 521824 kb
Host smart-782fe3e8-f495-4e1e-aee9-a83c3972d999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920963874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.1920963874
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.1799050934
Short name T650
Test name
Test status
Simulation time 109240387 ps
CPU time 0.96 seconds
Started Apr 23 01:27:38 PM PDT 24
Finished Apr 23 01:27:40 PM PDT 24
Peak memory 203380 kb
Host smart-7c8c2ed7-c77c-4a38-adc6-c8a68a6e8599
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799050934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.1799050934
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.1652448230
Short name T1229
Test name
Test status
Simulation time 426432192 ps
CPU time 5.14 seconds
Started Apr 23 01:27:38 PM PDT 24
Finished Apr 23 01:27:44 PM PDT 24
Peak memory 242460 kb
Host smart-b717ca0a-3b67-4f31-8679-003d5e75b126
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652448230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.1652448230
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.108979210
Short name T980
Test name
Test status
Simulation time 3804107809 ps
CPU time 113.99 seconds
Started Apr 23 01:27:39 PM PDT 24
Finished Apr 23 01:29:33 PM PDT 24
Peak memory 1150076 kb
Host smart-a32169b8-e4e3-49ac-989b-a57213818e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108979210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.108979210
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.535610578
Short name T1292
Test name
Test status
Simulation time 402125956 ps
CPU time 16.21 seconds
Started Apr 23 01:27:46 PM PDT 24
Finished Apr 23 01:28:03 PM PDT 24
Peak memory 203656 kb
Host smart-e72ab258-82ef-4d1a-b0c2-e62bcbbd68b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535610578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.535610578
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.1499465263
Short name T548
Test name
Test status
Simulation time 2699568816 ps
CPU time 58.45 seconds
Started Apr 23 01:27:44 PM PDT 24
Finished Apr 23 01:28:43 PM PDT 24
Peak memory 282380 kb
Host smart-96380dfd-8c35-473e-ad3d-9e135d5f0d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499465263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.1499465263
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.2223301199
Short name T364
Test name
Test status
Simulation time 31798706 ps
CPU time 0.68 seconds
Started Apr 23 01:27:38 PM PDT 24
Finished Apr 23 01:27:39 PM PDT 24
Peak memory 203404 kb
Host smart-0b80bda5-6590-4a44-9c46-19ea6a1e47cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223301199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.2223301199
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.4136513574
Short name T90
Test name
Test status
Simulation time 7262321501 ps
CPU time 676.39 seconds
Started Apr 23 01:27:36 PM PDT 24
Finished Apr 23 01:38:53 PM PDT 24
Peak memory 1673824 kb
Host smart-93c72739-7111-4f6d-9189-ac86f441d49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136513574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.4136513574
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.2456840241
Short name T1078
Test name
Test status
Simulation time 6738627115 ps
CPU time 28.83 seconds
Started Apr 23 01:27:41 PM PDT 24
Finished Apr 23 01:28:11 PM PDT 24
Peak memory 331692 kb
Host smart-9be2d3f4-4828-49a2-bdaf-cd140df300b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456840241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.2456840241
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.3150321355
Short name T959
Test name
Test status
Simulation time 7696547255 ps
CPU time 289.54 seconds
Started Apr 23 01:27:39 PM PDT 24
Finished Apr 23 01:32:30 PM PDT 24
Peak memory 756612 kb
Host smart-05eea841-9a26-414d-a95d-da9a813d064e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150321355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.3150321355
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.1198798018
Short name T1087
Test name
Test status
Simulation time 931652412 ps
CPU time 2.84 seconds
Started Apr 23 01:27:41 PM PDT 24
Finished Apr 23 01:27:44 PM PDT 24
Peak memory 203696 kb
Host smart-b148bc2a-b413-4003-b9b8-4f67438174c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198798018 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.1198798018
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.3411294101
Short name T563
Test name
Test status
Simulation time 10233860681 ps
CPU time 12.88 seconds
Started Apr 23 01:27:43 PM PDT 24
Finished Apr 23 01:27:56 PM PDT 24
Peak memory 253096 kb
Host smart-7b951f4f-8297-427b-bbda-f716dd15e8ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411294101 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.3411294101
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3039534961
Short name T596
Test name
Test status
Simulation time 10262573545 ps
CPU time 5.9 seconds
Started Apr 23 01:27:40 PM PDT 24
Finished Apr 23 01:27:47 PM PDT 24
Peak memory 232252 kb
Host smart-294533e2-2831-4e2d-aca8-8be4d55bc2b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039534961 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.3039534961
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.4284936318
Short name T520
Test name
Test status
Simulation time 1775604321 ps
CPU time 2.68 seconds
Started Apr 23 01:27:40 PM PDT 24
Finished Apr 23 01:27:44 PM PDT 24
Peak memory 203728 kb
Host smart-9a6605a0-02f6-4c91-9bd5-bdd37c33957a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284936318 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.4284936318
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.1946576354
Short name T463
Test name
Test status
Simulation time 5274986544 ps
CPU time 6.04 seconds
Started Apr 23 01:27:42 PM PDT 24
Finished Apr 23 01:27:49 PM PDT 24
Peak memory 212012 kb
Host smart-7e47074f-dc6d-4d4a-815f-53e93f8abd88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946576354 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.1946576354
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.2502709698
Short name T1045
Test name
Test status
Simulation time 4475742137 ps
CPU time 4.7 seconds
Started Apr 23 01:27:42 PM PDT 24
Finished Apr 23 01:27:47 PM PDT 24
Peak memory 304372 kb
Host smart-51dd6f2a-d663-46a2-bc99-739f01039a6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502709698 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2502709698
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3201778718
Short name T447
Test name
Test status
Simulation time 652304929 ps
CPU time 23.07 seconds
Started Apr 23 01:27:44 PM PDT 24
Finished Apr 23 01:28:07 PM PDT 24
Peak memory 203596 kb
Host smart-206f1395-d3a7-4290-8108-0ccd95051af7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201778718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3201778718
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.483298290
Short name T895
Test name
Test status
Simulation time 4886305541 ps
CPU time 12.13 seconds
Started Apr 23 01:27:42 PM PDT 24
Finished Apr 23 01:27:55 PM PDT 24
Peak memory 217388 kb
Host smart-4e097a69-0bc1-4677-b366-d425a4a8d1fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483298290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_rd.483298290
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.826689473
Short name T1200
Test name
Test status
Simulation time 61260349402 ps
CPU time 2177.49 seconds
Started Apr 23 01:27:42 PM PDT 24
Finished Apr 23 02:04:00 PM PDT 24
Peak memory 10572400 kb
Host smart-5015331e-49ff-4595-9052-06deeafd374b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826689473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_wr.826689473
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.902323806
Short name T1054
Test name
Test status
Simulation time 24421600499 ps
CPU time 134.7 seconds
Started Apr 23 01:27:42 PM PDT 24
Finished Apr 23 01:29:57 PM PDT 24
Peak memory 1336376 kb
Host smart-6984ea5e-21da-4cc2-be16-8a19389b7a6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902323806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_t
arget_stretch.902323806
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.1549746459
Short name T809
Test name
Test status
Simulation time 1258084003 ps
CPU time 6.63 seconds
Started Apr 23 01:27:47 PM PDT 24
Finished Apr 23 01:27:54 PM PDT 24
Peak memory 219900 kb
Host smart-22d6f704-5b6e-43dd-baf0-cbe515b142e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549746459 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.1549746459
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.1168673118
Short name T115
Test name
Test status
Simulation time 28761230 ps
CPU time 0.64 seconds
Started Apr 23 01:27:52 PM PDT 24
Finished Apr 23 01:27:54 PM PDT 24
Peak memory 203324 kb
Host smart-f3c5ed2d-90ce-4ed1-9e69-676f10180775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168673118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.1168673118
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3717315030
Short name T183
Test name
Test status
Simulation time 96541311 ps
CPU time 1.52 seconds
Started Apr 23 01:27:49 PM PDT 24
Finished Apr 23 01:27:51 PM PDT 24
Peak memory 212028 kb
Host smart-1f4f7524-3c1f-46cd-a4ac-e1b5859fff89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717315030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3717315030
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.2398085978
Short name T448
Test name
Test status
Simulation time 888804695 ps
CPU time 22.92 seconds
Started Apr 23 01:27:45 PM PDT 24
Finished Apr 23 01:28:09 PM PDT 24
Peak memory 284900 kb
Host smart-c618cf61-32ab-456d-b493-17ff86ad40e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398085978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.2398085978
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.1265972981
Short name T1143
Test name
Test status
Simulation time 10196391906 ps
CPU time 56.32 seconds
Started Apr 23 01:27:46 PM PDT 24
Finished Apr 23 01:28:43 PM PDT 24
Peak memory 556904 kb
Host smart-88214ca6-7325-4b9d-955a-df1c7db2ae6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265972981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.1265972981
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.2279908994
Short name T502
Test name
Test status
Simulation time 1496854456 ps
CPU time 99.54 seconds
Started Apr 23 01:27:46 PM PDT 24
Finished Apr 23 01:29:26 PM PDT 24
Peak memory 534352 kb
Host smart-4cdf8a44-b931-4daf-b36d-dd47a5984d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279908994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2279908994
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.1581361159
Short name T995
Test name
Test status
Simulation time 68283603 ps
CPU time 0.86 seconds
Started Apr 23 01:27:44 PM PDT 24
Finished Apr 23 01:27:46 PM PDT 24
Peak memory 203456 kb
Host smart-852da740-a52a-4e6e-978a-8d31429b3381
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581361159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.1581361159
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.755779527
Short name T1014
Test name
Test status
Simulation time 690182987 ps
CPU time 8.67 seconds
Started Apr 23 01:27:44 PM PDT 24
Finished Apr 23 01:27:54 PM PDT 24
Peak memory 203676 kb
Host smart-a24899c4-4753-4ee0-94ca-04c7ca5c20f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755779527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.
755779527
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.2178644690
Short name T170
Test name
Test status
Simulation time 13519800432 ps
CPU time 75.62 seconds
Started Apr 23 01:27:46 PM PDT 24
Finished Apr 23 01:29:02 PM PDT 24
Peak memory 916332 kb
Host smart-4db1896d-cd74-49eb-8b4d-33ddc0cc3db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178644690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2178644690
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.347224259
Short name T1132
Test name
Test status
Simulation time 466674113 ps
CPU time 19.09 seconds
Started Apr 23 01:27:52 PM PDT 24
Finished Apr 23 01:28:12 PM PDT 24
Peak memory 203668 kb
Host smart-9a02ffef-be9c-4595-afed-9789d993f999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347224259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.347224259
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.3147500528
Short name T1358
Test name
Test status
Simulation time 2299998958 ps
CPU time 17.48 seconds
Started Apr 23 01:27:53 PM PDT 24
Finished Apr 23 01:28:11 PM PDT 24
Peak memory 262312 kb
Host smart-347a3d6e-7a4f-45ae-bcab-90f2fd8be27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147500528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.3147500528
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.1472188427
Short name T1105
Test name
Test status
Simulation time 20549539 ps
CPU time 0.67 seconds
Started Apr 23 01:27:45 PM PDT 24
Finished Apr 23 01:27:46 PM PDT 24
Peak memory 203344 kb
Host smart-8edb180c-2cbf-4d4a-88de-64716658452c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472188427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.1472188427
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.2172690674
Short name T751
Test name
Test status
Simulation time 54995896968 ps
CPU time 118.03 seconds
Started Apr 23 01:27:45 PM PDT 24
Finished Apr 23 01:29:44 PM PDT 24
Peak memory 203704 kb
Host smart-7998c6a4-85a2-4040-b951-f2dc2c5e808b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172690674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2172690674
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.2326493713
Short name T449
Test name
Test status
Simulation time 1717425355 ps
CPU time 72.34 seconds
Started Apr 23 01:27:46 PM PDT 24
Finished Apr 23 01:28:59 PM PDT 24
Peak memory 358104 kb
Host smart-8a3d9295-8728-4240-9332-52a58ee862c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326493713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2326493713
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.615808854
Short name T294
Test name
Test status
Simulation time 606820410 ps
CPU time 9.15 seconds
Started Apr 23 01:27:47 PM PDT 24
Finished Apr 23 01:27:57 PM PDT 24
Peak memory 220204 kb
Host smart-e76f56fa-bba4-4980-99af-005bdbe1dd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615808854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.615808854
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3275928307
Short name T1025
Test name
Test status
Simulation time 3753404048 ps
CPU time 4.11 seconds
Started Apr 23 01:27:52 PM PDT 24
Finished Apr 23 01:27:57 PM PDT 24
Peak memory 211964 kb
Host smart-62a69968-fc21-4ad4-b7b4-97100b9ef47b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275928307 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3275928307
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.3226114365
Short name T369
Test name
Test status
Simulation time 10417419911 ps
CPU time 13.7 seconds
Started Apr 23 01:27:48 PM PDT 24
Finished Apr 23 01:28:02 PM PDT 24
Peak memory 291580 kb
Host smart-6f3d5325-564a-42ba-b5b9-c76a7f070969
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226114365 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.3226114365
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.264880646
Short name T1104
Test name
Test status
Simulation time 10037433484 ps
CPU time 76.11 seconds
Started Apr 23 01:27:46 PM PDT 24
Finished Apr 23 01:29:03 PM PDT 24
Peak memory 478276 kb
Host smart-46a49966-8988-4a58-9695-8fac6ec005e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264880646 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.i2c_target_fifo_reset_tx.264880646
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.327693836
Short name T1072
Test name
Test status
Simulation time 2026130009 ps
CPU time 1.77 seconds
Started Apr 23 01:27:52 PM PDT 24
Finished Apr 23 01:27:54 PM PDT 24
Peak memory 203720 kb
Host smart-05aa2347-ef66-40d9-ae96-7fbf35361e18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327693836 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.i2c_target_hrst.327693836
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.417773266
Short name T3
Test name
Test status
Simulation time 1308861168 ps
CPU time 3.33 seconds
Started Apr 23 01:27:47 PM PDT 24
Finished Apr 23 01:27:51 PM PDT 24
Peak memory 203740 kb
Host smart-e048d96c-a0a2-4bae-9071-de082c4a571c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417773266 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_intr_smoke.417773266
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.219333203
Short name T1264
Test name
Test status
Simulation time 6150632276 ps
CPU time 10.44 seconds
Started Apr 23 01:27:51 PM PDT 24
Finished Apr 23 01:28:02 PM PDT 24
Peak memory 477936 kb
Host smart-3059e26d-03f0-40da-a940-d8ccd336cdae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219333203 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.219333203
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.1904091094
Short name T891
Test name
Test status
Simulation time 578375352 ps
CPU time 19.33 seconds
Started Apr 23 01:27:51 PM PDT 24
Finished Apr 23 01:28:11 PM PDT 24
Peak memory 203708 kb
Host smart-58991fea-586b-46be-86b1-b3221b75be64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904091094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.1904091094
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.322885525
Short name T1006
Test name
Test status
Simulation time 4938825454 ps
CPU time 25.95 seconds
Started Apr 23 01:27:51 PM PDT 24
Finished Apr 23 01:28:17 PM PDT 24
Peak memory 224348 kb
Host smart-82f57aae-3a00-4ea5-a5c4-5bb4c823d97a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322885525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_rd.322885525
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.3138919724
Short name T999
Test name
Test status
Simulation time 37443813959 ps
CPU time 70.63 seconds
Started Apr 23 01:27:51 PM PDT 24
Finished Apr 23 01:29:03 PM PDT 24
Peak memory 1135276 kb
Host smart-db609669-234e-4809-9413-b6f1b77a27ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138919724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.3138919724
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.1341230842
Short name T1056
Test name
Test status
Simulation time 19335096044 ps
CPU time 109 seconds
Started Apr 23 01:27:51 PM PDT 24
Finished Apr 23 01:29:40 PM PDT 24
Peak memory 1236052 kb
Host smart-659bcb52-c7e2-449a-b5a5-4eceb460e3bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341230842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.1341230842
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.3820212268
Short name T590
Test name
Test status
Simulation time 14829176399 ps
CPU time 7.07 seconds
Started Apr 23 01:27:47 PM PDT 24
Finished Apr 23 01:27:55 PM PDT 24
Peak memory 220116 kb
Host smart-67d672bc-d285-4df6-b1a5-22f3063f143a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820212268 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.3820212268
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.1009591265
Short name T982
Test name
Test status
Simulation time 15827169 ps
CPU time 0.62 seconds
Started Apr 23 01:27:58 PM PDT 24
Finished Apr 23 01:27:59 PM PDT 24
Peak memory 203304 kb
Host smart-66bffc8b-b994-4004-bb05-a37eef890353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009591265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1009591265
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.3327804467
Short name T778
Test name
Test status
Simulation time 362981824 ps
CPU time 1.54 seconds
Started Apr 23 01:27:55 PM PDT 24
Finished Apr 23 01:27:57 PM PDT 24
Peak memory 211992 kb
Host smart-f40c221f-bad1-4e6e-a693-7a1dbdcdf178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327804467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3327804467
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.536173231
Short name T690
Test name
Test status
Simulation time 426040617 ps
CPU time 11.51 seconds
Started Apr 23 01:27:51 PM PDT 24
Finished Apr 23 01:28:04 PM PDT 24
Peak memory 243920 kb
Host smart-45792e50-ea92-4581-9ddb-4f2c6d78fd0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536173231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empt
y.536173231
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.2983275879
Short name T68
Test name
Test status
Simulation time 4781277223 ps
CPU time 54.82 seconds
Started Apr 23 01:27:53 PM PDT 24
Finished Apr 23 01:28:49 PM PDT 24
Peak memory 581868 kb
Host smart-e592b31a-848d-4321-9a9c-5c951cda503f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983275879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.2983275879
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.509827567
Short name T332
Test name
Test status
Simulation time 6677319389 ps
CPU time 49.62 seconds
Started Apr 23 01:27:52 PM PDT 24
Finished Apr 23 01:28:43 PM PDT 24
Peak memory 608460 kb
Host smart-74b06da5-3489-47c4-9cf2-f4137a70f03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509827567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.509827567
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.2842792142
Short name T74
Test name
Test status
Simulation time 103277398 ps
CPU time 0.89 seconds
Started Apr 23 01:27:53 PM PDT 24
Finished Apr 23 01:27:54 PM PDT 24
Peak memory 203448 kb
Host smart-5aa5d7c9-c1f3-4ba4-b698-267c038dc9fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842792142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.2842792142
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.2597189965
Short name T378
Test name
Test status
Simulation time 121288328 ps
CPU time 6.28 seconds
Started Apr 23 01:27:53 PM PDT 24
Finished Apr 23 01:28:00 PM PDT 24
Peak memory 203612 kb
Host smart-73921063-7944-49f1-8f78-a4e5ec41b37f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597189965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.2597189965
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.3484141843
Short name T657
Test name
Test status
Simulation time 3037608383 ps
CPU time 203.55 seconds
Started Apr 23 01:27:52 PM PDT 24
Finished Apr 23 01:31:16 PM PDT 24
Peak memory 877128 kb
Host smart-3b785252-9ff5-45c7-8348-45f8039fb239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484141843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.3484141843
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.3815082908
Short name T971
Test name
Test status
Simulation time 292438987 ps
CPU time 4.68 seconds
Started Apr 23 01:27:57 PM PDT 24
Finished Apr 23 01:28:02 PM PDT 24
Peak memory 203740 kb
Host smart-1a6119fc-9498-4668-90a7-ada6da36ecd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815082908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.3815082908
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.2275884508
Short name T784
Test name
Test status
Simulation time 4274182185 ps
CPU time 16.5 seconds
Started Apr 23 01:28:01 PM PDT 24
Finished Apr 23 01:28:17 PM PDT 24
Peak memory 278292 kb
Host smart-db9526fc-1c85-41fc-9fba-b27ca760a119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275884508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.2275884508
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.381408987
Short name T1333
Test name
Test status
Simulation time 55296396 ps
CPU time 0.66 seconds
Started Apr 23 01:27:52 PM PDT 24
Finished Apr 23 01:27:53 PM PDT 24
Peak memory 203320 kb
Host smart-ee253f41-c9f5-48f5-9a43-5dc3d002a26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381408987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.381408987
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.4227535772
Short name T888
Test name
Test status
Simulation time 72862775200 ps
CPU time 581.96 seconds
Started Apr 23 01:27:52 PM PDT 24
Finished Apr 23 01:37:35 PM PDT 24
Peak memory 203720 kb
Host smart-1bd1af06-9cb4-46e6-89d1-3a540810f268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227535772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.4227535772
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.1653481721
Short name T72
Test name
Test status
Simulation time 2279465008 ps
CPU time 54.59 seconds
Started Apr 23 01:27:53 PM PDT 24
Finished Apr 23 01:28:48 PM PDT 24
Peak memory 346536 kb
Host smart-d029f051-647b-47ec-9e3c-c3306bd18440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653481721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.1653481721
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.3487641538
Short name T358
Test name
Test status
Simulation time 17168732320 ps
CPU time 407.95 seconds
Started Apr 23 01:27:55 PM PDT 24
Finished Apr 23 01:34:44 PM PDT 24
Peak memory 1671276 kb
Host smart-dd3ad69d-cf02-4e4b-a900-cd4dbdf54917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487641538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.3487641538
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.3416160655
Short name T316
Test name
Test status
Simulation time 2293824038 ps
CPU time 23.03 seconds
Started Apr 23 01:27:56 PM PDT 24
Finished Apr 23 01:28:19 PM PDT 24
Peak memory 212044 kb
Host smart-c1c887f8-66c3-4c1f-a0e8-ccee9ef775f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416160655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.3416160655
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.3641975205
Short name T761
Test name
Test status
Simulation time 2590467408 ps
CPU time 3.29 seconds
Started Apr 23 01:27:58 PM PDT 24
Finished Apr 23 01:28:01 PM PDT 24
Peak memory 203736 kb
Host smart-717cea6f-9f2f-47f1-a645-9ca67215c9c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641975205 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.3641975205
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1685196961
Short name T54
Test name
Test status
Simulation time 10120403136 ps
CPU time 72.5 seconds
Started Apr 23 01:27:57 PM PDT 24
Finished Apr 23 01:29:10 PM PDT 24
Peak memory 420168 kb
Host smart-5f964676-b66e-4cbc-a361-174f0a75efc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685196961 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1685196961
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.198368951
Short name T507
Test name
Test status
Simulation time 10768297219 ps
CPU time 9.22 seconds
Started Apr 23 01:27:59 PM PDT 24
Finished Apr 23 01:28:09 PM PDT 24
Peak memory 245208 kb
Host smart-f658fe5f-a423-423a-97a6-f737a683ac15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198368951 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.i2c_target_fifo_reset_tx.198368951
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.1509359467
Short name T669
Test name
Test status
Simulation time 1060461102 ps
CPU time 2.73 seconds
Started Apr 23 01:27:59 PM PDT 24
Finished Apr 23 01:28:02 PM PDT 24
Peak memory 203680 kb
Host smart-de9ad5fe-12e7-44de-80b0-1687a6f0b309
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509359467 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.1509359467
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1985139821
Short name T732
Test name
Test status
Simulation time 946048991 ps
CPU time 4.78 seconds
Started Apr 23 01:27:53 PM PDT 24
Finished Apr 23 01:27:59 PM PDT 24
Peak memory 217240 kb
Host smart-0702d533-0fd7-454d-ad17-7f20cc3f6d7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985139821 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1985139821
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.3295313993
Short name T973
Test name
Test status
Simulation time 14475612053 ps
CPU time 5.5 seconds
Started Apr 23 01:27:56 PM PDT 24
Finished Apr 23 01:28:02 PM PDT 24
Peak memory 203692 kb
Host smart-a6067f13-95bd-4b8b-aa9b-ec7d6558c337
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295313993 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.3295313993
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.1130404094
Short name T308
Test name
Test status
Simulation time 1807414893 ps
CPU time 12.4 seconds
Started Apr 23 01:27:55 PM PDT 24
Finished Apr 23 01:28:07 PM PDT 24
Peak memory 203668 kb
Host smart-f5ef4a86-88f2-4493-b695-8880a774636a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130404094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.1130404094
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.2634138879
Short name T867
Test name
Test status
Simulation time 2551574736 ps
CPU time 22.31 seconds
Started Apr 23 01:27:55 PM PDT 24
Finished Apr 23 01:28:18 PM PDT 24
Peak memory 217024 kb
Host smart-c724583b-44e6-47e4-aabb-9bfb7a89ba67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634138879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.2634138879
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.2700077705
Short name T517
Test name
Test status
Simulation time 13516890630 ps
CPU time 24.79 seconds
Started Apr 23 01:27:55 PM PDT 24
Finished Apr 23 01:28:21 PM PDT 24
Peak memory 203740 kb
Host smart-eb48bf9a-535e-409c-a4be-6d119b162e8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700077705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.2700077705
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.4173725328
Short name T842
Test name
Test status
Simulation time 4832426506 ps
CPU time 6.33 seconds
Started Apr 23 01:27:53 PM PDT 24
Finished Apr 23 01:28:00 PM PDT 24
Peak memory 219716 kb
Host smart-2a544c53-c61f-46a0-8fab-4ebcd9d9ba85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173725328 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.4173725328
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_unexp_stop.1873412827
Short name T631
Test name
Test status
Simulation time 4245290722 ps
CPU time 6.23 seconds
Started Apr 23 01:27:55 PM PDT 24
Finished Apr 23 01:28:02 PM PDT 24
Peak memory 203836 kb
Host smart-24713ba0-9f6a-4088-be5b-c272b1d8c177
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873412827 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.i2c_target_unexp_stop.1873412827
Directory /workspace/45.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/46.i2c_alert_test.2129710197
Short name T384
Test name
Test status
Simulation time 39773325 ps
CPU time 0.63 seconds
Started Apr 23 01:28:15 PM PDT 24
Finished Apr 23 01:28:17 PM PDT 24
Peak memory 203384 kb
Host smart-89baca55-31ec-43e0-ba68-d80e5db775e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129710197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.2129710197
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.2876068437
Short name T790
Test name
Test status
Simulation time 68526281 ps
CPU time 1.27 seconds
Started Apr 23 01:28:02 PM PDT 24
Finished Apr 23 01:28:04 PM PDT 24
Peak memory 212020 kb
Host smart-0b26af6e-1da3-437a-b7ac-d98e1fb9b893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876068437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.2876068437
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.760781433
Short name T904
Test name
Test status
Simulation time 293351419 ps
CPU time 13.89 seconds
Started Apr 23 01:28:01 PM PDT 24
Finished Apr 23 01:28:16 PM PDT 24
Peak memory 252152 kb
Host smart-bce98ec7-5139-46d8-a05d-8686ab54c2ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760781433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empt
y.760781433
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.1323899258
Short name T639
Test name
Test status
Simulation time 5603661080 ps
CPU time 90.47 seconds
Started Apr 23 01:28:01 PM PDT 24
Finished Apr 23 01:29:32 PM PDT 24
Peak memory 539636 kb
Host smart-5b2ca6a5-df34-49f8-bc36-4bec3dae4934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323899258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1323899258
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.2960202195
Short name T285
Test name
Test status
Simulation time 1409673930 ps
CPU time 96.4 seconds
Started Apr 23 01:28:01 PM PDT 24
Finished Apr 23 01:29:38 PM PDT 24
Peak memory 489572 kb
Host smart-7cac555b-353a-4ed5-ae3e-e72ecfde0d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960202195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2960202195
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.1174400990
Short name T696
Test name
Test status
Simulation time 136188888 ps
CPU time 1.16 seconds
Started Apr 23 01:28:03 PM PDT 24
Finished Apr 23 01:28:05 PM PDT 24
Peak memory 203692 kb
Host smart-6f9b5883-e79e-488b-8ce1-a0ad3c9ce9a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174400990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.1174400990
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.1025534045
Short name T395
Test name
Test status
Simulation time 239271822 ps
CPU time 6.73 seconds
Started Apr 23 01:28:04 PM PDT 24
Finished Apr 23 01:28:11 PM PDT 24
Peak memory 203692 kb
Host smart-c13cb5a9-2202-4594-9ab9-31c23444401e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025534045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.1025534045
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.958069292
Short name T235
Test name
Test status
Simulation time 4543569919 ps
CPU time 141.32 seconds
Started Apr 23 01:28:02 PM PDT 24
Finished Apr 23 01:30:24 PM PDT 24
Peak memory 1237940 kb
Host smart-45a3c744-47aa-44ff-9f72-32fcecdda436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958069292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.958069292
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.2207554510
Short name T1242
Test name
Test status
Simulation time 916852367 ps
CPU time 18.46 seconds
Started Apr 23 01:28:10 PM PDT 24
Finished Apr 23 01:28:29 PM PDT 24
Peak memory 203648 kb
Host smart-e4ae7970-1d6f-4d31-8b9d-865acabafdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207554510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.2207554510
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.1607438018
Short name T1109
Test name
Test status
Simulation time 6372583728 ps
CPU time 96.77 seconds
Started Apr 23 01:28:10 PM PDT 24
Finished Apr 23 01:29:47 PM PDT 24
Peak memory 378628 kb
Host smart-2ea95abf-6ef8-446b-9ef2-a13437d5a158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607438018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.1607438018
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.403787678
Short name T1043
Test name
Test status
Simulation time 19871811 ps
CPU time 0.65 seconds
Started Apr 23 01:28:02 PM PDT 24
Finished Apr 23 01:28:03 PM PDT 24
Peak memory 203340 kb
Host smart-4d8e4853-9c42-4359-a68a-d1cf0afcc642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403787678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.403787678
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.2755170294
Short name T860
Test name
Test status
Simulation time 3079016652 ps
CPU time 78.99 seconds
Started Apr 23 01:28:01 PM PDT 24
Finished Apr 23 01:29:21 PM PDT 24
Peak memory 445572 kb
Host smart-68c18352-755f-4dfa-8bca-a6c13400a18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755170294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.2755170294
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.2650083934
Short name T1228
Test name
Test status
Simulation time 5578631571 ps
CPU time 68.88 seconds
Started Apr 23 01:27:59 PM PDT 24
Finished Apr 23 01:29:08 PM PDT 24
Peak memory 329920 kb
Host smart-585a0b8d-3955-4d0a-9c91-ce4a45505001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650083934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.2650083934
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.2355462738
Short name T789
Test name
Test status
Simulation time 67354441735 ps
CPU time 653.86 seconds
Started Apr 23 01:28:07 PM PDT 24
Finished Apr 23 01:39:02 PM PDT 24
Peak memory 1626512 kb
Host smart-a8f33b53-73bb-46f0-8711-4c15d6d564af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355462738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.2355462738
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.3251049469
Short name T892
Test name
Test status
Simulation time 1644593650 ps
CPU time 8.27 seconds
Started Apr 23 01:28:04 PM PDT 24
Finished Apr 23 01:28:13 PM PDT 24
Peak memory 212052 kb
Host smart-31edc4bf-f7be-42c4-89a8-60e273f12f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251049469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.3251049469
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.1764528961
Short name T1256
Test name
Test status
Simulation time 3097014287 ps
CPU time 3.98 seconds
Started Apr 23 01:28:09 PM PDT 24
Finished Apr 23 01:28:13 PM PDT 24
Peak memory 212012 kb
Host smart-f443f0a7-1110-48e9-ac54-4c514165c3a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764528961 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.1764528961
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.2055414142
Short name T715
Test name
Test status
Simulation time 10224356371 ps
CPU time 30.37 seconds
Started Apr 23 01:28:07 PM PDT 24
Finished Apr 23 01:28:38 PM PDT 24
Peak memory 329328 kb
Host smart-f90a05b7-9af4-44c3-8db6-5181a26c69ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055414142 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.2055414142
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.1346225849
Short name T38
Test name
Test status
Simulation time 10104115756 ps
CPU time 30.49 seconds
Started Apr 23 01:28:06 PM PDT 24
Finished Apr 23 01:28:37 PM PDT 24
Peak memory 412496 kb
Host smart-4e7748a1-51da-44aa-9eb2-19f3627d18d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346225849 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.1346225849
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.397423557
Short name T450
Test name
Test status
Simulation time 318691654 ps
CPU time 2.3 seconds
Started Apr 23 01:28:12 PM PDT 24
Finished Apr 23 01:28:14 PM PDT 24
Peak memory 203808 kb
Host smart-c574bdb1-e788-48e3-b4db-1de54f9dbeb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397423557 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.i2c_target_hrst.397423557
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.1944222284
Short name T303
Test name
Test status
Simulation time 1043249208 ps
CPU time 5.29 seconds
Started Apr 23 01:28:08 PM PDT 24
Finished Apr 23 01:28:14 PM PDT 24
Peak memory 203668 kb
Host smart-ded9780c-d30c-4d79-b48f-9cb96f6e1470
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944222284 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.1944222284
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.22669309
Short name T1044
Test name
Test status
Simulation time 17103903129 ps
CPU time 44.63 seconds
Started Apr 23 01:28:06 PM PDT 24
Finished Apr 23 01:28:51 PM PDT 24
Peak memory 991600 kb
Host smart-76416c4b-4b22-4d96-98e7-b77528c6848c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22669309 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.22669309
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.883853360
Short name T381
Test name
Test status
Simulation time 7464807839 ps
CPU time 43.77 seconds
Started Apr 23 01:28:06 PM PDT 24
Finished Apr 23 01:28:50 PM PDT 24
Peak memory 203716 kb
Host smart-05008eb3-7a14-40e4-b7e0-523ff4a8cb50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883853360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_tar
get_smoke.883853360
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.2670533314
Short name T1123
Test name
Test status
Simulation time 3040540728 ps
CPU time 29.16 seconds
Started Apr 23 01:28:07 PM PDT 24
Finished Apr 23 01:28:36 PM PDT 24
Peak memory 229488 kb
Host smart-e2b738df-cc7d-4980-a5ba-6340680cb9df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670533314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.2670533314
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.543122815
Short name T1153
Test name
Test status
Simulation time 37287095473 ps
CPU time 35.91 seconds
Started Apr 23 01:28:04 PM PDT 24
Finished Apr 23 01:28:40 PM PDT 24
Peak memory 802564 kb
Host smart-a3053fe3-eb0f-4de8-904f-ae3007483380
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543122815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_wr.543122815
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.848457597
Short name T425
Test name
Test status
Simulation time 23177976283 ps
CPU time 1336.76 seconds
Started Apr 23 01:28:06 PM PDT 24
Finished Apr 23 01:50:23 PM PDT 24
Peak memory 5489124 kb
Host smart-26ed9700-ab21-43eb-8a73-88cf2a8d05d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848457597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_t
arget_stretch.848457597
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2388660061
Short name T100
Test name
Test status
Simulation time 1322014251 ps
CPU time 7.11 seconds
Started Apr 23 01:28:05 PM PDT 24
Finished Apr 23 01:28:13 PM PDT 24
Peak memory 219964 kb
Host smart-380ad431-8288-4be5-939b-4a5ac5315810
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388660061 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2388660061
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.1791232699
Short name T540
Test name
Test status
Simulation time 45078072 ps
CPU time 0.6 seconds
Started Apr 23 01:28:17 PM PDT 24
Finished Apr 23 01:28:18 PM PDT 24
Peak memory 203412 kb
Host smart-39493c38-1657-4109-8a5f-c69ad004efb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791232699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.1791232699
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.961222162
Short name T608
Test name
Test status
Simulation time 301585588 ps
CPU time 1.17 seconds
Started Apr 23 01:28:12 PM PDT 24
Finished Apr 23 01:28:13 PM PDT 24
Peak memory 203812 kb
Host smart-bcb556e9-05a0-486b-80b0-a183eac17b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961222162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.961222162
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.4097452684
Short name T787
Test name
Test status
Simulation time 216277082 ps
CPU time 10.38 seconds
Started Apr 23 01:28:15 PM PDT 24
Finished Apr 23 01:28:25 PM PDT 24
Peak memory 222128 kb
Host smart-e6dcd30d-84c2-49ab-bdeb-bfcd0ae340ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097452684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.4097452684
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.3139254087
Short name T771
Test name
Test status
Simulation time 2437694983 ps
CPU time 95.44 seconds
Started Apr 23 01:28:14 PM PDT 24
Finished Apr 23 01:29:50 PM PDT 24
Peak memory 787032 kb
Host smart-bd3dd3e5-0a32-40bd-b161-66c41fd3a750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139254087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.3139254087
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.1342085863
Short name T878
Test name
Test status
Simulation time 4398689394 ps
CPU time 159.35 seconds
Started Apr 23 01:28:10 PM PDT 24
Finished Apr 23 01:30:50 PM PDT 24
Peak memory 677144 kb
Host smart-08e46b27-f74c-45f2-b4fd-30fa971504c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342085863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1342085863
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.2422536352
Short name T614
Test name
Test status
Simulation time 350636834 ps
CPU time 1 seconds
Started Apr 23 01:28:13 PM PDT 24
Finished Apr 23 01:28:15 PM PDT 24
Peak memory 203644 kb
Host smart-d67efa2b-ea54-43a1-ad4e-f2621e903d40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422536352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.2422536352
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.2828104963
Short name T1224
Test name
Test status
Simulation time 433596343 ps
CPU time 5.95 seconds
Started Apr 23 01:28:13 PM PDT 24
Finished Apr 23 01:28:19 PM PDT 24
Peak memory 203608 kb
Host smart-7cd93b8a-c005-491f-9a93-de66c78c063b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828104963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.2828104963
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.1212564371
Short name T781
Test name
Test status
Simulation time 16102583935 ps
CPU time 114.93 seconds
Started Apr 23 01:28:09 PM PDT 24
Finished Apr 23 01:30:04 PM PDT 24
Peak memory 1182916 kb
Host smart-5a2fc44f-d208-4448-9226-e19c17373243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212564371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1212564371
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.2497442872
Short name T1198
Test name
Test status
Simulation time 346108947 ps
CPU time 14.04 seconds
Started Apr 23 01:28:16 PM PDT 24
Finished Apr 23 01:28:30 PM PDT 24
Peak memory 203696 kb
Host smart-ce7a8c50-a514-4114-bc97-132bd588f3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497442872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.2497442872
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.3953619820
Short name T263
Test name
Test status
Simulation time 2495022863 ps
CPU time 55.79 seconds
Started Apr 23 01:28:17 PM PDT 24
Finished Apr 23 01:29:13 PM PDT 24
Peak memory 299968 kb
Host smart-0ab6f21f-b1ab-40c6-a91f-00e242f34417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953619820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.3953619820
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.3523744915
Short name T39
Test name
Test status
Simulation time 38136403 ps
CPU time 0.67 seconds
Started Apr 23 01:28:10 PM PDT 24
Finished Apr 23 01:28:11 PM PDT 24
Peak memory 203324 kb
Host smart-2c3827f5-831a-42af-a36a-dbcf0ae8db12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523744915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.3523744915
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.1706821053
Short name T798
Test name
Test status
Simulation time 7008725759 ps
CPU time 26.61 seconds
Started Apr 23 01:28:14 PM PDT 24
Finished Apr 23 01:28:41 PM PDT 24
Peak memory 248940 kb
Host smart-d7279e28-4157-4ad1-a584-60d530e1ad89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706821053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.1706821053
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.1450027930
Short name T1301
Test name
Test status
Simulation time 1025979302 ps
CPU time 46.24 seconds
Started Apr 23 01:28:13 PM PDT 24
Finished Apr 23 01:29:00 PM PDT 24
Peak memory 238224 kb
Host smart-5f51f389-49d0-4ad8-a13a-0ce5c3a498ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450027930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.1450027930
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.1757261653
Short name T1208
Test name
Test status
Simulation time 42499775019 ps
CPU time 1847.86 seconds
Started Apr 23 01:28:16 PM PDT 24
Finished Apr 23 01:59:05 PM PDT 24
Peak memory 1372048 kb
Host smart-f9566062-1a28-4b80-b50e-a5db6ddab8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757261653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.1757261653
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.406573034
Short name T1049
Test name
Test status
Simulation time 1835306479 ps
CPU time 19.52 seconds
Started Apr 23 01:28:16 PM PDT 24
Finished Apr 23 01:28:36 PM PDT 24
Peak memory 211864 kb
Host smart-255f29a0-dee2-49a0-8826-b72be81817e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406573034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.406573034
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.1122915623
Short name T933
Test name
Test status
Simulation time 4027913604 ps
CPU time 4.53 seconds
Started Apr 23 01:28:18 PM PDT 24
Finished Apr 23 01:28:23 PM PDT 24
Peak memory 203844 kb
Host smart-f8e48384-452e-4686-8ade-9392f11c6933
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122915623 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.1122915623
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.2344695549
Short name T983
Test name
Test status
Simulation time 10046678408 ps
CPU time 55.26 seconds
Started Apr 23 01:28:14 PM PDT 24
Finished Apr 23 01:29:10 PM PDT 24
Peak memory 486368 kb
Host smart-7458c336-fe16-4225-9b42-0dc86ee47961
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344695549 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.2344695549
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.2483915582
Short name T1205
Test name
Test status
Simulation time 10719525971 ps
CPU time 5.51 seconds
Started Apr 23 01:28:13 PM PDT 24
Finished Apr 23 01:28:19 PM PDT 24
Peak memory 235328 kb
Host smart-dceb2a07-c9ca-49d8-a79f-0c335ed39c58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483915582 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.2483915582
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.1256334582
Short name T225
Test name
Test status
Simulation time 1231856444 ps
CPU time 2.33 seconds
Started Apr 23 01:28:17 PM PDT 24
Finished Apr 23 01:28:20 PM PDT 24
Peak memory 203712 kb
Host smart-ea384af2-fcf8-4227-92c0-d2071da52a4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256334582 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.1256334582
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2443650074
Short name T1222
Test name
Test status
Simulation time 1023595009 ps
CPU time 5.47 seconds
Started Apr 23 01:28:14 PM PDT 24
Finished Apr 23 01:28:20 PM PDT 24
Peak memory 217884 kb
Host smart-ad4b9986-c331-4d0a-a204-6347b6de2b48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443650074 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2443650074
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.2333687171
Short name T653
Test name
Test status
Simulation time 24340164223 ps
CPU time 532.28 seconds
Started Apr 23 01:28:16 PM PDT 24
Finished Apr 23 01:37:09 PM PDT 24
Peak memory 5894668 kb
Host smart-727ddebb-12ff-4fe6-87b0-8b2f5df3fc51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333687171 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.2333687171
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.1613342642
Short name T731
Test name
Test status
Simulation time 1315933289 ps
CPU time 21.93 seconds
Started Apr 23 01:28:12 PM PDT 24
Finished Apr 23 01:28:34 PM PDT 24
Peak memory 203636 kb
Host smart-ea51b368-547b-45b0-92b7-40d38bbbc501
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613342642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.1613342642
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.3108803489
Short name T1245
Test name
Test status
Simulation time 331375672 ps
CPU time 14.12 seconds
Started Apr 23 01:28:15 PM PDT 24
Finished Apr 23 01:28:29 PM PDT 24
Peak memory 203648 kb
Host smart-c878fa2d-abd3-4c38-855c-f8d1b5a5071f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108803489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.3108803489
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.101722001
Short name T821
Test name
Test status
Simulation time 8060875277 ps
CPU time 9.2 seconds
Started Apr 23 01:28:16 PM PDT 24
Finished Apr 23 01:28:26 PM PDT 24
Peak memory 203768 kb
Host smart-6fcc863c-7ab7-41aa-bde5-157692228b40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101722001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_wr.101722001
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.2762623902
Short name T626
Test name
Test status
Simulation time 13855497560 ps
CPU time 773.9 seconds
Started Apr 23 01:28:13 PM PDT 24
Finished Apr 23 01:41:07 PM PDT 24
Peak memory 3478248 kb
Host smart-d19c1142-70fb-4981-8a98-89095975d5af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762623902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.2762623902
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.3568671406
Short name T1287
Test name
Test status
Simulation time 9084732563 ps
CPU time 6.5 seconds
Started Apr 23 01:28:14 PM PDT 24
Finished Apr 23 01:28:21 PM PDT 24
Peak memory 217784 kb
Host smart-32f60a64-4a86-46b0-8d0b-be83971a532a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568671406 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.3568671406
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.1438762065
Short name T116
Test name
Test status
Simulation time 21077371 ps
CPU time 0.69 seconds
Started Apr 23 01:28:26 PM PDT 24
Finished Apr 23 01:28:27 PM PDT 24
Peak memory 203288 kb
Host smart-7bbc4e2f-c0f5-4a9f-8853-f6142119dfd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438762065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.1438762065
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.53931540
Short name T1249
Test name
Test status
Simulation time 96752236 ps
CPU time 1.59 seconds
Started Apr 23 01:28:19 PM PDT 24
Finished Apr 23 01:28:21 PM PDT 24
Peak memory 220148 kb
Host smart-7b09c1cf-b4bc-4fbc-8699-ca52f92bd22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53931540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.53931540
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.4126066918
Short name T640
Test name
Test status
Simulation time 352559103 ps
CPU time 5.39 seconds
Started Apr 23 01:28:19 PM PDT 24
Finished Apr 23 01:28:25 PM PDT 24
Peak memory 219792 kb
Host smart-bbab43de-b418-4f38-a2e6-4f7cd13853b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126066918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.4126066918
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.4065721516
Short name T336
Test name
Test status
Simulation time 7595036401 ps
CPU time 145.88 seconds
Started Apr 23 01:28:21 PM PDT 24
Finished Apr 23 01:30:47 PM PDT 24
Peak memory 659244 kb
Host smart-8e7377d9-7c8c-4216-98e3-82b015593f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065721516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.4065721516
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.438137141
Short name T616
Test name
Test status
Simulation time 8424103841 ps
CPU time 148.58 seconds
Started Apr 23 01:28:19 PM PDT 24
Finished Apr 23 01:30:48 PM PDT 24
Peak memory 655516 kb
Host smart-bb8d1001-a3e4-44ad-aee5-cd9ff3c93987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438137141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.438137141
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.1816840699
Short name T594
Test name
Test status
Simulation time 515904725 ps
CPU time 0.98 seconds
Started Apr 23 01:28:16 PM PDT 24
Finished Apr 23 01:28:18 PM PDT 24
Peak memory 203348 kb
Host smart-ac2de7db-622e-4e16-affd-7a03005f0c76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816840699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.1816840699
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3487654086
Short name T869
Test name
Test status
Simulation time 1246491075 ps
CPU time 3.04 seconds
Started Apr 23 01:28:17 PM PDT 24
Finished Apr 23 01:28:21 PM PDT 24
Peak memory 220424 kb
Host smart-0478cb94-5dfd-4a6d-a190-68842028e5b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487654086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3487654086
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.2892029198
Short name T1262
Test name
Test status
Simulation time 7988575121 ps
CPU time 126.84 seconds
Started Apr 23 01:28:18 PM PDT 24
Finished Apr 23 01:30:26 PM PDT 24
Peak memory 1198592 kb
Host smart-9c6b67a9-58d2-44e4-a0b9-008b7a7391d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892029198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.2892029198
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.2269150447
Short name T578
Test name
Test status
Simulation time 1689402680 ps
CPU time 17.25 seconds
Started Apr 23 01:28:27 PM PDT 24
Finished Apr 23 01:28:45 PM PDT 24
Peak memory 203628 kb
Host smart-77b5a637-bb61-42d6-b3bc-b5ff170139f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269150447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.2269150447
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.3269980849
Short name T969
Test name
Test status
Simulation time 3004394404 ps
CPU time 26.32 seconds
Started Apr 23 01:28:27 PM PDT 24
Finished Apr 23 01:28:54 PM PDT 24
Peak memory 342944 kb
Host smart-0ad15b28-eda2-4279-9be7-3f1c5d263741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269980849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.3269980849
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.3853228817
Short name T805
Test name
Test status
Simulation time 39374076 ps
CPU time 0.63 seconds
Started Apr 23 01:28:16 PM PDT 24
Finished Apr 23 01:28:17 PM PDT 24
Peak memory 203340 kb
Host smart-25594c82-4ff3-4fd8-92a9-782022ec53cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853228817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.3853228817
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.789291758
Short name T1334
Test name
Test status
Simulation time 13411388173 ps
CPU time 140.39 seconds
Started Apr 23 01:28:20 PM PDT 24
Finished Apr 23 01:30:41 PM PDT 24
Peak memory 358324 kb
Host smart-68c86f37-67a9-427a-a947-cc00732adc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789291758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.789291758
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.1904660604
Short name T622
Test name
Test status
Simulation time 1518490152 ps
CPU time 37.71 seconds
Started Apr 23 01:28:18 PM PDT 24
Finished Apr 23 01:28:56 PM PDT 24
Peak memory 300780 kb
Host smart-887ce6b9-d435-4875-8d63-ab75a8c87db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904660604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.1904660604
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.2169584299
Short name T1108
Test name
Test status
Simulation time 25393393715 ps
CPU time 783.84 seconds
Started Apr 23 01:28:20 PM PDT 24
Finished Apr 23 01:41:25 PM PDT 24
Peak memory 3238248 kb
Host smart-3e16db94-15e4-4bbc-9d17-5371f1314060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169584299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.2169584299
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.1322985786
Short name T468
Test name
Test status
Simulation time 2373205258 ps
CPU time 13.38 seconds
Started Apr 23 01:28:20 PM PDT 24
Finished Apr 23 01:28:34 PM PDT 24
Peak memory 220076 kb
Host smart-0add0f35-8af8-42b4-95ff-cf3194ccdcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322985786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.1322985786
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.2251478936
Short name T498
Test name
Test status
Simulation time 947484837 ps
CPU time 4 seconds
Started Apr 23 01:28:24 PM PDT 24
Finished Apr 23 01:28:29 PM PDT 24
Peak memory 211884 kb
Host smart-b71ba7c0-2d4f-4991-9448-131633bb7e27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251478936 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.2251478936
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.1776479761
Short name T585
Test name
Test status
Simulation time 10050995014 ps
CPU time 67.03 seconds
Started Apr 23 01:28:23 PM PDT 24
Finished Apr 23 01:29:30 PM PDT 24
Peak memory 434124 kb
Host smart-4f0e0095-c332-41af-a4b6-e1f154d0b3a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776479761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.1776479761
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.4180995076
Short name T735
Test name
Test status
Simulation time 10324854928 ps
CPU time 9.42 seconds
Started Apr 23 01:28:23 PM PDT 24
Finished Apr 23 01:28:33 PM PDT 24
Peak memory 242732 kb
Host smart-7289dd61-dcef-41c2-890a-310ade377d69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180995076 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.4180995076
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.3222502478
Short name T843
Test name
Test status
Simulation time 875660340 ps
CPU time 2.85 seconds
Started Apr 23 01:28:24 PM PDT 24
Finished Apr 23 01:28:27 PM PDT 24
Peak memory 203744 kb
Host smart-6427c391-51a5-427a-b2bb-912999a6c318
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222502478 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.3222502478
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.362904845
Short name T488
Test name
Test status
Simulation time 3906094516 ps
CPU time 5.67 seconds
Started Apr 23 01:28:21 PM PDT 24
Finished Apr 23 01:28:27 PM PDT 24
Peak memory 215044 kb
Host smart-0cb9abc1-fa67-4121-a3f6-8a2d6a53da67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362904845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_intr_smoke.362904845
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.421107049
Short name T226
Test name
Test status
Simulation time 7278559011 ps
CPU time 33.36 seconds
Started Apr 23 01:28:18 PM PDT 24
Finished Apr 23 01:28:51 PM PDT 24
Peak memory 1007036 kb
Host smart-b6f9036d-1ee8-484c-8d93-117dae1db1e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421107049 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.421107049
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.372317885
Short name T273
Test name
Test status
Simulation time 2667733033 ps
CPU time 16.05 seconds
Started Apr 23 01:28:27 PM PDT 24
Finished Apr 23 01:28:43 PM PDT 24
Peak memory 203760 kb
Host smart-d7904352-14a7-4125-b0b5-8684d203e3b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372317885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_tar
get_smoke.372317885
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.602048193
Short name T252
Test name
Test status
Simulation time 1221445228 ps
CPU time 18.94 seconds
Started Apr 23 01:28:22 PM PDT 24
Finished Apr 23 01:28:42 PM PDT 24
Peak memory 220788 kb
Host smart-250a338d-166d-4eed-b24b-de9906013086
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602048193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_rd.602048193
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3835301600
Short name T25
Test name
Test status
Simulation time 48608633525 ps
CPU time 1115.68 seconds
Started Apr 23 01:28:19 PM PDT 24
Finished Apr 23 01:46:56 PM PDT 24
Peak memory 7042264 kb
Host smart-26746850-51c9-48f8-9a2f-ccfae8be89a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835301600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3835301600
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.4223073893
Short name T872
Test name
Test status
Simulation time 29065908594 ps
CPU time 1839.08 seconds
Started Apr 23 01:28:19 PM PDT 24
Finished Apr 23 01:58:59 PM PDT 24
Peak memory 3534276 kb
Host smart-5bb99c24-fce4-4df1-92f5-b5e9ed498850
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223073893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.4223073893
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.3740160703
Short name T886
Test name
Test status
Simulation time 1505081442 ps
CPU time 7.39 seconds
Started Apr 23 01:28:19 PM PDT 24
Finished Apr 23 01:28:27 PM PDT 24
Peak memory 211044 kb
Host smart-272c2e8b-a06b-4031-9d06-a892a25ee1d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740160703 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.3740160703
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.585397892
Short name T977
Test name
Test status
Simulation time 45859388 ps
CPU time 0.62 seconds
Started Apr 23 01:28:34 PM PDT 24
Finished Apr 23 01:28:36 PM PDT 24
Peak memory 203300 kb
Host smart-a0045d6b-8659-4f84-8741-a27c817d6717
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585397892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.585397892
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.3699874269
Short name T59
Test name
Test status
Simulation time 855900408 ps
CPU time 1.34 seconds
Started Apr 23 01:28:28 PM PDT 24
Finished Apr 23 01:28:30 PM PDT 24
Peak memory 212008 kb
Host smart-ad872c9f-7cbb-4437-9aa0-0c74649fe876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699874269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.3699874269
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.943736177
Short name T799
Test name
Test status
Simulation time 539577786 ps
CPU time 6.22 seconds
Started Apr 23 01:28:25 PM PDT 24
Finished Apr 23 01:28:32 PM PDT 24
Peak memory 259516 kb
Host smart-8a51c1a1-ad37-46db-9d18-613ab91a23b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943736177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empt
y.943736177
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.3460290080
Short name T1150
Test name
Test status
Simulation time 3753617727 ps
CPU time 58.02 seconds
Started Apr 23 01:28:27 PM PDT 24
Finished Apr 23 01:29:25 PM PDT 24
Peak memory 653104 kb
Host smart-85925103-d042-4cb6-9398-ccd4c9932226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460290080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.3460290080
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.3995186463
Short name T1093
Test name
Test status
Simulation time 2338097603 ps
CPU time 74.07 seconds
Started Apr 23 01:28:27 PM PDT 24
Finished Apr 23 01:29:42 PM PDT 24
Peak memory 746432 kb
Host smart-717fc0d5-2d31-48db-83f5-7aa35301685c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995186463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.3995186463
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.1607463877
Short name T1317
Test name
Test status
Simulation time 79948028 ps
CPU time 0.94 seconds
Started Apr 23 01:28:29 PM PDT 24
Finished Apr 23 01:28:30 PM PDT 24
Peak memory 203464 kb
Host smart-6e95fd28-ae0b-471b-a4ef-61be28d24b09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607463877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.1607463877
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.3277620713
Short name T1214
Test name
Test status
Simulation time 166983284 ps
CPU time 4.57 seconds
Started Apr 23 01:28:31 PM PDT 24
Finished Apr 23 01:28:36 PM PDT 24
Peak memory 203668 kb
Host smart-a9f3fc12-25f6-4aae-bf53-a7fd60395039
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277620713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.3277620713
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.2280434310
Short name T260
Test name
Test status
Simulation time 5454039151 ps
CPU time 184.33 seconds
Started Apr 23 01:28:26 PM PDT 24
Finished Apr 23 01:31:31 PM PDT 24
Peak memory 882840 kb
Host smart-960a9475-8901-469b-ba81-f746f4f13724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280434310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.2280434310
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.3662097943
Short name T1097
Test name
Test status
Simulation time 1629413684 ps
CPU time 2.86 seconds
Started Apr 23 01:28:36 PM PDT 24
Finished Apr 23 01:28:39 PM PDT 24
Peak memory 203692 kb
Host smart-97cfad1a-e0f1-4e5f-882e-21c1a6f03838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662097943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.3662097943
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.3867487678
Short name T859
Test name
Test status
Simulation time 7199423570 ps
CPU time 25.01 seconds
Started Apr 23 01:28:33 PM PDT 24
Finished Apr 23 01:28:59 PM PDT 24
Peak memory 329764 kb
Host smart-689b4f38-6253-420f-9ac8-d13df423861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867487678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.3867487678
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.736097162
Short name T1357
Test name
Test status
Simulation time 57374379 ps
CPU time 0.68 seconds
Started Apr 23 01:28:28 PM PDT 24
Finished Apr 23 01:28:29 PM PDT 24
Peak memory 203412 kb
Host smart-1f57c5a5-aaac-4886-9475-9b17ebe44e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736097162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.736097162
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.1655837840
Short name T195
Test name
Test status
Simulation time 3426545834 ps
CPU time 204.82 seconds
Started Apr 23 01:28:25 PM PDT 24
Finished Apr 23 01:31:50 PM PDT 24
Peak memory 620376 kb
Host smart-da441c23-4870-48ee-b7bf-3fd623530117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655837840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1655837840
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.3019718733
Short name T1289
Test name
Test status
Simulation time 3252177016 ps
CPU time 38.71 seconds
Started Apr 23 01:28:27 PM PDT 24
Finished Apr 23 01:29:06 PM PDT 24
Peak memory 296112 kb
Host smart-dc0c0b54-f280-4329-8a82-162d1ec0ab52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019718733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.3019718733
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.2530765123
Short name T457
Test name
Test status
Simulation time 30926364017 ps
CPU time 382.42 seconds
Started Apr 23 01:28:29 PM PDT 24
Finished Apr 23 01:34:52 PM PDT 24
Peak memory 1576568 kb
Host smart-574a85af-2f7a-4038-8040-bb03cbca442b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530765123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.2530765123
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.451427134
Short name T1241
Test name
Test status
Simulation time 5633368411 ps
CPU time 7.41 seconds
Started Apr 23 01:28:27 PM PDT 24
Finished Apr 23 01:28:35 PM PDT 24
Peak memory 213532 kb
Host smart-2d0518f4-863d-4b5b-8802-a3dbb87ce2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451427134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.451427134
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.748545071
Short name T992
Test name
Test status
Simulation time 3772259442 ps
CPU time 4.49 seconds
Started Apr 23 01:28:30 PM PDT 24
Finished Apr 23 01:28:35 PM PDT 24
Peak memory 203908 kb
Host smart-de282224-8d15-4492-992f-89467945177e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748545071 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.748545071
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.3207682873
Short name T424
Test name
Test status
Simulation time 10460213020 ps
CPU time 11.17 seconds
Started Apr 23 01:28:30 PM PDT 24
Finished Apr 23 01:28:42 PM PDT 24
Peak memory 275872 kb
Host smart-d4a308e1-4de1-4a86-a17f-84b08db3cc77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207682873 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.3207682873
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.2370650338
Short name T923
Test name
Test status
Simulation time 10306220522 ps
CPU time 16.09 seconds
Started Apr 23 01:28:30 PM PDT 24
Finished Apr 23 01:28:46 PM PDT 24
Peak memory 274340 kb
Host smart-bfe15668-977b-4682-84d3-f892491fab9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370650338 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.2370650338
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.1222335594
Short name T1261
Test name
Test status
Simulation time 2474023181 ps
CPU time 2.39 seconds
Started Apr 23 01:28:29 PM PDT 24
Finished Apr 23 01:28:32 PM PDT 24
Peak memory 203780 kb
Host smart-4204f634-f3be-4297-8c1f-9a922dc27cf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222335594 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.1222335594
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.3556268389
Short name T1096
Test name
Test status
Simulation time 5855413345 ps
CPU time 6.49 seconds
Started Apr 23 01:28:32 PM PDT 24
Finished Apr 23 01:28:39 PM PDT 24
Peak memory 220112 kb
Host smart-e33d0765-6c0c-4ec1-b291-1aee6a1dd2a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556268389 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.3556268389
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.259247027
Short name T532
Test name
Test status
Simulation time 21736123558 ps
CPU time 173.18 seconds
Started Apr 23 01:28:31 PM PDT 24
Finished Apr 23 01:31:25 PM PDT 24
Peak memory 2667096 kb
Host smart-ab24a25b-5664-4ab5-a892-0febc5c69624
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259247027 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.259247027
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.2450532615
Short name T764
Test name
Test status
Simulation time 4831414562 ps
CPU time 19.57 seconds
Started Apr 23 01:28:30 PM PDT 24
Finished Apr 23 01:28:50 PM PDT 24
Peak memory 203820 kb
Host smart-e3d40a8b-6485-4b6d-9462-005de2828798
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450532615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.2450532615
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.555514390
Short name T703
Test name
Test status
Simulation time 4458552373 ps
CPU time 50.37 seconds
Started Apr 23 01:28:34 PM PDT 24
Finished Apr 23 01:29:25 PM PDT 24
Peak memory 204916 kb
Host smart-58741d37-d748-4328-a881-1a1e2f8e947a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555514390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_rd.555514390
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.3644019825
Short name T624
Test name
Test status
Simulation time 19933057731 ps
CPU time 5.83 seconds
Started Apr 23 01:28:32 PM PDT 24
Finished Apr 23 01:28:38 PM PDT 24
Peak memory 203820 kb
Host smart-fef525b6-0b6a-4b4f-ada4-b86b5c3c84ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644019825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.3644019825
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.1008091691
Short name T416
Test name
Test status
Simulation time 9096291132 ps
CPU time 894.68 seconds
Started Apr 23 01:28:30 PM PDT 24
Finished Apr 23 01:43:25 PM PDT 24
Peak memory 2322832 kb
Host smart-cc65ec66-fac3-4b84-906e-d45b22a013d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008091691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.1008091691
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.1573328996
Short name T1311
Test name
Test status
Simulation time 4540200303 ps
CPU time 5.75 seconds
Started Apr 23 01:28:31 PM PDT 24
Finished Apr 23 01:28:37 PM PDT 24
Peak memory 218056 kb
Host smart-0a490f5b-3bd2-41c9-b796-2b86ce23df2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573328996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.1573328996
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.2069256514
Short name T320
Test name
Test status
Simulation time 18071251 ps
CPU time 0.61 seconds
Started Apr 23 01:22:10 PM PDT 24
Finished Apr 23 01:22:11 PM PDT 24
Peak memory 203396 kb
Host smart-8166141a-c433-48c8-8741-868dbe6d362e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069256514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.2069256514
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.1956341502
Short name T966
Test name
Test status
Simulation time 780091113 ps
CPU time 1.5 seconds
Started Apr 23 01:22:02 PM PDT 24
Finished Apr 23 01:22:04 PM PDT 24
Peak memory 203860 kb
Host smart-0be224ea-8144-452d-b75b-6314e2a1b7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956341502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.1956341502
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.2958998504
Short name T1183
Test name
Test status
Simulation time 1432203743 ps
CPU time 7.07 seconds
Started Apr 23 01:22:02 PM PDT 24
Finished Apr 23 01:22:10 PM PDT 24
Peak memory 279188 kb
Host smart-4ea3af10-7a67-4980-b7f3-304327a73963
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958998504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.2958998504
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2553902308
Short name T312
Test name
Test status
Simulation time 1390369886 ps
CPU time 30.67 seconds
Started Apr 23 01:22:03 PM PDT 24
Finished Apr 23 01:22:34 PM PDT 24
Peak memory 307044 kb
Host smart-c87ba46d-60c0-4e73-ab7e-4ea49026ed1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553902308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2553902308
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.2285798710
Short name T478
Test name
Test status
Simulation time 2366802174 ps
CPU time 68.28 seconds
Started Apr 23 01:22:04 PM PDT 24
Finished Apr 23 01:23:13 PM PDT 24
Peak memory 748116 kb
Host smart-03114bfe-4f05-48f5-9df8-969fde918e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285798710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.2285798710
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.3512172188
Short name T1281
Test name
Test status
Simulation time 1326972664 ps
CPU time 1.01 seconds
Started Apr 23 01:22:02 PM PDT 24
Finished Apr 23 01:22:04 PM PDT 24
Peak memory 203632 kb
Host smart-96f99495-d5ac-4a4f-a4be-1f4b2d30ca58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512172188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.3512172188
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.1663984917
Short name T1032
Test name
Test status
Simulation time 119676863 ps
CPU time 2.97 seconds
Started Apr 23 01:22:04 PM PDT 24
Finished Apr 23 01:22:07 PM PDT 24
Peak memory 203536 kb
Host smart-7332bece-ea16-4098-8a68-2fa3aeeb3bc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663984917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
1663984917
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.3873813293
Short name T1341
Test name
Test status
Simulation time 3841668292 ps
CPU time 295.63 seconds
Started Apr 23 01:21:59 PM PDT 24
Finished Apr 23 01:26:55 PM PDT 24
Peak memory 1135992 kb
Host smart-9be7a7f7-4da4-4526-94dd-5ddb253ef432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873813293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3873813293
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.724176770
Short name T483
Test name
Test status
Simulation time 432087704 ps
CPU time 18.65 seconds
Started Apr 23 01:22:08 PM PDT 24
Finished Apr 23 01:22:27 PM PDT 24
Peak memory 203636 kb
Host smart-9b2852b5-5919-4a14-ab42-aa2e27ab4677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724176770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.724176770
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.3854332453
Short name T454
Test name
Test status
Simulation time 5409502118 ps
CPU time 26.06 seconds
Started Apr 23 01:22:08 PM PDT 24
Finished Apr 23 01:22:35 PM PDT 24
Peak memory 341836 kb
Host smart-b9831dd6-e4b4-4f08-8ae4-bb7eeefa9e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854332453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.3854332453
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.1048507388
Short name T339
Test name
Test status
Simulation time 18558863 ps
CPU time 0.66 seconds
Started Apr 23 01:21:57 PM PDT 24
Finished Apr 23 01:21:59 PM PDT 24
Peak memory 203284 kb
Host smart-8e299fd7-2be0-4399-bc60-5a74ec9c9d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048507388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.1048507388
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.1458460576
Short name T1252
Test name
Test status
Simulation time 12444056703 ps
CPU time 471.89 seconds
Started Apr 23 01:22:03 PM PDT 24
Finished Apr 23 01:29:56 PM PDT 24
Peak memory 240232 kb
Host smart-a8c4f112-9e5d-4a89-b2d5-de458c4e0599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458460576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.1458460576
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.1170310924
Short name T86
Test name
Test status
Simulation time 2581620603 ps
CPU time 61.27 seconds
Started Apr 23 01:21:58 PM PDT 24
Finished Apr 23 01:23:00 PM PDT 24
Peak memory 311140 kb
Host smart-b0df2b33-47d3-4cff-896f-48065c97c841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170310924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.1170310924
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.1440539016
Short name T1052
Test name
Test status
Simulation time 1518907046 ps
CPU time 26.83 seconds
Started Apr 23 01:22:01 PM PDT 24
Finished Apr 23 01:22:29 PM PDT 24
Peak memory 211864 kb
Host smart-fd812ab5-f66e-44fb-92de-acc0817da6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440539016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.1440539016
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.2011731542
Short name T549
Test name
Test status
Simulation time 733106568 ps
CPU time 3.95 seconds
Started Apr 23 01:22:10 PM PDT 24
Finished Apr 23 01:22:15 PM PDT 24
Peak memory 211960 kb
Host smart-58bcb68a-4e9c-4c08-b58f-aa8cb541d757
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011731542 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2011731542
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.2612405852
Short name T605
Test name
Test status
Simulation time 10102015576 ps
CPU time 29.75 seconds
Started Apr 23 01:22:10 PM PDT 24
Finished Apr 23 01:22:41 PM PDT 24
Peak memory 345608 kb
Host smart-7dc1e5c5-89b5-4137-87db-7a4febabbace
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612405852 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.2612405852
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.824094361
Short name T635
Test name
Test status
Simulation time 10130207422 ps
CPU time 19.24 seconds
Started Apr 23 01:22:08 PM PDT 24
Finished Apr 23 01:22:28 PM PDT 24
Peak memory 294116 kb
Host smart-9f2e4a5c-824f-4838-a0fa-feab50912ac3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824094361 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_fifo_reset_tx.824094361
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.1949010975
Short name T938
Test name
Test status
Simulation time 495760789 ps
CPU time 1.74 seconds
Started Apr 23 01:22:08 PM PDT 24
Finished Apr 23 01:22:11 PM PDT 24
Peak memory 203764 kb
Host smart-2b18a2af-c45b-43b8-b250-3ac8856c45d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949010975 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.1949010975
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.1228911671
Short name T834
Test name
Test status
Simulation time 1641963542 ps
CPU time 7.77 seconds
Started Apr 23 01:22:05 PM PDT 24
Finished Apr 23 01:22:13 PM PDT 24
Peak memory 219932 kb
Host smart-99c5bbde-f7e2-4510-9b42-0905f23de00b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228911671 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.1228911671
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.619181251
Short name T94
Test name
Test status
Simulation time 10400589074 ps
CPU time 2.92 seconds
Started Apr 23 01:22:05 PM PDT 24
Finished Apr 23 01:22:09 PM PDT 24
Peak memory 203712 kb
Host smart-9d1442ad-92fb-4b71-a052-9cde397f802a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619181251 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.619181251
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.3122021794
Short name T811
Test name
Test status
Simulation time 807632884 ps
CPU time 12.66 seconds
Started Apr 23 01:22:05 PM PDT 24
Finished Apr 23 01:22:19 PM PDT 24
Peak memory 203636 kb
Host smart-d584d228-01f0-4bef-b1a9-1bec2fd0a826
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122021794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.3122021794
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.2202664070
Short name T1067
Test name
Test status
Simulation time 1039556340 ps
CPU time 42.48 seconds
Started Apr 23 01:22:06 PM PDT 24
Finished Apr 23 01:22:49 PM PDT 24
Peak memory 203748 kb
Host smart-f1b29107-4512-40f0-a090-f4e531322ca2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202664070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.2202664070
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.971011433
Short name T850
Test name
Test status
Simulation time 23579846209 ps
CPU time 13.35 seconds
Started Apr 23 01:22:05 PM PDT 24
Finished Apr 23 01:22:18 PM PDT 24
Peak memory 257016 kb
Host smart-118003fd-0090-43e6-b946-89bbcd559ec2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971011433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_wr.971011433
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.1974675725
Short name T944
Test name
Test status
Simulation time 29990615078 ps
CPU time 757.29 seconds
Started Apr 23 01:22:04 PM PDT 24
Finished Apr 23 01:34:42 PM PDT 24
Peak memory 3811188 kb
Host smart-5b50b660-34f0-45fb-bd6b-d7d1cc3221d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974675725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.1974675725
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.3751194185
Short name T11
Test name
Test status
Simulation time 5617622206 ps
CPU time 6.77 seconds
Started Apr 23 01:22:05 PM PDT 24
Finished Apr 23 01:22:13 PM PDT 24
Peak memory 216496 kb
Host smart-bd2c432c-b1a7-4f39-85c4-d5a22fdb55ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751194185 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.3751194185
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.942325965
Short name T1102
Test name
Test status
Simulation time 19191400 ps
CPU time 0.62 seconds
Started Apr 23 01:22:23 PM PDT 24
Finished Apr 23 01:22:24 PM PDT 24
Peak memory 203328 kb
Host smart-265987e1-a8f0-4845-bc08-18577bedf63c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942325965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.942325965
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1681021203
Short name T245
Test name
Test status
Simulation time 376636140 ps
CPU time 1.54 seconds
Started Apr 23 01:22:11 PM PDT 24
Finished Apr 23 01:22:13 PM PDT 24
Peak memory 212016 kb
Host smart-ecf1483c-f1ab-4abd-9a19-fd975b19cce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681021203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1681021203
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.3807425357
Short name T1075
Test name
Test status
Simulation time 526724492 ps
CPU time 5.64 seconds
Started Apr 23 01:22:11 PM PDT 24
Finished Apr 23 01:22:17 PM PDT 24
Peak memory 255164 kb
Host smart-507548ea-5b16-42d5-98c5-9da0ab4406b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807425357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.3807425357
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.1095060484
Short name T1162
Test name
Test status
Simulation time 2071259803 ps
CPU time 76.01 seconds
Started Apr 23 01:22:12 PM PDT 24
Finished Apr 23 01:23:29 PM PDT 24
Peak memory 695728 kb
Host smart-5e726aab-479d-49c0-9a22-b67bd05ba1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095060484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.1095060484
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.3554477056
Short name T1120
Test name
Test status
Simulation time 22418414940 ps
CPU time 39.19 seconds
Started Apr 23 01:22:13 PM PDT 24
Finished Apr 23 01:22:52 PM PDT 24
Peak memory 537264 kb
Host smart-e26b3bce-fd2e-4731-b6f9-340edf234e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554477056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.3554477056
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.1226386852
Short name T411
Test name
Test status
Simulation time 555244682 ps
CPU time 0.95 seconds
Started Apr 23 01:22:11 PM PDT 24
Finished Apr 23 01:22:13 PM PDT 24
Peak memory 203456 kb
Host smart-0c26ddab-b565-406f-b034-288aa8c6d2e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226386852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.1226386852
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.893969945
Short name T1343
Test name
Test status
Simulation time 175164766 ps
CPU time 5.36 seconds
Started Apr 23 01:22:12 PM PDT 24
Finished Apr 23 01:22:18 PM PDT 24
Peak memory 203680 kb
Host smart-ad21afa8-655f-4268-a913-378b38db25a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893969945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.893969945
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.2750662461
Short name T870
Test name
Test status
Simulation time 3083099862 ps
CPU time 196.14 seconds
Started Apr 23 01:22:11 PM PDT 24
Finished Apr 23 01:25:28 PM PDT 24
Peak memory 932196 kb
Host smart-4353ef22-7d8d-4e49-8e28-966cfbb3d786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750662461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2750662461
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.4251751318
Short name T552
Test name
Test status
Simulation time 243905507 ps
CPU time 10.57 seconds
Started Apr 23 01:22:20 PM PDT 24
Finished Apr 23 01:22:31 PM PDT 24
Peak memory 203660 kb
Host smart-575656f3-aa16-47d5-a22f-61ee22c5fef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251751318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.4251751318
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.2540373330
Short name T518
Test name
Test status
Simulation time 4356719681 ps
CPU time 44.81 seconds
Started Apr 23 01:22:19 PM PDT 24
Finished Apr 23 01:23:04 PM PDT 24
Peak memory 255576 kb
Host smart-71e5d9ab-e369-41dc-858c-7b69b26a4303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540373330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.2540373330
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.2088134727
Short name T1071
Test name
Test status
Simulation time 46012605 ps
CPU time 0.66 seconds
Started Apr 23 01:22:13 PM PDT 24
Finished Apr 23 01:22:14 PM PDT 24
Peak memory 203320 kb
Host smart-563d2540-fc35-4b4b-8025-48116988e88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088134727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.2088134727
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.2003572901
Short name T1057
Test name
Test status
Simulation time 28093307697 ps
CPU time 69.65 seconds
Started Apr 23 01:22:15 PM PDT 24
Finished Apr 23 01:23:25 PM PDT 24
Peak memory 211956 kb
Host smart-e1fa6df2-195b-45c1-b3af-2491173acf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003572901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.2003572901
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1915594127
Short name T711
Test name
Test status
Simulation time 3029613482 ps
CPU time 50.95 seconds
Started Apr 23 01:22:10 PM PDT 24
Finished Apr 23 01:23:01 PM PDT 24
Peak memory 287092 kb
Host smart-63023156-dcb9-4336-9406-37915c3a511f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915594127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1915594127
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.2336483174
Short name T240
Test name
Test status
Simulation time 6712852638 ps
CPU time 345.94 seconds
Started Apr 23 01:22:15 PM PDT 24
Finished Apr 23 01:28:01 PM PDT 24
Peak memory 1661884 kb
Host smart-8c18e9ff-9ab4-449f-9468-5339ec0c8948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336483174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.2336483174
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.2010326397
Short name T1119
Test name
Test status
Simulation time 1516765200 ps
CPU time 15.95 seconds
Started Apr 23 01:22:12 PM PDT 24
Finished Apr 23 01:22:29 PM PDT 24
Peak memory 228124 kb
Host smart-0bde7741-f119-472b-820b-481c18da3296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010326397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.2010326397
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.301633327
Short name T881
Test name
Test status
Simulation time 807271276 ps
CPU time 3.73 seconds
Started Apr 23 01:22:17 PM PDT 24
Finished Apr 23 01:22:22 PM PDT 24
Peak memory 212036 kb
Host smart-0c981189-78ed-4ad3-9dbf-6ae3f6f2bf41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301633327 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.301633327
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.889563108
Short name T956
Test name
Test status
Simulation time 10187168183 ps
CPU time 8.09 seconds
Started Apr 23 01:22:16 PM PDT 24
Finished Apr 23 01:22:25 PM PDT 24
Peak memory 229124 kb
Host smart-1fd44437-a5de-4a1e-bc65-b82aea348344
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889563108 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_acq.889563108
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.2949219441
Short name T566
Test name
Test status
Simulation time 10176179607 ps
CPU time 11.41 seconds
Started Apr 23 01:22:14 PM PDT 24
Finished Apr 23 01:22:26 PM PDT 24
Peak memory 266560 kb
Host smart-e5ad8bce-b8e0-4c0c-b667-9ae08e0ad40f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949219441 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.2949219441
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.2224483321
Short name T705
Test name
Test status
Simulation time 1195444386 ps
CPU time 2.19 seconds
Started Apr 23 01:22:16 PM PDT 24
Finished Apr 23 01:22:19 PM PDT 24
Peak memory 203780 kb
Host smart-1d00b75d-298f-4610-89a3-c62dc193b45c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224483321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.2224483321
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3338978014
Short name T963
Test name
Test status
Simulation time 1549364838 ps
CPU time 6.23 seconds
Started Apr 23 01:22:14 PM PDT 24
Finished Apr 23 01:22:21 PM PDT 24
Peak memory 217992 kb
Host smart-ae5eeec6-c75e-47d1-b03a-542a8776ae01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338978014 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3338978014
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.3527179637
Short name T224
Test name
Test status
Simulation time 2983587350 ps
CPU time 23.82 seconds
Started Apr 23 01:22:18 PM PDT 24
Finished Apr 23 01:22:42 PM PDT 24
Peak memory 839264 kb
Host smart-3f73425c-5918-4be8-8473-753b3a5f1763
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527179637 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.3527179637
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.2893633518
Short name T1189
Test name
Test status
Simulation time 1143086289 ps
CPU time 42.67 seconds
Started Apr 23 01:22:12 PM PDT 24
Finished Apr 23 01:22:55 PM PDT 24
Peak memory 203736 kb
Host smart-73ee9ae1-f7d4-4fa2-bcc6-11aed4481fe7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893633518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.2893633518
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.2484761969
Short name T95
Test name
Test status
Simulation time 242654395 ps
CPU time 9.74 seconds
Started Apr 23 01:22:22 PM PDT 24
Finished Apr 23 01:22:33 PM PDT 24
Peak memory 203696 kb
Host smart-a5999800-11e0-4e95-8d09-0acd45432f8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484761969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.2484761969
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.317279116
Short name T1279
Test name
Test status
Simulation time 56087556000 ps
CPU time 181.84 seconds
Started Apr 23 01:22:12 PM PDT 24
Finished Apr 23 01:25:15 PM PDT 24
Peak memory 2085636 kb
Host smart-9a04e5df-bb85-477d-8d87-c877eca33787
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317279116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_
target_stress_wr.317279116
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.3321254009
Short name T241
Test name
Test status
Simulation time 16290303439 ps
CPU time 833.05 seconds
Started Apr 23 01:22:16 PM PDT 24
Finished Apr 23 01:36:10 PM PDT 24
Peak memory 3952912 kb
Host smart-c5f9abe8-5f7e-4fd0-9c5c-6fce74f669b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321254009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.3321254009
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.3849117556
Short name T577
Test name
Test status
Simulation time 2819361639 ps
CPU time 6.68 seconds
Started Apr 23 01:22:18 PM PDT 24
Finished Apr 23 01:22:25 PM PDT 24
Peak memory 220004 kb
Host smart-275558dc-09ee-4291-89bd-e0c680bd18fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849117556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.3849117556
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.2277728536
Short name T606
Test name
Test status
Simulation time 49985021 ps
CPU time 0.58 seconds
Started Apr 23 01:22:25 PM PDT 24
Finished Apr 23 01:22:26 PM PDT 24
Peak memory 203392 kb
Host smart-a0a1f86f-6020-4dd5-9978-f3c433e544ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277728536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2277728536
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.3872456290
Short name T254
Test name
Test status
Simulation time 68473374 ps
CPU time 1.21 seconds
Started Apr 23 01:22:19 PM PDT 24
Finished Apr 23 01:22:21 PM PDT 24
Peak memory 211956 kb
Host smart-f3a9a263-16a5-4e09-8ec9-158b75aee82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872456290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.3872456290
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.133116374
Short name T1203
Test name
Test status
Simulation time 382279553 ps
CPU time 4.91 seconds
Started Apr 23 01:22:19 PM PDT 24
Finished Apr 23 01:22:24 PM PDT 24
Peak memory 232296 kb
Host smart-502d35bc-77d8-4c52-af1f-6dd3a4953482
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133116374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.133116374
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.3967296248
Short name T85
Test name
Test status
Simulation time 6530885213 ps
CPU time 40.18 seconds
Started Apr 23 01:22:20 PM PDT 24
Finished Apr 23 01:23:01 PM PDT 24
Peak memory 421960 kb
Host smart-869ace87-b7ce-4569-9ddf-36f22fb6902f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967296248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.3967296248
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.3515330037
Short name T1117
Test name
Test status
Simulation time 7519225841 ps
CPU time 45.4 seconds
Started Apr 23 01:22:18 PM PDT 24
Finished Apr 23 01:23:04 PM PDT 24
Peak memory 584540 kb
Host smart-2e8d78ef-d230-4afb-8ba3-ad4c605f125e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515330037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.3515330037
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.1023879382
Short name T73
Test name
Test status
Simulation time 149312560 ps
CPU time 0.78 seconds
Started Apr 23 01:22:20 PM PDT 24
Finished Apr 23 01:22:22 PM PDT 24
Peak memory 203452 kb
Host smart-0fff03ee-f9e7-41cd-a70d-0e146d1440f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023879382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.1023879382
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.260275734
Short name T1348
Test name
Test status
Simulation time 151972060 ps
CPU time 3.73 seconds
Started Apr 23 01:22:22 PM PDT 24
Finished Apr 23 01:22:26 PM PDT 24
Peak memory 203732 kb
Host smart-5bb2a09f-2837-4afb-ae92-c73f2249617b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260275734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.260275734
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3951352325
Short name T234
Test name
Test status
Simulation time 2440928390 ps
CPU time 71.28 seconds
Started Apr 23 01:22:17 PM PDT 24
Finished Apr 23 01:23:29 PM PDT 24
Peak memory 810084 kb
Host smart-8b79a97b-db27-479c-bb55-186a75cb243b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951352325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3951352325
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.3958864333
Short name T875
Test name
Test status
Simulation time 1138794761 ps
CPU time 12.21 seconds
Started Apr 23 01:22:26 PM PDT 24
Finished Apr 23 01:22:39 PM PDT 24
Peak memory 203620 kb
Host smart-7b2a88a4-88d7-42e7-af36-0be5de71a00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958864333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3958864333
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.2203555287
Short name T856
Test name
Test status
Simulation time 3966487008 ps
CPU time 17.32 seconds
Started Apr 23 01:22:27 PM PDT 24
Finished Apr 23 01:22:44 PM PDT 24
Peak memory 265616 kb
Host smart-a3ac14d6-0e7e-4133-9c6a-b49714814161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203555287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.2203555287
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.2058199012
Short name T1042
Test name
Test status
Simulation time 16407833 ps
CPU time 0.64 seconds
Started Apr 23 01:22:20 PM PDT 24
Finished Apr 23 01:22:22 PM PDT 24
Peak memory 203320 kb
Host smart-7dc8200f-8ff8-43d7-b05d-3da8d1faad6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058199012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.2058199012
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.3684292950
Short name T659
Test name
Test status
Simulation time 1126555555 ps
CPU time 23.22 seconds
Started Apr 23 01:22:19 PM PDT 24
Finished Apr 23 01:22:43 PM PDT 24
Peak memory 220028 kb
Host smart-bb265850-5772-449d-aa98-0b2336e7a73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684292950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.3684292950
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.2885303658
Short name T942
Test name
Test status
Simulation time 1132210906 ps
CPU time 59.35 seconds
Started Apr 23 01:22:18 PM PDT 24
Finished Apr 23 01:23:18 PM PDT 24
Peak memory 350656 kb
Host smart-7d15fd84-1466-428b-8796-175b6b63441c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885303658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2885303658
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.3865647328
Short name T868
Test name
Test status
Simulation time 6936816565 ps
CPU time 189.42 seconds
Started Apr 23 01:22:22 PM PDT 24
Finished Apr 23 01:25:32 PM PDT 24
Peak memory 1177428 kb
Host smart-291bf7ca-464e-4c86-b126-2b021b93b9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865647328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.3865647328
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.3621564279
Short name T1338
Test name
Test status
Simulation time 758100452 ps
CPU time 6.51 seconds
Started Apr 23 01:22:23 PM PDT 24
Finished Apr 23 01:22:30 PM PDT 24
Peak memory 212956 kb
Host smart-394d299f-33c2-47a1-af60-3c0d7031e5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621564279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.3621564279
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.3790157011
Short name T368
Test name
Test status
Simulation time 2656401461 ps
CPU time 5.91 seconds
Started Apr 23 01:22:28 PM PDT 24
Finished Apr 23 01:22:34 PM PDT 24
Peak memory 216600 kb
Host smart-a26a23b6-3fd2-4827-9ce0-10e5ba427830
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790157011 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3790157011
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2669692259
Short name T970
Test name
Test status
Simulation time 10549143500 ps
CPU time 12.63 seconds
Started Apr 23 01:22:22 PM PDT 24
Finished Apr 23 01:22:35 PM PDT 24
Peak memory 256916 kb
Host smart-30c4e168-8b40-436d-9222-836166cf1d19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669692259 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2669692259
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.3174642342
Short name T327
Test name
Test status
Simulation time 10266135392 ps
CPU time 12.85 seconds
Started Apr 23 01:22:25 PM PDT 24
Finished Apr 23 01:22:38 PM PDT 24
Peak memory 277236 kb
Host smart-2b9c46c8-adbf-45b2-ae76-d635106b9416
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174642342 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.3174642342
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.1947230771
Short name T625
Test name
Test status
Simulation time 402802782 ps
CPU time 2.63 seconds
Started Apr 23 01:22:25 PM PDT 24
Finished Apr 23 01:22:29 PM PDT 24
Peak memory 203660 kb
Host smart-3ebfc8f8-ddd8-4382-963c-93e14972036d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947230771 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.1947230771
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1828765417
Short name T315
Test name
Test status
Simulation time 3261105682 ps
CPU time 4.46 seconds
Started Apr 23 01:22:23 PM PDT 24
Finished Apr 23 01:22:28 PM PDT 24
Peak memory 203828 kb
Host smart-99a02643-1dc3-48d7-a44b-05fe5e1d3113
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828765417 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1828765417
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.3476054774
Short name T287
Test name
Test status
Simulation time 7189751895 ps
CPU time 94.22 seconds
Started Apr 23 01:22:23 PM PDT 24
Finished Apr 23 01:23:58 PM PDT 24
Peak memory 1859932 kb
Host smart-afdc8975-dec2-4888-84ff-00efdff23ebc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476054774 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.3476054774
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.327448386
Short name T486
Test name
Test status
Simulation time 4269059236 ps
CPU time 13.95 seconds
Started Apr 23 01:22:23 PM PDT 24
Finished Apr 23 01:22:37 PM PDT 24
Peak memory 203716 kb
Host smart-985bf25e-a6ea-4bc6-ab3c-e08e61416268
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327448386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_targ
et_smoke.327448386
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.699110550
Short name T1073
Test name
Test status
Simulation time 352612645 ps
CPU time 6.71 seconds
Started Apr 23 01:22:24 PM PDT 24
Finished Apr 23 01:22:31 PM PDT 24
Peak memory 203680 kb
Host smart-9442b0a0-de6f-42c8-bd8a-872fd53b5a41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699110550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_rd.699110550
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.390194603
Short name T994
Test name
Test status
Simulation time 66236311385 ps
CPU time 214.88 seconds
Started Apr 23 01:22:21 PM PDT 24
Finished Apr 23 01:25:56 PM PDT 24
Peak memory 2248784 kb
Host smart-6f91bf98-3108-4bd0-9023-3c9b18eb066b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390194603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_wr.390194603
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.3463462291
Short name T383
Test name
Test status
Simulation time 7686901675 ps
CPU time 136.94 seconds
Started Apr 23 01:22:21 PM PDT 24
Finished Apr 23 01:24:39 PM PDT 24
Peak memory 1477688 kb
Host smart-5c86fa25-f9d0-4f9a-a03a-a2e5a85659a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463462291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.3463462291
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.2740874043
Short name T861
Test name
Test status
Simulation time 5622222117 ps
CPU time 6.82 seconds
Started Apr 23 01:22:21 PM PDT 24
Finished Apr 23 01:22:29 PM PDT 24
Peak memory 211984 kb
Host smart-241fdb2e-0669-4ac2-828f-6e81537d9628
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740874043 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.2740874043
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.3818964288
Short name T627
Test name
Test status
Simulation time 21983524 ps
CPU time 0.62 seconds
Started Apr 23 01:22:36 PM PDT 24
Finished Apr 23 01:22:37 PM PDT 24
Peak memory 203300 kb
Host smart-c6cdbccd-7f4d-4360-a29e-79499323c09a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818964288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.3818964288
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.351097254
Short name T897
Test name
Test status
Simulation time 137424874 ps
CPU time 1.44 seconds
Started Apr 23 01:22:34 PM PDT 24
Finished Apr 23 01:22:36 PM PDT 24
Peak memory 212020 kb
Host smart-409351ba-c119-4260-b19d-250a53b50e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351097254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.351097254
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.723678182
Short name T530
Test name
Test status
Simulation time 2999536812 ps
CPU time 12.2 seconds
Started Apr 23 01:22:28 PM PDT 24
Finished Apr 23 01:22:41 PM PDT 24
Peak memory 248820 kb
Host smart-8ebeba27-0099-49b0-a9a4-f5534178ed26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723678182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty
.723678182
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.2306249981
Short name T348
Test name
Test status
Simulation time 2262971675 ps
CPU time 167.44 seconds
Started Apr 23 01:22:29 PM PDT 24
Finished Apr 23 01:25:17 PM PDT 24
Peak memory 747284 kb
Host smart-7a74b040-dc0e-4944-a1e8-1b04cdf68576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306249981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2306249981
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.4216060151
Short name T1226
Test name
Test status
Simulation time 3519302818 ps
CPU time 50.17 seconds
Started Apr 23 01:22:28 PM PDT 24
Finished Apr 23 01:23:18 PM PDT 24
Peak memory 585856 kb
Host smart-0476706a-5e22-45e6-8aa6-c5c7abee3a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216060151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.4216060151
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.1587531478
Short name T1128
Test name
Test status
Simulation time 385666453 ps
CPU time 0.96 seconds
Started Apr 23 01:22:27 PM PDT 24
Finished Apr 23 01:22:29 PM PDT 24
Peak memory 203372 kb
Host smart-59ec8ee1-1503-4ee0-83a2-55fded94e6cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587531478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.1587531478
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.2785557015
Short name T428
Test name
Test status
Simulation time 125035726 ps
CPU time 6.8 seconds
Started Apr 23 01:22:28 PM PDT 24
Finished Apr 23 01:22:35 PM PDT 24
Peak memory 220544 kb
Host smart-f2b0fad8-b23a-4cd9-8500-0e76dc2b3345
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785557015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
2785557015
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.653636029
Short name T974
Test name
Test status
Simulation time 5855510418 ps
CPU time 109.43 seconds
Started Apr 23 01:22:29 PM PDT 24
Finished Apr 23 01:24:19 PM PDT 24
Peak memory 1253908 kb
Host smart-afb3e211-0830-4b60-b4f9-390dcc5a93e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653636029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.653636029
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.174934347
Short name T1294
Test name
Test status
Simulation time 381689725 ps
CPU time 5.85 seconds
Started Apr 23 01:22:36 PM PDT 24
Finished Apr 23 01:22:43 PM PDT 24
Peak memory 203652 kb
Host smart-6f7d3620-6c38-424a-879b-37831a5e814a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174934347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.174934347
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.394937232
Short name T103
Test name
Test status
Simulation time 1378098781 ps
CPU time 66.29 seconds
Started Apr 23 01:22:35 PM PDT 24
Finished Apr 23 01:23:42 PM PDT 24
Peak memory 352364 kb
Host smart-367d431a-21c6-436f-8b6d-47eeb3de10c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394937232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.394937232
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.1892516765
Short name T124
Test name
Test status
Simulation time 213597057 ps
CPU time 0.65 seconds
Started Apr 23 01:22:29 PM PDT 24
Finished Apr 23 01:22:30 PM PDT 24
Peak memory 203340 kb
Host smart-a5790f87-38fc-4196-ac96-69d366d1c19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892516765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.1892516765
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.2505587758
Short name T655
Test name
Test status
Simulation time 3422610827 ps
CPU time 15.63 seconds
Started Apr 23 01:22:30 PM PDT 24
Finished Apr 23 01:22:46 PM PDT 24
Peak memory 212820 kb
Host smart-31725b8f-17ef-44c8-ab85-4512a0a3f02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505587758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.2505587758
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.613853900
Short name T302
Test name
Test status
Simulation time 1694824710 ps
CPU time 24.93 seconds
Started Apr 23 01:22:26 PM PDT 24
Finished Apr 23 01:22:52 PM PDT 24
Peak memory 325428 kb
Host smart-bd14e87a-1f08-41ad-9939-b360bb53487e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613853900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.613853900
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.1471993688
Short name T227
Test name
Test status
Simulation time 43582105378 ps
CPU time 467.77 seconds
Started Apr 23 01:22:34 PM PDT 24
Finished Apr 23 01:30:23 PM PDT 24
Peak memory 1524728 kb
Host smart-f1121a50-d682-487c-972e-2a7573e3740f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471993688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.1471993688
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.1331193739
Short name T274
Test name
Test status
Simulation time 479883466 ps
CPU time 7.38 seconds
Started Apr 23 01:22:32 PM PDT 24
Finished Apr 23 01:22:39 PM PDT 24
Peak memory 228240 kb
Host smart-7a2d3d96-fb10-4ea8-9cea-7a8f60671522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331193739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.1331193739
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.3513563557
Short name T1174
Test name
Test status
Simulation time 1027401849 ps
CPU time 4.31 seconds
Started Apr 23 01:22:34 PM PDT 24
Finished Apr 23 01:22:40 PM PDT 24
Peak memory 211948 kb
Host smart-b0edb181-1e4c-4d0c-8985-53483dd6abc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513563557 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3513563557
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.509410663
Short name T914
Test name
Test status
Simulation time 10051910140 ps
CPU time 60.06 seconds
Started Apr 23 01:22:33 PM PDT 24
Finished Apr 23 01:23:34 PM PDT 24
Peak memory 452556 kb
Host smart-c9be9986-27e3-4fac-9484-5442e4eb54e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509410663 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_acq.509410663
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2017676618
Short name T965
Test name
Test status
Simulation time 11378859164 ps
CPU time 5.66 seconds
Started Apr 23 01:22:30 PM PDT 24
Finished Apr 23 01:22:36 PM PDT 24
Peak memory 239464 kb
Host smart-e5ba4110-5e31-4d87-8665-2fe5270b4059
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017676618 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2017676618
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.2318120340
Short name T29
Test name
Test status
Simulation time 1454217676 ps
CPU time 2.59 seconds
Started Apr 23 01:22:34 PM PDT 24
Finished Apr 23 01:22:37 PM PDT 24
Peak memory 203668 kb
Host smart-b073c187-5cfd-4311-b0d7-6f933812729b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318120340 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.2318120340
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.515312333
Short name T1286
Test name
Test status
Simulation time 5492636230 ps
CPU time 6.19 seconds
Started Apr 23 01:22:34 PM PDT 24
Finished Apr 23 01:22:41 PM PDT 24
Peak memory 211892 kb
Host smart-e6209085-3fac-4823-b54f-5bb709cb404c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515312333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_intr_smoke.515312333
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.2329132265
Short name T1148
Test name
Test status
Simulation time 28799485926 ps
CPU time 78.84 seconds
Started Apr 23 01:22:31 PM PDT 24
Finished Apr 23 01:23:50 PM PDT 24
Peak memory 1580304 kb
Host smart-39758083-98d4-46c4-aa0e-d0856951be65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329132265 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.2329132265
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.3578002161
Short name T668
Test name
Test status
Simulation time 711302743 ps
CPU time 9.31 seconds
Started Apr 23 01:22:34 PM PDT 24
Finished Apr 23 01:22:44 PM PDT 24
Peak memory 203688 kb
Host smart-54737a43-283b-4a75-8881-f66525f046a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578002161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.3578002161
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.1813437469
Short name T609
Test name
Test status
Simulation time 770113527 ps
CPU time 6.58 seconds
Started Apr 23 01:22:36 PM PDT 24
Finished Apr 23 01:22:43 PM PDT 24
Peak memory 203696 kb
Host smart-ce0f1b7f-9f7d-4af3-9e34-d16a9166750c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813437469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.1813437469
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.3051002612
Short name T24
Test name
Test status
Simulation time 25524840119 ps
CPU time 17.47 seconds
Started Apr 23 01:22:34 PM PDT 24
Finished Apr 23 01:22:52 PM PDT 24
Peak memory 378836 kb
Host smart-8fdffde7-3f17-42a7-8c56-50b6c3163e07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051002612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.3051002612
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.289447671
Short name T925
Test name
Test status
Simulation time 29900885606 ps
CPU time 2228 seconds
Started Apr 23 01:22:34 PM PDT 24
Finished Apr 23 01:59:43 PM PDT 24
Peak memory 7023188 kb
Host smart-bb18e02f-1b73-48db-a0a2-c81922202fd6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289447671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_ta
rget_stretch.289447671
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.187473080
Short name T702
Test name
Test status
Simulation time 1278541745 ps
CPU time 7.02 seconds
Started Apr 23 01:22:32 PM PDT 24
Finished Apr 23 01:22:40 PM PDT 24
Peak memory 217728 kb
Host smart-2f7a99bc-e79e-4cc4-a268-704114ee98af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187473080 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_timeout.187473080
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.873221169
Short name T325
Test name
Test status
Simulation time 16152212 ps
CPU time 0.6 seconds
Started Apr 23 01:22:47 PM PDT 24
Finished Apr 23 01:22:48 PM PDT 24
Peak memory 203328 kb
Host smart-0c8e2a11-10b6-4446-8375-198ab6a251dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873221169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.873221169
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1174685805
Short name T356
Test name
Test status
Simulation time 192424834 ps
CPU time 1.65 seconds
Started Apr 23 01:22:43 PM PDT 24
Finished Apr 23 01:22:45 PM PDT 24
Peak memory 203800 kb
Host smart-4f86d80a-0fa5-43aa-8327-c73c337275d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174685805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1174685805
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.2057848003
Short name T288
Test name
Test status
Simulation time 110745308 ps
CPU time 2.5 seconds
Started Apr 23 01:22:39 PM PDT 24
Finished Apr 23 01:22:42 PM PDT 24
Peak memory 215520 kb
Host smart-ffdbfac4-35e2-4723-a015-dc7b57cf1541
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057848003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.2057848003
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.3416796072
Short name T1230
Test name
Test status
Simulation time 1844207545 ps
CPU time 49.11 seconds
Started Apr 23 01:22:39 PM PDT 24
Finished Apr 23 01:23:28 PM PDT 24
Peak memory 517012 kb
Host smart-2a4cbc7b-dc49-4649-af01-e88767c20042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416796072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3416796072
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.2330433762
Short name T266
Test name
Test status
Simulation time 29633508329 ps
CPU time 59.97 seconds
Started Apr 23 01:22:37 PM PDT 24
Finished Apr 23 01:23:38 PM PDT 24
Peak memory 719656 kb
Host smart-28c9c119-1308-4f28-b4f9-bcbeb46b6ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330433762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.2330433762
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.1642080234
Short name T647
Test name
Test status
Simulation time 200572342 ps
CPU time 0.96 seconds
Started Apr 23 01:22:37 PM PDT 24
Finished Apr 23 01:22:38 PM PDT 24
Peak memory 203392 kb
Host smart-a0f6dd3a-4b7b-4c31-855b-accbfe5aa584
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642080234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.1642080234
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.1504748130
Short name T1002
Test name
Test status
Simulation time 1758391473 ps
CPU time 9.62 seconds
Started Apr 23 01:22:37 PM PDT 24
Finished Apr 23 01:22:47 PM PDT 24
Peak memory 235036 kb
Host smart-71a100e8-1e62-440f-83f3-22dd52a91b46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504748130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
1504748130
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.3100352894
Short name T828
Test name
Test status
Simulation time 7470491987 ps
CPU time 274.41 seconds
Started Apr 23 01:22:38 PM PDT 24
Finished Apr 23 01:27:13 PM PDT 24
Peak memory 1094064 kb
Host smart-5b311c98-e88b-4a94-bce0-ed1bf8f06a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100352894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.3100352894
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.3665131908
Short name T1098
Test name
Test status
Simulation time 575333034 ps
CPU time 4.45 seconds
Started Apr 23 01:22:52 PM PDT 24
Finished Apr 23 01:22:57 PM PDT 24
Peak memory 203668 kb
Host smart-81d741c0-e6c8-4663-b666-1015fa7e482c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665131908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.3665131908
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.1238703781
Short name T1184
Test name
Test status
Simulation time 3485882145 ps
CPU time 89.82 seconds
Started Apr 23 01:22:47 PM PDT 24
Finished Apr 23 01:24:18 PM PDT 24
Peak memory 417860 kb
Host smart-29e06a11-8506-4857-aff8-1bea8144cb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238703781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.1238703781
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.4111246077
Short name T443
Test name
Test status
Simulation time 19272461 ps
CPU time 0.67 seconds
Started Apr 23 01:22:39 PM PDT 24
Finished Apr 23 01:22:40 PM PDT 24
Peak memory 203252 kb
Host smart-078cac53-fc38-46eb-ac3b-3a9e68d2fa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111246077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.4111246077
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.2195926937
Short name T924
Test name
Test status
Simulation time 3805835424 ps
CPU time 68.51 seconds
Started Apr 23 01:22:39 PM PDT 24
Finished Apr 23 01:23:48 PM PDT 24
Peak memory 408360 kb
Host smart-eb766755-4b81-4588-8b58-bdc9ba8b1f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195926937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2195926937
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.2691059924
Short name T1145
Test name
Test status
Simulation time 2751209987 ps
CPU time 77.1 seconds
Started Apr 23 01:22:34 PM PDT 24
Finished Apr 23 01:23:52 PM PDT 24
Peak memory 441620 kb
Host smart-221404c6-7e63-46a6-a5e4-6bd20e07fe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691059924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2691059924
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.3466099295
Short name T479
Test name
Test status
Simulation time 5943962520 ps
CPU time 9.41 seconds
Started Apr 23 01:22:37 PM PDT 24
Finished Apr 23 01:22:47 PM PDT 24
Peak memory 217124 kb
Host smart-08bad957-9252-40f9-8aba-222ce6b2b6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466099295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.3466099295
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.1286010873
Short name T1323
Test name
Test status
Simulation time 890342961 ps
CPU time 4.69 seconds
Started Apr 23 01:22:46 PM PDT 24
Finished Apr 23 01:22:52 PM PDT 24
Peak memory 211948 kb
Host smart-fda565f7-e3e2-48e1-9103-09f9c9997cb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286010873 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.1286010873
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.1660649418
Short name T51
Test name
Test status
Simulation time 10080234499 ps
CPU time 77.55 seconds
Started Apr 23 01:22:44 PM PDT 24
Finished Apr 23 01:24:02 PM PDT 24
Peak memory 524164 kb
Host smart-27cda8cc-aa39-4a8a-807c-f9f0f4968202
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660649418 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.1660649418
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.2640452181
Short name T547
Test name
Test status
Simulation time 10097703972 ps
CPU time 69.69 seconds
Started Apr 23 01:22:45 PM PDT 24
Finished Apr 23 01:23:55 PM PDT 24
Peak memory 532008 kb
Host smart-39686783-3b7c-4365-bc4f-55c2f815b9c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640452181 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.2640452181
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.4130256599
Short name T212
Test name
Test status
Simulation time 747093450 ps
CPU time 2.37 seconds
Started Apr 23 01:22:45 PM PDT 24
Finished Apr 23 01:22:47 PM PDT 24
Peak memory 203648 kb
Host smart-28c8e4a6-8f79-47ae-84f0-e13818621e0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130256599 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.4130256599
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.3222905464
Short name T543
Test name
Test status
Simulation time 7427490319 ps
CPU time 3.1 seconds
Started Apr 23 01:22:41 PM PDT 24
Finished Apr 23 01:22:44 PM PDT 24
Peak memory 203716 kb
Host smart-3ebd736e-0ba9-4bb9-aa49-e747909fffa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222905464 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.3222905464
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.3435554262
Short name T795
Test name
Test status
Simulation time 4416199965 ps
CPU time 41 seconds
Started Apr 23 01:22:42 PM PDT 24
Finished Apr 23 01:23:23 PM PDT 24
Peak memory 1209696 kb
Host smart-3a236d2d-21a1-4a05-9739-fb284fd41771
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435554262 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.3435554262
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.3393739811
Short name T689
Test name
Test status
Simulation time 1876172675 ps
CPU time 34.99 seconds
Started Apr 23 01:22:43 PM PDT 24
Finished Apr 23 01:23:18 PM PDT 24
Peak memory 203688 kb
Host smart-f4aabc39-010c-4ca9-8185-33e0b162d3a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393739811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.3393739811
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.2866985446
Short name T736
Test name
Test status
Simulation time 898305103 ps
CPU time 16.71 seconds
Started Apr 23 01:22:41 PM PDT 24
Finished Apr 23 01:22:58 PM PDT 24
Peak memory 210656 kb
Host smart-be201c11-b3a5-4dfd-bd46-59c1c876dc7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866985446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.2866985446
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.2340006429
Short name T742
Test name
Test status
Simulation time 19273046445 ps
CPU time 10.11 seconds
Started Apr 23 01:22:42 PM PDT 24
Finished Apr 23 01:22:53 PM PDT 24
Peak memory 203756 kb
Host smart-de641b6e-0a5e-4f2b-969f-0f8e17cdfb71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340006429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.2340006429
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.1238398733
Short name T988
Test name
Test status
Simulation time 5078218803 ps
CPU time 361.96 seconds
Started Apr 23 01:22:43 PM PDT 24
Finished Apr 23 01:28:45 PM PDT 24
Peak memory 1322644 kb
Host smart-4415a0b5-3cbc-4a6b-a79b-fceb909be912
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238398733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.1238398733
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.1923122690
Short name T1047
Test name
Test status
Simulation time 3867301331 ps
CPU time 7.15 seconds
Started Apr 23 01:22:44 PM PDT 24
Finished Apr 23 01:22:52 PM PDT 24
Peak memory 212000 kb
Host smart-21df91ee-572a-4344-a7df-53ec853fd95d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923122690 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.1923122690
Directory /workspace/9.i2c_target_timeout/latest
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