Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	939065	1			T1	20		T2	171		T3	301
all_values[1]	939065	1			T1	20		T2	171		T3	301
all_values[2]	939065	1			T1	20		T2	171		T3	301
all_values[3]	939065	1			T1	20		T2	171		T3	301
all_values[4]	939065	1			T1	20		T2	171		T3	301
all_values[5]	939065	1			T1	20		T2	171		T3	301
all_values[6]	939065	1			T1	20		T2	171		T3	301
all_values[7]	939065	1			T1	20		T2	171		T3	301
all_values[8]	939065	1			T1	20		T2	171		T3	301
all_values[9]	939065	1			T1	20		T2	171		T3	301
all_values[10]	939065	1			T1	20		T2	171		T3	301
all_values[11]	939065	1			T1	20		T2	171		T3	301
all_values[12]	939065	1			T1	20		T2	171		T3	301
all_values[13]	939065	1			T1	20		T2	171		T3	301
all_values[14]	939065	1			T1	20		T2	171		T3	301

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9998462

1

T1

259

T2

2133

T3

3795

auto[1]

4087513

1

T1

41

T2

432

T3

720

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11793111

1

T1

300

T2

2565

T3

4515

auto[1]

2292864

1

T42

126935

T71

8639

T77

308645

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12] , all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	82528	1			T1	5		T2	3		T3	7
all_values[0]	auto[0]	auto[1]	17854	1			T42	640		T71	34		T77	944
all_values[0]	auto[1]	auto[0]	704667	1			T1	15		T2	168		T3	294
all_values[0]	auto[1]	auto[1]	134016	1			T42	7822		T71	542		T77	19651
all_values[1]	auto[0]	auto[0]	775239	1			T1	20		T2	171		T3	301
all_values[1]	auto[0]	auto[1]	163055	1			T42	8447		T71	572		T77	20590
all_values[1]	auto[1]	auto[0]	351	1			T57	7		T66	1		T44	1
all_values[1]	auto[1]	auto[1]	420	1			T42	13		T71	4		T77	6
all_values[2]	auto[0]	auto[0]	799290	1			T1	20		T2	171		T3	301
all_values[2]	auto[0]	auto[1]	139512	1			T42	8459		T71	569		T77	20589
all_values[2]	auto[1]	auto[1]	263	1			T42	4		T71	8		T77	6
all_values[3]	auto[0]	auto[0]	783432	1			T1	20		T2	171		T3	301
all_values[3]	auto[0]	auto[1]	155338	1			T42	8458		T71	570		T77	20588
all_values[3]	auto[1]	auto[1]	295	1			T42	4		T71	6		T77	8
all_values[4]	auto[0]	auto[0]	771412	1			T1	20		T2	171		T3	301
all_values[4]	auto[0]	auto[1]	167380	1			T42	8457		T71	569		T77	20302
all_values[4]	auto[1]	auto[0]	17	1			T188	1		T189	1		T190	1
all_values[4]	auto[1]	auto[1]	256	1			T42	1		T71	6		T77	4
all_values[5]	auto[0]	auto[0]	789618	1			T1	20		T2	171		T3	301
all_values[5]	auto[0]	auto[1]	149160	1			T42	8460		T71	565		T77	20592
all_values[5]	auto[1]	auto[1]	287	1			T42	3		T71	8		T77	4
all_values[6]	auto[0]	auto[0]	166189	1			T1	18		T2	161		T3	284
all_values[6]	auto[0]	auto[1]	26543	1			T42	613		T71	561		T77	336
all_values[6]	auto[1]	auto[0]	604941	1			T1	2		T2	10		T3	17
all_values[6]	auto[1]	auto[1]	141392	1			T42	7850		T71	16		T77	20260
all_values[7]	auto[0]	auto[0]	756354	1			T1	16		T2	123		T3	251
all_values[7]	auto[0]	auto[1]	152551	1			T42	7997		T71	428		T77	20321
all_values[7]	auto[1]	auto[0]	25427	1			T1	4		T2	48		T3	50
all_values[7]	auto[1]	auto[1]	4733	1			T42	466		T71	147		T77	275
all_values[8]	auto[0]	auto[0]	133385	1			T1	16		T2	145		T3	263
all_values[8]	auto[0]	auto[1]	21957	1			T42	546		T71	423		T77	359
all_values[8]	auto[1]	auto[0]	651448	1			T1	4		T2	26		T3	38
all_values[8]	auto[1]	auto[1]	132275	1			T42	7917		T71	153		T77	20237
all_values[9]	auto[0]	auto[0]	161729	1			T1	19		T2	160		T3	277
all_values[9]	auto[0]	auto[1]	27129	1			T42	702		T71	567		T77	613
all_values[9]	auto[1]	auto[0]	621696	1			T1	1		T2	11		T3	24
all_values[9]	auto[1]	auto[1]	128511	1			T42	7761		T71	8		T77	19983
all_values[10]	auto[0]	auto[0]	781376	1			T1	20		T2	171		T3	301
all_values[10]	auto[0]	auto[1]	157440	1			T42	8458		T71	570		T77	20593
all_values[10]	auto[1]	auto[1]	249	1			T42	5		T71	7		T77	3
all_values[11]	auto[0]	auto[0]	2865	1			T1	5		T2	2		T3	4
all_values[11]	auto[0]	auto[1]	729	1			T42	18		T71	16		T77	41
all_values[11]	auto[1]	auto[0]	780580	1			T1	15		T2	169		T3	297
all_values[11]	auto[1]	auto[1]	154891	1			T42	8445		T71	561		T77	20555
all_values[12]	auto[0]	auto[0]	817151	1			T1	20		T2	171		T3	301
all_values[12]	auto[0]	auto[1]	121660	1			T42	8459		T71	571		T77	20591
all_values[12]	auto[1]	auto[1]	254	1			T42	4		T71	6		T77	4
all_values[13]	auto[0]	auto[0]	783892	1			T1	20		T2	171		T3	301
all_values[13]	auto[0]	auto[1]	154894	1			T42	8457		T71	569		T77	20591
all_values[13]	auto[1]	auto[1]	279	1			T42	6		T71	8		T77	3
all_values[14]	auto[0]	auto[0]	799524	1			T1	20		T2	171		T3	301
all_values[14]	auto[0]	auto[1]	139276	1			T42	8458		T71	567		T77	20593
all_values[14]	auto[1]	auto[1]	265	1			T42	5		T71	8		T77	3