Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	939065	1			T1	20		T2	171		T3	301
all_pins[1]	939065	1			T1	20		T2	171		T3	301
all_pins[2]	939065	1			T1	20		T2	171		T3	301
all_pins[3]	939065	1			T1	20		T2	171		T3	301
all_pins[4]	939065	1			T1	20		T2	171		T3	301
all_pins[5]	939065	1			T1	20		T2	171		T3	301
all_pins[6]	939065	1			T1	20		T2	171		T3	301
all_pins[7]	939065	1			T1	20		T2	171		T3	301
all_pins[8]	939065	1			T1	20		T2	171		T3	301
all_pins[9]	939065	1			T1	20		T2	171		T3	301
all_pins[10]	939065	1			T1	20		T2	171		T3	301
all_pins[11]	939065	1			T1	20		T2	171		T3	301
all_pins[12]	939065	1			T1	20		T2	171		T3	301
all_pins[13]	939065	1			T1	20		T2	171		T3	301
all_pins[14]	939065	1			T1	20		T2	171		T3	301

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10002490	1			T1	258		T2	2131		T3	3781
values[0x1]	4083485	1			T1	42		T2	434		T3	734
transitions[0x0=>0x1]	3294423	1			T1	39		T2	427		T3	719
transitions[0x1=>0x0]	3293393	1			T1	38		T2	426		T3	718

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	103229	1			T1	5		T2	3		T3	7
all_pins[0]	values[0x1]	835836	1			T1	15		T2	168		T3	294
all_pins[0]	transitions[0x0=>0x1]	835178	1			T1	15		T2	168		T3	294
all_pins[0]	transitions[0x1=>0x0]	107	1			T42	1		T66	1		T71	2
all_pins[1]	values[0x0]	938300	1			T1	20		T2	171		T3	301
all_pins[1]	values[0x1]	765	1			T57	8		T42	15		T66	1
all_pins[1]	transitions[0x0=>0x1]	731	1			T57	8		T42	14		T66	1
all_pins[1]	transitions[0x1=>0x0]	90	1			T71	3		T77	3		T162	3
all_pins[2]	values[0x0]	938941	1			T1	20		T2	171		T3	301
all_pins[2]	values[0x1]	124	1			T42	1		T71	4		T77	3
all_pins[2]	transitions[0x0=>0x1]	99	1			T71	3		T77	1		T151	2
all_pins[2]	transitions[0x1=>0x0]	135	1			T42	2		T71	3		T77	2
all_pins[3]	values[0x0]	938905	1			T1	20		T2	171		T3	301
all_pins[3]	values[0x1]	160	1			T42	3		T71	4		T77	4
all_pins[3]	transitions[0x0=>0x1]	132	1			T42	3		T71	4		T77	4
all_pins[3]	transitions[0x1=>0x0]	118	1			T188	1		T71	3		T77	2
all_pins[4]	values[0x0]	938919	1			T1	20		T2	171		T3	301
all_pins[4]	values[0x1]	146	1			T188	1		T71	3		T77	2
all_pins[4]	transitions[0x0=>0x1]	113	1			T188	1		T71	2		T77	2
all_pins[4]	transitions[0x1=>0x0]	112	1			T42	1		T71	3		T77	1
all_pins[5]	values[0x0]	938920	1			T1	20		T2	171		T3	301
all_pins[5]	values[0x1]	145	1			T42	1		T71	4		T77	1
all_pins[5]	transitions[0x0=>0x1]	102	1			T71	4		T77	1		T151	1
all_pins[5]	transitions[0x1=>0x0]	745945	1			T1	2		T2	10		T3	17
all_pins[6]	values[0x0]	193077	1			T1	18		T2	161		T3	284
all_pins[6]	values[0x1]	745988	1			T1	2		T2	10		T3	17
all_pins[6]	transitions[0x0=>0x1]	727092	1			T1	2		T2	7		T3	13
all_pins[6]	transitions[0x1=>0x0]	14802	1			T1	5		T2	46		T3	59
all_pins[7]	values[0x0]	905367	1			T1	15		T2	122		T3	238
all_pins[7]	values[0x1]	33698	1			T1	5		T2	49		T3	63
all_pins[7]	transitions[0x0=>0x1]	12194	1			T1	3		T2	47		T3	59
all_pins[7]	transitions[0x1=>0x0]	762103	1			T1	2		T2	25		T3	35
all_pins[8]	values[0x0]	155458	1			T1	16		T2	144		T3	262
all_pins[8]	values[0x1]	783607	1			T1	4		T2	27		T3	39
all_pins[8]	transitions[0x0=>0x1]	35965	1			T1	3		T2	25		T3	32
all_pins[8]	transitions[0x1=>0x0]	2445	1			T2	9		T3	17		T4	1
all_pins[9]	values[0x0]	188978	1			T1	19		T2	160		T3	277
all_pins[9]	values[0x1]	750087	1			T1	1		T2	11		T3	24
all_pins[9]	transitions[0x0=>0x1]	750058	1			T1	1		T2	11		T3	24
all_pins[9]	transitions[0x1=>0x0]	78	1			T42	2		T71	1		T77	1
all_pins[10]	values[0x0]	938958	1			T1	20		T2	171		T3	301
all_pins[10]	values[0x1]	107	1			T42	3		T71	2		T77	3
all_pins[10]	transitions[0x0=>0x1]	76	1			T42	2		T71	2		T77	2
all_pins[10]	transitions[0x1=>0x0]	932381	1			T1	15		T2	169		T3	297
all_pins[11]	values[0x0]	6653	1			T1	5		T2	2		T3	4
all_pins[11]	values[0x1]	932412	1			T1	15		T2	169		T3	297
all_pins[11]	transitions[0x0=>0x1]	932376	1			T1	15		T2	169		T3	297
all_pins[11]	transitions[0x1=>0x0]	90	1			T42	3		T71	4		T77	2
all_pins[12]	values[0x0]	938939	1			T1	20		T2	171		T3	301
all_pins[12]	values[0x1]	126	1			T42	3		T71	4		T77	3
all_pins[12]	transitions[0x0=>0x1]	102	1			T42	2		T71	2		T77	3
all_pins[12]	transitions[0x1=>0x0]	126	1			T42	2		T71	3		T77	1
all_pins[13]	values[0x0]	938915	1			T1	20		T2	171		T3	301
all_pins[13]	values[0x1]	150	1			T42	3		T71	5		T77	1
all_pins[13]	transitions[0x0=>0x1]	120	1			T42	2		T71	2		T77	1
all_pins[13]	transitions[0x1=>0x0]	104	1			T42	3		T71	3		T77	3
all_pins[14]	values[0x0]	938931	1			T1	20		T2	171		T3	301
all_pins[14]	values[0x1]	134	1			T42	4		T71	6		T77	3
all_pins[14]	transitions[0x0=>0x1]	85	1			T42	3		T71	3		T77	2
all_pins[14]	transitions[0x1=>0x0]	834757	1			T1	14		T2	167		T3	293