Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	608	1			T42	7		T71	14		T77	11
all_values[1]	608	1			T42	7		T71	14		T77	11
all_values[2]	608	1			T42	7		T71	14		T77	11
all_values[3]	608	1			T42	7		T71	14		T77	11
all_values[4]	608	1			T42	7		T71	14		T77	11
all_values[5]	608	1			T42	7		T71	14		T77	11
all_values[6]	608	1			T42	7		T71	14		T77	11
all_values[7]	608	1			T42	7		T71	14		T77	11
all_values[8]	608	1			T42	7		T71	14		T77	11
all_values[9]	608	1			T42	7		T71	14		T77	11
all_values[10]	608	1			T42	7		T71	14		T77	11
all_values[11]	608	1			T42	7		T71	14		T77	11
all_values[12]	608	1			T42	7		T71	14		T77	11
all_values[13]	608	1			T42	7		T71	14		T77	11
all_values[14]	608	1			T42	7		T71	14		T77	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4830

1

T42

57

T71

111

T77

75

auto[1]

4290

1

T42

48

T71

99

T77

90

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1272

1

T42

10

T71

16

T77

10

auto[1]

7848

1

T42

95

T71

194

T77

155

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5333

1

T42

57

T71

116

T77

95

auto[1]

3787

1

T42

48

T71

94

T77

70

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	45	1			T42	1		T97	2		T219	1
all_values[0]	auto[0]	auto[0]	auto[1]	128	1			T42	1		T71	3		T77	3
all_values[0]	auto[0]	auto[1]	auto[0]	34	1			T71	1		T77	1		T151	1
all_values[0]	auto[0]	auto[1]	auto[1]	146	1			T42	1		T71	2		T77	4
all_values[0]	auto[1]	auto[0]	auto[1]	135	1			T42	4		T71	3		T77	1
all_values[0]	auto[1]	auto[1]	auto[1]	120	1			T71	5		T77	2		T151	1
all_values[1]	auto[0]	auto[0]	auto[0]	60	1			T42	1		T195	6		T164	2
all_values[1]	auto[0]	auto[0]	auto[1]	121	1			T42	3		T71	5		T77	3
all_values[1]	auto[0]	auto[1]	auto[0]	35	1			T42	2		T71	1		T151	2
all_values[1]	auto[0]	auto[1]	auto[1]	136	1			T71	4		T77	2		T151	2
all_values[1]	auto[1]	auto[0]	auto[1]	131	1			T42	1		T71	2		T77	3
all_values[1]	auto[1]	auto[1]	auto[1]	125	1			T71	2		T77	3		T151	3
all_values[2]	auto[0]	auto[0]	auto[0]	42	1			T151	2		T195	1		T186	1
all_values[2]	auto[0]	auto[0]	auto[1]	146	1			T42	3		T71	2		T77	3
all_values[2]	auto[0]	auto[1]	auto[0]	28	1			T77	1		T151	2		T80	2
all_values[2]	auto[0]	auto[1]	auto[1]	129	1			T71	4		T77	1		T151	2
all_values[2]	auto[1]	auto[0]	auto[1]	144	1			T42	4		T71	2		T77	2
all_values[2]	auto[1]	auto[1]	auto[1]	119	1			T71	6		T77	4		T151	1
all_values[3]	auto[0]	auto[0]	auto[0]	41	1			T42	1		T186	2		T97	1
all_values[3]	auto[0]	auto[0]	auto[1]	138	1			T71	5		T77	2		T151	2
all_values[3]	auto[0]	auto[1]	auto[0]	25	1			T71	1		T151	1		T185	1
all_values[3]	auto[0]	auto[1]	auto[1]	142	1			T42	3		T71	3		T77	3
all_values[3]	auto[1]	auto[0]	auto[1]	153	1			T42	1		T71	3		T77	4
all_values[3]	auto[1]	auto[1]	auto[1]	109	1			T42	2		T71	2		T77	2
all_values[4]	auto[0]	auto[0]	auto[0]	57	1			T42	2		T71	1		T186	1
all_values[4]	auto[0]	auto[0]	auto[1]	132	1			T42	1		T71	2		T77	1
all_values[4]	auto[0]	auto[1]	auto[0]	41	1			T42	3		T71	1		T77	5
all_values[4]	auto[0]	auto[1]	auto[1]	122	1			T71	4		T77	1		T151	4
all_values[4]	auto[1]	auto[0]	auto[1]	141	1			T42	1		T71	5		T151	2
all_values[4]	auto[1]	auto[1]	auto[1]	115	1			T71	1		T77	4		T151	1
all_values[5]	auto[0]	auto[0]	auto[0]	59	1			T71	3		T220	1		T164	1
all_values[5]	auto[0]	auto[0]	auto[1]	119	1			T71	3		T77	3		T151	2
all_values[5]	auto[0]	auto[1]	auto[0]	37	1			T71	1		T162	1		T80	1
all_values[5]	auto[0]	auto[1]	auto[1]	152	1			T42	4		T71	2		T77	3
all_values[5]	auto[1]	auto[0]	auto[1]	135	1			T42	2		T71	1		T77	4
all_values[5]	auto[1]	auto[1]	auto[1]	106	1			T42	1		T71	4		T77	1
all_values[6]	auto[0]	auto[0]	auto[0]	55	1			T185	1		T164	1		T97	4
all_values[6]	auto[0]	auto[0]	auto[1]	135	1			T42	3		T71	6		T77	3
all_values[6]	auto[0]	auto[1]	auto[0]	21	1			T151	1		T185	3		T164	1
all_values[6]	auto[0]	auto[1]	auto[1]	148	1			T42	2		T71	1		T77	4
all_values[6]	auto[1]	auto[0]	auto[1]	135	1			T71	5		T151	4		T162	3
all_values[6]	auto[1]	auto[1]	auto[1]	114	1			T42	2		T71	2		T77	4
all_values[7]	auto[0]	auto[0]	auto[0]	53	1			T71	1		T80	2		T220	1
all_values[7]	auto[0]	auto[0]	auto[1]	141	1			T42	2		T71	4		T77	1
all_values[7]	auto[0]	auto[1]	auto[0]	26	1			T71	1		T151	1		T80	2
all_values[7]	auto[0]	auto[1]	auto[1]	138	1			T42	2		T71	1		T77	5
all_values[7]	auto[1]	auto[0]	auto[1]	127	1			T42	1		T71	4		T77	3
all_values[7]	auto[1]	auto[1]	auto[1]	123	1			T42	2		T71	3		T77	2
all_values[8]	auto[0]	auto[0]	auto[0]	47	1			T80	2		T163	1		T185	2
all_values[8]	auto[0]	auto[0]	auto[1]	143	1			T42	3		T71	3		T77	3
all_values[8]	auto[0]	auto[1]	auto[0]	42	1			T71	1		T162	1		T80	2
all_values[8]	auto[0]	auto[1]	auto[1]	136	1			T42	1		T71	5		T77	2
all_values[8]	auto[1]	auto[0]	auto[1]	119	1			T42	1		T71	4		T77	5
all_values[8]	auto[1]	auto[1]	auto[1]	121	1			T42	2		T71	1		T77	1
all_values[9]	auto[0]	auto[0]	auto[0]	42	1			T71	1		T195	1		T186	3
all_values[9]	auto[0]	auto[0]	auto[1]	151	1			T42	2		T71	2		T77	2
all_values[9]	auto[0]	auto[1]	auto[0]	19	1			T71	1		T151	1		T162	1
all_values[9]	auto[0]	auto[1]	auto[1]	139	1			T42	3		T71	3		T77	1
all_values[9]	auto[1]	auto[0]	auto[1]	139	1			T42	1		T71	4		T77	5
all_values[9]	auto[1]	auto[1]	auto[1]	118	1			T42	1		T71	3		T77	3
all_values[10]	auto[0]	auto[0]	auto[0]	65	1			T185	3		T164	1		T186	1
all_values[10]	auto[0]	auto[0]	auto[1]	126	1			T42	2		T71	4		T77	5
all_values[10]	auto[0]	auto[1]	auto[0]	43	1			T151	1		T185	1		T195	2
all_values[10]	auto[0]	auto[1]	auto[1]	125	1			T71	3		T77	3		T151	6
all_values[10]	auto[1]	auto[0]	auto[1]	141	1			T42	2		T71	5		T77	1
all_values[10]	auto[1]	auto[1]	auto[1]	108	1			T42	3		T71	2		T77	2
all_values[11]	auto[0]	auto[0]	auto[0]	42	1			T195	1		T186	1		T97	1
all_values[11]	auto[0]	auto[0]	auto[1]	137	1			T42	2		T71	5		T77	4
all_values[11]	auto[0]	auto[1]	auto[0]	36	1			T80	1		T186	3		T221	2
all_values[11]	auto[0]	auto[1]	auto[1]	133	1			T42	1		T71	4		T77	2
all_values[11]	auto[1]	auto[0]	auto[1]	132	1			T42	3		T71	5		T77	2
all_values[11]	auto[1]	auto[1]	auto[1]	128	1			T42	1		T77	3		T151	2
all_values[12]	auto[0]	auto[0]	auto[0]	65	1			T151	4		T185	1		T186	1
all_values[12]	auto[0]	auto[0]	auto[1]	150	1			T42	3		T71	4		T77	3
all_values[12]	auto[0]	auto[1]	auto[0]	41	1			T77	1		T151	4		T80	1
all_values[12]	auto[0]	auto[1]	auto[1]	98	1			T71	4		T77	3		T151	1
all_values[12]	auto[1]	auto[0]	auto[1]	128	1			T42	1		T71	3		T151	1
all_values[12]	auto[1]	auto[1]	auto[1]	126	1			T42	3		T71	3		T77	4
all_values[13]	auto[0]	auto[0]	auto[0]	58	1			T77	2		T80	1		T195	1
all_values[13]	auto[0]	auto[0]	auto[1]	133	1			T71	2		T77	2		T151	3
all_values[13]	auto[0]	auto[1]	auto[0]	26	1			T151	1		T80	3		T164	2
all_values[13]	auto[0]	auto[1]	auto[1]	131	1			T42	2		T71	5		T77	4
all_values[13]	auto[1]	auto[0]	auto[1]	129	1			T42	2		T71	3		T77	1
all_values[13]	auto[1]	auto[1]	auto[1]	131	1			T42	3		T71	4		T77	2
all_values[14]	auto[0]	auto[0]	auto[0]	57	1			T71	2		T186	4		T97	1
all_values[14]	auto[0]	auto[0]	auto[1]	137	1			T42	2		T71	1		T77	4
all_values[14]	auto[0]	auto[1]	auto[0]	30	1			T163	1		T185	1		T164	1
all_values[14]	auto[0]	auto[1]	auto[1]	149	1			T42	1		T71	4		T77	5
all_values[14]	auto[1]	auto[0]	auto[1]	116	1			T42	1		T71	3		T151	5
all_values[14]	auto[1]	auto[1]	auto[1]	119	1			T42	3		T71	4		T77	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal