Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.62 97.22 92.04 97.66 83.74 94.60 98.67 91.39


Total test records in report: 1450
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T1297 /workspace/coverage/default/14.i2c_target_fifo_reset_tx.2073075804 Apr 25 03:08:42 PM PDT 24 Apr 25 03:10:09 PM PDT 24 10046085827 ps
T1298 /workspace/coverage/default/39.i2c_target_stress_wr.1399612648 Apr 25 03:13:25 PM PDT 24 Apr 25 03:13:54 PM PDT 24 13573097272 ps
T1299 /workspace/coverage/default/34.i2c_host_may_nack.98355503 Apr 25 03:12:36 PM PDT 24 Apr 25 03:12:44 PM PDT 24 2477536869 ps
T1300 /workspace/coverage/default/15.i2c_target_hrst.4186053789 Apr 25 03:08:53 PM PDT 24 Apr 25 03:08:56 PM PDT 24 1599943311 ps
T1301 /workspace/coverage/default/4.i2c_target_intr_stress_wr.3159465415 Apr 25 03:05:55 PM PDT 24 Apr 25 03:06:59 PM PDT 24 6073472186 ps
T1302 /workspace/coverage/default/20.i2c_target_bad_addr.2176585990 Apr 25 03:09:55 PM PDT 24 Apr 25 03:09:59 PM PDT 24 2805187435 ps
T1303 /workspace/coverage/default/26.i2c_target_bad_addr.483439277 Apr 25 03:11:02 PM PDT 24 Apr 25 03:11:07 PM PDT 24 1843411629 ps
T1304 /workspace/coverage/default/13.i2c_host_fifo_reset_rx.9926566 Apr 25 03:08:19 PM PDT 24 Apr 25 03:08:23 PM PDT 24 114155695 ps
T1305 /workspace/coverage/default/31.i2c_host_smoke.2868806431 Apr 25 03:11:47 PM PDT 24 Apr 25 03:13:22 PM PDT 24 8249531047 ps
T1306 /workspace/coverage/default/21.i2c_host_may_nack.3923712354 Apr 25 03:10:07 PM PDT 24 Apr 25 03:10:13 PM PDT 24 997076376 ps
T1307 /workspace/coverage/default/49.i2c_target_intr_smoke.1611139979 Apr 25 03:15:07 PM PDT 24 Apr 25 03:15:12 PM PDT 24 1709387308 ps
T1308 /workspace/coverage/default/29.i2c_target_fifo_reset_tx.2980795473 Apr 25 03:11:30 PM PDT 24 Apr 25 03:11:48 PM PDT 24 10442950185 ps
T1309 /workspace/coverage/default/19.i2c_target_bad_addr.2116188728 Apr 25 03:09:43 PM PDT 24 Apr 25 03:09:48 PM PDT 24 4667275517 ps
T1310 /workspace/coverage/default/24.i2c_host_override.4168244302 Apr 25 03:10:38 PM PDT 24 Apr 25 03:10:40 PM PDT 24 42507468 ps
T1311 /workspace/coverage/default/17.i2c_host_error_intr.1960747839 Apr 25 03:09:08 PM PDT 24 Apr 25 03:09:10 PM PDT 24 307092899 ps
T1312 /workspace/coverage/default/29.i2c_host_stretch_timeout.4060409940 Apr 25 03:11:44 PM PDT 24 Apr 25 03:12:06 PM PDT 24 586203051 ps
T1313 /workspace/coverage/default/7.i2c_target_stress_wr.73056649 Apr 25 03:06:45 PM PDT 24 Apr 25 03:10:01 PM PDT 24 55522796245 ps
T1314 /workspace/coverage/default/4.i2c_host_fifo_full.3470248682 Apr 25 03:05:48 PM PDT 24 Apr 25 03:07:19 PM PDT 24 1391277349 ps
T1315 /workspace/coverage/default/42.i2c_host_mode_toggle.3270846958 Apr 25 03:13:56 PM PDT 24 Apr 25 03:14:32 PM PDT 24 3941581988 ps
T1316 /workspace/coverage/default/24.i2c_host_mode_toggle.1527684191 Apr 25 03:10:48 PM PDT 24 Apr 25 03:11:56 PM PDT 24 10772658150 ps
T1317 /workspace/coverage/default/23.i2c_target_stretch.2444178564 Apr 25 03:10:42 PM PDT 24 Apr 25 03:12:00 PM PDT 24 5435286710 ps
T1318 /workspace/coverage/default/26.i2c_host_fifo_full.2802970653 Apr 25 03:11:02 PM PDT 24 Apr 25 03:13:54 PM PDT 24 4439888634 ps
T1319 /workspace/coverage/default/41.i2c_target_smoke.3821976035 Apr 25 03:13:44 PM PDT 24 Apr 25 03:14:06 PM PDT 24 3523493724 ps
T1320 /workspace/coverage/default/32.i2c_target_timeout.483510372 Apr 25 03:12:04 PM PDT 24 Apr 25 03:12:13 PM PDT 24 7766323869 ps
T1321 /workspace/coverage/default/16.i2c_host_perf.3119493161 Apr 25 03:08:55 PM PDT 24 Apr 25 03:09:33 PM PDT 24 2607816896 ps
T1322 /workspace/coverage/default/25.i2c_target_stress_wr.299976696 Apr 25 03:10:47 PM PDT 24 Apr 25 03:26:08 PM PDT 24 69974280434 ps
T1323 /workspace/coverage/default/4.i2c_host_mode_toggle.756340111 Apr 25 03:06:04 PM PDT 24 Apr 25 03:07:09 PM PDT 24 3700802338 ps
T1324 /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.2460444028 Apr 25 03:09:56 PM PDT 24 Apr 25 03:09:58 PM PDT 24 237086173 ps
T1325 /workspace/coverage/default/23.i2c_target_bad_addr.688572136 Apr 25 03:10:29 PM PDT 24 Apr 25 03:10:33 PM PDT 24 805616686 ps
T1326 /workspace/coverage/default/45.i2c_host_smoke.404558842 Apr 25 03:14:19 PM PDT 24 Apr 25 03:15:34 PM PDT 24 3191467854 ps
T1327 /workspace/coverage/default/41.i2c_target_intr_stress_wr.999660969 Apr 25 03:13:43 PM PDT 24 Apr 25 03:18:20 PM PDT 24 18857987338 ps
T1328 /workspace/coverage/default/27.i2c_target_fifo_reset_acq.2658101164 Apr 25 03:11:09 PM PDT 24 Apr 25 03:12:13 PM PDT 24 10099830324 ps
T1329 /workspace/coverage/default/43.i2c_target_bad_addr.2343930096 Apr 25 03:14:08 PM PDT 24 Apr 25 03:14:13 PM PDT 24 848748041 ps
T1330 /workspace/coverage/default/12.i2c_host_stretch_timeout.3786831670 Apr 25 03:08:07 PM PDT 24 Apr 25 03:08:20 PM PDT 24 4698647511 ps
T1331 /workspace/coverage/default/49.i2c_target_bad_addr.3238417778 Apr 25 03:15:07 PM PDT 24 Apr 25 03:15:11 PM PDT 24 444500686 ps
T1332 /workspace/coverage/default/18.i2c_host_stretch_timeout.1551960292 Apr 25 03:09:19 PM PDT 24 Apr 25 03:09:31 PM PDT 24 512467699 ps
T1333 /workspace/coverage/default/27.i2c_target_intr_smoke.2224413324 Apr 25 03:11:09 PM PDT 24 Apr 25 03:11:16 PM PDT 24 13317786804 ps
T1334 /workspace/coverage/default/23.i2c_host_fifo_watermark.3198649538 Apr 25 03:10:25 PM PDT 24 Apr 25 03:11:33 PM PDT 24 6394899975 ps
T1335 /workspace/coverage/default/28.i2c_host_override.2468443241 Apr 25 03:11:14 PM PDT 24 Apr 25 03:11:15 PM PDT 24 42250827 ps
T1336 /workspace/coverage/default/21.i2c_target_hrst.2044172444 Apr 25 03:10:08 PM PDT 24 Apr 25 03:10:11 PM PDT 24 293442119 ps
T1337 /workspace/coverage/default/3.i2c_target_stress_rd.1845508533 Apr 25 03:05:29 PM PDT 24 Apr 25 03:05:36 PM PDT 24 1681590426 ps
T1338 /workspace/coverage/default/19.i2c_target_hrst.2039058067 Apr 25 03:09:50 PM PDT 24 Apr 25 03:09:55 PM PDT 24 2136153540 ps
T1339 /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.2309278068 Apr 25 03:03:53 PM PDT 24 Apr 25 03:03:55 PM PDT 24 251387779 ps
T1340 /workspace/coverage/default/24.i2c_target_fifo_reset_acq.3449222534 Apr 25 03:10:44 PM PDT 24 Apr 25 03:11:54 PM PDT 24 10033219644 ps
T1341 /workspace/coverage/default/44.i2c_target_hrst.1837323785 Apr 25 03:14:19 PM PDT 24 Apr 25 03:14:23 PM PDT 24 348060063 ps
T1342 /workspace/coverage/default/12.i2c_target_smoke.3264742090 Apr 25 03:08:08 PM PDT 24 Apr 25 03:08:41 PM PDT 24 855816235 ps
T1343 /workspace/coverage/default/43.i2c_host_override.3175335658 Apr 25 03:13:55 PM PDT 24 Apr 25 03:13:57 PM PDT 24 28582323 ps
T1344 /workspace/coverage/default/25.i2c_host_stress_all.3937621757 Apr 25 03:10:51 PM PDT 24 Apr 25 03:35:02 PM PDT 24 19938785468 ps
T1345 /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.4089306758 Apr 25 03:12:27 PM PDT 24 Apr 25 03:12:29 PM PDT 24 436038806 ps
T1346 /workspace/coverage/default/43.i2c_host_fifo_overflow.2286762529 Apr 25 03:13:58 PM PDT 24 Apr 25 03:14:44 PM PDT 24 1509231676 ps
T1347 /workspace/coverage/default/11.i2c_target_intr_stress_wr.3289133308 Apr 25 03:07:52 PM PDT 24 Apr 25 03:09:38 PM PDT 24 16327559060 ps
T1348 /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.1908616265 Apr 25 03:07:13 PM PDT 24 Apr 25 03:07:15 PM PDT 24 431885995 ps
T1349 /workspace/coverage/default/10.i2c_target_stress_rd.2124886047 Apr 25 03:07:33 PM PDT 24 Apr 25 03:08:01 PM PDT 24 6674711609 ps
T1350 /workspace/coverage/default/47.i2c_host_stress_all.1291285345 Apr 25 03:14:42 PM PDT 24 Apr 25 03:28:02 PM PDT 24 77460445407 ps
T1351 /workspace/coverage/default/47.i2c_host_may_nack.3027866517 Apr 25 03:14:49 PM PDT 24 Apr 25 03:14:52 PM PDT 24 160174256 ps
T1352 /workspace/coverage/default/39.i2c_target_bad_addr.1666078104 Apr 25 03:13:30 PM PDT 24 Apr 25 03:13:34 PM PDT 24 3023823505 ps
T1353 /workspace/coverage/default/20.i2c_host_perf.2588029492 Apr 25 03:09:50 PM PDT 24 Apr 25 03:10:00 PM PDT 24 778132478 ps
T1354 /workspace/coverage/default/49.i2c_target_intr_stress_wr.2247259835 Apr 25 03:15:08 PM PDT 24 Apr 25 03:21:11 PM PDT 24 19963556148 ps
T211 /workspace/coverage/default/8.i2c_host_stress_all.2592069301 Apr 25 03:07:06 PM PDT 24 Apr 25 03:09:25 PM PDT 24 23644506178 ps
T1355 /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1851522632 Apr 25 03:14:37 PM PDT 24 Apr 25 03:14:39 PM PDT 24 113548868 ps
T1356 /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3551730387 Apr 25 03:06:52 PM PDT 24 Apr 25 03:06:55 PM PDT 24 341822100 ps
T1357 /workspace/coverage/cover_reg_top/37.i2c_intr_test.1286645914 Apr 25 12:59:13 PM PDT 24 Apr 25 12:59:16 PM PDT 24 18686021 ps
T1358 /workspace/coverage/cover_reg_top/4.i2c_intr_test.1939258928 Apr 25 12:59:08 PM PDT 24 Apr 25 12:59:10 PM PDT 24 41497630 ps
T1359 /workspace/coverage/cover_reg_top/14.i2c_intr_test.1563677708 Apr 25 12:59:18 PM PDT 24 Apr 25 12:59:20 PM PDT 24 53170439 ps
T108 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2093257620 Apr 25 12:59:20 PM PDT 24 Apr 25 12:59:23 PM PDT 24 27433635 ps
T74 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.4049714648 Apr 25 12:59:09 PM PDT 24 Apr 25 12:59:12 PM PDT 24 94444194 ps
T75 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3546297927 Apr 25 12:59:13 PM PDT 24 Apr 25 12:59:18 PM PDT 24 134611065 ps
T109 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3933657873 Apr 25 12:59:02 PM PDT 24 Apr 25 12:59:06 PM PDT 24 365940291 ps
T116 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3442780299 Apr 25 12:59:16 PM PDT 24 Apr 25 12:59:19 PM PDT 24 107876875 ps
T76 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3081739638 Apr 25 12:59:38 PM PDT 24 Apr 25 12:59:42 PM PDT 24 129075990 ps
T117 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1555698671 Apr 25 12:59:18 PM PDT 24 Apr 25 12:59:22 PM PDT 24 518652947 ps
T145 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1320101746 Apr 25 12:59:03 PM PDT 24 Apr 25 12:59:05 PM PDT 24 54320847 ps
T118 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3783324370 Apr 25 12:59:23 PM PDT 24 Apr 25 12:59:26 PM PDT 24 219317473 ps
T1360 /workspace/coverage/cover_reg_top/33.i2c_intr_test.491294276 Apr 25 12:59:29 PM PDT 24 Apr 25 12:59:31 PM PDT 24 15886157 ps
T132 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2906817628 Apr 25 12:59:29 PM PDT 24 Apr 25 12:59:31 PM PDT 24 235567103 ps
T119 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.725707960 Apr 25 12:59:10 PM PDT 24 Apr 25 12:59:13 PM PDT 24 255741288 ps
T1361 /workspace/coverage/cover_reg_top/16.i2c_intr_test.3955472659 Apr 25 12:59:22 PM PDT 24 Apr 25 12:59:24 PM PDT 24 64784194 ps
T152 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.202434428 Apr 25 12:59:03 PM PDT 24 Apr 25 12:59:05 PM PDT 24 19531905 ps
T1362 /workspace/coverage/cover_reg_top/3.i2c_intr_test.2543443885 Apr 25 12:59:00 PM PDT 24 Apr 25 12:59:03 PM PDT 24 15990111 ps
T146 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2020609792 Apr 25 12:59:06 PM PDT 24 Apr 25 12:59:09 PM PDT 24 290581310 ps
T1363 /workspace/coverage/cover_reg_top/25.i2c_intr_test.401162138 Apr 25 12:59:08 PM PDT 24 Apr 25 12:59:10 PM PDT 24 51759748 ps
T147 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3407332700 Apr 25 12:59:08 PM PDT 24 Apr 25 12:59:11 PM PDT 24 57301779 ps
T135 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2524371670 Apr 25 12:59:19 PM PDT 24 Apr 25 12:59:21 PM PDT 24 27742668 ps
T148 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1053737322 Apr 25 12:59:16 PM PDT 24 Apr 25 12:59:18 PM PDT 24 49633269 ps
T1364 /workspace/coverage/cover_reg_top/11.i2c_intr_test.76566443 Apr 25 12:59:34 PM PDT 24 Apr 25 12:59:37 PM PDT 24 17141483 ps
T1365 /workspace/coverage/cover_reg_top/41.i2c_intr_test.1931821417 Apr 25 12:59:09 PM PDT 24 Apr 25 12:59:12 PM PDT 24 27367109 ps
T136 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1190664415 Apr 25 12:59:08 PM PDT 24 Apr 25 12:59:10 PM PDT 24 50684555 ps
T126 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1644374654 Apr 25 12:59:07 PM PDT 24 Apr 25 12:59:10 PM PDT 24 80592013 ps
T1366 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1011725090 Apr 25 12:59:02 PM PDT 24 Apr 25 12:59:05 PM PDT 24 60974277 ps
T120 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.932243846 Apr 25 12:58:53 PM PDT 24 Apr 25 12:58:59 PM PDT 24 175705939 ps
T1367 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3157564075 Apr 25 12:59:11 PM PDT 24 Apr 25 12:59:15 PM PDT 24 45456973 ps
T137 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.487985421 Apr 25 12:59:08 PM PDT 24 Apr 25 12:59:11 PM PDT 24 26762955 ps
T1368 /workspace/coverage/cover_reg_top/8.i2c_intr_test.1008252687 Apr 25 12:59:07 PM PDT 24 Apr 25 12:59:10 PM PDT 24 54875770 ps
T1369 /workspace/coverage/cover_reg_top/39.i2c_intr_test.2028374271 Apr 25 12:59:12 PM PDT 24 Apr 25 12:59:16 PM PDT 24 58135315 ps
T1370 /workspace/coverage/cover_reg_top/48.i2c_intr_test.829096187 Apr 25 12:59:38 PM PDT 24 Apr 25 12:59:41 PM PDT 24 91263294 ps
T133 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.831442854 Apr 25 12:59:08 PM PDT 24 Apr 25 12:59:11 PM PDT 24 32975039 ps
T134 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3032609038 Apr 25 12:59:04 PM PDT 24 Apr 25 12:59:07 PM PDT 24 113645374 ps
T127 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.171138579 Apr 25 12:59:28 PM PDT 24 Apr 25 12:59:31 PM PDT 24 81268608 ps
T124 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2173702993 Apr 25 12:59:05 PM PDT 24 Apr 25 12:59:18 PM PDT 24 32676979 ps
T1371 /workspace/coverage/cover_reg_top/18.i2c_intr_test.2410634913 Apr 25 12:59:22 PM PDT 24 Apr 25 12:59:23 PM PDT 24 118400252 ps
T153 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2967783169 Apr 25 12:59:35 PM PDT 24 Apr 25 12:59:40 PM PDT 24 668050967 ps
T121 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.432076138 Apr 25 12:59:05 PM PDT 24 Apr 25 12:59:10 PM PDT 24 287359456 ps
T1372 /workspace/coverage/cover_reg_top/22.i2c_intr_test.3145196123 Apr 25 12:59:28 PM PDT 24 Apr 25 12:59:30 PM PDT 24 54822170 ps
T154 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1586182138 Apr 25 12:59:18 PM PDT 24 Apr 25 12:59:21 PM PDT 24 38628487 ps
T122 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.31723810 Apr 25 12:59:09 PM PDT 24 Apr 25 12:59:12 PM PDT 24 410361473 ps
T1373 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1499700934 Apr 25 12:58:57 PM PDT 24 Apr 25 12:59:02 PM PDT 24 83004855 ps
T149 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2914987320 Apr 25 12:59:08 PM PDT 24 Apr 25 12:59:10 PM PDT 24 77296627 ps
T187 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3377850473 Apr 25 12:59:34 PM PDT 24 Apr 25 12:59:37 PM PDT 24 72814505 ps
T1374 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2884526328 Apr 25 12:59:17 PM PDT 24 Apr 25 12:59:20 PM PDT 24 39585073 ps
T1375 /workspace/coverage/cover_reg_top/27.i2c_intr_test.2166271538 Apr 25 12:59:30 PM PDT 24 Apr 25 12:59:31 PM PDT 24 18363674 ps
T1376 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.501516632 Apr 25 12:58:56 PM PDT 24 Apr 25 12:59:01 PM PDT 24 169091954 ps
T225 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2408017340 Apr 25 12:59:04 PM PDT 24 Apr 25 12:59:07 PM PDT 24 106696151 ps
T1377 /workspace/coverage/cover_reg_top/45.i2c_intr_test.2855944199 Apr 25 12:59:36 PM PDT 24 Apr 25 12:59:39 PM PDT 24 16381473 ps
T125 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2351711194 Apr 25 12:59:05 PM PDT 24 Apr 25 12:59:09 PM PDT 24 294721092 ps
T1378 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2641832838 Apr 25 12:59:13 PM PDT 24 Apr 25 12:59:16 PM PDT 24 41252926 ps
T138 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.422121547 Apr 25 12:59:26 PM PDT 24 Apr 25 12:59:28 PM PDT 24 88292994 ps
T1379 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3729932008 Apr 25 12:59:02 PM PDT 24 Apr 25 12:59:05 PM PDT 24 64597771 ps
T1380 /workspace/coverage/cover_reg_top/28.i2c_intr_test.1873349129 Apr 25 12:59:18 PM PDT 24 Apr 25 12:59:20 PM PDT 24 31695979 ps
T1381 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2685087740 Apr 25 12:59:23 PM PDT 24 Apr 25 12:59:25 PM PDT 24 27486614 ps
T1382 /workspace/coverage/cover_reg_top/36.i2c_intr_test.3059605710 Apr 25 12:59:21 PM PDT 24 Apr 25 12:59:23 PM PDT 24 16825219 ps
T1383 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2223900472 Apr 25 12:59:31 PM PDT 24 Apr 25 12:59:33 PM PDT 24 24906716 ps
T1384 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1890812613 Apr 25 12:59:11 PM PDT 24 Apr 25 12:59:15 PM PDT 24 148591554 ps
T1385 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3691889988 Apr 25 12:59:34 PM PDT 24 Apr 25 12:59:36 PM PDT 24 46363304 ps
T139 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1905768955 Apr 25 12:59:04 PM PDT 24 Apr 25 12:59:07 PM PDT 24 16383376 ps
T1386 /workspace/coverage/cover_reg_top/6.i2c_intr_test.3371593135 Apr 25 12:59:01 PM PDT 24 Apr 25 12:59:09 PM PDT 24 59309207 ps
T1387 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.278773551 Apr 25 12:59:22 PM PDT 24 Apr 25 12:59:25 PM PDT 24 216423512 ps
T1388 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3544250439 Apr 25 12:59:11 PM PDT 24 Apr 25 12:59:15 PM PDT 24 58603767 ps
T1389 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3434521140 Apr 25 12:59:07 PM PDT 24 Apr 25 12:59:11 PM PDT 24 143240843 ps
T1390 /workspace/coverage/cover_reg_top/44.i2c_intr_test.1871424774 Apr 25 12:59:34 PM PDT 24 Apr 25 12:59:36 PM PDT 24 56828775 ps
T1391 /workspace/coverage/cover_reg_top/20.i2c_intr_test.4104192129 Apr 25 12:59:24 PM PDT 24 Apr 25 12:59:26 PM PDT 24 30443996 ps
T1392 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.4226601574 Apr 25 12:59:17 PM PDT 24 Apr 25 12:59:19 PM PDT 24 83818543 ps
T129 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2957763552 Apr 25 12:59:23 PM PDT 24 Apr 25 12:59:27 PM PDT 24 126392758 ps
T1393 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.3135989525 Apr 25 12:59:31 PM PDT 24 Apr 25 12:59:35 PM PDT 24 154736050 ps
T1394 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3322713982 Apr 25 12:58:53 PM PDT 24 Apr 25 12:58:57 PM PDT 24 48798170 ps
T1395 /workspace/coverage/cover_reg_top/47.i2c_intr_test.3585900463 Apr 25 12:59:39 PM PDT 24 Apr 25 12:59:42 PM PDT 24 176761640 ps
T128 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2648694737 Apr 25 12:59:23 PM PDT 24 Apr 25 12:59:26 PM PDT 24 48819495 ps
T1396 /workspace/coverage/cover_reg_top/19.i2c_intr_test.2168412515 Apr 25 12:59:10 PM PDT 24 Apr 25 12:59:14 PM PDT 24 45777075 ps
T1397 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2221312708 Apr 25 12:59:27 PM PDT 24 Apr 25 12:59:30 PM PDT 24 43292683 ps
T150 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1656809666 Apr 25 12:59:21 PM PDT 24 Apr 25 12:59:24 PM PDT 24 346382753 ps
T1398 /workspace/coverage/cover_reg_top/29.i2c_intr_test.240192812 Apr 25 12:59:12 PM PDT 24 Apr 25 12:59:16 PM PDT 24 26138261 ps
T1399 /workspace/coverage/cover_reg_top/42.i2c_intr_test.337412373 Apr 25 12:59:11 PM PDT 24 Apr 25 12:59:15 PM PDT 24 39011674 ps
T1400 /workspace/coverage/cover_reg_top/13.i2c_intr_test.2450677748 Apr 25 12:59:43 PM PDT 24 Apr 25 12:59:45 PM PDT 24 40146772 ps
T1401 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.4263991951 Apr 25 12:59:10 PM PDT 24 Apr 25 12:59:13 PM PDT 24 63895262 ps
T1402 /workspace/coverage/cover_reg_top/43.i2c_intr_test.2863582168 Apr 25 12:59:33 PM PDT 24 Apr 25 12:59:40 PM PDT 24 17904015 ps
T1403 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.534616985 Apr 25 12:59:05 PM PDT 24 Apr 25 12:59:07 PM PDT 24 54994705 ps
T1404 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2788592407 Apr 25 12:59:08 PM PDT 24 Apr 25 12:59:11 PM PDT 24 37425380 ps
T1405 /workspace/coverage/cover_reg_top/40.i2c_intr_test.3484223063 Apr 25 12:59:13 PM PDT 24 Apr 25 12:59:16 PM PDT 24 45528596 ps
T131 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3242742607 Apr 25 12:59:10 PM PDT 24 Apr 25 12:59:15 PM PDT 24 354034258 ps
T140 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3716139342 Apr 25 12:59:19 PM PDT 24 Apr 25 12:59:21 PM PDT 24 16660412 ps
T1406 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1016560938 Apr 25 12:59:31 PM PDT 24 Apr 25 12:59:33 PM PDT 24 45066650 ps
T1407 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2331234967 Apr 25 12:59:38 PM PDT 24 Apr 25 12:59:41 PM PDT 24 121771225 ps
T130 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3190146851 Apr 25 12:59:16 PM PDT 24 Apr 25 12:59:20 PM PDT 24 181178306 ps
T1408 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2770477693 Apr 25 12:59:15 PM PDT 24 Apr 25 12:59:18 PM PDT 24 35703906 ps
T141 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.351356269 Apr 25 12:59:00 PM PDT 24 Apr 25 12:59:04 PM PDT 24 514639259 ps
T1409 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1656942556 Apr 25 12:58:52 PM PDT 24 Apr 25 12:58:56 PM PDT 24 577240266 ps
T1410 /workspace/coverage/cover_reg_top/35.i2c_intr_test.1477978305 Apr 25 12:59:30 PM PDT 24 Apr 25 12:59:32 PM PDT 24 43457387 ps
T1411 /workspace/coverage/cover_reg_top/15.i2c_intr_test.3324328670 Apr 25 12:59:19 PM PDT 24 Apr 25 12:59:21 PM PDT 24 30331103 ps
T1412 /workspace/coverage/cover_reg_top/23.i2c_intr_test.150619321 Apr 25 12:59:28 PM PDT 24 Apr 25 12:59:29 PM PDT 24 17468288 ps
T1413 /workspace/coverage/cover_reg_top/0.i2c_intr_test.3657003998 Apr 25 12:59:20 PM PDT 24 Apr 25 12:59:22 PM PDT 24 15844558 ps
T1414 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1319750174 Apr 25 12:59:16 PM PDT 24 Apr 25 12:59:18 PM PDT 24 351014596 ps
T142 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3083631525 Apr 25 12:59:12 PM PDT 24 Apr 25 12:59:16 PM PDT 24 21057771 ps
T1415 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1264597605 Apr 25 12:59:06 PM PDT 24 Apr 25 12:59:09 PM PDT 24 58430103 ps
T1416 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3671434171 Apr 25 12:59:26 PM PDT 24 Apr 25 12:59:30 PM PDT 24 117431296 ps
T1417 /workspace/coverage/cover_reg_top/34.i2c_intr_test.3105407956 Apr 25 12:59:25 PM PDT 24 Apr 25 12:59:27 PM PDT 24 18696325 ps
T1418 /workspace/coverage/cover_reg_top/10.i2c_intr_test.1163686774 Apr 25 12:59:03 PM PDT 24 Apr 25 12:59:05 PM PDT 24 159594891 ps
T1419 /workspace/coverage/cover_reg_top/46.i2c_intr_test.2392482131 Apr 25 12:59:21 PM PDT 24 Apr 25 12:59:23 PM PDT 24 33077163 ps
T1420 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1803240845 Apr 25 12:59:20 PM PDT 24 Apr 25 12:59:23 PM PDT 24 447489719 ps
T1421 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1436363879 Apr 25 12:58:58 PM PDT 24 Apr 25 12:59:01 PM PDT 24 15201388 ps
T1422 /workspace/coverage/cover_reg_top/21.i2c_intr_test.2909944343 Apr 25 12:59:13 PM PDT 24 Apr 25 12:59:16 PM PDT 24 36427719 ps
T1423 /workspace/coverage/cover_reg_top/5.i2c_intr_test.3506589574 Apr 25 12:59:02 PM PDT 24 Apr 25 12:59:05 PM PDT 24 17163529 ps
T1424 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1938581606 Apr 25 12:59:03 PM PDT 24 Apr 25 12:59:16 PM PDT 24 64777959 ps
T1425 /workspace/coverage/cover_reg_top/24.i2c_intr_test.1179191841 Apr 25 12:59:13 PM PDT 24 Apr 25 12:59:17 PM PDT 24 45567496 ps
T1426 /workspace/coverage/cover_reg_top/31.i2c_intr_test.2954336272 Apr 25 12:59:39 PM PDT 24 Apr 25 12:59:42 PM PDT 24 44610798 ps
T1427 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3421222215 Apr 25 12:59:25 PM PDT 24 Apr 25 12:59:27 PM PDT 24 19387334 ps
T1428 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.4140241853 Apr 25 12:59:18 PM PDT 24 Apr 25 12:59:21 PM PDT 24 101600817 ps
T1429 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3332493137 Apr 25 12:59:27 PM PDT 24 Apr 25 12:59:28 PM PDT 24 68631370 ps
T1430 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.276784491 Apr 25 12:59:19 PM PDT 24 Apr 25 12:59:21 PM PDT 24 47397908 ps
T143 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.871704331 Apr 25 12:58:58 PM PDT 24 Apr 25 12:59:02 PM PDT 24 17245537 ps
T1431 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1667281091 Apr 25 12:59:29 PM PDT 24 Apr 25 12:59:31 PM PDT 24 25862345 ps
T1432 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1211004777 Apr 25 12:59:12 PM PDT 24 Apr 25 12:59:16 PM PDT 24 38147057 ps
T1433 /workspace/coverage/cover_reg_top/30.i2c_intr_test.2700925653 Apr 25 12:59:21 PM PDT 24 Apr 25 12:59:23 PM PDT 24 15985447 ps
T1434 /workspace/coverage/cover_reg_top/7.i2c_intr_test.3905357799 Apr 25 12:59:12 PM PDT 24 Apr 25 12:59:16 PM PDT 24 23590370 ps
T1435 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1492731079 Apr 25 12:58:53 PM PDT 24 Apr 25 12:58:58 PM PDT 24 171306719 ps
T1436 /workspace/coverage/cover_reg_top/12.i2c_intr_test.132749900 Apr 25 12:59:30 PM PDT 24 Apr 25 12:59:32 PM PDT 24 43015711 ps
T1437 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.584490005 Apr 25 12:59:29 PM PDT 24 Apr 25 12:59:31 PM PDT 24 114812857 ps
T1438 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3476952615 Apr 25 12:59:24 PM PDT 24 Apr 25 12:59:26 PM PDT 24 119051921 ps
T144 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2048889682 Apr 25 12:59:02 PM PDT 24 Apr 25 12:59:05 PM PDT 24 22881255 ps
T1439 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1033912209 Apr 25 12:59:11 PM PDT 24 Apr 25 12:59:15 PM PDT 24 38859968 ps
T1440 /workspace/coverage/cover_reg_top/26.i2c_intr_test.3657095537 Apr 25 12:59:43 PM PDT 24 Apr 25 12:59:45 PM PDT 24 43513762 ps
T1441 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2998696385 Apr 25 12:59:28 PM PDT 24 Apr 25 12:59:31 PM PDT 24 70237250 ps
T1442 /workspace/coverage/cover_reg_top/17.i2c_intr_test.2838228237 Apr 25 12:59:15 PM PDT 24 Apr 25 12:59:17 PM PDT 24 42097138 ps
T1443 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2015245978 Apr 25 12:59:20 PM PDT 24 Apr 25 12:59:22 PM PDT 24 18772936 ps
T1444 /workspace/coverage/cover_reg_top/32.i2c_intr_test.2393948815 Apr 25 12:59:25 PM PDT 24 Apr 25 12:59:32 PM PDT 24 196426564 ps
T1445 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1050098985 Apr 25 12:59:20 PM PDT 24 Apr 25 12:59:23 PM PDT 24 59751640 ps
T123 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3327510467 Apr 25 12:59:13 PM PDT 24 Apr 25 12:59:17 PM PDT 24 72563907 ps
T1446 /workspace/coverage/cover_reg_top/38.i2c_intr_test.897458396 Apr 25 12:59:33 PM PDT 24 Apr 25 12:59:35 PM PDT 24 65108015 ps
T1447 /workspace/coverage/cover_reg_top/9.i2c_intr_test.2226280021 Apr 25 12:59:06 PM PDT 24 Apr 25 12:59:09 PM PDT 24 26871637 ps
T1448 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1901322655 Apr 25 12:59:10 PM PDT 24 Apr 25 12:59:14 PM PDT 24 90145177 ps
T1449 /workspace/coverage/cover_reg_top/49.i2c_intr_test.3464159305 Apr 25 12:59:26 PM PDT 24 Apr 25 12:59:28 PM PDT 24 45102568 ps
T1450 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2715349257 Apr 25 12:58:54 PM PDT 24 Apr 25 12:58:58 PM PDT 24 35211093 ps

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.451437923
Short name T7
Test name
Test status
Simulation time 1760228967 ps
CPU time 11.1 seconds
Started Apr 25 03:13:50 PM PDT 24
Finished Apr 25 03:14:03 PM PDT 24
Peak memory 302652 kb
Host smart-3ddfe501-c276-475d-9d5e-6d57a0818358
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451437923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt
y.451437923
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.463874299
Short name T29
Test name
Test status
Simulation time 10040234031 ps
CPU time 65.08 seconds
Started Apr 25 03:08:52 PM PDT 24
Finished Apr 25 03:09:58 PM PDT 24
Peak memory 469288 kb
Host smart-5fbd6abc-6eaf-46f3-bc91-dac6203c3e29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463874299 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_tx.463874299
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.1141052246
Short name T15
Test name
Test status
Simulation time 4962105665 ps
CPU time 10.5 seconds
Started Apr 25 03:04:30 PM PDT 24
Finished Apr 25 03:04:41 PM PDT 24
Peak memory 204316 kb
Host smart-76610d67-a910-4961-953e-176d84d15550
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141052246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.1141052246
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.2040492973
Short name T42
Test name
Test status
Simulation time 6667768938 ps
CPU time 199.94 seconds
Started Apr 25 03:08:57 PM PDT 24
Finished Apr 25 03:12:19 PM PDT 24
Peak memory 905552 kb
Host smart-e4aa74c6-4abe-4dcb-b23e-14dc223e89f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040492973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2040492973
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_perf.1191151656
Short name T6
Test name
Test status
Simulation time 4992377100 ps
CPU time 206.11 seconds
Started Apr 25 03:15:08 PM PDT 24
Finished Apr 25 03:18:35 PM PDT 24
Peak memory 1270948 kb
Host smart-d61b54a1-8f7d-449c-8be6-9839d0ba38bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191151656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1191151656
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3442780299
Short name T116
Test name
Test status
Simulation time 107876875 ps
CPU time 1.29 seconds
Started Apr 25 12:59:16 PM PDT 24
Finished Apr 25 12:59:19 PM PDT 24
Peak memory 204192 kb
Host smart-e2ed2e83-20d0-48f0-bab0-77c130abf246
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442780299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3442780299
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.2809756049
Short name T71
Test name
Test status
Simulation time 61693363754 ps
CPU time 192.77 seconds
Started Apr 25 03:08:18 PM PDT 24
Finished Apr 25 03:11:33 PM PDT 24
Peak memory 903936 kb
Host smart-1b6f531f-dea5-40bf-819a-af1a177ecc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809756049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.2809756049
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3546297927
Short name T75
Test name
Test status
Simulation time 134611065 ps
CPU time 2.06 seconds
Started Apr 25 12:59:13 PM PDT 24
Finished Apr 25 12:59:18 PM PDT 24
Peak memory 204248 kb
Host smart-fc52b522-afb0-45f0-818a-3ff2b7b3a781
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546297927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3546297927
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1556912753
Short name T110
Test name
Test status
Simulation time 130551590 ps
CPU time 0.85 seconds
Started Apr 25 03:04:19 PM PDT 24
Finished Apr 25 03:04:21 PM PDT 24
Peak memory 221500 kb
Host smart-090cfb6e-b403-47cc-9ff9-0c20574e1497
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556912753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1556912753
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/26.i2c_host_override.826572958
Short name T38
Test name
Test status
Simulation time 30431102 ps
CPU time 0.7 seconds
Started Apr 25 03:10:59 PM PDT 24
Finished Apr 25 03:11:01 PM PDT 24
Peak memory 203788 kb
Host smart-0e76f8c9-74f3-4cdf-8014-165001f64a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826572958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.826572958
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.2579869849
Short name T327
Test name
Test status
Simulation time 339034540 ps
CPU time 7.09 seconds
Started Apr 25 03:08:13 PM PDT 24
Finished Apr 25 03:08:22 PM PDT 24
Peak memory 204112 kb
Host smart-f4b9c7c1-dd80-4647-8a47-bc2097ddb805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579869849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.2579869849
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.3197271016
Short name T21
Test name
Test status
Simulation time 22208193039 ps
CPU time 493.34 seconds
Started Apr 25 03:05:04 PM PDT 24
Finished Apr 25 03:13:18 PM PDT 24
Peak memory 3946620 kb
Host smart-83059469-9b3d-401e-beed-75981919dab6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197271016 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.3197271016
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.2026115184
Short name T214
Test name
Test status
Simulation time 97594912214 ps
CPU time 1182.38 seconds
Started Apr 25 03:11:55 PM PDT 24
Finished Apr 25 03:31:39 PM PDT 24
Peak memory 2734784 kb
Host smart-e540fb63-8722-4267-8782-84f585ed1872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026115184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.2026115184
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.117571208
Short name T27
Test name
Test status
Simulation time 1617642045 ps
CPU time 2.35 seconds
Started Apr 25 03:08:27 PM PDT 24
Finished Apr 25 03:08:30 PM PDT 24
Peak memory 204180 kb
Host smart-69557d09-5575-4cd5-9ff9-f4f01946f7f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117571208 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.117571208
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.3411591222
Short name T96
Test name
Test status
Simulation time 154383280 ps
CPU time 1.27 seconds
Started Apr 25 03:14:55 PM PDT 24
Finished Apr 25 03:14:56 PM PDT 24
Peak memory 204104 kb
Host smart-228c5c68-c946-4c23-bdbd-ad9b8d78233d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411591222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.3411591222
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.742148125
Short name T97
Test name
Test status
Simulation time 56681602217 ps
CPU time 474.04 seconds
Started Apr 25 03:14:20 PM PDT 24
Finished Apr 25 03:22:16 PM PDT 24
Peak memory 1793860 kb
Host smart-ca2d6cfe-dd8f-40b8-abeb-137f6e00480e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742148125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.742148125
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2351711194
Short name T125
Test name
Test status
Simulation time 294721092 ps
CPU time 1.51 seconds
Started Apr 25 12:59:05 PM PDT 24
Finished Apr 25 12:59:09 PM PDT 24
Peak memory 204272 kb
Host smart-55b319ad-9ff1-4797-bc3c-0fff6a67e3c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351711194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2351711194
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.1574932227
Short name T48
Test name
Test status
Simulation time 43562271434 ps
CPU time 428.79 seconds
Started Apr 25 03:10:24 PM PDT 24
Finished Apr 25 03:17:34 PM PDT 24
Peak memory 1918776 kb
Host smart-aafad4e0-128a-457a-92ea-138db9d07cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574932227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.1574932227
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.14810178
Short name T151
Test name
Test status
Simulation time 8958500501 ps
CPU time 293.3 seconds
Started Apr 25 03:13:20 PM PDT 24
Finished Apr 25 03:18:14 PM PDT 24
Peak memory 317540 kb
Host smart-7ac03649-3dd3-4995-8685-2b908053279e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14810178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.14810178
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_alert_test.4169912927
Short name T228
Test name
Test status
Simulation time 16883058 ps
CPU time 0.63 seconds
Started Apr 25 03:09:14 PM PDT 24
Finished Apr 25 03:09:16 PM PDT 24
Peak memory 203876 kb
Host smart-acadcc94-f38a-45b5-a8d6-16fe99765d84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169912927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.4169912927
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.4051008476
Short name T202
Test name
Test status
Simulation time 3689793432 ps
CPU time 30.14 seconds
Started Apr 25 03:11:02 PM PDT 24
Finished Apr 25 03:11:34 PM PDT 24
Peak memory 380364 kb
Host smart-5dafd4b1-ef5d-44a7-871e-4ded29b7fad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051008476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.4051008476
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.1504010768
Short name T181
Test name
Test status
Simulation time 115701331 ps
CPU time 6.8 seconds
Started Apr 25 03:04:53 PM PDT 24
Finished Apr 25 03:05:01 PM PDT 24
Peak memory 221700 kb
Host smart-a250eb50-193f-47fc-86ef-9bf69ca73bbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504010768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
1504010768
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_target_unexp_stop.3939322035
Short name T19
Test name
Test status
Simulation time 1750394929 ps
CPU time 4.34 seconds
Started Apr 25 03:14:36 PM PDT 24
Finished Apr 25 03:14:41 PM PDT 24
Peak memory 207092 kb
Host smart-3fb30927-ff06-434e-a1bb-8a2b9bf5981c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939322035 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.i2c_target_unexp_stop.3939322035
Directory /workspace/46.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.4164640033
Short name T107
Test name
Test status
Simulation time 5957590193 ps
CPU time 61.45 seconds
Started Apr 25 03:10:34 PM PDT 24
Finished Apr 25 03:11:37 PM PDT 24
Peak memory 839128 kb
Host smart-9696b86e-eb7e-44a7-b06b-fd6fcfdc40c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164640033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.4164640033
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.901476440
Short name T13
Test name
Test status
Simulation time 5420458606 ps
CPU time 7.21 seconds
Started Apr 25 03:10:29 PM PDT 24
Finished Apr 25 03:10:37 PM PDT 24
Peak memory 212436 kb
Host smart-1d5e7169-ec59-4496-8d9b-6b87589c38a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901476440 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_timeout.901476440
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.1891369688
Short name T179
Test name
Test status
Simulation time 10069774932 ps
CPU time 76.38 seconds
Started Apr 25 03:10:52 PM PDT 24
Finished Apr 25 03:12:10 PM PDT 24
Peak memory 498092 kb
Host smart-99a4d6bc-f126-44d0-89bf-100c18ba3606
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891369688 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.1891369688
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.2943736156
Short name T72
Test name
Test status
Simulation time 15303510833 ps
CPU time 1646.18 seconds
Started Apr 25 03:08:31 PM PDT 24
Finished Apr 25 03:36:00 PM PDT 24
Peak memory 2424244 kb
Host smart-949e3932-2fe1-4fad-8b1b-587550c59856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943736156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.2943736156
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2957763552
Short name T129
Test name
Test status
Simulation time 126392758 ps
CPU time 2.13 seconds
Started Apr 25 12:59:23 PM PDT 24
Finished Apr 25 12:59:27 PM PDT 24
Peak memory 204268 kb
Host smart-21cec407-ff81-4082-891a-941c2e1fca85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957763552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.2957763552
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.3449222534
Short name T1340
Test name
Test status
Simulation time 10033219644 ps
CPU time 68.54 seconds
Started Apr 25 03:10:44 PM PDT 24
Finished Apr 25 03:11:54 PM PDT 24
Peak memory 469724 kb
Host smart-f81e854c-5700-4b1f-b29d-a0dc491ebcea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449222534 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.3449222534
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1656809666
Short name T150
Test name
Test status
Simulation time 346382753 ps
CPU time 1.14 seconds
Started Apr 25 12:59:21 PM PDT 24
Finished Apr 25 12:59:24 PM PDT 24
Peak memory 204316 kb
Host smart-83664311-1c21-418a-9a0e-b3a15b1bc086
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656809666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.1656809666
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2884526328
Short name T1374
Test name
Test status
Simulation time 39585073 ps
CPU time 1.84 seconds
Started Apr 25 12:59:17 PM PDT 24
Finished Apr 25 12:59:20 PM PDT 24
Peak memory 204228 kb
Host smart-1a3b9377-903c-4e5a-adb3-1c0eaa0a648a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884526328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2884526328
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.1905004426
Short name T264
Test name
Test status
Simulation time 1346380341 ps
CPU time 1.09 seconds
Started Apr 25 03:04:18 PM PDT 24
Finished Apr 25 03:04:20 PM PDT 24
Peak memory 204132 kb
Host smart-4fb6057d-30f1-49a6-9dcc-4f2db0aae8da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905004426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.1905004426
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.854663566
Short name T163
Test name
Test status
Simulation time 82151199408 ps
CPU time 145.19 seconds
Started Apr 25 03:04:30 PM PDT 24
Finished Apr 25 03:06:56 PM PDT 24
Peak memory 780776 kb
Host smart-65d36bdf-df3f-45af-93ff-016bf9e690af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854663566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.854663566
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.4134925837
Short name T209
Test name
Test status
Simulation time 20646661346 ps
CPU time 1546.3 seconds
Started Apr 25 03:07:51 PM PDT 24
Finished Apr 25 03:33:39 PM PDT 24
Peak memory 2523228 kb
Host smart-cd6421f0-61f0-4ed3-9b3f-51a23331b0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134925837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.4134925837
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.2829480622
Short name T24
Test name
Test status
Simulation time 2064781713 ps
CPU time 2.43 seconds
Started Apr 25 03:09:01 PM PDT 24
Finished Apr 25 03:09:05 PM PDT 24
Peak memory 204184 kb
Host smart-53a70ba1-f490-4b10-b50f-8638c7945a21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829480622 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.2829480622
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.2886242691
Short name T195
Test name
Test status
Simulation time 6737844895 ps
CPU time 252.25 seconds
Started Apr 25 03:06:44 PM PDT 24
Finished Apr 25 03:10:57 PM PDT 24
Peak memory 1074028 kb
Host smart-7e5ce349-c408-4c64-a3c4-224443aae279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886242691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.2886242691
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.431976105
Short name T67
Test name
Test status
Simulation time 1074589616 ps
CPU time 47.15 seconds
Started Apr 25 03:10:53 PM PDT 24
Finished Apr 25 03:11:41 PM PDT 24
Peak memory 312832 kb
Host smart-9fa171b9-b97e-4a44-b807-b3ee7070399d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431976105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.431976105
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2648694737
Short name T128
Test name
Test status
Simulation time 48819495 ps
CPU time 1.39 seconds
Started Apr 25 12:59:23 PM PDT 24
Finished Apr 25 12:59:26 PM PDT 24
Peak memory 204252 kb
Host smart-544e5a07-83a1-4d90-9875-7dc134daebc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648694737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.2648694737
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.2676659201
Short name T99
Test name
Test status
Simulation time 10074371184 ps
CPU time 72 seconds
Started Apr 25 03:06:13 PM PDT 24
Finished Apr 25 03:07:26 PM PDT 24
Peak memory 425848 kb
Host smart-9371072e-0bfd-417e-b7db-f7a28ef95270
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676659201 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.2676659201
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2408017340
Short name T225
Test name
Test status
Simulation time 106696151 ps
CPU time 0.77 seconds
Started Apr 25 12:59:04 PM PDT 24
Finished Apr 25 12:59:07 PM PDT 24
Peak memory 204028 kb
Host smart-2e189dd1-1940-4614-9cc2-d1031a1dc8e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408017340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2408017340
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.2081882749
Short name T676
Test name
Test status
Simulation time 724979541 ps
CPU time 4.59 seconds
Started Apr 25 03:07:45 PM PDT 24
Finished Apr 25 03:07:51 PM PDT 24
Peak memory 204144 kb
Host smart-8bdbb93b-0822-4931-8a80-e558b7909450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081882749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.2081882749
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.2202579286
Short name T721
Test name
Test status
Simulation time 494032683 ps
CPU time 2.87 seconds
Started Apr 25 03:07:42 PM PDT 24
Finished Apr 25 03:07:46 PM PDT 24
Peak memory 204236 kb
Host smart-f4436ac2-a310-4b09-b6a7-ed34bdc94749
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202579286 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.2202579286
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.3237214330
Short name T31
Test name
Test status
Simulation time 10125339123 ps
CPU time 67.77 seconds
Started Apr 25 03:10:01 PM PDT 24
Finished Apr 25 03:11:09 PM PDT 24
Peak memory 510236 kb
Host smart-b8fbe279-db30-469b-b708-11b8b1236f90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237214330 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.3237214330
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.135207807
Short name T197
Test name
Test status
Simulation time 1680520837 ps
CPU time 29.31 seconds
Started Apr 25 03:12:49 PM PDT 24
Finished Apr 25 03:13:19 PM PDT 24
Peak memory 224588 kb
Host smart-2df672d7-d4d3-49e1-9e71-17840f38a79d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135207807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_rd.135207807
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.1472221118
Short name T210
Test name
Test status
Simulation time 1599308909 ps
CPU time 36.54 seconds
Started Apr 25 03:13:49 PM PDT 24
Finished Apr 25 03:14:27 PM PDT 24
Peak memory 385928 kb
Host smart-559aa31d-0d92-4fc1-b328-d2cfea5d6c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472221118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.1472221118
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.4058429773
Short name T51
Test name
Test status
Simulation time 10133461883 ps
CPU time 31.09 seconds
Started Apr 25 03:05:14 PM PDT 24
Finished Apr 25 03:05:45 PM PDT 24
Peak memory 344084 kb
Host smart-a4999eb8-a1ed-4d7d-bee9-2cc8bc418171
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058429773 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.4058429773
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1499700934
Short name T1373
Test name
Test status
Simulation time 83004855 ps
CPU time 1.89 seconds
Started Apr 25 12:58:57 PM PDT 24
Finished Apr 25 12:59:02 PM PDT 24
Peak memory 204284 kb
Host smart-eaaedeec-9eff-4c05-9179-d4ecac43d7ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499700934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1499700934
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.31723810
Short name T122
Test name
Test status
Simulation time 410361473 ps
CPU time 1.48 seconds
Started Apr 25 12:59:09 PM PDT 24
Finished Apr 25 12:59:12 PM PDT 24
Peak memory 204244 kb
Host smart-7f2144ee-36bd-4d80-8a53-72580ba92d61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31723810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.31723810
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.4263991951
Short name T1401
Test name
Test status
Simulation time 63895262 ps
CPU time 1.41 seconds
Started Apr 25 12:59:10 PM PDT 24
Finished Apr 25 12:59:13 PM PDT 24
Peak memory 204196 kb
Host smart-be280ca0-bda6-47ab-a7c3-2ceefb42fcb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263991951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.4263991951
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1011725090
Short name T1366
Test name
Test status
Simulation time 60974277 ps
CPU time 0.8 seconds
Started Apr 25 12:59:02 PM PDT 24
Finished Apr 25 12:59:05 PM PDT 24
Peak memory 203972 kb
Host smart-17b96e55-fad0-43c9-ad4a-d3921c694649
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011725090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1011725090
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1644374654
Short name T126
Test name
Test status
Simulation time 80592013 ps
CPU time 1.16 seconds
Started Apr 25 12:59:07 PM PDT 24
Finished Apr 25 12:59:10 PM PDT 24
Peak memory 204348 kb
Host smart-79922a92-4e05-4080-a9bb-821ab9e6f74d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644374654 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1644374654
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.871704331
Short name T143
Test name
Test status
Simulation time 17245537 ps
CPU time 0.69 seconds
Started Apr 25 12:58:58 PM PDT 24
Finished Apr 25 12:59:02 PM PDT 24
Peak memory 203960 kb
Host smart-509b9ec4-681d-4dfd-91f2-55a014cb5e7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871704331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.871704331
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.3657003998
Short name T1413
Test name
Test status
Simulation time 15844558 ps
CPU time 0.69 seconds
Started Apr 25 12:59:20 PM PDT 24
Finished Apr 25 12:59:22 PM PDT 24
Peak memory 203944 kb
Host smart-bf06f3ff-e8f5-40bf-8e3e-8db56521be04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657003998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3657003998
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1492731079
Short name T1435
Test name
Test status
Simulation time 171306719 ps
CPU time 2.01 seconds
Started Apr 25 12:58:53 PM PDT 24
Finished Apr 25 12:58:58 PM PDT 24
Peak memory 204192 kb
Host smart-64963b16-f7ac-47ed-9114-02a4fadf0a98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492731079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1492731079
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1905768955
Short name T139
Test name
Test status
Simulation time 16383376 ps
CPU time 0.65 seconds
Started Apr 25 12:59:04 PM PDT 24
Finished Apr 25 12:59:07 PM PDT 24
Peak memory 203980 kb
Host smart-3450dae5-4085-41ea-9244-4be515dc9723
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905768955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1905768955
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2173702993
Short name T124
Test name
Test status
Simulation time 32676979 ps
CPU time 1.52 seconds
Started Apr 25 12:59:05 PM PDT 24
Finished Apr 25 12:59:18 PM PDT 24
Peak memory 212520 kb
Host smart-a240fecf-1420-4470-9653-d7806190392e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173702993 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.2173702993
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2048889682
Short name T144
Test name
Test status
Simulation time 22881255 ps
CPU time 0.69 seconds
Started Apr 25 12:59:02 PM PDT 24
Finished Apr 25 12:59:05 PM PDT 24
Peak memory 204044 kb
Host smart-e49469bb-e04b-45fd-8c9f-302fc23bd60f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048889682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2048889682
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3322713982
Short name T1394
Test name
Test status
Simulation time 48798170 ps
CPU time 0.65 seconds
Started Apr 25 12:58:53 PM PDT 24
Finished Apr 25 12:58:57 PM PDT 24
Peak memory 204004 kb
Host smart-5a96772a-3265-4861-923e-621ecd8f8856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322713982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3322713982
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3933657873
Short name T109
Test name
Test status
Simulation time 365940291 ps
CPU time 2.18 seconds
Started Apr 25 12:59:02 PM PDT 24
Finished Apr 25 12:59:06 PM PDT 24
Peak memory 204308 kb
Host smart-91e87b2b-161b-43ff-a422-de75ed792a12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933657873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3933657873
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.1656942556
Short name T1409
Test name
Test status
Simulation time 577240266 ps
CPU time 2.3 seconds
Started Apr 25 12:58:52 PM PDT 24
Finished Apr 25 12:58:56 PM PDT 24
Peak memory 204276 kb
Host smart-3e21d6c5-c122-471c-ae75-a8e260847e79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656942556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1656942556
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.584490005
Short name T1437
Test name
Test status
Simulation time 114812857 ps
CPU time 0.93 seconds
Started Apr 25 12:59:29 PM PDT 24
Finished Apr 25 12:59:31 PM PDT 24
Peak memory 204048 kb
Host smart-1e033f58-8f5c-479b-8840-65bfb15882b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584490005 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.584490005
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.1163686774
Short name T1418
Test name
Test status
Simulation time 159594891 ps
CPU time 0.62 seconds
Started Apr 25 12:59:03 PM PDT 24
Finished Apr 25 12:59:05 PM PDT 24
Peak memory 204016 kb
Host smart-7386abfc-3594-45df-9869-4d474fe716ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163686774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1163686774
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1211004777
Short name T1432
Test name
Test status
Simulation time 38147057 ps
CPU time 0.87 seconds
Started Apr 25 12:59:12 PM PDT 24
Finished Apr 25 12:59:16 PM PDT 24
Peak memory 203976 kb
Host smart-15abe204-a092-4db6-9870-fab48058733f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211004777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.1211004777
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.831442854
Short name T133
Test name
Test status
Simulation time 32975039 ps
CPU time 1.03 seconds
Started Apr 25 12:59:08 PM PDT 24
Finished Apr 25 12:59:11 PM PDT 24
Peak memory 204168 kb
Host smart-9348fc49-f212-4efd-bce3-c2113755e33b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831442854 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.831442854
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2770477693
Short name T1408
Test name
Test status
Simulation time 35703906 ps
CPU time 0.69 seconds
Started Apr 25 12:59:15 PM PDT 24
Finished Apr 25 12:59:18 PM PDT 24
Peak memory 203924 kb
Host smart-8ecd9e18-2355-4661-b306-bd5ec8dbcca4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770477693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2770477693
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.76566443
Short name T1364
Test name
Test status
Simulation time 17141483 ps
CPU time 0.73 seconds
Started Apr 25 12:59:34 PM PDT 24
Finished Apr 25 12:59:37 PM PDT 24
Peak memory 203952 kb
Host smart-21b6681e-68d2-4346-9c4e-918d5ae8c366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76566443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.76566443
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1050098985
Short name T1445
Test name
Test status
Simulation time 59751640 ps
CPU time 1.62 seconds
Started Apr 25 12:59:20 PM PDT 24
Finished Apr 25 12:59:23 PM PDT 24
Peak memory 204232 kb
Host smart-d68e50a8-daaf-481d-8787-1041351d30e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050098985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1050098985
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3242742607
Short name T131
Test name
Test status
Simulation time 354034258 ps
CPU time 1.46 seconds
Started Apr 25 12:59:10 PM PDT 24
Finished Apr 25 12:59:15 PM PDT 24
Peak memory 204316 kb
Host smart-4052a39e-a45e-453d-a5bf-167f9d063432
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242742607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.3242742607
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.4140241853
Short name T1428
Test name
Test status
Simulation time 101600817 ps
CPU time 1.45 seconds
Started Apr 25 12:59:18 PM PDT 24
Finished Apr 25 12:59:21 PM PDT 24
Peak memory 204312 kb
Host smart-7fc62699-88f9-4214-8af5-b03272b2e02d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140241853 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.4140241853
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.487985421
Short name T137
Test name
Test status
Simulation time 26762955 ps
CPU time 0.79 seconds
Started Apr 25 12:59:08 PM PDT 24
Finished Apr 25 12:59:11 PM PDT 24
Peak memory 203964 kb
Host smart-4c093015-aba2-4585-972e-6a77bd452163
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487985421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.487985421
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.132749900
Short name T1436
Test name
Test status
Simulation time 43015711 ps
CPU time 0.69 seconds
Started Apr 25 12:59:30 PM PDT 24
Finished Apr 25 12:59:32 PM PDT 24
Peak memory 204036 kb
Host smart-b42f88fb-a265-47c9-b860-de4fe1c4072b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132749900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.132749900
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.3135989525
Short name T1393
Test name
Test status
Simulation time 154736050 ps
CPU time 2.55 seconds
Started Apr 25 12:59:31 PM PDT 24
Finished Apr 25 12:59:35 PM PDT 24
Peak memory 204308 kb
Host smart-6867280e-790b-4e9b-b656-40d02791b096
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135989525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.3135989525
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.725707960
Short name T119
Test name
Test status
Simulation time 255741288 ps
CPU time 1.51 seconds
Started Apr 25 12:59:10 PM PDT 24
Finished Apr 25 12:59:13 PM PDT 24
Peak memory 204248 kb
Host smart-fb6fa2ab-e962-4a26-97b9-a9f1c6458f20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725707960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.725707960
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3032609038
Short name T134
Test name
Test status
Simulation time 113645374 ps
CPU time 0.92 seconds
Started Apr 25 12:59:04 PM PDT 24
Finished Apr 25 12:59:07 PM PDT 24
Peak memory 204052 kb
Host smart-812f9fc0-f8ee-4ccd-adc0-64f275d16a5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032609038 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.3032609038
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.2450677748
Short name T1400
Test name
Test status
Simulation time 40146772 ps
CPU time 0.63 seconds
Started Apr 25 12:59:43 PM PDT 24
Finished Apr 25 12:59:45 PM PDT 24
Peak memory 203948 kb
Host smart-610a829d-78ef-4f54-93d0-abc679a974f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450677748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2450677748
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.2093257620
Short name T108
Test name
Test status
Simulation time 27433635 ps
CPU time 1.29 seconds
Started Apr 25 12:59:20 PM PDT 24
Finished Apr 25 12:59:23 PM PDT 24
Peak memory 204212 kb
Host smart-647c1c67-825e-4440-9f13-820d50e37b9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093257620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2093257620
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3691889988
Short name T1385
Test name
Test status
Simulation time 46363304 ps
CPU time 0.85 seconds
Started Apr 25 12:59:34 PM PDT 24
Finished Apr 25 12:59:36 PM PDT 24
Peak memory 203972 kb
Host smart-6aea56b3-3370-41f5-b444-cb379edcf107
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691889988 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3691889988
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2641832838
Short name T1378
Test name
Test status
Simulation time 41252926 ps
CPU time 0.76 seconds
Started Apr 25 12:59:13 PM PDT 24
Finished Apr 25 12:59:16 PM PDT 24
Peak memory 203988 kb
Host smart-3a1832fe-1711-408c-9531-1479919bba21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641832838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2641832838
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.1563677708
Short name T1359
Test name
Test status
Simulation time 53170439 ps
CPU time 0.65 seconds
Started Apr 25 12:59:18 PM PDT 24
Finished Apr 25 12:59:20 PM PDT 24
Peak memory 204004 kb
Host smart-798b27f7-a490-4196-93ed-31ebfbf9219a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563677708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1563677708
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2685087740
Short name T1381
Test name
Test status
Simulation time 27486614 ps
CPU time 1.36 seconds
Started Apr 25 12:59:23 PM PDT 24
Finished Apr 25 12:59:25 PM PDT 24
Peak memory 204304 kb
Host smart-6e6abf4f-a112-4054-a4d5-eeb33b57c2f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685087740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2685087740
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2906817628
Short name T132
Test name
Test status
Simulation time 235567103 ps
CPU time 0.79 seconds
Started Apr 25 12:59:29 PM PDT 24
Finished Apr 25 12:59:31 PM PDT 24
Peak memory 204056 kb
Host smart-feb02ef6-3b55-4884-bc88-9c8f584e2e4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906817628 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.2906817628
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2015245978
Short name T1443
Test name
Test status
Simulation time 18772936 ps
CPU time 0.67 seconds
Started Apr 25 12:59:20 PM PDT 24
Finished Apr 25 12:59:22 PM PDT 24
Peak memory 204048 kb
Host smart-443a5550-97df-4429-9b28-5baf83424490
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015245978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2015245978
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.3324328670
Short name T1411
Test name
Test status
Simulation time 30331103 ps
CPU time 0.67 seconds
Started Apr 25 12:59:19 PM PDT 24
Finished Apr 25 12:59:21 PM PDT 24
Peak memory 203964 kb
Host smart-32c68af9-cabd-404b-9f4b-16bcfb05d509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324328670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3324328670
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2331234967
Short name T1407
Test name
Test status
Simulation time 121771225 ps
CPU time 1.2 seconds
Started Apr 25 12:59:38 PM PDT 24
Finished Apr 25 12:59:41 PM PDT 24
Peak memory 204260 kb
Host smart-2ff41222-543e-4040-8c79-10389933c966
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331234967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.2331234967
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2998696385
Short name T1441
Test name
Test status
Simulation time 70237250 ps
CPU time 2.08 seconds
Started Apr 25 12:59:28 PM PDT 24
Finished Apr 25 12:59:31 PM PDT 24
Peak memory 204328 kb
Host smart-9ef30f40-0d2c-4225-81c2-5989f00fb2a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998696385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2998696385
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3783324370
Short name T118
Test name
Test status
Simulation time 219317473 ps
CPU time 1.45 seconds
Started Apr 25 12:59:23 PM PDT 24
Finished Apr 25 12:59:26 PM PDT 24
Peak memory 204248 kb
Host smart-bf5b6acc-e161-47cc-a336-d89f20c71388
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783324370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3783324370
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.278773551
Short name T1387
Test name
Test status
Simulation time 216423512 ps
CPU time 1.51 seconds
Started Apr 25 12:59:22 PM PDT 24
Finished Apr 25 12:59:25 PM PDT 24
Peak memory 204188 kb
Host smart-b79c224b-5420-4e73-9bf2-77cefed28833
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278773551 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.278773551
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3421222215
Short name T1427
Test name
Test status
Simulation time 19387334 ps
CPU time 0.7 seconds
Started Apr 25 12:59:25 PM PDT 24
Finished Apr 25 12:59:27 PM PDT 24
Peak memory 204056 kb
Host smart-d09895f0-5e6e-461f-814f-df5fc9da0c72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421222215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.3421222215
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.3955472659
Short name T1361
Test name
Test status
Simulation time 64784194 ps
CPU time 0.66 seconds
Started Apr 25 12:59:22 PM PDT 24
Finished Apr 25 12:59:24 PM PDT 24
Peak memory 204000 kb
Host smart-d1234cea-8b6c-418b-b519-95eb52a5a7ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955472659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.3955472659
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1016560938
Short name T1406
Test name
Test status
Simulation time 45066650 ps
CPU time 0.9 seconds
Started Apr 25 12:59:31 PM PDT 24
Finished Apr 25 12:59:33 PM PDT 24
Peak memory 204108 kb
Host smart-2a98570b-fa79-4474-bf35-604327a542fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016560938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.1016560938
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.171138579
Short name T127
Test name
Test status
Simulation time 81268608 ps
CPU time 1.32 seconds
Started Apr 25 12:59:28 PM PDT 24
Finished Apr 25 12:59:31 PM PDT 24
Peak memory 204244 kb
Host smart-390dbb83-de5c-4381-8b35-db8a5d545ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171138579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.171138579
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.1319750174
Short name T1414
Test name
Test status
Simulation time 351014596 ps
CPU time 0.91 seconds
Started Apr 25 12:59:16 PM PDT 24
Finished Apr 25 12:59:18 PM PDT 24
Peak memory 204108 kb
Host smart-18d37042-963d-49be-9787-ccb2ead011bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319750174 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.1319750174
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.422121547
Short name T138
Test name
Test status
Simulation time 88292994 ps
CPU time 0.7 seconds
Started Apr 25 12:59:26 PM PDT 24
Finished Apr 25 12:59:28 PM PDT 24
Peak memory 204040 kb
Host smart-4d093418-3464-480b-aff2-d9f799e69320
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422121547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.422121547
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.2838228237
Short name T1442
Test name
Test status
Simulation time 42097138 ps
CPU time 0.68 seconds
Started Apr 25 12:59:15 PM PDT 24
Finished Apr 25 12:59:17 PM PDT 24
Peak memory 203960 kb
Host smart-c45df584-ef36-4199-b25a-c90b17573c2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838228237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2838228237
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3671434171
Short name T1416
Test name
Test status
Simulation time 117431296 ps
CPU time 2.46 seconds
Started Apr 25 12:59:26 PM PDT 24
Finished Apr 25 12:59:30 PM PDT 24
Peak memory 204196 kb
Host smart-393f0e7d-d77c-4384-a50d-fdb6e01e38da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671434171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3671434171
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3544250439
Short name T1388
Test name
Test status
Simulation time 58603767 ps
CPU time 1.28 seconds
Started Apr 25 12:59:11 PM PDT 24
Finished Apr 25 12:59:15 PM PDT 24
Peak memory 220692 kb
Host smart-980abdcc-088d-44f3-8c33-fd153abec55e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544250439 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3544250439
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3083631525
Short name T142
Test name
Test status
Simulation time 21057771 ps
CPU time 0.79 seconds
Started Apr 25 12:59:12 PM PDT 24
Finished Apr 25 12:59:16 PM PDT 24
Peak memory 204092 kb
Host smart-fba8be3f-1d1e-4698-a1b0-6203b70b66b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083631525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3083631525
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.2410634913
Short name T1371
Test name
Test status
Simulation time 118400252 ps
CPU time 0.65 seconds
Started Apr 25 12:59:22 PM PDT 24
Finished Apr 25 12:59:23 PM PDT 24
Peak memory 203988 kb
Host smart-7db15fe4-35ce-41a8-bc4e-b0ed9dad3ce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410634913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2410634913
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1033912209
Short name T1439
Test name
Test status
Simulation time 38859968 ps
CPU time 1.19 seconds
Started Apr 25 12:59:11 PM PDT 24
Finished Apr 25 12:59:15 PM PDT 24
Peak memory 204264 kb
Host smart-bdfd8325-b770-415f-93ec-feed4048f5e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033912209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.1033912209
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2967783169
Short name T153
Test name
Test status
Simulation time 668050967 ps
CPU time 2.45 seconds
Started Apr 25 12:59:35 PM PDT 24
Finished Apr 25 12:59:40 PM PDT 24
Peak memory 204220 kb
Host smart-b989c035-5f5d-4416-b604-bf6b727acf36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967783169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2967783169
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.276784491
Short name T1430
Test name
Test status
Simulation time 47397908 ps
CPU time 0.83 seconds
Started Apr 25 12:59:19 PM PDT 24
Finished Apr 25 12:59:21 PM PDT 24
Peak memory 204164 kb
Host smart-da8398af-1d5f-46df-a067-03888a39b868
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276784491 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.276784491
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.2168412515
Short name T1396
Test name
Test status
Simulation time 45777075 ps
CPU time 0.66 seconds
Started Apr 25 12:59:10 PM PDT 24
Finished Apr 25 12:59:14 PM PDT 24
Peak memory 204000 kb
Host smart-0c8dc90b-7e6f-49b6-a889-2660db4fd948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168412515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2168412515
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3081739638
Short name T76
Test name
Test status
Simulation time 129075990 ps
CPU time 1.15 seconds
Started Apr 25 12:59:38 PM PDT 24
Finished Apr 25 12:59:42 PM PDT 24
Peak memory 204236 kb
Host smart-278d96af-bc34-4bea-93bb-5062d57e1e4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081739638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.3081739638
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1555698671
Short name T117
Test name
Test status
Simulation time 518652947 ps
CPU time 2.63 seconds
Started Apr 25 12:59:18 PM PDT 24
Finished Apr 25 12:59:22 PM PDT 24
Peak memory 204268 kb
Host smart-b5f6267d-b5d9-45d5-a19b-ba2fbf1e3150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555698671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.1555698671
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3377850473
Short name T187
Test name
Test status
Simulation time 72814505 ps
CPU time 1.44 seconds
Started Apr 25 12:59:34 PM PDT 24
Finished Apr 25 12:59:37 PM PDT 24
Peak memory 204260 kb
Host smart-d3512247-dfd4-4518-ba18-40e76bfeeb7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377850473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.3377850473
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.351356269
Short name T141
Test name
Test status
Simulation time 514639259 ps
CPU time 2.13 seconds
Started Apr 25 12:59:00 PM PDT 24
Finished Apr 25 12:59:04 PM PDT 24
Peak memory 204328 kb
Host smart-a0884b8d-3f38-4de9-aa50-3760b7f957cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351356269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.351356269
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1053737322
Short name T148
Test name
Test status
Simulation time 49633269 ps
CPU time 0.69 seconds
Started Apr 25 12:59:16 PM PDT 24
Finished Apr 25 12:59:18 PM PDT 24
Peak memory 203980 kb
Host smart-35719855-bf09-4fa2-833f-8065c7a217e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053737322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.1053737322
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1436363879
Short name T1421
Test name
Test status
Simulation time 15201388 ps
CPU time 0.69 seconds
Started Apr 25 12:58:58 PM PDT 24
Finished Apr 25 12:59:01 PM PDT 24
Peak memory 204016 kb
Host smart-f43f47ef-63c7-457c-a5b9-2e4c83c1e968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436363879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1436363879
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2020609792
Short name T146
Test name
Test status
Simulation time 290581310 ps
CPU time 0.83 seconds
Started Apr 25 12:59:06 PM PDT 24
Finished Apr 25 12:59:09 PM PDT 24
Peak memory 204044 kb
Host smart-9241f4ce-bad7-4a3d-8fd0-9c81900c1476
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020609792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.2020609792
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.501516632
Short name T1376
Test name
Test status
Simulation time 169091954 ps
CPU time 2.36 seconds
Started Apr 25 12:58:56 PM PDT 24
Finished Apr 25 12:59:01 PM PDT 24
Peak memory 204280 kb
Host smart-1c6e8650-f5f2-4944-b1c9-755bbe7980f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501516632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.501516632
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.932243846
Short name T120
Test name
Test status
Simulation time 175705939 ps
CPU time 2.14 seconds
Started Apr 25 12:58:53 PM PDT 24
Finished Apr 25 12:58:59 PM PDT 24
Peak memory 204368 kb
Host smart-9aa9bdba-3c67-4ead-a151-c5a9c9ded4ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932243846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.932243846
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.4104192129
Short name T1391
Test name
Test status
Simulation time 30443996 ps
CPU time 0.65 seconds
Started Apr 25 12:59:24 PM PDT 24
Finished Apr 25 12:59:26 PM PDT 24
Peak memory 203992 kb
Host smart-2b116201-0fe0-4e66-8418-c6fa455a4146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104192129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.4104192129
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.2909944343
Short name T1422
Test name
Test status
Simulation time 36427719 ps
CPU time 0.66 seconds
Started Apr 25 12:59:13 PM PDT 24
Finished Apr 25 12:59:16 PM PDT 24
Peak memory 203980 kb
Host smart-14691914-2511-4540-9433-072bc7987d82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909944343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.2909944343
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.3145196123
Short name T1372
Test name
Test status
Simulation time 54822170 ps
CPU time 0.68 seconds
Started Apr 25 12:59:28 PM PDT 24
Finished Apr 25 12:59:30 PM PDT 24
Peak memory 204040 kb
Host smart-c95094a3-9e63-4a5f-9a6d-34e0d2a5ab92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145196123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3145196123
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.150619321
Short name T1412
Test name
Test status
Simulation time 17468288 ps
CPU time 0.71 seconds
Started Apr 25 12:59:28 PM PDT 24
Finished Apr 25 12:59:29 PM PDT 24
Peak memory 203940 kb
Host smart-0593e682-0f22-4b91-b663-e076794306f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150619321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.150619321
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.1179191841
Short name T1425
Test name
Test status
Simulation time 45567496 ps
CPU time 0.65 seconds
Started Apr 25 12:59:13 PM PDT 24
Finished Apr 25 12:59:17 PM PDT 24
Peak memory 203212 kb
Host smart-2f48a973-0da1-40b8-9df4-877fe3f4c655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179191841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.1179191841
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.401162138
Short name T1363
Test name
Test status
Simulation time 51759748 ps
CPU time 0.67 seconds
Started Apr 25 12:59:08 PM PDT 24
Finished Apr 25 12:59:10 PM PDT 24
Peak memory 204012 kb
Host smart-a17a2a98-4a61-4f4e-af43-632fb826c758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401162138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.401162138
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.3657095537
Short name T1440
Test name
Test status
Simulation time 43513762 ps
CPU time 0.65 seconds
Started Apr 25 12:59:43 PM PDT 24
Finished Apr 25 12:59:45 PM PDT 24
Peak memory 203940 kb
Host smart-cedcb5a8-d15d-49d7-810b-c2d9dc135d29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657095537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.3657095537
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.2166271538
Short name T1375
Test name
Test status
Simulation time 18363674 ps
CPU time 0.65 seconds
Started Apr 25 12:59:30 PM PDT 24
Finished Apr 25 12:59:31 PM PDT 24
Peak memory 204020 kb
Host smart-da2da1eb-f3fd-4e4a-a173-04636ac371da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166271538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2166271538
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.1873349129
Short name T1380
Test name
Test status
Simulation time 31695979 ps
CPU time 0.6 seconds
Started Apr 25 12:59:18 PM PDT 24
Finished Apr 25 12:59:20 PM PDT 24
Peak memory 203192 kb
Host smart-fc3bfbf9-848e-4556-8a67-b95483fa0d98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873349129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.1873349129
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.240192812
Short name T1398
Test name
Test status
Simulation time 26138261 ps
CPU time 0.7 seconds
Started Apr 25 12:59:12 PM PDT 24
Finished Apr 25 12:59:16 PM PDT 24
Peak memory 203944 kb
Host smart-2d8fac56-acf2-47da-b211-44bcfdbb852b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240192812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.240192812
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1190664415
Short name T136
Test name
Test status
Simulation time 50684555 ps
CPU time 0.68 seconds
Started Apr 25 12:59:08 PM PDT 24
Finished Apr 25 12:59:10 PM PDT 24
Peak memory 203984 kb
Host smart-b45dfc28-f6dd-4c74-a138-e3ce18a9d92b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190664415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1190664415
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2788592407
Short name T1404
Test name
Test status
Simulation time 37425380 ps
CPU time 1.06 seconds
Started Apr 25 12:59:08 PM PDT 24
Finished Apr 25 12:59:11 PM PDT 24
Peak memory 204024 kb
Host smart-db235c9d-adf2-4ca7-b1ac-9ad276526221
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788592407 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.2788592407
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.2715349257
Short name T1450
Test name
Test status
Simulation time 35211093 ps
CPU time 0.68 seconds
Started Apr 25 12:58:54 PM PDT 24
Finished Apr 25 12:58:58 PM PDT 24
Peak memory 203988 kb
Host smart-7dcca358-8d19-4400-bd6a-a1c5734d38c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715349257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.2715349257
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.2543443885
Short name T1362
Test name
Test status
Simulation time 15990111 ps
CPU time 0.64 seconds
Started Apr 25 12:59:00 PM PDT 24
Finished Apr 25 12:59:03 PM PDT 24
Peak memory 203992 kb
Host smart-3ca43209-7f22-49e2-bc56-8b5822e62009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543443885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.2543443885
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3407332700
Short name T147
Test name
Test status
Simulation time 57301779 ps
CPU time 0.84 seconds
Started Apr 25 12:59:08 PM PDT 24
Finished Apr 25 12:59:11 PM PDT 24
Peak memory 204040 kb
Host smart-d198f0d1-a1a8-4a77-b145-8304100ab9fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407332700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.3407332700
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1803240845
Short name T1420
Test name
Test status
Simulation time 447489719 ps
CPU time 1.39 seconds
Started Apr 25 12:59:20 PM PDT 24
Finished Apr 25 12:59:23 PM PDT 24
Peak memory 204264 kb
Host smart-7d352bb2-00ea-4977-a7d5-e2c26466bbfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803240845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1803240845
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.4226601574
Short name T1392
Test name
Test status
Simulation time 83818543 ps
CPU time 1.51 seconds
Started Apr 25 12:59:17 PM PDT 24
Finished Apr 25 12:59:19 PM PDT 24
Peak memory 204268 kb
Host smart-cc82db86-7915-4d7f-b26b-039870897e33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226601574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.4226601574
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.2700925653
Short name T1433
Test name
Test status
Simulation time 15985447 ps
CPU time 0.68 seconds
Started Apr 25 12:59:21 PM PDT 24
Finished Apr 25 12:59:23 PM PDT 24
Peak memory 204016 kb
Host smart-30f773a2-8fcc-4771-aae6-99000b46aebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700925653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.2700925653
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2954336272
Short name T1426
Test name
Test status
Simulation time 44610798 ps
CPU time 0.68 seconds
Started Apr 25 12:59:39 PM PDT 24
Finished Apr 25 12:59:42 PM PDT 24
Peak memory 203976 kb
Host smart-14a5b76d-d06f-464d-ab6f-4b4dcd858cc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954336272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2954336272
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.2393948815
Short name T1444
Test name
Test status
Simulation time 196426564 ps
CPU time 0.65 seconds
Started Apr 25 12:59:25 PM PDT 24
Finished Apr 25 12:59:32 PM PDT 24
Peak memory 203984 kb
Host smart-d82619e8-a955-4dde-bc32-520b7b22fe8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393948815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2393948815
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.491294276
Short name T1360
Test name
Test status
Simulation time 15886157 ps
CPU time 0.65 seconds
Started Apr 25 12:59:29 PM PDT 24
Finished Apr 25 12:59:31 PM PDT 24
Peak memory 203924 kb
Host smart-b53f365c-73af-466f-9437-80320be73114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491294276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.491294276
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.3105407956
Short name T1417
Test name
Test status
Simulation time 18696325 ps
CPU time 0.68 seconds
Started Apr 25 12:59:25 PM PDT 24
Finished Apr 25 12:59:27 PM PDT 24
Peak memory 203956 kb
Host smart-2dc09dd8-61f7-4f3c-a81e-c175ccdf77df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105407956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3105407956
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.1477978305
Short name T1410
Test name
Test status
Simulation time 43457387 ps
CPU time 0.64 seconds
Started Apr 25 12:59:30 PM PDT 24
Finished Apr 25 12:59:32 PM PDT 24
Peak memory 203908 kb
Host smart-01dc8360-5c70-40e2-83ed-a723c74c5766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477978305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1477978305
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.3059605710
Short name T1382
Test name
Test status
Simulation time 16825219 ps
CPU time 0.66 seconds
Started Apr 25 12:59:21 PM PDT 24
Finished Apr 25 12:59:23 PM PDT 24
Peak memory 204016 kb
Host smart-e90e126b-8254-4a88-9e28-db0f7f56c2b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059605710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3059605710
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.1286645914
Short name T1357
Test name
Test status
Simulation time 18686021 ps
CPU time 0.67 seconds
Started Apr 25 12:59:13 PM PDT 24
Finished Apr 25 12:59:16 PM PDT 24
Peak memory 203968 kb
Host smart-fa606fd7-9613-4aba-8539-dd9529e5c433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286645914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1286645914
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.897458396
Short name T1446
Test name
Test status
Simulation time 65108015 ps
CPU time 0.66 seconds
Started Apr 25 12:59:33 PM PDT 24
Finished Apr 25 12:59:35 PM PDT 24
Peak memory 203912 kb
Host smart-95881d60-82bb-4d4b-96f7-71eb6af5f81a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897458396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.897458396
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.2028374271
Short name T1369
Test name
Test status
Simulation time 58135315 ps
CPU time 0.69 seconds
Started Apr 25 12:59:12 PM PDT 24
Finished Apr 25 12:59:16 PM PDT 24
Peak memory 204008 kb
Host smart-93a0fe39-3e43-4ec7-8142-1eef3d5b0120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028374271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.2028374271
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3476952615
Short name T1438
Test name
Test status
Simulation time 119051921 ps
CPU time 1.29 seconds
Started Apr 25 12:59:24 PM PDT 24
Finished Apr 25 12:59:26 PM PDT 24
Peak memory 204188 kb
Host smart-9bf82e62-bc17-46d6-a758-da17a0826e4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476952615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3476952615
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2223900472
Short name T1383
Test name
Test status
Simulation time 24906716 ps
CPU time 0.76 seconds
Started Apr 25 12:59:31 PM PDT 24
Finished Apr 25 12:59:33 PM PDT 24
Peak memory 204044 kb
Host smart-bea89321-489e-4255-a40c-ef92fe33bf53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223900472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2223900472
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.4049714648
Short name T74
Test name
Test status
Simulation time 94444194 ps
CPU time 0.82 seconds
Started Apr 25 12:59:09 PM PDT 24
Finished Apr 25 12:59:12 PM PDT 24
Peak memory 204024 kb
Host smart-d78af2aa-3bb8-4df6-bc71-a62dec161898
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049714648 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.4049714648
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3157564075
Short name T1367
Test name
Test status
Simulation time 45456973 ps
CPU time 0.67 seconds
Started Apr 25 12:59:11 PM PDT 24
Finished Apr 25 12:59:15 PM PDT 24
Peak memory 204072 kb
Host smart-a9f62ebb-ed91-4bb9-87c6-9a003d1c0106
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157564075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.3157564075
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.1939258928
Short name T1358
Test name
Test status
Simulation time 41497630 ps
CPU time 0.65 seconds
Started Apr 25 12:59:08 PM PDT 24
Finished Apr 25 12:59:10 PM PDT 24
Peak memory 203992 kb
Host smart-6266a270-b6e2-4d5d-9798-fb22b2a10bb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939258928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1939258928
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3332493137
Short name T1429
Test name
Test status
Simulation time 68631370 ps
CPU time 0.82 seconds
Started Apr 25 12:59:27 PM PDT 24
Finished Apr 25 12:59:28 PM PDT 24
Peak memory 204036 kb
Host smart-31e5f236-2083-44ee-bc79-c34d990aba24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332493137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.3332493137
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2221312708
Short name T1397
Test name
Test status
Simulation time 43292683 ps
CPU time 1.97 seconds
Started Apr 25 12:59:27 PM PDT 24
Finished Apr 25 12:59:30 PM PDT 24
Peak memory 204236 kb
Host smart-ced178e1-b1fe-4680-b4c4-a764f5a3642c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221312708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2221312708
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3190146851
Short name T130
Test name
Test status
Simulation time 181178306 ps
CPU time 2.34 seconds
Started Apr 25 12:59:16 PM PDT 24
Finished Apr 25 12:59:20 PM PDT 24
Peak memory 204236 kb
Host smart-dae40b30-6c65-493e-ae07-616160d70b63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190146851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3190146851
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.3484223063
Short name T1405
Test name
Test status
Simulation time 45528596 ps
CPU time 0.68 seconds
Started Apr 25 12:59:13 PM PDT 24
Finished Apr 25 12:59:16 PM PDT 24
Peak memory 203956 kb
Host smart-3513b697-0608-4c37-b84f-3470c5cf6769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484223063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3484223063
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.1931821417
Short name T1365
Test name
Test status
Simulation time 27367109 ps
CPU time 0.63 seconds
Started Apr 25 12:59:09 PM PDT 24
Finished Apr 25 12:59:12 PM PDT 24
Peak memory 204016 kb
Host smart-5cdde78a-bcba-4bd4-a310-f943654c4e25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931821417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1931821417
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.337412373
Short name T1399
Test name
Test status
Simulation time 39011674 ps
CPU time 0.67 seconds
Started Apr 25 12:59:11 PM PDT 24
Finished Apr 25 12:59:15 PM PDT 24
Peak memory 204016 kb
Host smart-5cc0c116-b84f-4d64-b611-7d2d35e3eed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337412373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.337412373
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.2863582168
Short name T1402
Test name
Test status
Simulation time 17904015 ps
CPU time 0.66 seconds
Started Apr 25 12:59:33 PM PDT 24
Finished Apr 25 12:59:40 PM PDT 24
Peak memory 203960 kb
Host smart-14ac467a-6245-4864-80fb-7b4351f59db7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863582168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.2863582168
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1871424774
Short name T1390
Test name
Test status
Simulation time 56828775 ps
CPU time 0.69 seconds
Started Apr 25 12:59:34 PM PDT 24
Finished Apr 25 12:59:36 PM PDT 24
Peak memory 203920 kb
Host smart-507a0956-189f-43a1-a833-e37dc0919e5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871424774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1871424774
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2855944199
Short name T1377
Test name
Test status
Simulation time 16381473 ps
CPU time 0.68 seconds
Started Apr 25 12:59:36 PM PDT 24
Finished Apr 25 12:59:39 PM PDT 24
Peak memory 204028 kb
Host smart-58b5f785-aad9-466d-9490-23124cab9232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855944199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2855944199
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.2392482131
Short name T1419
Test name
Test status
Simulation time 33077163 ps
CPU time 0.68 seconds
Started Apr 25 12:59:21 PM PDT 24
Finished Apr 25 12:59:23 PM PDT 24
Peak memory 204008 kb
Host smart-4eec5c8b-7071-40f1-b09e-f10524d7fbfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392482131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2392482131
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.3585900463
Short name T1395
Test name
Test status
Simulation time 176761640 ps
CPU time 0.69 seconds
Started Apr 25 12:59:39 PM PDT 24
Finished Apr 25 12:59:42 PM PDT 24
Peak memory 203980 kb
Host smart-a1db4e16-ab21-4f63-b1d0-7fc949429edc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585900463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3585900463
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.829096187
Short name T1370
Test name
Test status
Simulation time 91263294 ps
CPU time 0.76 seconds
Started Apr 25 12:59:38 PM PDT 24
Finished Apr 25 12:59:41 PM PDT 24
Peak memory 203924 kb
Host smart-683daace-a2b4-428b-9e9c-5bec60281b27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829096187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.829096187
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.3464159305
Short name T1449
Test name
Test status
Simulation time 45102568 ps
CPU time 0.65 seconds
Started Apr 25 12:59:26 PM PDT 24
Finished Apr 25 12:59:28 PM PDT 24
Peak memory 203912 kb
Host smart-fc654688-7a18-408e-a486-903fe9cdac52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464159305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.3464159305
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1586182138
Short name T154
Test name
Test status
Simulation time 38628487 ps
CPU time 0.98 seconds
Started Apr 25 12:59:18 PM PDT 24
Finished Apr 25 12:59:21 PM PDT 24
Peak memory 204108 kb
Host smart-553f657a-b5c0-4b41-a0af-0b5b90b75675
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586182138 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.1586182138
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3716139342
Short name T140
Test name
Test status
Simulation time 16660412 ps
CPU time 0.67 seconds
Started Apr 25 12:59:19 PM PDT 24
Finished Apr 25 12:59:21 PM PDT 24
Peak memory 203996 kb
Host smart-c3688470-b0dc-4f76-924d-7b83aadcb3d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716139342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3716139342
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.3506589574
Short name T1423
Test name
Test status
Simulation time 17163529 ps
CPU time 0.66 seconds
Started Apr 25 12:59:02 PM PDT 24
Finished Apr 25 12:59:05 PM PDT 24
Peak memory 204008 kb
Host smart-0019bb1d-d86c-4e1b-bae4-3337ce712832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506589574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3506589574
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1938581606
Short name T1424
Test name
Test status
Simulation time 64777959 ps
CPU time 1.02 seconds
Started Apr 25 12:59:03 PM PDT 24
Finished Apr 25 12:59:16 PM PDT 24
Peak memory 204156 kb
Host smart-7237653a-cac5-44fe-86e5-1f5202f9b60c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938581606 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.1938581606
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2524371670
Short name T135
Test name
Test status
Simulation time 27742668 ps
CPU time 0.7 seconds
Started Apr 25 12:59:19 PM PDT 24
Finished Apr 25 12:59:21 PM PDT 24
Peak memory 203996 kb
Host smart-b04a5c8f-7349-421d-9e00-d3798afe956c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524371670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2524371670
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.3371593135
Short name T1386
Test name
Test status
Simulation time 59309207 ps
CPU time 0.7 seconds
Started Apr 25 12:59:01 PM PDT 24
Finished Apr 25 12:59:09 PM PDT 24
Peak memory 204004 kb
Host smart-9d5022cc-513f-441f-9f27-ebbb895e57b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371593135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.3371593135
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2914987320
Short name T149
Test name
Test status
Simulation time 77296627 ps
CPU time 0.91 seconds
Started Apr 25 12:59:08 PM PDT 24
Finished Apr 25 12:59:10 PM PDT 24
Peak memory 204056 kb
Host smart-0ef482ef-cb97-4c27-8833-f54663474af9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914987320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.2914987320
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1667281091
Short name T1431
Test name
Test status
Simulation time 25862345 ps
CPU time 1.1 seconds
Started Apr 25 12:59:29 PM PDT 24
Finished Apr 25 12:59:31 PM PDT 24
Peak memory 204220 kb
Host smart-752762af-8446-45f9-9cce-0791f319410a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667281091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1667281091
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.202434428
Short name T152
Test name
Test status
Simulation time 19531905 ps
CPU time 0.71 seconds
Started Apr 25 12:59:03 PM PDT 24
Finished Apr 25 12:59:05 PM PDT 24
Peak memory 204084 kb
Host smart-a69cf913-bdfc-49ae-ac2e-c64023a58a26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202434428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.202434428
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.3905357799
Short name T1434
Test name
Test status
Simulation time 23590370 ps
CPU time 0.68 seconds
Started Apr 25 12:59:12 PM PDT 24
Finished Apr 25 12:59:16 PM PDT 24
Peak memory 204004 kb
Host smart-3605e197-a9a4-4a18-8a5c-3d3eb87de9df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905357799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.3905357799
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1901322655
Short name T1448
Test name
Test status
Simulation time 90145177 ps
CPU time 1.09 seconds
Started Apr 25 12:59:10 PM PDT 24
Finished Apr 25 12:59:14 PM PDT 24
Peak memory 204000 kb
Host smart-035dae4a-bfc5-4adb-8278-f0265c25d9ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901322655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.1901322655
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.432076138
Short name T121
Test name
Test status
Simulation time 287359456 ps
CPU time 2.44 seconds
Started Apr 25 12:59:05 PM PDT 24
Finished Apr 25 12:59:10 PM PDT 24
Peak memory 204212 kb
Host smart-268b04c7-da73-4893-b075-2a38e6490487
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432076138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.432076138
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1890812613
Short name T1384
Test name
Test status
Simulation time 148591554 ps
CPU time 1.02 seconds
Started Apr 25 12:59:11 PM PDT 24
Finished Apr 25 12:59:15 PM PDT 24
Peak memory 204168 kb
Host smart-503441b3-078c-4836-8a36-cd075617ba25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890812613 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1890812613
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1008252687
Short name T1368
Test name
Test status
Simulation time 54875770 ps
CPU time 0.65 seconds
Started Apr 25 12:59:07 PM PDT 24
Finished Apr 25 12:59:10 PM PDT 24
Peak memory 204016 kb
Host smart-2860c8e2-33e0-4370-8a51-600252c7b6bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008252687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1008252687
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.534616985
Short name T1403
Test name
Test status
Simulation time 54994705 ps
CPU time 0.83 seconds
Started Apr 25 12:59:05 PM PDT 24
Finished Apr 25 12:59:07 PM PDT 24
Peak memory 204084 kb
Host smart-773858c1-72db-4b94-95e8-53a522ad123c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534616985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_out
standing.534616985
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1264597605
Short name T1415
Test name
Test status
Simulation time 58430103 ps
CPU time 1.57 seconds
Started Apr 25 12:59:06 PM PDT 24
Finished Apr 25 12:59:09 PM PDT 24
Peak memory 204260 kb
Host smart-2664c1f1-ccbf-4cb0-8521-1034bb5c868c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264597605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1264597605
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3327510467
Short name T123
Test name
Test status
Simulation time 72563907 ps
CPU time 1.57 seconds
Started Apr 25 12:59:13 PM PDT 24
Finished Apr 25 12:59:17 PM PDT 24
Peak memory 204256 kb
Host smart-b72a74dc-5d29-4d1b-8954-1756b418a8e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327510467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.3327510467
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3729932008
Short name T1379
Test name
Test status
Simulation time 64597771 ps
CPU time 0.99 seconds
Started Apr 25 12:59:02 PM PDT 24
Finished Apr 25 12:59:05 PM PDT 24
Peak memory 204020 kb
Host smart-2736adde-ef00-487a-a9df-4615ae5ef8f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729932008 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3729932008
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1320101746
Short name T145
Test name
Test status
Simulation time 54320847 ps
CPU time 0.68 seconds
Started Apr 25 12:59:03 PM PDT 24
Finished Apr 25 12:59:05 PM PDT 24
Peak memory 204048 kb
Host smart-9a1fd416-2da7-444d-b436-c92b22da37de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320101746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1320101746
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.2226280021
Short name T1447
Test name
Test status
Simulation time 26871637 ps
CPU time 0.68 seconds
Started Apr 25 12:59:06 PM PDT 24
Finished Apr 25 12:59:09 PM PDT 24
Peak memory 203988 kb
Host smart-722d7a06-e83a-4092-81e3-93e486f0256f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226280021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2226280021
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3434521140
Short name T1389
Test name
Test status
Simulation time 143240843 ps
CPU time 1.98 seconds
Started Apr 25 12:59:07 PM PDT 24
Finished Apr 25 12:59:11 PM PDT 24
Peak memory 204072 kb
Host smart-8b445df3-296c-4aca-a3df-82e90b946a57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434521140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3434521140
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_alert_test.3909802090
Short name T405
Test name
Test status
Simulation time 57804058 ps
CPU time 0.62 seconds
Started Apr 25 03:04:20 PM PDT 24
Finished Apr 25 03:04:21 PM PDT 24
Peak memory 203920 kb
Host smart-a7a8dd51-f9b9-47b8-9bcb-8f4485fe8f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909802090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.3909802090
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.1088003948
Short name T487
Test name
Test status
Simulation time 111860839 ps
CPU time 1.64 seconds
Started Apr 25 03:04:01 PM PDT 24
Finished Apr 25 03:04:03 PM PDT 24
Peak memory 220612 kb
Host smart-4dd09976-84a9-4995-a17a-b46c47ab72de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088003948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.1088003948
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2633419650
Short name T483
Test name
Test status
Simulation time 1147486062 ps
CPU time 12.09 seconds
Started Apr 25 03:03:53 PM PDT 24
Finished Apr 25 03:04:06 PM PDT 24
Peak memory 244480 kb
Host smart-b51c3d50-0bc9-4658-ad9e-26105274fdeb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633419650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.2633419650
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.851222138
Short name T1137
Test name
Test status
Simulation time 1504953191 ps
CPU time 42.52 seconds
Started Apr 25 03:03:53 PM PDT 24
Finished Apr 25 03:04:36 PM PDT 24
Peak memory 466488 kb
Host smart-014bbe74-6625-4fbf-b3a0-c8adea9c1b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851222138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.851222138
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.2586115676
Short name T1141
Test name
Test status
Simulation time 1903564946 ps
CPU time 149.89 seconds
Started Apr 25 03:03:57 PM PDT 24
Finished Apr 25 03:06:28 PM PDT 24
Peak memory 674516 kb
Host smart-924d7f15-02f7-4ab0-8c7a-6e6445c66c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586115676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.2586115676
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.2309278068
Short name T1339
Test name
Test status
Simulation time 251387779 ps
CPU time 0.92 seconds
Started Apr 25 03:03:53 PM PDT 24
Finished Apr 25 03:03:55 PM PDT 24
Peak memory 203920 kb
Host smart-8b1aef14-e032-471e-8693-640de5cfd64f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309278068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.2309278068
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.1215753628
Short name T393
Test name
Test status
Simulation time 154451548 ps
CPU time 4.05 seconds
Started Apr 25 03:03:58 PM PDT 24
Finished Apr 25 03:04:03 PM PDT 24
Peak memory 224048 kb
Host smart-6bc31098-8395-482b-ba29-69f3f42ceefb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215753628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
1215753628
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.1207421013
Short name T1046
Test name
Test status
Simulation time 16486793695 ps
CPU time 121.22 seconds
Started Apr 25 03:03:43 PM PDT 24
Finished Apr 25 03:05:45 PM PDT 24
Peak memory 1188084 kb
Host smart-90e8279b-9d7d-410f-8d74-e50402e224e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207421013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1207421013
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.523601134
Short name T480
Test name
Test status
Simulation time 383446611 ps
CPU time 15.72 seconds
Started Apr 25 03:04:20 PM PDT 24
Finished Apr 25 03:04:36 PM PDT 24
Peak memory 204208 kb
Host smart-752cc0ce-f632-47a3-9da4-269be170fe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523601134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.523601134
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.1910896864
Short name T775
Test name
Test status
Simulation time 1659644953 ps
CPU time 32.63 seconds
Started Apr 25 03:04:11 PM PDT 24
Finished Apr 25 03:04:44 PM PDT 24
Peak memory 355984 kb
Host smart-fc69bf04-89bb-4355-ab91-4dc16fabecb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910896864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.1910896864
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.921040995
Short name T173
Test name
Test status
Simulation time 204289870 ps
CPU time 0.74 seconds
Started Apr 25 03:03:42 PM PDT 24
Finished Apr 25 03:03:44 PM PDT 24
Peak memory 203856 kb
Host smart-788c40d0-7b84-4203-94d6-359499a02612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921040995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.921040995
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.2475153495
Short name T868
Test name
Test status
Simulation time 539368314 ps
CPU time 8.48 seconds
Started Apr 25 03:03:54 PM PDT 24
Finished Apr 25 03:04:03 PM PDT 24
Peak memory 226288 kb
Host smart-9a86081e-9c95-4225-bc5e-13f5797bd6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475153495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.2475153495
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.982140065
Short name T277
Test name
Test status
Simulation time 2507615417 ps
CPU time 21.66 seconds
Started Apr 25 03:03:42 PM PDT 24
Finished Apr 25 03:04:05 PM PDT 24
Peak memory 277456 kb
Host smart-11de1afb-29d8-4003-8059-9e53aa601141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982140065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.982140065
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.175370336
Short name T1134
Test name
Test status
Simulation time 8277680975 ps
CPU time 663.58 seconds
Started Apr 25 03:03:58 PM PDT 24
Finished Apr 25 03:15:03 PM PDT 24
Peak memory 1380524 kb
Host smart-b8060cea-28d2-4334-b23e-c4a2934b396a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175370336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.175370336
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.2971302427
Short name T899
Test name
Test status
Simulation time 985806915 ps
CPU time 22.07 seconds
Started Apr 25 03:03:54 PM PDT 24
Finished Apr 25 03:04:17 PM PDT 24
Peak memory 212292 kb
Host smart-bea26619-1879-4319-bd0c-f1cfc0fe7fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971302427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.2971302427
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.1696235128
Short name T768
Test name
Test status
Simulation time 5275137312 ps
CPU time 5.87 seconds
Started Apr 25 03:04:16 PM PDT 24
Finished Apr 25 03:04:23 PM PDT 24
Peak memory 215644 kb
Host smart-487ffd36-e605-4227-93c3-b1e2a0446585
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696235128 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1696235128
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.3166969644
Short name T82
Test name
Test status
Simulation time 10080412239 ps
CPU time 64.12 seconds
Started Apr 25 03:04:10 PM PDT 24
Finished Apr 25 03:05:15 PM PDT 24
Peak memory 526720 kb
Host smart-2a4344e8-121b-460c-8168-361c3b89b8cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166969644 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.3166969644
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.3633539579
Short name T837
Test name
Test status
Simulation time 10088977849 ps
CPU time 28.86 seconds
Started Apr 25 03:04:13 PM PDT 24
Finished Apr 25 03:04:43 PM PDT 24
Peak memory 382124 kb
Host smart-05d74600-bbbb-4505-a2cf-377e4aeef256
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633539579 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.3633539579
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.3938062084
Short name T16
Test name
Test status
Simulation time 2649606064 ps
CPU time 10.86 seconds
Started Apr 25 03:03:57 PM PDT 24
Finished Apr 25 03:04:09 PM PDT 24
Peak memory 204424 kb
Host smart-348c11a7-d06b-4097-979d-d4122d4cd8b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938062084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.3938062084
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.3451645579
Short name T465
Test name
Test status
Simulation time 487436544 ps
CPU time 2.82 seconds
Started Apr 25 03:04:14 PM PDT 24
Finished Apr 25 03:04:17 PM PDT 24
Peak memory 204164 kb
Host smart-e1777792-0523-4e0a-acfb-e77b0c6ab2f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451645579 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.3451645579
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.3758985906
Short name T730
Test name
Test status
Simulation time 2688299426 ps
CPU time 6.84 seconds
Started Apr 25 03:03:58 PM PDT 24
Finished Apr 25 03:04:06 PM PDT 24
Peak memory 220408 kb
Host smart-af379956-2198-4d22-89ba-7b2284d78497
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758985906 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.3758985906
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.4217163993
Short name T291
Test name
Test status
Simulation time 18483038986 ps
CPU time 82.49 seconds
Started Apr 25 03:03:58 PM PDT 24
Finished Apr 25 03:05:21 PM PDT 24
Peak memory 1104668 kb
Host smart-527603d4-5b37-4275-a291-f3a8b7099807
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217163993 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.4217163993
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.1615788287
Short name T467
Test name
Test status
Simulation time 1760773142 ps
CPU time 34.73 seconds
Started Apr 25 03:04:01 PM PDT 24
Finished Apr 25 03:04:36 PM PDT 24
Peak memory 204176 kb
Host smart-8ab00f12-4183-4b39-92a4-fb36bbd7911d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615788287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.1615788287
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.2458003680
Short name T703
Test name
Test status
Simulation time 7512848411 ps
CPU time 30.4 seconds
Started Apr 25 03:03:58 PM PDT 24
Finished Apr 25 03:04:29 PM PDT 24
Peak memory 236584 kb
Host smart-4a76765a-1bb6-4e76-8873-c9015e6f3393
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458003680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.2458003680
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.2837970998
Short name T859
Test name
Test status
Simulation time 29800178370 ps
CPU time 6.77 seconds
Started Apr 25 03:03:59 PM PDT 24
Finished Apr 25 03:04:06 PM PDT 24
Peak memory 205292 kb
Host smart-d8872419-bf9f-49f1-a7fa-7626842b86d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837970998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.2837970998
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.1321054977
Short name T770
Test name
Test status
Simulation time 14318029001 ps
CPU time 304.37 seconds
Started Apr 25 03:04:00 PM PDT 24
Finished Apr 25 03:09:05 PM PDT 24
Peak memory 2230976 kb
Host smart-cc3c3f99-8db4-4cfa-901a-35a3ec21c0d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321054977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.1321054977
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.3232713357
Short name T903
Test name
Test status
Simulation time 1084296030 ps
CPU time 6.16 seconds
Started Apr 25 03:03:58 PM PDT 24
Finished Apr 25 03:04:04 PM PDT 24
Peak memory 212372 kb
Host smart-dc6673a7-a9f2-4373-bcf0-7c5a83442d0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232713357 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.3232713357
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.4281672813
Short name T681
Test name
Test status
Simulation time 34801121 ps
CPU time 0.6 seconds
Started Apr 25 03:04:54 PM PDT 24
Finished Apr 25 03:04:56 PM PDT 24
Peak memory 203908 kb
Host smart-5bf07e12-3e3b-47e8-bf48-795857ecc217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281672813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.4281672813
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.3495474190
Short name T626
Test name
Test status
Simulation time 323762908 ps
CPU time 1.25 seconds
Started Apr 25 03:04:30 PM PDT 24
Finished Apr 25 03:04:32 PM PDT 24
Peak memory 212416 kb
Host smart-95c1b8a9-b7b6-40da-80d8-f0a3456a657d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495474190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3495474190
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.894294135
Short name T755
Test name
Test status
Simulation time 1391710125 ps
CPU time 18.74 seconds
Started Apr 25 03:04:31 PM PDT 24
Finished Apr 25 03:04:51 PM PDT 24
Peak memory 262240 kb
Host smart-7c7da1cf-932c-4b10-92df-a6e3792c8587
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894294135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.894294135
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.531797465
Short name T79
Test name
Test status
Simulation time 9386682073 ps
CPU time 58.57 seconds
Started Apr 25 03:04:31 PM PDT 24
Finished Apr 25 03:05:30 PM PDT 24
Peak memory 634836 kb
Host smart-20335078-44f8-48db-9130-872a317ca8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531797465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.531797465
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.1701721707
Short name T820
Test name
Test status
Simulation time 1438111634 ps
CPU time 93.5 seconds
Started Apr 25 03:04:18 PM PDT 24
Finished Apr 25 03:05:52 PM PDT 24
Peak memory 488920 kb
Host smart-4ba2e3ec-1bdd-47ee-873c-459dbdc0a55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701721707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.1701721707
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.1400863770
Short name T1270
Test name
Test status
Simulation time 1353325579 ps
CPU time 9.33 seconds
Started Apr 25 03:04:27 PM PDT 24
Finished Apr 25 03:04:37 PM PDT 24
Peak memory 233312 kb
Host smart-96a1e4e3-8f95-49b2-b29c-5e8197a13a4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400863770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
1400863770
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.2398731819
Short name T555
Test name
Test status
Simulation time 17943884557 ps
CPU time 155.44 seconds
Started Apr 25 03:04:27 PM PDT 24
Finished Apr 25 03:07:03 PM PDT 24
Peak memory 1321960 kb
Host smart-8cccb6cc-58ca-42ac-87bb-be2eb265c557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398731819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.2398731819
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.4204797998
Short name T459
Test name
Test status
Simulation time 2099316473 ps
CPU time 6.41 seconds
Started Apr 25 03:04:47 PM PDT 24
Finished Apr 25 03:04:54 PM PDT 24
Peak memory 204196 kb
Host smart-d9a77ea2-d34a-457c-86ae-2755a4546e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204797998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.4204797998
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.919864101
Short name T639
Test name
Test status
Simulation time 3727503781 ps
CPU time 26.03 seconds
Started Apr 25 03:04:46 PM PDT 24
Finished Apr 25 03:05:12 PM PDT 24
Peak memory 317888 kb
Host smart-2a57aeb0-0fdc-4c84-8eb5-dda886702eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919864101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.919864101
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.4144861708
Short name T738
Test name
Test status
Simulation time 22463273 ps
CPU time 0.67 seconds
Started Apr 25 03:04:19 PM PDT 24
Finished Apr 25 03:04:20 PM PDT 24
Peak memory 203808 kb
Host smart-9fe71a52-f812-4e8f-bb9d-0d0f04edfc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144861708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.4144861708
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.2867401991
Short name T764
Test name
Test status
Simulation time 2829839535 ps
CPU time 29.07 seconds
Started Apr 25 03:04:23 PM PDT 24
Finished Apr 25 03:04:52 PM PDT 24
Peak memory 245940 kb
Host smart-c4a7cf8d-0c87-49b7-93c8-ca3ce4ebc862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867401991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.2867401991
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.4119844233
Short name T1256
Test name
Test status
Simulation time 5681232910 ps
CPU time 16.48 seconds
Started Apr 25 03:04:19 PM PDT 24
Finished Apr 25 03:04:36 PM PDT 24
Peak memory 313028 kb
Host smart-5f157479-920d-43db-bb85-2f29b5b59257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119844233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.4119844233
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.3825975272
Short name T274
Test name
Test status
Simulation time 1866714112 ps
CPU time 24.68 seconds
Started Apr 25 03:04:25 PM PDT 24
Finished Apr 25 03:04:50 PM PDT 24
Peak memory 212364 kb
Host smart-9f9c0f41-c69a-4c68-a2af-c9222e52647d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825975272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.3825975272
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.3287948504
Short name T112
Test name
Test status
Simulation time 38144971 ps
CPU time 0.86 seconds
Started Apr 25 03:04:48 PM PDT 24
Finished Apr 25 03:04:50 PM PDT 24
Peak memory 221484 kb
Host smart-db6663cb-0ebb-4d87-98ee-bc65d4a7d1b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287948504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.3287948504
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.3034430616
Short name T314
Test name
Test status
Simulation time 3793175388 ps
CPU time 3.92 seconds
Started Apr 25 03:04:42 PM PDT 24
Finished Apr 25 03:04:47 PM PDT 24
Peak memory 204196 kb
Host smart-aab3910c-af70-4c7f-a91e-476ceeb16a0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034430616 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.3034430616
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.187960987
Short name T663
Test name
Test status
Simulation time 10700800761 ps
CPU time 13.87 seconds
Started Apr 25 03:04:42 PM PDT 24
Finished Apr 25 03:04:56 PM PDT 24
Peak memory 260308 kb
Host smart-6f3f8805-1293-40fc-9ba8-43ce9cc3e2b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187960987 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_acq.187960987
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.3702088064
Short name T513
Test name
Test status
Simulation time 10167292022 ps
CPU time 15.44 seconds
Started Apr 25 03:04:42 PM PDT 24
Finished Apr 25 03:04:59 PM PDT 24
Peak memory 301996 kb
Host smart-d1ee02e4-d359-4af2-b821-1f2bc07098ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702088064 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.3702088064
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.3618750348
Short name T856
Test name
Test status
Simulation time 444128449 ps
CPU time 2.62 seconds
Started Apr 25 03:04:41 PM PDT 24
Finished Apr 25 03:04:45 PM PDT 24
Peak memory 204196 kb
Host smart-43fcafe5-c744-4607-a805-dbd4d9eb0331
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618750348 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.3618750348
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.3404302437
Short name T329
Test name
Test status
Simulation time 3157075527 ps
CPU time 4.64 seconds
Started Apr 25 03:04:33 PM PDT 24
Finished Apr 25 03:04:39 PM PDT 24
Peak memory 204888 kb
Host smart-551ee34c-4b3f-46e3-8a03-3158793ff237
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404302437 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.3404302437
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.2349298771
Short name T848
Test name
Test status
Simulation time 22847856367 ps
CPU time 185.27 seconds
Started Apr 25 03:04:42 PM PDT 24
Finished Apr 25 03:07:48 PM PDT 24
Peak memory 2054832 kb
Host smart-0265d7d3-f38b-4cf5-aaa0-35f08db1e46d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349298771 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.2349298771
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1418248874
Short name T474
Test name
Test status
Simulation time 3571254460 ps
CPU time 12.56 seconds
Started Apr 25 03:04:34 PM PDT 24
Finished Apr 25 03:04:47 PM PDT 24
Peak memory 204296 kb
Host smart-541a051e-1fdf-467e-b182-35ed5f53e9f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418248874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1418248874
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.1002210365
Short name T1003
Test name
Test status
Simulation time 3975352808 ps
CPU time 37.12 seconds
Started Apr 25 03:04:34 PM PDT 24
Finished Apr 25 03:05:11 PM PDT 24
Peak memory 227356 kb
Host smart-cea181d7-3e40-4e0a-950e-c369553e8bfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002210365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.1002210365
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.1728952118
Short name T1290
Test name
Test status
Simulation time 36008984440 ps
CPU time 42.24 seconds
Started Apr 25 03:04:33 PM PDT 24
Finished Apr 25 03:05:16 PM PDT 24
Peak memory 906096 kb
Host smart-fc1c3274-edd2-40d8-b100-1d5e228189c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728952118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.1728952118
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.2337254213
Short name T637
Test name
Test status
Simulation time 36017565433 ps
CPU time 85.37 seconds
Started Apr 25 03:04:34 PM PDT 24
Finished Apr 25 03:06:00 PM PDT 24
Peak memory 740756 kb
Host smart-ef996c70-543a-4a9e-8336-f94716efc943
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337254213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.2337254213
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.2269131899
Short name T390
Test name
Test status
Simulation time 2531990200 ps
CPU time 6.4 seconds
Started Apr 25 03:04:41 PM PDT 24
Finished Apr 25 03:04:48 PM PDT 24
Peak memory 204160 kb
Host smart-07d6100d-a09a-4ead-93c7-6f5b3c4f80ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269131899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.2269131899
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.4277133757
Short name T1103
Test name
Test status
Simulation time 96761252 ps
CPU time 0.64 seconds
Started Apr 25 03:07:45 PM PDT 24
Finished Apr 25 03:07:47 PM PDT 24
Peak memory 203896 kb
Host smart-9cded886-51f7-4cbd-aa7d-7e0ae62c1dfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277133757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.4277133757
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.1751574775
Short name T250
Test name
Test status
Simulation time 78876901 ps
CPU time 1.4 seconds
Started Apr 25 03:07:34 PM PDT 24
Finished Apr 25 03:07:37 PM PDT 24
Peak memory 212508 kb
Host smart-75c92168-9ce3-4d9c-a4fd-f8490d413eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751574775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.1751574775
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.4235079794
Short name T551
Test name
Test status
Simulation time 698577623 ps
CPU time 4.43 seconds
Started Apr 25 03:07:31 PM PDT 24
Finished Apr 25 03:07:36 PM PDT 24
Peak memory 239268 kb
Host smart-eeb9518e-31c0-4532-959e-999cbea43ec0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235079794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.4235079794
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.1827113376
Short name T78
Test name
Test status
Simulation time 7330214689 ps
CPU time 54.96 seconds
Started Apr 25 03:07:32 PM PDT 24
Finished Apr 25 03:08:29 PM PDT 24
Peak memory 537552 kb
Host smart-d145cedb-5f37-4709-8034-bc40889d3494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827113376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.1827113376
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.1370735991
Short name T668
Test name
Test status
Simulation time 4533462356 ps
CPU time 83.54 seconds
Started Apr 25 03:07:32 PM PDT 24
Finished Apr 25 03:08:56 PM PDT 24
Peak memory 716756 kb
Host smart-d08c035e-a41f-471a-bee9-8d95d0f02004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370735991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1370735991
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.1951246369
Short name T759
Test name
Test status
Simulation time 553148817 ps
CPU time 0.95 seconds
Started Apr 25 03:07:33 PM PDT 24
Finished Apr 25 03:07:35 PM PDT 24
Peak memory 203956 kb
Host smart-8c79f7f9-a3a0-44dc-963b-183be8ec46f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951246369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.1951246369
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1275761030
Short name T1209
Test name
Test status
Simulation time 130829100 ps
CPU time 7.96 seconds
Started Apr 25 03:07:54 PM PDT 24
Finished Apr 25 03:08:03 PM PDT 24
Peak memory 225856 kb
Host smart-7a76c0c3-a466-458c-bd30-d340d11e8100
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275761030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1275761030
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.1839005007
Short name T980
Test name
Test status
Simulation time 10899236505 ps
CPU time 60.54 seconds
Started Apr 25 03:07:30 PM PDT 24
Finished Apr 25 03:08:31 PM PDT 24
Peak memory 856684 kb
Host smart-315a92eb-1305-4bef-bd19-fecdf739c615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839005007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.1839005007
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.265567158
Short name T1102
Test name
Test status
Simulation time 1097555832 ps
CPU time 22.1 seconds
Started Apr 25 03:07:43 PM PDT 24
Finished Apr 25 03:08:07 PM PDT 24
Peak memory 308348 kb
Host smart-b6a3b4de-81bf-46d7-9ba4-3338c337e986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265567158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.265567158
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.1092973950
Short name T496
Test name
Test status
Simulation time 28572225 ps
CPU time 0.68 seconds
Started Apr 25 03:07:33 PM PDT 24
Finished Apr 25 03:07:35 PM PDT 24
Peak memory 203860 kb
Host smart-303f527e-3087-4a32-8ac0-ec8c17f84f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092973950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.1092973950
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.2982947275
Short name T708
Test name
Test status
Simulation time 18668331267 ps
CPU time 95.17 seconds
Started Apr 25 03:07:33 PM PDT 24
Finished Apr 25 03:09:09 PM PDT 24
Peak memory 567412 kb
Host smart-64d60e43-ca88-45f5-96b7-31590f028721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982947275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.2982947275
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.4290090049
Short name T573
Test name
Test status
Simulation time 2899954692 ps
CPU time 21.94 seconds
Started Apr 25 03:07:31 PM PDT 24
Finished Apr 25 03:07:54 PM PDT 24
Peak memory 333796 kb
Host smart-fe32adc2-8ab3-4501-930d-3e0bd649da99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290090049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.4290090049
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.1147881231
Short name T938
Test name
Test status
Simulation time 36226859493 ps
CPU time 531.67 seconds
Started Apr 25 03:07:33 PM PDT 24
Finished Apr 25 03:16:26 PM PDT 24
Peak memory 1121364 kb
Host smart-03d69360-9c74-4d73-a516-f7dea274e5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147881231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.1147881231
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.251037195
Short name T742
Test name
Test status
Simulation time 461033737 ps
CPU time 8.54 seconds
Started Apr 25 03:07:32 PM PDT 24
Finished Apr 25 03:07:42 PM PDT 24
Peak memory 212312 kb
Host smart-f7e6e8e2-2f6a-469b-b8f2-e9e4a63974b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251037195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.251037195
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.573660135
Short name T954
Test name
Test status
Simulation time 657411109 ps
CPU time 3.64 seconds
Started Apr 25 03:07:47 PM PDT 24
Finished Apr 25 03:07:52 PM PDT 24
Peak memory 212372 kb
Host smart-4efc2458-703b-45de-84f3-336d3d3da5bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573660135 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.573660135
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2217306958
Short name T466
Test name
Test status
Simulation time 10494852708 ps
CPU time 6.11 seconds
Started Apr 25 03:07:37 PM PDT 24
Finished Apr 25 03:07:44 PM PDT 24
Peak memory 226620 kb
Host smart-c6b82710-ebf0-4ccd-9f4c-d35e77860fd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217306958 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2217306958
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.166928568
Short name T746
Test name
Test status
Simulation time 10054443994 ps
CPU time 28.04 seconds
Started Apr 25 03:07:38 PM PDT 24
Finished Apr 25 03:08:07 PM PDT 24
Peak memory 320688 kb
Host smart-cf0081e0-1dcb-4c3c-a33d-cca5a386c5c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166928568 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.i2c_target_fifo_reset_tx.166928568
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.820733783
Short name T974
Test name
Test status
Simulation time 2599621065 ps
CPU time 6.12 seconds
Started Apr 25 03:07:39 PM PDT 24
Finished Apr 25 03:07:46 PM PDT 24
Peak memory 212476 kb
Host smart-509342fc-0980-46fb-a64f-aa96ae05e6d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820733783 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_intr_smoke.820733783
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.3464271684
Short name T1050
Test name
Test status
Simulation time 18572929353 ps
CPU time 36.73 seconds
Started Apr 25 03:07:38 PM PDT 24
Finished Apr 25 03:08:16 PM PDT 24
Peak memory 697560 kb
Host smart-d70d1a3c-e4fa-4cb3-a5fe-f1e4686badde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464271684 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.3464271684
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.570236934
Short name T469
Test name
Test status
Simulation time 760175057 ps
CPU time 24.46 seconds
Started Apr 25 03:07:32 PM PDT 24
Finished Apr 25 03:07:58 PM PDT 24
Peak memory 204144 kb
Host smart-39205d43-0621-4a6e-96cd-ac1392f12ade
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570236934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_tar
get_smoke.570236934
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.2124886047
Short name T1349
Test name
Test status
Simulation time 6674711609 ps
CPU time 26.58 seconds
Started Apr 25 03:07:33 PM PDT 24
Finished Apr 25 03:08:01 PM PDT 24
Peak memory 204204 kb
Host smart-fdd70a57-5636-4ce4-9bee-e300b42511da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124886047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.2124886047
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.4044136765
Short name T338
Test name
Test status
Simulation time 10137789073 ps
CPU time 11.47 seconds
Started Apr 25 03:07:31 PM PDT 24
Finished Apr 25 03:07:44 PM PDT 24
Peak memory 204240 kb
Host smart-6444db1d-996b-4eb1-a5ca-3818f013693a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044136765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.4044136765
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.3302738048
Short name T387
Test name
Test status
Simulation time 15252019441 ps
CPU time 2409.79 seconds
Started Apr 25 03:07:32 PM PDT 24
Finished Apr 25 03:47:44 PM PDT 24
Peak memory 3628716 kb
Host smart-44fc51ed-f308-432f-b689-66dc8a0a6965
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302738048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.3302738048
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.3418228141
Short name T597
Test name
Test status
Simulation time 1246448228 ps
CPU time 6.82 seconds
Started Apr 25 03:07:37 PM PDT 24
Finished Apr 25 03:07:45 PM PDT 24
Peak memory 204232 kb
Host smart-57047d1f-171f-4f39-9f0b-9071fbdfb70d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418228141 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.3418228141
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.3147325487
Short name T1146
Test name
Test status
Simulation time 86834583 ps
CPU time 0.62 seconds
Started Apr 25 03:08:04 PM PDT 24
Finished Apr 25 03:08:06 PM PDT 24
Peak memory 203876 kb
Host smart-1cf5f6a5-50cb-4098-b7f6-4dfb00288c90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147325487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.3147325487
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.1073226276
Short name T421
Test name
Test status
Simulation time 63606769 ps
CPU time 1.56 seconds
Started Apr 25 03:07:46 PM PDT 24
Finished Apr 25 03:07:49 PM PDT 24
Peak memory 220668 kb
Host smart-fc8638ad-3ecd-4705-84c0-584449dd708b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073226276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.1073226276
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.1658166626
Short name T1199
Test name
Test status
Simulation time 1032528544 ps
CPU time 5.14 seconds
Started Apr 25 03:07:48 PM PDT 24
Finished Apr 25 03:07:55 PM PDT 24
Peak memory 255100 kb
Host smart-6e1bd039-f17b-4f93-92d5-c15cb2dc15b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658166626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.1658166626
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.3951141645
Short name T1219
Test name
Test status
Simulation time 3151467977 ps
CPU time 57.41 seconds
Started Apr 25 03:07:46 PM PDT 24
Finished Apr 25 03:08:45 PM PDT 24
Peak memory 510192 kb
Host smart-db26c3ab-033f-426b-b63b-4fdfb78841f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951141645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.3951141645
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.3017388198
Short name T473
Test name
Test status
Simulation time 2286342822 ps
CPU time 67.22 seconds
Started Apr 25 03:07:44 PM PDT 24
Finished Apr 25 03:08:53 PM PDT 24
Peak memory 761856 kb
Host smart-c616ad35-b4cd-45ef-9212-a3605d87b1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017388198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.3017388198
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.1274465704
Short name T1169
Test name
Test status
Simulation time 305366231 ps
CPU time 0.87 seconds
Started Apr 25 03:07:44 PM PDT 24
Finished Apr 25 03:07:47 PM PDT 24
Peak memory 203992 kb
Host smart-5086f2b1-2c21-40bb-bba4-99db4e8cb79f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274465704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.1274465704
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.4204168975
Short name T982
Test name
Test status
Simulation time 971009679 ps
CPU time 3.69 seconds
Started Apr 25 03:07:48 PM PDT 24
Finished Apr 25 03:07:52 PM PDT 24
Peak memory 226496 kb
Host smart-e43f40ce-fb04-4cfa-974c-733f248bbd6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204168975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.4204168975
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.1840001762
Short name T156
Test name
Test status
Simulation time 4313687925 ps
CPU time 108.57 seconds
Started Apr 25 03:07:42 PM PDT 24
Finished Apr 25 03:09:32 PM PDT 24
Peak memory 1189444 kb
Host smart-520e3850-850f-4b90-9e28-fbf0459ebdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840001762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.1840001762
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.3390683773
Short name T690
Test name
Test status
Simulation time 5177423971 ps
CPU time 4.18 seconds
Started Apr 25 03:08:05 PM PDT 24
Finished Apr 25 03:08:11 PM PDT 24
Peak memory 204216 kb
Host smart-adb22c18-3941-4b02-b50e-504a86e3f4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390683773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.3390683773
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.4209799651
Short name T669
Test name
Test status
Simulation time 4965053048 ps
CPU time 24.48 seconds
Started Apr 25 03:07:54 PM PDT 24
Finished Apr 25 03:08:20 PM PDT 24
Peak memory 342028 kb
Host smart-1c337508-35f7-4787-86d1-94acf33b7420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209799651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.4209799651
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.2702102808
Short name T1036
Test name
Test status
Simulation time 43394942 ps
CPU time 0.67 seconds
Started Apr 25 03:07:48 PM PDT 24
Finished Apr 25 03:07:50 PM PDT 24
Peak memory 203824 kb
Host smart-dc1e8c3a-483e-42c9-8491-96d80e0a4641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702102808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.2702102808
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.4267921151
Short name T62
Test name
Test status
Simulation time 50936820031 ps
CPU time 525.06 seconds
Started Apr 25 03:07:47 PM PDT 24
Finished Apr 25 03:16:33 PM PDT 24
Peak memory 1084612 kb
Host smart-6ed9c19d-a161-4f53-937d-f5eea531f7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267921151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.4267921151
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.2208997286
Short name T479
Test name
Test status
Simulation time 1230549170 ps
CPU time 20.32 seconds
Started Apr 25 03:07:43 PM PDT 24
Finished Apr 25 03:08:05 PM PDT 24
Peak memory 326984 kb
Host smart-3d7f9c99-0ede-4c36-b2bd-c731d95a330a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208997286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.2208997286
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.890852984
Short name T1030
Test name
Test status
Simulation time 833666921 ps
CPU time 6.64 seconds
Started Apr 25 03:07:49 PM PDT 24
Finished Apr 25 03:07:57 PM PDT 24
Peak memory 215756 kb
Host smart-e02c6902-67fc-477d-a27d-a1b6f39b94d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890852984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.890852984
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.1354553661
Short name T711
Test name
Test status
Simulation time 704847585 ps
CPU time 3.6 seconds
Started Apr 25 03:07:54 PM PDT 24
Finished Apr 25 03:07:58 PM PDT 24
Peak memory 204240 kb
Host smart-6f822b6d-46dd-4b23-ba28-75e9344b455e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354553661 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.1354553661
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.1106671178
Short name T822
Test name
Test status
Simulation time 12698528260 ps
CPU time 3.17 seconds
Started Apr 25 03:07:55 PM PDT 24
Finished Apr 25 03:07:59 PM PDT 24
Peak memory 211428 kb
Host smart-0f58d7d0-8e00-47b3-a30f-14f853b84b71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106671178 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.1106671178
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.4039788042
Short name T1211
Test name
Test status
Simulation time 10088120648 ps
CPU time 78.21 seconds
Started Apr 25 03:07:56 PM PDT 24
Finished Apr 25 03:09:15 PM PDT 24
Peak memory 539708 kb
Host smart-d4251113-3315-4d30-aaa3-9ad4b42b2464
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039788042 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.4039788042
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.190883017
Short name T658
Test name
Test status
Simulation time 644384866 ps
CPU time 2.27 seconds
Started Apr 25 03:07:54 PM PDT 24
Finished Apr 25 03:07:58 PM PDT 24
Peak memory 204200 kb
Host smart-08a95d22-37e1-4ec9-bcc1-c44797abfc06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190883017 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_hrst.190883017
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.3802781152
Short name T1148
Test name
Test status
Simulation time 5092927934 ps
CPU time 3.72 seconds
Started Apr 25 03:07:48 PM PDT 24
Finished Apr 25 03:07:53 PM PDT 24
Peak memory 204168 kb
Host smart-858e1035-97db-4023-bb74-f97aba4e2cba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802781152 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.3802781152
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.3289133308
Short name T1347
Test name
Test status
Simulation time 16327559060 ps
CPU time 105.06 seconds
Started Apr 25 03:07:52 PM PDT 24
Finished Apr 25 03:09:38 PM PDT 24
Peak memory 1934260 kb
Host smart-38c67332-25bd-4c17-9b53-f2c4ad1ceb1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289133308 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.3289133308
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.2741501975
Short name T206
Test name
Test status
Simulation time 4437430831 ps
CPU time 41.29 seconds
Started Apr 25 03:07:48 PM PDT 24
Finished Apr 25 03:08:30 PM PDT 24
Peak memory 204216 kb
Host smart-1733683a-b0b3-4362-9850-d11ed1302bb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741501975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.2741501975
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_all.379578285
Short name T1173
Test name
Test status
Simulation time 43059357385 ps
CPU time 1847.94 seconds
Started Apr 25 03:07:56 PM PDT 24
Finished Apr 25 03:38:45 PM PDT 24
Peak memory 8572264 kb
Host smart-a783c4d7-f545-4cdf-a558-82224cf5ced1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379578285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.i2c_target_stress_all.379578285
Directory /workspace/11.i2c_target_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.1056247107
Short name T1236
Test name
Test status
Simulation time 267891316 ps
CPU time 4.21 seconds
Started Apr 25 03:07:48 PM PDT 24
Finished Apr 25 03:07:54 PM PDT 24
Peak memory 204220 kb
Host smart-f0f3feb1-de4e-45cd-939c-eca42f70afb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056247107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.1056247107
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.902106722
Short name T1276
Test name
Test status
Simulation time 13315912254 ps
CPU time 12.55 seconds
Started Apr 25 03:07:47 PM PDT 24
Finished Apr 25 03:08:01 PM PDT 24
Peak memory 204204 kb
Host smart-6fcb8b64-e8c4-480f-8f8f-3209ce6aed8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902106722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_wr.902106722
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.977046713
Short name T801
Test name
Test status
Simulation time 29878916395 ps
CPU time 153.05 seconds
Started Apr 25 03:07:51 PM PDT 24
Finished Apr 25 03:10:24 PM PDT 24
Peak memory 1510380 kb
Host smart-4cf8f037-a48a-4ef6-b599-3e4b6d375d91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977046713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_t
arget_stretch.977046713
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.677194957
Short name T970
Test name
Test status
Simulation time 2393214983 ps
CPU time 6.43 seconds
Started Apr 25 03:07:49 PM PDT 24
Finished Apr 25 03:07:57 PM PDT 24
Peak memory 204284 kb
Host smart-d6e9570b-ab83-485c-9f90-3d31bd3de2c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677194957 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_timeout.677194957
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.512177897
Short name T317
Test name
Test status
Simulation time 17213826 ps
CPU time 0.63 seconds
Started Apr 25 03:08:14 PM PDT 24
Finished Apr 25 03:08:16 PM PDT 24
Peak memory 203908 kb
Host smart-f05f72d5-aec4-4ba7-bf1e-aaa58bc217f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512177897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.512177897
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.2985078852
Short name T1029
Test name
Test status
Simulation time 339340276 ps
CPU time 1.39 seconds
Started Apr 25 03:08:05 PM PDT 24
Finished Apr 25 03:08:09 PM PDT 24
Peak memory 212496 kb
Host smart-35ccb800-400a-47f0-8071-6043a447d027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985078852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.2985078852
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.951581939
Short name T1224
Test name
Test status
Simulation time 465254922 ps
CPU time 4.6 seconds
Started Apr 25 03:08:02 PM PDT 24
Finished Apr 25 03:08:08 PM PDT 24
Peak memory 236076 kb
Host smart-55e72e1d-3916-44dc-8169-d8e1e4821ff2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951581939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empt
y.951581939
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.724200320
Short name T874
Test name
Test status
Simulation time 2285589280 ps
CPU time 72.41 seconds
Started Apr 25 03:08:07 PM PDT 24
Finished Apr 25 03:09:23 PM PDT 24
Peak memory 661272 kb
Host smart-de7753f0-9c2c-4f44-b00c-82e6191be2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724200320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.724200320
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.2746452510
Short name T585
Test name
Test status
Simulation time 1452559516 ps
CPU time 46.06 seconds
Started Apr 25 03:08:00 PM PDT 24
Finished Apr 25 03:08:47 PM PDT 24
Peak memory 558732 kb
Host smart-04dbbb65-fc25-4e23-958e-ea898203eb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746452510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.2746452510
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.2331776915
Short name T912
Test name
Test status
Simulation time 66788746 ps
CPU time 0.79 seconds
Started Apr 25 03:08:00 PM PDT 24
Finished Apr 25 03:08:02 PM PDT 24
Peak memory 203960 kb
Host smart-d7d45596-76a3-4142-8765-79835c1c28ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331776915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.2331776915
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.3929341189
Short name T407
Test name
Test status
Simulation time 208377141 ps
CPU time 5.45 seconds
Started Apr 25 03:08:06 PM PDT 24
Finished Apr 25 03:08:15 PM PDT 24
Peak memory 204224 kb
Host smart-0acf87d3-0345-441e-9423-7c89b0c5e3e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929341189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.3929341189
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.2695331077
Short name T1012
Test name
Test status
Simulation time 2885205268 ps
CPU time 58.09 seconds
Started Apr 25 03:08:02 PM PDT 24
Finished Apr 25 03:09:02 PM PDT 24
Peak memory 822104 kb
Host smart-d9ab8d9b-10fb-4694-a9f8-762039f7551d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695331077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.2695331077
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.1206695349
Short name T928
Test name
Test status
Simulation time 1631014250 ps
CPU time 80.3 seconds
Started Apr 25 03:08:11 PM PDT 24
Finished Apr 25 03:09:34 PM PDT 24
Peak memory 372756 kb
Host smart-4f741ed3-fda0-4104-966f-11e94d4fd211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206695349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.1206695349
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.3647582258
Short name T534
Test name
Test status
Simulation time 23774665 ps
CPU time 0.66 seconds
Started Apr 25 03:08:08 PM PDT 24
Finished Apr 25 03:08:11 PM PDT 24
Peak memory 203820 kb
Host smart-12225bbe-fd5f-4c42-a89f-4a32d8611b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647582258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.3647582258
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.3517519335
Short name T1129
Test name
Test status
Simulation time 3119101426 ps
CPU time 129.39 seconds
Started Apr 25 03:08:07 PM PDT 24
Finished Apr 25 03:10:20 PM PDT 24
Peak memory 308864 kb
Host smart-8db7c1f2-4d4e-4996-ba49-bd83e5243026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517519335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.3517519335
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.1656699820
Short name T769
Test name
Test status
Simulation time 5801547480 ps
CPU time 22.47 seconds
Started Apr 25 03:08:01 PM PDT 24
Finished Apr 25 03:08:26 PM PDT 24
Peak memory 324188 kb
Host smart-10b115dd-ff92-4fd5-977a-1ef83a343673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656699820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.1656699820
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.1023204734
Short name T1055
Test name
Test status
Simulation time 2751985030 ps
CPU time 57.72 seconds
Started Apr 25 03:08:07 PM PDT 24
Finished Apr 25 03:09:08 PM PDT 24
Peak memory 377444 kb
Host smart-80e55d06-2a0c-43ab-bfe2-21957a7189d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023204734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.1023204734
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.3786831670
Short name T1330
Test name
Test status
Simulation time 4698647511 ps
CPU time 9.91 seconds
Started Apr 25 03:08:07 PM PDT 24
Finished Apr 25 03:08:20 PM PDT 24
Peak memory 220300 kb
Host smart-cc122a63-6afd-43f8-bb9d-73f86f96c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786831670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3786831670
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.2590969603
Short name T882
Test name
Test status
Simulation time 2139198842 ps
CPU time 2.83 seconds
Started Apr 25 03:08:16 PM PDT 24
Finished Apr 25 03:08:20 PM PDT 24
Peak memory 204248 kb
Host smart-a0e053b9-d307-4a6e-b8f9-9d52058a59ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590969603 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.2590969603
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.3399740222
Short name T83
Test name
Test status
Simulation time 10235140573 ps
CPU time 30.77 seconds
Started Apr 25 03:08:13 PM PDT 24
Finished Apr 25 03:08:46 PM PDT 24
Peak memory 321672 kb
Host smart-0c2efcd9-3c5d-42d4-a848-2feaa9abc663
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399740222 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.3399740222
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.1712283065
Short name T357
Test name
Test status
Simulation time 10097255828 ps
CPU time 75.4 seconds
Started Apr 25 03:08:11 PM PDT 24
Finished Apr 25 03:09:29 PM PDT 24
Peak memory 533808 kb
Host smart-ccf5bc41-fd74-4a5f-87f2-57f67a74b8d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712283065 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.1712283065
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.2250662986
Short name T1037
Test name
Test status
Simulation time 1458832409 ps
CPU time 2.23 seconds
Started Apr 25 03:08:12 PM PDT 24
Finished Apr 25 03:08:16 PM PDT 24
Peak memory 204168 kb
Host smart-a5c57b60-216b-4832-97de-e9bd33e36e3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250662986 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.2250662986
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.1606218381
Short name T790
Test name
Test status
Simulation time 4119226327 ps
CPU time 4.04 seconds
Started Apr 25 03:08:08 PM PDT 24
Finished Apr 25 03:08:15 PM PDT 24
Peak memory 204784 kb
Host smart-369423db-1b97-4847-9592-534f5ff93d30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606218381 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.1606218381
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.994635248
Short name T542
Test name
Test status
Simulation time 5043249904 ps
CPU time 19.02 seconds
Started Apr 25 03:08:06 PM PDT 24
Finished Apr 25 03:08:29 PM PDT 24
Peak memory 759460 kb
Host smart-3ee0b6fa-f524-42ed-97c7-57f2c3552b2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994635248 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.994635248
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.3264742090
Short name T1342
Test name
Test status
Simulation time 855816235 ps
CPU time 30.2 seconds
Started Apr 25 03:08:08 PM PDT 24
Finished Apr 25 03:08:41 PM PDT 24
Peak memory 204204 kb
Host smart-5c381f3b-a43a-4309-a9cc-78bb8ec40214
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264742090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.3264742090
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.2659663830
Short name T602
Test name
Test status
Simulation time 1835906312 ps
CPU time 40.64 seconds
Started Apr 25 03:08:08 PM PDT 24
Finished Apr 25 03:08:52 PM PDT 24
Peak memory 204140 kb
Host smart-199d78ac-56d8-40c5-a3a2-a8565570b590
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659663830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.2659663830
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.2431932040
Short name T436
Test name
Test status
Simulation time 55011051099 ps
CPU time 451.27 seconds
Started Apr 25 03:08:05 PM PDT 24
Finished Apr 25 03:15:40 PM PDT 24
Peak memory 4163932 kb
Host smart-538b76ab-9645-4671-a642-98265179e1d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431932040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.2431932040
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.699091713
Short name T875
Test name
Test status
Simulation time 34823980422 ps
CPU time 721.36 seconds
Started Apr 25 03:08:09 PM PDT 24
Finished Apr 25 03:20:13 PM PDT 24
Peak memory 2083612 kb
Host smart-bf7ecc83-7e55-4642-9603-c6dc25664ab0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699091713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_t
arget_stretch.699091713
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.3604158395
Short name T745
Test name
Test status
Simulation time 1168213661 ps
CPU time 6.13 seconds
Started Apr 25 03:08:13 PM PDT 24
Finished Apr 25 03:08:21 PM PDT 24
Peak memory 212436 kb
Host smart-25922733-9cc3-4bd8-a9a3-e92da56667c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604158395 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.3604158395
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_unexp_stop.1306789907
Short name T192
Test name
Test status
Simulation time 1180647736 ps
CPU time 5.9 seconds
Started Apr 25 03:08:14 PM PDT 24
Finished Apr 25 03:08:21 PM PDT 24
Peak memory 218276 kb
Host smart-3bf1df1a-d73b-4326-9451-d685a665c2f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306789907 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.i2c_target_unexp_stop.1306789907
Directory /workspace/12.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/13.i2c_alert_test.4273810530
Short name T935
Test name
Test status
Simulation time 28921885 ps
CPU time 0.6 seconds
Started Apr 25 03:08:34 PM PDT 24
Finished Apr 25 03:08:36 PM PDT 24
Peak memory 203856 kb
Host smart-416bb358-99ad-428e-8b25-d0c73346f981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273810530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.4273810530
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.679109526
Short name T235
Test name
Test status
Simulation time 175941841 ps
CPU time 1.09 seconds
Started Apr 25 03:08:17 PM PDT 24
Finished Apr 25 03:08:19 PM PDT 24
Peak memory 212472 kb
Host smart-d54b0747-1260-4d86-8880-e812b487377d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679109526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.679109526
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.2019136173
Short name T491
Test name
Test status
Simulation time 251385173 ps
CPU time 4.58 seconds
Started Apr 25 03:08:19 PM PDT 24
Finished Apr 25 03:08:25 PM PDT 24
Peak memory 253132 kb
Host smart-479572bf-72c9-4550-9029-bad8337cda94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019136173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.2019136173
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.1955790842
Short name T610
Test name
Test status
Simulation time 8256709157 ps
CPU time 57.54 seconds
Started Apr 25 03:08:21 PM PDT 24
Finished Apr 25 03:09:19 PM PDT 24
Peak memory 460352 kb
Host smart-9d1d8d3c-b2ad-42b2-9154-de3e8b9459a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955790842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1955790842
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.377413317
Short name T892
Test name
Test status
Simulation time 1391397402 ps
CPU time 94.98 seconds
Started Apr 25 03:08:18 PM PDT 24
Finished Apr 25 03:09:55 PM PDT 24
Peak memory 502044 kb
Host smart-820ff025-671e-4a95-a4d6-71ae3330408b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377413317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.377413317
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.3703405261
Short name T1243
Test name
Test status
Simulation time 223478421 ps
CPU time 1 seconds
Started Apr 25 03:08:19 PM PDT 24
Finished Apr 25 03:08:22 PM PDT 24
Peak memory 204096 kb
Host smart-b952cae9-0ff6-4dcc-ac8f-938095d5092a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703405261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.3703405261
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.9926566
Short name T1304
Test name
Test status
Simulation time 114155695 ps
CPU time 2.81 seconds
Started Apr 25 03:08:19 PM PDT 24
Finished Apr 25 03:08:23 PM PDT 24
Peak memory 204176 kb
Host smart-77b67c19-4503-4354-b321-e0a4ce2c46a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9926566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.9926566
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.3549632644
Short name T978
Test name
Test status
Simulation time 15629518954 ps
CPU time 97.53 seconds
Started Apr 25 03:08:19 PM PDT 24
Finished Apr 25 03:09:58 PM PDT 24
Peak memory 1140960 kb
Host smart-4f0a787a-7c3a-4f23-b5e1-a0e4a8dd18ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549632644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.3549632644
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.4275378751
Short name T583
Test name
Test status
Simulation time 964991451 ps
CPU time 4.49 seconds
Started Apr 25 03:08:34 PM PDT 24
Finished Apr 25 03:08:40 PM PDT 24
Peak memory 204152 kb
Host smart-446ce768-043d-4824-b213-2550bb82a711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275378751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.4275378751
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.2864017462
Short name T688
Test name
Test status
Simulation time 10482220330 ps
CPU time 20.53 seconds
Started Apr 25 03:08:31 PM PDT 24
Finished Apr 25 03:08:53 PM PDT 24
Peak memory 314268 kb
Host smart-f7e55e29-1d65-4d13-90bf-468aa6ee57ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864017462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.2864017462
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.893623552
Short name T283
Test name
Test status
Simulation time 86833491 ps
CPU time 0.64 seconds
Started Apr 25 03:08:20 PM PDT 24
Finished Apr 25 03:08:22 PM PDT 24
Peak memory 203732 kb
Host smart-0825038e-3713-4abe-8c3d-e46844d3fcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893623552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.893623552
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.2011869213
Short name T286
Test name
Test status
Simulation time 3244484334 ps
CPU time 29.9 seconds
Started Apr 25 03:08:18 PM PDT 24
Finished Apr 25 03:08:49 PM PDT 24
Peak memory 228632 kb
Host smart-5308e4d9-a6b3-41b6-abd8-6dffdbeea2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011869213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.2011869213
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.2431592117
Short name T462
Test name
Test status
Simulation time 1582252848 ps
CPU time 28.66 seconds
Started Apr 25 03:08:12 PM PDT 24
Finished Apr 25 03:08:43 PM PDT 24
Peak memory 296828 kb
Host smart-80559aad-b253-42b4-8ae0-358d905180d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431592117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.2431592117
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.2614311087
Short name T871
Test name
Test status
Simulation time 2469999531 ps
CPU time 9.91 seconds
Started Apr 25 03:08:19 PM PDT 24
Finished Apr 25 03:08:31 PM PDT 24
Peak memory 220528 kb
Host smart-c3a971e2-1484-40d1-9d8a-bcf627593aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614311087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.2614311087
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.1196344329
Short name T102
Test name
Test status
Simulation time 10379350889 ps
CPU time 6.52 seconds
Started Apr 25 03:08:25 PM PDT 24
Finished Apr 25 03:08:32 PM PDT 24
Peak memory 222244 kb
Host smart-61bac802-6780-4242-b114-47d1d9738fce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196344329 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.1196344329
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.405394564
Short name T260
Test name
Test status
Simulation time 10617001145 ps
CPU time 6.34 seconds
Started Apr 25 03:08:22 PM PDT 24
Finished Apr 25 03:08:31 PM PDT 24
Peak memory 229440 kb
Host smart-5e43c749-8e24-4e8c-929f-1d433b9e6e2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405394564 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_fifo_reset_tx.405394564
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.2041431100
Short name T495
Test name
Test status
Simulation time 242542127 ps
CPU time 1.93 seconds
Started Apr 25 03:08:25 PM PDT 24
Finished Apr 25 03:08:28 PM PDT 24
Peak memory 204208 kb
Host smart-d15e779b-d44a-4ef1-ba51-d7a44fba7420
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041431100 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.2041431100
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.88330174
Short name T567
Test name
Test status
Simulation time 1006623300 ps
CPU time 5.09 seconds
Started Apr 25 03:08:24 PM PDT 24
Finished Apr 25 03:08:30 PM PDT 24
Peak memory 204232 kb
Host smart-cd609156-9bdc-43f5-9bdd-a18f570eac33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88330174 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_intr_smoke.88330174
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.2121391427
Short name T1163
Test name
Test status
Simulation time 19622664046 ps
CPU time 401.96 seconds
Started Apr 25 03:08:23 PM PDT 24
Finished Apr 25 03:15:07 PM PDT 24
Peak memory 3277968 kb
Host smart-1b604dac-a1bb-4498-8ed3-4a3f8bbf82a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121391427 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.2121391427
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.2623539181
Short name T691
Test name
Test status
Simulation time 807115861 ps
CPU time 12.85 seconds
Started Apr 25 03:08:19 PM PDT 24
Finished Apr 25 03:08:33 PM PDT 24
Peak memory 204052 kb
Host smart-0a8aed7d-1163-40e5-be10-bf38e02052ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623539181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.2623539181
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.74069674
Short name T781
Test name
Test status
Simulation time 4284330562 ps
CPU time 46.16 seconds
Started Apr 25 03:08:18 PM PDT 24
Finished Apr 25 03:09:05 PM PDT 24
Peak memory 204240 kb
Host smart-4eb19ea6-a717-4feb-817e-3df95c687281
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74069674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stress_rd.74069674
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.3142452922
Short name T1166
Test name
Test status
Simulation time 46957664184 ps
CPU time 1020.82 seconds
Started Apr 25 03:08:18 PM PDT 24
Finished Apr 25 03:25:21 PM PDT 24
Peak memory 6623088 kb
Host smart-0e584317-0e3f-4a06-8de9-8c8ce6065845
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142452922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.3142452922
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.3268749652
Short name T821
Test name
Test status
Simulation time 17753205725 ps
CPU time 1141.01 seconds
Started Apr 25 03:08:25 PM PDT 24
Finished Apr 25 03:27:27 PM PDT 24
Peak memory 4129392 kb
Host smart-2ff1e900-b618-43f5-ad7c-f6a848152f77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268749652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.3268749652
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.2327841391
Short name T794
Test name
Test status
Simulation time 5267944726 ps
CPU time 6.81 seconds
Started Apr 25 03:08:23 PM PDT 24
Finished Apr 25 03:08:31 PM PDT 24
Peak memory 204284 kb
Host smart-464377f0-4192-4cea-b2a5-4779dc81c8c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327841391 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.2327841391
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.3771397802
Short name T1136
Test name
Test status
Simulation time 24380228 ps
CPU time 0.67 seconds
Started Apr 25 03:08:37 PM PDT 24
Finished Apr 25 03:08:39 PM PDT 24
Peak memory 203920 kb
Host smart-065ec6b6-1025-4d76-abb8-30c91cc072c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771397802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.3771397802
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.976611672
Short name T667
Test name
Test status
Simulation time 89982863 ps
CPU time 1.97 seconds
Started Apr 25 03:08:32 PM PDT 24
Finished Apr 25 03:08:36 PM PDT 24
Peak memory 212480 kb
Host smart-aeafb89e-2268-4398-9ee1-24ea0919902c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976611672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.976611672
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.2094186338
Short name T458
Test name
Test status
Simulation time 350876757 ps
CPU time 6.2 seconds
Started Apr 25 03:08:31 PM PDT 24
Finished Apr 25 03:08:38 PM PDT 24
Peak memory 258668 kb
Host smart-172cea7a-1f20-4bb4-a22a-ad2026d85859
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094186338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.2094186338
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.1705050888
Short name T741
Test name
Test status
Simulation time 10112854496 ps
CPU time 75.58 seconds
Started Apr 25 03:08:30 PM PDT 24
Finished Apr 25 03:09:47 PM PDT 24
Peak memory 808648 kb
Host smart-558cb5c7-11f4-4bb6-a534-8662a425e91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705050888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.1705050888
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.559165370
Short name T1005
Test name
Test status
Simulation time 4723538260 ps
CPU time 77.44 seconds
Started Apr 25 03:08:35 PM PDT 24
Finished Apr 25 03:09:54 PM PDT 24
Peak memory 442884 kb
Host smart-14a72f3d-2e1c-442d-a917-fe03d9bc7245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559165370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.559165370
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.3743141937
Short name T183
Test name
Test status
Simulation time 59815484 ps
CPU time 0.79 seconds
Started Apr 25 03:08:31 PM PDT 24
Finished Apr 25 03:08:33 PM PDT 24
Peak memory 203964 kb
Host smart-350f1f3d-dc33-4353-b4a4-a2a882d70295
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743141937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.3743141937
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.3344623647
Short name T547
Test name
Test status
Simulation time 603274633 ps
CPU time 8.58 seconds
Started Apr 25 03:08:31 PM PDT 24
Finished Apr 25 03:08:42 PM PDT 24
Peak memory 204184 kb
Host smart-3087480f-8e3f-4d9a-ae98-db78e13a143c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344623647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.3344623647
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.312785591
Short name T598
Test name
Test status
Simulation time 3109184846 ps
CPU time 184.92 seconds
Started Apr 25 03:08:35 PM PDT 24
Finished Apr 25 03:11:41 PM PDT 24
Peak memory 837304 kb
Host smart-f41972a7-04c7-4ae4-8de5-f7c07857012e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312785591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.312785591
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.3278099838
Short name T829
Test name
Test status
Simulation time 818202326 ps
CPU time 16.51 seconds
Started Apr 25 03:08:40 PM PDT 24
Finished Apr 25 03:09:00 PM PDT 24
Peak memory 204100 kb
Host smart-abda1476-3ffa-43f7-8221-0b6147a83ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278099838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.3278099838
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.170220411
Short name T557
Test name
Test status
Simulation time 5682005524 ps
CPU time 28.52 seconds
Started Apr 25 03:08:40 PM PDT 24
Finished Apr 25 03:09:11 PM PDT 24
Peak memory 309796 kb
Host smart-555fddbd-c770-4bc9-a0e1-b27f25c48ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170220411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.170220411
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.1816582395
Short name T651
Test name
Test status
Simulation time 14665531 ps
CPU time 0.67 seconds
Started Apr 25 03:08:31 PM PDT 24
Finished Apr 25 03:08:34 PM PDT 24
Peak memory 203808 kb
Host smart-c67c946b-74f0-4774-baed-e3863df5c7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816582395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1816582395
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.506021104
Short name T941
Test name
Test status
Simulation time 6686227328 ps
CPU time 94.57 seconds
Started Apr 25 03:08:33 PM PDT 24
Finished Apr 25 03:10:09 PM PDT 24
Peak memory 245860 kb
Host smart-b8d7d770-0baf-41f0-962c-552b7e849934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506021104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.506021104
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.155596942
Short name T1185
Test name
Test status
Simulation time 1772168626 ps
CPU time 70.84 seconds
Started Apr 25 03:08:35 PM PDT 24
Finished Apr 25 03:09:47 PM PDT 24
Peak memory 378332 kb
Host smart-e7753cc3-f81e-45c0-8074-4a573cfb0b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155596942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.155596942
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.3670808785
Short name T642
Test name
Test status
Simulation time 1240924636 ps
CPU time 13.6 seconds
Started Apr 25 03:08:31 PM PDT 24
Finished Apr 25 03:08:47 PM PDT 24
Peak memory 212356 kb
Host smart-c84754a2-4f53-402b-84a3-d5834c0092ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670808785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.3670808785
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.646248390
Short name T543
Test name
Test status
Simulation time 2639851886 ps
CPU time 3.02 seconds
Started Apr 25 03:08:45 PM PDT 24
Finished Apr 25 03:08:49 PM PDT 24
Peak memory 204268 kb
Host smart-83d934c1-13a0-4574-8578-9507a943949b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646248390 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.646248390
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2785354025
Short name T1118
Test name
Test status
Simulation time 10053997591 ps
CPU time 66.69 seconds
Started Apr 25 03:08:32 PM PDT 24
Finished Apr 25 03:09:40 PM PDT 24
Peak memory 497528 kb
Host smart-f375efc0-1825-466e-b6bd-f0d0c51ae3de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785354025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2785354025
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.2073075804
Short name T1297
Test name
Test status
Simulation time 10046085827 ps
CPU time 85.39 seconds
Started Apr 25 03:08:42 PM PDT 24
Finished Apr 25 03:10:09 PM PDT 24
Peak memory 604120 kb
Host smart-8038c042-6144-4853-bed3-3ed1d458cc69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073075804 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.2073075804
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.355866335
Short name T632
Test name
Test status
Simulation time 779143857 ps
CPU time 2.76 seconds
Started Apr 25 03:08:40 PM PDT 24
Finished Apr 25 03:08:46 PM PDT 24
Peak memory 204196 kb
Host smart-5c3976bb-8523-439a-bb09-eb1c480e739f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355866335 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.i2c_target_hrst.355866335
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.1987861798
Short name T1098
Test name
Test status
Simulation time 4535316086 ps
CPU time 5.73 seconds
Started Apr 25 03:08:32 PM PDT 24
Finished Apr 25 03:08:39 PM PDT 24
Peak memory 216136 kb
Host smart-3313dc2c-5ee8-4fbc-97dc-d1f55621c199
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987861798 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.1987861798
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.3829386632
Short name T420
Test name
Test status
Simulation time 21084501571 ps
CPU time 404.29 seconds
Started Apr 25 03:08:31 PM PDT 24
Finished Apr 25 03:15:18 PM PDT 24
Peak memory 3171140 kb
Host smart-98cbcb03-094b-4fac-841c-10c5ed817fdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829386632 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.3829386632
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.3941318810
Short name T869
Test name
Test status
Simulation time 4449345948 ps
CPU time 18.6 seconds
Started Apr 25 03:08:31 PM PDT 24
Finished Apr 25 03:08:52 PM PDT 24
Peak memory 204132 kb
Host smart-00c0e70c-0dcb-4d1f-a7b0-ceefe87cfa61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941318810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.3941318810
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.1086909508
Short name T430
Test name
Test status
Simulation time 8549551498 ps
CPU time 51.26 seconds
Started Apr 25 03:08:32 PM PDT 24
Finished Apr 25 03:09:25 PM PDT 24
Peak memory 207092 kb
Host smart-d6966407-8cfc-4c82-a7ab-773fb7cc519b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086909508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.1086909508
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.2313474083
Short name T1132
Test name
Test status
Simulation time 40525093997 ps
CPU time 207.41 seconds
Started Apr 25 03:08:33 PM PDT 24
Finished Apr 25 03:12:02 PM PDT 24
Peak memory 2621160 kb
Host smart-d3115ec1-2942-4afd-a04e-195c4a13e951
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313474083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.2313474083
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.3697728182
Short name T650
Test name
Test status
Simulation time 1972654254 ps
CPU time 6.47 seconds
Started Apr 25 03:08:32 PM PDT 24
Finished Apr 25 03:08:41 PM PDT 24
Peak memory 212432 kb
Host smart-a6509f26-1019-4a37-bfbc-be9978bd7146
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697728182 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.3697728182
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.4062039093
Short name T418
Test name
Test status
Simulation time 113879284 ps
CPU time 0.6 seconds
Started Apr 25 03:09:01 PM PDT 24
Finished Apr 25 03:09:03 PM PDT 24
Peak memory 203800 kb
Host smart-dab4c8b8-f26b-4615-9c48-caf977a699d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062039093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.4062039093
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.360884702
Short name T1049
Test name
Test status
Simulation time 99025741 ps
CPU time 1.56 seconds
Started Apr 25 03:08:46 PM PDT 24
Finished Apr 25 03:08:48 PM PDT 24
Peak memory 220696 kb
Host smart-1a9197a5-7b13-4acf-979b-095aa2a69c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360884702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.360884702
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.1170594359
Short name T816
Test name
Test status
Simulation time 277934941 ps
CPU time 8.62 seconds
Started Apr 25 03:08:41 PM PDT 24
Finished Apr 25 03:08:52 PM PDT 24
Peak memory 233120 kb
Host smart-8c91430e-ea7a-451e-a881-2d9c77d7b793
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170594359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.1170594359
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.3282379322
Short name T90
Test name
Test status
Simulation time 1994030871 ps
CPU time 66.52 seconds
Started Apr 25 03:08:44 PM PDT 24
Finished Apr 25 03:09:51 PM PDT 24
Peak memory 688188 kb
Host smart-c4671b51-34bc-4315-897c-7cf4139ef26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282379322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.3282379322
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.2504770011
Short name T517
Test name
Test status
Simulation time 2756782115 ps
CPU time 47.92 seconds
Started Apr 25 03:08:42 PM PDT 24
Finished Apr 25 03:09:32 PM PDT 24
Peak memory 559220 kb
Host smart-279ea848-55f7-438e-a930-1e042ca81af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504770011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.2504770011
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.3335492464
Short name T884
Test name
Test status
Simulation time 124160301 ps
CPU time 0.97 seconds
Started Apr 25 03:08:42 PM PDT 24
Finished Apr 25 03:08:45 PM PDT 24
Peak memory 204004 kb
Host smart-ee519022-3477-49d5-9c23-416b6993c59d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335492464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.3335492464
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3381498581
Short name T1011
Test name
Test status
Simulation time 213640008 ps
CPU time 2.49 seconds
Started Apr 25 03:08:43 PM PDT 24
Finished Apr 25 03:08:47 PM PDT 24
Peak memory 204200 kb
Host smart-a2c63e3e-07be-4c2b-98ee-d2b13cfb73a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381498581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.3381498581
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.2015585825
Short name T1215
Test name
Test status
Simulation time 20849740699 ps
CPU time 131.09 seconds
Started Apr 25 03:08:40 PM PDT 24
Finished Apr 25 03:10:54 PM PDT 24
Peak memory 1318988 kb
Host smart-7018f07e-efc9-4c8a-aea6-5b4b90910695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015585825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.2015585825
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.3764341105
Short name T1032
Test name
Test status
Simulation time 482083154 ps
CPU time 18.64 seconds
Started Apr 25 03:08:58 PM PDT 24
Finished Apr 25 03:09:19 PM PDT 24
Peak memory 204204 kb
Host smart-5efd4884-f300-45b5-afbc-ee36e7662063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764341105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.3764341105
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.3467116509
Short name T771
Test name
Test status
Simulation time 15886043487 ps
CPU time 80.52 seconds
Started Apr 25 03:08:57 PM PDT 24
Finished Apr 25 03:10:19 PM PDT 24
Peak memory 285544 kb
Host smart-558b4a2c-af10-4c34-865a-66cadc0cfbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467116509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.3467116509
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.522841130
Short name T762
Test name
Test status
Simulation time 86026122 ps
CPU time 0.68 seconds
Started Apr 25 03:08:37 PM PDT 24
Finished Apr 25 03:08:39 PM PDT 24
Peak memory 203836 kb
Host smart-de45bfe6-27b5-47f9-80de-46e1379516a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522841130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.522841130
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.4218017930
Short name T716
Test name
Test status
Simulation time 7779182450 ps
CPU time 118.18 seconds
Started Apr 25 03:08:44 PM PDT 24
Finished Apr 25 03:10:43 PM PDT 24
Peak memory 641112 kb
Host smart-e4e50444-d720-4a65-9c96-4c244ae49a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218017930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.4218017930
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.1068686471
Short name T339
Test name
Test status
Simulation time 1082995031 ps
CPU time 52.58 seconds
Started Apr 25 03:08:41 PM PDT 24
Finished Apr 25 03:09:36 PM PDT 24
Peak memory 281612 kb
Host smart-08ec3cb8-86c0-4585-ad2f-7a40a22eab2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068686471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1068686471
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.497750911
Short name T1155
Test name
Test status
Simulation time 11865834421 ps
CPU time 658.92 seconds
Started Apr 25 03:08:42 PM PDT 24
Finished Apr 25 03:19:43 PM PDT 24
Peak memory 613680 kb
Host smart-74c8dbcf-737a-456f-9c96-b49545776d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497750911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.497750911
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.3460269526
Short name T1207
Test name
Test status
Simulation time 374000835 ps
CPU time 7.64 seconds
Started Apr 25 03:08:42 PM PDT 24
Finished Apr 25 03:08:52 PM PDT 24
Peak memory 212356 kb
Host smart-dbdcffc5-470c-4fe3-be93-484c741df242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460269526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3460269526
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.1154180624
Short name T946
Test name
Test status
Simulation time 2352385367 ps
CPU time 2.77 seconds
Started Apr 25 03:08:52 PM PDT 24
Finished Apr 25 03:08:56 PM PDT 24
Peak memory 204160 kb
Host smart-9480e13f-7944-40a4-acd2-dd29a2b9888e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154180624 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.1154180624
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.2897640149
Short name T1151
Test name
Test status
Simulation time 10158640008 ps
CPU time 30 seconds
Started Apr 25 03:08:49 PM PDT 24
Finished Apr 25 03:09:20 PM PDT 24
Peak memory 354448 kb
Host smart-9b8a8233-58b6-4604-a779-28ec4870059b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897640149 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.2897640149
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.4186053789
Short name T1300
Test name
Test status
Simulation time 1599943311 ps
CPU time 1.91 seconds
Started Apr 25 03:08:53 PM PDT 24
Finished Apr 25 03:08:56 PM PDT 24
Peak memory 204052 kb
Host smart-450471c5-6f7d-4333-b902-236fcfac2bda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186053789 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.4186053789
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.3740572834
Short name T470
Test name
Test status
Simulation time 3839781589 ps
CPU time 4.5 seconds
Started Apr 25 03:08:50 PM PDT 24
Finished Apr 25 03:08:55 PM PDT 24
Peak memory 204268 kb
Host smart-1e90d923-1925-4a3e-8f14-ab3982fc79a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740572834 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.3740572834
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.3734676713
Short name T1105
Test name
Test status
Simulation time 18620078597 ps
CPU time 43.01 seconds
Started Apr 25 03:08:52 PM PDT 24
Finished Apr 25 03:09:36 PM PDT 24
Peak memory 733184 kb
Host smart-653d3b66-3e1a-40af-b15f-b6ec35f83daf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734676713 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.3734676713
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.394124221
Short name T523
Test name
Test status
Simulation time 3636776588 ps
CPU time 37.14 seconds
Started Apr 25 03:08:47 PM PDT 24
Finished Apr 25 03:09:25 PM PDT 24
Peak memory 204272 kb
Host smart-709887aa-23d1-4ed7-a704-a15940ed07f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394124221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_tar
get_smoke.394124221
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.3535783740
Short name T630
Test name
Test status
Simulation time 1190939900 ps
CPU time 18.13 seconds
Started Apr 25 03:08:44 PM PDT 24
Finished Apr 25 03:09:03 PM PDT 24
Peak memory 220344 kb
Host smart-acc133f8-cf71-4988-96c8-c06c3a3c6f97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535783740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.3535783740
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.1131702729
Short name T1282
Test name
Test status
Simulation time 22476987643 ps
CPU time 56.94 seconds
Started Apr 25 03:08:43 PM PDT 24
Finished Apr 25 03:09:42 PM PDT 24
Peak memory 706492 kb
Host smart-dee12b09-647d-447a-87ed-0dccc6bd00d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131702729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.1131702729
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.703962844
Short name T259
Test name
Test status
Simulation time 33709873102 ps
CPU time 237.02 seconds
Started Apr 25 03:08:52 PM PDT 24
Finished Apr 25 03:12:50 PM PDT 24
Peak memory 2020516 kb
Host smart-d3fa32e4-6ddf-4293-8369-bbae1efd9860
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703962844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_t
arget_stretch.703962844
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.3661433045
Short name T354
Test name
Test status
Simulation time 1150846374 ps
CPU time 5.83 seconds
Started Apr 25 03:08:49 PM PDT 24
Finished Apr 25 03:08:56 PM PDT 24
Peak memory 219464 kb
Host smart-ad13e897-8839-40f7-8430-35e25fb12b32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661433045 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.3661433045
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_unexp_stop.893026243
Short name T983
Test name
Test status
Simulation time 5084390175 ps
CPU time 5.66 seconds
Started Apr 25 03:08:52 PM PDT 24
Finished Apr 25 03:08:59 PM PDT 24
Peak memory 219672 kb
Host smart-90d3b79a-dffa-4650-82c2-34524b0225f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893026243 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_unexp_stop.893026243
Directory /workspace/15.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/16.i2c_alert_test.3194103077
Short name T1041
Test name
Test status
Simulation time 179209346 ps
CPU time 0.6 seconds
Started Apr 25 03:09:07 PM PDT 24
Finished Apr 25 03:09:09 PM PDT 24
Peak memory 203908 kb
Host smart-0c4ec58f-7610-4cc4-8ef8-b99c4d7a9bca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194103077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.3194103077
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.1575549678
Short name T319
Test name
Test status
Simulation time 68087003 ps
CPU time 1.21 seconds
Started Apr 25 03:08:58 PM PDT 24
Finished Apr 25 03:09:01 PM PDT 24
Peak memory 220680 kb
Host smart-ad18d022-1316-4612-ac43-d4386be25d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575549678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.1575549678
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.1348965415
Short name T767
Test name
Test status
Simulation time 397684355 ps
CPU time 4.34 seconds
Started Apr 25 03:08:57 PM PDT 24
Finished Apr 25 03:09:03 PM PDT 24
Peak memory 237492 kb
Host smart-eb369afd-cc7c-4184-9b27-58a964355418
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348965415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.1348965415
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.1277637948
Short name T46
Test name
Test status
Simulation time 2247380196 ps
CPU time 68.04 seconds
Started Apr 25 03:08:55 PM PDT 24
Finished Apr 25 03:10:04 PM PDT 24
Peak memory 727728 kb
Host smart-dbce5f11-3996-437e-8d2b-5c845f1aa4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277637948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.1277637948
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.4040787620
Short name T788
Test name
Test status
Simulation time 4762530856 ps
CPU time 38.94 seconds
Started Apr 25 03:08:55 PM PDT 24
Finished Apr 25 03:09:35 PM PDT 24
Peak memory 525408 kb
Host smart-8d4b54ba-8d80-4ab3-b5ae-568179466828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040787620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.4040787620
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.3578348589
Short name T1145
Test name
Test status
Simulation time 194781097 ps
CPU time 0.96 seconds
Started Apr 25 03:08:57 PM PDT 24
Finished Apr 25 03:08:58 PM PDT 24
Peak memory 203976 kb
Host smart-2b15ee80-b09c-4213-82c2-c9fc3a0657bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578348589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.3578348589
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.2999203495
Short name T766
Test name
Test status
Simulation time 485607109 ps
CPU time 3.34 seconds
Started Apr 25 03:08:57 PM PDT 24
Finished Apr 25 03:09:03 PM PDT 24
Peak memory 204144 kb
Host smart-16773d39-a3ac-4eed-9723-89e52bbc75b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999203495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.2999203495
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.252046739
Short name T36
Test name
Test status
Simulation time 3658856509 ps
CPU time 97.18 seconds
Started Apr 25 03:08:53 PM PDT 24
Finished Apr 25 03:10:31 PM PDT 24
Peak memory 981660 kb
Host smart-2f1e485e-5a64-408d-ae9d-eaf4659fda5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252046739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.252046739
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.3640337836
Short name T671
Test name
Test status
Simulation time 654509369 ps
CPU time 14.04 seconds
Started Apr 25 03:09:08 PM PDT 24
Finished Apr 25 03:09:23 PM PDT 24
Peak memory 204116 kb
Host smart-681fdb6c-e9d5-460a-8a27-d72513261e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640337836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.3640337836
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.1978579617
Short name T783
Test name
Test status
Simulation time 3111212751 ps
CPU time 30.84 seconds
Started Apr 25 03:09:07 PM PDT 24
Finished Apr 25 03:09:39 PM PDT 24
Peak memory 442592 kb
Host smart-5986743f-b91f-4b63-a899-1518e9ff3342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978579617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.1978579617
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.305478519
Short name T169
Test name
Test status
Simulation time 33993070 ps
CPU time 0.65 seconds
Started Apr 25 03:08:56 PM PDT 24
Finished Apr 25 03:08:58 PM PDT 24
Peak memory 203864 kb
Host smart-8fb9a802-e4c4-49bd-b5c0-510b4a38ed7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305478519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.305478519
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.3119493161
Short name T1321
Test name
Test status
Simulation time 2607816896 ps
CPU time 37.47 seconds
Started Apr 25 03:08:55 PM PDT 24
Finished Apr 25 03:09:33 PM PDT 24
Peak memory 228804 kb
Host smart-f7fb74b3-638a-4834-8165-b7d1ed300acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119493161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.3119493161
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.2222875398
Short name T695
Test name
Test status
Simulation time 1203156229 ps
CPU time 59.92 seconds
Started Apr 25 03:08:55 PM PDT 24
Finished Apr 25 03:09:56 PM PDT 24
Peak memory 303416 kb
Host smart-04af99fe-1254-4896-86ba-ce34135235de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222875398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.2222875398
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.198381065
Short name T290
Test name
Test status
Simulation time 1683748322 ps
CPU time 19.5 seconds
Started Apr 25 03:09:00 PM PDT 24
Finished Apr 25 03:09:21 PM PDT 24
Peak memory 212216 kb
Host smart-40217804-c294-4739-a163-51225623f707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198381065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.198381065
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.438888134
Short name T330
Test name
Test status
Simulation time 632970345 ps
CPU time 3.12 seconds
Started Apr 25 03:09:04 PM PDT 24
Finished Apr 25 03:09:09 PM PDT 24
Peak memory 204212 kb
Host smart-ef19dd01-e81f-4c42-a169-35ddbda1e1a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438888134 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.438888134
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.1844119206
Short name T508
Test name
Test status
Simulation time 10160474084 ps
CPU time 45.87 seconds
Started Apr 25 03:09:03 PM PDT 24
Finished Apr 25 03:09:50 PM PDT 24
Peak memory 405704 kb
Host smart-a95d1e33-c6c8-4197-af7c-42d3726d9455
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844119206 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.1844119206
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.2321872658
Short name T942
Test name
Test status
Simulation time 10149227962 ps
CPU time 6.01 seconds
Started Apr 25 03:09:04 PM PDT 24
Finished Apr 25 03:09:12 PM PDT 24
Peak memory 228792 kb
Host smart-a389d773-1ac4-4107-98a5-60a4b85aa22a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321872658 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.2321872658
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.1835256397
Short name T367
Test name
Test status
Simulation time 969043362 ps
CPU time 5.21 seconds
Started Apr 25 03:08:56 PM PDT 24
Finished Apr 25 03:09:03 PM PDT 24
Peak memory 212416 kb
Host smart-50e10f68-81bd-47a1-982c-ae412a9a1f62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835256397 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.1835256397
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.939624042
Short name T907
Test name
Test status
Simulation time 4228951822 ps
CPU time 5.32 seconds
Started Apr 25 03:08:56 PM PDT 24
Finished Apr 25 03:09:02 PM PDT 24
Peak memory 204284 kb
Host smart-28bbed8a-cdd7-4a7c-aae1-da60d69bfb20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939624042 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.939624042
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.393299072
Short name T736
Test name
Test status
Simulation time 1206274896 ps
CPU time 15.44 seconds
Started Apr 25 03:08:57 PM PDT 24
Finished Apr 25 03:09:15 PM PDT 24
Peak memory 204236 kb
Host smart-ebe2e9a7-38e9-4017-adf1-44b79d8a7c58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393299072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_tar
get_smoke.393299072
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.671044249
Short name T383
Test name
Test status
Simulation time 904394050 ps
CPU time 32.1 seconds
Started Apr 25 03:08:57 PM PDT 24
Finished Apr 25 03:09:31 PM PDT 24
Peak memory 204176 kb
Host smart-7a67c012-000b-44d8-a8de-48030c69ca49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671044249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_rd.671044249
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.3987942050
Short name T1107
Test name
Test status
Simulation time 25089290580 ps
CPU time 32.68 seconds
Started Apr 25 03:09:00 PM PDT 24
Finished Apr 25 03:09:34 PM PDT 24
Peak memory 614788 kb
Host smart-2d132749-5070-49ec-8565-7e92041a77bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987942050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.3987942050
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.1527613371
Short name T533
Test name
Test status
Simulation time 20369899241 ps
CPU time 146.29 seconds
Started Apr 25 03:08:58 PM PDT 24
Finished Apr 25 03:11:26 PM PDT 24
Peak memory 1529016 kb
Host smart-9fbd209c-c894-4559-b5a4-e04f6e9bc014
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527613371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.1527613371
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.1671982568
Short name T237
Test name
Test status
Simulation time 1163306271 ps
CPU time 6.85 seconds
Started Apr 25 03:09:04 PM PDT 24
Finished Apr 25 03:09:12 PM PDT 24
Peak memory 220340 kb
Host smart-5ec7e62f-b94f-4550-ba6c-729467cd4469
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671982568 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.1671982568
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.1960747839
Short name T1311
Test name
Test status
Simulation time 307092899 ps
CPU time 1.3 seconds
Started Apr 25 03:09:08 PM PDT 24
Finished Apr 25 03:09:10 PM PDT 24
Peak memory 212504 kb
Host smart-cfc011c1-5c45-4061-b747-5c19532a7b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960747839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.1960747839
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.1185783359
Short name T362
Test name
Test status
Simulation time 281463374 ps
CPU time 5.77 seconds
Started Apr 25 03:09:06 PM PDT 24
Finished Apr 25 03:09:14 PM PDT 24
Peak memory 262420 kb
Host smart-89146444-f154-4182-8b2e-56be28e29eb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185783359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.1185783359
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.2546750375
Short name T1057
Test name
Test status
Simulation time 8397403012 ps
CPU time 135.09 seconds
Started Apr 25 03:09:08 PM PDT 24
Finished Apr 25 03:11:25 PM PDT 24
Peak memory 621336 kb
Host smart-d9fb3996-198e-43c5-9e40-8da3eeb1670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546750375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.2546750375
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.3248202781
Short name T507
Test name
Test status
Simulation time 3024646600 ps
CPU time 89.61 seconds
Started Apr 25 03:09:06 PM PDT 24
Finished Apr 25 03:10:37 PM PDT 24
Peak memory 490636 kb
Host smart-335cc3f4-e3e9-45ec-88df-1ea7da03e50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248202781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.3248202781
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.1623092531
Short name T595
Test name
Test status
Simulation time 107296874 ps
CPU time 0.96 seconds
Started Apr 25 03:09:07 PM PDT 24
Finished Apr 25 03:09:09 PM PDT 24
Peak memory 204160 kb
Host smart-debe4a0e-7ef7-4e9b-88a4-adfda7cc8568
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623092531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.1623092531
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.3688338137
Short name T1201
Test name
Test status
Simulation time 316696729 ps
CPU time 4.26 seconds
Started Apr 25 03:09:05 PM PDT 24
Finished Apr 25 03:09:11 PM PDT 24
Peak memory 229876 kb
Host smart-e79f4063-7b84-4949-b3fb-0af98ef47950
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688338137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.3688338137
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.1015641505
Short name T962
Test name
Test status
Simulation time 12915294006 ps
CPU time 157.56 seconds
Started Apr 25 03:09:07 PM PDT 24
Finished Apr 25 03:11:46 PM PDT 24
Peak memory 1330940 kb
Host smart-c192ce73-8c4a-4372-9fb2-ca2583188ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015641505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.1015641505
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1136429998
Short name T1184
Test name
Test status
Simulation time 333970869 ps
CPU time 5.59 seconds
Started Apr 25 03:09:16 PM PDT 24
Finished Apr 25 03:09:23 PM PDT 24
Peak memory 204160 kb
Host smart-30826f3d-b1a4-41e0-b2ec-0bd07c80357e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136429998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1136429998
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.3814189350
Short name T1015
Test name
Test status
Simulation time 1247555980 ps
CPU time 22.09 seconds
Started Apr 25 03:09:15 PM PDT 24
Finished Apr 25 03:09:38 PM PDT 24
Peak memory 326232 kb
Host smart-effc92b8-ee4a-4ae0-8734-836505a1898a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814189350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.3814189350
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.1029728700
Short name T726
Test name
Test status
Simulation time 19324940 ps
CPU time 0.66 seconds
Started Apr 25 03:09:09 PM PDT 24
Finished Apr 25 03:09:11 PM PDT 24
Peak memory 203856 kb
Host smart-649920cf-992e-4204-8840-4fe4d2084211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029728700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1029728700
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.1893317455
Short name T406
Test name
Test status
Simulation time 537082201 ps
CPU time 12.78 seconds
Started Apr 25 03:09:09 PM PDT 24
Finished Apr 25 03:09:23 PM PDT 24
Peak memory 255460 kb
Host smart-b218226a-67e5-4e6f-8327-3b8da80a3c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893317455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.1893317455
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.3913651258
Short name T258
Test name
Test status
Simulation time 1978768680 ps
CPU time 21.06 seconds
Started Apr 25 03:09:06 PM PDT 24
Finished Apr 25 03:09:29 PM PDT 24
Peak memory 341948 kb
Host smart-cbffcefc-b2dd-4af6-a86b-0cb3078d74ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913651258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3913651258
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.1266851111
Short name T531
Test name
Test status
Simulation time 32979329369 ps
CPU time 2859.13 seconds
Started Apr 25 03:09:06 PM PDT 24
Finished Apr 25 03:56:47 PM PDT 24
Peak memory 3202744 kb
Host smart-5ee6715b-3e1e-48c7-8961-96534ace6031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266851111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.1266851111
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.1415655359
Short name T1127
Test name
Test status
Simulation time 814002467 ps
CPU time 13.93 seconds
Started Apr 25 03:09:07 PM PDT 24
Finished Apr 25 03:09:22 PM PDT 24
Peak memory 216024 kb
Host smart-c998eb2f-d252-4aa3-b884-0d6daf7e9f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415655359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.1415655359
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.2877750912
Short name T224
Test name
Test status
Simulation time 883984047 ps
CPU time 3.73 seconds
Started Apr 25 03:09:13 PM PDT 24
Finished Apr 25 03:09:18 PM PDT 24
Peak memory 204188 kb
Host smart-e0ac2f7a-f07d-4e1b-9fb1-c2a56c9d243b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877750912 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.2877750912
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.3434299444
Short name T1044
Test name
Test status
Simulation time 10074196899 ps
CPU time 66.51 seconds
Started Apr 25 03:09:14 PM PDT 24
Finished Apr 25 03:10:21 PM PDT 24
Peak memory 485956 kb
Host smart-4f9cde22-c9e4-47f1-bd4f-e6a7ebbe68f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434299444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.3434299444
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.230909037
Short name T233
Test name
Test status
Simulation time 10672769143 ps
CPU time 3.44 seconds
Started Apr 25 03:09:12 PM PDT 24
Finished Apr 25 03:09:17 PM PDT 24
Peak memory 220704 kb
Host smart-4ed89e38-b166-4c41-8306-c0d6a7abd86e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230909037 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_fifo_reset_tx.230909037
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.2655251906
Short name T343
Test name
Test status
Simulation time 354967592 ps
CPU time 2.09 seconds
Started Apr 25 03:09:14 PM PDT 24
Finished Apr 25 03:09:17 PM PDT 24
Peak memory 204196 kb
Host smart-3589f10f-c9b6-4da8-80a9-6e5d5a6d6700
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655251906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.2655251906
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.1902436004
Short name T1182
Test name
Test status
Simulation time 985108745 ps
CPU time 5.97 seconds
Started Apr 25 03:09:12 PM PDT 24
Finished Apr 25 03:09:20 PM PDT 24
Peak memory 209136 kb
Host smart-c135ec6d-d5b0-46a9-84d7-bf91e8578f35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902436004 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.1902436004
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.661551988
Short name T1067
Test name
Test status
Simulation time 3705758119 ps
CPU time 7.83 seconds
Started Apr 25 03:09:14 PM PDT 24
Finished Apr 25 03:09:23 PM PDT 24
Peak memory 204232 kb
Host smart-605b1dcc-1ee0-443a-8595-e0aa684e15c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661551988 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.661551988
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.1195023890
Short name T1152
Test name
Test status
Simulation time 1112824452 ps
CPU time 8.01 seconds
Started Apr 25 03:09:06 PM PDT 24
Finished Apr 25 03:09:15 PM PDT 24
Peak memory 204120 kb
Host smart-1d262148-5ffc-4919-8365-dcd450dfb516
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195023890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.1195023890
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.940583130
Short name T1279
Test name
Test status
Simulation time 3092082173 ps
CPU time 66.85 seconds
Started Apr 25 03:09:16 PM PDT 24
Finished Apr 25 03:10:24 PM PDT 24
Peak memory 207876 kb
Host smart-bfa4ab99-5b5d-4b00-971f-9e8e1f92ad6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940583130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_rd.940583130
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.3363954943
Short name T860
Test name
Test status
Simulation time 53279179833 ps
CPU time 1590.23 seconds
Started Apr 25 03:09:08 PM PDT 24
Finished Apr 25 03:35:40 PM PDT 24
Peak memory 8612020 kb
Host smart-6a0c9090-4521-4cb5-bb0e-e1163eca10d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363954943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.3363954943
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.1039524572
Short name T1275
Test name
Test status
Simulation time 21408638077 ps
CPU time 361.87 seconds
Started Apr 25 03:09:14 PM PDT 24
Finished Apr 25 03:15:17 PM PDT 24
Peak memory 2564268 kb
Host smart-3836ae35-8815-4815-a8db-082e338c9333
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039524572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.1039524572
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.2534974140
Short name T744
Test name
Test status
Simulation time 2362003197 ps
CPU time 6.4 seconds
Started Apr 25 03:09:16 PM PDT 24
Finished Apr 25 03:09:23 PM PDT 24
Peak memory 204312 kb
Host smart-daca6829-f349-4622-8240-91dc5b029020
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534974140 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.2534974140
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.1961190714
Short name T1100
Test name
Test status
Simulation time 15771846 ps
CPU time 0.65 seconds
Started Apr 25 03:09:30 PM PDT 24
Finished Apr 25 03:09:31 PM PDT 24
Peak memory 203872 kb
Host smart-d08c84c8-db42-4ce7-897f-844c75fc570b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961190714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.1961190714
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.2355583614
Short name T451
Test name
Test status
Simulation time 238569166 ps
CPU time 1.28 seconds
Started Apr 25 03:09:27 PM PDT 24
Finished Apr 25 03:09:30 PM PDT 24
Peak memory 220612 kb
Host smart-9ffb0d3d-8eb2-4e7b-86ad-b8826f05c7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355583614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.2355583614
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.324635971
Short name T488
Test name
Test status
Simulation time 471490184 ps
CPU time 12.6 seconds
Started Apr 25 03:09:19 PM PDT 24
Finished Apr 25 03:09:32 PM PDT 24
Peak memory 250920 kb
Host smart-932b0c52-0892-49ff-842d-013db6a2d4fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324635971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empt
y.324635971
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.3899359394
Short name T627
Test name
Test status
Simulation time 4902088988 ps
CPU time 30.66 seconds
Started Apr 25 03:09:27 PM PDT 24
Finished Apr 25 03:10:00 PM PDT 24
Peak memory 376024 kb
Host smart-39c6c776-d8c2-4ebe-94c8-f867420984be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899359394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.3899359394
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.2702466485
Short name T604
Test name
Test status
Simulation time 1479965422 ps
CPU time 43.98 seconds
Started Apr 25 03:09:19 PM PDT 24
Finished Apr 25 03:10:04 PM PDT 24
Peak memory 506968 kb
Host smart-15c759c0-91ac-4f7f-a386-937f6b10451f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702466485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2702466485
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.847065967
Short name T686
Test name
Test status
Simulation time 426694572 ps
CPU time 0.85 seconds
Started Apr 25 03:09:27 PM PDT 24
Finished Apr 25 03:09:30 PM PDT 24
Peak memory 203960 kb
Host smart-2bd09c60-92a9-4cb2-ad97-81d61a980f22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847065967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fm
t.847065967
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.992918563
Short name T798
Test name
Test status
Simulation time 2487050617 ps
CPU time 8.56 seconds
Started Apr 25 03:09:19 PM PDT 24
Finished Apr 25 03:09:29 PM PDT 24
Peak memory 204236 kb
Host smart-dba67dad-666b-4189-bcdf-6bd865d259a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992918563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.
992918563
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.1394264213
Short name T949
Test name
Test status
Simulation time 5548598203 ps
CPU time 76.04 seconds
Started Apr 25 03:09:27 PM PDT 24
Finished Apr 25 03:10:45 PM PDT 24
Peak memory 844132 kb
Host smart-5fdb3589-ebd5-4a26-acbf-d7d478c326f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394264213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.1394264213
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.267747794
Short name T203
Test name
Test status
Simulation time 1974061965 ps
CPU time 6.3 seconds
Started Apr 25 03:09:32 PM PDT 24
Finished Apr 25 03:09:40 PM PDT 24
Peak memory 204116 kb
Host smart-fd9ad08d-60de-4e7b-a617-90fad633d72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267747794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.267747794
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.1640248896
Short name T845
Test name
Test status
Simulation time 5818591118 ps
CPU time 30.03 seconds
Started Apr 25 03:09:33 PM PDT 24
Finished Apr 25 03:10:04 PM PDT 24
Peak memory 376520 kb
Host smart-db0175db-8086-4c16-848f-a2c4e79acfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640248896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.1640248896
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.1990960603
Short name T993
Test name
Test status
Simulation time 31873526 ps
CPU time 0.64 seconds
Started Apr 25 03:09:27 PM PDT 24
Finished Apr 25 03:09:30 PM PDT 24
Peak memory 203820 kb
Host smart-ebf9364e-44f2-458d-999a-9b54c141ddbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990960603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.1990960603
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.1915402001
Short name T1054
Test name
Test status
Simulation time 6842594957 ps
CPU time 103.76 seconds
Started Apr 25 03:09:17 PM PDT 24
Finished Apr 25 03:11:02 PM PDT 24
Peak memory 604808 kb
Host smart-14b3e886-1dd4-4268-9ef0-3ea872c12aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915402001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1915402001
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.1487031131
Short name T1263
Test name
Test status
Simulation time 6115040008 ps
CPU time 73.96 seconds
Started Apr 25 03:09:21 PM PDT 24
Finished Apr 25 03:10:36 PM PDT 24
Peak memory 328760 kb
Host smart-ab3d0a89-4c11-4d47-b407-b6366c06392b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487031131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1487031131
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.766647248
Short name T1265
Test name
Test status
Simulation time 18837561209 ps
CPU time 352.85 seconds
Started Apr 25 03:09:27 PM PDT 24
Finished Apr 25 03:15:22 PM PDT 24
Peak memory 996836 kb
Host smart-91c4f1f0-044b-48bd-a300-7466594b089b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766647248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.766647248
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.1551960292
Short name T1332
Test name
Test status
Simulation time 512467699 ps
CPU time 10.77 seconds
Started Apr 25 03:09:19 PM PDT 24
Finished Apr 25 03:09:31 PM PDT 24
Peak memory 219608 kb
Host smart-8efb8193-a06d-4d9d-a0f6-cc593df75051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551960292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.1551960292
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.2276544762
Short name T297
Test name
Test status
Simulation time 1468650500 ps
CPU time 3.68 seconds
Started Apr 25 03:09:26 PM PDT 24
Finished Apr 25 03:09:31 PM PDT 24
Peak memory 204208 kb
Host smart-ecdf32d9-d5da-442e-87e5-e874df2b7f0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276544762 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.2276544762
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.1539322360
Short name T453
Test name
Test status
Simulation time 10072480928 ps
CPU time 31.49 seconds
Started Apr 25 03:09:27 PM PDT 24
Finished Apr 25 03:10:01 PM PDT 24
Peak memory 341548 kb
Host smart-0a619c23-f6bd-4d5b-aa6b-30763122f8aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539322360 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.1539322360
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.407324332
Short name T877
Test name
Test status
Simulation time 10063483445 ps
CPU time 73.07 seconds
Started Apr 25 03:09:27 PM PDT 24
Finished Apr 25 03:10:42 PM PDT 24
Peak memory 470052 kb
Host smart-382803dc-9615-448d-bb5d-9add2464efe7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407324332 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_fifo_reset_tx.407324332
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.431867691
Short name T17
Test name
Test status
Simulation time 368742299 ps
CPU time 2.31 seconds
Started Apr 25 03:09:25 PM PDT 24
Finished Apr 25 03:09:29 PM PDT 24
Peak memory 204172 kb
Host smart-feb0ee12-b643-455a-a48e-4554d6cfd00b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431867691 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.i2c_target_hrst.431867691
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.930982412
Short name T366
Test name
Test status
Simulation time 888737410 ps
CPU time 4.46 seconds
Started Apr 25 03:09:28 PM PDT 24
Finished Apr 25 03:09:34 PM PDT 24
Peak memory 204164 kb
Host smart-f4532164-617a-443a-8d94-d87aa97a7e8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930982412 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_intr_smoke.930982412
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.3764423861
Short name T242
Test name
Test status
Simulation time 8736829207 ps
CPU time 79.45 seconds
Started Apr 25 03:09:27 PM PDT 24
Finished Apr 25 03:10:48 PM PDT 24
Peak memory 1733968 kb
Host smart-788da456-d69f-4535-8230-2987d284b7ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764423861 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.3764423861
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.1600643490
Short name T584
Test name
Test status
Simulation time 738058870 ps
CPU time 26.71 seconds
Started Apr 25 03:09:26 PM PDT 24
Finished Apr 25 03:09:55 PM PDT 24
Peak memory 204212 kb
Host smart-94ec265d-eaeb-433a-8e78-d9dadfe17ded
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600643490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.1600643490
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.2881134551
Short name T863
Test name
Test status
Simulation time 475918060 ps
CPU time 12.35 seconds
Started Apr 25 03:09:29 PM PDT 24
Finished Apr 25 03:09:42 PM PDT 24
Peak memory 204176 kb
Host smart-9728aa34-3f8c-46ef-aeb4-88eb1eb112ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881134551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.2881134551
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.701653344
Short name T349
Test name
Test status
Simulation time 46062647834 ps
CPU time 896.58 seconds
Started Apr 25 03:09:24 PM PDT 24
Finished Apr 25 03:24:22 PM PDT 24
Peak memory 6537424 kb
Host smart-d9922cdb-f4f8-49ad-9571-51cf4ba72778
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701653344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_wr.701653344
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.458043674
Short name T115
Test name
Test status
Simulation time 20850381575 ps
CPU time 365.84 seconds
Started Apr 25 03:09:24 PM PDT 24
Finished Apr 25 03:15:31 PM PDT 24
Peak memory 2566796 kb
Host smart-f042d144-af11-417c-a8eb-dd08ba41ee23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458043674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_t
arget_stretch.458043674
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.3959879948
Short name T1165
Test name
Test status
Simulation time 7580502207 ps
CPU time 7.09 seconds
Started Apr 25 03:09:27 PM PDT 24
Finished Apr 25 03:09:36 PM PDT 24
Peak memory 212424 kb
Host smart-39f609f9-7057-418c-bfec-d2ca923f6d7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959879948 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.3959879948
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2707283898
Short name T814
Test name
Test status
Simulation time 22835505 ps
CPU time 0.63 seconds
Started Apr 25 03:09:46 PM PDT 24
Finished Apr 25 03:09:48 PM PDT 24
Peak memory 203892 kb
Host smart-c16cffdd-2ded-432c-9fc3-b975fa5ca1d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707283898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2707283898
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.3850863831
Short name T866
Test name
Test status
Simulation time 386092287 ps
CPU time 1.46 seconds
Started Apr 25 03:09:37 PM PDT 24
Finished Apr 25 03:09:40 PM PDT 24
Peak memory 212564 kb
Host smart-9493f69d-871f-43f4-b54c-76936cd9364b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850863831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.3850863831
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3820591402
Short name T571
Test name
Test status
Simulation time 261025707 ps
CPU time 4.83 seconds
Started Apr 25 03:09:33 PM PDT 24
Finished Apr 25 03:09:39 PM PDT 24
Peak memory 251848 kb
Host smart-0685a2ce-ce2a-4391-b931-717ea833cb6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820591402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.3820591402
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.1684561091
Short name T1266
Test name
Test status
Simulation time 6393088304 ps
CPU time 112.63 seconds
Started Apr 25 03:09:39 PM PDT 24
Finished Apr 25 03:11:32 PM PDT 24
Peak memory 587644 kb
Host smart-c357ae9c-99f9-41d9-887f-2e9a74b33596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684561091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.1684561091
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.2431974346
Short name T1138
Test name
Test status
Simulation time 8777144941 ps
CPU time 91.02 seconds
Started Apr 25 03:09:30 PM PDT 24
Finished Apr 25 03:11:02 PM PDT 24
Peak memory 458200 kb
Host smart-90bfb70d-5cf3-4ec6-870a-3c9665ab660f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431974346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.2431974346
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.2197120579
Short name T402
Test name
Test status
Simulation time 510889695 ps
CPU time 1.08 seconds
Started Apr 25 03:09:32 PM PDT 24
Finished Apr 25 03:09:34 PM PDT 24
Peak memory 204160 kb
Host smart-b12fc36b-5e0b-4384-a6fa-bcf5a43ec4aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197120579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.2197120579
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.2738598633
Short name T437
Test name
Test status
Simulation time 184615576 ps
CPU time 3.97 seconds
Started Apr 25 03:09:33 PM PDT 24
Finished Apr 25 03:09:38 PM PDT 24
Peak memory 204168 kb
Host smart-537fa366-873e-4f46-89f9-850229d77c22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738598633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.2738598633
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.127391638
Short name T1244
Test name
Test status
Simulation time 29543801595 ps
CPU time 117.26 seconds
Started Apr 25 03:09:34 PM PDT 24
Finished Apr 25 03:11:32 PM PDT 24
Peak memory 1306184 kb
Host smart-be0c1bd3-9e76-47a0-a8f6-400600ca52ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127391638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.127391638
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.1266278326
Short name T953
Test name
Test status
Simulation time 611804443 ps
CPU time 7.23 seconds
Started Apr 25 03:09:45 PM PDT 24
Finished Apr 25 03:09:54 PM PDT 24
Peak memory 204148 kb
Host smart-82158981-3a74-4205-b70f-1a42931126a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266278326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.1266278326
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.4086364651
Short name T1251
Test name
Test status
Simulation time 1133866254 ps
CPU time 54.85 seconds
Started Apr 25 03:09:44 PM PDT 24
Finished Apr 25 03:10:40 PM PDT 24
Peak memory 347588 kb
Host smart-ff0a533b-f856-4fd6-8408-4d2b5047dfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086364651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.4086364651
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.2559779596
Short name T171
Test name
Test status
Simulation time 18456856 ps
CPU time 0.68 seconds
Started Apr 25 03:09:32 PM PDT 24
Finished Apr 25 03:09:34 PM PDT 24
Peak memory 203784 kb
Host smart-5c4d5c3a-e466-4b1d-89ed-d6a9216846b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559779596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.2559779596
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.1089399897
Short name T776
Test name
Test status
Simulation time 5622188214 ps
CPU time 231.49 seconds
Started Apr 25 03:09:37 PM PDT 24
Finished Apr 25 03:13:30 PM PDT 24
Peak memory 204272 kb
Host smart-b3883593-b86f-4697-93a1-024e665ac6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089399897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.1089399897
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.647408704
Short name T605
Test name
Test status
Simulation time 6860392021 ps
CPU time 28.04 seconds
Started Apr 25 03:09:31 PM PDT 24
Finished Apr 25 03:10:01 PM PDT 24
Peak memory 333104 kb
Host smart-3bbfeed6-5eda-4692-9a51-f527992bbb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647408704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.647408704
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.496228264
Short name T215
Test name
Test status
Simulation time 59798100796 ps
CPU time 2043.37 seconds
Started Apr 25 03:09:38 PM PDT 24
Finished Apr 25 03:43:43 PM PDT 24
Peak memory 3068112 kb
Host smart-d873033c-099b-45ca-934b-9b160f9218a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496228264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.496228264
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.3319802484
Short name T554
Test name
Test status
Simulation time 874992068 ps
CPU time 8.61 seconds
Started Apr 25 03:09:37 PM PDT 24
Finished Apr 25 03:09:47 PM PDT 24
Peak memory 212384 kb
Host smart-d7210ab5-d359-4f1c-a07e-88565e6cdd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319802484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3319802484
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.2116188728
Short name T1309
Test name
Test status
Simulation time 4667275517 ps
CPU time 4.88 seconds
Started Apr 25 03:09:43 PM PDT 24
Finished Apr 25 03:09:48 PM PDT 24
Peak memory 213352 kb
Host smart-8cdaade4-6325-4459-ba8d-10d38fbea574
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116188728 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.2116188728
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.3712235054
Short name T53
Test name
Test status
Simulation time 10406626431 ps
CPU time 13.66 seconds
Started Apr 25 03:09:37 PM PDT 24
Finished Apr 25 03:09:52 PM PDT 24
Peak memory 259712 kb
Host smart-3480087f-bbdf-4356-9487-14a881fcf5b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712235054 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.3712235054
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.157348192
Short name T484
Test name
Test status
Simulation time 10917629971 ps
CPU time 5.68 seconds
Started Apr 25 03:09:44 PM PDT 24
Finished Apr 25 03:09:51 PM PDT 24
Peak memory 230252 kb
Host smart-469768c6-efcd-4004-a7dc-b26e01afc933
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157348192 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_fifo_reset_tx.157348192
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.2039058067
Short name T1338
Test name
Test status
Simulation time 2136153540 ps
CPU time 2.75 seconds
Started Apr 25 03:09:50 PM PDT 24
Finished Apr 25 03:09:55 PM PDT 24
Peak memory 204212 kb
Host smart-e916ca72-01d1-453c-a4e9-2830910794e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039058067 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.2039058067
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.988881017
Short name T404
Test name
Test status
Simulation time 1262839193 ps
CPU time 5.78 seconds
Started Apr 25 03:09:39 PM PDT 24
Finished Apr 25 03:09:45 PM PDT 24
Peak memory 212280 kb
Host smart-2e5be19a-953d-4707-b8cd-b68d6cdc2561
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988881017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.988881017
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.3943552840
Short name T925
Test name
Test status
Simulation time 18209166431 ps
CPU time 48.58 seconds
Started Apr 25 03:09:37 PM PDT 24
Finished Apr 25 03:10:27 PM PDT 24
Peak memory 1040696 kb
Host smart-e209d46e-b132-4775-b40a-c04c42cd38e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943552840 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.3943552840
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.591725783
Short name T248
Test name
Test status
Simulation time 5483946955 ps
CPU time 50.23 seconds
Started Apr 25 03:09:38 PM PDT 24
Finished Apr 25 03:10:29 PM PDT 24
Peak memory 204232 kb
Host smart-cc3d0b90-ef22-48e5-9d77-db384f0d006c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591725783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_tar
get_smoke.591725783
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.2559156487
Short name T724
Test name
Test status
Simulation time 8249848235 ps
CPU time 59.41 seconds
Started Apr 25 03:09:37 PM PDT 24
Finished Apr 25 03:10:38 PM PDT 24
Peak memory 206964 kb
Host smart-e6ddbd02-8f4d-4ce0-9723-02417f996283
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559156487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.2559156487
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.3239108717
Short name T4
Test name
Test status
Simulation time 14103900522 ps
CPU time 8 seconds
Started Apr 25 03:09:37 PM PDT 24
Finished Apr 25 03:09:46 PM PDT 24
Peak memory 204212 kb
Host smart-2c3857bf-83f7-4ca1-9e13-3ff91333b401
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239108717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.3239108717
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.4048675130
Short name T757
Test name
Test status
Simulation time 36089533241 ps
CPU time 275.63 seconds
Started Apr 25 03:09:38 PM PDT 24
Finished Apr 25 03:14:15 PM PDT 24
Peak memory 2037744 kb
Host smart-87139591-64c5-4d15-b9aa-3d40aa3dfa2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048675130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.4048675130
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.236159685
Short name T12
Test name
Test status
Simulation time 5135082682 ps
CPU time 7.07 seconds
Started Apr 25 03:09:37 PM PDT 24
Finished Apr 25 03:09:45 PM PDT 24
Peak memory 220500 kb
Host smart-9976428f-d6d2-4f4c-b441-e23e5bdc76e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236159685 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_timeout.236159685
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.3603065243
Short name T1115
Test name
Test status
Simulation time 24080141 ps
CPU time 0.61 seconds
Started Apr 25 03:05:17 PM PDT 24
Finished Apr 25 03:05:18 PM PDT 24
Peak memory 203924 kb
Host smart-50a3ed4b-ca46-44df-96fd-ad45bb2009eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603065243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.3603065243
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.2694533711
Short name T498
Test name
Test status
Simulation time 61917819 ps
CPU time 1.28 seconds
Started Apr 25 03:04:59 PM PDT 24
Finished Apr 25 03:05:02 PM PDT 24
Peak memory 212496 kb
Host smart-ef9047e1-013f-4c88-9652-991a98d32961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694533711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.2694533711
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.847271190
Short name T442
Test name
Test status
Simulation time 880814606 ps
CPU time 4.11 seconds
Started Apr 25 03:04:55 PM PDT 24
Finished Apr 25 03:05:00 PM PDT 24
Peak memory 245804 kb
Host smart-da55e345-75a3-4b1e-b842-82d145cb5fa1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847271190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty
.847271190
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.896398032
Short name T1076
Test name
Test status
Simulation time 3009771011 ps
CPU time 34.84 seconds
Started Apr 25 03:04:59 PM PDT 24
Finished Apr 25 03:05:34 PM PDT 24
Peak memory 467484 kb
Host smart-b3f4c689-4c87-4453-a0db-a43e3680a748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896398032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.896398032
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.1779358492
Short name T1296
Test name
Test status
Simulation time 1177175717 ps
CPU time 78.89 seconds
Started Apr 25 03:04:59 PM PDT 24
Finished Apr 25 03:06:19 PM PDT 24
Peak memory 468592 kb
Host smart-1f540cac-5061-43a8-a264-b31e03df352a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779358492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.1779358492
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.432043832
Short name T1223
Test name
Test status
Simulation time 611633022 ps
CPU time 0.97 seconds
Started Apr 25 03:04:55 PM PDT 24
Finished Apr 25 03:04:57 PM PDT 24
Peak memory 204072 kb
Host smart-37552242-00a0-41a4-a207-5b3d942c3631
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432043832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt
.432043832
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.1263956428
Short name T911
Test name
Test status
Simulation time 2784439748 ps
CPU time 176.44 seconds
Started Apr 25 03:04:52 PM PDT 24
Finished Apr 25 03:07:49 PM PDT 24
Peak memory 873188 kb
Host smart-c82d6c2d-6898-424a-bc5c-53be54572de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263956428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.1263956428
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.1104306104
Short name T1241
Test name
Test status
Simulation time 324702534 ps
CPU time 11.52 seconds
Started Apr 25 03:05:15 PM PDT 24
Finished Apr 25 03:05:28 PM PDT 24
Peak memory 204192 kb
Host smart-bd4c6a5a-1087-445f-aac9-23fe41559474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104306104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.1104306104
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.2584154691
Short name T1245
Test name
Test status
Simulation time 1069584961 ps
CPU time 51.6 seconds
Started Apr 25 03:05:14 PM PDT 24
Finished Apr 25 03:06:07 PM PDT 24
Peak memory 301136 kb
Host smart-79d6c5e2-f931-423a-9f84-5449695a677b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584154691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.2584154691
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.1250833464
Short name T514
Test name
Test status
Simulation time 74681902 ps
CPU time 0.63 seconds
Started Apr 25 03:04:54 PM PDT 24
Finished Apr 25 03:04:56 PM PDT 24
Peak memory 203848 kb
Host smart-e6bff6bf-7315-4087-a312-e84953739442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250833464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1250833464
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.1690320327
Short name T752
Test name
Test status
Simulation time 5288343254 ps
CPU time 69.37 seconds
Started Apr 25 03:05:00 PM PDT 24
Finished Apr 25 03:06:10 PM PDT 24
Peak memory 486876 kb
Host smart-8963c63a-eb9b-40bb-b2b0-1746fa18b782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690320327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.1690320327
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.4142209602
Short name T1183
Test name
Test status
Simulation time 5455372961 ps
CPU time 15.82 seconds
Started Apr 25 03:04:55 PM PDT 24
Finished Apr 25 03:05:12 PM PDT 24
Peak memory 311840 kb
Host smart-3ffdb0ea-4a97-45f2-910c-48519749fd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142209602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.4142209602
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.1129919648
Short name T160
Test name
Test status
Simulation time 57989271583 ps
CPU time 891.47 seconds
Started Apr 25 03:04:59 PM PDT 24
Finished Apr 25 03:19:52 PM PDT 24
Peak memory 3271412 kb
Host smart-44c2e251-638c-4d74-974b-5a71899baa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129919648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.1129919648
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.3288651883
Short name T589
Test name
Test status
Simulation time 2107137159 ps
CPU time 10.48 seconds
Started Apr 25 03:04:58 PM PDT 24
Finished Apr 25 03:05:09 PM PDT 24
Peak memory 213388 kb
Host smart-73b2e6b4-aa96-4750-a4bf-1b0a31a0d2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288651883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3288651883
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.743303774
Short name T114
Test name
Test status
Simulation time 39728002 ps
CPU time 0.88 seconds
Started Apr 25 03:05:18 PM PDT 24
Finished Apr 25 03:05:19 PM PDT 24
Peak memory 221448 kb
Host smart-153368b2-063b-40e9-8f04-545442b53578
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743303774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.743303774
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.3305017983
Short name T1013
Test name
Test status
Simulation time 10239317792 ps
CPU time 3.2 seconds
Started Apr 25 03:05:13 PM PDT 24
Finished Apr 25 03:05:17 PM PDT 24
Peak memory 204268 kb
Host smart-80bc52b4-97cf-4712-a685-c017f73d854c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305017983 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.3305017983
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.2738054821
Short name T1249
Test name
Test status
Simulation time 10277332628 ps
CPU time 14.3 seconds
Started Apr 25 03:05:12 PM PDT 24
Finished Apr 25 03:05:28 PM PDT 24
Peak memory 302052 kb
Host smart-88106070-ed0a-40c1-9e79-87193cda8c40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738054821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.2738054821
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.3506944280
Short name T230
Test name
Test status
Simulation time 842745675 ps
CPU time 2.43 seconds
Started Apr 25 03:05:11 PM PDT 24
Finished Apr 25 03:05:15 PM PDT 24
Peak memory 204224 kb
Host smart-58588ca3-ce24-4841-956a-74c731a0406a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506944280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.3506944280
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.1554276183
Short name T1038
Test name
Test status
Simulation time 8075037753 ps
CPU time 6.8 seconds
Started Apr 25 03:05:03 PM PDT 24
Finished Apr 25 03:05:11 PM PDT 24
Peak memory 220572 kb
Host smart-772e5db2-8e74-4a5e-bae9-4b525168dc3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554276183 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.1554276183
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.4261659589
Short name T1212
Test name
Test status
Simulation time 866967540 ps
CPU time 10.58 seconds
Started Apr 25 03:05:00 PM PDT 24
Finished Apr 25 03:05:11 PM PDT 24
Peak memory 204144 kb
Host smart-e61440c2-8d8e-44c8-b4ed-f9adf8b7f098
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261659589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.4261659589
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.2681041302
Short name T1017
Test name
Test status
Simulation time 1547089420 ps
CPU time 31.81 seconds
Started Apr 25 03:04:59 PM PDT 24
Finished Apr 25 03:05:31 PM PDT 24
Peak memory 204156 kb
Host smart-7bb28d27-e715-4c4f-a87a-dc6392040beb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681041302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.2681041302
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.145530355
Short name T958
Test name
Test status
Simulation time 52436775932 ps
CPU time 456.06 seconds
Started Apr 25 03:04:59 PM PDT 24
Finished Apr 25 03:12:36 PM PDT 24
Peak memory 4141584 kb
Host smart-f4f9989b-0b3e-44da-93e6-b8f22ba4c0f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145530355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_wr.145530355
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.3136670660
Short name T623
Test name
Test status
Simulation time 37879953201 ps
CPU time 3150.48 seconds
Started Apr 25 03:04:59 PM PDT 24
Finished Apr 25 03:57:31 PM PDT 24
Peak memory 4564476 kb
Host smart-1e469388-1196-4d4b-b563-8f7ddfd8907f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136670660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.3136670660
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.1362953919
Short name T1238
Test name
Test status
Simulation time 22103636084 ps
CPU time 6.57 seconds
Started Apr 25 03:05:06 PM PDT 24
Finished Apr 25 03:05:13 PM PDT 24
Peak memory 212420 kb
Host smart-8df60611-b08d-483b-8c91-6f64af35cb38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362953919 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.1362953919
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.217932588
Short name T1142
Test name
Test status
Simulation time 15345835 ps
CPU time 0.62 seconds
Started Apr 25 03:09:56 PM PDT 24
Finished Apr 25 03:09:58 PM PDT 24
Peak memory 203776 kb
Host smart-d46a4dcc-78f1-45fe-9044-a098c8380c47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217932588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.217932588
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.2073248327
Short name T917
Test name
Test status
Simulation time 212388594 ps
CPU time 1.52 seconds
Started Apr 25 03:09:51 PM PDT 24
Finished Apr 25 03:09:55 PM PDT 24
Peak memory 212444 kb
Host smart-4f332057-d95d-4c2b-bbac-d7abf8697278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073248327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.2073248327
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.1843295854
Short name T940
Test name
Test status
Simulation time 1290502676 ps
CPU time 12.94 seconds
Started Apr 25 03:09:51 PM PDT 24
Finished Apr 25 03:10:06 PM PDT 24
Peak memory 341920 kb
Host smart-bedef18a-1604-4062-aba1-23d7831964d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843295854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.1843295854
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.1487529253
Short name T1068
Test name
Test status
Simulation time 9150065770 ps
CPU time 159.25 seconds
Started Apr 25 03:09:49 PM PDT 24
Finished Apr 25 03:12:30 PM PDT 24
Peak memory 722356 kb
Host smart-232aa200-5977-4c9b-8329-268226a31def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487529253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.1487529253
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.3496779019
Short name T544
Test name
Test status
Simulation time 10196163439 ps
CPU time 30.97 seconds
Started Apr 25 03:09:44 PM PDT 24
Finished Apr 25 03:10:16 PM PDT 24
Peak memory 415500 kb
Host smart-b13ded46-f565-47b3-99b1-2c2633c22931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496779019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3496779019
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.3337738343
Short name T1135
Test name
Test status
Simulation time 1064092949 ps
CPU time 0.94 seconds
Started Apr 25 03:09:50 PM PDT 24
Finished Apr 25 03:09:53 PM PDT 24
Peak memory 203976 kb
Host smart-8a7fad63-6d96-48f0-8bf7-96e21388968d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337738343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.3337738343
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.940962353
Short name T478
Test name
Test status
Simulation time 197218381 ps
CPU time 11.02 seconds
Started Apr 25 03:09:50 PM PDT 24
Finished Apr 25 03:10:02 PM PDT 24
Peak memory 240472 kb
Host smart-bedac196-c3c5-4a7a-9f6f-9081858a0f94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940962353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.
940962353
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.1713167593
Short name T207
Test name
Test status
Simulation time 36515801084 ps
CPU time 132.15 seconds
Started Apr 25 03:09:45 PM PDT 24
Finished Apr 25 03:11:58 PM PDT 24
Peak memory 1172696 kb
Host smart-276f644b-3ad6-472c-9ada-04bc8e726b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713167593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.1713167593
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.3429349106
Short name T392
Test name
Test status
Simulation time 917886247 ps
CPU time 7.46 seconds
Started Apr 25 03:09:58 PM PDT 24
Finished Apr 25 03:10:06 PM PDT 24
Peak memory 204176 kb
Host smart-4ebe822a-4ae2-4716-8bf3-623603f0aa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429349106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.3429349106
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.1570975873
Short name T552
Test name
Test status
Simulation time 1631380315 ps
CPU time 29.96 seconds
Started Apr 25 03:09:56 PM PDT 24
Finished Apr 25 03:10:27 PM PDT 24
Peak memory 294188 kb
Host smart-d2e827c7-78d9-4a66-be01-15ee5acda9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570975873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.1570975873
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.2690466298
Short name T275
Test name
Test status
Simulation time 27678317 ps
CPU time 0.68 seconds
Started Apr 25 03:09:45 PM PDT 24
Finished Apr 25 03:09:46 PM PDT 24
Peak memory 203904 kb
Host smart-d7a4f562-49c5-4214-b18a-fa22d1ed2270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690466298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.2690466298
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.2588029492
Short name T1353
Test name
Test status
Simulation time 778132478 ps
CPU time 7.77 seconds
Started Apr 25 03:09:50 PM PDT 24
Finished Apr 25 03:10:00 PM PDT 24
Peak memory 245676 kb
Host smart-c4ae587c-e972-4932-83d4-56e867122af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588029492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2588029492
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1726227246
Short name T55
Test name
Test status
Simulation time 1762179389 ps
CPU time 13.83 seconds
Started Apr 25 03:09:45 PM PDT 24
Finished Apr 25 03:09:59 PM PDT 24
Peak memory 243100 kb
Host smart-2edd02c9-1f38-4519-b614-bce583c93898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726227246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1726227246
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.3137129459
Short name T773
Test name
Test status
Simulation time 25264879178 ps
CPU time 3095.61 seconds
Started Apr 25 03:09:49 PM PDT 24
Finished Apr 25 04:01:27 PM PDT 24
Peak memory 1931420 kb
Host smart-2c13c809-95bf-4cd1-ac95-a0ac5a069bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137129459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.3137129459
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.892119925
Short name T1133
Test name
Test status
Simulation time 2406062672 ps
CPU time 32.21 seconds
Started Apr 25 03:09:49 PM PDT 24
Finished Apr 25 03:10:23 PM PDT 24
Peak memory 212572 kb
Host smart-76d80b40-e1d1-4ed2-ab6c-d0e9794c7afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892119925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.892119925
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.2176585990
Short name T1302
Test name
Test status
Simulation time 2805187435 ps
CPU time 2.96 seconds
Started Apr 25 03:09:55 PM PDT 24
Finished Apr 25 03:09:59 PM PDT 24
Peak memory 204288 kb
Host smart-0a91c30f-70e7-4fb4-8252-146be33a80ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176585990 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.2176585990
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.812172853
Short name T1168
Test name
Test status
Simulation time 10258789061 ps
CPU time 34.78 seconds
Started Apr 25 03:09:57 PM PDT 24
Finished Apr 25 03:10:33 PM PDT 24
Peak memory 407252 kb
Host smart-a51a16ff-c7f1-4f68-80f2-9ccc326362cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812172853 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_fifo_reset_tx.812172853
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.1654124079
Short name T360
Test name
Test status
Simulation time 1539044035 ps
CPU time 2.52 seconds
Started Apr 25 03:10:01 PM PDT 24
Finished Apr 25 03:10:04 PM PDT 24
Peak memory 204104 kb
Host smart-baae63cd-7888-43a5-b6e2-b4068920c51c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654124079 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.1654124079
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.1848205475
Short name T493
Test name
Test status
Simulation time 3485384891 ps
CPU time 4.8 seconds
Started Apr 25 03:09:52 PM PDT 24
Finished Apr 25 03:09:59 PM PDT 24
Peak memory 206348 kb
Host smart-b58108bc-1900-4354-8dfb-44bc6c03944f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848205475 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.1848205475
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.3923163306
Short name T11
Test name
Test status
Simulation time 18855921110 ps
CPU time 122.62 seconds
Started Apr 25 03:09:51 PM PDT 24
Finished Apr 25 03:11:56 PM PDT 24
Peak memory 2233212 kb
Host smart-cbe19d7a-9189-468e-a703-d2d11e14655e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923163306 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.3923163306
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.1377695644
Short name T365
Test name
Test status
Simulation time 842255787 ps
CPU time 31.31 seconds
Started Apr 25 03:09:50 PM PDT 24
Finished Apr 25 03:10:23 PM PDT 24
Peak memory 204116 kb
Host smart-b6256816-2035-40a6-898a-acbf75375a0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377695644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.1377695644
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.3944462380
Short name T199
Test name
Test status
Simulation time 1647124003 ps
CPU time 72.42 seconds
Started Apr 25 03:09:48 PM PDT 24
Finished Apr 25 03:11:02 PM PDT 24
Peak memory 206024 kb
Host smart-2a6ee7ec-63f9-44ce-8610-d881fe6de5ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944462380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.3944462380
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.228239737
Short name T973
Test name
Test status
Simulation time 60639998587 ps
CPU time 2131.14 seconds
Started Apr 25 03:09:57 PM PDT 24
Finished Apr 25 03:45:30 PM PDT 24
Peak memory 10038336 kb
Host smart-87ce2ffe-9b5e-45c6-8240-ab3575d786ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228239737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_wr.228239737
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.3739511368
Short name T990
Test name
Test status
Simulation time 32748983468 ps
CPU time 264.09 seconds
Started Apr 25 03:09:52 PM PDT 24
Finished Apr 25 03:14:18 PM PDT 24
Peak memory 2008812 kb
Host smart-a4e7c2eb-60d4-499a-8d50-45bf7c0c2f87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739511368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.3739511368
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.800899801
Short name T252
Test name
Test status
Simulation time 7323645530 ps
CPU time 7.49 seconds
Started Apr 25 03:09:50 PM PDT 24
Finished Apr 25 03:09:59 PM PDT 24
Peak memory 212472 kb
Host smart-a1e7ae14-6b8d-4b88-a3a6-d54045989662
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800899801 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.800899801
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.3559978988
Short name T417
Test name
Test status
Simulation time 1246683977 ps
CPU time 3.61 seconds
Started Apr 25 03:09:54 PM PDT 24
Finished Apr 25 03:09:59 PM PDT 24
Peak memory 204196 kb
Host smart-74192f83-b9af-4fc0-814a-8e5e013a7ed2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559978988 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.i2c_target_unexp_stop.3559978988
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.17559411
Short name T1287
Test name
Test status
Simulation time 39839318 ps
CPU time 0.6 seconds
Started Apr 25 03:10:05 PM PDT 24
Finished Apr 25 03:10:06 PM PDT 24
Peak memory 203920 kb
Host smart-4339fe15-2c44-4294-81df-4359d7d2d449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17559411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.17559411
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.2880051385
Short name T1210
Test name
Test status
Simulation time 374736271 ps
CPU time 1.97 seconds
Started Apr 25 03:10:04 PM PDT 24
Finished Apr 25 03:10:07 PM PDT 24
Peak memory 212508 kb
Host smart-8524ae78-4628-42df-951b-92778f709365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880051385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2880051385
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.3661301519
Short name T616
Test name
Test status
Simulation time 1134487759 ps
CPU time 6.61 seconds
Started Apr 25 03:09:55 PM PDT 24
Finished Apr 25 03:10:03 PM PDT 24
Peak memory 260576 kb
Host smart-3be7a681-a070-4037-b1bc-e004f64c192f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661301519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.3661301519
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.3006358031
Short name T1088
Test name
Test status
Simulation time 2309669335 ps
CPU time 68.93 seconds
Started Apr 25 03:10:02 PM PDT 24
Finished Apr 25 03:11:12 PM PDT 24
Peak memory 710720 kb
Host smart-298f66d7-fd6b-488d-9dc7-0bdbc34b49e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006358031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.3006358031
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.2193854336
Short name T482
Test name
Test status
Simulation time 16890919459 ps
CPU time 80.99 seconds
Started Apr 25 03:10:01 PM PDT 24
Finished Apr 25 03:11:23 PM PDT 24
Peak memory 750244 kb
Host smart-66aafc93-b779-4032-aa84-f4cf71825f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193854336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.2193854336
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.2460444028
Short name T1324
Test name
Test status
Simulation time 237086173 ps
CPU time 1.1 seconds
Started Apr 25 03:09:56 PM PDT 24
Finished Apr 25 03:09:58 PM PDT 24
Peak memory 204172 kb
Host smart-9fdfc1b4-a189-454e-8012-d62d61fc4fc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460444028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.2460444028
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.3219171685
Short name T705
Test name
Test status
Simulation time 785199870 ps
CPU time 7.45 seconds
Started Apr 25 03:10:04 PM PDT 24
Finished Apr 25 03:10:12 PM PDT 24
Peak memory 224088 kb
Host smart-47332d1a-4cdf-45e8-bb7d-bea761022667
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219171685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.3219171685
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.842569709
Short name T265
Test name
Test status
Simulation time 16244556208 ps
CPU time 105.56 seconds
Started Apr 25 03:09:55 PM PDT 24
Finished Apr 25 03:11:42 PM PDT 24
Peak memory 1061920 kb
Host smart-c74e12aa-3cb2-427a-bcaf-fc0ea8e7a715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842569709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.842569709
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.3923712354
Short name T1306
Test name
Test status
Simulation time 997076376 ps
CPU time 5.49 seconds
Started Apr 25 03:10:07 PM PDT 24
Finished Apr 25 03:10:13 PM PDT 24
Peak memory 204136 kb
Host smart-9fdda60d-0aca-4cec-8972-4e7b96cac258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923712354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.3923712354
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.629012625
Short name T570
Test name
Test status
Simulation time 7862545156 ps
CPU time 37.7 seconds
Started Apr 25 03:10:06 PM PDT 24
Finished Apr 25 03:10:44 PM PDT 24
Peak memory 432132 kb
Host smart-bdb45c45-e2ff-439b-a676-11d7211dfcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629012625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.629012625
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.1396090506
Short name T395
Test name
Test status
Simulation time 28588164 ps
CPU time 0.65 seconds
Started Apr 25 03:09:56 PM PDT 24
Finished Apr 25 03:09:58 PM PDT 24
Peak memory 203844 kb
Host smart-548cdf14-b34a-4846-94ba-67dde1579518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396090506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1396090506
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.1789553682
Short name T175
Test name
Test status
Simulation time 28290764347 ps
CPU time 529.29 seconds
Started Apr 25 03:10:03 PM PDT 24
Finished Apr 25 03:18:53 PM PDT 24
Peak memory 1251476 kb
Host smart-89e79ea3-d3c8-4102-a768-3bcbe972c890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789553682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.1789553682
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.517703659
Short name T270
Test name
Test status
Simulation time 1674815718 ps
CPU time 91.91 seconds
Started Apr 25 03:09:55 PM PDT 24
Finished Apr 25 03:11:28 PM PDT 24
Peak memory 414704 kb
Host smart-7cb95fe7-6908-4444-a400-078aa32deb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517703659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.517703659
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.3640098273
Short name T157
Test name
Test status
Simulation time 43339733415 ps
CPU time 396.93 seconds
Started Apr 25 03:10:06 PM PDT 24
Finished Apr 25 03:16:44 PM PDT 24
Peak memory 1239572 kb
Host smart-763b212d-4a2d-4545-9ff9-f26a990fafbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640098273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.3640098273
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.1082716948
Short name T262
Test name
Test status
Simulation time 1287118019 ps
CPU time 7.76 seconds
Started Apr 25 03:10:04 PM PDT 24
Finished Apr 25 03:10:13 PM PDT 24
Peak memory 212284 kb
Host smart-971737c9-6cce-48af-af25-7ff5b9fb2e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082716948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.1082716948
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.1965015509
Short name T28
Test name
Test status
Simulation time 2672276963 ps
CPU time 3.46 seconds
Started Apr 25 03:10:11 PM PDT 24
Finished Apr 25 03:10:15 PM PDT 24
Peak memory 204204 kb
Host smart-e1c91751-0058-4acf-8247-5b74cbd47a4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965015509 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.1965015509
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.4021387286
Short name T629
Test name
Test status
Simulation time 10322423532 ps
CPU time 14.8 seconds
Started Apr 25 03:10:09 PM PDT 24
Finished Apr 25 03:10:25 PM PDT 24
Peak memory 253576 kb
Host smart-d7e8a173-05c5-4afb-a2e3-3c16afbb1840
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021387286 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.4021387286
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3517318845
Short name T304
Test name
Test status
Simulation time 10215313270 ps
CPU time 13.29 seconds
Started Apr 25 03:10:14 PM PDT 24
Finished Apr 25 03:10:28 PM PDT 24
Peak memory 273852 kb
Host smart-67fa868e-8c54-4cd5-95d3-3c1cd856342a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517318845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3517318845
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.2044172444
Short name T1336
Test name
Test status
Simulation time 293442119 ps
CPU time 2.13 seconds
Started Apr 25 03:10:08 PM PDT 24
Finished Apr 25 03:10:11 PM PDT 24
Peak memory 204132 kb
Host smart-0ce2d844-01c9-42e7-926f-d6708f84186b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044172444 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.2044172444
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.3417867996
Short name T577
Test name
Test status
Simulation time 3499432613 ps
CPU time 4.1 seconds
Started Apr 25 03:10:05 PM PDT 24
Finished Apr 25 03:10:10 PM PDT 24
Peak memory 206028 kb
Host smart-22e54a7e-253a-4ee6-a65b-9315186afeb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417867996 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.3417867996
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.1859782043
Short name T784
Test name
Test status
Simulation time 19647087747 ps
CPU time 32.82 seconds
Started Apr 25 03:10:09 PM PDT 24
Finished Apr 25 03:10:42 PM PDT 24
Peak memory 852520 kb
Host smart-9d0a89b1-2fb5-4ffe-9bb0-6eae6a961d17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859782043 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.1859782043
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.4091389818
Short name T310
Test name
Test status
Simulation time 541750980 ps
CPU time 8.59 seconds
Started Apr 25 03:10:04 PM PDT 24
Finished Apr 25 03:10:13 PM PDT 24
Peak memory 204180 kb
Host smart-18a64995-9589-4e82-9380-826071b993d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091389818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.4091389818
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.3693984074
Short name T772
Test name
Test status
Simulation time 613871576 ps
CPU time 6.18 seconds
Started Apr 25 03:10:01 PM PDT 24
Finished Apr 25 03:10:08 PM PDT 24
Peak memory 204220 kb
Host smart-22734a7c-9f67-4479-a6f2-efc1b0e6a77a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693984074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.3693984074
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.1992128983
Short name T1043
Test name
Test status
Simulation time 15803655163 ps
CPU time 30.38 seconds
Started Apr 25 03:10:04 PM PDT 24
Finished Apr 25 03:10:35 PM PDT 24
Peak memory 204148 kb
Host smart-26e91261-e878-414b-b6a6-fa6001a0bb91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992128983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.1992128983
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.769943290
Short name T1259
Test name
Test status
Simulation time 15019991800 ps
CPU time 87.84 seconds
Started Apr 25 03:10:04 PM PDT 24
Finished Apr 25 03:11:33 PM PDT 24
Peak memory 940916 kb
Host smart-f3f378fe-9e8a-49c1-bc3a-e6965729494a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769943290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_t
arget_stretch.769943290
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.714239448
Short name T932
Test name
Test status
Simulation time 5156462302 ps
CPU time 6.45 seconds
Started Apr 25 03:10:07 PM PDT 24
Finished Apr 25 03:10:14 PM PDT 24
Peak memory 212484 kb
Host smart-5b254cbf-dfaf-43a3-80ec-3e88eb1b3fec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714239448 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_timeout.714239448
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.2726441492
Short name T1031
Test name
Test status
Simulation time 17215304 ps
CPU time 0.63 seconds
Started Apr 25 03:10:20 PM PDT 24
Finished Apr 25 03:10:21 PM PDT 24
Peak memory 203892 kb
Host smart-34b65cfe-9ee2-4506-b21a-275ed96e16d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726441492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.2726441492
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.904335345
Short name T964
Test name
Test status
Simulation time 438901992 ps
CPU time 1.35 seconds
Started Apr 25 03:10:13 PM PDT 24
Finished Apr 25 03:10:16 PM PDT 24
Peak memory 212484 kb
Host smart-8b6d2e9a-9b26-4495-bd5f-0e10c7e6886e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904335345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.904335345
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1665382846
Short name T803
Test name
Test status
Simulation time 303580755 ps
CPU time 6.89 seconds
Started Apr 25 03:10:13 PM PDT 24
Finished Apr 25 03:10:22 PM PDT 24
Peak memory 263108 kb
Host smart-5119c365-2446-472a-8526-344ee693eec9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665382846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1665382846
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.4058212892
Short name T1178
Test name
Test status
Simulation time 3743096562 ps
CPU time 60.99 seconds
Started Apr 25 03:10:14 PM PDT 24
Finished Apr 25 03:11:16 PM PDT 24
Peak memory 593176 kb
Host smart-3002abcb-fbab-4f90-83ae-62462ab4a8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058212892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.4058212892
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.3241797999
Short name T1181
Test name
Test status
Simulation time 1176655295 ps
CPU time 36.58 seconds
Started Apr 25 03:10:07 PM PDT 24
Finished Apr 25 03:10:45 PM PDT 24
Peak memory 493016 kb
Host smart-a70404ab-4bf1-4b4a-95c8-6b4e8d9fb6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241797999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.3241797999
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2731264629
Short name T819
Test name
Test status
Simulation time 1488305147 ps
CPU time 1.08 seconds
Started Apr 25 03:10:07 PM PDT 24
Finished Apr 25 03:10:09 PM PDT 24
Peak memory 204000 kb
Host smart-9a302a81-7273-4cfc-8782-618cbf6077ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731264629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.2731264629
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.2104501566
Short name T986
Test name
Test status
Simulation time 131828382 ps
CPU time 3.4 seconds
Started Apr 25 03:10:21 PM PDT 24
Finished Apr 25 03:10:25 PM PDT 24
Peak memory 204164 kb
Host smart-59e72fa5-8344-40c5-8654-0e3d20c343f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104501566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.2104501566
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.2243633807
Short name T159
Test name
Test status
Simulation time 11677310635 ps
CPU time 84.75 seconds
Started Apr 25 03:10:14 PM PDT 24
Finished Apr 25 03:11:40 PM PDT 24
Peak memory 988148 kb
Host smart-35a8abd4-e05c-4546-be7d-5b94db39027c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243633807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.2243633807
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.4171359552
Short name T189
Test name
Test status
Simulation time 577573283 ps
CPU time 9.02 seconds
Started Apr 25 03:10:22 PM PDT 24
Finished Apr 25 03:10:31 PM PDT 24
Peak memory 204188 kb
Host smart-2747d62f-c878-44de-9205-2e1278ef855f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171359552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.4171359552
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.430866867
Short name T582
Test name
Test status
Simulation time 6551438100 ps
CPU time 69.62 seconds
Started Apr 25 03:10:21 PM PDT 24
Finished Apr 25 03:11:32 PM PDT 24
Peak memory 314920 kb
Host smart-271b0501-8af1-4221-809a-e924e1aae87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430866867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.430866867
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.4243753525
Short name T408
Test name
Test status
Simulation time 22905973 ps
CPU time 0.65 seconds
Started Apr 25 03:10:07 PM PDT 24
Finished Apr 25 03:10:09 PM PDT 24
Peak memory 203824 kb
Host smart-4c8e96e5-0add-4e8b-b394-5b861fa25b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243753525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.4243753525
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.3173921857
Short name T622
Test name
Test status
Simulation time 556888192 ps
CPU time 2.35 seconds
Started Apr 25 03:10:13 PM PDT 24
Finished Apr 25 03:10:16 PM PDT 24
Peak memory 214640 kb
Host smart-f67559f5-b299-464e-92a5-7874003da7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173921857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.3173921857
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.897140618
Short name T808
Test name
Test status
Simulation time 4244918922 ps
CPU time 32.29 seconds
Started Apr 25 03:10:07 PM PDT 24
Finished Apr 25 03:10:40 PM PDT 24
Peak memory 369312 kb
Host smart-60d04c95-a80f-4b14-9c6f-7937aceaa265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897140618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.897140618
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.4191351308
Short name T80
Test name
Test status
Simulation time 10026175566 ps
CPU time 315.72 seconds
Started Apr 25 03:10:25 PM PDT 24
Finished Apr 25 03:15:41 PM PDT 24
Peak memory 1121236 kb
Host smart-b1ba7e67-c832-4243-9c27-685ece22b470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191351308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.4191351308
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.1346912403
Short name T434
Test name
Test status
Simulation time 767711945 ps
CPU time 7.11 seconds
Started Apr 25 03:10:14 PM PDT 24
Finished Apr 25 03:10:22 PM PDT 24
Peak memory 212384 kb
Host smart-57103964-89d7-4977-9d89-9cfc72a3f30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346912403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.1346912403
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.3691058707
Short name T905
Test name
Test status
Simulation time 10638282536 ps
CPU time 4.45 seconds
Started Apr 25 03:10:20 PM PDT 24
Finished Apr 25 03:10:25 PM PDT 24
Peak memory 212464 kb
Host smart-6de8d461-cf65-4c58-af9c-fb154daace02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691058707 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.3691058707
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.1487632037
Short name T84
Test name
Test status
Simulation time 10071836140 ps
CPU time 67.76 seconds
Started Apr 25 03:10:23 PM PDT 24
Finished Apr 25 03:11:32 PM PDT 24
Peak memory 440176 kb
Host smart-43faa0d6-3019-4744-ba46-cb77f5d84325
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487632037 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.1487632037
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.4264514491
Short name T591
Test name
Test status
Simulation time 10123025367 ps
CPU time 31.76 seconds
Started Apr 25 03:10:19 PM PDT 24
Finished Apr 25 03:10:51 PM PDT 24
Peak memory 361456 kb
Host smart-95d218cb-578e-4280-a2ba-8d3cc5f8574f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264514491 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.4264514491
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.3546823514
Short name T1156
Test name
Test status
Simulation time 421532621 ps
CPU time 2.53 seconds
Started Apr 25 03:10:23 PM PDT 24
Finished Apr 25 03:10:26 PM PDT 24
Peak memory 204232 kb
Host smart-498c3694-574f-4000-9fe7-f0ac87cc292b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546823514 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.3546823514
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.277151965
Short name T727
Test name
Test status
Simulation time 1061618550 ps
CPU time 5.24 seconds
Started Apr 25 03:10:13 PM PDT 24
Finished Apr 25 03:10:19 PM PDT 24
Peak memory 212332 kb
Host smart-9590759c-3316-4755-94f4-02d930bf7744
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277151965 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_intr_smoke.277151965
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.3982311937
Short name T239
Test name
Test status
Simulation time 11611551100 ps
CPU time 27.2 seconds
Started Apr 25 03:10:20 PM PDT 24
Finished Apr 25 03:10:48 PM PDT 24
Peak memory 794776 kb
Host smart-1445b4d2-6301-41ee-ad87-96d578391e37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982311937 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.3982311937
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.947480866
Short name T640
Test name
Test status
Simulation time 970589507 ps
CPU time 38.11 seconds
Started Apr 25 03:10:23 PM PDT 24
Finished Apr 25 03:11:02 PM PDT 24
Peak memory 204148 kb
Host smart-96c2070a-9668-4a5f-bcdf-ff59320fddfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947480866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.947480866
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.185203723
Short name T1202
Test name
Test status
Simulation time 9457858853 ps
CPU time 11.63 seconds
Started Apr 25 03:10:16 PM PDT 24
Finished Apr 25 03:10:28 PM PDT 24
Peak memory 206952 kb
Host smart-bbf7c3f6-442d-470b-88f2-c928ec630840
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185203723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_rd.185203723
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.4157313977
Short name T396
Test name
Test status
Simulation time 25539146697 ps
CPU time 17.11 seconds
Started Apr 25 03:10:14 PM PDT 24
Finished Apr 25 03:10:32 PM PDT 24
Peak memory 386204 kb
Host smart-360f1b9a-2abf-47a3-8392-feebdee04423
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157313977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.4157313977
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.4045366907
Short name T909
Test name
Test status
Simulation time 3196663916 ps
CPU time 8.22 seconds
Started Apr 25 03:10:14 PM PDT 24
Finished Apr 25 03:10:23 PM PDT 24
Peak memory 220388 kb
Host smart-20f746eb-4fda-4f2c-9d2e-f1523b80a307
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045366907 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.4045366907
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.3188842927
Short name T400
Test name
Test status
Simulation time 21034406 ps
CPU time 0.66 seconds
Started Apr 25 03:10:34 PM PDT 24
Finished Apr 25 03:10:36 PM PDT 24
Peak memory 203900 kb
Host smart-56efd3b1-1ac4-4a10-bd11-62b0fd2679d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188842927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.3188842927
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.59289496
Short name T1291
Test name
Test status
Simulation time 72557280 ps
CPU time 1.65 seconds
Started Apr 25 03:10:26 PM PDT 24
Finished Apr 25 03:10:29 PM PDT 24
Peak memory 212536 kb
Host smart-0d72bc25-6200-43b5-96cf-ef1ecf62224a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59289496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.59289496
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.68571789
Short name T624
Test name
Test status
Simulation time 147339222 ps
CPU time 3.2 seconds
Started Apr 25 03:10:23 PM PDT 24
Finished Apr 25 03:10:28 PM PDT 24
Peak memory 229288 kb
Host smart-02fea0c5-e676-4a01-8946-d10135c5fd14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68571789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empty
.68571789
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.1482253745
Short name T719
Test name
Test status
Simulation time 1806129500 ps
CPU time 39.4 seconds
Started Apr 25 03:10:25 PM PDT 24
Finished Apr 25 03:11:06 PM PDT 24
Peak memory 374004 kb
Host smart-51126221-5b2e-43b7-95ca-9c065cabb5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482253745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1482253745
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.4095765118
Short name T41
Test name
Test status
Simulation time 1297103129 ps
CPU time 31.96 seconds
Started Apr 25 03:10:24 PM PDT 24
Finished Apr 25 03:10:57 PM PDT 24
Peak memory 513584 kb
Host smart-5be69399-764a-4610-82b8-abf7fc720367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095765118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.4095765118
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.2429870819
Short name T697
Test name
Test status
Simulation time 317988017 ps
CPU time 0.86 seconds
Started Apr 25 03:10:25 PM PDT 24
Finished Apr 25 03:10:27 PM PDT 24
Peak memory 203992 kb
Host smart-9152e9e6-745f-48a4-985b-96e51113563b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429870819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.2429870819
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.3851695423
Short name T861
Test name
Test status
Simulation time 637914293 ps
CPU time 2.87 seconds
Started Apr 25 03:10:27 PM PDT 24
Finished Apr 25 03:10:31 PM PDT 24
Peak memory 204232 kb
Host smart-b7deeaa0-5527-4f82-92ba-7efeeda94355
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851695423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.3851695423
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.3198649538
Short name T1334
Test name
Test status
Simulation time 6394899975 ps
CPU time 67.14 seconds
Started Apr 25 03:10:25 PM PDT 24
Finished Apr 25 03:11:33 PM PDT 24
Peak memory 914660 kb
Host smart-9984f017-6a36-4446-899e-ea6c66279fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198649538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3198649538
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.2453240566
Short name T947
Test name
Test status
Simulation time 512593575 ps
CPU time 10.89 seconds
Started Apr 25 03:10:32 PM PDT 24
Finished Apr 25 03:10:44 PM PDT 24
Peak memory 204144 kb
Host smart-65596b11-9c49-43c0-ae1e-9721bfa0769c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453240566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.2453240566
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.3003160012
Short name T1295
Test name
Test status
Simulation time 1444583777 ps
CPU time 21.19 seconds
Started Apr 25 03:10:32 PM PDT 24
Finished Apr 25 03:10:54 PM PDT 24
Peak memory 293556 kb
Host smart-5dbff41a-56d5-4dc9-b278-ff32b9d297dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003160012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.3003160012
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.356191371
Short name T1180
Test name
Test status
Simulation time 18552486 ps
CPU time 0.66 seconds
Started Apr 25 03:10:20 PM PDT 24
Finished Apr 25 03:10:22 PM PDT 24
Peak memory 203776 kb
Host smart-a9b0416c-ffc6-4f79-a9c0-0ffd946fead3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356191371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.356191371
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.1450128576
Short name T549
Test name
Test status
Simulation time 74397573206 ps
CPU time 901.05 seconds
Started Apr 25 03:10:23 PM PDT 24
Finished Apr 25 03:25:26 PM PDT 24
Peak memory 204316 kb
Host smart-ca3ebdbe-999b-468e-adbb-ae281a6efad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450128576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.1450128576
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.2641705564
Short name T1094
Test name
Test status
Simulation time 1479267154 ps
CPU time 32.11 seconds
Started Apr 25 03:10:19 PM PDT 24
Finished Apr 25 03:10:52 PM PDT 24
Peak memory 423904 kb
Host smart-19326924-b701-4da8-b885-fd64eee442f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641705564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.2641705564
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.2012172654
Short name T680
Test name
Test status
Simulation time 4513537389 ps
CPU time 12.29 seconds
Started Apr 25 03:10:26 PM PDT 24
Finished Apr 25 03:10:39 PM PDT 24
Peak memory 220576 kb
Host smart-f316063d-0d22-4d7e-ab26-c87a62b3b63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012172654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.2012172654
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.688572136
Short name T1325
Test name
Test status
Simulation time 805616686 ps
CPU time 4 seconds
Started Apr 25 03:10:29 PM PDT 24
Finished Apr 25 03:10:33 PM PDT 24
Peak memory 212356 kb
Host smart-76f68885-6169-4f6d-859b-7a14dad01145
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688572136 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.688572136
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.701463323
Short name T456
Test name
Test status
Simulation time 10031542411 ps
CPU time 87.7 seconds
Started Apr 25 03:10:32 PM PDT 24
Finished Apr 25 03:12:00 PM PDT 24
Peak memory 464016 kb
Host smart-61ab1b4c-37f8-4197-b191-0a279092b7aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701463323 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_acq.701463323
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.4136405870
Short name T712
Test name
Test status
Simulation time 10151963518 ps
CPU time 29.15 seconds
Started Apr 25 03:10:31 PM PDT 24
Finished Apr 25 03:11:01 PM PDT 24
Peak memory 345124 kb
Host smart-33c1bca6-3b2b-4d05-9d97-961306a37338
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136405870 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.4136405870
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.783650894
Short name T205
Test name
Test status
Simulation time 1617093509 ps
CPU time 2.5 seconds
Started Apr 25 03:10:30 PM PDT 24
Finished Apr 25 03:10:33 PM PDT 24
Peak memory 204156 kb
Host smart-f9c63da4-581b-44bb-b71d-67c351ab54d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783650894 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.i2c_target_hrst.783650894
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.2197398675
Short name T1153
Test name
Test status
Simulation time 774564697 ps
CPU time 3.8 seconds
Started Apr 25 03:10:33 PM PDT 24
Finished Apr 25 03:10:37 PM PDT 24
Peak memory 204180 kb
Host smart-2d514481-89ac-401f-b0c4-ee5a63aa8185
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197398675 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.2197398675
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.141929669
Short name T296
Test name
Test status
Simulation time 2520289453 ps
CPU time 5.7 seconds
Started Apr 25 03:10:33 PM PDT 24
Finished Apr 25 03:10:40 PM PDT 24
Peak memory 204264 kb
Host smart-0b2119e3-8b03-4033-bce9-ad632ebec73d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141929669 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.141929669
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2030491191
Short name T105
Test name
Test status
Simulation time 4247132446 ps
CPU time 40.49 seconds
Started Apr 25 03:10:25 PM PDT 24
Finished Apr 25 03:11:07 PM PDT 24
Peak memory 204244 kb
Host smart-004d11fc-8398-4d02-947e-fe789cf26a3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030491191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2030491191
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2806215831
Short name T263
Test name
Test status
Simulation time 1055832525 ps
CPU time 32.19 seconds
Started Apr 25 03:10:28 PM PDT 24
Finished Apr 25 03:11:01 PM PDT 24
Peak memory 204096 kb
Host smart-c2ccbfb8-dfa6-4844-80d3-b4b370b3071b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806215831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2806215831
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.1856577505
Short name T827
Test name
Test status
Simulation time 41434729719 ps
CPU time 240.79 seconds
Started Apr 25 03:10:26 PM PDT 24
Finished Apr 25 03:14:28 PM PDT 24
Peak memory 2663776 kb
Host smart-1c74124a-64c1-4c91-826a-697fad4f9041
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856577505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.1856577505
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.2444178564
Short name T1317
Test name
Test status
Simulation time 5435286710 ps
CPU time 76.53 seconds
Started Apr 25 03:10:42 PM PDT 24
Finished Apr 25 03:12:00 PM PDT 24
Peak memory 496556 kb
Host smart-f9d058e0-5450-4439-984e-3042d6917473
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444178564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.2444178564
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_alert_test.2952188416
Short name T9
Test name
Test status
Simulation time 48354100 ps
CPU time 0.63 seconds
Started Apr 25 03:10:46 PM PDT 24
Finished Apr 25 03:10:48 PM PDT 24
Peak memory 203876 kb
Host smart-a856ebd9-8aee-4ffa-9cb7-eda5fd393303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952188416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.2952188416
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.1177924683
Short name T1240
Test name
Test status
Simulation time 195455957 ps
CPU time 1.63 seconds
Started Apr 25 03:10:36 PM PDT 24
Finished Apr 25 03:10:39 PM PDT 24
Peak memory 212380 kb
Host smart-37a0315e-faca-41e1-a05a-27e5be8cfbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177924683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.1177924683
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3373052215
Short name T293
Test name
Test status
Simulation time 260813279 ps
CPU time 4.64 seconds
Started Apr 25 03:10:35 PM PDT 24
Finished Apr 25 03:10:41 PM PDT 24
Peak memory 255248 kb
Host smart-9209849d-fedf-482a-b6a6-a47396b7be33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373052215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.3373052215
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.1266787992
Short name T714
Test name
Test status
Simulation time 1877657003 ps
CPU time 68.14 seconds
Started Apr 25 03:10:35 PM PDT 24
Finished Apr 25 03:11:45 PM PDT 24
Peak memory 659408 kb
Host smart-d06b81b0-e12b-4b50-931f-5c99933806a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266787992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.1266787992
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.933623681
Short name T830
Test name
Test status
Simulation time 2133247626 ps
CPU time 67.71 seconds
Started Apr 25 03:10:35 PM PDT 24
Finished Apr 25 03:11:44 PM PDT 24
Peak memory 461628 kb
Host smart-cf3383ce-683c-46a5-86d0-ccdb03286556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933623681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.933623681
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.3485790255
Short name T70
Test name
Test status
Simulation time 1862776986 ps
CPU time 0.96 seconds
Started Apr 25 03:10:37 PM PDT 24
Finished Apr 25 03:10:39 PM PDT 24
Peak memory 203968 kb
Host smart-c84372d5-3888-4d72-8a07-523f0b4f92cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485790255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.3485790255
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.3386054299
Short name T88
Test name
Test status
Simulation time 633480094 ps
CPU time 7.47 seconds
Started Apr 25 03:10:37 PM PDT 24
Finished Apr 25 03:10:45 PM PDT 24
Peak memory 204208 kb
Host smart-14f00c71-275a-450d-93f7-cc9dee00629e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386054299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.3386054299
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.4039187510
Short name T190
Test name
Test status
Simulation time 261648009 ps
CPU time 4.23 seconds
Started Apr 25 03:10:41 PM PDT 24
Finished Apr 25 03:10:46 PM PDT 24
Peak memory 204236 kb
Host smart-d062a8d6-ee9a-4bb0-813d-096a2c1b2294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039187510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.4039187510
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.1527684191
Short name T1316
Test name
Test status
Simulation time 10772658150 ps
CPU time 66.03 seconds
Started Apr 25 03:10:48 PM PDT 24
Finished Apr 25 03:11:56 PM PDT 24
Peak memory 385944 kb
Host smart-49b7ae4f-df90-4f5d-9dc7-4bf0a4b58908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527684191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.1527684191
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.4168244302
Short name T1310
Test name
Test status
Simulation time 42507468 ps
CPU time 0.65 seconds
Started Apr 25 03:10:38 PM PDT 24
Finished Apr 25 03:10:40 PM PDT 24
Peak memory 203856 kb
Host smart-4753d387-8082-41c7-9cb4-c3c706b3162e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168244302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.4168244302
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.1899439098
Short name T950
Test name
Test status
Simulation time 5287403971 ps
CPU time 149.02 seconds
Started Apr 25 03:10:37 PM PDT 24
Finished Apr 25 03:13:07 PM PDT 24
Peak memory 549956 kb
Host smart-54a9f6a1-f21e-48b6-9103-23ef0d18fce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899439098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.1899439098
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.3279784682
Short name T572
Test name
Test status
Simulation time 1256679320 ps
CPU time 27.19 seconds
Started Apr 25 03:10:38 PM PDT 24
Finished Apr 25 03:11:06 PM PDT 24
Peak memory 326652 kb
Host smart-b0fd2289-529a-4d8c-bfb3-8d482a2ce5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279784682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.3279784682
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.4180617042
Short name T98
Test name
Test status
Simulation time 15745349262 ps
CPU time 512.67 seconds
Started Apr 25 03:10:35 PM PDT 24
Finished Apr 25 03:19:09 PM PDT 24
Peak memory 1101360 kb
Host smart-88d5ef68-4623-434a-beb6-8249ff748a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180617042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.4180617042
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.3645865065
Short name T559
Test name
Test status
Simulation time 3609721522 ps
CPU time 12.17 seconds
Started Apr 25 03:10:34 PM PDT 24
Finished Apr 25 03:10:48 PM PDT 24
Peak memory 220548 kb
Host smart-44ecddac-7396-4dab-8587-b2edff9e4686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645865065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3645865065
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.3380790869
Short name T1197
Test name
Test status
Simulation time 408770093 ps
CPU time 2.38 seconds
Started Apr 25 03:10:42 PM PDT 24
Finished Apr 25 03:10:46 PM PDT 24
Peak memory 204172 kb
Host smart-c58407ed-99d0-498e-baeb-2c597138cf18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380790869 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.3380790869
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.1359327028
Short name T18
Test name
Test status
Simulation time 10031967056 ps
CPU time 82.54 seconds
Started Apr 25 03:10:41 PM PDT 24
Finished Apr 25 03:12:05 PM PDT 24
Peak memory 604440 kb
Host smart-9f3cb1da-8c18-468b-b379-0dc026b5cfa8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359327028 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.1359327028
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.2522366865
Short name T412
Test name
Test status
Simulation time 1103086458 ps
CPU time 2.62 seconds
Started Apr 25 03:10:44 PM PDT 24
Finished Apr 25 03:10:49 PM PDT 24
Peak memory 204208 kb
Host smart-743b347b-b2c5-480a-b98f-ee7db23c605b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522366865 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.2522366865
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.892231801
Short name T939
Test name
Test status
Simulation time 4787157164 ps
CPU time 4.56 seconds
Started Apr 25 03:10:35 PM PDT 24
Finished Apr 25 03:10:41 PM PDT 24
Peak memory 204508 kb
Host smart-a36dcd45-79b0-46c1-8b9a-cedd658271a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892231801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_intr_smoke.892231801
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.3030565264
Short name T201
Test name
Test status
Simulation time 23679655749 ps
CPU time 549.41 seconds
Started Apr 25 03:10:38 PM PDT 24
Finished Apr 25 03:19:48 PM PDT 24
Peak memory 5789120 kb
Host smart-ddc80e2c-37bb-4035-8392-c60f5448d66f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030565264 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.3030565264
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.2188919872
Short name T1242
Test name
Test status
Simulation time 3677256958 ps
CPU time 43.86 seconds
Started Apr 25 03:10:35 PM PDT 24
Finished Apr 25 03:11:21 PM PDT 24
Peak memory 204216 kb
Host smart-b7145f5b-2316-4c1a-83a5-dbf63a52003b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188919872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.2188919872
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.2137522647
Short name T965
Test name
Test status
Simulation time 1457643811 ps
CPU time 31.24 seconds
Started Apr 25 03:10:35 PM PDT 24
Finished Apr 25 03:11:08 PM PDT 24
Peak memory 204136 kb
Host smart-abf8816f-2cd9-41ac-be49-10185450f0eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137522647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.2137522647
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.3297472155
Short name T307
Test name
Test status
Simulation time 10859173960 ps
CPU time 22.67 seconds
Started Apr 25 03:10:35 PM PDT 24
Finished Apr 25 03:10:59 PM PDT 24
Peak memory 204208 kb
Host smart-1d07f27b-923d-4e05-a965-ce64bb2271b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297472155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.3297472155
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.2887334962
Short name T471
Test name
Test status
Simulation time 5256330500 ps
CPU time 19.85 seconds
Started Apr 25 03:10:35 PM PDT 24
Finished Apr 25 03:10:57 PM PDT 24
Peak memory 436600 kb
Host smart-d52e4656-d52c-4715-af40-26910e79d9cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887334962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.2887334962
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2412811914
Short name T601
Test name
Test status
Simulation time 2424558333 ps
CPU time 7.74 seconds
Started Apr 25 03:10:34 PM PDT 24
Finished Apr 25 03:10:44 PM PDT 24
Peak memory 213560 kb
Host smart-bc77c8c5-9738-432e-ad51-0d0d21d1f39d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412811914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2412811914
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_unexp_stop.784999110
Short name T718
Test name
Test status
Simulation time 1518799279 ps
CPU time 8.39 seconds
Started Apr 25 03:10:45 PM PDT 24
Finished Apr 25 03:10:55 PM PDT 24
Peak memory 212412 kb
Host smart-1ddd6fb4-2847-40e5-aaf3-2bd1831d4a6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784999110 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_unexp_stop.784999110
Directory /workspace/24.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/25.i2c_alert_test.1429359090
Short name T56
Test name
Test status
Simulation time 17197636 ps
CPU time 0.61 seconds
Started Apr 25 03:10:57 PM PDT 24
Finished Apr 25 03:10:59 PM PDT 24
Peak memory 203816 kb
Host smart-1a6d9fbc-e1a7-430a-b1b4-009282a0cec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429359090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1429359090
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.2807695360
Short name T706
Test name
Test status
Simulation time 207920290 ps
CPU time 1.9 seconds
Started Apr 25 03:10:48 PM PDT 24
Finished Apr 25 03:10:51 PM PDT 24
Peak memory 216156 kb
Host smart-2a2f81ad-baf9-4311-b39c-848958887092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807695360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.2807695360
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2157845041
Short name T968
Test name
Test status
Simulation time 275219203 ps
CPU time 5.9 seconds
Started Apr 25 03:10:48 PM PDT 24
Finished Apr 25 03:10:55 PM PDT 24
Peak memory 250720 kb
Host smart-95198cc5-984f-4955-ad87-93cef7bb1651
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157845041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2157845041
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.2599665743
Short name T1008
Test name
Test status
Simulation time 8744858109 ps
CPU time 160.35 seconds
Started Apr 25 03:10:48 PM PDT 24
Finished Apr 25 03:13:30 PM PDT 24
Peak memory 729068 kb
Host smart-d4ba5910-86bf-4656-9e1c-a1c7371456a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599665743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.2599665743
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.2646128822
Short name T881
Test name
Test status
Simulation time 1505197454 ps
CPU time 36.76 seconds
Started Apr 25 03:10:50 PM PDT 24
Finished Apr 25 03:11:28 PM PDT 24
Peak memory 479428 kb
Host smart-dd9bda9a-a587-435f-b989-7a2fda505885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646128822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.2646128822
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.4006676936
Short name T324
Test name
Test status
Simulation time 488832607 ps
CPU time 1.15 seconds
Started Apr 25 03:10:47 PM PDT 24
Finished Apr 25 03:10:50 PM PDT 24
Peak memory 204204 kb
Host smart-4a10a094-d337-4e5c-87cb-d92aed27fee6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006676936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.4006676936
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.1416796335
Short name T414
Test name
Test status
Simulation time 763717265 ps
CPU time 4.35 seconds
Started Apr 25 03:10:48 PM PDT 24
Finished Apr 25 03:10:54 PM PDT 24
Peak memory 204128 kb
Host smart-3b9dee25-ca29-43a5-bfde-ff217ce02037
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416796335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.1416796335
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.2662723321
Short name T161
Test name
Test status
Simulation time 7576283126 ps
CPU time 87.07 seconds
Started Apr 25 03:10:49 PM PDT 24
Finished Apr 25 03:12:18 PM PDT 24
Peak memory 1088720 kb
Host smart-a5bf0ae7-bc26-439e-bca0-b9419ae63598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662723321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.2662723321
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.791599494
Short name T194
Test name
Test status
Simulation time 1136106741 ps
CPU time 4.97 seconds
Started Apr 25 03:10:55 PM PDT 24
Finished Apr 25 03:11:01 PM PDT 24
Peak memory 204188 kb
Host smart-508d5baa-b9b2-4036-a0c2-fd40033cde23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791599494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.791599494
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_override.2393390380
Short name T843
Test name
Test status
Simulation time 26636355 ps
CPU time 0.64 seconds
Started Apr 25 03:10:49 PM PDT 24
Finished Apr 25 03:10:51 PM PDT 24
Peak memory 203792 kb
Host smart-03430882-3a12-402e-b8ae-e45e2441445c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393390380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.2393390380
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.2368929481
Short name T700
Test name
Test status
Simulation time 839161054 ps
CPU time 11.56 seconds
Started Apr 25 03:10:48 PM PDT 24
Finished Apr 25 03:11:01 PM PDT 24
Peak memory 230544 kb
Host smart-b78697fb-f4c6-417b-abc3-96d67e47f5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368929481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.2368929481
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.5677722
Short name T977
Test name
Test status
Simulation time 3455127622 ps
CPU time 96.91 seconds
Started Apr 25 03:10:47 PM PDT 24
Finished Apr 25 03:12:25 PM PDT 24
Peak memory 415044 kb
Host smart-5908c293-4f2a-4a30-a799-a5e17a3c5075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5677722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.5677722
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.3937621757
Short name T1344
Test name
Test status
Simulation time 19938785468 ps
CPU time 1450.26 seconds
Started Apr 25 03:10:51 PM PDT 24
Finished Apr 25 03:35:02 PM PDT 24
Peak memory 4378276 kb
Host smart-8f280a0d-2488-4fc7-a93a-e76dcc80989e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937621757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.3937621757
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.3055843438
Short name T342
Test name
Test status
Simulation time 465835174 ps
CPU time 7.62 seconds
Started Apr 25 03:10:57 PM PDT 24
Finished Apr 25 03:11:06 PM PDT 24
Peak memory 214144 kb
Host smart-153d2542-4a99-40a4-8d6b-7e4549ee0818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055843438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.3055843438
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.121268245
Short name T26
Test name
Test status
Simulation time 1543868593 ps
CPU time 3.77 seconds
Started Apr 25 03:10:53 PM PDT 24
Finished Apr 25 03:10:57 PM PDT 24
Peak memory 212324 kb
Host smart-16b90f07-1002-48f0-a6d8-817c2ff8b523
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121268245 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.121268245
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3763571916
Short name T419
Test name
Test status
Simulation time 10038646924 ps
CPU time 67.59 seconds
Started Apr 25 03:10:54 PM PDT 24
Finished Apr 25 03:12:02 PM PDT 24
Peak memory 433568 kb
Host smart-2a534f6c-ba3b-4c2f-8805-92bb57054605
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763571916 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3763571916
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.2646206196
Short name T851
Test name
Test status
Simulation time 474789589 ps
CPU time 2.83 seconds
Started Apr 25 03:10:54 PM PDT 24
Finished Apr 25 03:10:57 PM PDT 24
Peak memory 204200 kb
Host smart-65220d94-885a-4399-a3de-01419dd3fb0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646206196 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.2646206196
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.712731984
Short name T763
Test name
Test status
Simulation time 1375713676 ps
CPU time 5.25 seconds
Started Apr 25 03:10:48 PM PDT 24
Finished Apr 25 03:10:55 PM PDT 24
Peak memory 204140 kb
Host smart-de0afd44-e69a-41a4-bda5-60fe7adebd5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712731984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_intr_smoke.712731984
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.2591917394
Short name T1231
Test name
Test status
Simulation time 12195374094 ps
CPU time 111.96 seconds
Started Apr 25 03:10:48 PM PDT 24
Finished Apr 25 03:12:42 PM PDT 24
Peak memory 1461968 kb
Host smart-5099e283-22af-425f-bb33-92309e929845
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591917394 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.2591917394
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.2114363618
Short name T998
Test name
Test status
Simulation time 6111769617 ps
CPU time 17.34 seconds
Started Apr 25 03:10:48 PM PDT 24
Finished Apr 25 03:11:06 PM PDT 24
Peak memory 204204 kb
Host smart-bd97bcb8-82ca-4fd2-9ce6-d18a1836b2fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114363618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.2114363618
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.4186885040
Short name T684
Test name
Test status
Simulation time 1444053192 ps
CPU time 25.68 seconds
Started Apr 25 03:10:49 PM PDT 24
Finished Apr 25 03:11:16 PM PDT 24
Peak memory 226408 kb
Host smart-903b6eaa-6dbf-41ec-a4f7-1a501ec1434d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186885040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.4186885040
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.299976696
Short name T1322
Test name
Test status
Simulation time 69974280434 ps
CPU time 919.97 seconds
Started Apr 25 03:10:47 PM PDT 24
Finished Apr 25 03:26:08 PM PDT 24
Peak memory 6345876 kb
Host smart-e1b66500-22dc-4ddb-9912-b24e661a2eda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299976696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_wr.299976696
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.3413118733
Short name T758
Test name
Test status
Simulation time 10191798861 ps
CPU time 1276.54 seconds
Started Apr 25 03:10:46 PM PDT 24
Finished Apr 25 03:32:04 PM PDT 24
Peak memory 2614256 kb
Host smart-81c0d098-759e-43bf-aba4-4cbc1cc409cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413118733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.3413118733
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.783615904
Short name T273
Test name
Test status
Simulation time 1219264435 ps
CPU time 6.73 seconds
Started Apr 25 03:10:48 PM PDT 24
Finished Apr 25 03:10:56 PM PDT 24
Peak memory 217608 kb
Host smart-9b8729ad-a6a8-443e-8a2c-035484d61e1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783615904 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_timeout.783615904
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.3346638371
Short name T336
Test name
Test status
Simulation time 72167266 ps
CPU time 0.62 seconds
Started Apr 25 03:11:04 PM PDT 24
Finished Apr 25 03:11:06 PM PDT 24
Peak memory 203912 kb
Host smart-f4dae0aa-aa6a-4dc0-ba0f-33df2f49adb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346638371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.3346638371
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.2857539612
Short name T1220
Test name
Test status
Simulation time 224110635 ps
CPU time 2.1 seconds
Started Apr 25 03:10:58 PM PDT 24
Finished Apr 25 03:11:01 PM PDT 24
Peak memory 212400 kb
Host smart-f7298044-4d46-428d-aefe-0c7582fae829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857539612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.2857539612
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.134096283
Short name T279
Test name
Test status
Simulation time 393449161 ps
CPU time 21.87 seconds
Started Apr 25 03:10:59 PM PDT 24
Finished Apr 25 03:11:23 PM PDT 24
Peak memory 289492 kb
Host smart-3eaf2017-331e-4fac-86a1-e60bd281c999
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134096283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empt
y.134096283
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2802970653
Short name T1318
Test name
Test status
Simulation time 4439888634 ps
CPU time 169.92 seconds
Started Apr 25 03:11:02 PM PDT 24
Finished Apr 25 03:13:54 PM PDT 24
Peak memory 733516 kb
Host smart-725987e2-97b7-4c81-9319-49c198ba213a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802970653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2802970653
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.3335148641
Short name T568
Test name
Test status
Simulation time 5848593911 ps
CPU time 35.63 seconds
Started Apr 25 03:11:00 PM PDT 24
Finished Apr 25 03:11:37 PM PDT 24
Peak memory 511532 kb
Host smart-0ec14e4a-5fee-4644-8820-a26f1a611d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335148641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.3335148641
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.1464478376
Short name T1289
Test name
Test status
Simulation time 129612743 ps
CPU time 0.96 seconds
Started Apr 25 03:11:02 PM PDT 24
Finished Apr 25 03:11:05 PM PDT 24
Peak memory 203960 kb
Host smart-66af5784-0684-4685-a206-192e2c33b54d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464478376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.1464478376
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.1723840173
Short name T615
Test name
Test status
Simulation time 115877847 ps
CPU time 2.88 seconds
Started Apr 25 03:11:07 PM PDT 24
Finished Apr 25 03:11:10 PM PDT 24
Peak memory 204108 kb
Host smart-f350151a-43a6-4eae-9668-4e02d4aca013
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723840173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.1723840173
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.3603381004
Short name T1221
Test name
Test status
Simulation time 3242896469 ps
CPU time 86.35 seconds
Started Apr 25 03:10:58 PM PDT 24
Finished Apr 25 03:12:26 PM PDT 24
Peak memory 978580 kb
Host smart-7939c5ef-b1ce-465f-b01c-f5f9136f320c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603381004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.3603381004
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.602639695
Short name T740
Test name
Test status
Simulation time 423005876 ps
CPU time 14.53 seconds
Started Apr 25 03:11:02 PM PDT 24
Finished Apr 25 03:11:18 PM PDT 24
Peak memory 204160 kb
Host smart-13098e61-e128-4147-8e39-10888a9d1c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602639695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.602639695
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_perf.3817667416
Short name T852
Test name
Test status
Simulation time 5235704889 ps
CPU time 106.03 seconds
Started Apr 25 03:11:00 PM PDT 24
Finished Apr 25 03:12:48 PM PDT 24
Peak memory 617008 kb
Host smart-0d8c5328-9daf-4b32-91de-3bb63c1539d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817667416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.3817667416
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1858864884
Short name T611
Test name
Test status
Simulation time 1250682574 ps
CPU time 63.47 seconds
Started Apr 25 03:10:57 PM PDT 24
Finished Apr 25 03:12:02 PM PDT 24
Peak memory 350296 kb
Host smart-75b46245-da11-4db3-807d-e2f4af3fbb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858864884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1858864884
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.2395938269
Short name T164
Test name
Test status
Simulation time 34974167312 ps
CPU time 478.78 seconds
Started Apr 25 03:11:00 PM PDT 24
Finished Apr 25 03:19:01 PM PDT 24
Peak memory 1639664 kb
Host smart-b7907336-617c-4cd8-9790-bf1813258554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395938269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.2395938269
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.3727485032
Short name T10
Test name
Test status
Simulation time 1600504465 ps
CPU time 34.81 seconds
Started Apr 25 03:11:02 PM PDT 24
Finished Apr 25 03:11:39 PM PDT 24
Peak memory 212292 kb
Host smart-eed456b6-ed81-4261-b0bb-530be349d674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727485032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3727485032
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.483439277
Short name T1303
Test name
Test status
Simulation time 1843411629 ps
CPU time 2.56 seconds
Started Apr 25 03:11:02 PM PDT 24
Finished Apr 25 03:11:07 PM PDT 24
Peak memory 204212 kb
Host smart-8335e4e1-ae5e-4436-b281-876a78961330
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483439277 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.483439277
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.1529398035
Short name T956
Test name
Test status
Simulation time 10209485311 ps
CPU time 14.73 seconds
Started Apr 25 03:11:00 PM PDT 24
Finished Apr 25 03:11:16 PM PDT 24
Peak memory 298240 kb
Host smart-d5c15b5a-394d-4335-9877-450ef737cca5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529398035 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.1529398035
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.990940005
Short name T528
Test name
Test status
Simulation time 10614872153 ps
CPU time 14.68 seconds
Started Apr 25 03:10:59 PM PDT 24
Finished Apr 25 03:11:16 PM PDT 24
Peak memory 273932 kb
Host smart-cabedfb0-89bc-4ba0-9434-cbe06a5a33e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990940005 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_fifo_reset_tx.990940005
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.2304610515
Short name T519
Test name
Test status
Simulation time 353895604 ps
CPU time 2.14 seconds
Started Apr 25 03:11:03 PM PDT 24
Finished Apr 25 03:11:07 PM PDT 24
Peak memory 204224 kb
Host smart-d8dcfcd4-0e00-46a1-be3a-049e77e56674
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304610515 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.2304610515
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.3383564883
Short name T1110
Test name
Test status
Simulation time 1437552404 ps
CPU time 4.31 seconds
Started Apr 25 03:11:02 PM PDT 24
Finished Apr 25 03:11:08 PM PDT 24
Peak memory 206060 kb
Host smart-43f8e886-06ed-461c-b45e-bb6176651385
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383564883 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.3383564883
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.1207774254
Short name T654
Test name
Test status
Simulation time 19260132008 ps
CPU time 410.88 seconds
Started Apr 25 03:10:57 PM PDT 24
Finished Apr 25 03:17:49 PM PDT 24
Peak memory 4666168 kb
Host smart-9532f1e6-6f2d-411d-851b-cc49041aec80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207774254 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.1207774254
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.943715948
Short name T936
Test name
Test status
Simulation time 1642192220 ps
CPU time 22.83 seconds
Started Apr 25 03:11:00 PM PDT 24
Finished Apr 25 03:11:24 PM PDT 24
Peak memory 204108 kb
Host smart-49ba6537-c892-4f42-be5a-6dc329b4bab9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943715948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_tar
get_smoke.943715948
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.258631692
Short name T937
Test name
Test status
Simulation time 888721823 ps
CPU time 18.9 seconds
Started Apr 25 03:10:59 PM PDT 24
Finished Apr 25 03:11:20 PM PDT 24
Peak memory 204072 kb
Host smart-69e62b82-ef33-4fce-a0c2-acd666e8ec3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258631692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_rd.258631692
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.254499158
Short name T382
Test name
Test status
Simulation time 24642952144 ps
CPU time 78.03 seconds
Started Apr 25 03:11:00 PM PDT 24
Finished Apr 25 03:12:20 PM PDT 24
Peak memory 1106840 kb
Host smart-d0308a02-6d03-492d-a4b0-75807ba8d7e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254499158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_wr.254499158
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.790449994
Short name T619
Test name
Test status
Simulation time 14586982612 ps
CPU time 114.78 seconds
Started Apr 25 03:10:57 PM PDT 24
Finished Apr 25 03:12:53 PM PDT 24
Peak memory 590484 kb
Host smart-0b524acd-18ce-45ab-b22c-8a3fb7ca0eda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790449994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_t
arget_stretch.790449994
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.3421870628
Short name T540
Test name
Test status
Simulation time 4874693098 ps
CPU time 6.53 seconds
Started Apr 25 03:10:58 PM PDT 24
Finished Apr 25 03:11:06 PM PDT 24
Peak memory 212476 kb
Host smart-e38fdcc1-5e18-4de2-8b48-cacacc002e85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421870628 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.3421870628
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.463671246
Short name T94
Test name
Test status
Simulation time 108702882 ps
CPU time 0.61 seconds
Started Apr 25 03:11:13 PM PDT 24
Finished Apr 25 03:11:14 PM PDT 24
Peak memory 203876 kb
Host smart-fab54191-a110-4f2a-aacf-6f01c2ee6c29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463671246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.463671246
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.1973747266
Short name T592
Test name
Test status
Simulation time 67442607 ps
CPU time 1.3 seconds
Started Apr 25 03:11:15 PM PDT 24
Finished Apr 25 03:11:18 PM PDT 24
Peak memory 212348 kb
Host smart-104f4f03-e678-45de-a80a-acd5a3ad0fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973747266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.1973747266
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.2317521757
Short name T166
Test name
Test status
Simulation time 1058412615 ps
CPU time 10.35 seconds
Started Apr 25 03:11:06 PM PDT 24
Finished Apr 25 03:11:17 PM PDT 24
Peak memory 239432 kb
Host smart-5fd649fd-0936-4475-9fae-13cc4756ba0b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317521757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.2317521757
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.2419372517
Short name T1227
Test name
Test status
Simulation time 7336988897 ps
CPU time 46.43 seconds
Started Apr 25 03:11:11 PM PDT 24
Finished Apr 25 03:11:58 PM PDT 24
Peak memory 568772 kb
Host smart-79b0e4c9-cead-485a-a9f2-62f9422c7fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419372517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.2419372517
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.1483293193
Short name T1025
Test name
Test status
Simulation time 1233769336 ps
CPU time 35.3 seconds
Started Apr 25 03:11:02 PM PDT 24
Finished Apr 25 03:11:39 PM PDT 24
Peak memory 446644 kb
Host smart-4d8756f7-b53b-4d7c-9e9b-c5838bf47d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483293193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.1483293193
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2792291921
Short name T1108
Test name
Test status
Simulation time 298259194 ps
CPU time 1.21 seconds
Started Apr 25 03:11:04 PM PDT 24
Finished Apr 25 03:11:07 PM PDT 24
Peak memory 204180 kb
Host smart-038d08f5-c492-4151-8c81-f73d4453d505
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792291921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.2792291921
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.1644775141
Short name T713
Test name
Test status
Simulation time 633293680 ps
CPU time 3.74 seconds
Started Apr 25 03:11:09 PM PDT 24
Finished Apr 25 03:11:14 PM PDT 24
Peak memory 204140 kb
Host smart-1505f09f-3704-45d5-8c28-8e225ecb573e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644775141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.1644775141
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.703662767
Short name T682
Test name
Test status
Simulation time 37546814402 ps
CPU time 244.75 seconds
Started Apr 25 03:11:04 PM PDT 24
Finished Apr 25 03:15:10 PM PDT 24
Peak memory 959108 kb
Host smart-4c35a255-a270-4506-b279-8401ec129a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703662767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.703662767
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.2282164895
Short name T1228
Test name
Test status
Simulation time 431819426 ps
CPU time 4.74 seconds
Started Apr 25 03:11:14 PM PDT 24
Finished Apr 25 03:11:20 PM PDT 24
Peak memory 204164 kb
Host smart-93694756-e818-4391-a4ff-8b157bcc6fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282164895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2282164895
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.53642191
Short name T662
Test name
Test status
Simulation time 6440498610 ps
CPU time 29.43 seconds
Started Apr 25 03:11:13 PM PDT 24
Finished Apr 25 03:11:43 PM PDT 24
Peak memory 339164 kb
Host smart-3657425c-25e1-42c4-a633-d27b8ce35c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53642191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.53642191
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.1280858556
Short name T463
Test name
Test status
Simulation time 127645484 ps
CPU time 0.67 seconds
Started Apr 25 03:11:03 PM PDT 24
Finished Apr 25 03:11:05 PM PDT 24
Peak memory 203832 kb
Host smart-00cc829f-834f-4579-977b-30ce4d3251a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280858556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.1280858556
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.1486105663
Short name T1213
Test name
Test status
Simulation time 6218499331 ps
CPU time 265.22 seconds
Started Apr 25 03:11:11 PM PDT 24
Finished Apr 25 03:15:37 PM PDT 24
Peak memory 212484 kb
Host smart-62f84aa2-de5c-4ac9-b25f-00d5e0b9c360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486105663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.1486105663
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.389432317
Short name T588
Test name
Test status
Simulation time 986842812 ps
CPU time 50.2 seconds
Started Apr 25 03:11:03 PM PDT 24
Finished Apr 25 03:11:55 PM PDT 24
Peak memory 326972 kb
Host smart-a7bee6a1-e071-44a6-b6cb-f35160edc313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389432317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.389432317
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.2807422596
Short name T525
Test name
Test status
Simulation time 12962863482 ps
CPU time 834.12 seconds
Started Apr 25 03:11:08 PM PDT 24
Finished Apr 25 03:25:03 PM PDT 24
Peak memory 2330916 kb
Host smart-6553db95-f5ea-49d2-a4af-e54207ca373f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807422596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.2807422596
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.1699888070
Short name T864
Test name
Test status
Simulation time 278732746 ps
CPU time 11.88 seconds
Started Apr 25 03:11:09 PM PDT 24
Finished Apr 25 03:11:23 PM PDT 24
Peak memory 212288 kb
Host smart-dd5d2eae-dbfc-482d-9dbd-e7ea316c8dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699888070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.1699888070
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.3409283014
Short name T1292
Test name
Test status
Simulation time 540521160 ps
CPU time 3.25 seconds
Started Apr 25 03:11:08 PM PDT 24
Finished Apr 25 03:11:13 PM PDT 24
Peak memory 204132 kb
Host smart-9ed7daf0-1407-49ac-952a-d420d6290d0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409283014 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.3409283014
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.2658101164
Short name T1328
Test name
Test status
Simulation time 10099830324 ps
CPU time 62.18 seconds
Started Apr 25 03:11:09 PM PDT 24
Finished Apr 25 03:12:13 PM PDT 24
Peak memory 473708 kb
Host smart-d84a8566-23dc-4b7c-81f3-59261f9fe441
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658101164 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.2658101164
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.4161262093
Short name T1160
Test name
Test status
Simulation time 10035575672 ps
CPU time 65.61 seconds
Started Apr 25 03:11:10 PM PDT 24
Finished Apr 25 03:12:17 PM PDT 24
Peak memory 525788 kb
Host smart-ea06552f-51a8-4b2e-a48d-f77cc859caac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161262093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.4161262093
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.3746880463
Short name T5
Test name
Test status
Simulation time 2140878451 ps
CPU time 2.45 seconds
Started Apr 25 03:11:16 PM PDT 24
Finished Apr 25 03:11:19 PM PDT 24
Peak memory 204188 kb
Host smart-8c3bd129-5d17-4f76-8a3b-275ce7ca09d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746880463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.3746880463
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.2224413324
Short name T1333
Test name
Test status
Simulation time 13317786804 ps
CPU time 6.71 seconds
Started Apr 25 03:11:09 PM PDT 24
Finished Apr 25 03:11:16 PM PDT 24
Peak memory 212500 kb
Host smart-96d0eafd-4b5d-49bf-89dc-9fdd18558fcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224413324 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.2224413324
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.4064925268
Short name T1089
Test name
Test status
Simulation time 7645264327 ps
CPU time 4.91 seconds
Started Apr 25 03:11:10 PM PDT 24
Finished Apr 25 03:11:16 PM PDT 24
Peak memory 204244 kb
Host smart-ad072e5a-c78c-4be4-8ffd-183eedfae4ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064925268 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.4064925268
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.3611215095
Short name T34
Test name
Test status
Simulation time 3915989580 ps
CPU time 11.48 seconds
Started Apr 25 03:11:10 PM PDT 24
Finished Apr 25 03:11:23 PM PDT 24
Peak memory 204232 kb
Host smart-5705097c-f1cb-4238-89e1-0c8faac6a754
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611215095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.3611215095
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.2520937999
Short name T280
Test name
Test status
Simulation time 419769556 ps
CPU time 7.58 seconds
Started Apr 25 03:11:11 PM PDT 24
Finished Apr 25 03:11:20 PM PDT 24
Peak memory 204216 kb
Host smart-7b552d9b-2830-47fe-affe-8c1e9f9ea174
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520937999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.2520937999
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.1948512945
Short name T23
Test name
Test status
Simulation time 30194405523 ps
CPU time 87.95 seconds
Started Apr 25 03:11:09 PM PDT 24
Finished Apr 25 03:12:39 PM PDT 24
Peak memory 1312540 kb
Host smart-d02103d9-8b17-46f6-b2e2-1809d41fef73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948512945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.1948512945
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.2399884853
Short name T33
Test name
Test status
Simulation time 11654705902 ps
CPU time 141.4 seconds
Started Apr 25 03:11:10 PM PDT 24
Finished Apr 25 03:13:32 PM PDT 24
Peak memory 683968 kb
Host smart-6bba3b31-6565-4fb5-ac9d-92fa3aeecfc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399884853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.2399884853
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.166758378
Short name T440
Test name
Test status
Simulation time 1556924495 ps
CPU time 7.11 seconds
Started Apr 25 03:11:10 PM PDT 24
Finished Apr 25 03:11:19 PM PDT 24
Peak memory 212392 kb
Host smart-d3ac1abf-9ad3-443b-90b9-aedcb1817586
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166758378 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_timeout.166758378
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_unexp_stop.392998359
Short name T20
Test name
Test status
Simulation time 31313755013 ps
CPU time 8.28 seconds
Started Apr 25 03:11:21 PM PDT 24
Finished Apr 25 03:11:31 PM PDT 24
Peak memory 218752 kb
Host smart-ff5e2ac6-aca5-47e5-84ea-97a24ee986b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392998359 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_unexp_stop.392998359
Directory /workspace/27.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/28.i2c_alert_test.437861562
Short name T846
Test name
Test status
Simulation time 47592297 ps
CPU time 0.62 seconds
Started Apr 25 03:11:25 PM PDT 24
Finished Apr 25 03:11:27 PM PDT 24
Peak memory 203924 kb
Host smart-b084e736-894b-40aa-92a1-7d7174bcb137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437861562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.437861562
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.4132070584
Short name T1250
Test name
Test status
Simulation time 178703294 ps
CPU time 1.16 seconds
Started Apr 25 03:11:21 PM PDT 24
Finished Apr 25 03:11:24 PM PDT 24
Peak memory 215464 kb
Host smart-f7673eca-d2d6-43ef-a2d7-f2e538e93ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132070584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.4132070584
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.3943396318
Short name T476
Test name
Test status
Simulation time 349077615 ps
CPU time 6.49 seconds
Started Apr 25 03:11:15 PM PDT 24
Finished Apr 25 03:11:22 PM PDT 24
Peak memory 275128 kb
Host smart-ac4e1392-985a-44be-96a4-b7f910f38761
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943396318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.3943396318
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.2616956641
Short name T1125
Test name
Test status
Simulation time 6556813536 ps
CPU time 108.26 seconds
Started Apr 25 03:11:14 PM PDT 24
Finished Apr 25 03:13:03 PM PDT 24
Peak memory 594912 kb
Host smart-36221f03-0c0a-456a-8d6c-335f37928fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616956641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.2616956641
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.3154412008
Short name T1072
Test name
Test status
Simulation time 1916545746 ps
CPU time 133.6 seconds
Started Apr 25 03:11:13 PM PDT 24
Finished Apr 25 03:13:27 PM PDT 24
Peak memory 614708 kb
Host smart-15d2b891-1176-46b9-ad99-15923fded434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154412008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3154412008
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.3346867313
Short name T608
Test name
Test status
Simulation time 277908217 ps
CPU time 1.18 seconds
Started Apr 25 03:11:15 PM PDT 24
Finished Apr 25 03:11:17 PM PDT 24
Peak memory 204184 kb
Host smart-461f6cd6-d5f7-4769-9c80-b73cb5fd2e2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346867313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.3346867313
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.1039782109
Short name T385
Test name
Test status
Simulation time 122203443 ps
CPU time 2.67 seconds
Started Apr 25 03:11:15 PM PDT 24
Finished Apr 25 03:11:19 PM PDT 24
Peak memory 204168 kb
Host smart-7b469d57-5beb-46c5-9601-b969999a4235
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039782109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.1039782109
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.2096643904
Short name T91
Test name
Test status
Simulation time 2359402468 ps
CPU time 61.44 seconds
Started Apr 25 03:11:15 PM PDT 24
Finished Apr 25 03:12:17 PM PDT 24
Peak memory 772776 kb
Host smart-66171715-4313-4a43-a542-6f9a11565c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096643904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.2096643904
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.1285095009
Short name T800
Test name
Test status
Simulation time 1062680903 ps
CPU time 5.04 seconds
Started Apr 25 03:11:24 PM PDT 24
Finished Apr 25 03:11:31 PM PDT 24
Peak memory 204200 kb
Host smart-e32454ab-83c9-4b49-a1c2-d01e5c137c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285095009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.1285095009
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.3896812080
Short name T895
Test name
Test status
Simulation time 17248549606 ps
CPU time 82.44 seconds
Started Apr 25 03:11:26 PM PDT 24
Finished Apr 25 03:12:50 PM PDT 24
Peak memory 298144 kb
Host smart-a6fb1289-ed36-4516-a86a-6e1f50a9ab9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896812080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.3896812080
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.2468443241
Short name T1335
Test name
Test status
Simulation time 42250827 ps
CPU time 0.68 seconds
Started Apr 25 03:11:14 PM PDT 24
Finished Apr 25 03:11:15 PM PDT 24
Peak memory 203868 kb
Host smart-b5b7ad9c-9807-4ee6-855a-08e9dc21dc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468443241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.2468443241
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.1058894240
Short name T824
Test name
Test status
Simulation time 3299187625 ps
CPU time 44.54 seconds
Started Apr 25 03:11:21 PM PDT 24
Finished Apr 25 03:12:08 PM PDT 24
Peak memory 367608 kb
Host smart-5b3041dc-acab-4a63-a205-3e0611b18aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058894240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.1058894240
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1097596222
Short name T683
Test name
Test status
Simulation time 23291050301 ps
CPU time 72.71 seconds
Started Apr 25 03:11:15 PM PDT 24
Finished Apr 25 03:12:28 PM PDT 24
Peak memory 350728 kb
Host smart-e01093cd-ced0-4977-b203-f278e3092f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097596222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1097596222
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.3508219157
Short name T77
Test name
Test status
Simulation time 20586369124 ps
CPU time 323.17 seconds
Started Apr 25 03:11:20 PM PDT 24
Finished Apr 25 03:16:45 PM PDT 24
Peak memory 827704 kb
Host smart-82366425-453e-423c-8157-129191450663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508219157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.3508219157
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.1113388333
Short name T839
Test name
Test status
Simulation time 569781149 ps
CPU time 25.17 seconds
Started Apr 25 03:11:21 PM PDT 24
Finished Apr 25 03:11:48 PM PDT 24
Peak memory 212320 kb
Host smart-ba49b531-06e4-4f5c-8df0-38d83357ae9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113388333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.1113388333
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.632140417
Short name T1262
Test name
Test status
Simulation time 1940377638 ps
CPU time 4.47 seconds
Started Apr 25 03:11:19 PM PDT 24
Finished Apr 25 03:11:24 PM PDT 24
Peak memory 212328 kb
Host smart-b5a9bb1b-2042-4dde-80b5-94d006b3f4b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632140417 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.632140417
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.643202603
Short name T446
Test name
Test status
Simulation time 10211904059 ps
CPU time 14.49 seconds
Started Apr 25 03:11:20 PM PDT 24
Finished Apr 25 03:11:36 PM PDT 24
Peak memory 276124 kb
Host smart-ef3ef081-7181-433a-baa1-afacc87007ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643202603 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_acq.643202603
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.2150866698
Short name T527
Test name
Test status
Simulation time 10313568598 ps
CPU time 13.43 seconds
Started Apr 25 03:11:21 PM PDT 24
Finished Apr 25 03:11:36 PM PDT 24
Peak memory 265836 kb
Host smart-f9131421-22a6-4317-8ac5-1757d80a44c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150866698 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.2150866698
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.868093541
Short name T191
Test name
Test status
Simulation time 4630058861 ps
CPU time 2.06 seconds
Started Apr 25 03:11:26 PM PDT 24
Finished Apr 25 03:11:29 PM PDT 24
Peak memory 204244 kb
Host smart-597ae8eb-064b-4b12-aa4c-c03067e6c1ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868093541 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.i2c_target_hrst.868093541
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.2469100823
Short name T1284
Test name
Test status
Simulation time 4268754946 ps
CPU time 4.3 seconds
Started Apr 25 03:11:19 PM PDT 24
Finished Apr 25 03:11:25 PM PDT 24
Peak memory 208928 kb
Host smart-a1df4290-4507-47a2-a4ac-9612fce5b83a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469100823 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.2469100823
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.4041122236
Short name T358
Test name
Test status
Simulation time 2522190156 ps
CPU time 16.78 seconds
Started Apr 25 03:11:20 PM PDT 24
Finished Apr 25 03:11:38 PM PDT 24
Peak memory 762120 kb
Host smart-eb263d63-81ad-4260-a61e-41647d057596
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041122236 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.4041122236
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.3897821291
Short name T222
Test name
Test status
Simulation time 4766298342 ps
CPU time 23.38 seconds
Started Apr 25 03:11:18 PM PDT 24
Finished Apr 25 03:11:42 PM PDT 24
Peak memory 204268 kb
Host smart-722a42aa-e144-4827-8c4e-bcac21383c82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897821291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.3897821291
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.2992104349
Short name T1034
Test name
Test status
Simulation time 5703693609 ps
CPU time 52.72 seconds
Started Apr 25 03:11:18 PM PDT 24
Finished Apr 25 03:12:12 PM PDT 24
Peak memory 204904 kb
Host smart-3f22bed7-2936-4317-a265-2258c0040305
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992104349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.2992104349
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.1911564171
Short name T634
Test name
Test status
Simulation time 33878595685 ps
CPU time 138.06 seconds
Started Apr 25 03:11:21 PM PDT 24
Finished Apr 25 03:13:41 PM PDT 24
Peak memory 1936512 kb
Host smart-75944dde-84da-49d5-bb19-c1690efc37e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911564171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.1911564171
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.1920335273
Short name T464
Test name
Test status
Simulation time 4360188014 ps
CPU time 13.99 seconds
Started Apr 25 03:11:20 PM PDT 24
Finished Apr 25 03:11:36 PM PDT 24
Peak memory 329564 kb
Host smart-da618d80-838b-41db-abd6-dd7654c26ee3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920335273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.1920335273
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.4246242193
Short name T399
Test name
Test status
Simulation time 6017365137 ps
CPU time 7.72 seconds
Started Apr 25 03:11:20 PM PDT 24
Finished Apr 25 03:11:30 PM PDT 24
Peak memory 218832 kb
Host smart-34fc2314-6860-4da6-93c7-4c45006ff509
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246242193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.4246242193
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3125832347
Short name T832
Test name
Test status
Simulation time 33259430 ps
CPU time 0.6 seconds
Started Apr 25 03:11:37 PM PDT 24
Finished Apr 25 03:11:39 PM PDT 24
Peak memory 203892 kb
Host smart-54385cfb-a9ad-4d88-b5ea-d818505d459e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125832347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3125832347
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.4115150104
Short name T984
Test name
Test status
Simulation time 68603301 ps
CPU time 1.06 seconds
Started Apr 25 03:11:50 PM PDT 24
Finished Apr 25 03:11:52 PM PDT 24
Peak memory 212508 kb
Host smart-5c7a56e3-7dc4-4cf9-a528-7ed3a6d1fafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115150104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.4115150104
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.992010437
Short name T305
Test name
Test status
Simulation time 517735711 ps
CPU time 13.72 seconds
Started Apr 25 03:11:26 PM PDT 24
Finished Apr 25 03:11:42 PM PDT 24
Peak memory 253616 kb
Host smart-e65cbb86-dce8-4279-887c-514e8a613618
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992010437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empt
y.992010437
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.751044421
Short name T351
Test name
Test status
Simulation time 1497277489 ps
CPU time 101.5 seconds
Started Apr 25 03:11:32 PM PDT 24
Finished Apr 25 03:13:14 PM PDT 24
Peak memory 565508 kb
Host smart-c531c2fc-a307-4dda-9241-ecf9987ead7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751044421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.751044421
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.857330572
Short name T253
Test name
Test status
Simulation time 1492760083 ps
CPU time 49.82 seconds
Started Apr 25 03:11:24 PM PDT 24
Finished Apr 25 03:12:15 PM PDT 24
Peak memory 554056 kb
Host smart-edd7c362-7945-4bad-8f38-b6d2beaa2c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857330572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.857330572
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1153886092
Short name T1177
Test name
Test status
Simulation time 439180915 ps
CPU time 1.08 seconds
Started Apr 25 03:11:25 PM PDT 24
Finished Apr 25 03:11:27 PM PDT 24
Peak memory 204140 kb
Host smart-e0118d08-fa23-4f8a-b483-ddc222c06a2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153886092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1153886092
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.2310562702
Short name T85
Test name
Test status
Simulation time 599935430 ps
CPU time 5.64 seconds
Started Apr 25 03:11:44 PM PDT 24
Finished Apr 25 03:11:51 PM PDT 24
Peak memory 239660 kb
Host smart-5cd418fa-5aa2-403b-b144-c4d325f9fbc6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310562702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.2310562702
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.3161695578
Short name T728
Test name
Test status
Simulation time 4341664440 ps
CPU time 344.19 seconds
Started Apr 25 03:11:26 PM PDT 24
Finished Apr 25 03:17:12 PM PDT 24
Peak memory 1245676 kb
Host smart-fbadf19c-d49c-42f3-9c7c-2fcdc9ad6f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161695578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.3161695578
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.3354280993
Short name T891
Test name
Test status
Simulation time 1391411171 ps
CPU time 12.26 seconds
Started Apr 25 03:11:36 PM PDT 24
Finished Apr 25 03:11:49 PM PDT 24
Peak memory 204148 kb
Host smart-c6c6583f-3224-4ea3-8510-155724ff5bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354280993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.3354280993
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.4267848825
Short name T782
Test name
Test status
Simulation time 7016631264 ps
CPU time 87.56 seconds
Started Apr 25 03:11:36 PM PDT 24
Finished Apr 25 03:13:05 PM PDT 24
Peak memory 333552 kb
Host smart-29c5768f-a0ca-4b24-b02a-26482674ad48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267848825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.4267848825
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.5772155
Short name T37
Test name
Test status
Simulation time 31714696 ps
CPU time 0.66 seconds
Started Apr 25 03:11:24 PM PDT 24
Finished Apr 25 03:11:26 PM PDT 24
Peak memory 203832 kb
Host smart-ee6a37fd-a3bc-41ef-8fdc-6fe4f9d30304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5772155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.5772155
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.1259640599
Short name T1014
Test name
Test status
Simulation time 4561375510 ps
CPU time 5.79 seconds
Started Apr 25 03:11:39 PM PDT 24
Finished Apr 25 03:11:46 PM PDT 24
Peak memory 259248 kb
Host smart-a0b9a2d7-4829-42b4-9cd2-3946e8cc3525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259640599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.1259640599
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.3784120596
Short name T918
Test name
Test status
Simulation time 3857688865 ps
CPU time 50.69 seconds
Started Apr 25 03:11:24 PM PDT 24
Finished Apr 25 03:12:16 PM PDT 24
Peak memory 280640 kb
Host smart-5e42f984-f268-48d4-a458-04df281c1fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784120596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.3784120596
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.748163473
Short name T901
Test name
Test status
Simulation time 6768898502 ps
CPU time 337.27 seconds
Started Apr 25 03:11:35 PM PDT 24
Finished Apr 25 03:17:13 PM PDT 24
Peak memory 1608284 kb
Host smart-e23ea5d6-6690-4853-ac59-61346098ca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748163473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.748163473
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.4060409940
Short name T1312
Test name
Test status
Simulation time 586203051 ps
CPU time 21.16 seconds
Started Apr 25 03:11:44 PM PDT 24
Finished Apr 25 03:12:06 PM PDT 24
Peak memory 212224 kb
Host smart-25aab195-09e0-45ea-b72e-e740c0c454c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060409940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.4060409940
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.3445694298
Short name T761
Test name
Test status
Simulation time 2032582371 ps
CPU time 2.68 seconds
Started Apr 25 03:11:36 PM PDT 24
Finished Apr 25 03:11:40 PM PDT 24
Peak memory 204184 kb
Host smart-4bdca7ea-97b2-493f-b256-8c2bf0c23330
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445694298 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.3445694298
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.2766596132
Short name T806
Test name
Test status
Simulation time 10149376692 ps
CPU time 12.97 seconds
Started Apr 25 03:11:32 PM PDT 24
Finished Apr 25 03:11:45 PM PDT 24
Peak memory 252568 kb
Host smart-0fff827a-c5b8-4ee8-b087-74dff434f2c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766596132 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.2766596132
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.2980795473
Short name T1308
Test name
Test status
Simulation time 10442950185 ps
CPU time 16.67 seconds
Started Apr 25 03:11:30 PM PDT 24
Finished Apr 25 03:11:48 PM PDT 24
Peak memory 270804 kb
Host smart-e9d7bd1b-eff8-4cdc-97c4-08800ff8e8bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980795473 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.2980795473
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.620170094
Short name T921
Test name
Test status
Simulation time 927558828 ps
CPU time 2.4 seconds
Started Apr 25 03:11:37 PM PDT 24
Finished Apr 25 03:11:40 PM PDT 24
Peak memory 204236 kb
Host smart-27dc3e6a-6b5d-4583-9919-64bb00f5a28c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620170094 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.i2c_target_hrst.620170094
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.1856802607
Short name T578
Test name
Test status
Simulation time 6930787731 ps
CPU time 6.04 seconds
Started Apr 25 03:11:44 PM PDT 24
Finished Apr 25 03:11:52 PM PDT 24
Peak memory 219460 kb
Host smart-e69b1296-c1c1-4682-87a9-b14afc905277
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856802607 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.1856802607
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.3725108889
Short name T807
Test name
Test status
Simulation time 14671705015 ps
CPU time 60.28 seconds
Started Apr 25 03:11:29 PM PDT 24
Finished Apr 25 03:12:31 PM PDT 24
Peak memory 1240052 kb
Host smart-e7daebc6-c809-48e5-ba98-a41b0cb9734f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725108889 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.3725108889
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.747017922
Short name T674
Test name
Test status
Simulation time 1750527350 ps
CPU time 32.1 seconds
Started Apr 25 03:11:30 PM PDT 24
Finished Apr 25 03:12:03 PM PDT 24
Peak memory 204076 kb
Host smart-036007af-c12b-4fea-ad9d-d793f62615a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747017922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_tar
get_smoke.747017922
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.1598635409
Short name T444
Test name
Test status
Simulation time 769184411 ps
CPU time 12.7 seconds
Started Apr 25 03:11:44 PM PDT 24
Finished Apr 25 03:11:58 PM PDT 24
Peak memory 210048 kb
Host smart-847bd54a-b534-4553-b1cb-f84d822f69a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598635409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.1598635409
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.3555498742
Short name T777
Test name
Test status
Simulation time 28389119417 ps
CPU time 59.53 seconds
Started Apr 25 03:11:44 PM PDT 24
Finished Apr 25 03:12:45 PM PDT 24
Peak memory 1026132 kb
Host smart-e4789818-771a-4d3e-b69e-8e85c4eff9ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555498742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.3555498742
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.1442483166
Short name T1000
Test name
Test status
Simulation time 5109287974 ps
CPU time 7.3 seconds
Started Apr 25 03:11:31 PM PDT 24
Finished Apr 25 03:11:39 PM PDT 24
Peak memory 211144 kb
Host smart-46dc20be-f44b-4b16-9cc6-b850b283dfac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442483166 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.1442483166
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.2160126232
Short name T910
Test name
Test status
Simulation time 27763864 ps
CPU time 0.63 seconds
Started Apr 25 03:05:34 PM PDT 24
Finished Apr 25 03:05:36 PM PDT 24
Peak memory 203984 kb
Host smart-b493537c-5ee1-4918-b851-5814afca31d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160126232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.2160126232
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3274256759
Short name T1286
Test name
Test status
Simulation time 1279255973 ps
CPU time 1.34 seconds
Started Apr 25 03:05:22 PM PDT 24
Finished Apr 25 03:05:25 PM PDT 24
Peak memory 212508 kb
Host smart-4bf04e30-456f-4b26-ad93-630437f96981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274256759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3274256759
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.3169998719
Short name T477
Test name
Test status
Simulation time 929759610 ps
CPU time 13.56 seconds
Started Apr 25 03:05:22 PM PDT 24
Finished Apr 25 03:05:37 PM PDT 24
Peak memory 257528 kb
Host smart-f8ddc931-5b9b-4952-b192-c549042cb404
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169998719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.3169998719
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.4099877382
Short name T972
Test name
Test status
Simulation time 14132230936 ps
CPU time 187.79 seconds
Started Apr 25 03:05:25 PM PDT 24
Finished Apr 25 03:08:34 PM PDT 24
Peak memory 801320 kb
Host smart-8557747c-d0e5-4b1f-99d2-c63c2fa0a977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099877382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.4099877382
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.1536880641
Short name T840
Test name
Test status
Simulation time 1320008655 ps
CPU time 36.56 seconds
Started Apr 25 03:05:25 PM PDT 24
Finished Apr 25 03:06:03 PM PDT 24
Peak memory 515848 kb
Host smart-0d5d11d4-1c93-4116-b39c-0429ebf510a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536880641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.1536880641
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.721596556
Short name T95
Test name
Test status
Simulation time 316138208 ps
CPU time 1.19 seconds
Started Apr 25 03:05:23 PM PDT 24
Finished Apr 25 03:05:25 PM PDT 24
Peak memory 204140 kb
Host smart-99171da8-7218-4bb2-b6a6-e67950246859
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721596556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt
.721596556
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.3891465828
Short name T760
Test name
Test status
Simulation time 379129108 ps
CPU time 3.42 seconds
Started Apr 25 03:05:22 PM PDT 24
Finished Apr 25 03:05:26 PM PDT 24
Peak memory 224284 kb
Host smart-6bf60d96-d3ba-4fca-b6aa-c640accdf081
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891465828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
3891465828
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.1167098696
Short name T609
Test name
Test status
Simulation time 4261073222 ps
CPU time 228.55 seconds
Started Apr 25 03:05:22 PM PDT 24
Finished Apr 25 03:09:12 PM PDT 24
Peak memory 966488 kb
Host smart-f32fc64e-5757-4c20-b368-f49b00486358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167098696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1167098696
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.3545585745
Short name T644
Test name
Test status
Simulation time 249356758 ps
CPU time 4.29 seconds
Started Apr 25 03:05:35 PM PDT 24
Finished Apr 25 03:05:41 PM PDT 24
Peak memory 204184 kb
Host smart-09e9d8d6-f014-4626-8a9e-d9cad6649e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545585745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.3545585745
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.3204985181
Short name T731
Test name
Test status
Simulation time 1558641686 ps
CPU time 75.98 seconds
Started Apr 25 03:05:37 PM PDT 24
Finished Apr 25 03:06:54 PM PDT 24
Peak memory 347456 kb
Host smart-bae2687c-c28a-4f38-b86f-b6da28d1d724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204985181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.3204985181
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.3188276167
Short name T1203
Test name
Test status
Simulation time 47504853 ps
CPU time 0.65 seconds
Started Apr 25 03:05:16 PM PDT 24
Finished Apr 25 03:05:18 PM PDT 24
Peak memory 203824 kb
Host smart-26b9c1c6-2e9b-4ede-943c-242ef3a81971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188276167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3188276167
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.4096434191
Short name T1001
Test name
Test status
Simulation time 49790985327 ps
CPU time 630.29 seconds
Started Apr 25 03:05:24 PM PDT 24
Finished Apr 25 03:15:55 PM PDT 24
Peak memory 232860 kb
Host smart-f177bdbb-cac1-47f6-8053-d18867bc850d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096434191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.4096434191
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.1703931153
Short name T240
Test name
Test status
Simulation time 1403430471 ps
CPU time 28.34 seconds
Started Apr 25 03:05:16 PM PDT 24
Finished Apr 25 03:05:45 PM PDT 24
Peak memory 314764 kb
Host smart-934d1b1d-e150-4983-b00f-fc0137b6c40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703931153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1703931153
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.2807513172
Short name T165
Test name
Test status
Simulation time 2683160115 ps
CPU time 53.94 seconds
Started Apr 25 03:05:22 PM PDT 24
Finished Apr 25 03:06:17 PM PDT 24
Peak memory 489396 kb
Host smart-e0667446-4d18-4127-9269-57f87b815895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807513172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.2807513172
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.4096899111
Short name T1230
Test name
Test status
Simulation time 422595199 ps
CPU time 17.68 seconds
Started Apr 25 03:05:24 PM PDT 24
Finished Apr 25 03:05:42 PM PDT 24
Peak memory 212336 kb
Host smart-6409cfc8-0c69-43bb-9d80-12daf476f9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096899111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.4096899111
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.2014989272
Short name T111
Test name
Test status
Simulation time 45187209 ps
CPU time 0.85 seconds
Started Apr 25 03:05:35 PM PDT 24
Finished Apr 25 03:05:36 PM PDT 24
Peak memory 221476 kb
Host smart-aff05227-fe7f-466d-b8ff-1155f2847631
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014989272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.2014989272
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.2556586959
Short name T1154
Test name
Test status
Simulation time 3728490602 ps
CPU time 4.48 seconds
Started Apr 25 03:05:35 PM PDT 24
Finished Apr 25 03:05:40 PM PDT 24
Peak memory 214720 kb
Host smart-45bfb15c-38e3-40e1-984d-439aca2d7027
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556586959 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.2556586959
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.719040637
Short name T804
Test name
Test status
Simulation time 10109240510 ps
CPU time 39.17 seconds
Started Apr 25 03:05:33 PM PDT 24
Finished Apr 25 03:06:12 PM PDT 24
Peak memory 383392 kb
Host smart-2dc9d77c-e441-4c71-b4eb-0a48123e5925
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719040637 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_acq.719040637
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.182270972
Short name T792
Test name
Test status
Simulation time 10104302746 ps
CPU time 73.14 seconds
Started Apr 25 03:05:37 PM PDT 24
Finished Apr 25 03:06:51 PM PDT 24
Peak memory 570236 kb
Host smart-bf223517-16c8-4595-a1c9-67aa76111d71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182270972 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_fifo_reset_tx.182270972
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.523744239
Short name T232
Test name
Test status
Simulation time 618395872 ps
CPU time 2.15 seconds
Started Apr 25 03:05:34 PM PDT 24
Finished Apr 25 03:05:37 PM PDT 24
Peak memory 204212 kb
Host smart-a33bf27c-84d8-4f7f-befb-22fa572c2a50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523744239 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.i2c_target_hrst.523744239
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.4155540638
Short name T326
Test name
Test status
Simulation time 2359039998 ps
CPU time 5.82 seconds
Started Apr 25 03:05:29 PM PDT 24
Finished Apr 25 03:05:36 PM PDT 24
Peak memory 220404 kb
Host smart-f9bb4342-e82c-4075-854a-45176d90cdb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155540638 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.4155540638
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.138500910
Short name T833
Test name
Test status
Simulation time 16729874799 ps
CPU time 343.46 seconds
Started Apr 25 03:05:30 PM PDT 24
Finished Apr 25 03:11:14 PM PDT 24
Peak memory 4024192 kb
Host smart-2164adda-6af0-4aaa-84fb-7d729ffc69ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138500910 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.138500910
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.4233092612
Short name T704
Test name
Test status
Simulation time 3583580320 ps
CPU time 34.33 seconds
Started Apr 25 03:05:25 PM PDT 24
Finished Apr 25 03:06:00 PM PDT 24
Peak memory 204212 kb
Host smart-cf287618-77de-42f4-8192-cd262648f636
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233092612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.4233092612
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.1845508533
Short name T1337
Test name
Test status
Simulation time 1681590426 ps
CPU time 6.78 seconds
Started Apr 25 03:05:29 PM PDT 24
Finished Apr 25 03:05:36 PM PDT 24
Peak memory 204096 kb
Host smart-ae92e290-7f8e-4c8a-8eae-ed7bd237828d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845508533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.1845508533
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.1870979600
Short name T729
Test name
Test status
Simulation time 56092871645 ps
CPU time 232.36 seconds
Started Apr 25 03:05:32 PM PDT 24
Finished Apr 25 03:09:25 PM PDT 24
Peak memory 2513968 kb
Host smart-eb34b91f-5e09-4a17-958e-2dfde02ed97b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870979600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.1870979600
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.1166531037
Short name T298
Test name
Test status
Simulation time 13197420195 ps
CPU time 239.48 seconds
Started Apr 25 03:05:29 PM PDT 24
Finished Apr 25 03:09:30 PM PDT 24
Peak memory 1602568 kb
Host smart-5ed4edc1-ad12-4e7d-8a28-56759a484805
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166531037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.1166531037
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.379137800
Short name T303
Test name
Test status
Simulation time 3315156480 ps
CPU time 7.86 seconds
Started Apr 25 03:05:33 PM PDT 24
Finished Apr 25 03:05:42 PM PDT 24
Peak memory 204276 kb
Host smart-4eed1b99-e0b8-4935-8dbb-5687502c272f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379137800 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_timeout.379137800
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.4191063144
Short name T817
Test name
Test status
Simulation time 45045240 ps
CPU time 0.61 seconds
Started Apr 25 03:11:46 PM PDT 24
Finished Apr 25 03:11:48 PM PDT 24
Peak memory 203868 kb
Host smart-34b79595-9d91-49b3-8da4-dc3c9a096ec5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191063144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.4191063144
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.4258349032
Short name T516
Test name
Test status
Simulation time 263363975 ps
CPU time 1.18 seconds
Started Apr 25 03:11:42 PM PDT 24
Finished Apr 25 03:11:44 PM PDT 24
Peak memory 212388 kb
Host smart-0df12df6-a9c5-429b-bdd6-c185adb55917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258349032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.4258349032
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.2108486305
Short name T612
Test name
Test status
Simulation time 946497768 ps
CPU time 12.64 seconds
Started Apr 25 03:11:36 PM PDT 24
Finished Apr 25 03:11:50 PM PDT 24
Peak memory 251540 kb
Host smart-7b5731ab-d094-4020-b787-705623e4f20e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108486305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.2108486305
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.1552963538
Short name T692
Test name
Test status
Simulation time 2219015979 ps
CPU time 68.71 seconds
Started Apr 25 03:11:45 PM PDT 24
Finished Apr 25 03:12:55 PM PDT 24
Peak memory 732296 kb
Host smart-8744a047-a501-4a43-9b89-de134cf6a7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552963538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.1552963538
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.3684534088
Short name T765
Test name
Test status
Simulation time 5040609535 ps
CPU time 42.22 seconds
Started Apr 25 03:11:35 PM PDT 24
Finished Apr 25 03:12:18 PM PDT 24
Peak memory 594108 kb
Host smart-b1de5f8a-f648-4a28-bc7b-c9f7f395b09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684534088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.3684534088
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.2748691225
Short name T749
Test name
Test status
Simulation time 710204282 ps
CPU time 1.21 seconds
Started Apr 25 03:11:36 PM PDT 24
Finished Apr 25 03:11:38 PM PDT 24
Peak memory 204124 kb
Host smart-dc46a832-5159-46c2-b1db-177796f36d04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748691225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.2748691225
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.4032720884
Short name T1002
Test name
Test status
Simulation time 1379767595 ps
CPU time 6.12 seconds
Started Apr 25 03:12:03 PM PDT 24
Finished Apr 25 03:12:10 PM PDT 24
Peak memory 204232 kb
Host smart-4abfa7af-eeb9-4cd4-bfc1-a128b0902620
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032720884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.4032720884
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.3302294989
Short name T1024
Test name
Test status
Simulation time 6132302794 ps
CPU time 85.09 seconds
Started Apr 25 03:11:39 PM PDT 24
Finished Apr 25 03:13:05 PM PDT 24
Peak memory 934812 kb
Host smart-2a5df6ca-9e43-46ac-b069-d1af6a437f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302294989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3302294989
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.2579182603
Short name T809
Test name
Test status
Simulation time 1835153899 ps
CPU time 4.99 seconds
Started Apr 25 03:11:54 PM PDT 24
Finished Apr 25 03:12:01 PM PDT 24
Peak memory 203472 kb
Host smart-6fe8c4d7-eef2-4132-ac28-1b78924c7e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579182603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.2579182603
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.153937132
Short name T878
Test name
Test status
Simulation time 1407537044 ps
CPU time 60.08 seconds
Started Apr 25 03:11:47 PM PDT 24
Finished Apr 25 03:12:49 PM PDT 24
Peak memory 302268 kb
Host smart-aa76dc2a-6a47-4b38-9ede-73a43e3f98c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153937132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.153937132
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.3135473867
Short name T1267
Test name
Test status
Simulation time 52341903 ps
CPU time 0.69 seconds
Started Apr 25 03:11:36 PM PDT 24
Finished Apr 25 03:11:37 PM PDT 24
Peak memory 203836 kb
Host smart-2a7e0fb5-a046-41de-862a-cb5e662ec999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135473867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3135473867
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.3334603741
Short name T1222
Test name
Test status
Simulation time 3079351958 ps
CPU time 16.53 seconds
Started Apr 25 03:11:45 PM PDT 24
Finished Apr 25 03:12:03 PM PDT 24
Peak memory 364860 kb
Host smart-78e8a7d9-007c-42f3-bc53-b7e7cac44e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334603741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.3334603741
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.514877465
Short name T438
Test name
Test status
Simulation time 864821299 ps
CPU time 42.13 seconds
Started Apr 25 03:11:38 PM PDT 24
Finished Apr 25 03:12:21 PM PDT 24
Peak memory 293996 kb
Host smart-73aa35cc-0c78-4252-991b-aaeddcb6ad1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514877465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.514877465
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.2342113090
Short name T815
Test name
Test status
Simulation time 20721564136 ps
CPU time 410.63 seconds
Started Apr 25 03:11:46 PM PDT 24
Finished Apr 25 03:18:38 PM PDT 24
Peak memory 1526968 kb
Host smart-e29e7b89-d558-4aae-aca4-609dc14919a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342113090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.2342113090
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.662891527
Short name T57
Test name
Test status
Simulation time 1004287113 ps
CPU time 22.69 seconds
Started Apr 25 03:11:44 PM PDT 24
Finished Apr 25 03:12:08 PM PDT 24
Peak memory 212328 kb
Host smart-e8b436cf-0dbf-44a6-8bf9-e75e37f67a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662891527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.662891527
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.3911858174
Short name T927
Test name
Test status
Simulation time 3925569599 ps
CPU time 4.33 seconds
Started Apr 25 03:11:46 PM PDT 24
Finished Apr 25 03:11:51 PM PDT 24
Peak memory 213200 kb
Host smart-2abf9a83-68a1-4db2-baf0-24be5e514b00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911858174 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3911858174
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.1740595434
Short name T441
Test name
Test status
Simulation time 10096612437 ps
CPU time 67.32 seconds
Started Apr 25 03:11:45 PM PDT 24
Finished Apr 25 03:12:53 PM PDT 24
Peak memory 451056 kb
Host smart-43bab19e-e195-400e-b2bb-8abbcb7414ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740595434 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.1740595434
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.1845602624
Short name T963
Test name
Test status
Simulation time 10368708547 ps
CPU time 17.54 seconds
Started Apr 25 03:11:42 PM PDT 24
Finished Apr 25 03:12:01 PM PDT 24
Peak memory 277336 kb
Host smart-efed9e65-2535-4016-b66b-779e47016b17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845602624 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.1845602624
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.4222144334
Short name T885
Test name
Test status
Simulation time 4237657128 ps
CPU time 2.57 seconds
Started Apr 25 03:11:47 PM PDT 24
Finished Apr 25 03:11:52 PM PDT 24
Peak memory 204276 kb
Host smart-0a78cb68-fd11-4015-aa5a-00a99e2bbf53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222144334 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.4222144334
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.2386618312
Short name T289
Test name
Test status
Simulation time 646656165 ps
CPU time 3.67 seconds
Started Apr 25 03:11:43 PM PDT 24
Finished Apr 25 03:11:48 PM PDT 24
Peak memory 204184 kb
Host smart-95c23881-ca20-4e8b-bfc9-65febccfb5ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386618312 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.2386618312
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.1048132709
Short name T346
Test name
Test status
Simulation time 20813288969 ps
CPU time 269.34 seconds
Started Apr 25 03:11:41 PM PDT 24
Finished Apr 25 03:16:12 PM PDT 24
Peak memory 2755080 kb
Host smart-d7eb8b44-aa4b-403b-8710-73e37513e8a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048132709 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.1048132709
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.647109139
Short name T356
Test name
Test status
Simulation time 1633104040 ps
CPU time 13.55 seconds
Started Apr 25 03:11:41 PM PDT 24
Finished Apr 25 03:11:56 PM PDT 24
Peak memory 204168 kb
Host smart-d2edefa9-c47d-4516-856e-88bfd66d2b4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647109139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_tar
get_smoke.647109139
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_all.4144660070
Short name T594
Test name
Test status
Simulation time 50168928037 ps
CPU time 93.68 seconds
Started Apr 25 03:11:46 PM PDT 24
Finished Apr 25 03:13:20 PM PDT 24
Peak memory 1280548 kb
Host smart-db1bd430-bbb3-46f8-8382-5572ae875197
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144660070 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.i2c_target_stress_all.4144660070
Directory /workspace/30.i2c_target_stress_all/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.1696695830
Short name T198
Test name
Test status
Simulation time 2218785835 ps
CPU time 19.42 seconds
Started Apr 25 03:11:41 PM PDT 24
Finished Apr 25 03:12:01 PM PDT 24
Peak memory 217616 kb
Host smart-ade19684-c08b-48e8-8734-b72ba30aae0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696695830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.1696695830
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.1680177650
Short name T1271
Test name
Test status
Simulation time 61118379136 ps
CPU time 226.1 seconds
Started Apr 25 03:11:46 PM PDT 24
Finished Apr 25 03:15:33 PM PDT 24
Peak memory 2440288 kb
Host smart-a3bd91f6-822e-4879-931d-925fe9589ccc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680177650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.1680177650
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.60909710
Short name T505
Test name
Test status
Simulation time 8406964545 ps
CPU time 38.74 seconds
Started Apr 25 03:11:42 PM PDT 24
Finished Apr 25 03:12:22 PM PDT 24
Peak memory 572928 kb
Host smart-99a3009f-6139-4cfb-a689-0e0129953ec1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60909710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_stretch.60909710
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.741330341
Short name T931
Test name
Test status
Simulation time 2291278560 ps
CPU time 6.42 seconds
Started Apr 25 03:11:46 PM PDT 24
Finished Apr 25 03:11:53 PM PDT 24
Peak memory 218120 kb
Host smart-2cfdc457-6309-49aa-937b-d87cf405ad1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741330341 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_timeout.741330341
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.3008163764
Short name T58
Test name
Test status
Simulation time 17403748 ps
CPU time 0.65 seconds
Started Apr 25 03:12:02 PM PDT 24
Finished Apr 25 03:12:03 PM PDT 24
Peak memory 203868 kb
Host smart-a3631292-0fda-4824-bf11-863d92a5a961
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008163764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.3008163764
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.710453100
Short name T226
Test name
Test status
Simulation time 246136621 ps
CPU time 1.31 seconds
Started Apr 25 03:11:54 PM PDT 24
Finished Apr 25 03:11:57 PM PDT 24
Peak memory 211816 kb
Host smart-bc5e38dd-d472-4b5c-842a-4debb4fd354e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710453100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.710453100
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.544702302
Short name T1255
Test name
Test status
Simulation time 930910905 ps
CPU time 9.88 seconds
Started Apr 25 03:11:52 PM PDT 24
Finished Apr 25 03:12:04 PM PDT 24
Peak memory 289404 kb
Host smart-aff553ce-f19a-436c-b9d0-e48d69baa195
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544702302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empt
y.544702302
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.4190613205
Short name T599
Test name
Test status
Simulation time 10071223247 ps
CPU time 192.74 seconds
Started Apr 25 03:11:51 PM PDT 24
Finished Apr 25 03:15:06 PM PDT 24
Peak memory 830116 kb
Host smart-5cc23ad6-4a28-46cc-8e0d-c1315505a12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190613205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.4190613205
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.2161527654
Short name T1189
Test name
Test status
Simulation time 2424406288 ps
CPU time 76.74 seconds
Started Apr 25 03:11:53 PM PDT 24
Finished Apr 25 03:13:12 PM PDT 24
Peak memory 755484 kb
Host smart-ca6bedd1-6922-4f9e-92c7-130d5a13ef67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161527654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.2161527654
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.1243148594
Short name T720
Test name
Test status
Simulation time 131928761 ps
CPU time 1.26 seconds
Started Apr 25 03:11:51 PM PDT 24
Finished Apr 25 03:11:54 PM PDT 24
Peak memory 204176 kb
Host smart-6384b47f-941e-4fac-b50b-498def94095e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243148594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.1243148594
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.3250399376
Short name T987
Test name
Test status
Simulation time 669808341 ps
CPU time 2.91 seconds
Started Apr 25 03:11:52 PM PDT 24
Finished Apr 25 03:11:56 PM PDT 24
Peak memory 204156 kb
Host smart-08c34898-2b1c-4c53-bb4b-840b0e69611c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250399376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.3250399376
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.2420901108
Short name T1039
Test name
Test status
Simulation time 2522672121 ps
CPU time 160.52 seconds
Started Apr 25 03:11:53 PM PDT 24
Finished Apr 25 03:14:36 PM PDT 24
Peak memory 824540 kb
Host smart-72ea9163-fe87-4d17-b10d-4481171fa4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420901108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.2420901108
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.88955186
Short name T1280
Test name
Test status
Simulation time 540322465 ps
CPU time 4.06 seconds
Started Apr 25 03:11:57 PM PDT 24
Finished Apr 25 03:12:02 PM PDT 24
Peak memory 204164 kb
Host smart-848564f0-96ee-46bb-98c3-77aa89b10494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88955186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.88955186
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.2703865765
Short name T919
Test name
Test status
Simulation time 3404728995 ps
CPU time 57.9 seconds
Started Apr 25 03:11:58 PM PDT 24
Finished Apr 25 03:12:57 PM PDT 24
Peak memory 329980 kb
Host smart-a7160d7c-76ef-4e0d-a8ed-981900fc3447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703865765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.2703865765
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.406430836
Short name T656
Test name
Test status
Simulation time 107817891 ps
CPU time 0.66 seconds
Started Apr 25 03:11:49 PM PDT 24
Finished Apr 25 03:11:51 PM PDT 24
Peak memory 203852 kb
Host smart-7f6e2cb1-b861-48e5-a7f0-d56892fecdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406430836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.406430836
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.398727127
Short name T522
Test name
Test status
Simulation time 7074785921 ps
CPU time 384.28 seconds
Started Apr 25 03:11:53 PM PDT 24
Finished Apr 25 03:18:19 PM PDT 24
Peak memory 807768 kb
Host smart-78cd18b1-e563-4e6c-97df-6f2eadc2e90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398727127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.398727127
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.2868806431
Short name T1305
Test name
Test status
Simulation time 8249531047 ps
CPU time 94.48 seconds
Started Apr 25 03:11:47 PM PDT 24
Finished Apr 25 03:13:22 PM PDT 24
Peak memory 412788 kb
Host smart-b8730104-0e02-4c4d-bd24-2ed654023c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868806431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.2868806431
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.400437563
Short name T893
Test name
Test status
Simulation time 1089463828 ps
CPU time 7.88 seconds
Started Apr 25 03:11:53 PM PDT 24
Finished Apr 25 03:12:03 PM PDT 24
Peak memory 213440 kb
Host smart-3d367fe6-b3a2-47c6-97fd-0d54814bca75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400437563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.400437563
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.3214526787
Short name T520
Test name
Test status
Simulation time 3426372115 ps
CPU time 3.4 seconds
Started Apr 25 03:11:58 PM PDT 24
Finished Apr 25 03:12:03 PM PDT 24
Peak memory 212436 kb
Host smart-d2770d2f-08f9-4bf5-b323-0651009e92f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214526787 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.3214526787
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3393467561
Short name T422
Test name
Test status
Simulation time 10238519540 ps
CPU time 13.37 seconds
Started Apr 25 03:11:52 PM PDT 24
Finished Apr 25 03:12:07 PM PDT 24
Peak memory 268852 kb
Host smart-63c98192-ab53-4326-bd52-dd9f5b3ca127
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393467561 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3393467561
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.4211044506
Short name T1020
Test name
Test status
Simulation time 10095558373 ps
CPU time 67.83 seconds
Started Apr 25 03:11:58 PM PDT 24
Finished Apr 25 03:13:08 PM PDT 24
Peak memory 458460 kb
Host smart-55c6013a-e811-4e42-8863-146f59e6d5bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211044506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.4211044506
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.3818647694
Short name T1162
Test name
Test status
Simulation time 2168726634 ps
CPU time 2.91 seconds
Started Apr 25 03:11:56 PM PDT 24
Finished Apr 25 03:12:01 PM PDT 24
Peak memory 204260 kb
Host smart-e80f59c0-de50-492b-aabb-541df8cabd46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818647694 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.3818647694
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.1885799876
Short name T272
Test name
Test status
Simulation time 2551050479 ps
CPU time 3.4 seconds
Started Apr 25 03:11:54 PM PDT 24
Finished Apr 25 03:11:59 PM PDT 24
Peak memory 206960 kb
Host smart-57ce8114-067c-447e-9ddf-b028198d90e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885799876 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.1885799876
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.1002540053
Short name T485
Test name
Test status
Simulation time 18527462436 ps
CPU time 37.47 seconds
Started Apr 25 03:11:52 PM PDT 24
Finished Apr 25 03:12:31 PM PDT 24
Peak memory 721192 kb
Host smart-736bda78-03e9-4e05-8c6f-14bf766005a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002540053 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.1002540053
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.1216526252
Short name T1253
Test name
Test status
Simulation time 5235217145 ps
CPU time 14.88 seconds
Started Apr 25 03:11:56 PM PDT 24
Finished Apr 25 03:12:12 PM PDT 24
Peak memory 204244 kb
Host smart-659be57a-b90f-4f8e-9e14-7ca352b7588d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216526252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.1216526252
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.2915918247
Short name T666
Test name
Test status
Simulation time 1069288042 ps
CPU time 18.59 seconds
Started Apr 25 03:11:54 PM PDT 24
Finished Apr 25 03:12:15 PM PDT 24
Peak memory 219668 kb
Host smart-08a3faef-9f1a-4c6f-afb4-1904dab92e22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915918247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.2915918247
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.1715674509
Short name T359
Test name
Test status
Simulation time 16768398743 ps
CPU time 9.22 seconds
Started Apr 25 03:11:52 PM PDT 24
Finished Apr 25 03:12:03 PM PDT 24
Peak memory 204272 kb
Host smart-502e69e5-3823-423e-a5f6-fdf117c9ecba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715674509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.1715674509
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.88776240
Short name T916
Test name
Test status
Simulation time 7152915993 ps
CPU time 76.68 seconds
Started Apr 25 03:11:52 PM PDT 24
Finished Apr 25 03:13:10 PM PDT 24
Peak memory 514040 kb
Host smart-8bc2a952-577d-4355-8763-559329763283
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88776240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_stretch.88776240
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.3919820534
Short name T306
Test name
Test status
Simulation time 5521244626 ps
CPU time 6.65 seconds
Started Apr 25 03:11:53 PM PDT 24
Finished Apr 25 03:12:02 PM PDT 24
Peak memory 218704 kb
Host smart-b5a14e21-5e6a-43bf-a1eb-e8585a769832
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919820534 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.3919820534
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.1041850670
Short name T254
Test name
Test status
Simulation time 19843464 ps
CPU time 0.61 seconds
Started Apr 25 03:12:09 PM PDT 24
Finished Apr 25 03:12:11 PM PDT 24
Peak memory 203892 kb
Host smart-4b67c2c9-2ef9-4aab-83b7-5e14c158dbe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041850670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.1041850670
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.1779420903
Short name T8
Test name
Test status
Simulation time 183641342 ps
CPU time 1.21 seconds
Started Apr 25 03:12:07 PM PDT 24
Finished Apr 25 03:12:09 PM PDT 24
Peak memory 215172 kb
Host smart-98b63031-8984-454f-a372-4cd264fe9ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779420903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1779420903
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.328654254
Short name T858
Test name
Test status
Simulation time 697913810 ps
CPU time 20.33 seconds
Started Apr 25 03:11:58 PM PDT 24
Finished Apr 25 03:12:20 PM PDT 24
Peak memory 268672 kb
Host smart-eb65882c-8558-4836-bb2f-28fa99572b63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328654254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empt
y.328654254
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.3338540671
Short name T715
Test name
Test status
Simulation time 7084332182 ps
CPU time 55.32 seconds
Started Apr 25 03:11:58 PM PDT 24
Finished Apr 25 03:12:54 PM PDT 24
Peak memory 646968 kb
Host smart-6561af16-3fc2-4e6c-be68-4cc988174561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338540671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.3338540671
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.2321003313
Short name T926
Test name
Test status
Simulation time 2537485275 ps
CPU time 29.22 seconds
Started Apr 25 03:11:58 PM PDT 24
Finished Apr 25 03:12:29 PM PDT 24
Peak memory 422080 kb
Host smart-876138c9-2449-412a-a7fb-1100ecd25961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321003313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.2321003313
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.255068842
Short name T600
Test name
Test status
Simulation time 244335839 ps
CPU time 0.95 seconds
Started Apr 25 03:11:59 PM PDT 24
Finished Apr 25 03:12:01 PM PDT 24
Peak memory 203916 kb
Host smart-ab658dae-2dc5-43e3-81aa-2f4d4a6b3570
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255068842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fm
t.255068842
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.1035566355
Short name T1065
Test name
Test status
Simulation time 154428260 ps
CPU time 8.1 seconds
Started Apr 25 03:11:58 PM PDT 24
Finished Apr 25 03:12:08 PM PDT 24
Peak memory 204156 kb
Host smart-58e457a0-f0e7-4cc3-addd-c25f0aefaf35
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035566355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.1035566355
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.751845484
Short name T217
Test name
Test status
Simulation time 11121844958 ps
CPU time 152.09 seconds
Started Apr 25 03:12:01 PM PDT 24
Finished Apr 25 03:14:34 PM PDT 24
Peak memory 756316 kb
Host smart-923bcbff-027b-433e-886b-53a4a5f6c5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751845484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.751845484
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.2124146331
Short name T586
Test name
Test status
Simulation time 1319010211 ps
CPU time 1.83 seconds
Started Apr 25 03:12:39 PM PDT 24
Finished Apr 25 03:12:43 PM PDT 24
Peak memory 204164 kb
Host smart-f6c948da-382c-4fa7-ae11-06bdb7e1b89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124146331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.2124146331
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.870253219
Short name T413
Test name
Test status
Simulation time 1503026655 ps
CPU time 21.45 seconds
Started Apr 25 03:12:10 PM PDT 24
Finished Apr 25 03:12:32 PM PDT 24
Peak memory 315568 kb
Host smart-a4886d11-bcf3-444e-9d25-5e7353f895ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870253219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.870253219
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.350535784
Short name T995
Test name
Test status
Simulation time 81860497 ps
CPU time 0.65 seconds
Started Apr 25 03:11:57 PM PDT 24
Finished Apr 25 03:11:59 PM PDT 24
Peak memory 203840 kb
Host smart-43f1b24f-597c-443a-91f2-21547bb9237b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350535784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.350535784
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.3434824644
Short name T73
Test name
Test status
Simulation time 3022718994 ps
CPU time 26.36 seconds
Started Apr 25 03:12:02 PM PDT 24
Finished Apr 25 03:12:30 PM PDT 24
Peak memory 228728 kb
Host smart-5a998676-ee6e-445d-85b6-9d1953fa9914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434824644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.3434824644
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.3231776699
Short name T955
Test name
Test status
Simulation time 4258424626 ps
CPU time 31.31 seconds
Started Apr 25 03:12:01 PM PDT 24
Finished Apr 25 03:12:33 PM PDT 24
Peak memory 332948 kb
Host smart-84b0771c-9732-46d2-adaa-dea818cad083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231776699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.3231776699
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.800694462
Short name T220
Test name
Test status
Simulation time 36611991878 ps
CPU time 834.34 seconds
Started Apr 25 03:12:04 PM PDT 24
Finished Apr 25 03:26:00 PM PDT 24
Peak memory 1351736 kb
Host smart-cd3606c4-b258-4161-966e-acd5107cda04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800694462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.800694462
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.3729809038
Short name T288
Test name
Test status
Simulation time 737654837 ps
CPU time 20.99 seconds
Started Apr 25 03:12:13 PM PDT 24
Finished Apr 25 03:12:35 PM PDT 24
Peak memory 212412 kb
Host smart-79fa6bf7-7606-4eb0-bfa6-5942e19515b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729809038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.3729809038
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.3608519138
Short name T774
Test name
Test status
Simulation time 2219426672 ps
CPU time 4.68 seconds
Started Apr 25 03:12:10 PM PDT 24
Finished Apr 25 03:12:16 PM PDT 24
Peak memory 212440 kb
Host smart-ca8ad185-5385-499e-bcbf-441cfeb07d5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608519138 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.3608519138
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.1911309566
Short name T930
Test name
Test status
Simulation time 10235759404 ps
CPU time 26.76 seconds
Started Apr 25 03:12:03 PM PDT 24
Finished Apr 25 03:12:31 PM PDT 24
Peak memory 339516 kb
Host smart-b4028062-2e37-4e4e-b4d4-c5dc6d6d4864
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911309566 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.1911309566
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.2883021430
Short name T896
Test name
Test status
Simulation time 10463734684 ps
CPU time 11.7 seconds
Started Apr 25 03:12:04 PM PDT 24
Finished Apr 25 03:12:17 PM PDT 24
Peak memory 271052 kb
Host smart-d5195c7b-2a55-464e-bf8b-060dff6dfe4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883021430 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.2883021430
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.2224480240
Short name T256
Test name
Test status
Simulation time 2602861226 ps
CPU time 2.41 seconds
Started Apr 25 03:12:09 PM PDT 24
Finished Apr 25 03:12:13 PM PDT 24
Peak memory 204300 kb
Host smart-83bbd81a-c3f9-44aa-b678-8cb8525a03b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224480240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.2224480240
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.2625435336
Short name T1061
Test name
Test status
Simulation time 560811400 ps
CPU time 3.47 seconds
Started Apr 25 03:12:03 PM PDT 24
Finished Apr 25 03:12:07 PM PDT 24
Peak memory 204200 kb
Host smart-60f68e36-3376-45e1-97e8-6512a8d8529f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625435336 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.2625435336
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.883320921
Short name T1124
Test name
Test status
Simulation time 10608405237 ps
CPU time 159.51 seconds
Started Apr 25 03:12:03 PM PDT 24
Finished Apr 25 03:14:44 PM PDT 24
Peak memory 2629960 kb
Host smart-ee31be6d-6265-4774-a8a5-be33960c69a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883320921 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.883320921
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3441722447
Short name T106
Test name
Test status
Simulation time 818893216 ps
CPU time 31.1 seconds
Started Apr 25 03:12:05 PM PDT 24
Finished Apr 25 03:12:36 PM PDT 24
Peak memory 204144 kb
Host smart-892f0b23-6440-4908-a88a-4f862aaa6762
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441722447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3441722447
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.1938142848
Short name T1081
Test name
Test status
Simulation time 9790361876 ps
CPU time 82.8 seconds
Started Apr 25 03:12:03 PM PDT 24
Finished Apr 25 03:13:27 PM PDT 24
Peak memory 207296 kb
Host smart-a66192c8-ef11-4a67-8eee-2874a0e5b53a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938142848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.1938142848
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.444136968
Short name T575
Test name
Test status
Simulation time 36125976074 ps
CPU time 464.03 seconds
Started Apr 25 03:12:04 PM PDT 24
Finished Apr 25 03:19:49 PM PDT 24
Peak memory 4247268 kb
Host smart-524d1bed-ac63-4cad-b5ef-7218c8f4e7cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444136968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c
_target_stress_wr.444136968
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1018146809
Short name T30
Test name
Test status
Simulation time 29400101706 ps
CPU time 657.88 seconds
Started Apr 25 03:12:02 PM PDT 24
Finished Apr 25 03:23:01 PM PDT 24
Peak memory 1758460 kb
Host smart-d90363f6-b296-44f3-bdad-a94e666c01c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018146809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1018146809
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.483510372
Short name T1320
Test name
Test status
Simulation time 7766323869 ps
CPU time 7.76 seconds
Started Apr 25 03:12:04 PM PDT 24
Finished Apr 25 03:12:13 PM PDT 24
Peak memory 220304 kb
Host smart-4dab259e-8c2c-45f2-a443-c380641d0ddb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483510372 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_timeout.483510372
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_unexp_stop.782290636
Short name T539
Test name
Test status
Simulation time 2702385737 ps
CPU time 7.46 seconds
Started Apr 25 03:12:06 PM PDT 24
Finished Apr 25 03:12:14 PM PDT 24
Peak memory 218520 kb
Host smart-e75fd0bd-be27-4075-889c-6dc9743be990
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782290636 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_unexp_stop.782290636
Directory /workspace/32.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/33.i2c_alert_test.2224671936
Short name T659
Test name
Test status
Simulation time 66330781 ps
CPU time 0.64 seconds
Started Apr 25 03:12:18 PM PDT 24
Finished Apr 25 03:12:19 PM PDT 24
Peak memory 203892 kb
Host smart-788b9c47-dee5-4314-93c3-097046e4e20f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224671936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.2224671936
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.3393942108
Short name T750
Test name
Test status
Simulation time 95882334 ps
CPU time 1.77 seconds
Started Apr 25 03:12:13 PM PDT 24
Finished Apr 25 03:12:16 PM PDT 24
Peak memory 212472 kb
Host smart-36aac62c-cac6-47c7-a93b-7f324fb70f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393942108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.3393942108
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.235079402
Short name T504
Test name
Test status
Simulation time 697717452 ps
CPU time 17.53 seconds
Started Apr 25 03:12:13 PM PDT 24
Finished Apr 25 03:12:31 PM PDT 24
Peak memory 241980 kb
Host smart-f87af8ac-9833-4598-b9d2-62cc12c882e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235079402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empt
y.235079402
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.1234610444
Short name T976
Test name
Test status
Simulation time 2194427085 ps
CPU time 73.66 seconds
Started Apr 25 03:12:15 PM PDT 24
Finished Apr 25 03:13:30 PM PDT 24
Peak memory 644080 kb
Host smart-85195a95-897b-4b59-b967-f22b81aabc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234610444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.1234610444
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2044505185
Short name T401
Test name
Test status
Simulation time 8201260437 ps
CPU time 147.63 seconds
Started Apr 25 03:12:08 PM PDT 24
Finished Apr 25 03:14:37 PM PDT 24
Peak memory 667844 kb
Host smart-bcc90b7a-1674-4a66-b0c9-3dd443b942eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044505185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2044505185
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.3854694431
Short name T184
Test name
Test status
Simulation time 100650168 ps
CPU time 0.84 seconds
Started Apr 25 03:12:08 PM PDT 24
Finished Apr 25 03:12:10 PM PDT 24
Peak memory 203992 kb
Host smart-30352cb1-babc-4421-9231-749e00f004d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854694431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.3854694431
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.4161423029
Short name T182
Test name
Test status
Simulation time 479678122 ps
CPU time 6.31 seconds
Started Apr 25 03:12:14 PM PDT 24
Finished Apr 25 03:12:21 PM PDT 24
Peak memory 204184 kb
Host smart-234c5452-6d8d-4fdd-861a-16b80fd2e213
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161423029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.4161423029
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.1060361747
Short name T35
Test name
Test status
Simulation time 4962394420 ps
CPU time 282.17 seconds
Started Apr 25 03:12:31 PM PDT 24
Finished Apr 25 03:17:14 PM PDT 24
Peak memory 1111668 kb
Host smart-8700e268-ec7c-4c9a-bb71-cf845073a638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060361747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.1060361747
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.3038306067
Short name T672
Test name
Test status
Simulation time 218533581 ps
CPU time 8.52 seconds
Started Apr 25 03:12:18 PM PDT 24
Finished Apr 25 03:12:28 PM PDT 24
Peak memory 204192 kb
Host smart-599e8e11-a946-4032-b377-bdc8c67cfbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038306067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.3038306067
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.2343579225
Short name T350
Test name
Test status
Simulation time 2092197017 ps
CPU time 91.86 seconds
Started Apr 25 03:12:20 PM PDT 24
Finished Apr 25 03:13:53 PM PDT 24
Peak memory 330924 kb
Host smart-5a43f10b-651f-43c9-9fc6-2b6bbb63f680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343579225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.2343579225
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.2452176191
Short name T168
Test name
Test status
Simulation time 51338335 ps
CPU time 0.68 seconds
Started Apr 25 03:12:10 PM PDT 24
Finished Apr 25 03:12:11 PM PDT 24
Peak memory 203864 kb
Host smart-e0f9387a-4329-4963-8f47-44087bafd7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452176191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.2452176191
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.1521082061
Short name T176
Test name
Test status
Simulation time 71148058332 ps
CPU time 806.74 seconds
Started Apr 25 03:12:15 PM PDT 24
Finished Apr 25 03:25:44 PM PDT 24
Peak memory 212460 kb
Host smart-24816a65-d221-494c-a3d4-3dfc8634dee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521082061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.1521082061
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.399166756
Short name T334
Test name
Test status
Simulation time 7452971657 ps
CPU time 27.91 seconds
Started Apr 25 03:12:10 PM PDT 24
Finished Apr 25 03:12:38 PM PDT 24
Peak memory 324264 kb
Host smart-8ff516f6-3d45-4e97-8be3-64dc19981355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399166756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.399166756
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.3462774274
Short name T44
Test name
Test status
Simulation time 46474340013 ps
CPU time 266.21 seconds
Started Apr 25 03:12:15 PM PDT 24
Finished Apr 25 03:16:43 PM PDT 24
Peak memory 1236536 kb
Host smart-e8e0e54c-5105-4be8-8a2d-1a841d0c2583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462774274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.3462774274
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.1975210114
Short name T1261
Test name
Test status
Simulation time 3553000171 ps
CPU time 25.91 seconds
Started Apr 25 03:12:19 PM PDT 24
Finished Apr 25 03:12:46 PM PDT 24
Peak memory 212372 kb
Host smart-8fec1d87-7991-4588-b056-233af8cded14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975210114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.1975210114
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.4092268599
Short name T1079
Test name
Test status
Simulation time 579921477 ps
CPU time 3.15 seconds
Started Apr 25 03:12:19 PM PDT 24
Finished Apr 25 03:12:24 PM PDT 24
Peak memory 204244 kb
Host smart-c3a6a267-e96f-4990-8d4c-1b5096cedc0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092268599 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.4092268599
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.620954154
Short name T723
Test name
Test status
Simulation time 10074382816 ps
CPU time 40.81 seconds
Started Apr 25 03:12:15 PM PDT 24
Finished Apr 25 03:12:57 PM PDT 24
Peak memory 339036 kb
Host smart-376b94b6-a0a7-49f0-97eb-56808cc25b02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620954154 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_acq.620954154
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.2441965530
Short name T532
Test name
Test status
Simulation time 10287031208 ps
CPU time 13.6 seconds
Started Apr 25 03:12:18 PM PDT 24
Finished Apr 25 03:12:33 PM PDT 24
Peak memory 288408 kb
Host smart-97031658-0ef5-4072-b5ad-1f4c3128613d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441965530 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.2441965530
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.1348911351
Short name T780
Test name
Test status
Simulation time 1505046191 ps
CPU time 2.48 seconds
Started Apr 25 03:12:20 PM PDT 24
Finished Apr 25 03:12:23 PM PDT 24
Peak memory 204208 kb
Host smart-d7aaffeb-69b9-4806-9b5f-4f31a6e1ec60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348911351 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.1348911351
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.4141015215
Short name T282
Test name
Test status
Simulation time 18008457487 ps
CPU time 7.16 seconds
Started Apr 25 03:12:16 PM PDT 24
Finished Apr 25 03:12:24 PM PDT 24
Peak memory 220544 kb
Host smart-d085ee5e-e8f7-4fd9-8fe9-235a651dcc9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141015215 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.4141015215
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.2433198610
Short name T1128
Test name
Test status
Simulation time 16737287779 ps
CPU time 343.46 seconds
Started Apr 25 03:12:15 PM PDT 24
Finished Apr 25 03:17:59 PM PDT 24
Peak memory 4093604 kb
Host smart-3e078c4d-9dc0-40a8-bce4-dfb7ff6f920f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433198610 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.2433198610
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.3888224388
Short name T379
Test name
Test status
Simulation time 1273847022 ps
CPU time 52.11 seconds
Started Apr 25 03:12:16 PM PDT 24
Finished Apr 25 03:13:09 PM PDT 24
Peak memory 204148 kb
Host smart-cb1419cd-0f72-4827-bc5f-a55067b941fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888224388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.3888224388
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.529249875
Short name T915
Test name
Test status
Simulation time 1649024938 ps
CPU time 20.64 seconds
Started Apr 25 03:12:20 PM PDT 24
Finished Apr 25 03:12:42 PM PDT 24
Peak memory 223384 kb
Host smart-479c679c-a56e-4312-b13c-b43946ac0f8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529249875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_rd.529249875
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.652760841
Short name T797
Test name
Test status
Simulation time 7428950653 ps
CPU time 4.75 seconds
Started Apr 25 03:12:15 PM PDT 24
Finished Apr 25 03:12:21 PM PDT 24
Peak memory 204204 kb
Host smart-ebd0f071-fbd3-46d4-8b9a-93720d013097
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652760841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_wr.652760841
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.1893116208
Short name T249
Test name
Test status
Simulation time 28350978750 ps
CPU time 228.5 seconds
Started Apr 25 03:12:14 PM PDT 24
Finished Apr 25 03:16:03 PM PDT 24
Peak memory 1619932 kb
Host smart-55b27ecf-2c28-49a2-9ca0-011d7c764236
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893116208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.1893116208
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.3943143736
Short name T227
Test name
Test status
Simulation time 5957283011 ps
CPU time 7.35 seconds
Started Apr 25 03:12:14 PM PDT 24
Finished Apr 25 03:12:22 PM PDT 24
Peak memory 217108 kb
Host smart-8d10e38f-eca8-41b6-a9a3-c20f09c9726d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943143736 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.3943143736
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.3439942309
Short name T537
Test name
Test status
Simulation time 22961620 ps
CPU time 0.61 seconds
Started Apr 25 03:12:39 PM PDT 24
Finished Apr 25 03:12:41 PM PDT 24
Peak memory 203728 kb
Host smart-d4883a0e-366d-41ac-b287-4a383be45b91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439942309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.3439942309
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.4167524522
Short name T880
Test name
Test status
Simulation time 400774537 ps
CPU time 1.46 seconds
Started Apr 25 03:12:24 PM PDT 24
Finished Apr 25 03:12:26 PM PDT 24
Peak memory 212500 kb
Host smart-338dd559-4851-4092-a03e-a81364475af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167524522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.4167524522
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.441411021
Short name T381
Test name
Test status
Simulation time 870468211 ps
CPU time 6.93 seconds
Started Apr 25 03:12:28 PM PDT 24
Finished Apr 25 03:12:36 PM PDT 24
Peak memory 270416 kb
Host smart-829abfdb-9286-4325-a399-9fb1fd346cc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441411021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empt
y.441411021
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.2037086053
Short name T54
Test name
Test status
Simulation time 1227398771 ps
CPU time 81.09 seconds
Started Apr 25 03:12:26 PM PDT 24
Finished Apr 25 03:13:48 PM PDT 24
Peak memory 476636 kb
Host smart-542df439-c3ce-4ad4-b459-d0debc7aecc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037086053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.2037086053
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.176152364
Short name T664
Test name
Test status
Simulation time 9642902221 ps
CPU time 56.24 seconds
Started Apr 25 03:12:20 PM PDT 24
Finished Apr 25 03:13:17 PM PDT 24
Peak memory 659572 kb
Host smart-7abbae87-cef2-4387-94c8-4f88699f4b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176152364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.176152364
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.4089306758
Short name T1345
Test name
Test status
Simulation time 436038806 ps
CPU time 0.96 seconds
Started Apr 25 03:12:27 PM PDT 24
Finished Apr 25 03:12:29 PM PDT 24
Peak memory 204000 kb
Host smart-580f1b94-7916-4378-b7b8-377b169b8121
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089306758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.4089306758
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.725255806
Short name T1175
Test name
Test status
Simulation time 133390088 ps
CPU time 3.93 seconds
Started Apr 25 03:12:26 PM PDT 24
Finished Apr 25 03:12:31 PM PDT 24
Peak memory 223092 kb
Host smart-3ea8ba8b-397b-456a-98c3-355aee9bb62d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725255806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.
725255806
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.4058731704
Short name T353
Test name
Test status
Simulation time 10984633545 ps
CPU time 76.08 seconds
Started Apr 25 03:12:18 PM PDT 24
Finished Apr 25 03:13:35 PM PDT 24
Peak memory 862708 kb
Host smart-408a12f1-6f43-4cb6-9b3a-62785967ff7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058731704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.4058731704
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.98355503
Short name T1299
Test name
Test status
Simulation time 2477536869 ps
CPU time 7.23 seconds
Started Apr 25 03:12:36 PM PDT 24
Finished Apr 25 03:12:44 PM PDT 24
Peak memory 204196 kb
Host smart-d98abafb-59b0-4611-aa31-4f7ad29beacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98355503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.98355503
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.2856547555
Short name T461
Test name
Test status
Simulation time 7041409301 ps
CPU time 24.08 seconds
Started Apr 25 03:12:40 PM PDT 24
Finished Apr 25 03:13:05 PM PDT 24
Peak memory 282188 kb
Host smart-73f73229-6634-4a32-9251-44998bce169c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856547555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.2856547555
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.1524927130
Short name T971
Test name
Test status
Simulation time 21346206 ps
CPU time 0.65 seconds
Started Apr 25 03:12:19 PM PDT 24
Finished Apr 25 03:12:21 PM PDT 24
Peak memory 203824 kb
Host smart-5c7cecbc-60b3-4498-9747-8bc9eba4cf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524927130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1524927130
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.3404452620
Short name T411
Test name
Test status
Simulation time 6225397881 ps
CPU time 42.92 seconds
Started Apr 25 03:12:25 PM PDT 24
Finished Apr 25 03:13:09 PM PDT 24
Peak memory 215944 kb
Host smart-6812075f-fe4e-4d4d-9553-1f60aeeb5830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404452620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.3404452620
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.386040475
Short name T1195
Test name
Test status
Simulation time 7355190088 ps
CPU time 28.68 seconds
Started Apr 25 03:12:19 PM PDT 24
Finished Apr 25 03:12:48 PM PDT 24
Peak memory 314416 kb
Host smart-2917fbf7-bd2b-4212-a3fb-c8de608607f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386040475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.386040475
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.2130834821
Short name T219
Test name
Test status
Simulation time 6044390695 ps
CPU time 235.51 seconds
Started Apr 25 03:12:27 PM PDT 24
Finished Apr 25 03:16:23 PM PDT 24
Peak memory 1055100 kb
Host smart-7a9b5fb2-94a2-4591-b915-61e7a141028b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130834821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.2130834821
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.3642757074
Short name T1069
Test name
Test status
Simulation time 1403501018 ps
CPU time 31.25 seconds
Started Apr 25 03:12:25 PM PDT 24
Finished Apr 25 03:12:57 PM PDT 24
Peak memory 212484 kb
Host smart-5023f904-437b-49bc-9265-451165ffdccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642757074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3642757074
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.138444765
Short name T556
Test name
Test status
Simulation time 1360166961 ps
CPU time 5.53 seconds
Started Apr 25 03:12:30 PM PDT 24
Finished Apr 25 03:12:36 PM PDT 24
Peak memory 214060 kb
Host smart-47fb168f-41a8-451d-938d-a834ddd2e2c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138444765 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.138444765
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.1761202049
Short name T753
Test name
Test status
Simulation time 10335522104 ps
CPU time 27 seconds
Started Apr 25 03:12:31 PM PDT 24
Finished Apr 25 03:12:59 PM PDT 24
Peak memory 341868 kb
Host smart-230bea45-c906-4de2-ab68-07c03683c144
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761202049 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.1761202049
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.2896638648
Short name T1090
Test name
Test status
Simulation time 10139938485 ps
CPU time 14.57 seconds
Started Apr 25 03:12:32 PM PDT 24
Finished Apr 25 03:12:47 PM PDT 24
Peak memory 275788 kb
Host smart-c28252a1-6ef2-4e48-97e5-ee32589f4130
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896638648 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.2896638648
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.1472625623
Short name T1205
Test name
Test status
Simulation time 1662441403 ps
CPU time 2.6 seconds
Started Apr 25 03:12:31 PM PDT 24
Finished Apr 25 03:12:34 PM PDT 24
Peak memory 204152 kb
Host smart-5c3b1dd2-dee0-40a3-9f89-9a6cfd7032db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472625623 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.1472625623
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.3186301575
Short name T812
Test name
Test status
Simulation time 3479043261 ps
CPU time 5.06 seconds
Started Apr 25 03:12:34 PM PDT 24
Finished Apr 25 03:12:39 PM PDT 24
Peak memory 214484 kb
Host smart-cb640f43-1a11-47f2-b38f-d1190a6aa94e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186301575 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.3186301575
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.2822883128
Short name T1293
Test name
Test status
Simulation time 26159300785 ps
CPU time 64.42 seconds
Started Apr 25 03:12:30 PM PDT 24
Finished Apr 25 03:13:35 PM PDT 24
Peak memory 1349340 kb
Host smart-57771ec1-f837-4187-a607-b4f4a93be3df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822883128 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.2822883128
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.2594946014
Short name T104
Test name
Test status
Simulation time 13637474269 ps
CPU time 17.79 seconds
Started Apr 25 03:12:28 PM PDT 24
Finished Apr 25 03:12:47 PM PDT 24
Peak memory 204268 kb
Host smart-82c6e181-9e76-4a87-b0c8-c39e5d5fd431
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594946014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.2594946014
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.4190337421
Short name T1119
Test name
Test status
Simulation time 1997078992 ps
CPU time 14.31 seconds
Started Apr 25 03:12:24 PM PDT 24
Finished Apr 25 03:12:39 PM PDT 24
Peak memory 214400 kb
Host smart-c87ddcaf-d78c-465d-92a3-34dcbed69a38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190337421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.4190337421
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.2723458940
Short name T841
Test name
Test status
Simulation time 16565766023 ps
CPU time 30.71 seconds
Started Apr 25 03:12:25 PM PDT 24
Finished Apr 25 03:12:57 PM PDT 24
Peak memory 204248 kb
Host smart-ddac0ec5-59fb-4ab3-810a-c395b642e43b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723458940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.2723458940
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.1652088668
Short name T550
Test name
Test status
Simulation time 11931231497 ps
CPU time 601.34 seconds
Started Apr 25 03:12:24 PM PDT 24
Finished Apr 25 03:22:26 PM PDT 24
Peak memory 1762148 kb
Host smart-ba7e58e4-eec4-4f70-a522-5c85356b1ce4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652088668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.1652088668
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.30608947
Short name T320
Test name
Test status
Simulation time 4659295005 ps
CPU time 7.2 seconds
Started Apr 25 03:12:32 PM PDT 24
Finished Apr 25 03:12:40 PM PDT 24
Peak memory 220484 kb
Host smart-b8b21612-9991-42ed-acf8-c19f919d448f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30608947 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_timeout.30608947
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.866250927
Short name T294
Test name
Test status
Simulation time 30164749 ps
CPU time 0.63 seconds
Started Apr 25 03:12:44 PM PDT 24
Finished Apr 25 03:12:46 PM PDT 24
Peak memory 203868 kb
Host smart-0d9c7d27-3138-4d9e-84c4-dee4194f1d74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866250927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.866250927
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.3029302442
Short name T276
Test name
Test status
Simulation time 230631400 ps
CPU time 1.67 seconds
Started Apr 25 03:12:38 PM PDT 24
Finished Apr 25 03:12:41 PM PDT 24
Peak memory 216500 kb
Host smart-615fad31-7090-4b6d-9dff-fc9832c57b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029302442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.3029302442
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.2569215283
Short name T1232
Test name
Test status
Simulation time 1073724115 ps
CPU time 6.46 seconds
Started Apr 25 03:12:38 PM PDT 24
Finished Apr 25 03:12:45 PM PDT 24
Peak memory 262272 kb
Host smart-57827ef9-1c2b-4e74-8813-023d952848ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569215283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.2569215283
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.3274220008
Short name T45
Test name
Test status
Simulation time 8790619438 ps
CPU time 200.14 seconds
Started Apr 25 03:12:40 PM PDT 24
Finished Apr 25 03:16:01 PM PDT 24
Peak memory 727780 kb
Host smart-3619c246-a03f-49a9-8ca4-1cb2d766b176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274220008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.3274220008
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.3657095078
Short name T933
Test name
Test status
Simulation time 1235995115 ps
CPU time 82.68 seconds
Started Apr 25 03:12:37 PM PDT 24
Finished Apr 25 03:14:00 PM PDT 24
Peak memory 495336 kb
Host smart-f578a4bf-75db-4f2d-9000-780f26b799e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657095078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.3657095078
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.2517958028
Short name T553
Test name
Test status
Simulation time 265722904 ps
CPU time 1.05 seconds
Started Apr 25 03:12:39 PM PDT 24
Finished Apr 25 03:12:41 PM PDT 24
Peak memory 204056 kb
Host smart-8b525dcb-95b2-4d7b-adb9-08a0ffae5d79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517958028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.2517958028
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.3089834231
Short name T530
Test name
Test status
Simulation time 699944381 ps
CPU time 5.71 seconds
Started Apr 25 03:12:38 PM PDT 24
Finished Apr 25 03:12:44 PM PDT 24
Peak memory 242124 kb
Host smart-348ca492-1113-4d02-9d2a-202b588b847b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089834231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.3089834231
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.2164060260
Short name T564
Test name
Test status
Simulation time 3938957537 ps
CPU time 268.32 seconds
Started Apr 25 03:12:38 PM PDT 24
Finished Apr 25 03:17:07 PM PDT 24
Peak memory 1100172 kb
Host smart-a2890ab4-9e32-440d-8c53-c0618cde2a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164060260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.2164060260
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.892132197
Short name T679
Test name
Test status
Simulation time 1145904837 ps
CPU time 9.45 seconds
Started Apr 25 03:12:44 PM PDT 24
Finished Apr 25 03:12:55 PM PDT 24
Peak memory 204132 kb
Host smart-de6f6e83-7452-4094-96f4-13e76d59fd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892132197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.892132197
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.3204069996
Short name T63
Test name
Test status
Simulation time 1926779010 ps
CPU time 40.3 seconds
Started Apr 25 03:12:43 PM PDT 24
Finished Apr 25 03:13:25 PM PDT 24
Peak memory 369008 kb
Host smart-04df65f4-39d1-4b9c-8997-b7da4e44006e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204069996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.3204069996
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.1426357681
Short name T433
Test name
Test status
Simulation time 49705151 ps
CPU time 0.66 seconds
Started Apr 25 03:12:36 PM PDT 24
Finished Apr 25 03:12:38 PM PDT 24
Peak memory 203856 kb
Host smart-a89de2dc-c6f1-4bec-8a81-770a97ec543f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426357681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.1426357681
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.815345935
Short name T908
Test name
Test status
Simulation time 1539923151 ps
CPU time 12.07 seconds
Started Apr 25 03:12:36 PM PDT 24
Finished Apr 25 03:12:49 PM PDT 24
Peak memory 322156 kb
Host smart-47266e80-0ba7-40c5-8182-b0e06420029d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815345935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.815345935
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.224743100
Short name T1140
Test name
Test status
Simulation time 9170598425 ps
CPU time 55.84 seconds
Started Apr 25 03:12:37 PM PDT 24
Finished Apr 25 03:13:34 PM PDT 24
Peak memory 315088 kb
Host smart-deba74af-d0bf-4689-a250-16579cdc239c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224743100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.224743100
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.2983069600
Short name T325
Test name
Test status
Simulation time 27902741314 ps
CPU time 746.86 seconds
Started Apr 25 03:12:40 PM PDT 24
Finished Apr 25 03:25:08 PM PDT 24
Peak memory 1293692 kb
Host smart-9fdb9ed5-e074-4abb-9535-5d09b957bbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983069600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.2983069600
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.629809462
Short name T1131
Test name
Test status
Simulation time 515762136 ps
CPU time 22.21 seconds
Started Apr 25 03:12:38 PM PDT 24
Finished Apr 25 03:13:02 PM PDT 24
Peak memory 212396 kb
Host smart-fedfc42d-e333-4f38-8630-9bb7c477a343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629809462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.629809462
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.2286603905
Short name T455
Test name
Test status
Simulation time 17690443547 ps
CPU time 4.72 seconds
Started Apr 25 03:12:41 PM PDT 24
Finished Apr 25 03:12:47 PM PDT 24
Peak memory 212508 kb
Host smart-7a5d612b-185a-4af0-b388-a7a3d9f3bd3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286603905 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.2286603905
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.2271438853
Short name T391
Test name
Test status
Simulation time 10065309165 ps
CPU time 64.46 seconds
Started Apr 25 03:12:40 PM PDT 24
Finished Apr 25 03:13:45 PM PDT 24
Peak memory 446548 kb
Host smart-c578206a-5c17-4a32-99a8-255436c9f8d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271438853 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.2271438853
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.1589349272
Short name T562
Test name
Test status
Simulation time 10440782676 ps
CPU time 14.36 seconds
Started Apr 25 03:12:37 PM PDT 24
Finished Apr 25 03:12:53 PM PDT 24
Peak memory 303720 kb
Host smart-53424f9f-21b5-4902-8f1e-b212a16d67c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589349272 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.1589349272
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.4069936097
Short name T810
Test name
Test status
Simulation time 974012504 ps
CPU time 2.83 seconds
Started Apr 25 03:12:43 PM PDT 24
Finished Apr 25 03:12:48 PM PDT 24
Peak memory 204148 kb
Host smart-f03c0fc9-320b-4be8-a0bc-f5e894bf22d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069936097 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.4069936097
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.2508682745
Short name T631
Test name
Test status
Simulation time 1136537514 ps
CPU time 3.23 seconds
Started Apr 25 03:12:36 PM PDT 24
Finished Apr 25 03:12:40 PM PDT 24
Peak memory 204192 kb
Host smart-340b7274-abf4-40f7-88bf-0ba3bbda2bd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508682745 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.2508682745
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.1040821153
Short name T828
Test name
Test status
Simulation time 9618835439 ps
CPU time 46.15 seconds
Started Apr 25 03:12:37 PM PDT 24
Finished Apr 25 03:13:24 PM PDT 24
Peak memory 1226972 kb
Host smart-9e3645f6-1b1b-4e11-a2f3-7c474d1e7a03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040821153 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.1040821153
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.2119717272
Short name T653
Test name
Test status
Simulation time 1185612075 ps
CPU time 14.4 seconds
Started Apr 25 03:12:36 PM PDT 24
Finished Apr 25 03:12:51 PM PDT 24
Peak memory 204184 kb
Host smart-fc252a5d-9e3f-48ba-9694-234929490929
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119717272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.2119717272
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.1139832829
Short name T368
Test name
Test status
Simulation time 1051453915 ps
CPU time 4.37 seconds
Started Apr 25 03:12:36 PM PDT 24
Finished Apr 25 03:12:41 PM PDT 24
Peak memory 204184 kb
Host smart-7c2b47df-d512-4e8a-ba28-9e271a397514
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139832829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.1139832829
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.623606220
Short name T546
Test name
Test status
Simulation time 70399523160 ps
CPU time 3050.79 seconds
Started Apr 25 03:12:36 PM PDT 24
Finished Apr 25 04:03:28 PM PDT 24
Peak memory 12319856 kb
Host smart-ad0b6015-0605-463b-936c-798df151d454
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623606220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_wr.623606220
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.556528766
Short name T566
Test name
Test status
Simulation time 14406812320 ps
CPU time 191.83 seconds
Started Apr 25 03:12:36 PM PDT 24
Finished Apr 25 03:15:48 PM PDT 24
Peak memory 895540 kb
Host smart-c56dc87c-f415-4ebf-a556-15bba2635cf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556528766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_t
arget_stretch.556528766
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.2241643536
Short name T887
Test name
Test status
Simulation time 7607646975 ps
CPU time 7.28 seconds
Started Apr 25 03:12:36 PM PDT 24
Finished Apr 25 03:12:44 PM PDT 24
Peak memory 210536 kb
Host smart-458845c5-350c-41df-9da6-7e93a8d2285f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241643536 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.2241643536
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.1804882501
Short name T606
Test name
Test status
Simulation time 64823193 ps
CPU time 0.64 seconds
Started Apr 25 03:13:01 PM PDT 24
Finished Apr 25 03:13:03 PM PDT 24
Peak memory 203916 kb
Host smart-8998d8f9-9f3e-4100-959d-399aa6a428ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804882501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.1804882501
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.945081985
Short name T1233
Test name
Test status
Simulation time 356914787 ps
CPU time 1.54 seconds
Started Apr 25 03:12:48 PM PDT 24
Finished Apr 25 03:12:50 PM PDT 24
Peak memory 216604 kb
Host smart-797985e8-dfa9-406a-aa93-eec55e7858ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945081985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.945081985
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.2387993002
Short name T894
Test name
Test status
Simulation time 1520707410 ps
CPU time 20.8 seconds
Started Apr 25 03:12:44 PM PDT 24
Finished Apr 25 03:13:06 PM PDT 24
Peak memory 285976 kb
Host smart-035a7546-06c7-4039-85f6-ae73ac02bec8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387993002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.2387993002
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.4155858155
Short name T52
Test name
Test status
Simulation time 8127267638 ps
CPU time 149.7 seconds
Started Apr 25 03:12:40 PM PDT 24
Finished Apr 25 03:15:11 PM PDT 24
Peak memory 709132 kb
Host smart-77cbaab7-14d4-4ae6-b742-70c3622cdb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155858155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.4155858155
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.3170508110
Short name T957
Test name
Test status
Simulation time 2718665523 ps
CPU time 44.82 seconds
Started Apr 25 03:12:46 PM PDT 24
Finished Apr 25 03:13:31 PM PDT 24
Peak memory 519812 kb
Host smart-0053a76d-df62-4396-a4c4-f9e2f4f16594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170508110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.3170508110
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3039887707
Short name T1179
Test name
Test status
Simulation time 685964051 ps
CPU time 1.26 seconds
Started Apr 25 03:12:42 PM PDT 24
Finished Apr 25 03:12:44 PM PDT 24
Peak memory 204164 kb
Host smart-e1741c7b-59cd-41f1-8095-0ecf7fb39bb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039887707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3039887707
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.2364510144
Short name T257
Test name
Test status
Simulation time 1639904974 ps
CPU time 4.53 seconds
Started Apr 25 03:12:43 PM PDT 24
Finished Apr 25 03:12:48 PM PDT 24
Peak memory 204124 kb
Host smart-5746cec9-b82f-4725-8f1d-61d8320bd3f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364510144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.2364510144
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.1283598365
Short name T284
Test name
Test status
Simulation time 3197317792 ps
CPU time 87.64 seconds
Started Apr 25 03:12:43 PM PDT 24
Finished Apr 25 03:14:12 PM PDT 24
Peak memory 884680 kb
Host smart-b52b0daa-25a1-475a-83b2-b79839bd6643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283598365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.1283598365
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.1269581983
Short name T994
Test name
Test status
Simulation time 1270511839 ps
CPU time 8.84 seconds
Started Apr 25 03:13:01 PM PDT 24
Finished Apr 25 03:13:11 PM PDT 24
Peak memory 204164 kb
Host smart-deb7cf74-c6eb-4256-8ae7-7f507804eb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269581983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.1269581983
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.3226104431
Short name T1095
Test name
Test status
Simulation time 1169397673 ps
CPU time 16.88 seconds
Started Apr 25 03:13:03 PM PDT 24
Finished Apr 25 03:13:21 PM PDT 24
Peak memory 279560 kb
Host smart-e4676e43-c447-4b06-94a1-ebc7e6aa2172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226104431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.3226104431
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.2092900677
Short name T847
Test name
Test status
Simulation time 85554462 ps
CPU time 0.66 seconds
Started Apr 25 03:12:42 PM PDT 24
Finished Apr 25 03:12:44 PM PDT 24
Peak memory 203856 kb
Host smart-f005a27b-d5cf-401a-8e73-323c30398a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092900677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.2092900677
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.408441526
Short name T266
Test name
Test status
Simulation time 2622861241 ps
CPU time 38.76 seconds
Started Apr 25 03:12:46 PM PDT 24
Finished Apr 25 03:13:25 PM PDT 24
Peak memory 236992 kb
Host smart-f5fa2f30-956d-420b-a540-91c11c7515e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408441526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.408441526
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.1282660560
Short name T635
Test name
Test status
Simulation time 1837016906 ps
CPU time 18.5 seconds
Started Apr 25 03:12:46 PM PDT 24
Finished Apr 25 03:13:05 PM PDT 24
Peak memory 283652 kb
Host smart-23570ded-72dc-41a3-8716-6c3841b4ef39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282660560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.1282660560
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.2095999799
Short name T186
Test name
Test status
Simulation time 53862702756 ps
CPU time 1639.08 seconds
Started Apr 25 03:12:50 PM PDT 24
Finished Apr 25 03:40:10 PM PDT 24
Peak memory 1800356 kb
Host smart-bc1e54c7-4aec-4884-897c-38083e261188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095999799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.2095999799
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.316321214
Short name T388
Test name
Test status
Simulation time 1438139226 ps
CPU time 12.55 seconds
Started Apr 25 03:12:43 PM PDT 24
Finished Apr 25 03:12:56 PM PDT 24
Peak memory 220568 kb
Host smart-6ee8544f-74f8-4ee5-a914-d4d79317cef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316321214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.316321214
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.1549474234
Short name T929
Test name
Test status
Simulation time 2316571116 ps
CPU time 5.29 seconds
Started Apr 25 03:13:00 PM PDT 24
Finished Apr 25 03:13:06 PM PDT 24
Peak memory 212520 kb
Host smart-cdb3fab0-f1d0-48bb-a35f-cf524336098d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549474234 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.1549474234
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.3651670486
Short name T371
Test name
Test status
Simulation time 10137902446 ps
CPU time 27.36 seconds
Started Apr 25 03:12:48 PM PDT 24
Finished Apr 25 03:13:16 PM PDT 24
Peak memory 354628 kb
Host smart-1e329730-8b98-45dc-a7ba-85f4d6f057aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651670486 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.3651670486
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.2170828616
Short name T255
Test name
Test status
Simulation time 10376765495 ps
CPU time 12.79 seconds
Started Apr 25 03:12:47 PM PDT 24
Finished Apr 25 03:13:00 PM PDT 24
Peak memory 273440 kb
Host smart-a285d30f-6282-4e9d-85ff-f601207068f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170828616 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.2170828616
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.186564273
Short name T1194
Test name
Test status
Simulation time 558806466 ps
CPU time 3.03 seconds
Started Apr 25 03:13:00 PM PDT 24
Finished Apr 25 03:13:05 PM PDT 24
Peak memory 204140 kb
Host smart-1dc3eb8a-2fb5-4178-a8c9-202fb36e3732
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186564273 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 36.i2c_target_hrst.186564273
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.789323311
Short name T236
Test name
Test status
Simulation time 863470978 ps
CPU time 4.29 seconds
Started Apr 25 03:12:48 PM PDT 24
Finished Apr 25 03:12:53 PM PDT 24
Peak memory 204200 kb
Host smart-7a6c1bb8-89ce-4c67-92b8-ebfb3614166b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789323311 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_intr_smoke.789323311
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.3032821747
Short name T450
Test name
Test status
Simulation time 22483009316 ps
CPU time 55.03 seconds
Started Apr 25 03:12:49 PM PDT 24
Finished Apr 25 03:13:45 PM PDT 24
Peak memory 1272460 kb
Host smart-d9d3ba1f-70b1-41b9-8bee-7c3a53026b4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032821747 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.3032821747
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.1284542806
Short name T1161
Test name
Test status
Simulation time 5701770406 ps
CPU time 22.14 seconds
Started Apr 25 03:12:48 PM PDT 24
Finished Apr 25 03:13:11 PM PDT 24
Peak memory 204272 kb
Host smart-c9c5e068-037c-4027-9d73-49f1fb223a75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284542806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.1284542806
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.2775894486
Short name T1252
Test name
Test status
Simulation time 25961984028 ps
CPU time 9.93 seconds
Started Apr 25 03:12:47 PM PDT 24
Finished Apr 25 03:12:58 PM PDT 24
Peak memory 254772 kb
Host smart-f9ee37be-0573-45be-bff5-32f8313668ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775894486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.2775894486
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.234752328
Short name T200
Test name
Test status
Simulation time 25517314968 ps
CPU time 119.73 seconds
Started Apr 25 03:12:49 PM PDT 24
Finished Apr 25 03:14:50 PM PDT 24
Peak memory 604008 kb
Host smart-b2c58f7c-aa38-45af-8da8-8ed3cb94a0fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234752328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_t
arget_stretch.234752328
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.2605841425
Short name T657
Test name
Test status
Simulation time 1681848344 ps
CPU time 7.05 seconds
Started Apr 25 03:12:49 PM PDT 24
Finished Apr 25 03:12:57 PM PDT 24
Peak memory 219816 kb
Host smart-46b86aea-d245-4f5a-be66-d7977421a3b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605841425 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.2605841425
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.270272887
Short name T699
Test name
Test status
Simulation time 14877174 ps
CPU time 0.62 seconds
Started Apr 25 03:13:08 PM PDT 24
Finished Apr 25 03:13:10 PM PDT 24
Peak memory 203912 kb
Host smart-0538f40c-8bc8-44ca-94d8-ec2942ecc8f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270272887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.270272887
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.3836742925
Short name T344
Test name
Test status
Simulation time 217931895 ps
CPU time 1.44 seconds
Started Apr 25 03:13:01 PM PDT 24
Finished Apr 25 03:13:04 PM PDT 24
Peak memory 212404 kb
Host smart-240bd7dd-127b-4f0a-b56a-cfc43543ec95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836742925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.3836742925
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.2316686072
Short name T287
Test name
Test status
Simulation time 814038936 ps
CPU time 21.39 seconds
Started Apr 25 03:13:01 PM PDT 24
Finished Apr 25 03:13:24 PM PDT 24
Peak memory 291404 kb
Host smart-aaa82bbe-cfb9-47b8-ae9c-6788229a41b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316686072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.2316686072
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.2633252555
Short name T906
Test name
Test status
Simulation time 1394937035 ps
CPU time 38.72 seconds
Started Apr 25 03:13:02 PM PDT 24
Finished Apr 25 03:13:42 PM PDT 24
Peak memory 536592 kb
Host smart-10a843a9-f751-4d66-bccd-dd79fce2e5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633252555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.2633252555
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.1941553370
Short name T1257
Test name
Test status
Simulation time 1853147754 ps
CPU time 59.06 seconds
Started Apr 25 03:13:00 PM PDT 24
Finished Apr 25 03:14:00 PM PDT 24
Peak memory 614192 kb
Host smart-f0f3abe5-6736-4dfe-9e33-0a8c1fe2620e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941553370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.1941553370
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.4165656012
Short name T873
Test name
Test status
Simulation time 414121489 ps
CPU time 1.14 seconds
Started Apr 25 03:13:00 PM PDT 24
Finished Apr 25 03:13:02 PM PDT 24
Peak memory 204000 kb
Host smart-7ff9a8be-0656-461a-8279-6d541da55c80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165656012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.4165656012
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.1750678782
Short name T945
Test name
Test status
Simulation time 121878597 ps
CPU time 3.25 seconds
Started Apr 25 03:13:03 PM PDT 24
Finished Apr 25 03:13:08 PM PDT 24
Peak memory 222060 kb
Host smart-b6c9149c-8011-4725-9ac9-d7bd617cc32b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750678782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.1750678782
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1524252768
Short name T43
Test name
Test status
Simulation time 11585570639 ps
CPU time 137.51 seconds
Started Apr 25 03:13:00 PM PDT 24
Finished Apr 25 03:15:19 PM PDT 24
Peak memory 675900 kb
Host smart-53b53d8c-9af5-4939-90c7-ea596d774d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524252768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1524252768
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.2040263627
Short name T1045
Test name
Test status
Simulation time 393913405 ps
CPU time 5.11 seconds
Started Apr 25 03:13:09 PM PDT 24
Finished Apr 25 03:13:14 PM PDT 24
Peak memory 204168 kb
Host smart-bbb85d2e-ca45-42f0-9624-a7fc5b11acb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040263627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.2040263627
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.258180719
Short name T323
Test name
Test status
Simulation time 1713278301 ps
CPU time 35.73 seconds
Started Apr 25 03:13:02 PM PDT 24
Finished Apr 25 03:13:39 PM PDT 24
Peak memory 347400 kb
Host smart-a2e060bd-a5ee-4d48-a6c7-86235f0ee299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258180719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.258180719
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.2720613852
Short name T698
Test name
Test status
Simulation time 27104914 ps
CPU time 0.72 seconds
Started Apr 25 03:13:00 PM PDT 24
Finished Apr 25 03:13:03 PM PDT 24
Peak memory 203824 kb
Host smart-01abbc83-4676-4c01-b31d-fa27b63f7558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720613852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.2720613852
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.1523911018
Short name T997
Test name
Test status
Simulation time 2572924883 ps
CPU time 30.9 seconds
Started Apr 25 03:13:01 PM PDT 24
Finished Apr 25 03:13:33 PM PDT 24
Peak memory 204236 kb
Host smart-592f98f6-88bb-4abd-8ddd-6e60a114a3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523911018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.1523911018
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.4207125760
Short name T231
Test name
Test status
Simulation time 967355381 ps
CPU time 17.54 seconds
Started Apr 25 03:12:59 PM PDT 24
Finished Apr 25 03:13:17 PM PDT 24
Peak memory 261216 kb
Host smart-1f3cff0d-b778-42f2-91d9-c7db24fbe567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207125760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.4207125760
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.3995433909
Short name T185
Test name
Test status
Simulation time 13107445138 ps
CPU time 1796.47 seconds
Started Apr 25 03:13:00 PM PDT 24
Finished Apr 25 03:42:58 PM PDT 24
Peak memory 2854344 kb
Host smart-9b452be8-b76d-433d-96c1-bcc9dbf99836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995433909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.3995433909
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.2419588865
Short name T811
Test name
Test status
Simulation time 1085939583 ps
CPU time 9.53 seconds
Started Apr 25 03:12:58 PM PDT 24
Finished Apr 25 03:13:08 PM PDT 24
Peak memory 212364 kb
Host smart-8ec23d0a-9580-4807-9261-3ca4bcc66a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419588865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.2419588865
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.2057863609
Short name T285
Test name
Test status
Simulation time 1178923611 ps
CPU time 5.36 seconds
Started Apr 25 03:13:03 PM PDT 24
Finished Apr 25 03:13:10 PM PDT 24
Peak memory 212348 kb
Host smart-70824b1b-b938-4429-91b1-d104618ed289
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057863609 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2057863609
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.3760840922
Short name T426
Test name
Test status
Simulation time 10157201794 ps
CPU time 12.86 seconds
Started Apr 25 03:13:01 PM PDT 24
Finished Apr 25 03:13:15 PM PDT 24
Peak memory 273776 kb
Host smart-03803bdd-c4c4-4849-ac4e-b683d64f6b42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760840922 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.3760840922
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.1090227516
Short name T1035
Test name
Test status
Simulation time 10084072638 ps
CPU time 76.08 seconds
Started Apr 25 03:13:03 PM PDT 24
Finished Apr 25 03:14:21 PM PDT 24
Peak memory 450332 kb
Host smart-992ffcef-100c-4242-ade6-d7bb31e341cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090227516 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.1090227516
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.3484181732
Short name T876
Test name
Test status
Simulation time 4096934065 ps
CPU time 2.4 seconds
Started Apr 25 03:13:00 PM PDT 24
Finished Apr 25 03:13:04 PM PDT 24
Peak memory 204272 kb
Host smart-a6e69759-ddda-48bd-828f-e6dd7409ef33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484181732 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.3484181732
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.2364766718
Short name T32
Test name
Test status
Simulation time 3839241701 ps
CPU time 5.22 seconds
Started Apr 25 03:13:01 PM PDT 24
Finished Apr 25 03:13:08 PM PDT 24
Peak memory 213032 kb
Host smart-bdc401de-7781-4daf-825e-7346582eac94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364766718 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.2364766718
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.3459942938
Short name T494
Test name
Test status
Simulation time 10068399188 ps
CPU time 46.63 seconds
Started Apr 25 03:13:03 PM PDT 24
Finished Apr 25 03:13:51 PM PDT 24
Peak memory 1220084 kb
Host smart-75a84ed4-f45f-4918-9ed0-8f67b08c211b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459942938 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.3459942938
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.3303968072
Short name T103
Test name
Test status
Simulation time 749027966 ps
CPU time 10.12 seconds
Started Apr 25 03:13:00 PM PDT 24
Finished Apr 25 03:13:11 PM PDT 24
Peak memory 204164 kb
Host smart-3ddbd6c8-b591-4432-84e9-d54040b37693
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303968072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.3303968072
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.3727030182
Short name T647
Test name
Test status
Simulation time 6033607093 ps
CPU time 22.94 seconds
Started Apr 25 03:12:59 PM PDT 24
Finished Apr 25 03:13:23 PM PDT 24
Peak memory 228760 kb
Host smart-bc231fbe-d920-42ab-a3a2-3309dfc5d8f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727030182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.3727030182
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.4285354347
Short name T1111
Test name
Test status
Simulation time 50327266683 ps
CPU time 134.83 seconds
Started Apr 25 03:13:01 PM PDT 24
Finished Apr 25 03:15:17 PM PDT 24
Peak memory 1765856 kb
Host smart-9acb42fd-3106-44e9-9912-895597c8dcdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285354347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.4285354347
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.3061402131
Short name T1092
Test name
Test status
Simulation time 15367348534 ps
CPU time 7.04 seconds
Started Apr 25 03:13:00 PM PDT 24
Finished Apr 25 03:13:09 PM PDT 24
Peak memory 212500 kb
Host smart-f4534185-f251-4fe5-87c6-9778c647df92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061402131 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.3061402131
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.2884175933
Short name T295
Test name
Test status
Simulation time 35682024 ps
CPU time 0.6 seconds
Started Apr 25 03:13:11 PM PDT 24
Finished Apr 25 03:13:13 PM PDT 24
Peak memory 203780 kb
Host smart-ebd7f736-96d1-4d92-9ee2-fb02c006ab75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884175933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.2884175933
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.2260093221
Short name T1052
Test name
Test status
Simulation time 103075244 ps
CPU time 1.26 seconds
Started Apr 25 03:13:08 PM PDT 24
Finished Apr 25 03:13:10 PM PDT 24
Peak memory 212444 kb
Host smart-e890c186-6d2d-485d-8a32-bb3e5be509a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260093221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.2260093221
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2738836605
Short name T1258
Test name
Test status
Simulation time 1111495064 ps
CPU time 2.21 seconds
Started Apr 25 03:13:08 PM PDT 24
Finished Apr 25 03:13:11 PM PDT 24
Peak memory 218048 kb
Host smart-7afacfd9-f988-4b24-8c17-36718e789d69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738836605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2738836605
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.2238334315
Short name T748
Test name
Test status
Simulation time 16716190995 ps
CPU time 37.72 seconds
Started Apr 25 03:13:08 PM PDT 24
Finished Apr 25 03:13:46 PM PDT 24
Peak memory 478364 kb
Host smart-425f0dd6-2ae3-4b07-90fc-03ad974df362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238334315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.2238334315
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.686578946
Short name T92
Test name
Test status
Simulation time 1815069552 ps
CPU time 53.01 seconds
Started Apr 25 03:13:09 PM PDT 24
Finished Apr 25 03:14:02 PM PDT 24
Peak memory 617572 kb
Host smart-8ebf786a-ce92-40de-9080-85a419173c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686578946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.686578946
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.3837249204
Short name T1214
Test name
Test status
Simulation time 137835295 ps
CPU time 1.02 seconds
Started Apr 25 03:13:07 PM PDT 24
Finished Apr 25 03:13:08 PM PDT 24
Peak memory 204100 kb
Host smart-860a570f-1eb5-4411-9bdf-6f812391ba0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837249204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.3837249204
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.1311040260
Short name T511
Test name
Test status
Simulation time 2182010474 ps
CPU time 9.08 seconds
Started Apr 25 03:13:08 PM PDT 24
Finished Apr 25 03:13:18 PM PDT 24
Peak memory 204232 kb
Host smart-f692ce22-619f-46f6-8e48-c0436993749c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311040260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.1311040260
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1660865986
Short name T247
Test name
Test status
Simulation time 4108629543 ps
CPU time 135.53 seconds
Started Apr 25 03:13:08 PM PDT 24
Finished Apr 25 03:15:25 PM PDT 24
Peak memory 712960 kb
Host smart-be4e0802-ad4d-40a3-a003-8ff15584a859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660865986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1660865986
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.1752249158
Short name T813
Test name
Test status
Simulation time 1040080613 ps
CPU time 18.91 seconds
Started Apr 25 03:13:14 PM PDT 24
Finished Apr 25 03:13:34 PM PDT 24
Peak memory 204196 kb
Host smart-943b05a3-208c-4f8d-8deb-4bccc4597804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752249158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.1752249158
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.2004745093
Short name T431
Test name
Test status
Simulation time 3705389809 ps
CPU time 28.04 seconds
Started Apr 25 03:13:13 PM PDT 24
Finished Apr 25 03:13:43 PM PDT 24
Peak memory 326796 kb
Host smart-0b8bcdf2-f992-4be4-8098-a85a502bc2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004745093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.2004745093
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.1391637873
Short name T427
Test name
Test status
Simulation time 51223803 ps
CPU time 0.67 seconds
Started Apr 25 03:13:07 PM PDT 24
Finished Apr 25 03:13:09 PM PDT 24
Peak memory 203868 kb
Host smart-3f9a71fa-a01c-4505-822b-b0d3b70c5a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391637873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1391637873
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.1475062831
Short name T423
Test name
Test status
Simulation time 7113350438 ps
CPU time 51.22 seconds
Started Apr 25 03:13:09 PM PDT 24
Finished Apr 25 03:14:01 PM PDT 24
Peak memory 573148 kb
Host smart-c1b1d0b1-9bd5-4d55-9b71-a98eabf6be0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475062831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.1475062831
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.79692833
Short name T1193
Test name
Test status
Simulation time 1863671267 ps
CPU time 65.96 seconds
Started Apr 25 03:13:07 PM PDT 24
Finished Apr 25 03:14:13 PM PDT 24
Peak memory 316992 kb
Host smart-18ec3f5f-a737-4643-93a5-177e7a14b535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79692833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.79692833
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.3527711186
Short name T670
Test name
Test status
Simulation time 30717366072 ps
CPU time 2040.2 seconds
Started Apr 25 03:13:09 PM PDT 24
Finished Apr 25 03:47:10 PM PDT 24
Peak memory 1780972 kb
Host smart-2b652282-8229-4747-b48b-895468c6cf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527711186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.3527711186
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.2323325703
Short name T1237
Test name
Test status
Simulation time 3163399992 ps
CPU time 15 seconds
Started Apr 25 03:13:06 PM PDT 24
Finished Apr 25 03:13:22 PM PDT 24
Peak memory 220100 kb
Host smart-31f5b53f-623e-4375-a62c-c758fb4372b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323325703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.2323325703
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.3775974993
Short name T687
Test name
Test status
Simulation time 894510031 ps
CPU time 3.71 seconds
Started Apr 25 03:13:15 PM PDT 24
Finished Apr 25 03:13:19 PM PDT 24
Peak memory 204172 kb
Host smart-f89a60b1-b513-4e2b-81c1-6c28f6740921
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775974993 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.3775974993
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.498069893
Short name T93
Test name
Test status
Simulation time 10201493105 ps
CPU time 29.01 seconds
Started Apr 25 03:13:13 PM PDT 24
Finished Apr 25 03:13:43 PM PDT 24
Peak memory 352920 kb
Host smart-c23b783b-dfd3-420a-89bb-153976e45616
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498069893 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_acq.498069893
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.1335453251
Short name T386
Test name
Test status
Simulation time 10213389851 ps
CPU time 23.21 seconds
Started Apr 25 03:13:13 PM PDT 24
Finished Apr 25 03:13:38 PM PDT 24
Peak memory 291736 kb
Host smart-f02d9863-3451-44a1-9c9a-d1fc61f63e51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335453251 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.1335453251
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.1452063055
Short name T1022
Test name
Test status
Simulation time 1826156572 ps
CPU time 2.61 seconds
Started Apr 25 03:13:14 PM PDT 24
Finished Apr 25 03:13:18 PM PDT 24
Peak memory 204184 kb
Host smart-37057992-1a9a-4d74-8b19-7d9a753c247f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452063055 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.1452063055
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.782261240
Short name T373
Test name
Test status
Simulation time 4776282198 ps
CPU time 4.28 seconds
Started Apr 25 03:13:12 PM PDT 24
Finished Apr 25 03:13:18 PM PDT 24
Peak memory 204268 kb
Host smart-adb39f71-ec1f-4db8-9b37-18c1fa488e11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782261240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_intr_smoke.782261240
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.4251798411
Short name T409
Test name
Test status
Simulation time 3523666673 ps
CPU time 31.4 seconds
Started Apr 25 03:13:12 PM PDT 24
Finished Apr 25 03:13:44 PM PDT 24
Peak memory 1001764 kb
Host smart-66b05f91-ebac-4e0c-94df-bb2204c569e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251798411 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.4251798411
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.3413783136
Short name T1004
Test name
Test status
Simulation time 2124299980 ps
CPU time 10.9 seconds
Started Apr 25 03:13:05 PM PDT 24
Finished Apr 25 03:13:17 PM PDT 24
Peak memory 204108 kb
Host smart-31fd80f6-830a-4173-97bf-b0d1d96cd236
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413783136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.3413783136
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.3493374982
Short name T737
Test name
Test status
Simulation time 793655731 ps
CPU time 12.81 seconds
Started Apr 25 03:13:14 PM PDT 24
Finished Apr 25 03:13:28 PM PDT 24
Peak memory 212600 kb
Host smart-92faf65e-d075-41c0-bb90-4b266ab22e75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493374982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.3493374982
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.4047073375
Short name T831
Test name
Test status
Simulation time 29751084122 ps
CPU time 22.77 seconds
Started Apr 25 03:13:14 PM PDT 24
Finished Apr 25 03:13:38 PM PDT 24
Peak memory 498116 kb
Host smart-0d33c081-ad24-4999-a5dc-010177bab568
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047073375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.4047073375
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.1605430560
Short name T999
Test name
Test status
Simulation time 10213303873 ps
CPU time 258.11 seconds
Started Apr 25 03:13:13 PM PDT 24
Finished Apr 25 03:17:33 PM PDT 24
Peak memory 1078436 kb
Host smart-9f61c69e-75d4-48a7-abb0-a92f17270275
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605430560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.1605430560
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.2584006615
Short name T311
Test name
Test status
Simulation time 6196607409 ps
CPU time 7.6 seconds
Started Apr 25 03:13:11 PM PDT 24
Finished Apr 25 03:13:20 PM PDT 24
Peak memory 204188 kb
Host smart-ca975147-7429-46b2-ad1f-ec6c7540353f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584006615 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.2584006615
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1800168264
Short name T981
Test name
Test status
Simulation time 15923219 ps
CPU time 0.62 seconds
Started Apr 25 03:13:28 PM PDT 24
Finished Apr 25 03:13:29 PM PDT 24
Peak memory 203852 kb
Host smart-9390ebde-e89a-4d18-bb78-a530ba0f56c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800168264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1800168264
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2220834182
Short name T756
Test name
Test status
Simulation time 183725757 ps
CPU time 1.46 seconds
Started Apr 25 03:13:22 PM PDT 24
Finished Apr 25 03:13:24 PM PDT 24
Peak memory 212528 kb
Host smart-04df88d3-3c0d-4a8b-bc70-852ff86ef062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220834182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2220834182
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.2129157652
Short name T328
Test name
Test status
Simulation time 324375749 ps
CPU time 3.66 seconds
Started Apr 25 03:13:22 PM PDT 24
Finished Apr 25 03:13:27 PM PDT 24
Peak memory 233020 kb
Host smart-1b73beff-ffa4-495e-8247-d3d57cfd19b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129157652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.2129157652
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.173133264
Short name T834
Test name
Test status
Simulation time 1566477033 ps
CPU time 55.36 seconds
Started Apr 25 03:13:29 PM PDT 24
Finished Apr 25 03:14:25 PM PDT 24
Peak memory 589348 kb
Host smart-042d1943-8af1-4021-b1c3-4d4c550658f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173133264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.173133264
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.3002266416
Short name T802
Test name
Test status
Simulation time 4436516030 ps
CPU time 65.33 seconds
Started Apr 25 03:13:24 PM PDT 24
Finished Apr 25 03:14:30 PM PDT 24
Peak memory 695424 kb
Host smart-d370b322-b60e-4db1-bcb3-4a0d03de3850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002266416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.3002266416
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.4111453405
Short name T751
Test name
Test status
Simulation time 254228553 ps
CPU time 0.94 seconds
Started Apr 25 03:13:20 PM PDT 24
Finished Apr 25 03:13:21 PM PDT 24
Peak memory 204200 kb
Host smart-458fe26d-1262-449d-8ab0-db9c897a6354
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111453405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.4111453405
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.2896008465
Short name T509
Test name
Test status
Simulation time 139681016 ps
CPU time 8.1 seconds
Started Apr 25 03:13:21 PM PDT 24
Finished Apr 25 03:13:30 PM PDT 24
Peak memory 228188 kb
Host smart-6fe4eef3-a58a-4f20-a051-24e6dd8db9e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896008465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.2896008465
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.1944763480
Short name T943
Test name
Test status
Simulation time 16667041333 ps
CPU time 331.06 seconds
Started Apr 25 03:13:24 PM PDT 24
Finished Apr 25 03:18:56 PM PDT 24
Peak memory 1240344 kb
Host smart-aa37eb87-78d4-47a4-9af2-76579111c394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944763480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1944763480
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.2974205759
Short name T500
Test name
Test status
Simulation time 562526407 ps
CPU time 7.31 seconds
Started Apr 25 03:13:27 PM PDT 24
Finished Apr 25 03:13:36 PM PDT 24
Peak memory 204156 kb
Host smart-aa8ba21a-c2fe-475e-ab5a-90a76db44afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974205759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.2974205759
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.3996376949
Short name T673
Test name
Test status
Simulation time 1984175884 ps
CPU time 44.59 seconds
Started Apr 25 03:13:26 PM PDT 24
Finished Apr 25 03:14:12 PM PDT 24
Peak memory 291204 kb
Host smart-1e6087f7-08b8-416d-b241-b935effbb9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996376949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.3996376949
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.1482443364
Short name T174
Test name
Test status
Simulation time 93312115 ps
CPU time 0.67 seconds
Started Apr 25 03:13:21 PM PDT 24
Finished Apr 25 03:13:22 PM PDT 24
Peak memory 203840 kb
Host smart-c46f75bd-092d-4319-8052-49bb711bcc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482443364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.1482443364
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.864466218
Short name T865
Test name
Test status
Simulation time 7581614226 ps
CPU time 99.48 seconds
Started Apr 25 03:13:25 PM PDT 24
Finished Apr 25 03:15:05 PM PDT 24
Peak memory 494892 kb
Host smart-214ba73d-383f-4e6f-8d7f-d3874a7f1319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864466218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.864466218
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.825345262
Short name T603
Test name
Test status
Simulation time 7553437330 ps
CPU time 32.22 seconds
Started Apr 25 03:13:13 PM PDT 24
Finished Apr 25 03:13:47 PM PDT 24
Peak memory 326900 kb
Host smart-242d850a-77c7-461e-a1fb-f2989015eca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825345262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.825345262
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.2976692915
Short name T384
Test name
Test status
Simulation time 720187482 ps
CPU time 35.54 seconds
Started Apr 25 03:13:23 PM PDT 24
Finished Apr 25 03:14:00 PM PDT 24
Peak memory 212376 kb
Host smart-b3674f9f-6aeb-4238-bc7f-9134f5666bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976692915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.2976692915
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.1666078104
Short name T1352
Test name
Test status
Simulation time 3023823505 ps
CPU time 3.66 seconds
Started Apr 25 03:13:30 PM PDT 24
Finished Apr 25 03:13:34 PM PDT 24
Peak memory 204200 kb
Host smart-a2f03bcc-a2c7-4390-aa27-323bacbfdbcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666078104 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1666078104
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.3656581575
Short name T655
Test name
Test status
Simulation time 10077017357 ps
CPU time 27.24 seconds
Started Apr 25 03:13:23 PM PDT 24
Finished Apr 25 03:13:51 PM PDT 24
Peak memory 328400 kb
Host smart-308db7eb-5d2a-43c9-87e7-55635491d608
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656581575 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.3656581575
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.784714625
Short name T857
Test name
Test status
Simulation time 10168310719 ps
CPU time 83.01 seconds
Started Apr 25 03:13:21 PM PDT 24
Finished Apr 25 03:14:44 PM PDT 24
Peak memory 524976 kb
Host smart-395cc236-32f3-44da-abf2-74239127d6b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784714625 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_fifo_reset_tx.784714625
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.4032150684
Short name T499
Test name
Test status
Simulation time 1328317056 ps
CPU time 2.15 seconds
Started Apr 25 03:13:29 PM PDT 24
Finished Apr 25 03:13:32 PM PDT 24
Peak memory 204136 kb
Host smart-966e0b38-fa1f-4d38-acd7-971309ef7907
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032150684 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.4032150684
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.2551431785
Short name T268
Test name
Test status
Simulation time 841207867 ps
CPU time 4.64 seconds
Started Apr 25 03:13:21 PM PDT 24
Finished Apr 25 03:13:26 PM PDT 24
Peak memory 216456 kb
Host smart-0fefd93d-7a08-48c0-9e88-d85d59cc0f70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551431785 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.2551431785
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.1313062992
Short name T587
Test name
Test status
Simulation time 18039834940 ps
CPU time 303.24 seconds
Started Apr 25 03:13:21 PM PDT 24
Finished Apr 25 03:18:25 PM PDT 24
Peak memory 3087636 kb
Host smart-65200b96-d756-428e-b1f6-a849ee37a6dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313062992 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.1313062992
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.4049656647
Short name T234
Test name
Test status
Simulation time 1188097601 ps
CPU time 22.95 seconds
Started Apr 25 03:13:25 PM PDT 24
Finished Apr 25 03:13:49 PM PDT 24
Peak memory 204148 kb
Host smart-23ed5937-32d2-40e4-8470-c55f0c6ef509
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049656647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.4049656647
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.512374980
Short name T1167
Test name
Test status
Simulation time 1068366535 ps
CPU time 18.38 seconds
Started Apr 25 03:13:22 PM PDT 24
Finished Apr 25 03:13:41 PM PDT 24
Peak memory 210820 kb
Host smart-d70b91db-c2a6-4309-b697-1f664e57738f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512374980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_rd.512374980
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.1399612648
Short name T1298
Test name
Test status
Simulation time 13573097272 ps
CPU time 28.14 seconds
Started Apr 25 03:13:25 PM PDT 24
Finished Apr 25 03:13:54 PM PDT 24
Peak memory 204216 kb
Host smart-305792d1-ce0e-49f2-86ee-f6ea30665693
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399612648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.1399612648
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.2660322133
Short name T502
Test name
Test status
Simulation time 31491090980 ps
CPU time 3566.64 seconds
Started Apr 25 03:13:20 PM PDT 24
Finished Apr 25 04:12:48 PM PDT 24
Peak memory 7779504 kb
Host smart-185d17f6-cbb6-41cd-a1b4-03e9b2665e37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660322133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.2660322133
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.1152366756
Short name T535
Test name
Test status
Simulation time 5350714976 ps
CPU time 6.63 seconds
Started Apr 25 03:13:20 PM PDT 24
Finished Apr 25 03:13:27 PM PDT 24
Peak memory 212480 kb
Host smart-93fc71e9-8dbb-4548-851e-2f1f54da6241
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152366756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.1152366756
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.400271672
Short name T246
Test name
Test status
Simulation time 18783336 ps
CPU time 0.69 seconds
Started Apr 25 03:06:02 PM PDT 24
Finished Apr 25 03:06:04 PM PDT 24
Peak memory 203920 kb
Host smart-6f6c4422-ca2f-4fc8-993f-5cf8df7e5d2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400271672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.400271672
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.1023026052
Short name T1112
Test name
Test status
Simulation time 208509513 ps
CPU time 1.5 seconds
Started Apr 25 03:05:46 PM PDT 24
Finished Apr 25 03:05:48 PM PDT 24
Peak memory 216408 kb
Host smart-c216d0b9-7998-411c-8638-a7b667c1fe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023026052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.1023026052
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.1409036384
Short name T335
Test name
Test status
Simulation time 287859634 ps
CPU time 5.82 seconds
Started Apr 25 03:05:46 PM PDT 24
Finished Apr 25 03:05:53 PM PDT 24
Peak memory 264744 kb
Host smart-bf8f730f-9390-4697-93d4-d639c4187d15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409036384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.1409036384
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.3470248682
Short name T1314
Test name
Test status
Simulation time 1391277349 ps
CPU time 89.82 seconds
Started Apr 25 03:05:48 PM PDT 24
Finished Apr 25 03:07:19 PM PDT 24
Peak memory 533368 kb
Host smart-a81a95da-5687-4d86-a517-63f731dcb302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470248682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3470248682
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.15408588
Short name T665
Test name
Test status
Simulation time 2062955764 ps
CPU time 156.63 seconds
Started Apr 25 03:05:41 PM PDT 24
Finished Apr 25 03:08:18 PM PDT 24
Peak memory 716944 kb
Host smart-ff77df86-eb5d-47cd-8614-0831eb073503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15408588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.15408588
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.922380965
Short name T475
Test name
Test status
Simulation time 687883559 ps
CPU time 0.93 seconds
Started Apr 25 03:05:42 PM PDT 24
Finished Apr 25 03:05:43 PM PDT 24
Peak memory 204004 kb
Host smart-2d675658-dbb7-4e11-8c54-81a785a878e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922380965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt
.922380965
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.135217325
Short name T1087
Test name
Test status
Simulation time 294853361 ps
CPU time 4.88 seconds
Started Apr 25 03:05:57 PM PDT 24
Finished Apr 25 03:06:03 PM PDT 24
Peak memory 231020 kb
Host smart-97b0e732-24e6-42ce-af26-28f9cbd9eaab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135217325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.135217325
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.1258312438
Short name T1273
Test name
Test status
Simulation time 4319276217 ps
CPU time 334.52 seconds
Started Apr 25 03:05:45 PM PDT 24
Finished Apr 25 03:11:20 PM PDT 24
Peak memory 1257204 kb
Host smart-6b6d199d-404b-43e2-bb19-5beea04ab3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258312438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.1258312438
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.3375046031
Short name T1083
Test name
Test status
Simulation time 1278657928 ps
CPU time 6.46 seconds
Started Apr 25 03:06:02 PM PDT 24
Finished Apr 25 03:06:10 PM PDT 24
Peak memory 204164 kb
Host smart-9a469951-6d8a-49ac-ab11-f897806c4c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375046031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.3375046031
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.756340111
Short name T1323
Test name
Test status
Simulation time 3700802338 ps
CPU time 63.57 seconds
Started Apr 25 03:06:04 PM PDT 24
Finished Apr 25 03:07:09 PM PDT 24
Peak memory 291044 kb
Host smart-4fa6aa99-4ba8-4b71-b025-1aa8d40820ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756340111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.756340111
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.3003164071
Short name T361
Test name
Test status
Simulation time 36318177 ps
CPU time 0.61 seconds
Started Apr 25 03:05:41 PM PDT 24
Finished Apr 25 03:05:43 PM PDT 24
Peak memory 203776 kb
Host smart-e84d0c55-9e1e-4520-86ed-dac2668ebef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003164071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.3003164071
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.2411882797
Short name T1278
Test name
Test status
Simulation time 6746532320 ps
CPU time 198.46 seconds
Started Apr 25 03:05:48 PM PDT 24
Finished Apr 25 03:09:07 PM PDT 24
Peak memory 691368 kb
Host smart-c7a5c29e-72d5-49b8-8aec-3b670c60a0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411882797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.2411882797
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.2484341265
Short name T447
Test name
Test status
Simulation time 1597103875 ps
CPU time 27.11 seconds
Started Apr 25 03:05:41 PM PDT 24
Finished Apr 25 03:06:09 PM PDT 24
Peak memory 414492 kb
Host smart-53c8f617-190a-4503-ab85-248b3131e871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484341265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.2484341265
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.1761999048
Short name T1198
Test name
Test status
Simulation time 9536726033 ps
CPU time 272.73 seconds
Started Apr 25 03:05:49 PM PDT 24
Finished Apr 25 03:10:22 PM PDT 24
Peak memory 1062000 kb
Host smart-713c219f-e1ff-40b7-95ff-000156a13fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761999048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.1761999048
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.2675226182
Short name T787
Test name
Test status
Simulation time 3438392239 ps
CPU time 40.05 seconds
Started Apr 25 03:05:47 PM PDT 24
Finished Apr 25 03:06:27 PM PDT 24
Peak memory 213496 kb
Host smart-c43cd6b4-fa71-44d4-a2b4-1589de63d52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675226182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.2675226182
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.921295335
Short name T113
Test name
Test status
Simulation time 120366955 ps
CPU time 1.1 seconds
Started Apr 25 03:06:02 PM PDT 24
Finished Apr 25 03:06:05 PM PDT 24
Peak memory 222504 kb
Host smart-289dde6d-7ffb-4473-ae74-726a21d188be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921295335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.921295335
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.48257788
Short name T352
Test name
Test status
Simulation time 565426351 ps
CPU time 3.01 seconds
Started Apr 25 03:05:56 PM PDT 24
Finished Apr 25 03:06:00 PM PDT 24
Peak memory 204204 kb
Host smart-6d9e51bd-8140-462e-8003-06fbdfb2b79e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48257788 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_bad_addr.48257788
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.90590060
Short name T1053
Test name
Test status
Simulation time 10838092080 ps
CPU time 3.76 seconds
Started Apr 25 03:05:56 PM PDT 24
Finished Apr 25 03:06:01 PM PDT 24
Peak memory 220392 kb
Host smart-e0e43433-90f6-46f0-9701-5219993ed007
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90590060 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.i2c_target_fifo_reset_acq.90590060
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.3053737160
Short name T855
Test name
Test status
Simulation time 10049048212 ps
CPU time 77.29 seconds
Started Apr 25 03:05:57 PM PDT 24
Finished Apr 25 03:07:15 PM PDT 24
Peak memory 516936 kb
Host smart-7c6bc72b-84c6-4b22-a73f-32e30388d369
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053737160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.3053737160
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.3880773202
Short name T1157
Test name
Test status
Simulation time 374433028 ps
CPU time 2.32 seconds
Started Apr 25 03:05:53 PM PDT 24
Finished Apr 25 03:05:56 PM PDT 24
Peak memory 204192 kb
Host smart-b62f50d1-fbba-4da8-b3f9-bc8d58664519
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880773202 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.3880773202
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.3654878197
Short name T1048
Test name
Test status
Simulation time 12135646576 ps
CPU time 6.99 seconds
Started Apr 25 03:05:55 PM PDT 24
Finished Apr 25 03:06:03 PM PDT 24
Peak memory 204292 kb
Host smart-36deae10-e7fc-4acc-abf2-ac829f664b8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654878197 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.3654878197
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.3159465415
Short name T1301
Test name
Test status
Simulation time 6073472186 ps
CPU time 62.98 seconds
Started Apr 25 03:05:55 PM PDT 24
Finished Apr 25 03:06:59 PM PDT 24
Peak memory 1596196 kb
Host smart-5f6427c8-455f-4811-8f79-ac25472849ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159465415 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.3159465415
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.2841067553
Short name T853
Test name
Test status
Simulation time 810601817 ps
CPU time 12.35 seconds
Started Apr 25 03:05:48 PM PDT 24
Finished Apr 25 03:06:01 PM PDT 24
Peak memory 204160 kb
Host smart-5d871983-226a-457b-a22a-d567d0374c91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841067553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.2841067553
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.3262257758
Short name T321
Test name
Test status
Simulation time 1280055946 ps
CPU time 6.01 seconds
Started Apr 25 03:05:55 PM PDT 24
Finished Apr 25 03:06:02 PM PDT 24
Peak memory 204140 kb
Host smart-7e84ac25-1e45-4fbd-a477-8a99cd25c9c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262257758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.3262257758
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.3378458792
Short name T1077
Test name
Test status
Simulation time 9058368249 ps
CPU time 17.3 seconds
Started Apr 25 03:05:48 PM PDT 24
Finished Apr 25 03:06:06 PM PDT 24
Peak memory 204232 kb
Host smart-41e5057b-a426-4f72-8f2b-827e1e23ab44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378458792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.3378458792
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.2716575361
Short name T1091
Test name
Test status
Simulation time 13697197471 ps
CPU time 658.07 seconds
Started Apr 25 03:05:56 PM PDT 24
Finished Apr 25 03:16:56 PM PDT 24
Peak memory 1870792 kb
Host smart-173baeef-a786-4405-b095-02a83c6845f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716575361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.2716575361
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.2938507017
Short name T14
Test name
Test status
Simulation time 2608993038 ps
CPU time 7.1 seconds
Started Apr 25 03:05:54 PM PDT 24
Finished Apr 25 03:06:01 PM PDT 24
Peak memory 219108 kb
Host smart-397eb230-79f4-4203-9551-53983c7a779d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938507017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.2938507017
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_unexp_stop.3127588702
Short name T1047
Test name
Test status
Simulation time 998736240 ps
CPU time 5.08 seconds
Started Apr 25 03:05:56 PM PDT 24
Finished Apr 25 03:06:02 PM PDT 24
Peak memory 204172 kb
Host smart-b7f6359c-b588-4196-953b-50a158c49502
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127588702 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.i2c_target_unexp_stop.3127588702
Directory /workspace/4.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1747620015
Short name T1117
Test name
Test status
Simulation time 41198092 ps
CPU time 0.61 seconds
Started Apr 25 03:13:39 PM PDT 24
Finished Apr 25 03:13:41 PM PDT 24
Peak memory 203892 kb
Host smart-e4f07567-197c-45d1-9041-168c6f6b2c6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747620015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1747620015
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.22778262
Short name T646
Test name
Test status
Simulation time 163824238 ps
CPU time 1.58 seconds
Started Apr 25 03:13:30 PM PDT 24
Finished Apr 25 03:13:32 PM PDT 24
Peak memory 212468 kb
Host smart-bb2ae1ab-14ab-4258-a352-97b104962211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22778262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.22778262
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.6075091
Short name T660
Test name
Test status
Simulation time 498279859 ps
CPU time 5.23 seconds
Started Apr 25 03:13:28 PM PDT 24
Finished Apr 25 03:13:34 PM PDT 24
Peak memory 246172 kb
Host smart-34cc0090-4ff0-457c-8645-df0f7e2b6bee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6075091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empty.6075091
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.1824934304
Short name T1060
Test name
Test status
Simulation time 5831177370 ps
CPU time 87.76 seconds
Started Apr 25 03:13:27 PM PDT 24
Finished Apr 25 03:14:56 PM PDT 24
Peak memory 522960 kb
Host smart-6de5ea74-71cc-4c41-b2b8-24579f3976e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824934304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.1824934304
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.539033191
Short name T340
Test name
Test status
Simulation time 4932750500 ps
CPU time 44.73 seconds
Started Apr 25 03:13:25 PM PDT 24
Finished Apr 25 03:14:11 PM PDT 24
Peak memory 546732 kb
Host smart-49102787-747b-4841-ac00-33aeb75ffba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539033191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.539033191
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.1674056539
Short name T445
Test name
Test status
Simulation time 126805662 ps
CPU time 0.96 seconds
Started Apr 25 03:13:27 PM PDT 24
Finished Apr 25 03:13:29 PM PDT 24
Peak memory 203960 kb
Host smart-8ce2944f-7681-4f78-bf2d-234917af7cea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674056539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.1674056539
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.2837699549
Short name T872
Test name
Test status
Simulation time 249890095 ps
CPU time 3.51 seconds
Started Apr 25 03:13:27 PM PDT 24
Finished Apr 25 03:13:31 PM PDT 24
Peak memory 204200 kb
Host smart-9ac2e061-8efb-48f7-b2be-d0882049d189
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837699549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.2837699549
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.1374307603
Short name T155
Test name
Test status
Simulation time 5184605636 ps
CPU time 59.48 seconds
Started Apr 25 03:13:28 PM PDT 24
Finished Apr 25 03:14:29 PM PDT 24
Peak memory 826820 kb
Host smart-2e356b6a-0a48-41a2-8898-30f0242084fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374307603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.1374307603
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.718463394
Short name T448
Test name
Test status
Simulation time 814497632 ps
CPU time 5.36 seconds
Started Apr 25 03:13:41 PM PDT 24
Finished Apr 25 03:13:47 PM PDT 24
Peak memory 204072 kb
Host smart-469af98b-ef68-4956-9202-7a935787a1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718463394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.718463394
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.4060555885
Short name T1283
Test name
Test status
Simulation time 3831760271 ps
CPU time 18.31 seconds
Started Apr 25 03:13:39 PM PDT 24
Finished Apr 25 03:13:59 PM PDT 24
Peak memory 281024 kb
Host smart-b0092ac9-46c2-4746-9ebe-946c5331d168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060555885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.4060555885
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.2216455233
Short name T922
Test name
Test status
Simulation time 44010244 ps
CPU time 0.62 seconds
Started Apr 25 03:13:31 PM PDT 24
Finished Apr 25 03:13:32 PM PDT 24
Peak memory 203796 kb
Host smart-6430ccab-dd08-4065-a6ac-97dadd8383a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216455233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.2216455233
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.2971871866
Short name T1208
Test name
Test status
Simulation time 5216912155 ps
CPU time 202.64 seconds
Started Apr 25 03:13:33 PM PDT 24
Finished Apr 25 03:16:56 PM PDT 24
Peak memory 204144 kb
Host smart-6c68ebd9-9a2e-4deb-85d5-d462494c8593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971871866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.2971871866
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.144567345
Short name T472
Test name
Test status
Simulation time 829433737 ps
CPU time 14.88 seconds
Started Apr 25 03:13:28 PM PDT 24
Finished Apr 25 03:13:44 PM PDT 24
Peak memory 313340 kb
Host smart-ebdcc11d-6c67-4759-9411-7a64f05a2860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144567345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.144567345
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.1415219739
Short name T61
Test name
Test status
Simulation time 164052611870 ps
CPU time 900.97 seconds
Started Apr 25 03:13:46 PM PDT 24
Finished Apr 25 03:28:47 PM PDT 24
Peak memory 1572164 kb
Host smart-9676cbd8-c15f-4264-9841-27a8009b5aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415219739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.1415219739
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.3412919137
Short name T934
Test name
Test status
Simulation time 793300743 ps
CPU time 7.48 seconds
Started Apr 25 03:13:27 PM PDT 24
Finished Apr 25 03:13:35 PM PDT 24
Peak memory 220436 kb
Host smart-302c6bb3-5981-48b6-afd6-b10f675281ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412919137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.3412919137
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.421806065
Short name T733
Test name
Test status
Simulation time 13836643978 ps
CPU time 3.55 seconds
Started Apr 25 03:13:37 PM PDT 24
Finished Apr 25 03:13:43 PM PDT 24
Peak memory 212364 kb
Host smart-858e44ce-cfbd-4d9f-9895-af847f8cdc32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421806065 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.421806065
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.951823278
Short name T1033
Test name
Test status
Simulation time 10162447563 ps
CPU time 12.64 seconds
Started Apr 25 03:13:31 PM PDT 24
Finished Apr 25 03:13:45 PM PDT 24
Peak memory 275496 kb
Host smart-3c56f16f-b563-44b2-adb5-ade91fb4a199
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951823278 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_acq.951823278
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.1678737849
Short name T870
Test name
Test status
Simulation time 10124080055 ps
CPU time 72.06 seconds
Started Apr 25 03:13:33 PM PDT 24
Finished Apr 25 03:14:45 PM PDT 24
Peak memory 472500 kb
Host smart-295c0f59-63bb-442a-847a-94a4284483c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678737849 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.1678737849
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.497929555
Short name T732
Test name
Test status
Simulation time 330184922 ps
CPU time 2.18 seconds
Started Apr 25 03:13:32 PM PDT 24
Finished Apr 25 03:13:35 PM PDT 24
Peak memory 204172 kb
Host smart-48112610-c2b0-4f18-899a-be53739987eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497929555 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.i2c_target_hrst.497929555
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.1366483381
Short name T308
Test name
Test status
Simulation time 802203536 ps
CPU time 4.56 seconds
Started Apr 25 03:13:32 PM PDT 24
Finished Apr 25 03:13:37 PM PDT 24
Peak memory 212372 kb
Host smart-ea01582b-2915-4864-abb2-dba11c674070
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366483381 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.1366483381
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.1281347997
Short name T1149
Test name
Test status
Simulation time 10802990623 ps
CPU time 54.79 seconds
Started Apr 25 03:13:32 PM PDT 24
Finished Apr 25 03:14:28 PM PDT 24
Peak memory 1333352 kb
Host smart-e7b0cc2e-c9b7-46b0-8e9a-5a331ad30467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281347997 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.1281347997
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.786623929
Short name T1056
Test name
Test status
Simulation time 7645605519 ps
CPU time 18.75 seconds
Started Apr 25 03:13:28 PM PDT 24
Finished Apr 25 03:13:47 PM PDT 24
Peak memory 204252 kb
Host smart-a0f4cdea-5f41-4cd3-bdea-5b8ae1fe501c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786623929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.786623929
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2553834662
Short name T377
Test name
Test status
Simulation time 4179368847 ps
CPU time 44.93 seconds
Started Apr 25 03:13:33 PM PDT 24
Finished Apr 25 03:14:18 PM PDT 24
Peak memory 204224 kb
Host smart-44333d56-686e-4cb6-8566-bd4939ce7c75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553834662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2553834662
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.316439663
Short name T299
Test name
Test status
Simulation time 69713217972 ps
CPU time 898.5 seconds
Started Apr 25 03:13:37 PM PDT 24
Finished Apr 25 03:28:37 PM PDT 24
Peak memory 6303220 kb
Host smart-e35db25f-dc7c-4300-9748-55e983aea77c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316439663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_wr.316439663
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1318228951
Short name T1018
Test name
Test status
Simulation time 14167686781 ps
CPU time 83.51 seconds
Started Apr 25 03:13:32 PM PDT 24
Finished Apr 25 03:14:56 PM PDT 24
Peak memory 968844 kb
Host smart-c5cf32a3-0927-41b5-a8f3-c72364a2a971
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318228951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1318228951
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.1249742327
Short name T1120
Test name
Test status
Simulation time 1420844225 ps
CPU time 7.9 seconds
Started Apr 25 03:13:32 PM PDT 24
Finished Apr 25 03:13:41 PM PDT 24
Peak memory 220472 kb
Host smart-5f0f8da5-6dbf-4d6e-80d5-569d12d4eb6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249742327 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.1249742327
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.1519451275
Short name T529
Test name
Test status
Simulation time 16387741 ps
CPU time 0.61 seconds
Started Apr 25 03:13:43 PM PDT 24
Finished Apr 25 03:13:45 PM PDT 24
Peak memory 203896 kb
Host smart-cc1aae41-a67f-4e76-b0ef-0b12f21e7521
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519451275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.1519451275
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.224461825
Short name T1159
Test name
Test status
Simulation time 109441924 ps
CPU time 1.24 seconds
Started Apr 25 03:13:44 PM PDT 24
Finished Apr 25 03:13:46 PM PDT 24
Peak memory 212484 kb
Host smart-2861b6e0-76f5-44bb-b426-c52eb948c8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224461825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.224461825
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.2953466016
Short name T969
Test name
Test status
Simulation time 1231554194 ps
CPU time 8.65 seconds
Started Apr 25 03:13:37 PM PDT 24
Finished Apr 25 03:13:48 PM PDT 24
Peak memory 232248 kb
Host smart-24448a87-01c2-4f2f-99cf-1d249c95ab8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953466016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.2953466016
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.2626738612
Short name T1130
Test name
Test status
Simulation time 2292806621 ps
CPU time 33.26 seconds
Started Apr 25 03:13:39 PM PDT 24
Finished Apr 25 03:14:14 PM PDT 24
Peak memory 481184 kb
Host smart-89a397c3-1ccd-4669-a498-6649e6851219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626738612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2626738612
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.3674800253
Short name T372
Test name
Test status
Simulation time 6985530672 ps
CPU time 52.12 seconds
Started Apr 25 03:13:38 PM PDT 24
Finished Apr 25 03:14:32 PM PDT 24
Peak memory 567256 kb
Host smart-68d705db-f6c3-417b-9514-8acfbfa7b5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674800253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.3674800253
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.3608430182
Short name T779
Test name
Test status
Simulation time 469394245 ps
CPU time 0.91 seconds
Started Apr 25 03:13:39 PM PDT 24
Finished Apr 25 03:13:41 PM PDT 24
Peak memory 204012 kb
Host smart-ebf56e49-277d-4e26-82c0-63cb36dd3f1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608430182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.3608430182
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.1631153573
Short name T1082
Test name
Test status
Simulation time 277791470 ps
CPU time 3.31 seconds
Started Apr 25 03:13:41 PM PDT 24
Finished Apr 25 03:13:45 PM PDT 24
Peak memory 204188 kb
Host smart-3cac4f55-ca52-4626-9967-65c663c2f621
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631153573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.1631153573
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.1241190861
Short name T208
Test name
Test status
Simulation time 3638134400 ps
CPU time 283.57 seconds
Started Apr 25 03:13:38 PM PDT 24
Finished Apr 25 03:18:24 PM PDT 24
Peak memory 1109416 kb
Host smart-a1569ef2-bb86-47ee-8d4d-5ef74f8087d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241190861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1241190861
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.1827363027
Short name T825
Test name
Test status
Simulation time 378565843 ps
CPU time 5.08 seconds
Started Apr 25 03:13:43 PM PDT 24
Finished Apr 25 03:13:50 PM PDT 24
Peak memory 204240 kb
Host smart-64e1acbc-dd45-453b-a078-2ca0c28a354f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827363027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.1827363027
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.1916450417
Short name T3
Test name
Test status
Simulation time 14504992862 ps
CPU time 22.98 seconds
Started Apr 25 03:13:44 PM PDT 24
Finished Apr 25 03:14:09 PM PDT 24
Peak memory 301780 kb
Host smart-3ce7f6e2-10f5-4f76-97f9-c4489b364cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916450417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.1916450417
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.2830102396
Short name T867
Test name
Test status
Simulation time 45734148 ps
CPU time 0.64 seconds
Started Apr 25 03:13:39 PM PDT 24
Finished Apr 25 03:13:41 PM PDT 24
Peak memory 203804 kb
Host smart-ebcd103b-c39e-4ab2-9f79-a7380dee3345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830102396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.2830102396
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.2988578046
Short name T177
Test name
Test status
Simulation time 13579499583 ps
CPU time 828.29 seconds
Started Apr 25 03:13:40 PM PDT 24
Finished Apr 25 03:27:30 PM PDT 24
Peak memory 1539188 kb
Host smart-42783272-4304-4462-88f4-f34dc724e5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988578046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.2988578046
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2709531580
Short name T1027
Test name
Test status
Simulation time 1197782278 ps
CPU time 56.85 seconds
Started Apr 25 03:13:38 PM PDT 24
Finished Apr 25 03:14:36 PM PDT 24
Peak memory 335336 kb
Host smart-2646f9b5-3122-4244-be92-b96770f6ba3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709531580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2709531580
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.4272723794
Short name T218
Test name
Test status
Simulation time 27233203834 ps
CPU time 582.14 seconds
Started Apr 25 03:13:45 PM PDT 24
Finished Apr 25 03:23:28 PM PDT 24
Peak memory 1023144 kb
Host smart-c1188193-7ee6-4757-9a49-fc199d47dbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272723794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.4272723794
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.3916464129
Short name T979
Test name
Test status
Simulation time 3318077743 ps
CPU time 18.41 seconds
Started Apr 25 03:13:37 PM PDT 24
Finished Apr 25 03:13:58 PM PDT 24
Peak memory 212436 kb
Host smart-8eac0f60-c172-4697-948a-c03e81e4078a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916464129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3916464129
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.3290477164
Short name T826
Test name
Test status
Simulation time 905322117 ps
CPU time 4.22 seconds
Started Apr 25 03:13:46 PM PDT 24
Finished Apr 25 03:13:51 PM PDT 24
Peak memory 212348 kb
Host smart-de540d55-f440-44b5-9c2e-950e1b9ae36d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290477164 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.3290477164
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.3526021533
Short name T1042
Test name
Test status
Simulation time 10495030841 ps
CPU time 12.82 seconds
Started Apr 25 03:13:45 PM PDT 24
Finished Apr 25 03:13:59 PM PDT 24
Peak memory 267716 kb
Host smart-6debdf7a-425c-4a46-8a4f-906bbac20df3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526021533 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.3526021533
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.2993645959
Short name T1085
Test name
Test status
Simulation time 10181780105 ps
CPU time 13.44 seconds
Started Apr 25 03:13:45 PM PDT 24
Finished Apr 25 03:13:59 PM PDT 24
Peak memory 280964 kb
Host smart-96c0f416-e14e-4166-b0d0-b1101b3e5b28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993645959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.2993645959
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.290625860
Short name T196
Test name
Test status
Simulation time 280651564 ps
CPU time 1.97 seconds
Started Apr 25 03:13:52 PM PDT 24
Finished Apr 25 03:13:54 PM PDT 24
Peak memory 204176 kb
Host smart-921b98f4-95e9-4550-a7dc-a7f580f15be0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290625860 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.i2c_target_hrst.290625860
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.1297460171
Short name T204
Test name
Test status
Simulation time 2151727441 ps
CPU time 5.21 seconds
Started Apr 25 03:13:43 PM PDT 24
Finished Apr 25 03:13:48 PM PDT 24
Peak memory 204712 kb
Host smart-f36ff5b1-7e88-4257-b49a-afae42090f07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297460171 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.1297460171
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.999660969
Short name T1327
Test name
Test status
Simulation time 18857987338 ps
CPU time 274.76 seconds
Started Apr 25 03:13:43 PM PDT 24
Finished Apr 25 03:18:20 PM PDT 24
Peak memory 3063780 kb
Host smart-d382f820-bc19-4ddb-95b3-fcbb47b7e85a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999660969 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.999660969
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.3821976035
Short name T1319
Test name
Test status
Simulation time 3523493724 ps
CPU time 20.94 seconds
Started Apr 25 03:13:44 PM PDT 24
Finished Apr 25 03:14:06 PM PDT 24
Peak memory 204236 kb
Host smart-c3a2daf8-f9a2-4fe9-9ceb-fa3eecf5ff7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821976035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.3821976035
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.3482988684
Short name T1235
Test name
Test status
Simulation time 1648330983 ps
CPU time 67.42 seconds
Started Apr 25 03:13:43 PM PDT 24
Finished Apr 25 03:14:52 PM PDT 24
Peak memory 205856 kb
Host smart-c971fc2e-e01d-44bb-8f89-dd4c57748b6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482988684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.3482988684
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.39751358
Short name T805
Test name
Test status
Simulation time 15795177998 ps
CPU time 14.04 seconds
Started Apr 25 03:13:44 PM PDT 24
Finished Apr 25 03:13:59 PM PDT 24
Peak memory 204196 kb
Host smart-947882be-6c86-480a-86a2-ba7f07733661
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39751358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stress_wr.39751358
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.1177999100
Short name T725
Test name
Test status
Simulation time 40979733088 ps
CPU time 1132.44 seconds
Started Apr 25 03:13:47 PM PDT 24
Finished Apr 25 03:32:40 PM PDT 24
Peak memory 4571992 kb
Host smart-7031232c-0d8c-4409-a693-673daa5b692d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177999100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.1177999100
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.3332161501
Short name T914
Test name
Test status
Simulation time 1097744702 ps
CPU time 5.52 seconds
Started Apr 25 03:13:44 PM PDT 24
Finished Apr 25 03:13:51 PM PDT 24
Peak memory 212440 kb
Host smart-fc8bdf07-78a2-46c6-be16-885cd67967fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332161501 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.3332161501
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.980008719
Short name T1073
Test name
Test status
Simulation time 61800889 ps
CPU time 0.62 seconds
Started Apr 25 03:13:59 PM PDT 24
Finished Apr 25 03:14:01 PM PDT 24
Peak memory 203932 kb
Host smart-a40cb243-72d2-421f-8ab5-4b4b23046543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980008719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.980008719
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.4197618894
Short name T1122
Test name
Test status
Simulation time 125127207 ps
CPU time 1.74 seconds
Started Apr 25 03:13:49 PM PDT 24
Finished Apr 25 03:13:52 PM PDT 24
Peak memory 212412 kb
Host smart-f244a53c-a103-42de-9d19-ab00a1b75352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197618894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.4197618894
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.2100899910
Short name T457
Test name
Test status
Simulation time 2314573726 ps
CPU time 69.33 seconds
Started Apr 25 03:13:50 PM PDT 24
Finished Apr 25 03:15:01 PM PDT 24
Peak memory 732012 kb
Host smart-d97d7429-d50a-4c2e-ae59-5ded49df550e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100899910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.2100899910
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.1362060295
Short name T1272
Test name
Test status
Simulation time 164517575 ps
CPU time 0.89 seconds
Started Apr 25 03:13:50 PM PDT 24
Finished Apr 25 03:13:52 PM PDT 24
Peak memory 203972 kb
Host smart-8452821e-6592-4e73-a7af-38288af127a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362060295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.1362060295
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3216238362
Short name T1064
Test name
Test status
Simulation time 189156704 ps
CPU time 3.7 seconds
Started Apr 25 03:13:51 PM PDT 24
Finished Apr 25 03:13:56 PM PDT 24
Peak memory 204180 kb
Host smart-8a74f568-a84f-4265-ad05-1a7621e3cae1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216238362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.3216238362
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.2075231148
Short name T823
Test name
Test status
Simulation time 14740526595 ps
CPU time 270.92 seconds
Started Apr 25 03:13:44 PM PDT 24
Finished Apr 25 03:18:17 PM PDT 24
Peak memory 1085940 kb
Host smart-90349c69-63dd-4cb0-90e7-159262bbf105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075231148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.2075231148
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.2243998539
Short name T900
Test name
Test status
Simulation time 302320488 ps
CPU time 4.77 seconds
Started Apr 25 03:13:56 PM PDT 24
Finished Apr 25 03:14:02 PM PDT 24
Peak memory 204204 kb
Host smart-961525fe-6ee9-4ea8-a2c0-509ce5a8a6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243998539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.2243998539
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.3270846958
Short name T1315
Test name
Test status
Simulation time 3941581988 ps
CPU time 33.68 seconds
Started Apr 25 03:13:56 PM PDT 24
Finished Apr 25 03:14:32 PM PDT 24
Peak memory 362032 kb
Host smart-65f9f707-46e3-4f69-a8d2-529ef29622df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270846958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.3270846958
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.2653575531
Short name T167
Test name
Test status
Simulation time 34244186 ps
CPU time 0.72 seconds
Started Apr 25 03:13:43 PM PDT 24
Finished Apr 25 03:13:45 PM PDT 24
Peak memory 203868 kb
Host smart-390ce063-f9cb-43e8-8f5a-fbe3452ab2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653575531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2653575531
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.2457521808
Short name T944
Test name
Test status
Simulation time 12525377734 ps
CPU time 78.74 seconds
Started Apr 25 03:13:49 PM PDT 24
Finished Apr 25 03:15:09 PM PDT 24
Peak memory 599732 kb
Host smart-785ec85d-fff8-45d3-9454-74e8d9ba9c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457521808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2457521808
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.4228204164
Short name T348
Test name
Test status
Simulation time 6956264734 ps
CPU time 15.53 seconds
Started Apr 25 03:13:45 PM PDT 24
Finished Apr 25 03:14:01 PM PDT 24
Peak memory 278108 kb
Host smart-af54c51f-e037-45cf-9663-7d90785932ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228204164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.4228204164
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.1970714816
Short name T1066
Test name
Test status
Simulation time 20605077474 ps
CPU time 454.39 seconds
Started Apr 25 03:13:49 PM PDT 24
Finished Apr 25 03:21:25 PM PDT 24
Peak memory 1315124 kb
Host smart-e21f6129-7a8a-48c2-a715-5981ec906350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970714816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.1970714816
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.2965244387
Short name T739
Test name
Test status
Simulation time 932646743 ps
CPU time 20.96 seconds
Started Apr 25 03:13:49 PM PDT 24
Finished Apr 25 03:14:10 PM PDT 24
Peak memory 212364 kb
Host smart-20f1e7bb-3477-4dc6-b123-931318345964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965244387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.2965244387
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.3973750763
Short name T355
Test name
Test status
Simulation time 1133999567 ps
CPU time 5.08 seconds
Started Apr 25 03:13:57 PM PDT 24
Finished Apr 25 03:14:03 PM PDT 24
Peak memory 204264 kb
Host smart-5d3f2c23-370f-4e13-8ab9-7315211169f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973750763 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.3973750763
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.2472665540
Short name T1123
Test name
Test status
Simulation time 10701094971 ps
CPU time 3.16 seconds
Started Apr 25 03:13:57 PM PDT 24
Finished Apr 25 03:14:02 PM PDT 24
Peak memory 206956 kb
Host smart-b7b6a087-ee70-44c6-aca3-45e184e64481
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472665540 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.2472665540
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.3184086070
Short name T593
Test name
Test status
Simulation time 10186943681 ps
CPU time 35.01 seconds
Started Apr 25 03:13:57 PM PDT 24
Finished Apr 25 03:14:34 PM PDT 24
Peak memory 416508 kb
Host smart-4c624dae-3665-4cb3-b23c-7214f0213fab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184086070 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.3184086070
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.3400253087
Short name T389
Test name
Test status
Simulation time 921904133 ps
CPU time 2.72 seconds
Started Apr 25 03:13:57 PM PDT 24
Finished Apr 25 03:14:01 PM PDT 24
Peak memory 204196 kb
Host smart-001a0dc7-7e34-46ee-84be-230955d1e78c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400253087 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.3400253087
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.3298267979
Short name T920
Test name
Test status
Simulation time 4978471951 ps
CPU time 6.67 seconds
Started Apr 25 03:13:48 PM PDT 24
Finished Apr 25 03:13:56 PM PDT 24
Peak memory 220556 kb
Host smart-539bd048-9fec-4c13-ac80-b1848f9e3f43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298267979 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.3298267979
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.1699837433
Short name T403
Test name
Test status
Simulation time 10094491396 ps
CPU time 45.13 seconds
Started Apr 25 03:13:55 PM PDT 24
Finished Apr 25 03:14:41 PM PDT 24
Peak memory 905336 kb
Host smart-311286b5-6fa5-48ab-9766-58352f913853
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699837433 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.1699837433
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.3296659372
Short name T223
Test name
Test status
Simulation time 1353399344 ps
CPU time 22.25 seconds
Started Apr 25 03:13:49 PM PDT 24
Finished Apr 25 03:14:13 PM PDT 24
Peak memory 204188 kb
Host smart-c9d3fff5-c7f5-45d8-b580-c56ee2581ff1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296659372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.3296659372
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.1384791655
Short name T435
Test name
Test status
Simulation time 1576910351 ps
CPU time 11.15 seconds
Started Apr 25 03:13:49 PM PDT 24
Finished Apr 25 03:14:01 PM PDT 24
Peak memory 213080 kb
Host smart-d0e3cad6-07ef-4d3f-831a-6831aea21a42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384791655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.1384791655
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.1218618879
Short name T1062
Test name
Test status
Simulation time 25372302907 ps
CPU time 90.97 seconds
Started Apr 25 03:13:49 PM PDT 24
Finished Apr 25 03:15:21 PM PDT 24
Peak memory 1349052 kb
Host smart-8690a42c-29fc-44f5-a80f-be8bb056589c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218618879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.1218618879
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.3616419693
Short name T486
Test name
Test status
Simulation time 25570958955 ps
CPU time 1525.52 seconds
Started Apr 25 03:13:50 PM PDT 24
Finished Apr 25 03:39:17 PM PDT 24
Peak memory 5003632 kb
Host smart-660ae49b-b805-4ee4-96d1-33c185fbf64f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616419693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.3616419693
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.1681470664
Short name T1139
Test name
Test status
Simulation time 9205203242 ps
CPU time 6.8 seconds
Started Apr 25 03:13:56 PM PDT 24
Finished Apr 25 03:14:04 PM PDT 24
Peak memory 215192 kb
Host smart-d16ee0e7-7c0a-45f1-95fd-09dd9d3e8726
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681470664 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.1681470664
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.487038927
Short name T1028
Test name
Test status
Simulation time 48694501 ps
CPU time 0.62 seconds
Started Apr 25 03:14:09 PM PDT 24
Finished Apr 25 03:14:10 PM PDT 24
Peak memory 203840 kb
Host smart-a989df52-463f-4728-98b0-05a04daa1b58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487038927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.487038927
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.684604938
Short name T1247
Test name
Test status
Simulation time 86885700 ps
CPU time 1.73 seconds
Started Apr 25 03:14:10 PM PDT 24
Finished Apr 25 03:14:12 PM PDT 24
Peak memory 212444 kb
Host smart-0eb8289e-6292-4692-a014-46dac86e8bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684604938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.684604938
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.290412718
Short name T1113
Test name
Test status
Simulation time 481847084 ps
CPU time 12.68 seconds
Started Apr 25 03:13:56 PM PDT 24
Finished Apr 25 03:14:11 PM PDT 24
Peak memory 250756 kb
Host smart-45fbea71-875c-431b-ae95-564ac48ad3c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290412718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empt
y.290412718
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.3853483550
Short name T271
Test name
Test status
Simulation time 5279849965 ps
CPU time 81.47 seconds
Started Apr 25 03:14:03 PM PDT 24
Finished Apr 25 03:15:27 PM PDT 24
Peak memory 504344 kb
Host smart-e8ac940d-f3cd-42a5-ae5b-cdc8e9e2b292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853483550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.3853483550
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.2286762529
Short name T1346
Test name
Test status
Simulation time 1509231676 ps
CPU time 44 seconds
Started Apr 25 03:13:58 PM PDT 24
Finished Apr 25 03:14:44 PM PDT 24
Peak memory 516008 kb
Host smart-59f62703-3d43-4128-ba8f-67cabdef30dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286762529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.2286762529
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.3871919405
Short name T397
Test name
Test status
Simulation time 395863731 ps
CPU time 1.12 seconds
Started Apr 25 03:13:55 PM PDT 24
Finished Apr 25 03:13:57 PM PDT 24
Peak memory 204144 kb
Host smart-8f182b52-0239-4368-9193-ab1dfa767249
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871919405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.3871919405
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.3551213160
Short name T1226
Test name
Test status
Simulation time 162795697 ps
CPU time 4.27 seconds
Started Apr 25 03:13:58 PM PDT 24
Finished Apr 25 03:14:04 PM PDT 24
Peak memory 232956 kb
Host smart-130756a1-95d6-478b-ad5a-926abc0c5be3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551213160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.3551213160
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.925295716
Short name T216
Test name
Test status
Simulation time 42891816147 ps
CPU time 264.73 seconds
Started Apr 25 03:14:16 PM PDT 24
Finished Apr 25 03:18:42 PM PDT 24
Peak memory 1056952 kb
Host smart-9631f63b-4c97-435a-b1e1-63c4df0a79db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925295716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.925295716
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.4007605991
Short name T628
Test name
Test status
Simulation time 789000541 ps
CPU time 10.17 seconds
Started Apr 25 03:14:20 PM PDT 24
Finished Apr 25 03:14:32 PM PDT 24
Peak memory 204164 kb
Host smart-14effd0f-5256-4652-94ef-4f6b522ef6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007605991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.4007605991
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.1298900886
Short name T60
Test name
Test status
Simulation time 1579021443 ps
CPU time 24.16 seconds
Started Apr 25 03:14:15 PM PDT 24
Finished Apr 25 03:14:40 PM PDT 24
Peak memory 317732 kb
Host smart-ebd000d5-225c-4767-bf14-315d2baaef5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298900886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.1298900886
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.3175335658
Short name T1343
Test name
Test status
Simulation time 28582323 ps
CPU time 0.65 seconds
Started Apr 25 03:13:55 PM PDT 24
Finished Apr 25 03:13:57 PM PDT 24
Peak memory 203844 kb
Host smart-c3371ce4-8331-4663-a5db-53a32c16ffce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175335658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.3175335658
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.2628928748
Short name T961
Test name
Test status
Simulation time 49493165397 ps
CPU time 1958.47 seconds
Started Apr 25 03:14:10 PM PDT 24
Finished Apr 25 03:46:50 PM PDT 24
Peak memory 3115548 kb
Host smart-027535c5-d776-46d0-9ecb-0676999c8e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628928748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.2628928748
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.3847750719
Short name T862
Test name
Test status
Simulation time 1398885616 ps
CPU time 61.1 seconds
Started Apr 25 03:13:58 PM PDT 24
Finished Apr 25 03:15:00 PM PDT 24
Peak memory 300168 kb
Host smart-3f5fac1a-c85a-4673-9095-7388941f14df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847750719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.3847750719
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.98157969
Short name T521
Test name
Test status
Simulation time 3058969613 ps
CPU time 9.14 seconds
Started Apr 25 03:14:01 PM PDT 24
Finished Apr 25 03:14:12 PM PDT 24
Peak memory 212432 kb
Host smart-8359cfa8-cc3e-4559-a4ea-05822aee78b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98157969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.98157969
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.2343930096
Short name T1329
Test name
Test status
Simulation time 848748041 ps
CPU time 4.02 seconds
Started Apr 25 03:14:08 PM PDT 24
Finished Apr 25 03:14:13 PM PDT 24
Peak memory 212520 kb
Host smart-d5b62738-a5c7-44dc-ad92-c40ac97918ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343930096 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.2343930096
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.3551765628
Short name T1192
Test name
Test status
Simulation time 10340540789 ps
CPU time 6.32 seconds
Started Apr 25 03:14:01 PM PDT 24
Finished Apr 25 03:14:10 PM PDT 24
Peak memory 221664 kb
Host smart-2abf60ff-06a5-4cff-9fb4-14a5d37d7d31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551765628 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.3551765628
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.525526197
Short name T854
Test name
Test status
Simulation time 10025677390 ps
CPU time 93.14 seconds
Started Apr 25 03:14:03 PM PDT 24
Finished Apr 25 03:15:38 PM PDT 24
Peak memory 608068 kb
Host smart-a9188d0d-eaa7-46c5-8723-f0e1433f5d9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525526197 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_fifo_reset_tx.525526197
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.1251238381
Short name T1281
Test name
Test status
Simulation time 492522986 ps
CPU time 2.19 seconds
Started Apr 25 03:14:10 PM PDT 24
Finished Apr 25 03:14:13 PM PDT 24
Peak memory 204208 kb
Host smart-dee7de6b-cbb8-4c45-a63d-32d92d81299a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251238381 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.1251238381
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3588245312
Short name T818
Test name
Test status
Simulation time 1458123765 ps
CPU time 3.8 seconds
Started Apr 25 03:14:03 PM PDT 24
Finished Apr 25 03:14:09 PM PDT 24
Peak memory 204152 kb
Host smart-d058fc56-e65a-4de7-878f-74ec273bb854
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588245312 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3588245312
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.2172306968
Short name T625
Test name
Test status
Simulation time 5461012643 ps
CPU time 3.69 seconds
Started Apr 25 03:14:03 PM PDT 24
Finished Apr 25 03:14:09 PM PDT 24
Peak memory 204224 kb
Host smart-ed15dadd-2817-4241-8dd7-ee40d0e6745f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172306968 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2172306968
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.2266697941
Short name T581
Test name
Test status
Simulation time 933329927 ps
CPU time 12.23 seconds
Started Apr 25 03:14:10 PM PDT 24
Finished Apr 25 03:14:23 PM PDT 24
Peak memory 204140 kb
Host smart-76fa3483-2eec-4f7c-8821-cb3ba3e1fa7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266697941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.2266697941
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.122338884
Short name T449
Test name
Test status
Simulation time 1236839968 ps
CPU time 51.45 seconds
Started Apr 25 03:14:03 PM PDT 24
Finished Apr 25 03:14:57 PM PDT 24
Peak memory 205580 kb
Host smart-1aab4b0c-aa63-4903-a62d-d1dd9fa1d75b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122338884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_rd.122338884
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.2571293780
Short name T678
Test name
Test status
Simulation time 27601028379 ps
CPU time 54.89 seconds
Started Apr 25 03:14:04 PM PDT 24
Finished Apr 25 03:15:00 PM PDT 24
Peak memory 1017856 kb
Host smart-7b50912b-2871-4938-8fb5-8a59a346ed39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571293780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.2571293780
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.3412919763
Short name T558
Test name
Test status
Simulation time 20029469562 ps
CPU time 1110.43 seconds
Started Apr 25 03:14:03 PM PDT 24
Finished Apr 25 03:32:36 PM PDT 24
Peak memory 2327452 kb
Host smart-cb3da65e-fa0e-4ae4-9441-11acd31712e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412919763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.3412919763
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.1296908576
Short name T996
Test name
Test status
Simulation time 2542170809 ps
CPU time 6.95 seconds
Started Apr 25 03:14:02 PM PDT 24
Finished Apr 25 03:14:11 PM PDT 24
Peak memory 217976 kb
Host smart-72d67938-dda4-4e35-9deb-388497714065
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296908576 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.1296908576
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.1791181808
Short name T1188
Test name
Test status
Simulation time 23089202 ps
CPU time 0.58 seconds
Started Apr 25 03:14:18 PM PDT 24
Finished Apr 25 03:14:19 PM PDT 24
Peak memory 203780 kb
Host smart-95ce029a-76ca-4e79-bc8e-b0cf01d18f24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791181808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.1791181808
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3177041637
Short name T649
Test name
Test status
Simulation time 143405315 ps
CPU time 1.59 seconds
Started Apr 25 03:14:19 PM PDT 24
Finished Apr 25 03:14:22 PM PDT 24
Peak memory 212496 kb
Host smart-5c5d3cb3-32d1-45e8-9cad-417acd04d136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177041637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3177041637
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.663550005
Short name T959
Test name
Test status
Simulation time 1687011461 ps
CPU time 22.32 seconds
Started Apr 25 03:14:12 PM PDT 24
Finished Apr 25 03:14:35 PM PDT 24
Peak memory 296124 kb
Host smart-fc79da35-0b79-497f-b494-ee56e1336a91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663550005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empt
y.663550005
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.3065749335
Short name T1158
Test name
Test status
Simulation time 1481300626 ps
CPU time 98.45 seconds
Started Apr 25 03:14:11 PM PDT 24
Finished Apr 25 03:15:50 PM PDT 24
Peak memory 547004 kb
Host smart-66b58f80-a7f2-4906-9012-8066aed06c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065749335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.3065749335
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.1307612771
Short name T952
Test name
Test status
Simulation time 4407460168 ps
CPU time 62.52 seconds
Started Apr 25 03:14:09 PM PDT 24
Finished Apr 25 03:15:13 PM PDT 24
Peak memory 707644 kb
Host smart-7166f67e-f769-4a3e-88b0-da7784a4d9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307612771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.1307612771
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.2957207293
Short name T302
Test name
Test status
Simulation time 522726578 ps
CPU time 1.11 seconds
Started Apr 25 03:14:10 PM PDT 24
Finished Apr 25 03:14:12 PM PDT 24
Peak memory 204132 kb
Host smart-b744450e-5873-4ccf-9b57-99609e5e57ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957207293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.2957207293
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.1592976259
Short name T561
Test name
Test status
Simulation time 595054371 ps
CPU time 5.09 seconds
Started Apr 25 03:14:09 PM PDT 24
Finished Apr 25 03:14:15 PM PDT 24
Peak memory 241408 kb
Host smart-25d47f60-f480-48e6-a69c-6412247ca33c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592976259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.1592976259
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.1180203099
Short name T213
Test name
Test status
Simulation time 4086491686 ps
CPU time 129.67 seconds
Started Apr 25 03:14:22 PM PDT 24
Finished Apr 25 03:16:33 PM PDT 24
Peak memory 1197068 kb
Host smart-1405d03a-0492-4619-81b5-88c0e6769080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180203099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.1180203099
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.1876951556
Short name T66
Test name
Test status
Simulation time 939410834 ps
CPU time 2.7 seconds
Started Apr 25 03:14:21 PM PDT 24
Finished Apr 25 03:14:25 PM PDT 24
Peak memory 204196 kb
Host smart-cb8a95c0-989d-4eb8-9a9e-0f69413ae595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876951556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.1876951556
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.269047713
Short name T641
Test name
Test status
Simulation time 1195570249 ps
CPU time 21.31 seconds
Started Apr 25 03:14:19 PM PDT 24
Finished Apr 25 03:14:42 PM PDT 24
Peak memory 295872 kb
Host smart-28b11d93-e695-43c5-8356-3ebff22e1de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269047713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.269047713
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.2179121989
Short name T1206
Test name
Test status
Simulation time 157104045 ps
CPU time 0.64 seconds
Started Apr 25 03:14:12 PM PDT 24
Finished Apr 25 03:14:14 PM PDT 24
Peak memory 203832 kb
Host smart-b0219842-2237-4a42-b766-3366add64919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179121989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.2179121989
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.3521121360
Short name T1010
Test name
Test status
Simulation time 249573290 ps
CPU time 3.41 seconds
Started Apr 25 03:14:11 PM PDT 24
Finished Apr 25 03:14:15 PM PDT 24
Peak memory 228580 kb
Host smart-ae0c4774-4bae-4825-83e0-8e928b521366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521121360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.3521121360
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.2047053159
Short name T432
Test name
Test status
Simulation time 984059118 ps
CPU time 20.99 seconds
Started Apr 25 03:14:12 PM PDT 24
Finished Apr 25 03:14:34 PM PDT 24
Peak memory 307848 kb
Host smart-24bf3e90-4682-465c-9368-62446d958a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047053159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.2047053159
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.565400790
Short name T545
Test name
Test status
Simulation time 6624721924 ps
CPU time 204.85 seconds
Started Apr 25 03:14:15 PM PDT 24
Finished Apr 25 03:17:40 PM PDT 24
Peak memory 959060 kb
Host smart-ab8f59c8-b006-48b8-99e1-cfdba2169dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565400790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.565400790
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.4294184194
Short name T300
Test name
Test status
Simulation time 625295806 ps
CPU time 10.24 seconds
Started Apr 25 03:14:13 PM PDT 24
Finished Apr 25 03:14:24 PM PDT 24
Peak memory 220556 kb
Host smart-e30b63ac-deaa-4327-87c4-06f62982b973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294184194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.4294184194
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.1839113460
Short name T850
Test name
Test status
Simulation time 776861691 ps
CPU time 3.87 seconds
Started Apr 25 03:14:15 PM PDT 24
Finished Apr 25 03:14:20 PM PDT 24
Peak memory 204172 kb
Host smart-470d80fd-550d-42c9-bbb9-b78d798a2cbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839113460 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.1839113460
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.4184566366
Short name T563
Test name
Test status
Simulation time 10036631147 ps
CPU time 58.4 seconds
Started Apr 25 03:14:18 PM PDT 24
Finished Apr 25 03:15:17 PM PDT 24
Peak memory 477828 kb
Host smart-1c78a925-a68d-472f-9b2b-3afe265756f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184566366 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.4184566366
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1434641183
Short name T836
Test name
Test status
Simulation time 10095040714 ps
CPU time 65.87 seconds
Started Apr 25 03:14:17 PM PDT 24
Finished Apr 25 03:15:24 PM PDT 24
Peak memory 441976 kb
Host smart-7738bdcf-7730-462c-bc88-79c97924c207
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434641183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1434641183
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.1837323785
Short name T1341
Test name
Test status
Simulation time 348060063 ps
CPU time 2.15 seconds
Started Apr 25 03:14:19 PM PDT 24
Finished Apr 25 03:14:23 PM PDT 24
Peak memory 204168 kb
Host smart-8cc570f3-8d80-4de1-b56d-8d625b83ed40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837323785 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.1837323785
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.217885
Short name T410
Test name
Test status
Simulation time 1099213722 ps
CPU time 5.9 seconds
Started Apr 25 03:14:13 PM PDT 24
Finished Apr 25 03:14:20 PM PDT 24
Peak memory 220492 kb
Host smart-7bc38842-83dc-4731-9068-99cf3b0c3171
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217885 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.i2c_target_intr_smoke.217885
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.810987989
Short name T526
Test name
Test status
Simulation time 12729517278 ps
CPU time 229.79 seconds
Started Apr 25 03:14:15 PM PDT 24
Finished Apr 25 03:18:05 PM PDT 24
Peak memory 3145728 kb
Host smart-754a4231-8087-490e-a293-4fbb05d31485
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810987989 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.810987989
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.3077628510
Short name T951
Test name
Test status
Simulation time 2759206856 ps
CPU time 27.09 seconds
Started Apr 25 03:14:15 PM PDT 24
Finished Apr 25 03:14:43 PM PDT 24
Peak memory 204240 kb
Host smart-34cbe7eb-0d39-4746-98c0-7721db877366
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077628510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.3077628510
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.3992188912
Short name T1099
Test name
Test status
Simulation time 963255470 ps
CPU time 40.83 seconds
Started Apr 25 03:14:14 PM PDT 24
Finished Apr 25 03:14:56 PM PDT 24
Peak memory 204068 kb
Host smart-b7d83ad7-5c9c-40df-bce4-11fe79102ce2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992188912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.3992188912
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.1783526075
Short name T245
Test name
Test status
Simulation time 15573276151 ps
CPU time 32.39 seconds
Started Apr 25 03:14:15 PM PDT 24
Finished Apr 25 03:14:48 PM PDT 24
Peak memory 204088 kb
Host smart-fd5221d2-2501-4f1f-8b28-22e04322994d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783526075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.1783526075
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.2446138949
Short name T1078
Test name
Test status
Simulation time 10781787049 ps
CPU time 128.81 seconds
Started Apr 25 03:14:16 PM PDT 24
Finished Apr 25 03:16:25 PM PDT 24
Peak memory 1256116 kb
Host smart-f2980ba2-944a-4637-b039-b2b105f8ff5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446138949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.2446138949
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.3710420606
Short name T1016
Test name
Test status
Simulation time 1730964275 ps
CPU time 7.86 seconds
Started Apr 25 03:14:15 PM PDT 24
Finished Apr 25 03:14:24 PM PDT 24
Peak memory 217124 kb
Host smart-26dabbc2-5ad6-4fae-904f-4ffb6b4177d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710420606 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.3710420606
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.2691454083
Short name T538
Test name
Test status
Simulation time 16402273 ps
CPU time 0.61 seconds
Started Apr 25 03:14:25 PM PDT 24
Finished Apr 25 03:14:27 PM PDT 24
Peak memory 203752 kb
Host smart-87de3196-1a92-4610-bc6d-6c6a09796277
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691454083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.2691454083
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.1009673581
Short name T844
Test name
Test status
Simulation time 540261586 ps
CPU time 1.25 seconds
Started Apr 25 03:14:20 PM PDT 24
Finished Apr 25 03:14:23 PM PDT 24
Peak memory 212448 kb
Host smart-6a69942b-8663-4a83-b772-db50d2b6607d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009673581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.1009673581
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.1030476240
Short name T1147
Test name
Test status
Simulation time 873595531 ps
CPU time 9.32 seconds
Started Apr 25 03:14:20 PM PDT 24
Finished Apr 25 03:14:31 PM PDT 24
Peak memory 293016 kb
Host smart-384f67d6-b2da-4dce-95ba-73183ff75888
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030476240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.1030476240
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.3206384658
Short name T49
Test name
Test status
Simulation time 9287131970 ps
CPU time 126.92 seconds
Started Apr 25 03:14:19 PM PDT 24
Finished Apr 25 03:16:28 PM PDT 24
Peak memory 422908 kb
Host smart-d02c6c22-a59d-428e-b000-f9b3f3d4f227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206384658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3206384658
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.2576805490
Short name T369
Test name
Test status
Simulation time 21650323148 ps
CPU time 131.72 seconds
Started Apr 25 03:14:20 PM PDT 24
Finished Apr 25 03:16:33 PM PDT 24
Peak memory 637004 kb
Host smart-36b80792-6c26-45cf-9ef7-f1757376cf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576805490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2576805490
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.592376122
Short name T1246
Test name
Test status
Simulation time 126031082 ps
CPU time 1.06 seconds
Started Apr 25 03:14:19 PM PDT 24
Finished Apr 25 03:14:21 PM PDT 24
Peak memory 204168 kb
Host smart-3d461d24-1d8c-43b7-979f-81090830b7ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592376122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fm
t.592376122
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.1017598059
Short name T481
Test name
Test status
Simulation time 1857052884 ps
CPU time 9.58 seconds
Started Apr 25 03:14:22 PM PDT 24
Finished Apr 25 03:14:33 PM PDT 24
Peak memory 204132 kb
Host smart-4c143a1c-bcef-4667-949a-afab84c24141
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017598059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.1017598059
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.1094235745
Short name T992
Test name
Test status
Simulation time 90304163626 ps
CPU time 139.75 seconds
Started Apr 25 03:14:21 PM PDT 24
Finished Apr 25 03:16:42 PM PDT 24
Peak memory 1247412 kb
Host smart-659e64f3-973d-4c2f-bd88-b903e200b94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094235745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1094235745
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.3292434547
Short name T65
Test name
Test status
Simulation time 4400407253 ps
CPU time 3.54 seconds
Started Apr 25 03:14:27 PM PDT 24
Finished Apr 25 03:14:32 PM PDT 24
Peak memory 204272 kb
Host smart-10ecbf0d-6bb5-4e03-88d7-5fbbffec0e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292434547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.3292434547
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.4209129872
Short name T1023
Test name
Test status
Simulation time 6164869932 ps
CPU time 71 seconds
Started Apr 25 03:14:26 PM PDT 24
Finished Apr 25 03:15:39 PM PDT 24
Peak memory 316388 kb
Host smart-3e47ea7c-2d4a-40db-9e1f-85d864310ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209129872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.4209129872
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.1683999185
Short name T170
Test name
Test status
Simulation time 60033186 ps
CPU time 0.66 seconds
Started Apr 25 03:14:21 PM PDT 24
Finished Apr 25 03:14:23 PM PDT 24
Peak memory 203872 kb
Host smart-2b346007-3809-42cf-b0a1-efaed8822d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683999185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.1683999185
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.1828346109
Short name T178
Test name
Test status
Simulation time 7038825053 ps
CPU time 14.37 seconds
Started Apr 25 03:14:18 PM PDT 24
Finished Apr 25 03:14:34 PM PDT 24
Peak memory 351352 kb
Host smart-9dd19e6d-0bec-463f-b0d6-da0bd5975786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828346109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.1828346109
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.404558842
Short name T1326
Test name
Test status
Simulation time 3191467854 ps
CPU time 72.63 seconds
Started Apr 25 03:14:19 PM PDT 24
Finished Apr 25 03:15:34 PM PDT 24
Peak memory 297168 kb
Host smart-94602423-2c2d-4c12-95a4-6ed2abf57300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404558842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.404558842
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.2496545214
Short name T301
Test name
Test status
Simulation time 595503835 ps
CPU time 10.04 seconds
Started Apr 25 03:14:21 PM PDT 24
Finished Apr 25 03:14:32 PM PDT 24
Peak memory 220444 kb
Host smart-89c29aea-ea81-4bf8-9e70-4cc6e0f5862c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496545214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.2496545214
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.3832010311
Short name T1144
Test name
Test status
Simulation time 735438833 ps
CPU time 3.09 seconds
Started Apr 25 03:14:25 PM PDT 24
Finished Apr 25 03:14:30 PM PDT 24
Peak memory 204196 kb
Host smart-69dd9656-9cd2-440e-8a21-496b9d5d4fb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832010311 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.3832010311
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.2729350585
Short name T1239
Test name
Test status
Simulation time 10248949860 ps
CPU time 13.8 seconds
Started Apr 25 03:14:26 PM PDT 24
Finished Apr 25 03:14:42 PM PDT 24
Peak memory 253408 kb
Host smart-aa56a397-c43e-47e5-9235-a9a78e0bd3f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729350585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.2729350585
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.1338749608
Short name T1172
Test name
Test status
Simulation time 10133210512 ps
CPU time 71 seconds
Started Apr 25 03:14:25 PM PDT 24
Finished Apr 25 03:15:38 PM PDT 24
Peak memory 550948 kb
Host smart-d148e3db-f051-4091-8afa-794b1c03d557
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338749608 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.1338749608
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.1798343309
Short name T1204
Test name
Test status
Simulation time 1019422886 ps
CPU time 2.94 seconds
Started Apr 25 03:14:24 PM PDT 24
Finished Apr 25 03:14:29 PM PDT 24
Peak memory 204208 kb
Host smart-cd281c2c-fea1-4bcf-ad91-9e723aaf0ddf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798343309 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.1798343309
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.393714942
Short name T489
Test name
Test status
Simulation time 5746648658 ps
CPU time 5.73 seconds
Started Apr 25 03:14:24 PM PDT 24
Finished Apr 25 03:14:32 PM PDT 24
Peak memory 214432 kb
Host smart-2ad5724f-0d9f-46b9-8677-77de6c48774a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393714942 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_intr_smoke.393714942
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.2465041655
Short name T1260
Test name
Test status
Simulation time 11058591585 ps
CPU time 177.68 seconds
Started Apr 25 03:14:26 PM PDT 24
Finished Apr 25 03:17:25 PM PDT 24
Peak memory 2641044 kb
Host smart-3fd50131-5d26-458a-bc13-fd7cba27c55e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465041655 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.2465041655
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.4282722923
Short name T795
Test name
Test status
Simulation time 1259648207 ps
CPU time 16.12 seconds
Started Apr 25 03:14:17 PM PDT 24
Finished Apr 25 03:14:34 PM PDT 24
Peak memory 204216 kb
Host smart-7966ebda-0bd9-4b30-8402-d1e10dfe6ffd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282722923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.4282722923
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.3665371967
Short name T364
Test name
Test status
Simulation time 1522253681 ps
CPU time 20.61 seconds
Started Apr 25 03:14:19 PM PDT 24
Finished Apr 25 03:14:41 PM PDT 24
Peak memory 228392 kb
Host smart-54512c23-c549-4578-a1e1-fa72495a056c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665371967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.3665371967
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.2798390846
Short name T886
Test name
Test status
Simulation time 11466857824 ps
CPU time 23.19 seconds
Started Apr 25 03:14:18 PM PDT 24
Finished Apr 25 03:14:42 PM PDT 24
Peak memory 204284 kb
Host smart-903261a4-6c57-48b0-a6e5-e322e9336ba0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798390846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.2798390846
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.2327233452
Short name T1176
Test name
Test status
Simulation time 15444869924 ps
CPU time 30.87 seconds
Started Apr 25 03:14:26 PM PDT 24
Finished Apr 25 03:14:58 PM PDT 24
Peak memory 488976 kb
Host smart-f78e3b15-84e8-45cc-ba33-7e817aca4608
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327233452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.2327233452
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.546017044
Short name T490
Test name
Test status
Simulation time 4219616404 ps
CPU time 6.73 seconds
Started Apr 25 03:14:28 PM PDT 24
Finished Apr 25 03:14:36 PM PDT 24
Peak memory 218412 kb
Host smart-1bf9357a-fc50-4408-8b81-feefb9f5ec35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546017044 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_timeout.546017044
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.3022137756
Short name T735
Test name
Test status
Simulation time 80123445 ps
CPU time 0.6 seconds
Started Apr 25 03:14:37 PM PDT 24
Finished Apr 25 03:14:39 PM PDT 24
Peak memory 203888 kb
Host smart-046c3eba-a574-4bca-9579-dddb0571bef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022137756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.3022137756
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.1715442354
Short name T1268
Test name
Test status
Simulation time 164787469 ps
CPU time 1.61 seconds
Started Apr 25 03:14:29 PM PDT 24
Finished Apr 25 03:14:31 PM PDT 24
Peak memory 212468 kb
Host smart-c144a64c-4ac2-41a0-afac-1e952fe3f564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715442354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.1715442354
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.2976438711
Short name T524
Test name
Test status
Simulation time 312590954 ps
CPU time 8.73 seconds
Started Apr 25 03:14:33 PM PDT 24
Finished Apr 25 03:14:43 PM PDT 24
Peak memory 232204 kb
Host smart-c8ec28d3-9c8a-47df-9834-18eb935c3428
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976438711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.2976438711
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.129529690
Short name T1104
Test name
Test status
Simulation time 1687803763 ps
CPU time 46.23 seconds
Started Apr 25 03:14:38 PM PDT 24
Finished Apr 25 03:15:25 PM PDT 24
Peak memory 565084 kb
Host smart-a503f6f6-5ce6-452c-8832-7cf642f3c96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129529690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.129529690
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.184676967
Short name T87
Test name
Test status
Simulation time 6693862805 ps
CPU time 93.23 seconds
Started Apr 25 03:14:28 PM PDT 24
Finished Apr 25 03:16:02 PM PDT 24
Peak memory 495792 kb
Host smart-9810e031-5e6f-486c-acaa-85bb010dbc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184676967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.184676967
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.958938311
Short name T309
Test name
Test status
Simulation time 233982683 ps
CPU time 0.77 seconds
Started Apr 25 03:14:31 PM PDT 24
Finished Apr 25 03:14:32 PM PDT 24
Peak memory 203976 kb
Host smart-95a6c9fe-048c-478f-b261-6548cc95ce89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958938311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fm
t.958938311
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2113615851
Short name T1126
Test name
Test status
Simulation time 117840037 ps
CPU time 3.6 seconds
Started Apr 25 03:14:30 PM PDT 24
Finished Apr 25 03:14:34 PM PDT 24
Peak memory 222744 kb
Host smart-738c7fef-7438-4138-b8c1-35d043d3f9e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113615851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.2113615851
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.4158744632
Short name T633
Test name
Test status
Simulation time 27055286163 ps
CPU time 70.59 seconds
Started Apr 25 03:14:25 PM PDT 24
Finished Apr 25 03:15:38 PM PDT 24
Peak memory 793444 kb
Host smart-7672c5e5-9d65-4172-ac08-3c57d1f20a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158744632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.4158744632
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.3542011401
Short name T607
Test name
Test status
Simulation time 305416647 ps
CPU time 4.25 seconds
Started Apr 25 03:14:38 PM PDT 24
Finished Apr 25 03:14:43 PM PDT 24
Peak memory 204120 kb
Host smart-71192d4c-0e3f-4d34-b72c-2f290779911a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542011401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.3542011401
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.150700972
Short name T638
Test name
Test status
Simulation time 10609851860 ps
CPU time 23 seconds
Started Apr 25 03:14:37 PM PDT 24
Finished Apr 25 03:15:01 PM PDT 24
Peak memory 315992 kb
Host smart-a6eec488-1787-4b0d-affe-6316fb128148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150700972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.150700972
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.3011085129
Short name T39
Test name
Test status
Simulation time 101561777 ps
CPU time 0.65 seconds
Started Apr 25 03:14:24 PM PDT 24
Finished Apr 25 03:14:26 PM PDT 24
Peak memory 203864 kb
Host smart-ccd52dc9-7611-484f-9733-30a6fcb365e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011085129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.3011085129
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.2236918479
Short name T1216
Test name
Test status
Simulation time 6458645959 ps
CPU time 37.61 seconds
Started Apr 25 03:14:48 PM PDT 24
Finished Apr 25 03:15:26 PM PDT 24
Peak memory 213756 kb
Host smart-954b2677-01f9-4375-b6ba-b057254d7fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236918479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.2236918479
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.4015122754
Short name T2
Test name
Test status
Simulation time 4872205967 ps
CPU time 18.24 seconds
Started Apr 25 03:14:25 PM PDT 24
Finished Apr 25 03:14:45 PM PDT 24
Peak memory 285568 kb
Host smart-6a10be22-ee40-4b82-807c-f00b8985bbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015122754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.4015122754
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.2268655858
Short name T162
Test name
Test status
Simulation time 8031281028 ps
CPU time 170.31 seconds
Started Apr 25 03:14:32 PM PDT 24
Finished Apr 25 03:17:23 PM PDT 24
Peak memory 797448 kb
Host smart-b6d8e045-ffb3-4314-9e20-fa699606aa3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268655858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.2268655858
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.2830320482
Short name T734
Test name
Test status
Simulation time 848454035 ps
CPU time 16.19 seconds
Started Apr 25 03:14:30 PM PDT 24
Finished Apr 25 03:14:47 PM PDT 24
Peak memory 220552 kb
Host smart-f2996fe8-fb06-4cc4-a562-247a5a60ef7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830320482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2830320482
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.3895631905
Short name T468
Test name
Test status
Simulation time 1465552871 ps
CPU time 4.2 seconds
Started Apr 25 03:14:38 PM PDT 24
Finished Apr 25 03:14:43 PM PDT 24
Peak memory 204176 kb
Host smart-d103d896-6e20-407c-9112-bebe9399c03f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895631905 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.3895631905
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.2569612742
Short name T1196
Test name
Test status
Simulation time 10185910800 ps
CPU time 29.45 seconds
Started Apr 25 03:14:39 PM PDT 24
Finished Apr 25 03:15:09 PM PDT 24
Peak memory 316904 kb
Host smart-1eef2cd9-f02d-406e-9bf8-3351a5fdc08f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569612742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.2569612742
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.2866934398
Short name T643
Test name
Test status
Simulation time 10188404424 ps
CPU time 20.72 seconds
Started Apr 25 03:14:38 PM PDT 24
Finished Apr 25 03:15:00 PM PDT 24
Peak memory 297896 kb
Host smart-634e6720-1c9a-48e7-abec-997e4e702128
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866934398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.2866934398
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.300978528
Short name T675
Test name
Test status
Simulation time 1727967687 ps
CPU time 2.41 seconds
Started Apr 25 03:14:37 PM PDT 24
Finished Apr 25 03:14:41 PM PDT 24
Peak memory 204244 kb
Host smart-049efd82-1e03-4f5b-a4c9-ce255d9b1bee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300978528 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.i2c_target_hrst.300978528
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.1863298807
Short name T645
Test name
Test status
Simulation time 3798578611 ps
CPU time 5.3 seconds
Started Apr 25 03:14:36 PM PDT 24
Finished Apr 25 03:14:42 PM PDT 24
Peak memory 211244 kb
Host smart-e0eccd03-cab1-4378-af0d-24e1f386ecbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863298807 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.1863298807
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.3550959594
Short name T1116
Test name
Test status
Simulation time 15501823892 ps
CPU time 27.12 seconds
Started Apr 25 03:14:37 PM PDT 24
Finished Apr 25 03:15:05 PM PDT 24
Peak memory 589632 kb
Host smart-d7617bc4-5759-4ee9-898c-521e2c257b27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550959594 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.3550959594
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.1581969764
Short name T1006
Test name
Test status
Simulation time 4032704908 ps
CPU time 37.84 seconds
Started Apr 25 03:14:31 PM PDT 24
Finished Apr 25 03:15:09 PM PDT 24
Peak memory 204240 kb
Host smart-ee68129c-5ea6-4eba-aeb7-b866aa69fb9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581969764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.1581969764
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.2586146403
Short name T370
Test name
Test status
Simulation time 1915798715 ps
CPU time 77.33 seconds
Started Apr 25 03:14:37 PM PDT 24
Finished Apr 25 03:15:56 PM PDT 24
Peak memory 207932 kb
Host smart-a55071da-0a1d-4452-9bd4-df38b0053afc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586146403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.2586146403
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.2173047697
Short name T849
Test name
Test status
Simulation time 27921666708 ps
CPU time 154.04 seconds
Started Apr 25 03:14:32 PM PDT 24
Finished Apr 25 03:17:07 PM PDT 24
Peak memory 2036448 kb
Host smart-41b33a63-ee84-4b77-9161-280f827fd8e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173047697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.2173047697
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.1820173794
Short name T617
Test name
Test status
Simulation time 39688113138 ps
CPU time 3317.22 seconds
Started Apr 25 03:14:39 PM PDT 24
Finished Apr 25 04:09:57 PM PDT 24
Peak memory 4778668 kb
Host smart-7a026f1e-285e-46f4-9b31-e1abb3c4c55c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820173794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.1820173794
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.3518876751
Short name T966
Test name
Test status
Simulation time 6892990146 ps
CPU time 5.94 seconds
Started Apr 25 03:14:37 PM PDT 24
Finished Apr 25 03:14:44 PM PDT 24
Peak memory 212436 kb
Host smart-7caa679f-2722-4bd2-977b-b49b1d565ab5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518876751 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.3518876751
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.2964412831
Short name T429
Test name
Test status
Simulation time 18373208 ps
CPU time 0.65 seconds
Started Apr 25 03:14:50 PM PDT 24
Finished Apr 25 03:14:51 PM PDT 24
Peak memory 203880 kb
Host smart-9a1ca515-5869-46c4-89c4-616e0c9101ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964412831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.2964412831
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.509449186
Short name T238
Test name
Test status
Simulation time 1133375065 ps
CPU time 2.03 seconds
Started Apr 25 03:14:43 PM PDT 24
Finished Apr 25 03:14:46 PM PDT 24
Peak memory 212536 kb
Host smart-8fbef2d5-2fe6-41ad-ac11-ae5ab45790ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509449186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.509449186
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.1644638720
Short name T1059
Test name
Test status
Simulation time 273825382 ps
CPU time 13.9 seconds
Started Apr 25 03:14:43 PM PDT 24
Finished Apr 25 03:14:57 PM PDT 24
Peak memory 258644 kb
Host smart-3306a382-0dbd-43dc-83ce-711fa0f12062
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644638720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.1644638720
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1529291288
Short name T424
Test name
Test status
Simulation time 4546841881 ps
CPU time 61.01 seconds
Started Apr 25 03:14:45 PM PDT 24
Finished Apr 25 03:15:47 PM PDT 24
Peak memory 467224 kb
Host smart-951af65b-9cf7-4376-9024-76de62920237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529291288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1529291288
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.484313618
Short name T621
Test name
Test status
Simulation time 7195539643 ps
CPU time 87.32 seconds
Started Apr 25 03:14:38 PM PDT 24
Finished Apr 25 03:16:06 PM PDT 24
Peak memory 525596 kb
Host smart-37be08b4-0424-4a37-a744-eca5381f8708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484313618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.484313618
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1851522632
Short name T1355
Test name
Test status
Simulation time 113548868 ps
CPU time 1.08 seconds
Started Apr 25 03:14:37 PM PDT 24
Finished Apr 25 03:14:39 PM PDT 24
Peak memory 204188 kb
Host smart-856fe091-e2a4-42b4-aa4e-d81453f46394
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851522632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.1851522632
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.2260578809
Short name T913
Test name
Test status
Simulation time 356993114 ps
CPU time 8.56 seconds
Started Apr 25 03:14:42 PM PDT 24
Finished Apr 25 03:14:51 PM PDT 24
Peak memory 204200 kb
Host smart-93064c14-165d-42b7-b6b2-d2761cb37a4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260578809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.2260578809
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.521603593
Short name T86
Test name
Test status
Simulation time 3178323036 ps
CPU time 71.41 seconds
Started Apr 25 03:14:37 PM PDT 24
Finished Apr 25 03:15:49 PM PDT 24
Peak memory 955580 kb
Host smart-bcf4d0fc-9e4a-45e8-aa4d-4ea1741f7cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521603593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.521603593
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.3027866517
Short name T1351
Test name
Test status
Simulation time 160174256 ps
CPU time 2.23 seconds
Started Apr 25 03:14:49 PM PDT 24
Finished Apr 25 03:14:52 PM PDT 24
Peak memory 204188 kb
Host smart-b4aced9e-4b6a-4c19-b856-e7368c368ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027866517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.3027866517
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.2782693292
Short name T193
Test name
Test status
Simulation time 11860066412 ps
CPU time 46.19 seconds
Started Apr 25 03:14:48 PM PDT 24
Finished Apr 25 03:15:35 PM PDT 24
Peak memory 300732 kb
Host smart-7d23a171-42f7-4458-815c-6893cb675c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782693292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.2782693292
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.3051977410
Short name T501
Test name
Test status
Simulation time 15712983 ps
CPU time 0.64 seconds
Started Apr 25 03:14:37 PM PDT 24
Finished Apr 25 03:14:38 PM PDT 24
Peak memory 203872 kb
Host smart-cf98cb0a-880b-45bf-a5b9-843fa662c21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051977410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.3051977410
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.2345843482
Short name T902
Test name
Test status
Simulation time 30377521441 ps
CPU time 22.52 seconds
Started Apr 25 03:14:41 PM PDT 24
Finished Apr 25 03:15:04 PM PDT 24
Peak memory 245020 kb
Host smart-f5394baf-f004-4a71-88e6-dbfa7bb91300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345843482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2345843482
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.976502356
Short name T229
Test name
Test status
Simulation time 12117828637 ps
CPU time 14.23 seconds
Started Apr 25 03:14:38 PM PDT 24
Finished Apr 25 03:14:54 PM PDT 24
Peak memory 242284 kb
Host smart-115c2ee9-b68f-488f-a6e8-b84e14a932be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976502356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.976502356
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.1291285345
Short name T1350
Test name
Test status
Simulation time 77460445407 ps
CPU time 798.69 seconds
Started Apr 25 03:14:42 PM PDT 24
Finished Apr 25 03:28:02 PM PDT 24
Peak memory 2770600 kb
Host smart-fb7f9453-a4d3-47b7-829d-7b47025be465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291285345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.1291285345
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.3981710026
Short name T337
Test name
Test status
Simulation time 3661799024 ps
CPU time 11.2 seconds
Started Apr 25 03:14:42 PM PDT 24
Finished Apr 25 03:14:54 PM PDT 24
Peak memory 216004 kb
Host smart-d6477bdc-9901-4d29-9ef0-ec29553deec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981710026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.3981710026
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.1716589749
Short name T898
Test name
Test status
Simulation time 1126696448 ps
CPU time 5.63 seconds
Started Apr 25 03:14:49 PM PDT 24
Finished Apr 25 03:14:55 PM PDT 24
Peak memory 212380 kb
Host smart-dd937cf7-9ed4-42e3-bebe-18d682ff68dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716589749 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.1716589749
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.2461537614
Short name T988
Test name
Test status
Simulation time 10385896885 ps
CPU time 2.97 seconds
Started Apr 25 03:14:50 PM PDT 24
Finished Apr 25 03:14:54 PM PDT 24
Peak memory 206460 kb
Host smart-2c897324-d3cb-49a6-a833-1cf03763fac0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461537614 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.2461537614
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.3582099352
Short name T378
Test name
Test status
Simulation time 10130992340 ps
CPU time 13.8 seconds
Started Apr 25 03:14:49 PM PDT 24
Finished Apr 25 03:15:04 PM PDT 24
Peak memory 282208 kb
Host smart-e274c290-4766-41c8-99eb-5514d658da7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582099352 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.3582099352
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.923257823
Short name T985
Test name
Test status
Simulation time 1654685951 ps
CPU time 2.35 seconds
Started Apr 25 03:14:50 PM PDT 24
Finished Apr 25 03:14:53 PM PDT 24
Peak memory 204188 kb
Host smart-12b91b73-45a3-412a-ac9e-05ece229221c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923257823 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.i2c_target_hrst.923257823
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.1367777241
Short name T1190
Test name
Test status
Simulation time 1653674369 ps
CPU time 4.89 seconds
Started Apr 25 03:14:49 PM PDT 24
Finished Apr 25 03:14:54 PM PDT 24
Peak memory 204160 kb
Host smart-fe122126-896a-4768-beef-498e480b3c84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367777241 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.1367777241
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.2494655125
Short name T1071
Test name
Test status
Simulation time 4240374153 ps
CPU time 8.06 seconds
Started Apr 25 03:14:48 PM PDT 24
Finished Apr 25 03:14:57 PM PDT 24
Peak memory 204256 kb
Host smart-acf33e1c-4fb0-4a5c-9cc4-0e7d368a34c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494655125 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.2494655125
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.1963635999
Short name T613
Test name
Test status
Simulation time 4488599642 ps
CPU time 16.95 seconds
Started Apr 25 03:14:43 PM PDT 24
Finished Apr 25 03:15:00 PM PDT 24
Peak memory 204232 kb
Host smart-9289965e-b8b7-4f59-ad13-58e49e3f4feb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963635999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.1963635999
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.4239230970
Short name T923
Test name
Test status
Simulation time 1622627759 ps
CPU time 13.76 seconds
Started Apr 25 03:14:49 PM PDT 24
Finished Apr 25 03:15:03 PM PDT 24
Peak memory 207316 kb
Host smart-3cfa6e3f-67a1-40b3-ab4a-d7bc251f62c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239230970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.4239230970
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.2944914645
Short name T510
Test name
Test status
Simulation time 50054293419 ps
CPU time 961.35 seconds
Started Apr 25 03:14:47 PM PDT 24
Finished Apr 25 03:30:49 PM PDT 24
Peak memory 6600224 kb
Host smart-ccacc942-b72a-4778-9237-b4a947e5a331
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944914645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.2944914645
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.3747373120
Short name T515
Test name
Test status
Simulation time 23243873749 ps
CPU time 179.47 seconds
Started Apr 25 03:14:47 PM PDT 24
Finished Apr 25 03:17:47 PM PDT 24
Peak memory 1363496 kb
Host smart-951f4a8d-4c0f-41fa-b39a-8faa8b2820bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747373120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.3747373120
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.2315923228
Short name T1086
Test name
Test status
Simulation time 6382849779 ps
CPU time 6.8 seconds
Started Apr 25 03:14:46 PM PDT 24
Finished Apr 25 03:14:53 PM PDT 24
Peak memory 212476 kb
Host smart-25784728-355c-40f0-85ce-62795b4956c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315923228 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.2315923228
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.238073350
Short name T375
Test name
Test status
Simulation time 25959774 ps
CPU time 0.62 seconds
Started Apr 25 03:15:03 PM PDT 24
Finished Apr 25 03:15:05 PM PDT 24
Peak memory 203916 kb
Host smart-1c361332-6c92-4b6e-b3d2-254e09de4a69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238073350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.238073350
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.1762631468
Short name T838
Test name
Test status
Simulation time 110662953 ps
CPU time 1.72 seconds
Started Apr 25 03:14:56 PM PDT 24
Finished Apr 25 03:14:59 PM PDT 24
Peak memory 212428 kb
Host smart-d4bf8712-05b5-479c-bd7f-02493b722ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762631468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.1762631468
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.1805866325
Short name T1007
Test name
Test status
Simulation time 639418131 ps
CPU time 7.9 seconds
Started Apr 25 03:14:56 PM PDT 24
Finished Apr 25 03:15:05 PM PDT 24
Peak memory 230680 kb
Host smart-62129290-8c8a-4efa-93bc-a69baa7ffa7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805866325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.1805866325
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.3540006159
Short name T89
Test name
Test status
Simulation time 7141313238 ps
CPU time 55.85 seconds
Started Apr 25 03:14:56 PM PDT 24
Finished Apr 25 03:15:53 PM PDT 24
Peak memory 650844 kb
Host smart-56d11b90-6ed1-4941-84c8-d156a4b591fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540006159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.3540006159
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.3956866037
Short name T331
Test name
Test status
Simulation time 1507842602 ps
CPU time 96.74 seconds
Started Apr 25 03:14:58 PM PDT 24
Finished Apr 25 03:16:35 PM PDT 24
Peak memory 510776 kb
Host smart-4e1080ba-cbb2-4e5a-bfce-8379a340029c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956866037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3956866037
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3473117536
Short name T180
Test name
Test status
Simulation time 257233844 ps
CPU time 3.52 seconds
Started Apr 25 03:14:56 PM PDT 24
Finished Apr 25 03:15:01 PM PDT 24
Peak memory 222460 kb
Host smart-d0dbb1d3-88fd-46fe-b10a-c9e2465d6643
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473117536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3473117536
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.2208966319
Short name T796
Test name
Test status
Simulation time 3213573061 ps
CPU time 221.29 seconds
Started Apr 25 03:14:49 PM PDT 24
Finished Apr 25 03:18:31 PM PDT 24
Peak memory 956392 kb
Host smart-d5da53d7-caab-4429-928a-a541ae9db670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208966319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.2208966319
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.1645230942
Short name T1150
Test name
Test status
Simulation time 282930516 ps
CPU time 4.73 seconds
Started Apr 25 03:15:03 PM PDT 24
Finished Apr 25 03:15:08 PM PDT 24
Peak memory 204200 kb
Host smart-8daca1ef-94e8-450a-baf2-ed41bcac6e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645230942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.1645230942
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.4188671795
Short name T835
Test name
Test status
Simulation time 1528505324 ps
CPU time 27.3 seconds
Started Apr 25 03:15:03 PM PDT 24
Finished Apr 25 03:15:31 PM PDT 24
Peak memory 273748 kb
Host smart-f138107f-a4ba-4468-b7e5-62277dfbb30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188671795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.4188671795
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.2740495328
Short name T312
Test name
Test status
Simulation time 18532120 ps
CPU time 0.67 seconds
Started Apr 25 03:14:50 PM PDT 24
Finished Apr 25 03:14:51 PM PDT 24
Peak memory 203872 kb
Host smart-c16ba365-68ca-4793-8838-580d84a62a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740495328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.2740495328
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.3646719282
Short name T689
Test name
Test status
Simulation time 735864524 ps
CPU time 12.05 seconds
Started Apr 25 03:14:56 PM PDT 24
Finished Apr 25 03:15:09 PM PDT 24
Peak memory 236868 kb
Host smart-407f3f23-e751-4f77-a32f-ad8e4a0a08ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646719282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.3646719282
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2125079668
Short name T1269
Test name
Test status
Simulation time 2825942317 ps
CPU time 70.16 seconds
Started Apr 25 03:14:48 PM PDT 24
Finished Apr 25 03:15:58 PM PDT 24
Peak memory 337372 kb
Host smart-a21290fd-62cc-4575-86dc-0e44e559126d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125079668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2125079668
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.508089004
Short name T47
Test name
Test status
Simulation time 17897067587 ps
CPU time 1003.65 seconds
Started Apr 25 03:14:56 PM PDT 24
Finished Apr 25 03:31:41 PM PDT 24
Peak memory 2217916 kb
Host smart-33bb1339-a4b3-4363-a29c-2b26eb9d5539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508089004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.508089004
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.36270860
Short name T1109
Test name
Test status
Simulation time 2526217068 ps
CPU time 28.8 seconds
Started Apr 25 03:14:56 PM PDT 24
Finished Apr 25 03:15:26 PM PDT 24
Peak memory 212452 kb
Host smart-c4ff2e5b-74c0-42f6-a8be-cfd451da67b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36270860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.36270860
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.1298001064
Short name T991
Test name
Test status
Simulation time 2446182225 ps
CPU time 3.46 seconds
Started Apr 25 03:15:02 PM PDT 24
Finished Apr 25 03:15:06 PM PDT 24
Peak memory 212444 kb
Host smart-f6ee34bb-cbf0-4810-af03-5b9344499338
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298001064 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1298001064
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.760608965
Short name T924
Test name
Test status
Simulation time 10047066419 ps
CPU time 34.49 seconds
Started Apr 25 03:15:05 PM PDT 24
Finished Apr 25 03:15:40 PM PDT 24
Peak memory 314404 kb
Host smart-8deeb0f4-1e28-466a-84d7-dc911198bb0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760608965 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_acq.760608965
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.1231505957
Short name T1063
Test name
Test status
Simulation time 10951433859 ps
CPU time 4.31 seconds
Started Apr 25 03:15:00 PM PDT 24
Finished Apr 25 03:15:05 PM PDT 24
Peak memory 231068 kb
Host smart-dd1b4c7a-f74c-4439-8159-4e70a6d5e8bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231505957 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.1231505957
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.1181092952
Short name T590
Test name
Test status
Simulation time 1247557383 ps
CPU time 2.07 seconds
Started Apr 25 03:15:03 PM PDT 24
Finished Apr 25 03:15:06 PM PDT 24
Peak memory 204180 kb
Host smart-6af64a32-4814-4f9e-8a2f-ce7a12bc1d17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181092952 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.1181092952
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.1309304011
Short name T512
Test name
Test status
Simulation time 3113480971 ps
CPU time 4.07 seconds
Started Apr 25 03:15:02 PM PDT 24
Finished Apr 25 03:15:07 PM PDT 24
Peak memory 207000 kb
Host smart-c8121265-d12f-49dc-93a4-24bf4c1308da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309304011 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.1309304011
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.1974712905
Short name T345
Test name
Test status
Simulation time 7145588528 ps
CPU time 4.88 seconds
Started Apr 25 03:15:02 PM PDT 24
Finished Apr 25 03:15:07 PM PDT 24
Peak memory 204128 kb
Host smart-ee8ae73e-df95-43a2-858e-a479c2f4b1d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974712905 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.1974712905
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.2618071026
Short name T292
Test name
Test status
Simulation time 4045600502 ps
CPU time 12.5 seconds
Started Apr 25 03:14:56 PM PDT 24
Finished Apr 25 03:15:10 PM PDT 24
Peak memory 204236 kb
Host smart-ccf6e0c9-a5eb-484d-8f1f-7103a8a77929
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618071026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.2618071026
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.3559900791
Short name T1009
Test name
Test status
Simulation time 288560704 ps
CPU time 4.29 seconds
Started Apr 25 03:14:55 PM PDT 24
Finished Apr 25 03:15:00 PM PDT 24
Peak memory 204200 kb
Host smart-fc56d8d8-aab4-4c72-a189-062859073b0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559900791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.3559900791
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.2264279063
Short name T709
Test name
Test status
Simulation time 62897485462 ps
CPU time 2301.93 seconds
Started Apr 25 03:14:56 PM PDT 24
Finished Apr 25 03:53:19 PM PDT 24
Peak memory 10483816 kb
Host smart-523d71b5-0622-4582-8e77-041b91705e29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264279063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.2264279063
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.661649219
Short name T1277
Test name
Test status
Simulation time 31549805883 ps
CPU time 193.39 seconds
Started Apr 25 03:14:55 PM PDT 24
Finished Apr 25 03:18:09 PM PDT 24
Peak memory 1822752 kb
Host smart-4e480066-5701-4072-a06f-8dcd546d56f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661649219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_t
arget_stretch.661649219
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.3595082459
Short name T281
Test name
Test status
Simulation time 3064885184 ps
CPU time 7.36 seconds
Started Apr 25 03:15:01 PM PDT 24
Finished Apr 25 03:15:10 PM PDT 24
Peak memory 212480 kb
Host smart-085f9ecb-039f-4f03-9c84-bb8e9fede420
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595082459 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.3595082459
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.3671776806
Short name T1218
Test name
Test status
Simulation time 30987757 ps
CPU time 0.61 seconds
Started Apr 25 03:15:14 PM PDT 24
Finished Apr 25 03:15:15 PM PDT 24
Peak memory 203916 kb
Host smart-5cd78ef2-aaec-426f-9305-d93eb5f6b654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671776806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.3671776806
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.3797545290
Short name T267
Test name
Test status
Simulation time 355658202 ps
CPU time 1.45 seconds
Started Apr 25 03:15:06 PM PDT 24
Finished Apr 25 03:15:08 PM PDT 24
Peak memory 212408 kb
Host smart-f84e226a-92de-459d-aceb-ac8bd9d19df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797545290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.3797545290
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.546687662
Short name T786
Test name
Test status
Simulation time 970247350 ps
CPU time 4.36 seconds
Started Apr 25 03:15:09 PM PDT 24
Finished Apr 25 03:15:14 PM PDT 24
Peak memory 253268 kb
Host smart-d9a9fb63-188f-4517-a3dc-a604f1042741
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546687662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empt
y.546687662
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.3681865223
Short name T1019
Test name
Test status
Simulation time 4803268473 ps
CPU time 164.93 seconds
Started Apr 25 03:15:07 PM PDT 24
Finished Apr 25 03:17:53 PM PDT 24
Peak memory 674900 kb
Host smart-39599c63-f471-4d2e-b6af-3c8a68af1250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681865223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.3681865223
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.2986495
Short name T789
Test name
Test status
Simulation time 7258143867 ps
CPU time 128.17 seconds
Started Apr 25 03:15:00 PM PDT 24
Finished Apr 25 03:17:09 PM PDT 24
Peak memory 617332 kb
Host smart-71c7afe0-6a0b-4ce3-a782-984439e540d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.2986495
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.3801095565
Short name T1101
Test name
Test status
Simulation time 172027465 ps
CPU time 1.19 seconds
Started Apr 25 03:15:07 PM PDT 24
Finished Apr 25 03:15:09 PM PDT 24
Peak memory 204128 kb
Host smart-37169387-19d7-476b-9613-73fa89412847
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801095565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.3801095565
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.3493399770
Short name T332
Test name
Test status
Simulation time 770081067 ps
CPU time 5.04 seconds
Started Apr 25 03:15:06 PM PDT 24
Finished Apr 25 03:15:12 PM PDT 24
Peak memory 204164 kb
Host smart-4b30eed1-c294-47a6-8fd8-5bdee0a6bbfd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493399770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.3493399770
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.2674210402
Short name T1225
Test name
Test status
Simulation time 12131812551 ps
CPU time 79.66 seconds
Started Apr 25 03:15:24 PM PDT 24
Finished Apr 25 03:16:44 PM PDT 24
Peak memory 988308 kb
Host smart-010671e5-96eb-4574-a205-9fcbbc9ae0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674210402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.2674210402
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.1237783825
Short name T394
Test name
Test status
Simulation time 2179692293 ps
CPU time 21.67 seconds
Started Apr 25 03:15:13 PM PDT 24
Finished Apr 25 03:15:36 PM PDT 24
Peak memory 204244 kb
Host smart-57676f95-fa08-4ca2-b3a4-ab8fade1f74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237783825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.1237783825
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.978977006
Short name T1285
Test name
Test status
Simulation time 6857417583 ps
CPU time 28.2 seconds
Started Apr 25 03:15:08 PM PDT 24
Finished Apr 25 03:15:37 PM PDT 24
Peak memory 317944 kb
Host smart-ed4caccc-c09d-4a75-919a-da9ba20004c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978977006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.978977006
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.905087958
Short name T652
Test name
Test status
Simulation time 18829829 ps
CPU time 0.69 seconds
Started Apr 25 03:15:04 PM PDT 24
Finished Apr 25 03:15:05 PM PDT 24
Peak memory 203876 kb
Host smart-5d30aca7-4441-49e7-997d-d83896c50adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905087958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.905087958
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.2065655162
Short name T702
Test name
Test status
Simulation time 2127546750 ps
CPU time 79.61 seconds
Started Apr 25 03:15:05 PM PDT 24
Finished Apr 25 03:16:26 PM PDT 24
Peak memory 305548 kb
Host smart-88de09af-e811-4ee4-afc3-9f6998fa2b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065655162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.2065655162
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.21797234
Short name T221
Test name
Test status
Simulation time 104740582614 ps
CPU time 2279.88 seconds
Started Apr 25 03:15:08 PM PDT 24
Finished Apr 25 03:53:10 PM PDT 24
Peak memory 1510988 kb
Host smart-85ecfcfd-e22e-4e97-a4ec-69a577a2c3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21797234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.21797234
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.3011669
Short name T333
Test name
Test status
Simulation time 648950787 ps
CPU time 12.33 seconds
Started Apr 25 03:15:08 PM PDT 24
Finished Apr 25 03:15:22 PM PDT 24
Peak memory 212428 kb
Host smart-a7184e19-6d00-45cb-b85a-ba746f311c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.3011669
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.3238417778
Short name T1331
Test name
Test status
Simulation time 444500686 ps
CPU time 2.73 seconds
Started Apr 25 03:15:07 PM PDT 24
Finished Apr 25 03:15:11 PM PDT 24
Peak memory 212336 kb
Host smart-a90fe1d8-32c9-40d7-8037-294b99fe0797
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238417778 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.3238417778
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.1926911309
Short name T81
Test name
Test status
Simulation time 10036746218 ps
CPU time 69.72 seconds
Started Apr 25 03:15:07 PM PDT 24
Finished Apr 25 03:16:17 PM PDT 24
Peak memory 434360 kb
Host smart-12ccb675-5ffc-43f9-833b-6dc99d4b99cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926911309 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.1926911309
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.219002131
Short name T879
Test name
Test status
Simulation time 10044840122 ps
CPU time 74.35 seconds
Started Apr 25 03:15:08 PM PDT 24
Finished Apr 25 03:16:23 PM PDT 24
Peak memory 540268 kb
Host smart-e5c60e27-671d-4e28-8e1b-e380373bd826
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219002131 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_fifo_reset_tx.219002131
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.214592892
Short name T347
Test name
Test status
Simulation time 1204284062 ps
CPU time 2.17 seconds
Started Apr 25 03:15:07 PM PDT 24
Finished Apr 25 03:15:10 PM PDT 24
Peak memory 204212 kb
Host smart-8eaa50e0-c5cd-4691-8fea-3a15863719d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214592892 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.i2c_target_hrst.214592892
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1611139979
Short name T1307
Test name
Test status
Simulation time 1709387308 ps
CPU time 4.71 seconds
Started Apr 25 03:15:07 PM PDT 24
Finished Apr 25 03:15:12 PM PDT 24
Peak memory 204420 kb
Host smart-103ea024-341f-43a2-a45f-3322150bfcb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611139979 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1611139979
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.2247259835
Short name T1354
Test name
Test status
Simulation time 19963556148 ps
CPU time 361.96 seconds
Started Apr 25 03:15:08 PM PDT 24
Finished Apr 25 03:21:11 PM PDT 24
Peak memory 4378940 kb
Host smart-375cb9df-9d34-4a91-bf11-74fb89240fe5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247259835 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.2247259835
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.3545739810
Short name T398
Test name
Test status
Simulation time 1215548899 ps
CPU time 43.9 seconds
Started Apr 25 03:15:08 PM PDT 24
Finished Apr 25 03:15:52 PM PDT 24
Peak memory 204200 kb
Host smart-6c087e5e-e03c-49e3-93a9-ee83993f6151
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545739810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.3545739810
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.624728222
Short name T443
Test name
Test status
Simulation time 896813302 ps
CPU time 37.93 seconds
Started Apr 25 03:15:06 PM PDT 24
Finished Apr 25 03:15:44 PM PDT 24
Peak memory 204160 kb
Host smart-3d0b9c2d-8b63-4554-9fd4-e81141cb8dff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624728222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_rd.624728222
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.1997133656
Short name T22
Test name
Test status
Simulation time 35446402128 ps
CPU time 425.57 seconds
Started Apr 25 03:15:07 PM PDT 24
Finished Apr 25 03:22:14 PM PDT 24
Peak memory 4011500 kb
Host smart-57c99311-d625-45a1-b130-1436c41ddf56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997133656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.1997133656
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.3736212623
Short name T596
Test name
Test status
Simulation time 25819391990 ps
CPU time 1715.65 seconds
Started Apr 25 03:15:09 PM PDT 24
Finished Apr 25 03:43:46 PM PDT 24
Peak memory 3077164 kb
Host smart-38493442-6fdc-4aff-8105-609196aab72d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736212623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.3736212623
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.2662204767
Short name T518
Test name
Test status
Simulation time 1328496283 ps
CPU time 6.89 seconds
Started Apr 25 03:15:07 PM PDT 24
Finished Apr 25 03:15:15 PM PDT 24
Peak memory 217384 kb
Host smart-b37f778c-bf87-4d0b-a288-42c45d46fd03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662204767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.2662204767
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.4117822174
Short name T960
Test name
Test status
Simulation time 18489264 ps
CPU time 0.63 seconds
Started Apr 25 03:06:20 PM PDT 24
Finished Apr 25 03:06:22 PM PDT 24
Peak memory 203892 kb
Host smart-71bd7b6e-65fb-4577-ae6e-2cc61afe7aad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117822174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.4117822174
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.456559106
Short name T948
Test name
Test status
Simulation time 249287177 ps
CPU time 1.71 seconds
Started Apr 25 03:06:09 PM PDT 24
Finished Apr 25 03:06:12 PM PDT 24
Peak memory 212492 kb
Host smart-c31333ad-7206-4e47-a743-b5b07d135489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456559106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.456559106
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.1943209064
Short name T574
Test name
Test status
Simulation time 264338879 ps
CPU time 14.3 seconds
Started Apr 25 03:06:05 PM PDT 24
Finished Apr 25 03:06:21 PM PDT 24
Peak memory 257240 kb
Host smart-b6ea07f2-4aae-469b-8f43-619f684171fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943209064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.1943209064
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.1281535145
Short name T1191
Test name
Test status
Simulation time 32437105868 ps
CPU time 88.8 seconds
Started Apr 25 03:06:06 PM PDT 24
Finished Apr 25 03:07:37 PM PDT 24
Peak memory 742696 kb
Host smart-3da6b4dd-fc0f-4d94-8db3-0fdb578c8bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281535145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.1281535145
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.3542767709
Short name T1080
Test name
Test status
Simulation time 11358781645 ps
CPU time 52.46 seconds
Started Apr 25 03:06:06 PM PDT 24
Finished Apr 25 03:07:00 PM PDT 24
Peak memory 577080 kb
Host smart-aedfb9af-0d84-4f68-bdb9-7ec654730a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542767709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.3542767709
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.1367568812
Short name T425
Test name
Test status
Simulation time 637442756 ps
CPU time 1.07 seconds
Started Apr 25 03:06:21 PM PDT 24
Finished Apr 25 03:06:23 PM PDT 24
Peak memory 204144 kb
Host smart-1ddbb9ee-843e-4c6b-b20c-536e9a110c64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367568812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.1367568812
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.1192852538
Short name T1096
Test name
Test status
Simulation time 192883994 ps
CPU time 5.16 seconds
Started Apr 25 03:06:05 PM PDT 24
Finished Apr 25 03:06:12 PM PDT 24
Peak memory 238380 kb
Host smart-5c20dddf-2ffa-4ed1-9b95-d4d5496060d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192852538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
1192852538
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.2325335022
Short name T212
Test name
Test status
Simulation time 18844590639 ps
CPU time 120.86 seconds
Started Apr 25 03:06:00 PM PDT 24
Finished Apr 25 03:08:02 PM PDT 24
Peak memory 1188068 kb
Host smart-acf19679-a9c9-4876-ae71-8158f70753a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325335022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.2325335022
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.1977260058
Short name T188
Test name
Test status
Simulation time 845639794 ps
CPU time 9 seconds
Started Apr 25 03:06:20 PM PDT 24
Finished Apr 25 03:06:30 PM PDT 24
Peak memory 204192 kb
Host smart-f1a7f1f1-cc6f-47a1-bbbe-5f4abb04d8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977260058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.1977260058
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.2116647
Short name T701
Test name
Test status
Simulation time 1848226443 ps
CPU time 16.12 seconds
Started Apr 25 03:06:18 PM PDT 24
Finished Apr 25 03:06:35 PM PDT 24
Peak memory 248132 kb
Host smart-cf7218f7-23c3-4509-9003-f048c9d103fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.2116647
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.2248882883
Short name T1217
Test name
Test status
Simulation time 19090178 ps
CPU time 0.63 seconds
Started Apr 25 03:06:02 PM PDT 24
Finished Apr 25 03:06:04 PM PDT 24
Peak memory 203868 kb
Host smart-463eadf7-a117-4286-a4af-702446a18cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248882883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.2248882883
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.2229899133
Short name T793
Test name
Test status
Simulation time 2950350312 ps
CPU time 190.97 seconds
Started Apr 25 03:06:05 PM PDT 24
Finished Apr 25 03:09:18 PM PDT 24
Peak memory 806100 kb
Host smart-9ac4564d-76cc-464c-a5ea-2b11922cf218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229899133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.2229899133
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.404758681
Short name T717
Test name
Test status
Simulation time 4396264221 ps
CPU time 33.48 seconds
Started Apr 25 03:06:04 PM PDT 24
Finished Apr 25 03:06:39 PM PDT 24
Peak memory 363028 kb
Host smart-e0bf1558-69f7-408e-8499-648e675cbe56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404758681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.404758681
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.43767616
Short name T548
Test name
Test status
Simulation time 1755962167 ps
CPU time 20.92 seconds
Started Apr 25 03:06:05 PM PDT 24
Finished Apr 25 03:06:28 PM PDT 24
Peak memory 212380 kb
Host smart-5eeef840-aa2b-45e7-982e-ce82bad70519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43767616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.43767616
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.2209264985
Short name T541
Test name
Test status
Simulation time 2249567004 ps
CPU time 4.6 seconds
Started Apr 25 03:06:10 PM PDT 24
Finished Apr 25 03:06:15 PM PDT 24
Peak memory 212472 kb
Host smart-1f8ba364-d483-4c1f-9333-d7b159e6410d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209264985 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2209264985
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.3669063388
Short name T1264
Test name
Test status
Simulation time 10095858732 ps
CPU time 73.12 seconds
Started Apr 25 03:06:13 PM PDT 24
Finished Apr 25 03:07:27 PM PDT 24
Peak memory 460340 kb
Host smart-c4861f98-0905-41b8-a2e8-f8a7dd36a387
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669063388 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.3669063388
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.3003277310
Short name T693
Test name
Test status
Simulation time 478198958 ps
CPU time 2.67 seconds
Started Apr 25 03:06:10 PM PDT 24
Finished Apr 25 03:06:14 PM PDT 24
Peak memory 204152 kb
Host smart-936c2775-0d0f-41df-9880-6e747d04f559
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003277310 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.3003277310
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.2673176441
Short name T1171
Test name
Test status
Simulation time 3088703031 ps
CPU time 4.24 seconds
Started Apr 25 03:06:12 PM PDT 24
Finished Apr 25 03:06:17 PM PDT 24
Peak memory 204252 kb
Host smart-3fc018a7-76b3-49a1-bd2f-c2e94404866e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673176441 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.2673176441
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.2030038364
Short name T1294
Test name
Test status
Simulation time 22906831478 ps
CPU time 445.85 seconds
Started Apr 25 03:06:20 PM PDT 24
Finished Apr 25 03:13:47 PM PDT 24
Peak memory 3968552 kb
Host smart-fa042532-d7c3-4291-8005-92c0d51e738a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030038364 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.2030038364
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.2538935195
Short name T536
Test name
Test status
Simulation time 1837881598 ps
CPU time 13.99 seconds
Started Apr 25 03:06:07 PM PDT 24
Finished Apr 25 03:06:23 PM PDT 24
Peak memory 204064 kb
Host smart-ff53e889-53b0-41cd-a4ff-7de1d8173732
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538935195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.2538935195
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.2304576811
Short name T454
Test name
Test status
Simulation time 15117231820 ps
CPU time 59.85 seconds
Started Apr 25 03:06:12 PM PDT 24
Finished Apr 25 03:07:13 PM PDT 24
Peak memory 210308 kb
Host smart-69643690-6635-46c1-bc7e-2c6bac3e1473
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304576811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.2304576811
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.897990550
Short name T415
Test name
Test status
Simulation time 23294396349 ps
CPU time 66.43 seconds
Started Apr 25 03:06:05 PM PDT 24
Finished Apr 25 03:07:13 PM PDT 24
Peak memory 1008716 kb
Host smart-4ffe60fb-9dcd-4389-8ce4-6a32d712b5c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897990550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_wr.897990550
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.1010503230
Short name T416
Test name
Test status
Simulation time 11159898095 ps
CPU time 367.59 seconds
Started Apr 25 03:06:12 PM PDT 24
Finished Apr 25 03:12:21 PM PDT 24
Peak memory 2800496 kb
Host smart-249d0b63-d4a7-4625-9d77-16773f9f1429
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010503230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.1010503230
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.226591777
Short name T503
Test name
Test status
Simulation time 2446107787 ps
CPU time 6.25 seconds
Started Apr 25 03:06:11 PM PDT 24
Finished Apr 25 03:06:18 PM PDT 24
Peak memory 211924 kb
Host smart-87ef9a7c-ccc2-4d86-b996-236339afd16e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226591777 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_timeout.226591777
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.1936803674
Short name T261
Test name
Test status
Simulation time 18731651 ps
CPU time 0.64 seconds
Started Apr 25 03:06:39 PM PDT 24
Finished Apr 25 03:06:40 PM PDT 24
Peak memory 203888 kb
Host smart-4aa216ee-776c-425f-a891-527ce48a41fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936803674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.1936803674
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.3876159208
Short name T754
Test name
Test status
Simulation time 133313249 ps
CPU time 1.59 seconds
Started Apr 25 03:06:26 PM PDT 24
Finished Apr 25 03:06:29 PM PDT 24
Peak memory 212440 kb
Host smart-9669ba9a-beeb-4297-8aff-3b819772937a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876159208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.3876159208
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.3583851625
Short name T1200
Test name
Test status
Simulation time 474245953 ps
CPU time 12.26 seconds
Started Apr 25 03:06:20 PM PDT 24
Finished Apr 25 03:06:33 PM PDT 24
Peak memory 250716 kb
Host smart-68627d28-9437-4023-8020-b82c31d707d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583851625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.3583851625
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.4173502556
Short name T497
Test name
Test status
Simulation time 2238819923 ps
CPU time 61.03 seconds
Started Apr 25 03:06:26 PM PDT 24
Finished Apr 25 03:07:28 PM PDT 24
Peak memory 317656 kb
Host smart-1edf9a1a-c410-439c-ac6a-e5138b8cfae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173502556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.4173502556
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.1266609514
Short name T975
Test name
Test status
Simulation time 1375294571 ps
CPU time 47.36 seconds
Started Apr 25 03:06:17 PM PDT 24
Finished Apr 25 03:07:05 PM PDT 24
Peak memory 536028 kb
Host smart-e5ad9220-3c66-4783-aac3-88b4ec036432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266609514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1266609514
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.80057023
Short name T69
Test name
Test status
Simulation time 1173357353 ps
CPU time 1.15 seconds
Started Apr 25 03:06:17 PM PDT 24
Finished Apr 25 03:06:19 PM PDT 24
Peak memory 204152 kb
Host smart-3eee9882-5b93-4588-8c01-93f82b45731a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80057023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt.80057023
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.524397895
Short name T1248
Test name
Test status
Simulation time 2280505656 ps
CPU time 3.07 seconds
Started Apr 25 03:06:25 PM PDT 24
Finished Apr 25 03:06:28 PM PDT 24
Peak memory 204248 kb
Host smart-af0be2ba-d2d8-47cc-98e5-a6b4c0650df2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524397895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.524397895
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.167337051
Short name T989
Test name
Test status
Simulation time 4488242894 ps
CPU time 49.39 seconds
Started Apr 25 03:06:20 PM PDT 24
Finished Apr 25 03:07:10 PM PDT 24
Peak memory 760336 kb
Host smart-ec81952e-2a36-4c74-bd6c-7a88a8c6f776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167337051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.167337051
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.1117681801
Short name T1114
Test name
Test status
Simulation time 1866084587 ps
CPU time 20.02 seconds
Started Apr 25 03:06:35 PM PDT 24
Finished Apr 25 03:06:56 PM PDT 24
Peak memory 204084 kb
Host smart-87d4f840-0556-4f75-b110-7a4fa4c83704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117681801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.1117681801
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.1142212960
Short name T40
Test name
Test status
Simulation time 6388821642 ps
CPU time 30.4 seconds
Started Apr 25 03:06:35 PM PDT 24
Finished Apr 25 03:07:06 PM PDT 24
Peak memory 343064 kb
Host smart-1e35d708-ca22-4f63-a597-e9fa20da31da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142212960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.1142212960
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.1541062160
Short name T799
Test name
Test status
Simulation time 27389077 ps
CPU time 0.67 seconds
Started Apr 25 03:06:16 PM PDT 24
Finished Apr 25 03:06:17 PM PDT 24
Peak memory 203868 kb
Host smart-3665f1fc-ca7f-4187-9824-6c3cbf93c971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541062160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.1541062160
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.3637620923
Short name T1084
Test name
Test status
Simulation time 27638198430 ps
CPU time 1046.91 seconds
Started Apr 25 03:06:23 PM PDT 24
Finished Apr 25 03:23:51 PM PDT 24
Peak memory 1746132 kb
Host smart-b7266ace-3690-4400-8b2b-d787f5b6a4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637620923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.3637620923
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.4185301688
Short name T1170
Test name
Test status
Simulation time 2502073345 ps
CPU time 65.25 seconds
Started Apr 25 03:06:17 PM PDT 24
Finished Apr 25 03:07:23 PM PDT 24
Peak memory 310256 kb
Host smart-fcaed211-01af-4798-a44c-b23317efc9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185301688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.4185301688
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.2875622962
Short name T743
Test name
Test status
Simulation time 20903672242 ps
CPU time 397.07 seconds
Started Apr 25 03:06:24 PM PDT 24
Finished Apr 25 03:13:02 PM PDT 24
Peak memory 924324 kb
Host smart-27d44e07-cb28-4a35-a9b2-6abcd6b82eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875622962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.2875622962
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.3651031457
Short name T890
Test name
Test status
Simulation time 2708314839 ps
CPU time 31.97 seconds
Started Apr 25 03:06:29 PM PDT 24
Finished Apr 25 03:07:02 PM PDT 24
Peak memory 212360 kb
Host smart-d64338ff-862d-495b-9700-9cd71d0fd5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651031457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.3651031457
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.4234076807
Short name T1040
Test name
Test status
Simulation time 1307160189 ps
CPU time 2.88 seconds
Started Apr 25 03:07:04 PM PDT 24
Finished Apr 25 03:07:08 PM PDT 24
Peak memory 204136 kb
Host smart-c1b4e3fd-a87e-48d8-8b91-40b6c598ccb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234076807 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.4234076807
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.4162221126
Short name T428
Test name
Test status
Simulation time 10077620655 ps
CPU time 78.16 seconds
Started Apr 25 03:06:37 PM PDT 24
Finished Apr 25 03:07:55 PM PDT 24
Peak memory 449164 kb
Host smart-67497c9c-31e1-4be8-a3e9-856b10fa3fdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162221126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.4162221126
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.632093745
Short name T101
Test name
Test status
Simulation time 10160589788 ps
CPU time 28.03 seconds
Started Apr 25 03:07:02 PM PDT 24
Finished Apr 25 03:07:30 PM PDT 24
Peak memory 378144 kb
Host smart-27c2bd24-b5b1-410d-864f-0a6391c80462
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632093745 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.632093745
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.2267706760
Short name T1070
Test name
Test status
Simulation time 1318078538 ps
CPU time 2.15 seconds
Started Apr 25 03:06:36 PM PDT 24
Finished Apr 25 03:06:38 PM PDT 24
Peak memory 204180 kb
Host smart-eaeb285e-6f1b-4b2c-bd9d-7b4d8950f99b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267706760 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.2267706760
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.942954460
Short name T318
Test name
Test status
Simulation time 1609431447 ps
CPU time 4.19 seconds
Started Apr 25 03:06:32 PM PDT 24
Finished Apr 25 03:06:37 PM PDT 24
Peak memory 205952 kb
Host smart-4152468e-fbf3-4c31-b8f3-0863887657d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942954460 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_intr_smoke.942954460
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.4007716131
Short name T576
Test name
Test status
Simulation time 6200729454 ps
CPU time 3.65 seconds
Started Apr 25 03:06:30 PM PDT 24
Finished Apr 25 03:06:34 PM PDT 24
Peak memory 204144 kb
Host smart-cf554496-cd03-43f7-892a-b34c441180af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007716131 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.4007716131
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.65009715
Short name T685
Test name
Test status
Simulation time 5135967044 ps
CPU time 18.26 seconds
Started Apr 25 03:06:32 PM PDT 24
Finished Apr 25 03:06:50 PM PDT 24
Peak memory 204244 kb
Host smart-a0478da2-756b-42e9-a044-d890bdb63071
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65009715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_targe
t_smoke.65009715
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_all.247641905
Short name T452
Test name
Test status
Simulation time 54469127569 ps
CPU time 1530.83 seconds
Started Apr 25 03:06:36 PM PDT 24
Finished Apr 25 03:32:08 PM PDT 24
Peak memory 9195648 kb
Host smart-a5ebc452-c5e0-4aa1-8054-d43c2c587a81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247641905 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.i2c_target_stress_all.247641905
Directory /workspace/6.i2c_target_stress_all/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.1436217348
Short name T694
Test name
Test status
Simulation time 5003872434 ps
CPU time 22.06 seconds
Started Apr 25 03:06:30 PM PDT 24
Finished Apr 25 03:06:53 PM PDT 24
Peak memory 220440 kb
Host smart-3472bba4-764c-4e35-a35c-855bac36b573
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436217348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.1436217348
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.2242413077
Short name T1143
Test name
Test status
Simulation time 39184022209 ps
CPU time 46.52 seconds
Started Apr 25 03:06:30 PM PDT 24
Finished Apr 25 03:07:17 PM PDT 24
Peak memory 863904 kb
Host smart-3cc46032-0ed1-4992-b648-f5dfcf605cef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242413077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.2242413077
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.475866641
Short name T243
Test name
Test status
Simulation time 1877220090 ps
CPU time 6.68 seconds
Started Apr 25 03:06:30 PM PDT 24
Finished Apr 25 03:06:38 PM PDT 24
Peak memory 212336 kb
Host smart-c74730f7-4e88-47c9-9eb9-fa5eff2db898
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475866641 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_timeout.475866641
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.2211149934
Short name T59
Test name
Test status
Simulation time 19174853 ps
CPU time 0.6 seconds
Started Apr 25 03:06:51 PM PDT 24
Finished Apr 25 03:06:53 PM PDT 24
Peak memory 203916 kb
Host smart-bf910442-a98b-4738-b963-d59a286abb08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211149934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2211149934
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.2776810105
Short name T904
Test name
Test status
Simulation time 563888030 ps
CPU time 2.06 seconds
Started Apr 25 03:06:42 PM PDT 24
Finished Apr 25 03:06:44 PM PDT 24
Peak memory 212460 kb
Host smart-bd7c38a9-c83b-4d7f-b29e-7bed04d9427e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776810105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.2776810105
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.4029896401
Short name T363
Test name
Test status
Simulation time 901836201 ps
CPU time 11.53 seconds
Started Apr 25 03:06:42 PM PDT 24
Finished Apr 25 03:06:55 PM PDT 24
Peak memory 232684 kb
Host smart-9d71dcfd-777c-426c-bd8c-9813ed9e8f31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029896401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.4029896401
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.689207576
Short name T1121
Test name
Test status
Simulation time 7015644619 ps
CPU time 123.14 seconds
Started Apr 25 03:06:45 PM PDT 24
Finished Apr 25 03:08:48 PM PDT 24
Peak memory 622116 kb
Host smart-aff065cb-8887-4526-8413-46d115e032ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689207576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.689207576
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.331368711
Short name T888
Test name
Test status
Simulation time 7640866043 ps
CPU time 68.65 seconds
Started Apr 25 03:06:44 PM PDT 24
Finished Apr 25 03:07:53 PM PDT 24
Peak memory 377844 kb
Host smart-bdbe1e42-ff8a-4e3f-8170-c22da32b89f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331368711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.331368711
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.2479226606
Short name T68
Test name
Test status
Simulation time 295199817 ps
CPU time 1.08 seconds
Started Apr 25 03:06:45 PM PDT 24
Finished Apr 25 03:06:48 PM PDT 24
Peak memory 204176 kb
Host smart-07738cd7-752b-40c0-bb26-f79107d14b34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479226606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.2479226606
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.2767363724
Short name T579
Test name
Test status
Simulation time 499705821 ps
CPU time 3.69 seconds
Started Apr 25 03:06:46 PM PDT 24
Finished Apr 25 03:06:50 PM PDT 24
Peak memory 223708 kb
Host smart-9a82e5a8-b50f-466a-a522-9f130fa19a8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767363724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
2767363724
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.256977415
Short name T618
Test name
Test status
Simulation time 3397566320 ps
CPU time 99.78 seconds
Started Apr 25 03:06:41 PM PDT 24
Finished Apr 25 03:08:22 PM PDT 24
Peak memory 1015700 kb
Host smart-b35f606d-dac8-42e6-940b-96ce13fa7363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256977415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.256977415
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.3635973965
Short name T1021
Test name
Test status
Simulation time 644117628 ps
CPU time 2.45 seconds
Started Apr 25 03:06:53 PM PDT 24
Finished Apr 25 03:06:57 PM PDT 24
Peak memory 204108 kb
Host smart-7627b419-465f-43de-957b-bcddd01c8731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635973965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3635973965
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.3149445376
Short name T492
Test name
Test status
Simulation time 2604331818 ps
CPU time 23.14 seconds
Started Apr 25 03:06:46 PM PDT 24
Finished Apr 25 03:07:10 PM PDT 24
Peak memory 348896 kb
Host smart-5606d83a-9ef8-49d9-904e-e5fd83bfbe04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149445376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.3149445376
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.3923318670
Short name T565
Test name
Test status
Simulation time 42158210 ps
CPU time 0.65 seconds
Started Apr 25 03:06:38 PM PDT 24
Finished Apr 25 03:06:40 PM PDT 24
Peak memory 203868 kb
Host smart-557a5d3e-899e-4e70-a476-1b286b039bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923318670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.3923318670
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.1887570604
Short name T1
Test name
Test status
Simulation time 514674463 ps
CPU time 4.06 seconds
Started Apr 25 03:06:41 PM PDT 24
Finished Apr 25 03:06:46 PM PDT 24
Peak memory 220576 kb
Host smart-80124325-e03f-4517-b88a-e9ecff7c2c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887570604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.1887570604
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.3428631461
Short name T569
Test name
Test status
Simulation time 4281038143 ps
CPU time 19.8 seconds
Started Apr 25 03:06:36 PM PDT 24
Finished Apr 25 03:06:57 PM PDT 24
Peak memory 283868 kb
Host smart-29dfe006-9724-4df2-acd2-628db90d2cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428631461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.3428631461
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.3301128945
Short name T785
Test name
Test status
Simulation time 605129661 ps
CPU time 24.22 seconds
Started Apr 25 03:06:43 PM PDT 24
Finished Apr 25 03:07:08 PM PDT 24
Peak memory 212340 kb
Host smart-8b30d243-180f-44d8-bb25-1e29c250729b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301128945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.3301128945
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.724081970
Short name T636
Test name
Test status
Simulation time 5584638900 ps
CPU time 3.87 seconds
Started Apr 25 03:06:48 PM PDT 24
Finished Apr 25 03:06:53 PM PDT 24
Peak memory 212388 kb
Host smart-e2826b69-0e18-4245-993c-3baeff570b7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724081970 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.724081970
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.1192774337
Short name T661
Test name
Test status
Simulation time 10091096982 ps
CPU time 71.06 seconds
Started Apr 25 03:06:48 PM PDT 24
Finished Apr 25 03:08:01 PM PDT 24
Peak memory 418912 kb
Host smart-29fbb5f5-0452-475f-aa37-186758e61409
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192774337 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.1192774337
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.3002254883
Short name T560
Test name
Test status
Simulation time 10044154929 ps
CPU time 75.85 seconds
Started Apr 25 03:06:49 PM PDT 24
Finished Apr 25 03:08:07 PM PDT 24
Peak memory 431408 kb
Host smart-ce9b3576-0cb2-4477-bb52-f8f76c2c6af1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002254883 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.3002254883
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.1293193145
Short name T889
Test name
Test status
Simulation time 478349024 ps
CPU time 2.96 seconds
Started Apr 25 03:06:48 PM PDT 24
Finished Apr 25 03:06:52 PM PDT 24
Peak memory 204144 kb
Host smart-a24fa4a2-d734-49aa-951e-930d230ecf5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293193145 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.1293193145
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.2041618318
Short name T677
Test name
Test status
Simulation time 3576811642 ps
CPU time 5.73 seconds
Started Apr 25 03:06:49 PM PDT 24
Finished Apr 25 03:06:56 PM PDT 24
Peak memory 213508 kb
Host smart-70a1a9dd-bc03-486e-be4d-edaece17f90e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041618318 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.2041618318
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.505987537
Short name T316
Test name
Test status
Simulation time 5985500517 ps
CPU time 4.29 seconds
Started Apr 25 03:06:48 PM PDT 24
Finished Apr 25 03:06:54 PM PDT 24
Peak memory 204248 kb
Host smart-c6b831e0-97ea-4253-bb56-5cb56d578a68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505987537 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.505987537
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.1164518706
Short name T251
Test name
Test status
Simulation time 2944954653 ps
CPU time 29.98 seconds
Started Apr 25 03:06:43 PM PDT 24
Finished Apr 25 03:07:14 PM PDT 24
Peak memory 204228 kb
Host smart-f9898234-f2b3-4dc8-924e-64f1b4d53f4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164518706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.1164518706
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.2425863770
Short name T1051
Test name
Test status
Simulation time 328640007 ps
CPU time 14.1 seconds
Started Apr 25 03:06:43 PM PDT 24
Finished Apr 25 03:06:58 PM PDT 24
Peak memory 204112 kb
Host smart-c1a8481e-1267-4aba-a964-8b93aed62070
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425863770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.2425863770
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.73056649
Short name T1313
Test name
Test status
Simulation time 55522796245 ps
CPU time 194.44 seconds
Started Apr 25 03:06:45 PM PDT 24
Finished Apr 25 03:10:01 PM PDT 24
Peak memory 2303856 kb
Host smart-7321c313-ee64-4a76-9da4-5668730e063c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73056649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stress_wr.73056649
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.4075293976
Short name T1093
Test name
Test status
Simulation time 16246108379 ps
CPU time 772.6 seconds
Started Apr 25 03:06:42 PM PDT 24
Finished Apr 25 03:19:35 PM PDT 24
Peak memory 3986348 kb
Host smart-99f37121-d030-45d5-aa4a-63f583047ba7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075293976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.4075293976
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.3697747017
Short name T722
Test name
Test status
Simulation time 5581386758 ps
CPU time 8.06 seconds
Started Apr 25 03:06:49 PM PDT 24
Finished Apr 25 03:06:59 PM PDT 24
Peak memory 220500 kb
Host smart-f22a2962-e54d-4491-9f89-298d88d3fd03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697747017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.3697747017
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.218500178
Short name T1164
Test name
Test status
Simulation time 20517259 ps
CPU time 0.61 seconds
Started Apr 25 03:07:09 PM PDT 24
Finished Apr 25 03:07:10 PM PDT 24
Peak memory 203840 kb
Host smart-6b4b32f8-bad8-49dc-b4c7-4cc17bb48cd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218500178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.218500178
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.3257807448
Short name T1097
Test name
Test status
Simulation time 66799451 ps
CPU time 1.42 seconds
Started Apr 25 03:06:58 PM PDT 24
Finished Apr 25 03:07:01 PM PDT 24
Peak memory 212424 kb
Host smart-c1eaaf41-f1cc-432c-9760-d1427d22859a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257807448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.3257807448
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.1254438003
Short name T1174
Test name
Test status
Simulation time 221903169 ps
CPU time 12.26 seconds
Started Apr 25 03:06:52 PM PDT 24
Finished Apr 25 03:07:06 PM PDT 24
Peak memory 248632 kb
Host smart-5f79356d-f64e-468f-b185-646bc24463c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254438003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.1254438003
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.1947066143
Short name T747
Test name
Test status
Simulation time 3817192994 ps
CPU time 56.79 seconds
Started Apr 25 03:07:02 PM PDT 24
Finished Apr 25 03:07:59 PM PDT 24
Peak memory 642984 kb
Host smart-c1ccd9d6-a32e-451e-bf01-eecd18ad7428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947066143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.1947066143
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.882714782
Short name T1254
Test name
Test status
Simulation time 5191623778 ps
CPU time 38.43 seconds
Started Apr 25 03:06:52 PM PDT 24
Finished Apr 25 03:07:31 PM PDT 24
Peak memory 528588 kb
Host smart-2fe76042-2b72-45d0-9521-3fa4207b31a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882714782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.882714782
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3551730387
Short name T1356
Test name
Test status
Simulation time 341822100 ps
CPU time 0.97 seconds
Started Apr 25 03:06:52 PM PDT 24
Finished Apr 25 03:06:55 PM PDT 24
Peak memory 203992 kb
Host smart-36949b43-76ea-457e-b173-d89dc9d39c6d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551730387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3551730387
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.141076326
Short name T315
Test name
Test status
Simulation time 1027231585 ps
CPU time 10.85 seconds
Started Apr 25 03:06:54 PM PDT 24
Finished Apr 25 03:07:06 PM PDT 24
Peak memory 239508 kb
Host smart-32e8f51b-0b81-41cd-9cc5-c3b9b3c99438
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141076326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.141076326
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.2683822756
Short name T1274
Test name
Test status
Simulation time 5828245090 ps
CPU time 184.43 seconds
Started Apr 25 03:06:51 PM PDT 24
Finished Apr 25 03:09:56 PM PDT 24
Peak memory 819836 kb
Host smart-b156f9a8-8c88-4f98-b08a-37b4e9af4806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683822756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.2683822756
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.1868631687
Short name T1288
Test name
Test status
Simulation time 134795369 ps
CPU time 5.14 seconds
Started Apr 25 03:07:13 PM PDT 24
Finished Apr 25 03:07:19 PM PDT 24
Peak memory 204180 kb
Host smart-342e9ab8-ac99-49c3-a454-915d63fdde18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868631687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.1868631687
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.2869969215
Short name T1075
Test name
Test status
Simulation time 1613561569 ps
CPU time 32.73 seconds
Started Apr 25 03:07:10 PM PDT 24
Finished Apr 25 03:07:44 PM PDT 24
Peak memory 415500 kb
Host smart-62aaee39-e49f-4489-9a7b-a5b1d2277627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869969215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.2869969215
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.2280233999
Short name T172
Test name
Test status
Simulation time 18292864 ps
CPU time 0.66 seconds
Started Apr 25 03:06:52 PM PDT 24
Finished Apr 25 03:06:54 PM PDT 24
Peak memory 203844 kb
Host smart-bb27eb9d-7102-4e73-bbbc-7401a7232662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280233999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.2280233999
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.949075854
Short name T791
Test name
Test status
Simulation time 18653339690 ps
CPU time 1136.57 seconds
Started Apr 25 03:07:00 PM PDT 24
Finished Apr 25 03:25:58 PM PDT 24
Peak memory 2119572 kb
Host smart-c1824dd6-c168-4030-a482-e96a2b68102d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949075854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.949075854
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.313841831
Short name T696
Test name
Test status
Simulation time 674632314 ps
CPU time 12.61 seconds
Started Apr 25 03:06:54 PM PDT 24
Finished Apr 25 03:07:07 PM PDT 24
Peak memory 245960 kb
Host smart-6da6bbcc-c521-4f76-b174-774849b01b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313841831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.313841831
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.2592069301
Short name T211
Test name
Test status
Simulation time 23644506178 ps
CPU time 139.07 seconds
Started Apr 25 03:07:06 PM PDT 24
Finished Apr 25 03:09:25 PM PDT 24
Peak memory 1021020 kb
Host smart-5d06c758-4c84-4f17-a039-c16a88c25781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592069301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.2592069301
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.776275081
Short name T439
Test name
Test status
Simulation time 579656954 ps
CPU time 24.69 seconds
Started Apr 25 03:06:58 PM PDT 24
Finished Apr 25 03:07:24 PM PDT 24
Peak memory 212336 kb
Host smart-c58d91b2-c40d-456a-ab6b-9c8044892373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776275081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.776275081
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.288862425
Short name T322
Test name
Test status
Simulation time 927189338 ps
CPU time 4.53 seconds
Started Apr 25 03:07:11 PM PDT 24
Finished Apr 25 03:07:16 PM PDT 24
Peak memory 212372 kb
Host smart-9d800828-4853-4937-b16a-361685eb154c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288862425 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.288862425
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.1680147370
Short name T50
Test name
Test status
Simulation time 10070750549 ps
CPU time 71.15 seconds
Started Apr 25 03:07:06 PM PDT 24
Finished Apr 25 03:08:18 PM PDT 24
Peak memory 485360 kb
Host smart-ebf19e49-e1be-4620-8f9d-fe0f3fa1a1a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680147370 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.1680147370
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.3145545859
Short name T620
Test name
Test status
Simulation time 10036235949 ps
CPU time 74.36 seconds
Started Apr 25 03:07:05 PM PDT 24
Finished Apr 25 03:08:20 PM PDT 24
Peak memory 558684 kb
Host smart-cb81f3b0-c3b3-42c5-b7dc-9ee3c48722d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145545859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.3145545859
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.2859579672
Short name T278
Test name
Test status
Simulation time 1054248034 ps
CPU time 2.42 seconds
Started Apr 25 03:07:10 PM PDT 24
Finished Apr 25 03:07:14 PM PDT 24
Peak memory 204204 kb
Host smart-0856e3bb-b734-44ab-b26e-4640838c4ffd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859579672 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.2859579672
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.2246188755
Short name T313
Test name
Test status
Simulation time 1054191433 ps
CPU time 5.17 seconds
Started Apr 25 03:07:03 PM PDT 24
Finished Apr 25 03:07:09 PM PDT 24
Peak memory 204176 kb
Host smart-4c6757ee-efc0-4cda-8dfd-08d943e1d96e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246188755 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.2246188755
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.4177495548
Short name T1186
Test name
Test status
Simulation time 47198675274 ps
CPU time 20.92 seconds
Started Apr 25 03:07:02 PM PDT 24
Finished Apr 25 03:07:24 PM PDT 24
Peak memory 537852 kb
Host smart-edaa61a2-1102-4335-b720-0a6ee9ac6ad2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177495548 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.4177495548
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.2005073031
Short name T341
Test name
Test status
Simulation time 1413207654 ps
CPU time 51.54 seconds
Started Apr 25 03:07:02 PM PDT 24
Finished Apr 25 03:07:55 PM PDT 24
Peak memory 204260 kb
Host smart-b913ac11-e519-42bd-badf-4343c48d5e08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005073031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.2005073031
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.2073771590
Short name T648
Test name
Test status
Simulation time 1304383059 ps
CPU time 7.2 seconds
Started Apr 25 03:07:05 PM PDT 24
Finished Apr 25 03:07:13 PM PDT 24
Peak memory 204032 kb
Host smart-a884ba39-f94b-4306-a6fe-73cb275d9988
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073771590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.2073771590
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.2147257724
Short name T1106
Test name
Test status
Simulation time 56217739054 ps
CPU time 198.81 seconds
Started Apr 25 03:07:02 PM PDT 24
Finished Apr 25 03:10:22 PM PDT 24
Peak memory 2250860 kb
Host smart-468d3f85-4247-4d98-adfe-e5d433bea409
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147257724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.2147257724
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.3022168207
Short name T241
Test name
Test status
Simulation time 16153496101 ps
CPU time 932.46 seconds
Started Apr 25 03:07:27 PM PDT 24
Finished Apr 25 03:23:01 PM PDT 24
Peak memory 3861300 kb
Host smart-f67d89f6-228f-4282-b240-67278ee73b15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022168207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.3022168207
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.3571759622
Short name T374
Test name
Test status
Simulation time 1416182650 ps
CPU time 6.42 seconds
Started Apr 25 03:07:05 PM PDT 24
Finished Apr 25 03:07:12 PM PDT 24
Peak memory 204136 kb
Host smart-e9f87044-3da2-46d1-a5c2-b2fff7bcb24f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571759622 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.3571759622
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.216403266
Short name T380
Test name
Test status
Simulation time 45814886 ps
CPU time 0.61 seconds
Started Apr 25 03:07:32 PM PDT 24
Finished Apr 25 03:07:34 PM PDT 24
Peak memory 203896 kb
Host smart-7044fa30-7764-4652-8060-0b3a733f444a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216403266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.216403266
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1431620596
Short name T778
Test name
Test status
Simulation time 420378818 ps
CPU time 1.42 seconds
Started Apr 25 03:07:15 PM PDT 24
Finished Apr 25 03:07:17 PM PDT 24
Peak memory 212444 kb
Host smart-47fa0117-4523-4552-9dfa-9542c2fe97de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431620596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1431620596
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.1830002067
Short name T460
Test name
Test status
Simulation time 359159753 ps
CPU time 8.15 seconds
Started Apr 25 03:07:15 PM PDT 24
Finished Apr 25 03:07:24 PM PDT 24
Peak memory 278764 kb
Host smart-6f565fe1-3abb-4902-8fd2-7b32a5acb0a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830002067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.1830002067
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.291145731
Short name T376
Test name
Test status
Simulation time 8257811681 ps
CPU time 61.74 seconds
Started Apr 25 03:07:18 PM PDT 24
Finished Apr 25 03:08:20 PM PDT 24
Peak memory 614080 kb
Host smart-7c2f66f8-f8a1-4426-9c13-5a7fd3b263c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291145731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.291145731
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.1977258531
Short name T1234
Test name
Test status
Simulation time 4443655276 ps
CPU time 72.7 seconds
Started Apr 25 03:07:15 PM PDT 24
Finished Apr 25 03:08:29 PM PDT 24
Peak memory 468748 kb
Host smart-28a5c5c0-bb2c-43fb-b85c-75ce8dc76174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977258531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1977258531
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.1908616265
Short name T1348
Test name
Test status
Simulation time 431885995 ps
CPU time 0.93 seconds
Started Apr 25 03:07:13 PM PDT 24
Finished Apr 25 03:07:15 PM PDT 24
Peak memory 204016 kb
Host smart-b2a58913-eeca-4de9-8999-23b49dd20eb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908616265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.1908616265
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.4072338363
Short name T1229
Test name
Test status
Simulation time 1573503003 ps
CPU time 3.97 seconds
Started Apr 25 03:07:15 PM PDT 24
Finished Apr 25 03:07:20 PM PDT 24
Peak memory 204072 kb
Host smart-9c420daa-f068-42b8-bfb4-394250f83144
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072338363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
4072338363
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.2003174956
Short name T842
Test name
Test status
Simulation time 4645922491 ps
CPU time 161.98 seconds
Started Apr 25 03:07:14 PM PDT 24
Finished Apr 25 03:09:57 PM PDT 24
Peak memory 1346272 kb
Host smart-d06e2f6e-ba51-4351-98ae-0749fb721d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003174956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.2003174956
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.3819864102
Short name T64
Test name
Test status
Simulation time 410600014 ps
CPU time 16.01 seconds
Started Apr 25 03:07:32 PM PDT 24
Finished Apr 25 03:07:49 PM PDT 24
Peak memory 204116 kb
Host smart-e8732c6e-cb1b-43db-9807-26b90be0d3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819864102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.3819864102
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.2371538320
Short name T1026
Test name
Test status
Simulation time 1353675683 ps
CPU time 63.6 seconds
Started Apr 25 03:07:34 PM PDT 24
Finished Apr 25 03:08:38 PM PDT 24
Peak memory 341852 kb
Host smart-5f06bee7-a1e4-4c51-9719-5da2398d5b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371538320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.2371538320
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.4076386611
Short name T897
Test name
Test status
Simulation time 26790161 ps
CPU time 0.63 seconds
Started Apr 25 03:07:13 PM PDT 24
Finished Apr 25 03:07:15 PM PDT 24
Peak memory 203836 kb
Host smart-0a032d91-263f-442d-8e7b-51a083bc79dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076386611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.4076386611
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.1181798677
Short name T967
Test name
Test status
Simulation time 7409939321 ps
CPU time 151.15 seconds
Started Apr 25 03:07:17 PM PDT 24
Finished Apr 25 03:09:49 PM PDT 24
Peak memory 212524 kb
Host smart-5e5b8869-9374-4607-9a44-a99318e0ca30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181798677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.1181798677
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.2950223876
Short name T710
Test name
Test status
Simulation time 935829225 ps
CPU time 45.98 seconds
Started Apr 25 03:07:18 PM PDT 24
Finished Apr 25 03:08:04 PM PDT 24
Peak memory 285524 kb
Host smart-386955bd-c2ab-488e-b1a6-32b69243fbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950223876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2950223876
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.1698388955
Short name T158
Test name
Test status
Simulation time 24840314702 ps
CPU time 594.06 seconds
Started Apr 25 03:07:13 PM PDT 24
Finished Apr 25 03:17:08 PM PDT 24
Peak memory 2090528 kb
Host smart-5dd05ecf-6608-4f7d-9a1d-ab14180d1d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698388955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.1698388955
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.1428824407
Short name T1074
Test name
Test status
Simulation time 2370085707 ps
CPU time 15.44 seconds
Started Apr 25 03:07:16 PM PDT 24
Finished Apr 25 03:07:33 PM PDT 24
Peak memory 212376 kb
Host smart-5433399f-5773-469c-b8e8-9121eafaf973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428824407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.1428824407
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.1528353436
Short name T244
Test name
Test status
Simulation time 3569822210 ps
CPU time 4.51 seconds
Started Apr 25 03:07:28 PM PDT 24
Finished Apr 25 03:07:33 PM PDT 24
Peak memory 205772 kb
Host smart-47b68ca3-d84f-45b2-9a2c-53f5c90dd20d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528353436 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.1528353436
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.3502679414
Short name T1058
Test name
Test status
Simulation time 10876842997 ps
CPU time 4.6 seconds
Started Apr 25 03:07:27 PM PDT 24
Finished Apr 25 03:07:33 PM PDT 24
Peak memory 218620 kb
Host smart-903c67fe-f9d0-48cc-962a-1fcab81db63c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502679414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.3502679414
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.1715760302
Short name T100
Test name
Test status
Simulation time 10073989939 ps
CPU time 33.63 seconds
Started Apr 25 03:07:27 PM PDT 24
Finished Apr 25 03:08:02 PM PDT 24
Peak memory 336264 kb
Host smart-747a1f8c-0839-4a06-8a36-620d1e9fb6f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715760302 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.1715760302
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.2740957033
Short name T25
Test name
Test status
Simulation time 3018865389 ps
CPU time 3 seconds
Started Apr 25 03:07:36 PM PDT 24
Finished Apr 25 03:07:40 PM PDT 24
Peak memory 204276 kb
Host smart-44a9df54-e682-4ac0-b321-1771afea06c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740957033 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.2740957033
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.3501029133
Short name T580
Test name
Test status
Simulation time 3351308153 ps
CPU time 4.23 seconds
Started Apr 25 03:07:37 PM PDT 24
Finished Apr 25 03:07:42 PM PDT 24
Peak memory 204520 kb
Host smart-8324194b-f5af-4da7-8022-ac008c6789ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501029133 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.3501029133
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.2200253626
Short name T614
Test name
Test status
Simulation time 10833221720 ps
CPU time 25.52 seconds
Started Apr 25 03:07:19 PM PDT 24
Finished Apr 25 03:07:45 PM PDT 24
Peak memory 584976 kb
Host smart-f2201628-ac52-480f-98ce-10e6ce0728c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200253626 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.2200253626
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.2576251022
Short name T269
Test name
Test status
Simulation time 2010271761 ps
CPU time 6.6 seconds
Started Apr 25 03:07:22 PM PDT 24
Finished Apr 25 03:07:30 PM PDT 24
Peak memory 204124 kb
Host smart-423ef7d2-ff5b-4b7a-8f6b-6ed240e22a30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576251022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.2576251022
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.1867723600
Short name T707
Test name
Test status
Simulation time 1176126520 ps
CPU time 53.16 seconds
Started Apr 25 03:07:22 PM PDT 24
Finished Apr 25 03:08:16 PM PDT 24
Peak memory 204680 kb
Host smart-43daf08a-230b-4f44-bfa5-31a34fd0ec43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867723600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.1867723600
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.274619776
Short name T1187
Test name
Test status
Simulation time 46542351971 ps
CPU time 286.53 seconds
Started Apr 25 03:07:20 PM PDT 24
Finished Apr 25 03:12:08 PM PDT 24
Peak memory 3338208 kb
Host smart-72200e74-7081-4b49-a59a-b9cf1b646451
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274619776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_wr.274619776
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.4037701561
Short name T506
Test name
Test status
Simulation time 15358820207 ps
CPU time 20.95 seconds
Started Apr 25 03:07:22 PM PDT 24
Finished Apr 25 03:07:43 PM PDT 24
Peak memory 438572 kb
Host smart-3fe74758-8d80-4171-a5a1-a699aa3e6bd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037701561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.4037701561
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.2591867445
Short name T883
Test name
Test status
Simulation time 1492901942 ps
CPU time 7.19 seconds
Started Apr 25 03:07:22 PM PDT 24
Finished Apr 25 03:07:30 PM PDT 24
Peak memory 212416 kb
Host smart-17d768ee-ec51-4a6d-b147-d38f91548233
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591867445 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.2591867445
Directory /workspace/9.i2c_target_timeout/latest
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