Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	728343	1			T1	3		T2	3		T3	2
all_values[1]	728343	1			T1	3		T2	3		T3	2
all_values[2]	728343	1			T1	3		T2	3		T3	2
all_values[3]	728343	1			T1	3		T2	3		T3	2
all_values[4]	728343	1			T1	3		T2	3		T3	2
all_values[5]	728343	1			T1	3		T2	3		T3	2
all_values[6]	728343	1			T1	3		T2	3		T3	2
all_values[7]	728343	1			T1	3		T2	3		T3	2
all_values[8]	728343	1			T1	3		T2	3		T3	2
all_values[9]	728343	1			T1	3		T2	3		T3	2
all_values[10]	728343	1			T1	3		T2	3		T3	2
all_values[11]	728343	1			T1	3		T2	3		T3	2
all_values[12]	728343	1			T1	3		T2	3		T3	2
all_values[13]	728343	1			T1	3		T2	3		T3	2
all_values[14]	728343	1			T1	3		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7665444

1

T1

38

T2

37

T3

26

auto[1]

3259701

1

T1

7

T2

8

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9469118

1

T1

45

T2

45

T3

30

auto[1]

1456027

1

T44

72576

T66

227

T41

161268

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12] , all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	56026	1			T1	1		T2	1		T10	1
all_values[0]	auto[0]	auto[1]	8319	1			T44	1080		T66	14		T41	780
all_values[0]	auto[1]	auto[0]	567984	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	96014	1			T44	6178		T66	6		T41	9971
all_values[1]	auto[0]	auto[0]	633586	1			T1	3		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	94238	1			T66	18		T41	10747		T45	6
all_values[1]	auto[1]	auto[0]	279	1			T44	2		T61	2		T45	16
all_values[1]	auto[1]	auto[1]	240	1			T66	2		T41	5		T45	3
all_values[2]	auto[0]	auto[0]	622674	1			T1	3		T2	3		T3	2
all_values[2]	auto[0]	auto[1]	105459	1			T44	7255		T41	10748		T45	4
all_values[2]	auto[1]	auto[1]	210	1			T44	3		T41	4		T45	4
all_values[3]	auto[0]	auto[0]	622647	1			T1	3		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	105431	1			T44	7258		T41	10750		T45	6
all_values[3]	auto[1]	auto[1]	265	1			T41	2		T45	3		T174	8
all_values[4]	auto[0]	auto[0]	653513	1			T1	3		T2	3		T3	2
all_values[4]	auto[0]	auto[1]	74608	1			T66	20		T41	10746		T45	6
all_values[4]	auto[1]	auto[0]	21	1			T70	3		T71	1		T231	1
all_values[4]	auto[1]	auto[1]	201	1			T66	1		T41	6		T45	3
all_values[5]	auto[0]	auto[0]	624047	1			T1	3		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	104061	1			T44	7257		T66	18		T41	10741
all_values[5]	auto[1]	auto[1]	235	1			T66	3		T41	3		T45	3
all_values[6]	auto[0]	auto[0]	113703	1			T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	18032	1			T44	469		T66	15		T41	5858
all_values[6]	auto[1]	auto[0]	508943	1			T1	1		T2	1		T10	1
all_values[6]	auto[1]	auto[1]	87665	1			T44	6788		T66	6		T41	4895
all_values[7]	auto[0]	auto[0]	604074	1			T1	3		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	97234	1			T44	7148		T66	16		T41	10611
all_values[7]	auto[1]	auto[0]	22560	1			T2	1		T10	1		T40	208
all_values[7]	auto[1]	auto[1]	4475	1			T44	110		T66	5		T41	142
all_values[8]	auto[0]	auto[0]	84289	1			T1	2		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	10458	1			T44	62		T66	15		T41	185
all_values[8]	auto[1]	auto[0]	538354	1			T1	1		T2	1		T10	1
all_values[8]	auto[1]	auto[1]	95242	1			T44	7195		T66	5		T41	10567
all_values[9]	auto[0]	auto[0]	105340	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	11854	1			T44	250		T41	316		T45	3
all_values[9]	auto[1]	auto[0]	523438	1			T1	1		T2	1		T6	1
all_values[9]	auto[1]	auto[1]	87711	1			T44	7008		T41	10437		T45	3
all_values[10]	auto[0]	auto[0]	658845	1			T1	3		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	69300	1			T66	19		T41	10749		T45	5
all_values[10]	auto[1]	auto[1]	198	1			T66	1		T41	3		T45	1
all_values[11]	auto[0]	auto[0]	2773	1			T1	1		T2	1		T10	1
all_values[11]	auto[0]	auto[1]	606	1			T44	12		T41	18		T45	6
all_values[11]	auto[1]	auto[0]	619911	1			T1	2		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	105053	1			T44	7245		T41	10734		T45	3
all_values[12]	auto[0]	auto[0]	653500	1			T1	3		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	74636	1			T66	19		T41	10748		T45	4
all_values[12]	auto[1]	auto[1]	207	1			T66	2		T41	4		T45	4
all_values[13]	auto[0]	auto[0]	629954	1			T1	3		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	98151	1			T66	19		T41	10746		T45	7
all_values[13]	auto[1]	auto[1]	238	1			T66	2		T41	1		T45	2
all_values[14]	auto[0]	auto[0]	622657	1			T1	3		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	105429	1			T44	7255		T66	17		T41	10746
all_values[14]	auto[1]	auto[1]	257	1			T44	3		T66	4		T41	5