Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	728343	1			T1	3		T2	3		T3	2
all_pins[1]	728343	1			T1	3		T2	3		T3	2
all_pins[2]	728343	1			T1	3		T2	3		T3	2
all_pins[3]	728343	1			T1	3		T2	3		T3	2
all_pins[4]	728343	1			T1	3		T2	3		T3	2
all_pins[5]	728343	1			T1	3		T2	3		T3	2
all_pins[6]	728343	1			T1	3		T2	3		T3	2
all_pins[7]	728343	1			T1	3		T2	3		T3	2
all_pins[8]	728343	1			T1	3		T2	3		T3	2
all_pins[9]	728343	1			T1	3		T2	3		T3	2
all_pins[10]	728343	1			T1	3		T2	3		T3	2
all_pins[11]	728343	1			T1	3		T2	3		T3	2
all_pins[12]	728343	1			T1	3		T2	3		T3	2
all_pins[13]	728343	1			T1	3		T2	3		T3	2
all_pins[14]	728343	1			T1	3		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	7670811	1			T1	38		T2	37		T3	26
values[0x1]	3254334	1			T1	7		T2	8		T3	4
transitions[0x0=>0x1]	2606751	1			T1	6		T2	5		T3	4
transitions[0x1=>0x0]	2605721	1			T1	5		T2	4		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	67473	1			T1	1		T2	1		T10	1
all_pins[0]	values[0x1]	660870	1			T1	2		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	660469	1			T1	2		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	73	1			T41	1		T174	2		T248	2
all_pins[1]	values[0x0]	727869	1			T1	3		T2	3		T3	2
all_pins[1]	values[0x1]	474	1			T44	3		T61	2		T41	2
all_pins[1]	transitions[0x0=>0x1]	440	1			T44	3		T61	2		T41	1
all_pins[1]	transitions[0x1=>0x0]	83	1			T41	1		T45	3		T174	1
all_pins[2]	values[0x0]	728226	1			T1	3		T2	3		T3	2
all_pins[2]	values[0x1]	117	1			T41	2		T45	3		T174	3
all_pins[2]	transitions[0x0=>0x1]	94	1			T41	2		T45	2		T174	1
all_pins[2]	transitions[0x1=>0x0]	88	1			T41	2		T174	6		T248	1
all_pins[3]	values[0x0]	728232	1			T1	3		T2	3		T3	2
all_pins[3]	values[0x1]	111	1			T41	2		T45	1		T174	8
all_pins[3]	transitions[0x0=>0x1]	88	1			T45	1		T174	6		T248	2
all_pins[3]	transitions[0x1=>0x0]	99	1			T66	1		T41	2		T70	4
all_pins[4]	values[0x0]	728221	1			T1	3		T2	3		T3	2
all_pins[4]	values[0x1]	122	1			T66	1		T41	4		T70	4
all_pins[4]	transitions[0x0=>0x1]	100	1			T41	4		T70	4		T45	1
all_pins[4]	transitions[0x1=>0x0]	110	1			T66	2		T41	3		T45	2
all_pins[5]	values[0x0]	728211	1			T1	3		T2	3		T3	2
all_pins[5]	values[0x1]	132	1			T66	3		T41	3		T45	2
all_pins[5]	transitions[0x0=>0x1]	105	1			T66	1		T41	3		T45	2
all_pins[5]	transitions[0x1=>0x0]	596235	1			T1	1		T2	1		T10	1
all_pins[6]	values[0x0]	132081	1			T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	596262	1			T1	1		T2	1		T10	1
all_pins[6]	transitions[0x0=>0x1]	578724	1			T1	1		T40	3000		T68	3
all_pins[6]	transitions[0x1=>0x0]	12392	1			T40	4		T68	21		T80	27
all_pins[7]	values[0x0]	698413	1			T1	3		T2	2		T3	2
all_pins[7]	values[0x1]	29930	1			T2	1		T10	1		T40	267
all_pins[7]	transitions[0x0=>0x1]	9589	1			T68	17		T80	19		T60	5
all_pins[7]	transitions[0x1=>0x0]	612942	1			T1	1		T40	3043		T68	16
all_pins[8]	values[0x0]	95060	1			T1	2		T2	2		T3	2
all_pins[8]	values[0x1]	633283	1			T1	1		T2	1		T10	1
all_pins[8]	transitions[0x0=>0x1]	24292	1			T40	22		T68	21		T80	16
all_pins[8]	transitions[0x1=>0x0]	2072	1			T6	1		T8	1		T68	3
all_pins[9]	values[0x0]	117280	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	611063	1			T1	1		T2	1		T6	1
all_pins[9]	transitions[0x0=>0x1]	611034	1			T1	1		T2	1		T6	1
all_pins[9]	transitions[0x1=>0x0]	71	1			T41	3		T45	1		T174	3
all_pins[10]	values[0x0]	728243	1			T1	3		T2	3		T3	2
all_pins[10]	values[0x1]	100	1			T41	3		T45	1		T174	3
all_pins[10]	transitions[0x0=>0x1]	81	1			T41	2		T45	1		T174	3
all_pins[10]	transitions[0x1=>0x0]	721505	1			T1	2		T2	2		T3	2
all_pins[11]	values[0x0]	6819	1			T1	1		T2	1		T10	1
all_pins[11]	values[0x1]	721524	1			T1	2		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	721493	1			T1	2		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	69	1			T66	1		T41	2		T45	1
all_pins[12]	values[0x0]	728243	1			T1	3		T2	3		T3	2
all_pins[12]	values[0x1]	100	1			T66	1		T41	2		T45	1
all_pins[12]	transitions[0x0=>0x1]	65	1			T41	1		T45	1		T174	2
all_pins[12]	transitions[0x1=>0x0]	81	1			T174	1		T248	2		T230	1
all_pins[13]	values[0x0]	728227	1			T1	3		T2	3		T3	2
all_pins[13]	values[0x1]	116	1			T66	1		T41	1		T174	2
all_pins[13]	transitions[0x0=>0x1]	91	1			T41	1		T174	1		T248	2
all_pins[13]	transitions[0x1=>0x0]	105	1			T41	2		T174	5		T248	3
all_pins[14]	values[0x0]	728213	1			T1	3		T2	3		T3	2
all_pins[14]	values[0x1]	130	1			T66	1		T41	2		T174	6
all_pins[14]	transitions[0x0=>0x1]	86	1			T66	1		T41	1		T174	4
all_pins[14]	transitions[0x1=>0x0]	659796	1			T1	1		T2	1		T3	1