Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 21 0 21 100.00
Crosses 90 0 90 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 15 0 15 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 90 0 90 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 521 1 T44 4 T66 4 T41 11
all_values[1] 521 1 T44 4 T66 4 T41 11
all_values[2] 521 1 T44 4 T66 4 T41 11
all_values[3] 521 1 T44 4 T66 4 T41 11
all_values[4] 521 1 T44 4 T66 4 T41 11
all_values[5] 521 1 T44 4 T66 4 T41 11
all_values[6] 521 1 T44 4 T66 4 T41 11
all_values[7] 521 1 T44 4 T66 4 T41 11
all_values[8] 521 1 T44 4 T66 4 T41 11
all_values[9] 521 1 T44 4 T66 4 T41 11
all_values[10] 521 1 T44 4 T66 4 T41 11
all_values[11] 521 1 T44 4 T66 4 T41 11
all_values[12] 521 1 T44 4 T66 4 T41 11
all_values[13] 521 1 T44 4 T66 4 T41 11
all_values[14] 521 1 T44 4 T66 4 T41 11



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4072 1 T44 36 T66 29 T41 84
auto[1] 3743 1 T44 24 T66 31 T41 81



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1161 1 T44 24 T66 20 T41 25
auto[1] 6654 1 T44 36 T66 40 T41 140



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4615 1 T44 41 T66 42 T41 107
auto[1] 3200 1 T44 19 T66 18 T41 58



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 90 0 90 100.00
Automatically Generated Cross Bins 90 0 90 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 41 1 T41 2 T248 1 T196 1
all_values[0] auto[0] auto[0] auto[1] 106 1 T41 4 T45 1 T174 9
all_values[0] auto[0] auto[1] auto[0] 11 1 T66 1 T199 1 T201 1
all_values[0] auto[0] auto[1] auto[1] 148 1 T44 2 T66 2 T41 2
all_values[0] auto[1] auto[0] auto[1] 118 1 T44 1 T66 1 T45 2
all_values[0] auto[1] auto[1] auto[1] 97 1 T44 1 T41 3 T45 1
all_values[1] auto[0] auto[0] auto[0] 37 1 T44 1 T41 1 T174 3
all_values[1] auto[0] auto[0] auto[1] 118 1 T66 1 T41 3 T45 2
all_values[1] auto[0] auto[1] auto[0] 30 1 T44 3 T66 1 T174 1
all_values[1] auto[0] auto[1] auto[1] 118 1 T41 2 T45 2 T174 1
all_values[1] auto[1] auto[0] auto[1] 114 1 T66 2 T41 2 T45 3
all_values[1] auto[1] auto[1] auto[1] 104 1 T41 3 T174 5 T248 1
all_values[2] auto[0] auto[0] auto[0] 50 1 T66 1 T230 4 T258 2
all_values[2] auto[0] auto[0] auto[1] 129 1 T44 1 T41 1 T45 2
all_values[2] auto[0] auto[1] auto[0] 30 1 T66 3 T41 1 T45 1
all_values[2] auto[0] auto[1] auto[1] 102 1 T41 5 T248 4 T149 3
all_values[2] auto[1] auto[0] auto[1] 107 1 T44 3 T41 1 T45 2
all_values[2] auto[1] auto[1] auto[1] 103 1 T41 3 T45 2 T174 4
all_values[3] auto[0] auto[0] auto[0] 31 1 T41 1 T194 1 T195 1
all_values[3] auto[0] auto[0] auto[1] 125 1 T44 2 T41 5 T45 2
all_values[3] auto[0] auto[1] auto[0] 28 1 T66 4 T230 2 T149 1
all_values[3] auto[0] auto[1] auto[1] 114 1 T44 1 T41 2 T45 3
all_values[3] auto[1] auto[0] auto[1] 122 1 T44 1 T41 2 T45 2
all_values[3] auto[1] auto[1] auto[1] 101 1 T41 1 T174 5 T248 2
all_values[4] auto[0] auto[0] auto[0] 52 1 T44 2 T41 1 T174 1
all_values[4] auto[0] auto[0] auto[1] 122 1 T66 1 T41 3 T45 3
all_values[4] auto[0] auto[1] auto[0] 28 1 T44 2 T248 1 T201 5
all_values[4] auto[0] auto[1] auto[1] 118 1 T66 2 T41 1 T45 1
all_values[4] auto[1] auto[0] auto[1] 118 1 T41 3 T45 2 T174 3
all_values[4] auto[1] auto[1] auto[1] 83 1 T66 1 T41 3 T45 1
all_values[5] auto[0] auto[0] auto[0] 56 1 T44 1 T41 6 T45 1
all_values[5] auto[0] auto[0] auto[1] 107 1 T66 1 T174 4 T248 2
all_values[5] auto[0] auto[1] auto[0] 24 1 T41 2 T227 1 T259 2
all_values[5] auto[0] auto[1] auto[1] 136 1 T44 2 T66 1 T41 2
all_values[5] auto[1] auto[0] auto[1] 101 1 T44 1 T45 2 T174 5
all_values[5] auto[1] auto[1] auto[1] 97 1 T66 2 T41 1 T45 1
all_values[6] auto[0] auto[0] auto[0] 36 1 T44 1 T45 1 T174 1
all_values[6] auto[0] auto[0] auto[1] 133 1 T44 2 T66 1 T41 3
all_values[6] auto[0] auto[1] auto[0] 38 1 T194 2 T258 1 T197 2
all_values[6] auto[0] auto[1] auto[1] 90 1 T66 1 T41 2 T174 8
all_values[6] auto[1] auto[0] auto[1] 127 1 T44 1 T66 1 T41 3
all_values[6] auto[1] auto[1] auto[1] 97 1 T66 1 T41 3 T45 1
all_values[7] auto[0] auto[0] auto[0] 34 1 T150 2 T196 1 T201 4
all_values[7] auto[0] auto[0] auto[1] 125 1 T44 1 T66 2 T41 5
all_values[7] auto[0] auto[1] auto[0] 37 1 T174 2 T230 1 T195 1
all_values[7] auto[0] auto[1] auto[1] 114 1 T66 1 T41 2 T174 4
all_values[7] auto[1] auto[0] auto[1] 120 1 T44 3 T66 1 T41 1
all_values[7] auto[1] auto[1] auto[1] 91 1 T41 3 T45 2 T174 5
all_values[8] auto[0] auto[0] auto[0] 41 1 T44 1 T174 2 T194 1
all_values[8] auto[0] auto[0] auto[1] 101 1 T66 2 T41 5 T45 4
all_values[8] auto[0] auto[1] auto[0] 32 1 T66 1 T41 1 T174 2
all_values[8] auto[0] auto[1] auto[1] 119 1 T44 2 T41 1 T45 1
all_values[8] auto[1] auto[0] auto[1] 106 1 T41 3 T45 2 T174 4
all_values[8] auto[1] auto[1] auto[1] 122 1 T44 1 T66 1 T41 1
all_values[9] auto[0] auto[0] auto[0] 60 1 T66 3 T45 2 T194 1
all_values[9] auto[0] auto[0] auto[1] 98 1 T41 2 T174 3 T248 2
all_values[9] auto[0] auto[1] auto[0] 31 1 T66 1 T45 1 T258 2
all_values[9] auto[0] auto[1] auto[1] 111 1 T44 1 T41 6 T45 1
all_values[9] auto[1] auto[0] auto[1] 122 1 T44 1 T41 1 T45 2
all_values[9] auto[1] auto[1] auto[1] 99 1 T44 2 T41 2 T45 1
all_values[10] auto[0] auto[0] auto[0] 51 1 T44 3 T41 1 T45 3
all_values[10] auto[0] auto[0] auto[1] 116 1 T66 2 T41 2 T174 4
all_values[10] auto[0] auto[1] auto[0] 32 1 T44 1 T66 1 T248 3
all_values[10] auto[0] auto[1] auto[1] 124 1 T41 5 T45 3 T174 7
all_values[10] auto[1] auto[0] auto[1] 105 1 T66 1 T41 2 T149 2
all_values[10] auto[1] auto[1] auto[1] 93 1 T41 1 T45 1 T174 4
all_values[11] auto[0] auto[0] auto[0] 44 1 T44 1 T248 1 T230 2
all_values[11] auto[0] auto[0] auto[1] 99 1 T41 1 T174 3 T248 2
all_values[11] auto[0] auto[1] auto[0] 39 1 T66 4 T41 1 T248 1
all_values[11] auto[0] auto[1] auto[1] 116 1 T44 2 T41 4 T45 4
all_values[11] auto[1] auto[0] auto[1] 113 1 T44 1 T41 4 T174 3
all_values[11] auto[1] auto[1] auto[1] 110 1 T41 1 T45 3 T174 3
all_values[12] auto[0] auto[0] auto[0] 44 1 T44 3 T45 1 T248 5
all_values[12] auto[0] auto[0] auto[1] 114 1 T66 2 T41 1 T45 1
all_values[12] auto[0] auto[1] auto[0] 44 1 T44 1 T41 1 T174 4
all_values[12] auto[0] auto[1] auto[1] 112 1 T41 5 T45 1 T149 2
all_values[12] auto[1] auto[0] auto[1] 116 1 T66 1 T41 2 T45 2
all_values[12] auto[1] auto[1] auto[1] 91 1 T66 1 T41 2 T45 2
all_values[13] auto[0] auto[0] auto[0] 51 1 T44 2 T41 3 T195 1
all_values[13] auto[0] auto[0] auto[1] 110 1 T66 2 T41 3 T45 2
all_values[13] auto[0] auto[1] auto[0] 45 1 T44 2 T41 2 T260 1
all_values[13] auto[0] auto[1] auto[1] 108 1 T45 1 T174 6 T248 1
all_values[13] auto[1] auto[0] auto[1] 112 1 T66 1 T45 4 T174 6
all_values[13] auto[1] auto[1] auto[1] 95 1 T66 1 T41 3 T174 1
all_values[14] auto[0] auto[0] auto[0] 37 1 T149 1 T195 1 T150 1
all_values[14] auto[0] auto[0] auto[1] 93 1 T44 1 T66 1 T41 4
all_values[14] auto[0] auto[1] auto[0] 47 1 T41 2 T230 1 T194 3
all_values[14] auto[0] auto[1] auto[1] 128 1 T41 1 T45 2 T174 9
all_values[14] auto[1] auto[0] auto[1] 110 1 T44 2 T66 2 T41 3
all_values[14] auto[1] auto[1] auto[1] 106 1 T44 1 T66 1 T41 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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