Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.67 97.22 92.08 97.66 83.74 94.60 98.67 91.70


Total test records in report: 1458
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T1308 /workspace/coverage/default/6.i2c_host_may_nack.1360626230 Apr 28 12:59:18 PM PDT 24 Apr 28 12:59:30 PM PDT 24 634867080 ps
T1309 /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.3563577309 Apr 28 01:01:35 PM PDT 24 Apr 28 01:01:37 PM PDT 24 705536379 ps
T1310 /workspace/coverage/default/30.i2c_host_fifo_watermark.3868630597 Apr 28 01:01:37 PM PDT 24 Apr 28 01:06:54 PM PDT 24 18372394068 ps
T1311 /workspace/coverage/default/37.i2c_host_fifo_reset_rx.2710051881 Apr 28 01:02:27 PM PDT 24 Apr 28 01:02:31 PM PDT 24 414672604 ps
T1312 /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.1685099433 Apr 28 01:02:17 PM PDT 24 Apr 28 01:02:30 PM PDT 24 258008690 ps
T1313 /workspace/coverage/default/15.i2c_target_intr_stress_wr.4125390855 Apr 28 12:59:56 PM PDT 24 Apr 28 01:04:07 PM PDT 24 17088960137 ps
T1314 /workspace/coverage/default/5.i2c_host_stretch_timeout.3879391717 Apr 28 12:59:08 PM PDT 24 Apr 28 12:59:34 PM PDT 24 1060965708 ps
T1315 /workspace/coverage/default/14.i2c_host_fifo_watermark.2914242862 Apr 28 12:59:54 PM PDT 24 Apr 28 01:04:37 PM PDT 24 4046731915 ps
T1316 /workspace/coverage/default/27.i2c_host_stress_all.1796315729 Apr 28 01:01:18 PM PDT 24 Apr 28 01:04:24 PM PDT 24 106757254250 ps
T1317 /workspace/coverage/default/8.i2c_target_stretch.4230031596 Apr 28 12:59:23 PM PDT 24 Apr 28 01:02:08 PM PDT 24 29032047673 ps
T1318 /workspace/coverage/default/34.i2c_host_override.709963538 Apr 28 01:02:06 PM PDT 24 Apr 28 01:02:07 PM PDT 24 50951285 ps
T1319 /workspace/coverage/default/12.i2c_target_bad_addr.648079599 Apr 28 12:59:46 PM PDT 24 Apr 28 12:59:51 PM PDT 24 721819774 ps
T1320 /workspace/coverage/default/15.i2c_host_fifo_watermark.1096572665 Apr 28 01:00:01 PM PDT 24 Apr 28 01:04:39 PM PDT 24 3885237404 ps
T1321 /workspace/coverage/default/1.i2c_host_smoke.160809914 Apr 28 12:58:49 PM PDT 24 Apr 28 01:00:01 PM PDT 24 5876278025 ps
T1322 /workspace/coverage/default/14.i2c_target_intr_smoke.3863290716 Apr 28 12:59:59 PM PDT 24 Apr 28 01:00:04 PM PDT 24 1477494140 ps
T1323 /workspace/coverage/default/34.i2c_target_intr_smoke.2849485584 Apr 28 01:02:04 PM PDT 24 Apr 28 01:02:09 PM PDT 24 1705828401 ps
T1324 /workspace/coverage/default/11.i2c_target_timeout.3583682140 Apr 28 12:59:38 PM PDT 24 Apr 28 12:59:46 PM PDT 24 1612481906 ps
T1325 /workspace/coverage/default/35.i2c_target_unexp_stop.1322199770 Apr 28 01:02:16 PM PDT 24 Apr 28 01:02:21 PM PDT 24 6916206365 ps
T1326 /workspace/coverage/default/33.i2c_host_fifo_full.3765021147 Apr 28 01:02:03 PM PDT 24 Apr 28 01:04:22 PM PDT 24 3796276988 ps
T1327 /workspace/coverage/default/27.i2c_target_bad_addr.4196017723 Apr 28 01:01:28 PM PDT 24 Apr 28 01:01:34 PM PDT 24 3968017414 ps
T223 /workspace/coverage/default/12.i2c_target_fifo_reset_acq.2572508774 Apr 28 12:59:45 PM PDT 24 Apr 28 01:00:15 PM PDT 24 10238360840 ps
T1328 /workspace/coverage/default/14.i2c_target_stretch.1253988302 Apr 28 12:59:55 PM PDT 24 Apr 28 01:20:27 PM PDT 24 12444984113 ps
T1329 /workspace/coverage/default/37.i2c_target_stress_all.3165966637 Apr 28 01:02:26 PM PDT 24 Apr 28 01:12:22 PM PDT 24 98245158456 ps
T1330 /workspace/coverage/default/49.i2c_target_hrst.2920225921 Apr 28 01:04:02 PM PDT 24 Apr 28 01:04:06 PM PDT 24 1658611637 ps
T1331 /workspace/coverage/default/35.i2c_alert_test.1303762411 Apr 28 01:02:17 PM PDT 24 Apr 28 01:02:18 PM PDT 24 17699943 ps
T1332 /workspace/coverage/default/16.i2c_host_error_intr.625861094 Apr 28 01:00:07 PM PDT 24 Apr 28 01:00:09 PM PDT 24 394079938 ps
T1333 /workspace/coverage/default/22.i2c_target_hrst.381375980 Apr 28 01:00:50 PM PDT 24 Apr 28 01:00:53 PM PDT 24 8945519339 ps
T1334 /workspace/coverage/default/4.i2c_host_mode_toggle.425478765 Apr 28 12:59:05 PM PDT 24 Apr 28 01:00:34 PM PDT 24 1970882914 ps
T1335 /workspace/coverage/default/26.i2c_target_intr_smoke.357430138 Apr 28 01:01:14 PM PDT 24 Apr 28 01:01:21 PM PDT 24 2314720304 ps
T1336 /workspace/coverage/default/37.i2c_host_fifo_overflow.1491574903 Apr 28 01:02:25 PM PDT 24 Apr 28 01:04:34 PM PDT 24 4197775559 ps
T1337 /workspace/coverage/default/47.i2c_target_timeout.1173731536 Apr 28 01:03:41 PM PDT 24 Apr 28 01:03:48 PM PDT 24 1295018310 ps
T1338 /workspace/coverage/default/40.i2c_host_stress_all.1389155270 Apr 28 01:02:42 PM PDT 24 Apr 28 01:11:42 PM PDT 24 89819884682 ps
T1339 /workspace/coverage/default/13.i2c_target_stress_wr.1572818246 Apr 28 12:59:51 PM PDT 24 Apr 28 12:59:57 PM PDT 24 10372792204 ps
T1340 /workspace/coverage/default/5.i2c_host_stress_all.4048403651 Apr 28 12:59:10 PM PDT 24 Apr 28 01:05:42 PM PDT 24 46003382316 ps
T1341 /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.996237586 Apr 28 01:01:09 PM PDT 24 Apr 28 01:01:15 PM PDT 24 270522119 ps
T1342 /workspace/coverage/default/8.i2c_host_fifo_full.793604645 Apr 28 12:59:30 PM PDT 24 Apr 28 01:00:05 PM PDT 24 1532663958 ps
T1343 /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1519608093 Apr 28 01:00:44 PM PDT 24 Apr 28 01:00:53 PM PDT 24 10227177683 ps
T1344 /workspace/coverage/default/44.i2c_host_fifo_watermark.260904306 Apr 28 01:03:13 PM PDT 24 Apr 28 01:04:17 PM PDT 24 2993964778 ps
T1345 /workspace/coverage/default/42.i2c_host_fifo_full.2759156963 Apr 28 01:03:00 PM PDT 24 Apr 28 01:05:16 PM PDT 24 15576478841 ps
T1346 /workspace/coverage/default/43.i2c_host_smoke.4024001945 Apr 28 01:03:11 PM PDT 24 Apr 28 01:03:35 PM PDT 24 1202017892 ps
T1347 /workspace/coverage/default/3.i2c_host_override.3360924694 Apr 28 12:58:55 PM PDT 24 Apr 28 12:58:56 PM PDT 24 43406002 ps
T1348 /workspace/coverage/default/4.i2c_host_fifo_overflow.205559484 Apr 28 12:59:10 PM PDT 24 Apr 28 12:59:50 PM PDT 24 2524189001 ps
T1349 /workspace/coverage/default/27.i2c_alert_test.609761865 Apr 28 01:01:24 PM PDT 24 Apr 28 01:01:26 PM PDT 24 55082248 ps
T1350 /workspace/coverage/default/45.i2c_target_bad_addr.633677444 Apr 28 01:03:26 PM PDT 24 Apr 28 01:03:30 PM PDT 24 686222513 ps
T1351 /workspace/coverage/default/16.i2c_target_stretch.1389343040 Apr 28 01:00:07 PM PDT 24 Apr 28 01:46:34 PM PDT 24 26197195199 ps
T1352 /workspace/coverage/default/41.i2c_target_intr_stress_wr.2961682334 Apr 28 01:02:53 PM PDT 24 Apr 28 01:03:05 PM PDT 24 5290178107 ps
T117 /workspace/coverage/default/3.i2c_sec_cm.3469744188 Apr 28 12:59:07 PM PDT 24 Apr 28 12:59:10 PM PDT 24 98083090 ps
T1353 /workspace/coverage/default/30.i2c_host_perf.2358785093 Apr 28 01:01:42 PM PDT 24 Apr 28 01:06:02 PM PDT 24 48654008514 ps
T1354 /workspace/coverage/default/19.i2c_host_stretch_timeout.1582399139 Apr 28 01:00:27 PM PDT 24 Apr 28 01:00:39 PM PDT 24 818437803 ps
T1355 /workspace/coverage/default/37.i2c_host_override.3855975468 Apr 28 01:02:27 PM PDT 24 Apr 28 01:02:28 PM PDT 24 17540846 ps
T1356 /workspace/coverage/default/13.i2c_host_mode_toggle.4203125638 Apr 28 01:00:10 PM PDT 24 Apr 28 01:01:24 PM PDT 24 3480130082 ps
T1357 /workspace/coverage/default/7.i2c_host_fifo_overflow.2629958497 Apr 28 12:59:10 PM PDT 24 Apr 28 12:59:43 PM PDT 24 4419401386 ps
T1358 /workspace/coverage/default/7.i2c_host_fifo_reset_rx.1760790400 Apr 28 12:59:11 PM PDT 24 Apr 28 12:59:18 PM PDT 24 102691631 ps
T1359 /workspace/coverage/default/46.i2c_host_may_nack.2453297263 Apr 28 01:03:31 PM PDT 24 Apr 28 01:03:35 PM PDT 24 839460405 ps
T1360 /workspace/coverage/default/8.i2c_host_fifo_overflow.1495147444 Apr 28 12:59:31 PM PDT 24 Apr 28 01:01:08 PM PDT 24 2931530963 ps
T1361 /workspace/coverage/default/8.i2c_target_bad_addr.2058087215 Apr 28 12:59:16 PM PDT 24 Apr 28 12:59:20 PM PDT 24 3558626546 ps
T1362 /workspace/coverage/default/49.i2c_target_intr_stress_wr.1532446843 Apr 28 01:03:53 PM PDT 24 Apr 28 01:05:42 PM PDT 24 8028334505 ps
T1363 /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2497605840 Apr 28 01:01:38 PM PDT 24 Apr 28 01:03:09 PM PDT 24 10031203407 ps
T1364 /workspace/coverage/default/17.i2c_host_override.3531923058 Apr 28 01:00:07 PM PDT 24 Apr 28 01:00:09 PM PDT 24 204546516 ps
T1365 /workspace/coverage/default/21.i2c_host_stress_all.1503356321 Apr 28 01:00:36 PM PDT 24 Apr 28 01:01:47 PM PDT 24 13627406397 ps
T1366 /workspace/coverage/default/0.i2c_host_may_nack.2071890398 Apr 28 12:58:41 PM PDT 24 Apr 28 12:58:49 PM PDT 24 1223892059 ps
T81 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1673896331 Apr 28 12:46:01 PM PDT 24 Apr 28 12:46:02 PM PDT 24 23960289 ps
T1367 /workspace/coverage/cover_reg_top/24.i2c_intr_test.4049422745 Apr 28 12:46:12 PM PDT 24 Apr 28 12:46:13 PM PDT 24 215564837 ps
T82 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3686543646 Apr 28 12:46:04 PM PDT 24 Apr 28 12:46:06 PM PDT 24 87591458 ps
T1368 /workspace/coverage/cover_reg_top/10.i2c_intr_test.420420597 Apr 28 12:46:08 PM PDT 24 Apr 28 12:46:10 PM PDT 24 46224878 ps
T112 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.638981055 Apr 28 12:45:53 PM PDT 24 Apr 28 12:45:57 PM PDT 24 275492313 ps
T1369 /workspace/coverage/cover_reg_top/34.i2c_intr_test.3556496226 Apr 28 12:46:13 PM PDT 24 Apr 28 12:46:14 PM PDT 24 16691270 ps
T1370 /workspace/coverage/cover_reg_top/28.i2c_intr_test.420955724 Apr 28 12:46:15 PM PDT 24 Apr 28 12:46:16 PM PDT 24 18199179 ps
T83 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3758515486 Apr 28 12:46:05 PM PDT 24 Apr 28 12:46:08 PM PDT 24 359801207 ps
T1371 /workspace/coverage/cover_reg_top/16.i2c_intr_test.877402657 Apr 28 12:46:14 PM PDT 24 Apr 28 12:46:15 PM PDT 24 15758686 ps
T127 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1468771753 Apr 28 12:46:19 PM PDT 24 Apr 28 12:46:21 PM PDT 24 258650473 ps
T148 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2078882997 Apr 28 12:46:10 PM PDT 24 Apr 28 12:46:12 PM PDT 24 18786966 ps
T155 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1614794489 Apr 28 12:46:09 PM PDT 24 Apr 28 12:46:11 PM PDT 24 18217981 ps
T151 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3764975981 Apr 28 12:46:15 PM PDT 24 Apr 28 12:46:17 PM PDT 24 36328402 ps
T1372 /workspace/coverage/cover_reg_top/5.i2c_intr_test.3534396625 Apr 28 12:45:53 PM PDT 24 Apr 28 12:45:55 PM PDT 24 20683619 ps
T1373 /workspace/coverage/cover_reg_top/7.i2c_intr_test.740158627 Apr 28 12:45:59 PM PDT 24 Apr 28 12:46:01 PM PDT 24 26044894 ps
T1374 /workspace/coverage/cover_reg_top/30.i2c_intr_test.1594083674 Apr 28 12:46:23 PM PDT 24 Apr 28 12:46:29 PM PDT 24 18408253 ps
T128 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1606347056 Apr 28 12:45:55 PM PDT 24 Apr 28 12:45:58 PM PDT 24 129536840 ps
T1375 /workspace/coverage/cover_reg_top/48.i2c_intr_test.2907766994 Apr 28 12:46:19 PM PDT 24 Apr 28 12:46:20 PM PDT 24 19331570 ps
T152 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2597591619 Apr 28 12:46:13 PM PDT 24 Apr 28 12:46:15 PM PDT 24 23081213 ps
T1376 /workspace/coverage/cover_reg_top/19.i2c_intr_test.3373743970 Apr 28 12:46:15 PM PDT 24 Apr 28 12:46:16 PM PDT 24 19193584 ps
T1377 /workspace/coverage/cover_reg_top/18.i2c_intr_test.2972753113 Apr 28 12:46:08 PM PDT 24 Apr 28 12:46:10 PM PDT 24 149807357 ps
T1378 /workspace/coverage/cover_reg_top/15.i2c_intr_test.3594442871 Apr 28 12:46:08 PM PDT 24 Apr 28 12:46:10 PM PDT 24 16486225 ps
T130 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3267658570 Apr 28 12:45:59 PM PDT 24 Apr 28 12:46:01 PM PDT 24 34192962 ps
T169 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.399375129 Apr 28 12:46:02 PM PDT 24 Apr 28 12:46:05 PM PDT 24 91411138 ps
T1379 /workspace/coverage/cover_reg_top/47.i2c_intr_test.2887916181 Apr 28 12:46:24 PM PDT 24 Apr 28 12:46:26 PM PDT 24 17154189 ps
T129 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2484853170 Apr 28 12:46:24 PM PDT 24 Apr 28 12:46:26 PM PDT 24 95541638 ps
T156 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.127293974 Apr 28 12:46:03 PM PDT 24 Apr 28 12:46:06 PM PDT 24 80758044 ps
T1380 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1347910872 Apr 28 12:46:12 PM PDT 24 Apr 28 12:46:14 PM PDT 24 19385473 ps
T1381 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3573769844 Apr 28 12:45:53 PM PDT 24 Apr 28 12:45:56 PM PDT 24 31722718 ps
T131 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.4006422724 Apr 28 12:46:07 PM PDT 24 Apr 28 12:46:11 PM PDT 24 291302199 ps
T153 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2330287367 Apr 28 12:46:10 PM PDT 24 Apr 28 12:46:12 PM PDT 24 45820005 ps
T137 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1393711301 Apr 28 12:46:01 PM PDT 24 Apr 28 12:46:05 PM PDT 24 272925549 ps
T144 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1316648051 Apr 28 12:45:53 PM PDT 24 Apr 28 12:45:55 PM PDT 24 118286795 ps
T132 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2226995191 Apr 28 12:46:02 PM PDT 24 Apr 28 12:46:07 PM PDT 24 737546169 ps
T175 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1987291245 Apr 28 12:46:02 PM PDT 24 Apr 28 12:46:04 PM PDT 24 22711761 ps
T134 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2910804849 Apr 28 12:46:05 PM PDT 24 Apr 28 12:46:09 PM PDT 24 191556105 ps
T133 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3588039077 Apr 28 12:45:56 PM PDT 24 Apr 28 12:45:58 PM PDT 24 148660341 ps
T1382 /workspace/coverage/cover_reg_top/43.i2c_intr_test.217590442 Apr 28 12:46:18 PM PDT 24 Apr 28 12:46:19 PM PDT 24 19401295 ps
T170 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3907879325 Apr 28 12:46:07 PM PDT 24 Apr 28 12:46:09 PM PDT 24 103578447 ps
T140 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1236332616 Apr 28 12:45:53 PM PDT 24 Apr 28 12:45:56 PM PDT 24 282845999 ps
T176 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.710871630 Apr 28 12:46:09 PM PDT 24 Apr 28 12:46:11 PM PDT 24 46026536 ps
T193 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2775357434 Apr 28 12:46:04 PM PDT 24 Apr 28 12:46:06 PM PDT 24 35583682 ps
T1383 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.269236839 Apr 28 12:45:56 PM PDT 24 Apr 28 12:45:57 PM PDT 24 23400153 ps
T192 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.904171036 Apr 28 12:46:16 PM PDT 24 Apr 28 12:46:18 PM PDT 24 85698640 ps
T1384 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1852481574 Apr 28 12:45:57 PM PDT 24 Apr 28 12:45:59 PM PDT 24 35142420 ps
T1385 /workspace/coverage/cover_reg_top/0.i2c_intr_test.1502987249 Apr 28 12:45:52 PM PDT 24 Apr 28 12:45:54 PM PDT 24 17369524 ps
T1386 /workspace/coverage/cover_reg_top/3.i2c_intr_test.1346284213 Apr 28 12:45:59 PM PDT 24 Apr 28 12:46:01 PM PDT 24 19832541 ps
T1387 /workspace/coverage/cover_reg_top/29.i2c_intr_test.2579830013 Apr 28 12:46:22 PM PDT 24 Apr 28 12:46:23 PM PDT 24 16648568 ps
T216 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.535159317 Apr 28 12:46:20 PM PDT 24 Apr 28 12:46:26 PM PDT 24 26484538 ps
T217 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1569460296 Apr 28 12:46:03 PM PDT 24 Apr 28 12:46:07 PM PDT 24 311134945 ps
T1388 /workspace/coverage/cover_reg_top/8.i2c_intr_test.2566442700 Apr 28 12:46:02 PM PDT 24 Apr 28 12:46:04 PM PDT 24 15829994 ps
T1389 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2548569231 Apr 28 12:46:08 PM PDT 24 Apr 28 12:46:11 PM PDT 24 47885474 ps
T157 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2269664353 Apr 28 12:46:02 PM PDT 24 Apr 28 12:46:07 PM PDT 24 141966722 ps
T143 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2314143021 Apr 28 12:45:59 PM PDT 24 Apr 28 12:46:01 PM PDT 24 151424818 ps
T1390 /workspace/coverage/cover_reg_top/32.i2c_intr_test.1304486443 Apr 28 12:46:21 PM PDT 24 Apr 28 12:46:22 PM PDT 24 41256281 ps
T1391 /workspace/coverage/cover_reg_top/27.i2c_intr_test.2209184265 Apr 28 12:46:17 PM PDT 24 Apr 28 12:46:18 PM PDT 24 28427273 ps
T158 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1685490027 Apr 28 12:46:13 PM PDT 24 Apr 28 12:46:15 PM PDT 24 134031224 ps
T146 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2664880000 Apr 28 12:46:06 PM PDT 24 Apr 28 12:46:09 PM PDT 24 255159948 ps
T1392 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.34509735 Apr 28 12:46:06 PM PDT 24 Apr 28 12:46:08 PM PDT 24 28136382 ps
T1393 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2078129949 Apr 28 12:46:06 PM PDT 24 Apr 28 12:46:09 PM PDT 24 39348701 ps
T171 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3506881408 Apr 28 12:46:09 PM PDT 24 Apr 28 12:46:12 PM PDT 24 279182045 ps
T135 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4087775254 Apr 28 12:46:09 PM PDT 24 Apr 28 12:46:12 PM PDT 24 281082847 ps
T1394 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.4277496330 Apr 28 12:45:50 PM PDT 24 Apr 28 12:45:52 PM PDT 24 19676613 ps
T147 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3688428204 Apr 28 12:46:01 PM PDT 24 Apr 28 12:46:04 PM PDT 24 160724652 ps
T159 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1859336096 Apr 28 12:45:59 PM PDT 24 Apr 28 12:46:03 PM PDT 24 325225776 ps
T1395 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2498283386 Apr 28 12:46:12 PM PDT 24 Apr 28 12:46:14 PM PDT 24 64079331 ps
T172 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.859145319 Apr 28 12:46:13 PM PDT 24 Apr 28 12:46:15 PM PDT 24 56697733 ps
T1396 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3562779008 Apr 28 12:46:01 PM PDT 24 Apr 28 12:46:03 PM PDT 24 31632276 ps
T1397 /workspace/coverage/cover_reg_top/33.i2c_intr_test.452238575 Apr 28 12:46:15 PM PDT 24 Apr 28 12:46:16 PM PDT 24 27491744 ps
T173 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.837621735 Apr 28 12:46:02 PM PDT 24 Apr 28 12:46:04 PM PDT 24 32268935 ps
T1398 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2935449842 Apr 28 12:46:10 PM PDT 24 Apr 28 12:46:13 PM PDT 24 43809674 ps
T1399 /workspace/coverage/cover_reg_top/35.i2c_intr_test.3328880833 Apr 28 12:46:22 PM PDT 24 Apr 28 12:46:24 PM PDT 24 43948433 ps
T1400 /workspace/coverage/cover_reg_top/17.i2c_intr_test.1923118590 Apr 28 12:46:10 PM PDT 24 Apr 28 12:46:12 PM PDT 24 23868381 ps
T1401 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3002947502 Apr 28 12:46:02 PM PDT 24 Apr 28 12:46:04 PM PDT 24 58258482 ps
T1402 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3033779921 Apr 28 12:46:15 PM PDT 24 Apr 28 12:46:17 PM PDT 24 84162037 ps
T1403 /workspace/coverage/cover_reg_top/31.i2c_intr_test.757066830 Apr 28 12:46:23 PM PDT 24 Apr 28 12:46:24 PM PDT 24 58573649 ps
T138 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.243442643 Apr 28 12:46:05 PM PDT 24 Apr 28 12:46:07 PM PDT 24 82273764 ps
T160 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1292398944 Apr 28 12:46:06 PM PDT 24 Apr 28 12:46:08 PM PDT 24 46669507 ps
T1404 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1500660631 Apr 28 12:45:53 PM PDT 24 Apr 28 12:45:56 PM PDT 24 44699858 ps
T1405 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.3547078456 Apr 28 12:46:01 PM PDT 24 Apr 28 12:46:04 PM PDT 24 35451183 ps
T1406 /workspace/coverage/cover_reg_top/9.i2c_intr_test.2437066383 Apr 28 12:46:01 PM PDT 24 Apr 28 12:46:02 PM PDT 24 17198564 ps
T1407 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3795834619 Apr 28 12:45:59 PM PDT 24 Apr 28 12:46:02 PM PDT 24 122658409 ps
T1408 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1538422681 Apr 28 12:45:51 PM PDT 24 Apr 28 12:45:53 PM PDT 24 26336465 ps
T1409 /workspace/coverage/cover_reg_top/22.i2c_intr_test.1555415401 Apr 28 12:46:21 PM PDT 24 Apr 28 12:46:24 PM PDT 24 33498795 ps
T1410 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.4046078104 Apr 28 12:45:51 PM PDT 24 Apr 28 12:45:53 PM PDT 24 64028003 ps
T161 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1555968703 Apr 28 12:45:51 PM PDT 24 Apr 28 12:45:53 PM PDT 24 84513638 ps
T1411 /workspace/coverage/cover_reg_top/12.i2c_intr_test.132537440 Apr 28 12:46:21 PM PDT 24 Apr 28 12:46:25 PM PDT 24 26964565 ps
T1412 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2257148287 Apr 28 12:46:09 PM PDT 24 Apr 28 12:46:13 PM PDT 24 115505980 ps
T1413 /workspace/coverage/cover_reg_top/44.i2c_intr_test.147567321 Apr 28 12:46:18 PM PDT 24 Apr 28 12:46:19 PM PDT 24 38585212 ps
T1414 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.790082687 Apr 28 12:45:52 PM PDT 24 Apr 28 12:45:56 PM PDT 24 181395973 ps
T162 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2821570241 Apr 28 12:46:06 PM PDT 24 Apr 28 12:46:08 PM PDT 24 20176721 ps
T163 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2610337736 Apr 28 12:46:04 PM PDT 24 Apr 28 12:46:06 PM PDT 24 56200984 ps
T1415 /workspace/coverage/cover_reg_top/42.i2c_intr_test.4213662371 Apr 28 12:46:23 PM PDT 24 Apr 28 12:46:25 PM PDT 24 21500682 ps
T1416 /workspace/coverage/cover_reg_top/23.i2c_intr_test.3806961324 Apr 28 12:46:20 PM PDT 24 Apr 28 12:46:22 PM PDT 24 141482384 ps
T1417 /workspace/coverage/cover_reg_top/11.i2c_intr_test.1905821402 Apr 28 12:46:09 PM PDT 24 Apr 28 12:46:11 PM PDT 24 15110574 ps
T1418 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3259677851 Apr 28 12:46:08 PM PDT 24 Apr 28 12:46:12 PM PDT 24 388651136 ps
T164 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.65766197 Apr 28 12:46:07 PM PDT 24 Apr 28 12:46:09 PM PDT 24 18588702 ps
T1419 /workspace/coverage/cover_reg_top/49.i2c_intr_test.1103447137 Apr 28 12:46:18 PM PDT 24 Apr 28 12:46:19 PM PDT 24 18533495 ps
T1420 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3981993915 Apr 28 12:46:02 PM PDT 24 Apr 28 12:46:05 PM PDT 24 200246515 ps
T1421 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.705608015 Apr 28 12:46:02 PM PDT 24 Apr 28 12:46:04 PM PDT 24 98020774 ps
T1422 /workspace/coverage/cover_reg_top/4.i2c_intr_test.2699387435 Apr 28 12:46:11 PM PDT 24 Apr 28 12:46:13 PM PDT 24 59654652 ps
T232 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.491373913 Apr 28 12:46:08 PM PDT 24 Apr 28 12:46:11 PM PDT 24 170910664 ps
T1423 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.100443206 Apr 28 12:46:02 PM PDT 24 Apr 28 12:46:04 PM PDT 24 188055114 ps
T165 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1074868279 Apr 28 12:46:25 PM PDT 24 Apr 28 12:46:28 PM PDT 24 26657922 ps
T1424 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.854033472 Apr 28 12:46:19 PM PDT 24 Apr 28 12:46:21 PM PDT 24 253302850 ps
T1425 /workspace/coverage/cover_reg_top/39.i2c_intr_test.1643209030 Apr 28 12:46:21 PM PDT 24 Apr 28 12:46:24 PM PDT 24 16105733 ps
T1426 /workspace/coverage/cover_reg_top/2.i2c_intr_test.4061391767 Apr 28 12:45:58 PM PDT 24 Apr 28 12:45:59 PM PDT 24 19592313 ps
T166 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3212252678 Apr 28 12:45:50 PM PDT 24 Apr 28 12:45:52 PM PDT 24 21797187 ps
T1427 /workspace/coverage/cover_reg_top/37.i2c_intr_test.4028202801 Apr 28 12:46:16 PM PDT 24 Apr 28 12:46:17 PM PDT 24 21064024 ps
T139 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.567449078 Apr 28 12:46:10 PM PDT 24 Apr 28 12:46:13 PM PDT 24 150900173 ps
T1428 /workspace/coverage/cover_reg_top/13.i2c_intr_test.2252737189 Apr 28 12:46:07 PM PDT 24 Apr 28 12:46:09 PM PDT 24 40074053 ps
T1429 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.309863094 Apr 28 12:46:04 PM PDT 24 Apr 28 12:46:06 PM PDT 24 25559522 ps
T1430 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.277900638 Apr 28 12:46:08 PM PDT 24 Apr 28 12:46:12 PM PDT 24 53497072 ps
T167 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.566030581 Apr 28 12:45:52 PM PDT 24 Apr 28 12:45:54 PM PDT 24 234942193 ps
T1431 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2798094610 Apr 28 12:46:04 PM PDT 24 Apr 28 12:46:06 PM PDT 24 167138885 ps
T1432 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2377171022 Apr 28 12:45:52 PM PDT 24 Apr 28 12:45:55 PM PDT 24 27823983 ps
T141 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3407903747 Apr 28 12:46:09 PM PDT 24 Apr 28 12:46:11 PM PDT 24 178967257 ps
T1433 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.396315058 Apr 28 12:45:53 PM PDT 24 Apr 28 12:45:55 PM PDT 24 16810149 ps
T1434 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3966893584 Apr 28 12:46:02 PM PDT 24 Apr 28 12:46:03 PM PDT 24 24608172 ps
T1435 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.304555080 Apr 28 12:46:04 PM PDT 24 Apr 28 12:46:06 PM PDT 24 40025308 ps
T1436 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.523363755 Apr 28 12:45:50 PM PDT 24 Apr 28 12:45:54 PM PDT 24 95847396 ps
T1437 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1354755269 Apr 28 12:45:51 PM PDT 24 Apr 28 12:45:55 PM PDT 24 441652875 ps
T1438 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3135039857 Apr 28 12:46:06 PM PDT 24 Apr 28 12:46:08 PM PDT 24 18080198 ps
T1439 /workspace/coverage/cover_reg_top/21.i2c_intr_test.837094177 Apr 28 12:46:15 PM PDT 24 Apr 28 12:46:16 PM PDT 24 84369093 ps
T145 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1549935377 Apr 28 12:46:06 PM PDT 24 Apr 28 12:46:09 PM PDT 24 297515612 ps
T1440 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.4239755457 Apr 28 12:46:11 PM PDT 24 Apr 28 12:46:12 PM PDT 24 59790089 ps
T1441 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.4185754851 Apr 28 12:46:14 PM PDT 24 Apr 28 12:46:16 PM PDT 24 65509981 ps
T1442 /workspace/coverage/cover_reg_top/20.i2c_intr_test.3662990478 Apr 28 12:46:20 PM PDT 24 Apr 28 12:46:22 PM PDT 24 19940020 ps
T1443 /workspace/coverage/cover_reg_top/45.i2c_intr_test.2443291159 Apr 28 12:46:24 PM PDT 24 Apr 28 12:46:25 PM PDT 24 20733250 ps
T1444 /workspace/coverage/cover_reg_top/41.i2c_intr_test.3197588778 Apr 28 12:46:17 PM PDT 24 Apr 28 12:46:18 PM PDT 24 24768610 ps
T168 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1049065403 Apr 28 12:46:03 PM PDT 24 Apr 28 12:46:06 PM PDT 24 247170768 ps
T1445 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.173642287 Apr 28 12:46:07 PM PDT 24 Apr 28 12:46:09 PM PDT 24 48322153 ps
T142 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.164150622 Apr 28 12:46:06 PM PDT 24 Apr 28 12:46:09 PM PDT 24 314261759 ps
T1446 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1535860961 Apr 28 12:45:59 PM PDT 24 Apr 28 12:46:01 PM PDT 24 32050352 ps
T1447 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3547593730 Apr 28 12:46:02 PM PDT 24 Apr 28 12:46:05 PM PDT 24 102327969 ps
T1448 /workspace/coverage/cover_reg_top/40.i2c_intr_test.338670267 Apr 28 12:46:15 PM PDT 24 Apr 28 12:46:17 PM PDT 24 51541916 ps
T1449 /workspace/coverage/cover_reg_top/46.i2c_intr_test.1051711764 Apr 28 12:46:18 PM PDT 24 Apr 28 12:46:19 PM PDT 24 18671562 ps
T1450 /workspace/coverage/cover_reg_top/1.i2c_intr_test.233466764 Apr 28 12:46:05 PM PDT 24 Apr 28 12:46:07 PM PDT 24 17501095 ps
T1451 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1169370595 Apr 28 12:46:25 PM PDT 24 Apr 28 12:46:27 PM PDT 24 62852335 ps
T1452 /workspace/coverage/cover_reg_top/25.i2c_intr_test.3367290830 Apr 28 12:46:17 PM PDT 24 Apr 28 12:46:18 PM PDT 24 70346428 ps
T1453 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.4148385019 Apr 28 12:46:04 PM PDT 24 Apr 28 12:46:06 PM PDT 24 66866645 ps
T1454 /workspace/coverage/cover_reg_top/26.i2c_intr_test.2288739656 Apr 28 12:46:28 PM PDT 24 Apr 28 12:46:30 PM PDT 24 19279627 ps
T1455 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1293425231 Apr 28 12:46:03 PM PDT 24 Apr 28 12:46:06 PM PDT 24 60491507 ps
T1456 /workspace/coverage/cover_reg_top/38.i2c_intr_test.909558559 Apr 28 12:46:14 PM PDT 24 Apr 28 12:46:15 PM PDT 24 44872538 ps
T1457 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.28457065 Apr 28 12:46:14 PM PDT 24 Apr 28 12:46:16 PM PDT 24 185173700 ps
T1458 /workspace/coverage/cover_reg_top/6.i2c_intr_test.3148513301 Apr 28 12:46:01 PM PDT 24 Apr 28 12:46:03 PM PDT 24 43941006 ps
T136 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.4118920687 Apr 28 12:46:05 PM PDT 24 Apr 28 12:46:07 PM PDT 24 83807716 ps

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.2220363333
Short name T6
Test name
Test status
Simulation time 10437946717 ps
CPU time 13.93 seconds
Started Apr 28 12:59:09 PM PDT 24
Finished Apr 28 12:59:26 PM PDT 24
Peak memory 259880 kb
Host smart-6e6cccf9-005c-471c-a4b6-5983a9565bc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220363333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.2220363333
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.3608412366
Short name T44
Test name
Test status
Simulation time 29442767790 ps
CPU time 930.27 seconds
Started Apr 28 01:02:11 PM PDT 24
Finished Apr 28 01:17:42 PM PDT 24
Peak memory 1928104 kb
Host smart-29895381-caaa-44f2-9698-9a1b7485d8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608412366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.3608412366
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.1286255237
Short name T15
Test name
Test status
Simulation time 9605141617 ps
CPU time 11.32 seconds
Started Apr 28 12:58:53 PM PDT 24
Finished Apr 28 12:59:05 PM PDT 24
Peak memory 204216 kb
Host smart-012f1ca2-f4a6-4ff5-a104-52fad1dad125
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286255237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.1286255237
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.963146415
Short name T41
Test name
Test status
Simulation time 32826219758 ps
CPU time 632.6 seconds
Started Apr 28 01:01:49 PM PDT 24
Finished Apr 28 01:12:23 PM PDT 24
Peak memory 1061520 kb
Host smart-caea7239-417a-462f-b2a6-fd345e07064f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963146415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.963146415
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.4006422724
Short name T131
Test name
Test status
Simulation time 291302199 ps
CPU time 2.7 seconds
Started Apr 28 12:46:07 PM PDT 24
Finished Apr 28 12:46:11 PM PDT 24
Peak memory 204232 kb
Host smart-61f08e23-567a-4cb0-9418-f6135c58afa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006422724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.4006422724
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/default/49.i2c_host_override.4257613945
Short name T35
Test name
Test status
Simulation time 30509624 ps
CPU time 0.68 seconds
Started Apr 28 01:03:50 PM PDT 24
Finished Apr 28 01:03:51 PM PDT 24
Peak memory 203852 kb
Host smart-8782d62a-db7a-487c-9738-fa15ead77762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257613945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.4257613945
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1606347056
Short name T128
Test name
Test status
Simulation time 129536840 ps
CPU time 2.33 seconds
Started Apr 28 12:45:55 PM PDT 24
Finished Apr 28 12:45:58 PM PDT 24
Peak memory 204076 kb
Host smart-dd3a93aa-c82f-4153-be52-ca2d21c720ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606347056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.1606347056
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/49.i2c_target_stress_all.3834364412
Short name T31
Test name
Test status
Simulation time 41521973518 ps
CPU time 348.67 seconds
Started Apr 28 01:03:58 PM PDT 24
Finished Apr 28 01:09:47 PM PDT 24
Peak memory 2452088 kb
Host smart-2d022e76-a180-4a8c-b130-a9810521aa93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834364412 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.i2c_target_stress_all.3834364412
Directory /workspace/49.i2c_target_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.805897808
Short name T70
Test name
Test status
Simulation time 2167067400 ps
CPU time 6.61 seconds
Started Apr 28 12:58:46 PM PDT 24
Finished Apr 28 12:58:53 PM PDT 24
Peak memory 204240 kb
Host smart-7b8bfc8e-a7a4-4405-8b70-c9a4fc033c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805897808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.805897808
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.695970585
Short name T5
Test name
Test status
Simulation time 2874993418 ps
CPU time 3.36 seconds
Started Apr 28 01:00:49 PM PDT 24
Finished Apr 28 01:00:53 PM PDT 24
Peak memory 212504 kb
Host smart-d5b364de-2629-451e-9d73-4dead4ed7f0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695970585 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.695970585
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_alert_test.2760906617
Short name T395
Test name
Test status
Simulation time 18435166 ps
CPU time 0.61 seconds
Started Apr 28 12:59:45 PM PDT 24
Finished Apr 28 12:59:47 PM PDT 24
Peak memory 203904 kb
Host smart-166eca96-2099-4905-9070-9891309ffd53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760906617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.2760906617
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.127293974
Short name T156
Test name
Test status
Simulation time 80758044 ps
CPU time 0.83 seconds
Started Apr 28 12:46:03 PM PDT 24
Finished Apr 28 12:46:06 PM PDT 24
Peak memory 204040 kb
Host smart-a05959fd-a26d-4def-aef0-7cc11afbc2ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127293974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.127293974
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.566812362
Short name T149
Test name
Test status
Simulation time 61318003290 ps
CPU time 1829.62 seconds
Started Apr 28 12:58:45 PM PDT 24
Finished Apr 28 01:29:15 PM PDT 24
Peak memory 2317572 kb
Host smart-45a0436a-b5b0-4312-8fed-47333a6ae5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566812362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.566812362
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2450531839
Short name T204
Test name
Test status
Simulation time 111182126 ps
CPU time 0.92 seconds
Started Apr 28 01:00:44 PM PDT 24
Finished Apr 28 01:00:46 PM PDT 24
Peak memory 204004 kb
Host smart-75111432-897f-4783-ac4c-5eb970a461a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450531839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.2450531839
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.341415394
Short name T115
Test name
Test status
Simulation time 215081056 ps
CPU time 0.97 seconds
Started Apr 28 12:58:58 PM PDT 24
Finished Apr 28 12:58:59 PM PDT 24
Peak memory 222472 kb
Host smart-b4d71978-44c0-48e6-a258-4a571b9a6b6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341415394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.341415394
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.797588997
Short name T201
Test name
Test status
Simulation time 6433973098 ps
CPU time 181.09 seconds
Started Apr 28 01:00:12 PM PDT 24
Finished Apr 28 01:03:14 PM PDT 24
Peak memory 1330640 kb
Host smart-1a2445f4-b8dc-4cbd-8862-c9467ddb7d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797588997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.797588997
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.1312797030
Short name T237
Test name
Test status
Simulation time 422569666 ps
CPU time 2.21 seconds
Started Apr 28 12:59:49 PM PDT 24
Finished Apr 28 12:59:52 PM PDT 24
Peak memory 204076 kb
Host smart-50477288-3b4a-4f7d-8bca-4a05de4119b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312797030 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.1312797030
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.612969409
Short name T85
Test name
Test status
Simulation time 10474315924 ps
CPU time 12.64 seconds
Started Apr 28 12:59:07 PM PDT 24
Finished Apr 28 12:59:21 PM PDT 24
Peak memory 260172 kb
Host smart-2ba3d95b-f37f-48b9-be21-62867ef62bb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612969409 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_acq.612969409
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.4153747329
Short name T45
Test name
Test status
Simulation time 7792940630 ps
CPU time 388.58 seconds
Started Apr 28 01:01:29 PM PDT 24
Finished Apr 28 01:07:58 PM PDT 24
Peak memory 1903396 kb
Host smart-db2d1d2b-f87f-4dcb-b2e7-95800cbe5f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153747329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.4153747329
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.3281099843
Short name T62
Test name
Test status
Simulation time 2318470577 ps
CPU time 22.42 seconds
Started Apr 28 01:00:32 PM PDT 24
Finished Apr 28 01:00:56 PM PDT 24
Peak memory 316600 kb
Host smart-0d1bafb6-9540-4def-90fb-1e98a47581d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281099843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.3281099843
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_target_unexp_stop.2485557420
Short name T17
Test name
Test status
Simulation time 950765188 ps
CPU time 5.14 seconds
Started Apr 28 01:00:39 PM PDT 24
Finished Apr 28 01:00:45 PM PDT 24
Peak memory 212344 kb
Host smart-63f4c29f-b04c-49eb-85b8-5343a7359c78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485557420 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.i2c_target_unexp_stop.2485557420
Directory /workspace/19.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.1002986531
Short name T180
Test name
Test status
Simulation time 18071050311 ps
CPU time 113.74 seconds
Started Apr 28 01:01:54 PM PDT 24
Finished Apr 28 01:03:48 PM PDT 24
Peak memory 1298640 kb
Host smart-373c8124-a2d5-4728-8e81-c31ec0aaeb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002986531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.1002986531
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.1801750152
Short name T227
Test name
Test status
Simulation time 57163696877 ps
CPU time 512.73 seconds
Started Apr 28 12:59:37 PM PDT 24
Finished Apr 28 01:08:10 PM PDT 24
Peak memory 1985624 kb
Host smart-e9c46fc4-ad45-44a7-b2c1-26e672e7a1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801750152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.1801750152
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.2399275974
Short name T667
Test name
Test status
Simulation time 643789733 ps
CPU time 6.2 seconds
Started Apr 28 01:00:21 PM PDT 24
Finished Apr 28 01:00:27 PM PDT 24
Peak memory 204032 kb
Host smart-9db40814-d30a-47d8-b243-2db5da4393f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399275974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.2399275974
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.937854654
Short name T27
Test name
Test status
Simulation time 694752103 ps
CPU time 1.92 seconds
Started Apr 28 01:00:55 PM PDT 24
Finished Apr 28 01:00:57 PM PDT 24
Peak memory 204108 kb
Host smart-2e2fc54b-1426-4d8e-a56f-92fb8d75b6e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937854654 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.937854654
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.164150622
Short name T142
Test name
Test status
Simulation time 314261759 ps
CPU time 1.49 seconds
Started Apr 28 12:46:06 PM PDT 24
Finished Apr 28 12:46:09 PM PDT 24
Peak memory 204268 kb
Host smart-7b017087-aec4-4d2f-a617-9216ea2a520f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164150622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.164150622
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.984292957
Short name T72
Test name
Test status
Simulation time 64060891983 ps
CPU time 534.2 seconds
Started Apr 28 01:00:10 PM PDT 24
Finished Apr 28 01:09:04 PM PDT 24
Peak memory 2141140 kb
Host smart-41b32e71-e035-4b9e-ae05-e0887ea281ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984292957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.984292957
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.4256772349
Short name T51
Test name
Test status
Simulation time 10089534787 ps
CPU time 74.73 seconds
Started Apr 28 01:01:15 PM PDT 24
Finished Apr 28 01:02:30 PM PDT 24
Peak memory 554488 kb
Host smart-cafc5d9e-9368-4011-9ffd-58ac6933a87d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256772349 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.4256772349
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.2790022000
Short name T48
Test name
Test status
Simulation time 4943048381 ps
CPU time 83.91 seconds
Started Apr 28 12:58:51 PM PDT 24
Finished Apr 28 01:00:16 PM PDT 24
Peak memory 472552 kb
Host smart-bf15ca9e-2a56-4587-b724-05510673941d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790022000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.2790022000
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.2572508774
Short name T223
Test name
Test status
Simulation time 10238360840 ps
CPU time 29.36 seconds
Started Apr 28 12:59:45 PM PDT 24
Finished Apr 28 01:00:15 PM PDT 24
Peak memory 319156 kb
Host smart-cb1905df-5f57-4abd-8332-74055ba880cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572508774 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.2572508774
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_host_perf.4176147901
Short name T818
Test name
Test status
Simulation time 2322130983 ps
CPU time 6.88 seconds
Started Apr 28 01:00:00 PM PDT 24
Finished Apr 28 01:00:07 PM PDT 24
Peak memory 220568 kb
Host smart-83b6ed5d-0820-4b20-9d98-4b998d6b8f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176147901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.4176147901
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.3762181340
Short name T250
Test name
Test status
Simulation time 634569927 ps
CPU time 28.52 seconds
Started Apr 28 01:02:28 PM PDT 24
Finished Apr 28 01:02:57 PM PDT 24
Peak memory 212240 kb
Host smart-930a6907-f250-440f-8cc1-0e3af19b4e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762181340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.3762181340
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_host_override.3056766456
Short name T209
Test name
Test status
Simulation time 52227177 ps
CPU time 0.6 seconds
Started Apr 28 01:03:19 PM PDT 24
Finished Apr 28 01:03:21 PM PDT 24
Peak memory 203848 kb
Host smart-33a733d1-3090-4fdc-83bb-dfbb2859cdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056766456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.3056766456
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.2113285551
Short name T73
Test name
Test status
Simulation time 12766382459 ps
CPU time 51.22 seconds
Started Apr 28 01:00:47 PM PDT 24
Finished Apr 28 01:01:39 PM PDT 24
Peak memory 344996 kb
Host smart-e89be84d-b40e-4ddb-93b0-58e83ccbc57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113285551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.2113285551
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2314143021
Short name T143
Test name
Test status
Simulation time 151424818 ps
CPU time 1.41 seconds
Started Apr 28 12:45:59 PM PDT 24
Finished Apr 28 12:46:01 PM PDT 24
Peak memory 204104 kb
Host smart-9e8e85d1-9ba3-4b64-a44f-7c090cc39d12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314143021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2314143021
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2775357434
Short name T193
Test name
Test status
Simulation time 35583682 ps
CPU time 0.71 seconds
Started Apr 28 12:46:04 PM PDT 24
Finished Apr 28 12:46:06 PM PDT 24
Peak memory 203988 kb
Host smart-7d818553-1a55-47c9-9e6c-ac178b9c0820
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775357434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2775357434
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.3468702443
Short name T669
Test name
Test status
Simulation time 380201608 ps
CPU time 2.4 seconds
Started Apr 28 12:58:49 PM PDT 24
Finished Apr 28 12:58:51 PM PDT 24
Peak memory 204064 kb
Host smart-3bc3f6fc-dd10-450c-a08e-5b062b5319bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468702443 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.3468702443
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.710984865
Short name T905
Test name
Test status
Simulation time 2628784828 ps
CPU time 17.59 seconds
Started Apr 28 12:59:45 PM PDT 24
Finished Apr 28 01:00:03 PM PDT 24
Peak memory 222880 kb
Host smart-6a966670-9871-4d0e-ad31-bf39fdb77d16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710984865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c
_target_stress_rd.710984865
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.4118920687
Short name T136
Test name
Test status
Simulation time 83807716 ps
CPU time 1.49 seconds
Started Apr 28 12:46:05 PM PDT 24
Finished Apr 28 12:46:07 PM PDT 24
Peak memory 204172 kb
Host smart-bf09cac6-bd67-4d61-989f-2582e40d8c63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118920687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.4118920687
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.3569570996
Short name T52
Test name
Test status
Simulation time 10056138913 ps
CPU time 14.12 seconds
Started Apr 28 01:01:21 PM PDT 24
Finished Apr 28 01:01:35 PM PDT 24
Peak memory 297812 kb
Host smart-6734cc3b-dcc0-4f0a-9f7a-08a36a73171d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569570996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.3569570996
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2078129949
Short name T1393
Test name
Test status
Simulation time 39348701 ps
CPU time 1.72 seconds
Started Apr 28 12:46:06 PM PDT 24
Finished Apr 28 12:46:09 PM PDT 24
Peak memory 212484 kb
Host smart-d8621e4d-1d78-4cbc-9b22-29e92298f1da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078129949 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2078129949
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1549935377
Short name T145
Test name
Test status
Simulation time 297515612 ps
CPU time 1.61 seconds
Started Apr 28 12:46:06 PM PDT 24
Finished Apr 28 12:46:09 PM PDT 24
Peak memory 204096 kb
Host smart-f40ac54a-bcfe-4e43-9b15-2297679babd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549935377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1549935377
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3758515486
Short name T83
Test name
Test status
Simulation time 359801207 ps
CPU time 2.11 seconds
Started Apr 28 12:46:05 PM PDT 24
Finished Apr 28 12:46:08 PM PDT 24
Peak memory 204240 kb
Host smart-8bd18a1e-ffc1-48a9-91a0-2075bb838ffd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758515486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3758515486
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.567449078
Short name T139
Test name
Test status
Simulation time 150900173 ps
CPU time 2.48 seconds
Started Apr 28 12:46:10 PM PDT 24
Finished Apr 28 12:46:13 PM PDT 24
Peak memory 204244 kb
Host smart-0a367c99-d35f-4676-a265-1983dc88a135
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567449078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.567449078
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.566030581
Short name T167
Test name
Test status
Simulation time 234942193 ps
CPU time 1.34 seconds
Started Apr 28 12:45:52 PM PDT 24
Finished Apr 28 12:45:54 PM PDT 24
Peak memory 204204 kb
Host smart-209b437b-da92-459b-83c0-19375c248610
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566030581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.566030581
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.790082687
Short name T1414
Test name
Test status
Simulation time 181395973 ps
CPU time 2.89 seconds
Started Apr 28 12:45:52 PM PDT 24
Finished Apr 28 12:45:56 PM PDT 24
Peak memory 204076 kb
Host smart-b38f82a7-ce9b-4fff-9ac7-ef04c4ea81a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790082687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.790082687
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.4046078104
Short name T1410
Test name
Test status
Simulation time 64028003 ps
CPU time 0.71 seconds
Started Apr 28 12:45:51 PM PDT 24
Finished Apr 28 12:45:53 PM PDT 24
Peak memory 203980 kb
Host smart-6d3b96d5-b881-4edd-ab54-32169446b742
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046078104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.4046078104
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1538422681
Short name T1408
Test name
Test status
Simulation time 26336465 ps
CPU time 0.75 seconds
Started Apr 28 12:45:51 PM PDT 24
Finished Apr 28 12:45:53 PM PDT 24
Peak memory 204088 kb
Host smart-790867da-3c7b-4d8d-ae9a-16e342e667e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538422681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1538422681
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.1502987249
Short name T1385
Test name
Test status
Simulation time 17369524 ps
CPU time 0.69 seconds
Started Apr 28 12:45:52 PM PDT 24
Finished Apr 28 12:45:54 PM PDT 24
Peak memory 203820 kb
Host smart-77f868a5-b9bd-43e1-8e05-e950e363e310
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502987249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1502987249
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.523363755
Short name T1436
Test name
Test status
Simulation time 95847396 ps
CPU time 2.53 seconds
Started Apr 28 12:45:50 PM PDT 24
Finished Apr 28 12:45:54 PM PDT 24
Peak memory 204276 kb
Host smart-4875469c-c0ca-44bb-98c8-d92edc569c16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523363755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.523363755
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.1535860961
Short name T1446
Test name
Test status
Simulation time 32050352 ps
CPU time 1.27 seconds
Started Apr 28 12:45:59 PM PDT 24
Finished Apr 28 12:46:01 PM PDT 24
Peak memory 204156 kb
Host smart-d63dd439-6862-4b70-a761-1636150e68ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535860961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1535860961
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1354755269
Short name T1437
Test name
Test status
Simulation time 441652875 ps
CPU time 2.94 seconds
Started Apr 28 12:45:51 PM PDT 24
Finished Apr 28 12:45:55 PM PDT 24
Peak memory 204212 kb
Host smart-435921c4-4d62-4153-824b-d809531a32af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354755269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.1354755269
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.4277496330
Short name T1394
Test name
Test status
Simulation time 19676613 ps
CPU time 0.69 seconds
Started Apr 28 12:45:50 PM PDT 24
Finished Apr 28 12:45:52 PM PDT 24
Peak memory 203896 kb
Host smart-5770db8a-3e55-46c3-b01c-2656a245b2a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277496330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.4277496330
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.1500660631
Short name T1404
Test name
Test status
Simulation time 44699858 ps
CPU time 1.23 seconds
Started Apr 28 12:45:53 PM PDT 24
Finished Apr 28 12:45:56 PM PDT 24
Peak memory 204232 kb
Host smart-76cc48fd-2e69-472d-bb5e-c4ff25826e1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500660631 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.1500660631
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1555968703
Short name T161
Test name
Test status
Simulation time 84513638 ps
CPU time 0.73 seconds
Started Apr 28 12:45:51 PM PDT 24
Finished Apr 28 12:45:53 PM PDT 24
Peak memory 203976 kb
Host smart-2d1a263e-65b6-4416-913f-aeae3c445662
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555968703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.1555968703
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.233466764
Short name T1450
Test name
Test status
Simulation time 17501095 ps
CPU time 0.69 seconds
Started Apr 28 12:46:05 PM PDT 24
Finished Apr 28 12:46:07 PM PDT 24
Peak memory 203964 kb
Host smart-43cab18c-f1d9-498b-aa7c-ad744caff402
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233466764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.233466764
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1569460296
Short name T217
Test name
Test status
Simulation time 311134945 ps
CPU time 2.59 seconds
Started Apr 28 12:46:03 PM PDT 24
Finished Apr 28 12:46:07 PM PDT 24
Peak memory 204212 kb
Host smart-1a463c20-d2f0-4154-9f01-f07ec4804066
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569460296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.1569460296
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3686543646
Short name T82
Test name
Test status
Simulation time 87591458 ps
CPU time 0.85 seconds
Started Apr 28 12:46:04 PM PDT 24
Finished Apr 28 12:46:06 PM PDT 24
Peak memory 203940 kb
Host smart-2b255e86-481f-41ba-a62b-af2e9a19341d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686543646 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3686543646
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1292398944
Short name T160
Test name
Test status
Simulation time 46669507 ps
CPU time 0.76 seconds
Started Apr 28 12:46:06 PM PDT 24
Finished Apr 28 12:46:08 PM PDT 24
Peak memory 203972 kb
Host smart-611c9e88-1cfa-41d7-a703-8d06cff5439b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292398944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1292398944
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.420420597
Short name T1368
Test name
Test status
Simulation time 46224878 ps
CPU time 0.64 seconds
Started Apr 28 12:46:08 PM PDT 24
Finished Apr 28 12:46:10 PM PDT 24
Peak memory 203976 kb
Host smart-c63233d6-631a-45ad-acc2-531fc6580c95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420420597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.420420597
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.4148385019
Short name T1453
Test name
Test status
Simulation time 66866645 ps
CPU time 0.84 seconds
Started Apr 28 12:46:04 PM PDT 24
Finished Apr 28 12:46:06 PM PDT 24
Peak memory 203952 kb
Host smart-b4836a2f-87e4-4921-a9a4-fa5d506d72ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148385019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.4148385019
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.3547078456
Short name T1405
Test name
Test status
Simulation time 35451183 ps
CPU time 1.75 seconds
Started Apr 28 12:46:01 PM PDT 24
Finished Apr 28 12:46:04 PM PDT 24
Peak memory 204168 kb
Host smart-7ef8ae23-b31c-4c10-98d6-f573b5a74a18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547078456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.3547078456
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3407903747
Short name T141
Test name
Test status
Simulation time 178967257 ps
CPU time 1.39 seconds
Started Apr 28 12:46:09 PM PDT 24
Finished Apr 28 12:46:11 PM PDT 24
Peak memory 204224 kb
Host smart-7356968d-31ec-46b7-9620-12eba9cb80c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407903747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3407903747
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.34509735
Short name T1392
Test name
Test status
Simulation time 28136382 ps
CPU time 0.74 seconds
Started Apr 28 12:46:06 PM PDT 24
Finished Apr 28 12:46:08 PM PDT 24
Peak memory 203852 kb
Host smart-6de18b70-9913-4840-a347-67ede61ecbef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34509735 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.34509735
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3907879325
Short name T170
Test name
Test status
Simulation time 103578447 ps
CPU time 0.8 seconds
Started Apr 28 12:46:07 PM PDT 24
Finished Apr 28 12:46:09 PM PDT 24
Peak memory 203928 kb
Host smart-41b13cf5-c5b7-418e-b5ae-a40d70bfc889
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907879325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3907879325
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.1905821402
Short name T1417
Test name
Test status
Simulation time 15110574 ps
CPU time 0.67 seconds
Started Apr 28 12:46:09 PM PDT 24
Finished Apr 28 12:46:11 PM PDT 24
Peak memory 203960 kb
Host smart-1b91e571-0975-4a72-9be1-7a7a074b1779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905821402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1905821402
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3981993915
Short name T1420
Test name
Test status
Simulation time 200246515 ps
CPU time 1.85 seconds
Started Apr 28 12:46:02 PM PDT 24
Finished Apr 28 12:46:05 PM PDT 24
Peak memory 204316 kb
Host smart-a361f714-7bca-441f-b77b-afd306368fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981993915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3981993915
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2610337736
Short name T163
Test name
Test status
Simulation time 56200984 ps
CPU time 0.74 seconds
Started Apr 28 12:46:04 PM PDT 24
Finished Apr 28 12:46:06 PM PDT 24
Peak memory 203952 kb
Host smart-363e2e9b-7f7b-48a6-a561-7098056e6763
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610337736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2610337736
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.132537440
Short name T1411
Test name
Test status
Simulation time 26964565 ps
CPU time 0.66 seconds
Started Apr 28 12:46:21 PM PDT 24
Finished Apr 28 12:46:25 PM PDT 24
Peak memory 203936 kb
Host smart-24884060-2738-4b1b-b008-608e5e156b7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132537440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.132537440
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3002947502
Short name T1401
Test name
Test status
Simulation time 58258482 ps
CPU time 0.9 seconds
Started Apr 28 12:46:02 PM PDT 24
Finished Apr 28 12:46:04 PM PDT 24
Peak memory 204072 kb
Host smart-f4867b4b-ee1c-4576-8ebc-cf56d4032615
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002947502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.3002947502
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2548569231
Short name T1389
Test name
Test status
Simulation time 47885474 ps
CPU time 1.24 seconds
Started Apr 28 12:46:08 PM PDT 24
Finished Apr 28 12:46:11 PM PDT 24
Peak memory 204200 kb
Host smart-e69f986c-f2a3-47b2-8d26-e9b4ab916260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548569231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2548569231
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.491373913
Short name T232
Test name
Test status
Simulation time 170910664 ps
CPU time 1.4 seconds
Started Apr 28 12:46:08 PM PDT 24
Finished Apr 28 12:46:11 PM PDT 24
Peak memory 204228 kb
Host smart-4a186768-b449-42aa-a28c-d63a9e17768e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491373913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.491373913
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2330287367
Short name T153
Test name
Test status
Simulation time 45820005 ps
CPU time 0.86 seconds
Started Apr 28 12:46:10 PM PDT 24
Finished Apr 28 12:46:12 PM PDT 24
Peak memory 203956 kb
Host smart-3698786a-ca3c-4d1b-94b3-3cc4846aca24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330287367 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2330287367
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.2252737189
Short name T1428
Test name
Test status
Simulation time 40074053 ps
CPU time 0.71 seconds
Started Apr 28 12:46:07 PM PDT 24
Finished Apr 28 12:46:09 PM PDT 24
Peak memory 203964 kb
Host smart-383f71ba-89f1-4bbe-89a1-c7dc968b4d61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252737189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2252737189
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.277900638
Short name T1430
Test name
Test status
Simulation time 53497072 ps
CPU time 2.53 seconds
Started Apr 28 12:46:08 PM PDT 24
Finished Apr 28 12:46:12 PM PDT 24
Peak memory 204196 kb
Host smart-068b4157-73ce-489c-84bd-bcd0813a3a60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277900638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.277900638
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4087775254
Short name T135
Test name
Test status
Simulation time 281082847 ps
CPU time 1.4 seconds
Started Apr 28 12:46:09 PM PDT 24
Finished Apr 28 12:46:12 PM PDT 24
Peak memory 204216 kb
Host smart-9a0f5f4a-a00c-4e29-8688-da44f17b5524
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087775254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.4087775254
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.904171036
Short name T192
Test name
Test status
Simulation time 85698640 ps
CPU time 0.83 seconds
Started Apr 28 12:46:16 PM PDT 24
Finished Apr 28 12:46:18 PM PDT 24
Peak memory 203996 kb
Host smart-3519ece1-1ad9-4b59-aae8-599c59e5feb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904171036 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.904171036
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.65766197
Short name T164
Test name
Test status
Simulation time 18588702 ps
CPU time 0.77 seconds
Started Apr 28 12:46:07 PM PDT 24
Finished Apr 28 12:46:09 PM PDT 24
Peak memory 204032 kb
Host smart-3eb3ff90-9a0e-43ef-8550-bd2dc08e024f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65766197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.65766197
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3135039857
Short name T1438
Test name
Test status
Simulation time 18080198 ps
CPU time 0.72 seconds
Started Apr 28 12:46:06 PM PDT 24
Finished Apr 28 12:46:08 PM PDT 24
Peak memory 203964 kb
Host smart-5a7f1549-8f92-4962-a096-5e8d0a36eebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135039857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3135039857
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.1169370595
Short name T1451
Test name
Test status
Simulation time 62852335 ps
CPU time 0.79 seconds
Started Apr 28 12:46:25 PM PDT 24
Finished Apr 28 12:46:27 PM PDT 24
Peak memory 204124 kb
Host smart-6d1a534c-6aa9-44a2-b053-2a4c846d400d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169370595 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.1169370595
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.4239755457
Short name T1440
Test name
Test status
Simulation time 59790089 ps
CPU time 0.72 seconds
Started Apr 28 12:46:11 PM PDT 24
Finished Apr 28 12:46:12 PM PDT 24
Peak memory 203952 kb
Host smart-197d4c4e-abba-4753-a141-d24090a5949f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239755457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.4239755457
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.3594442871
Short name T1378
Test name
Test status
Simulation time 16486225 ps
CPU time 0.66 seconds
Started Apr 28 12:46:08 PM PDT 24
Finished Apr 28 12:46:10 PM PDT 24
Peak memory 203964 kb
Host smart-da94a4b1-5fbc-42cb-8e23-b962c265103c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594442871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3594442871
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.2798094610
Short name T1431
Test name
Test status
Simulation time 167138885 ps
CPU time 1.25 seconds
Started Apr 28 12:46:04 PM PDT 24
Finished Apr 28 12:46:06 PM PDT 24
Peak memory 204236 kb
Host smart-f43c69e1-fa96-44dc-9223-e11eb10e2d8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798094610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.2798094610
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3764975981
Short name T151
Test name
Test status
Simulation time 36328402 ps
CPU time 0.81 seconds
Started Apr 28 12:46:15 PM PDT 24
Finished Apr 28 12:46:17 PM PDT 24
Peak memory 204116 kb
Host smart-fdbb31c6-8bc9-4952-a56e-988ba2f8ecb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764975981 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.3764975981
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1074868279
Short name T165
Test name
Test status
Simulation time 26657922 ps
CPU time 0.8 seconds
Started Apr 28 12:46:25 PM PDT 24
Finished Apr 28 12:46:28 PM PDT 24
Peak memory 204052 kb
Host smart-3b1a738f-325b-4f7b-8b02-f3aa5ee88aea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074868279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1074868279
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.877402657
Short name T1371
Test name
Test status
Simulation time 15758686 ps
CPU time 0.67 seconds
Started Apr 28 12:46:14 PM PDT 24
Finished Apr 28 12:46:15 PM PDT 24
Peak memory 203876 kb
Host smart-e9ae8ad0-6171-4076-aa98-e8a9c0398bba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877402657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.877402657
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.28457065
Short name T1457
Test name
Test status
Simulation time 185173700 ps
CPU time 1.15 seconds
Started Apr 28 12:46:14 PM PDT 24
Finished Apr 28 12:46:16 PM PDT 24
Peak memory 204064 kb
Host smart-4911f8ec-f3b8-4912-942f-e7ca910e4f5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28457065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_out
standing.28457065
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.710871630
Short name T176
Test name
Test status
Simulation time 46026536 ps
CPU time 1.05 seconds
Started Apr 28 12:46:09 PM PDT 24
Finished Apr 28 12:46:11 PM PDT 24
Peak memory 204016 kb
Host smart-4ec2cf24-de0f-4f9d-a649-1641a6e22031
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710871630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.710871630
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.535159317
Short name T216
Test name
Test status
Simulation time 26484538 ps
CPU time 0.81 seconds
Started Apr 28 12:46:20 PM PDT 24
Finished Apr 28 12:46:26 PM PDT 24
Peak memory 204136 kb
Host smart-50c1cad2-967e-4934-bda2-d2876d0b91a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535159317 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.535159317
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1614794489
Short name T155
Test name
Test status
Simulation time 18217981 ps
CPU time 0.76 seconds
Started Apr 28 12:46:09 PM PDT 24
Finished Apr 28 12:46:11 PM PDT 24
Peak memory 204076 kb
Host smart-8fe56769-4eb6-4973-8e7b-552cbebf7586
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614794489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1614794489
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.1923118590
Short name T1400
Test name
Test status
Simulation time 23868381 ps
CPU time 0.68 seconds
Started Apr 28 12:46:10 PM PDT 24
Finished Apr 28 12:46:12 PM PDT 24
Peak memory 203884 kb
Host smart-2b3552e7-2061-41dd-8c22-7cce5650daf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923118590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1923118590
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.859145319
Short name T172
Test name
Test status
Simulation time 56697733 ps
CPU time 1.1 seconds
Started Apr 28 12:46:13 PM PDT 24
Finished Apr 28 12:46:15 PM PDT 24
Peak memory 204212 kb
Host smart-5e57017a-d6b8-454a-aa73-7c3b60c8ce6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859145319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_ou
tstanding.859145319
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3259677851
Short name T1418
Test name
Test status
Simulation time 388651136 ps
CPU time 2.15 seconds
Started Apr 28 12:46:08 PM PDT 24
Finished Apr 28 12:46:12 PM PDT 24
Peak memory 204172 kb
Host smart-27950e2c-848a-4249-a6ac-4f8b49f9907d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259677851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3259677851
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.2597591619
Short name T152
Test name
Test status
Simulation time 23081213 ps
CPU time 0.97 seconds
Started Apr 28 12:46:13 PM PDT 24
Finished Apr 28 12:46:15 PM PDT 24
Peak memory 204136 kb
Host smart-e785461a-e247-4cdb-89ed-703d92969e5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597591619 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.2597591619
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2078882997
Short name T148
Test name
Test status
Simulation time 18786966 ps
CPU time 0.67 seconds
Started Apr 28 12:46:10 PM PDT 24
Finished Apr 28 12:46:12 PM PDT 24
Peak memory 203940 kb
Host smart-1d7c0e6a-4396-49d9-8ad2-55d02fb4578d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078882997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2078882997
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.2972753113
Short name T1377
Test name
Test status
Simulation time 149807357 ps
CPU time 0.63 seconds
Started Apr 28 12:46:08 PM PDT 24
Finished Apr 28 12:46:10 PM PDT 24
Peak memory 203140 kb
Host smart-facfff29-8717-4619-8559-6427c03b5377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972753113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2972753113
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2935449842
Short name T1398
Test name
Test status
Simulation time 43809674 ps
CPU time 2.17 seconds
Started Apr 28 12:46:10 PM PDT 24
Finished Apr 28 12:46:13 PM PDT 24
Peak memory 204256 kb
Host smart-782ab3f0-85b8-470f-a7a0-6bcdf09c4e62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935449842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2935449842
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3033779921
Short name T1402
Test name
Test status
Simulation time 84162037 ps
CPU time 1.15 seconds
Started Apr 28 12:46:15 PM PDT 24
Finished Apr 28 12:46:17 PM PDT 24
Peak memory 204228 kb
Host smart-aed8a26a-5ea5-4b5e-abc5-d9339a7f5af1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033779921 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3033779921
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1685490027
Short name T158
Test name
Test status
Simulation time 134031224 ps
CPU time 0.78 seconds
Started Apr 28 12:46:13 PM PDT 24
Finished Apr 28 12:46:15 PM PDT 24
Peak memory 204044 kb
Host smart-11bca506-3d54-4bbb-b8f2-cfb9309ebfda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685490027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.1685490027
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.3373743970
Short name T1376
Test name
Test status
Simulation time 19193584 ps
CPU time 0.68 seconds
Started Apr 28 12:46:15 PM PDT 24
Finished Apr 28 12:46:16 PM PDT 24
Peak memory 203840 kb
Host smart-1f7ee5a1-c085-4adc-9e54-f984c4aa2dda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373743970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.3373743970
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.4185754851
Short name T1441
Test name
Test status
Simulation time 65509981 ps
CPU time 1.24 seconds
Started Apr 28 12:46:14 PM PDT 24
Finished Apr 28 12:46:16 PM PDT 24
Peak memory 204280 kb
Host smart-94374533-8748-46e6-87e7-4a31fa955d24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185754851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.4185754851
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1468771753
Short name T127
Test name
Test status
Simulation time 258650473 ps
CPU time 1.7 seconds
Started Apr 28 12:46:19 PM PDT 24
Finished Apr 28 12:46:21 PM PDT 24
Peak memory 204124 kb
Host smart-2aa1b89d-279b-4d9c-b08f-8f308060d615
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468771753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.1468771753
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2484853170
Short name T129
Test name
Test status
Simulation time 95541638 ps
CPU time 2.09 seconds
Started Apr 28 12:46:24 PM PDT 24
Finished Apr 28 12:46:26 PM PDT 24
Peak memory 204204 kb
Host smart-7ab0b2b0-d244-4833-a352-a1d1f962bde1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484853170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2484853170
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1049065403
Short name T168
Test name
Test status
Simulation time 247170768 ps
CPU time 1.38 seconds
Started Apr 28 12:46:03 PM PDT 24
Finished Apr 28 12:46:06 PM PDT 24
Peak memory 204260 kb
Host smart-42b61b37-c812-4507-abb1-b11874bfa6de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049065403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.1049065403
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3267658570
Short name T130
Test name
Test status
Simulation time 34192962 ps
CPU time 0.95 seconds
Started Apr 28 12:45:59 PM PDT 24
Finished Apr 28 12:46:01 PM PDT 24
Peak memory 204044 kb
Host smart-2dd7e7d4-f0ff-4884-8746-bd315b6ac214
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267658570 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3267658570
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3212252678
Short name T166
Test name
Test status
Simulation time 21797187 ps
CPU time 0.73 seconds
Started Apr 28 12:45:50 PM PDT 24
Finished Apr 28 12:45:52 PM PDT 24
Peak memory 203876 kb
Host smart-bc17ff14-42c5-4ef2-956d-5a172444b867
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212252678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3212252678
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.4061391767
Short name T1426
Test name
Test status
Simulation time 19592313 ps
CPU time 0.69 seconds
Started Apr 28 12:45:58 PM PDT 24
Finished Apr 28 12:45:59 PM PDT 24
Peak memory 203948 kb
Host smart-f40842c8-6f32-4877-b529-3ca318622f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061391767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.4061391767
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3506881408
Short name T171
Test name
Test status
Simulation time 279182045 ps
CPU time 1.25 seconds
Started Apr 28 12:46:09 PM PDT 24
Finished Apr 28 12:46:12 PM PDT 24
Peak memory 204160 kb
Host smart-b8de22bb-3b37-42b7-8409-51c9c95fa9fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506881408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.3506881408
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1236332616
Short name T140
Test name
Test status
Simulation time 282845999 ps
CPU time 1.67 seconds
Started Apr 28 12:45:53 PM PDT 24
Finished Apr 28 12:45:56 PM PDT 24
Peak memory 204164 kb
Host smart-a42f3cc6-3343-440d-aa9b-e2852cb7cb14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236332616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1236332616
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.3662990478
Short name T1442
Test name
Test status
Simulation time 19940020 ps
CPU time 0.68 seconds
Started Apr 28 12:46:20 PM PDT 24
Finished Apr 28 12:46:22 PM PDT 24
Peak memory 204008 kb
Host smart-a533128b-beef-45bd-9f60-0c6e7ce03fa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662990478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3662990478
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.837094177
Short name T1439
Test name
Test status
Simulation time 84369093 ps
CPU time 0.71 seconds
Started Apr 28 12:46:15 PM PDT 24
Finished Apr 28 12:46:16 PM PDT 24
Peak memory 203976 kb
Host smart-55cc9cfb-f3fa-4bdf-aa02-549ecba657a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837094177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.837094177
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.1555415401
Short name T1409
Test name
Test status
Simulation time 33498795 ps
CPU time 0.71 seconds
Started Apr 28 12:46:21 PM PDT 24
Finished Apr 28 12:46:24 PM PDT 24
Peak memory 203952 kb
Host smart-351353e9-746f-4e99-848c-cfa0d3d6862f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555415401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1555415401
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.3806961324
Short name T1416
Test name
Test status
Simulation time 141482384 ps
CPU time 0.66 seconds
Started Apr 28 12:46:20 PM PDT 24
Finished Apr 28 12:46:22 PM PDT 24
Peak memory 203820 kb
Host smart-2d368cae-13da-4873-a022-2c8b9079b7b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806961324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3806961324
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.4049422745
Short name T1367
Test name
Test status
Simulation time 215564837 ps
CPU time 0.75 seconds
Started Apr 28 12:46:12 PM PDT 24
Finished Apr 28 12:46:13 PM PDT 24
Peak memory 203952 kb
Host smart-922e8f3b-1e7e-4e37-98c0-da97484c01e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049422745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.4049422745
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3367290830
Short name T1452
Test name
Test status
Simulation time 70346428 ps
CPU time 0.74 seconds
Started Apr 28 12:46:17 PM PDT 24
Finished Apr 28 12:46:18 PM PDT 24
Peak memory 204004 kb
Host smart-7ec603d1-9675-40d4-8df8-34b408c38838
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367290830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3367290830
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.2288739656
Short name T1454
Test name
Test status
Simulation time 19279627 ps
CPU time 0.68 seconds
Started Apr 28 12:46:28 PM PDT 24
Finished Apr 28 12:46:30 PM PDT 24
Peak memory 203980 kb
Host smart-f4866f85-b040-4b40-b717-dcd5f832b099
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288739656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2288739656
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.2209184265
Short name T1391
Test name
Test status
Simulation time 28427273 ps
CPU time 0.64 seconds
Started Apr 28 12:46:17 PM PDT 24
Finished Apr 28 12:46:18 PM PDT 24
Peak memory 203920 kb
Host smart-4f3d55c2-3b52-4b06-866e-7ffd276b7219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209184265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2209184265
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.420955724
Short name T1370
Test name
Test status
Simulation time 18199179 ps
CPU time 0.69 seconds
Started Apr 28 12:46:15 PM PDT 24
Finished Apr 28 12:46:16 PM PDT 24
Peak memory 203852 kb
Host smart-e6412361-af37-49dd-b38b-a1bde93ae0f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420955724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.420955724
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.2579830013
Short name T1387
Test name
Test status
Simulation time 16648568 ps
CPU time 0.6 seconds
Started Apr 28 12:46:22 PM PDT 24
Finished Apr 28 12:46:23 PM PDT 24
Peak memory 203904 kb
Host smart-f5292ec5-ab9d-4f12-af52-8ffb51758307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579830013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2579830013
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.3573769844
Short name T1381
Test name
Test status
Simulation time 31722718 ps
CPU time 1.3 seconds
Started Apr 28 12:45:53 PM PDT 24
Finished Apr 28 12:45:56 PM PDT 24
Peak memory 204164 kb
Host smart-48c09bab-1342-4361-8d0b-e1928f81bdb5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573769844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3573769844
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.2269664353
Short name T157
Test name
Test status
Simulation time 141966722 ps
CPU time 2.92 seconds
Started Apr 28 12:46:02 PM PDT 24
Finished Apr 28 12:46:07 PM PDT 24
Peak memory 204136 kb
Host smart-c035429d-193c-426f-8e44-b2ff2420e254
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269664353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.2269664353
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1987291245
Short name T175
Test name
Test status
Simulation time 22711761 ps
CPU time 0.73 seconds
Started Apr 28 12:46:02 PM PDT 24
Finished Apr 28 12:46:04 PM PDT 24
Peak memory 203964 kb
Host smart-43ae7919-4320-4b00-b82a-2b9658a3a65e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987291245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1987291245
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1316648051
Short name T144
Test name
Test status
Simulation time 118286795 ps
CPU time 0.93 seconds
Started Apr 28 12:45:53 PM PDT 24
Finished Apr 28 12:45:55 PM PDT 24
Peak memory 204144 kb
Host smart-939ab860-67f8-4145-97c2-093496106737
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316648051 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.1316648051
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.396315058
Short name T1433
Test name
Test status
Simulation time 16810149 ps
CPU time 0.72 seconds
Started Apr 28 12:45:53 PM PDT 24
Finished Apr 28 12:45:55 PM PDT 24
Peak memory 203964 kb
Host smart-b57d58dd-8982-4af2-a0fc-ac5552262f48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396315058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.396315058
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.1346284213
Short name T1386
Test name
Test status
Simulation time 19832541 ps
CPU time 0.79 seconds
Started Apr 28 12:45:59 PM PDT 24
Finished Apr 28 12:46:01 PM PDT 24
Peak memory 203872 kb
Host smart-465f053f-a95f-4864-8942-00542169e133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346284213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.1346284213
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.837621735
Short name T173
Test name
Test status
Simulation time 32268935 ps
CPU time 0.83 seconds
Started Apr 28 12:46:02 PM PDT 24
Finished Apr 28 12:46:04 PM PDT 24
Peak memory 204060 kb
Host smart-72d8c832-50e5-47b9-957d-8e3c0bfa3ecc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837621735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_out
standing.837621735
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3795834619
Short name T1407
Test name
Test status
Simulation time 122658409 ps
CPU time 1.82 seconds
Started Apr 28 12:45:59 PM PDT 24
Finished Apr 28 12:46:02 PM PDT 24
Peak memory 204252 kb
Host smart-24cec665-8880-49fa-aeb7-435c68aa87fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795834619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.3795834619
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.1594083674
Short name T1374
Test name
Test status
Simulation time 18408253 ps
CPU time 0.67 seconds
Started Apr 28 12:46:23 PM PDT 24
Finished Apr 28 12:46:29 PM PDT 24
Peak memory 203908 kb
Host smart-9c640d91-c438-4e26-b53c-f2d8b8393663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594083674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1594083674
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.757066830
Short name T1403
Test name
Test status
Simulation time 58573649 ps
CPU time 0.69 seconds
Started Apr 28 12:46:23 PM PDT 24
Finished Apr 28 12:46:24 PM PDT 24
Peak memory 203880 kb
Host smart-be58bf4a-2e40-47bf-92cd-5a27e0e6a6a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757066830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.757066830
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.1304486443
Short name T1390
Test name
Test status
Simulation time 41256281 ps
CPU time 0.63 seconds
Started Apr 28 12:46:21 PM PDT 24
Finished Apr 28 12:46:22 PM PDT 24
Peak memory 203980 kb
Host smart-d2b8f5ce-44dd-412a-a848-afe91bbaa6d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304486443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.1304486443
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.452238575
Short name T1397
Test name
Test status
Simulation time 27491744 ps
CPU time 0.66 seconds
Started Apr 28 12:46:15 PM PDT 24
Finished Apr 28 12:46:16 PM PDT 24
Peak memory 203836 kb
Host smart-c5705b7e-073d-4b96-bb40-f757a1be6b38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452238575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.452238575
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.3556496226
Short name T1369
Test name
Test status
Simulation time 16691270 ps
CPU time 0.67 seconds
Started Apr 28 12:46:13 PM PDT 24
Finished Apr 28 12:46:14 PM PDT 24
Peak memory 203972 kb
Host smart-0d275c9c-4f84-4f87-b868-4e86f05108f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556496226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3556496226
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.3328880833
Short name T1399
Test name
Test status
Simulation time 43948433 ps
CPU time 0.67 seconds
Started Apr 28 12:46:22 PM PDT 24
Finished Apr 28 12:46:24 PM PDT 24
Peak memory 203896 kb
Host smart-a10c8eb5-101f-4212-a5ea-f647031d3acb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328880833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3328880833
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1347910872
Short name T1380
Test name
Test status
Simulation time 19385473 ps
CPU time 0.69 seconds
Started Apr 28 12:46:12 PM PDT 24
Finished Apr 28 12:46:14 PM PDT 24
Peak memory 203960 kb
Host smart-de9b46d5-d0c9-4879-9707-8b24db5a5c79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347910872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1347910872
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.4028202801
Short name T1427
Test name
Test status
Simulation time 21064024 ps
CPU time 0.69 seconds
Started Apr 28 12:46:16 PM PDT 24
Finished Apr 28 12:46:17 PM PDT 24
Peak memory 203852 kb
Host smart-ea957292-167e-4732-9d6a-acf363f805d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028202801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.4028202801
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.909558559
Short name T1456
Test name
Test status
Simulation time 44872538 ps
CPU time 0.63 seconds
Started Apr 28 12:46:14 PM PDT 24
Finished Apr 28 12:46:15 PM PDT 24
Peak memory 203852 kb
Host smart-ac3054af-897c-45c2-a0ac-41e1ba97bb62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909558559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.909558559
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1643209030
Short name T1425
Test name
Test status
Simulation time 16105733 ps
CPU time 0.63 seconds
Started Apr 28 12:46:21 PM PDT 24
Finished Apr 28 12:46:24 PM PDT 24
Peak memory 203820 kb
Host smart-79b9658b-dc8a-4cc2-818a-68c381fba6ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643209030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1643209030
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1293425231
Short name T1455
Test name
Test status
Simulation time 60491507 ps
CPU time 1.22 seconds
Started Apr 28 12:46:03 PM PDT 24
Finished Apr 28 12:46:06 PM PDT 24
Peak memory 203952 kb
Host smart-25ca4526-37a8-496b-9a35-5582e1c1279b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293425231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1293425231
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1859336096
Short name T159
Test name
Test status
Simulation time 325225776 ps
CPU time 3.3 seconds
Started Apr 28 12:45:59 PM PDT 24
Finished Apr 28 12:46:03 PM PDT 24
Peak memory 204164 kb
Host smart-62ca462e-59f4-4436-9fba-a6e603c5728a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859336096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1859336096
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.269236839
Short name T1383
Test name
Test status
Simulation time 23400153 ps
CPU time 0.75 seconds
Started Apr 28 12:45:56 PM PDT 24
Finished Apr 28 12:45:57 PM PDT 24
Peak memory 204060 kb
Host smart-ad973dbd-b07c-4bb4-90c3-c497e443f3e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269236839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.269236839
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.100443206
Short name T1423
Test name
Test status
Simulation time 188055114 ps
CPU time 0.77 seconds
Started Apr 28 12:46:02 PM PDT 24
Finished Apr 28 12:46:04 PM PDT 24
Peak memory 204128 kb
Host smart-4538d1ed-52f2-4a05-afd9-c2458df49c2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100443206 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.100443206
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.2699387435
Short name T1422
Test name
Test status
Simulation time 59654652 ps
CPU time 0.69 seconds
Started Apr 28 12:46:11 PM PDT 24
Finished Apr 28 12:46:13 PM PDT 24
Peak memory 204000 kb
Host smart-fef33583-f2b4-4382-89e3-2c0e7b4d8179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699387435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.2699387435
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2377171022
Short name T1432
Test name
Test status
Simulation time 27823983 ps
CPU time 1.08 seconds
Started Apr 28 12:45:52 PM PDT 24
Finished Apr 28 12:45:55 PM PDT 24
Peak memory 204116 kb
Host smart-bbf2ef38-d2ae-46fe-b3f7-8c94bd4d0dd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377171022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.2377171022
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3588039077
Short name T133
Test name
Test status
Simulation time 148660341 ps
CPU time 1.76 seconds
Started Apr 28 12:45:56 PM PDT 24
Finished Apr 28 12:45:58 PM PDT 24
Peak memory 204272 kb
Host smart-f8851a3d-c916-4a83-a58d-4db7d0591a69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588039077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3588039077
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.2664880000
Short name T146
Test name
Test status
Simulation time 255159948 ps
CPU time 1.48 seconds
Started Apr 28 12:46:06 PM PDT 24
Finished Apr 28 12:46:09 PM PDT 24
Peak memory 204184 kb
Host smart-39ade576-0d42-48ae-b56a-d94daeda7094
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664880000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.2664880000
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.338670267
Short name T1448
Test name
Test status
Simulation time 51541916 ps
CPU time 0.67 seconds
Started Apr 28 12:46:15 PM PDT 24
Finished Apr 28 12:46:17 PM PDT 24
Peak memory 203932 kb
Host smart-18dde676-9b52-42ab-9a32-5d23d01adcf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338670267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.338670267
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.3197588778
Short name T1444
Test name
Test status
Simulation time 24768610 ps
CPU time 0.69 seconds
Started Apr 28 12:46:17 PM PDT 24
Finished Apr 28 12:46:18 PM PDT 24
Peak memory 203984 kb
Host smart-60dde6d9-a339-4dec-8773-ce0702b14f82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197588778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3197588778
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.4213662371
Short name T1415
Test name
Test status
Simulation time 21500682 ps
CPU time 0.67 seconds
Started Apr 28 12:46:23 PM PDT 24
Finished Apr 28 12:46:25 PM PDT 24
Peak memory 204004 kb
Host smart-b0925774-f55e-4527-a104-706accbf70a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213662371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.4213662371
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.217590442
Short name T1382
Test name
Test status
Simulation time 19401295 ps
CPU time 0.68 seconds
Started Apr 28 12:46:18 PM PDT 24
Finished Apr 28 12:46:19 PM PDT 24
Peak memory 203928 kb
Host smart-e98f1d61-3ee1-4bea-86ad-dcad67266471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217590442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.217590442
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.147567321
Short name T1413
Test name
Test status
Simulation time 38585212 ps
CPU time 0.66 seconds
Started Apr 28 12:46:18 PM PDT 24
Finished Apr 28 12:46:19 PM PDT 24
Peak memory 203872 kb
Host smart-6b74fbf8-41f1-464f-8ecf-69e5f7d69e8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147567321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.147567321
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2443291159
Short name T1443
Test name
Test status
Simulation time 20733250 ps
CPU time 0.69 seconds
Started Apr 28 12:46:24 PM PDT 24
Finished Apr 28 12:46:25 PM PDT 24
Peak memory 203900 kb
Host smart-bcc4ea59-8dce-461e-a7ec-7bb7e6c3f892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443291159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2443291159
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.1051711764
Short name T1449
Test name
Test status
Simulation time 18671562 ps
CPU time 0.69 seconds
Started Apr 28 12:46:18 PM PDT 24
Finished Apr 28 12:46:19 PM PDT 24
Peak memory 203984 kb
Host smart-d064caae-7cd4-4911-bb40-f08a57c8e028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051711764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1051711764
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.2887916181
Short name T1379
Test name
Test status
Simulation time 17154189 ps
CPU time 0.7 seconds
Started Apr 28 12:46:24 PM PDT 24
Finished Apr 28 12:46:26 PM PDT 24
Peak memory 204008 kb
Host smart-8c5bf03c-37d7-4eb1-8b15-e45b1b11245a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887916181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2887916181
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.2907766994
Short name T1375
Test name
Test status
Simulation time 19331570 ps
CPU time 0.68 seconds
Started Apr 28 12:46:19 PM PDT 24
Finished Apr 28 12:46:20 PM PDT 24
Peak memory 203960 kb
Host smart-4dbb5e14-4b1c-402b-9cfd-ad1d3fc2bf4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907766994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2907766994
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.1103447137
Short name T1419
Test name
Test status
Simulation time 18533495 ps
CPU time 0.68 seconds
Started Apr 28 12:46:18 PM PDT 24
Finished Apr 28 12:46:19 PM PDT 24
Peak memory 203940 kb
Host smart-3efde332-aa91-49d0-8389-24b533f8a0e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103447137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1103447137
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1852481574
Short name T1384
Test name
Test status
Simulation time 35142420 ps
CPU time 1 seconds
Started Apr 28 12:45:57 PM PDT 24
Finished Apr 28 12:45:59 PM PDT 24
Peak memory 204088 kb
Host smart-e824d460-bd4c-4b2b-893c-59b3b7c9c714
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852481574 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.1852481574
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.304555080
Short name T1435
Test name
Test status
Simulation time 40025308 ps
CPU time 0.67 seconds
Started Apr 28 12:46:04 PM PDT 24
Finished Apr 28 12:46:06 PM PDT 24
Peak memory 203880 kb
Host smart-42110ce7-6a35-4974-91db-030f0a865860
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304555080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.304555080
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.3534396625
Short name T1372
Test name
Test status
Simulation time 20683619 ps
CPU time 0.68 seconds
Started Apr 28 12:45:53 PM PDT 24
Finished Apr 28 12:45:55 PM PDT 24
Peak memory 203928 kb
Host smart-04efb1d4-f23b-4ec6-b9a9-21793d5e227d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534396625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3534396625
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.638981055
Short name T112
Test name
Test status
Simulation time 275492313 ps
CPU time 1.75 seconds
Started Apr 28 12:45:53 PM PDT 24
Finished Apr 28 12:45:57 PM PDT 24
Peak memory 204064 kb
Host smart-8ae421e8-ccd5-48ea-9e3c-2a92d9ef1e2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638981055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.638981055
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.705608015
Short name T1421
Test name
Test status
Simulation time 98020774 ps
CPU time 0.9 seconds
Started Apr 28 12:46:02 PM PDT 24
Finished Apr 28 12:46:04 PM PDT 24
Peak memory 204012 kb
Host smart-c7cbe82f-70c8-4cee-ba12-c006b5773032
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705608015 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.705608015
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.309863094
Short name T1429
Test name
Test status
Simulation time 25559522 ps
CPU time 0.73 seconds
Started Apr 28 12:46:04 PM PDT 24
Finished Apr 28 12:46:06 PM PDT 24
Peak memory 203780 kb
Host smart-16874957-9067-415d-a489-cb24302af9de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309863094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.309863094
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.3148513301
Short name T1458
Test name
Test status
Simulation time 43941006 ps
CPU time 0.66 seconds
Started Apr 28 12:46:01 PM PDT 24
Finished Apr 28 12:46:03 PM PDT 24
Peak memory 203956 kb
Host smart-0b99b640-d9de-48ae-ab7a-e2644078242a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148513301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.3148513301
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.399375129
Short name T169
Test name
Test status
Simulation time 91411138 ps
CPU time 1.11 seconds
Started Apr 28 12:46:02 PM PDT 24
Finished Apr 28 12:46:05 PM PDT 24
Peak memory 204144 kb
Host smart-c28c7ee9-6e75-4832-905c-2e9b07131751
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399375129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_out
standing.399375129
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2226995191
Short name T132
Test name
Test status
Simulation time 737546169 ps
CPU time 3.01 seconds
Started Apr 28 12:46:02 PM PDT 24
Finished Apr 28 12:46:07 PM PDT 24
Peak memory 204104 kb
Host smart-91d73000-0321-4158-bbdd-ae58ad9ee0ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226995191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2226995191
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.243442643
Short name T138
Test name
Test status
Simulation time 82273764 ps
CPU time 1.48 seconds
Started Apr 28 12:46:05 PM PDT 24
Finished Apr 28 12:46:07 PM PDT 24
Peak memory 204188 kb
Host smart-2520da2b-2fa3-4944-9640-1fe79702dd89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243442643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.243442643
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3562779008
Short name T1396
Test name
Test status
Simulation time 31632276 ps
CPU time 1.42 seconds
Started Apr 28 12:46:01 PM PDT 24
Finished Apr 28 12:46:03 PM PDT 24
Peak memory 212512 kb
Host smart-e6a491cd-3e25-44ab-b51e-190f561b1c6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562779008 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.3562779008
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2821570241
Short name T162
Test name
Test status
Simulation time 20176721 ps
CPU time 0.68 seconds
Started Apr 28 12:46:06 PM PDT 24
Finished Apr 28 12:46:08 PM PDT 24
Peak memory 203972 kb
Host smart-105978e7-0d4a-442c-8c84-6033903e5e56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821570241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2821570241
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.740158627
Short name T1373
Test name
Test status
Simulation time 26044894 ps
CPU time 0.66 seconds
Started Apr 28 12:45:59 PM PDT 24
Finished Apr 28 12:46:01 PM PDT 24
Peak memory 203984 kb
Host smart-5b28190d-9860-4d0c-bfbb-18e4d77ca46b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740158627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.740158627
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.2257148287
Short name T1412
Test name
Test status
Simulation time 115505980 ps
CPU time 2.22 seconds
Started Apr 28 12:46:09 PM PDT 24
Finished Apr 28 12:46:13 PM PDT 24
Peak memory 204240 kb
Host smart-af0c8344-593b-4766-b388-15f12ac34e6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257148287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.2257148287
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3688428204
Short name T147
Test name
Test status
Simulation time 160724652 ps
CPU time 2.13 seconds
Started Apr 28 12:46:01 PM PDT 24
Finished Apr 28 12:46:04 PM PDT 24
Peak memory 204212 kb
Host smart-ea3c8d4a-9d3d-4d86-8967-fa418120abc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688428204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.3688428204
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.173642287
Short name T1445
Test name
Test status
Simulation time 48322153 ps
CPU time 0.77 seconds
Started Apr 28 12:46:07 PM PDT 24
Finished Apr 28 12:46:09 PM PDT 24
Peak memory 203952 kb
Host smart-6121b198-23cf-4e2b-9797-55905abd88ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173642287 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.173642287
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3966893584
Short name T1434
Test name
Test status
Simulation time 24608172 ps
CPU time 0.77 seconds
Started Apr 28 12:46:02 PM PDT 24
Finished Apr 28 12:46:03 PM PDT 24
Peak memory 203948 kb
Host smart-6f0f2276-5b24-49b7-8e83-dcb3571f28c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966893584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.3966893584
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.2566442700
Short name T1388
Test name
Test status
Simulation time 15829994 ps
CPU time 0.71 seconds
Started Apr 28 12:46:02 PM PDT 24
Finished Apr 28 12:46:04 PM PDT 24
Peak memory 203884 kb
Host smart-77d1b87b-1be4-4f7f-916b-9b3e1decf54a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566442700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.2566442700
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.854033472
Short name T1424
Test name
Test status
Simulation time 253302850 ps
CPU time 1.22 seconds
Started Apr 28 12:46:19 PM PDT 24
Finished Apr 28 12:46:21 PM PDT 24
Peak memory 204228 kb
Host smart-c5bc1046-1d15-428e-9d2b-804ee8b358c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854033472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_out
standing.854033472
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3547593730
Short name T1447
Test name
Test status
Simulation time 102327969 ps
CPU time 1.47 seconds
Started Apr 28 12:46:02 PM PDT 24
Finished Apr 28 12:46:05 PM PDT 24
Peak memory 204136 kb
Host smart-92828a75-b092-426b-af68-818d8bac2f25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547593730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3547593730
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2498283386
Short name T1395
Test name
Test status
Simulation time 64079331 ps
CPU time 1.39 seconds
Started Apr 28 12:46:12 PM PDT 24
Finished Apr 28 12:46:14 PM PDT 24
Peak memory 212392 kb
Host smart-87000e3d-00a2-4dfa-b1e6-d033f0ef2968
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498283386 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2498283386
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1673896331
Short name T81
Test name
Test status
Simulation time 23960289 ps
CPU time 0.66 seconds
Started Apr 28 12:46:01 PM PDT 24
Finished Apr 28 12:46:02 PM PDT 24
Peak memory 203932 kb
Host smart-abc4d169-9ca6-4766-abe9-1e7b9ded237a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673896331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1673896331
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.2437066383
Short name T1406
Test name
Test status
Simulation time 17198564 ps
CPU time 0.7 seconds
Started Apr 28 12:46:01 PM PDT 24
Finished Apr 28 12:46:02 PM PDT 24
Peak memory 203876 kb
Host smart-b8e67ff7-14c5-4856-b6b7-7a6bf4cdb6a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437066383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2437066383
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2910804849
Short name T134
Test name
Test status
Simulation time 191556105 ps
CPU time 2.2 seconds
Started Apr 28 12:46:05 PM PDT 24
Finished Apr 28 12:46:09 PM PDT 24
Peak memory 204216 kb
Host smart-4535276c-8311-464c-bd35-54cce75f0caf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910804849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2910804849
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.1393711301
Short name T137
Test name
Test status
Simulation time 272925549 ps
CPU time 2.38 seconds
Started Apr 28 12:46:01 PM PDT 24
Finished Apr 28 12:46:05 PM PDT 24
Peak memory 204160 kb
Host smart-c2c701f9-91f3-4b4d-8745-4e52daddd9b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393711301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.1393711301
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.875768386
Short name T867
Test name
Test status
Simulation time 17848792 ps
CPU time 0.6 seconds
Started Apr 28 12:58:49 PM PDT 24
Finished Apr 28 12:58:50 PM PDT 24
Peak memory 203720 kb
Host smart-e0b76811-3e28-43a4-9fb3-bd3de31c8f86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875768386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.875768386
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.1467691574
Short name T363
Test name
Test status
Simulation time 65566852 ps
CPU time 1.21 seconds
Started Apr 28 12:58:44 PM PDT 24
Finished Apr 28 12:58:46 PM PDT 24
Peak memory 212380 kb
Host smart-5cc3908c-e2eb-4b15-a2b6-4d9bf6c2b3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467691574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.1467691574
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.1821502216
Short name T508
Test name
Test status
Simulation time 6369438072 ps
CPU time 21.11 seconds
Started Apr 28 12:58:47 PM PDT 24
Finished Apr 28 12:59:09 PM PDT 24
Peak memory 292404 kb
Host smart-7e1ba4cd-d9d3-4985-ba2a-7369466a9501
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821502216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.1821502216
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.71709683
Short name T534
Test name
Test status
Simulation time 8864746005 ps
CPU time 192.63 seconds
Started Apr 28 12:58:38 PM PDT 24
Finished Apr 28 01:01:51 PM PDT 24
Peak memory 820940 kb
Host smart-659a65bb-e59c-44a1-9d23-44b7b58ad410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71709683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.71709683
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.1841919892
Short name T535
Test name
Test status
Simulation time 1782422957 ps
CPU time 128.11 seconds
Started Apr 28 12:58:43 PM PDT 24
Finished Apr 28 01:00:52 PM PDT 24
Peak memory 615104 kb
Host smart-c32107e9-418c-4e5c-affb-82727dd3d8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841919892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.1841919892
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.2163565059
Short name T878
Test name
Test status
Simulation time 803341438 ps
CPU time 0.96 seconds
Started Apr 28 12:58:51 PM PDT 24
Finished Apr 28 12:58:52 PM PDT 24
Peak memory 204096 kb
Host smart-1ab12791-6068-4172-a8c3-e3f03243b536
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163565059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.2163565059
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.2687886550
Short name T1284
Test name
Test status
Simulation time 129647842 ps
CPU time 2.9 seconds
Started Apr 28 12:58:49 PM PDT 24
Finished Apr 28 12:58:52 PM PDT 24
Peak memory 203936 kb
Host smart-7f132693-d20f-4ce0-aa18-ca4eba3078ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687886550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
2687886550
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.2847703858
Short name T1067
Test name
Test status
Simulation time 9546585442 ps
CPU time 104.25 seconds
Started Apr 28 12:58:43 PM PDT 24
Finished Apr 28 01:00:28 PM PDT 24
Peak memory 1248120 kb
Host smart-16ff08eb-d5c3-40b4-8548-f6d36a00c533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847703858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.2847703858
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.2071890398
Short name T1366
Test name
Test status
Simulation time 1223892059 ps
CPU time 6.7 seconds
Started Apr 28 12:58:41 PM PDT 24
Finished Apr 28 12:58:49 PM PDT 24
Peak memory 203976 kb
Host smart-91c15d08-34d1-4be4-9130-669bd1e6c2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071890398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.2071890398
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.3587133907
Short name T882
Test name
Test status
Simulation time 1795729432 ps
CPU time 34.9 seconds
Started Apr 28 12:59:10 PM PDT 24
Finished Apr 28 12:59:49 PM PDT 24
Peak memory 374416 kb
Host smart-ffef1985-b6e9-4175-82bf-415bda0685a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587133907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.3587133907
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.2708397775
Short name T532
Test name
Test status
Simulation time 153984600 ps
CPU time 0.71 seconds
Started Apr 28 12:58:42 PM PDT 24
Finished Apr 28 12:58:44 PM PDT 24
Peak memory 203856 kb
Host smart-0a8f794b-dc38-48df-b3d6-d47060f928ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708397775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.2708397775
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.3579780648
Short name T79
Test name
Test status
Simulation time 13547095955 ps
CPU time 262.54 seconds
Started Apr 28 12:58:45 PM PDT 24
Finished Apr 28 01:03:08 PM PDT 24
Peak memory 204252 kb
Host smart-d7f78a20-cfae-49f9-ae0a-1fe53cc194b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579780648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3579780648
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.219001291
Short name T590
Test name
Test status
Simulation time 20704760695 ps
CPU time 63.88 seconds
Started Apr 28 12:58:43 PM PDT 24
Finished Apr 28 12:59:48 PM PDT 24
Peak memory 350540 kb
Host smart-050c8bac-257a-4bf0-910b-95d9ff25b3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219001291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.219001291
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.2702826437
Short name T834
Test name
Test status
Simulation time 2172817592 ps
CPU time 15.79 seconds
Started Apr 28 12:58:46 PM PDT 24
Finished Apr 28 12:59:02 PM PDT 24
Peak memory 220160 kb
Host smart-a1b7aaba-bd00-4a20-a303-6e6d3fb5f2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702826437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.2702826437
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.1444410947
Short name T428
Test name
Test status
Simulation time 6153094231 ps
CPU time 2.85 seconds
Started Apr 28 12:58:44 PM PDT 24
Finished Apr 28 12:58:48 PM PDT 24
Peak memory 204276 kb
Host smart-d24ed75f-d9f4-4189-a9b6-9ca80dd4df0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444410947 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1444410947
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2249736686
Short name T517
Test name
Test status
Simulation time 10070759691 ps
CPU time 32.97 seconds
Started Apr 28 12:58:50 PM PDT 24
Finished Apr 28 12:59:24 PM PDT 24
Peak memory 364120 kb
Host smart-13c7ca01-27c2-4e32-945b-ad32be0c188c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249736686 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2249736686
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.700100392
Short name T1246
Test name
Test status
Simulation time 10048399901 ps
CPU time 80.99 seconds
Started Apr 28 12:58:42 PM PDT 24
Finished Apr 28 01:00:04 PM PDT 24
Peak memory 497448 kb
Host smart-8635e9b5-144f-4035-809c-5f14075c6c48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700100392 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_fifo_reset_tx.700100392
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.1078110541
Short name T23
Test name
Test status
Simulation time 11656233014 ps
CPU time 9.12 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 12:59:14 PM PDT 24
Peak memory 204420 kb
Host smart-504d0d5d-d732-49df-b275-243b1fef2e89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078110541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.1078110541
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.266358534
Short name T320
Test name
Test status
Simulation time 734715543 ps
CPU time 3.99 seconds
Started Apr 28 12:58:48 PM PDT 24
Finished Apr 28 12:58:52 PM PDT 24
Peak memory 206340 kb
Host smart-8175159a-5955-4d8d-ab89-0bf178045aeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266358534 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_intr_smoke.266358534
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.902110138
Short name T242
Test name
Test status
Simulation time 17595075440 ps
CPU time 39.78 seconds
Started Apr 28 12:58:43 PM PDT 24
Finished Apr 28 12:59:24 PM PDT 24
Peak memory 713328 kb
Host smart-05da104d-268d-41ab-85b0-96fa356b71d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902110138 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.902110138
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.4141024556
Short name T105
Test name
Test status
Simulation time 9221444988 ps
CPU time 21.95 seconds
Started Apr 28 12:58:44 PM PDT 24
Finished Apr 28 12:59:07 PM PDT 24
Peak memory 204064 kb
Host smart-ed2b477d-77b7-4738-9b59-50f817913bab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141024556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.4141024556
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.3287534711
Short name T936
Test name
Test status
Simulation time 655693722 ps
CPU time 26.61 seconds
Started Apr 28 12:58:51 PM PDT 24
Finished Apr 28 12:59:18 PM PDT 24
Peak memory 204224 kb
Host smart-c2af6a77-ff0c-4b2c-8d35-0b336bbc95c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287534711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.3287534711
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.984305000
Short name T825
Test name
Test status
Simulation time 41804168635 ps
CPU time 660.44 seconds
Started Apr 28 12:58:51 PM PDT 24
Finished Apr 28 01:09:52 PM PDT 24
Peak memory 5360064 kb
Host smart-d68a50d5-f8f5-476f-ae6b-b2c0c36ae744
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984305000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_wr.984305000
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3809351143
Short name T547
Test name
Test status
Simulation time 9238715566 ps
CPU time 268.06 seconds
Started Apr 28 12:58:52 PM PDT 24
Finished Apr 28 01:03:21 PM PDT 24
Peak memory 2366940 kb
Host smart-fb3af40d-152b-471b-946e-9edcc85e3d51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809351143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3809351143
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.1060749214
Short name T1178
Test name
Test status
Simulation time 5650808915 ps
CPU time 6.51 seconds
Started Apr 28 12:58:43 PM PDT 24
Finished Apr 28 12:58:50 PM PDT 24
Peak memory 212460 kb
Host smart-f8134a65-6454-46ff-8c1b-14f70cfd3379
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060749214 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.1060749214
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.418605741
Short name T403
Test name
Test status
Simulation time 31640302 ps
CPU time 0.65 seconds
Started Apr 28 12:58:56 PM PDT 24
Finished Apr 28 12:58:57 PM PDT 24
Peak memory 203912 kb
Host smart-744ba5bc-9c2b-4f72-8c91-be0247676239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418605741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.418605741
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.89485283
Short name T1301
Test name
Test status
Simulation time 419444499 ps
CPU time 1.25 seconds
Started Apr 28 12:58:55 PM PDT 24
Finished Apr 28 12:58:58 PM PDT 24
Peak memory 212320 kb
Host smart-049835d6-0c9e-4132-aee7-9078654d8de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89485283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.89485283
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.2333253155
Short name T1143
Test name
Test status
Simulation time 253445999 ps
CPU time 4.5 seconds
Started Apr 28 12:58:51 PM PDT 24
Finished Apr 28 12:58:56 PM PDT 24
Peak memory 251696 kb
Host smart-a3175111-4715-4b85-aaf7-810cb71610ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333253155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.2333253155
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.2203459236
Short name T737
Test name
Test status
Simulation time 14403154349 ps
CPU time 47.21 seconds
Started Apr 28 12:58:53 PM PDT 24
Finished Apr 28 12:59:41 PM PDT 24
Peak memory 582460 kb
Host smart-eb0d9afa-c174-42bb-96e7-19ba013cb0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203459236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2203459236
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.3214025266
Short name T1239
Test name
Test status
Simulation time 221837768 ps
CPU time 0.9 seconds
Started Apr 28 12:58:54 PM PDT 24
Finished Apr 28 12:58:55 PM PDT 24
Peak memory 203864 kb
Host smart-7cda68bd-0e18-41b6-a244-1dbbec0420f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214025266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.3214025266
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.3801349359
Short name T841
Test name
Test status
Simulation time 138992747 ps
CPU time 2.8 seconds
Started Apr 28 12:59:10 PM PDT 24
Finished Apr 28 12:59:17 PM PDT 24
Peak memory 204080 kb
Host smart-1a4e42ab-aee6-4e69-8a56-c78c48062953
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801349359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
3801349359
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.1731893006
Short name T178
Test name
Test status
Simulation time 2799518295 ps
CPU time 58.71 seconds
Started Apr 28 12:58:53 PM PDT 24
Finished Apr 28 12:59:52 PM PDT 24
Peak memory 855836 kb
Host smart-c049981d-13b6-4b00-893a-9915014fc9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731893006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.1731893006
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.1773784608
Short name T312
Test name
Test status
Simulation time 8829477365 ps
CPU time 117.47 seconds
Started Apr 28 12:58:56 PM PDT 24
Finished Apr 28 01:00:55 PM PDT 24
Peak memory 499876 kb
Host smart-38c09683-82df-44ed-a268-f4bcd61ee609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773784608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.1773784608
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.2049998476
Short name T36
Test name
Test status
Simulation time 79264279 ps
CPU time 0.65 seconds
Started Apr 28 12:58:52 PM PDT 24
Finished Apr 28 12:58:53 PM PDT 24
Peak memory 203788 kb
Host smart-4d68e666-d92a-40b8-88bd-7cb1ee76cf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049998476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2049998476
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.2734050778
Short name T222
Test name
Test status
Simulation time 13616167737 ps
CPU time 43.98 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 12:59:48 PM PDT 24
Peak memory 322104 kb
Host smart-af08b146-4adc-462c-abc2-0151c5d2e489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734050778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.2734050778
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.160809914
Short name T1321
Test name
Test status
Simulation time 5876278025 ps
CPU time 71.43 seconds
Started Apr 28 12:58:49 PM PDT 24
Finished Apr 28 01:00:01 PM PDT 24
Peak memory 345744 kb
Host smart-3e0cacae-4993-49b4-ac5e-401e0342c701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160809914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.160809914
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.2794937951
Short name T596
Test name
Test status
Simulation time 2281370301 ps
CPU time 25.17 seconds
Started Apr 28 12:58:53 PM PDT 24
Finished Apr 28 12:59:19 PM PDT 24
Peak memory 212396 kb
Host smart-19008f25-21df-45ca-b69c-4cb2482de343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794937951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2794937951
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.443323377
Short name T113
Test name
Test status
Simulation time 42094410 ps
CPU time 0.85 seconds
Started Apr 28 12:58:50 PM PDT 24
Finished Apr 28 12:58:52 PM PDT 24
Peak memory 221452 kb
Host smart-1b7c97b1-295a-4305-88a0-3bbc5d03cc88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443323377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.443323377
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.2125149666
Short name T990
Test name
Test status
Simulation time 3922278758 ps
CPU time 4 seconds
Started Apr 28 12:58:56 PM PDT 24
Finished Apr 28 12:59:01 PM PDT 24
Peak memory 204264 kb
Host smart-c73160ee-d765-4b38-aa2d-c9a5b60ba012
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125149666 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.2125149666
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.2081048210
Short name T726
Test name
Test status
Simulation time 10152582581 ps
CPU time 11.59 seconds
Started Apr 28 12:58:51 PM PDT 24
Finished Apr 28 12:59:03 PM PDT 24
Peak memory 256308 kb
Host smart-fc94f80c-b633-40fa-9d0c-0ada11659e51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081048210 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.2081048210
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.2828522159
Short name T870
Test name
Test status
Simulation time 10238667005 ps
CPU time 16.37 seconds
Started Apr 28 12:58:49 PM PDT 24
Finished Apr 28 12:59:06 PM PDT 24
Peak memory 326588 kb
Host smart-90df35c0-c98f-4853-9cf2-b5aabc2534ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828522159 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.2828522159
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.1559571740
Short name T24
Test name
Test status
Simulation time 1185772741 ps
CPU time 2.11 seconds
Started Apr 28 12:58:50 PM PDT 24
Finished Apr 28 12:58:53 PM PDT 24
Peak memory 204004 kb
Host smart-7463a5e4-e447-4dd7-8b54-025385b412cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559571740 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.1559571740
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.1967377072
Short name T1041
Test name
Test status
Simulation time 4369949185 ps
CPU time 5.91 seconds
Started Apr 28 12:59:02 PM PDT 24
Finished Apr 28 12:59:09 PM PDT 24
Peak memory 204148 kb
Host smart-cc723c72-19e5-4f72-ae43-bf6eb99a4792
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967377072 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.1967377072
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.505046204
Short name T975
Test name
Test status
Simulation time 9777833616 ps
CPU time 14.31 seconds
Started Apr 28 12:59:09 PM PDT 24
Finished Apr 28 12:59:27 PM PDT 24
Peak memory 375812 kb
Host smart-e6367acc-a411-4626-8d0a-6a086bebea11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505046204 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.505046204
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.2021495070
Short name T833
Test name
Test status
Simulation time 4547643723 ps
CPU time 14.12 seconds
Started Apr 28 12:58:52 PM PDT 24
Finished Apr 28 12:59:07 PM PDT 24
Peak memory 204040 kb
Host smart-d3dec105-f108-49bd-ae8e-6ba513d8b2f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021495070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.2021495070
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.3935669544
Short name T1121
Test name
Test status
Simulation time 474530963 ps
CPU time 4.07 seconds
Started Apr 28 12:58:56 PM PDT 24
Finished Apr 28 12:59:02 PM PDT 24
Peak memory 204148 kb
Host smart-86ca6a56-cabe-48c8-a7a9-dae159242c9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935669544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.3935669544
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.3239980406
Short name T401
Test name
Test status
Simulation time 28199610190 ps
CPU time 166.01 seconds
Started Apr 28 12:59:04 PM PDT 24
Finished Apr 28 01:01:52 PM PDT 24
Peak memory 2219712 kb
Host smart-6434474f-031f-407d-8f7d-284f6639b6ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239980406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.3239980406
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.760162038
Short name T1197
Test name
Test status
Simulation time 24759696294 ps
CPU time 3197.1 seconds
Started Apr 28 12:59:02 PM PDT 24
Finished Apr 28 01:52:21 PM PDT 24
Peak memory 4540964 kb
Host smart-a0fb2130-5e47-40d5-bd9d-c40d5333085f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760162038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_ta
rget_stretch.760162038
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.42549838
Short name T593
Test name
Test status
Simulation time 17222433443 ps
CPU time 6.62 seconds
Started Apr 28 12:58:56 PM PDT 24
Finished Apr 28 12:59:04 PM PDT 24
Peak memory 212432 kb
Host smart-a5fae509-c891-4885-a454-ca83e3fbc2e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42549838 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_timeout.42549838
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.3822725046
Short name T1179
Test name
Test status
Simulation time 16940581 ps
CPU time 0.61 seconds
Started Apr 28 12:59:32 PM PDT 24
Finished Apr 28 12:59:33 PM PDT 24
Peak memory 203888 kb
Host smart-2b270ba0-a6da-43f8-86ae-7e2836c6063b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822725046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.3822725046
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.2166468557
Short name T989
Test name
Test status
Simulation time 63330820 ps
CPU time 1.64 seconds
Started Apr 28 12:59:33 PM PDT 24
Finished Apr 28 12:59:35 PM PDT 24
Peak memory 212444 kb
Host smart-4d02b659-13b0-4c94-8f94-e1aad745ba7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166468557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2166468557
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.315886870
Short name T1024
Test name
Test status
Simulation time 1567038190 ps
CPU time 6.01 seconds
Started Apr 28 12:59:37 PM PDT 24
Finished Apr 28 12:59:44 PM PDT 24
Peak memory 257956 kb
Host smart-251d2390-cbbc-4712-851b-500db756a8ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315886870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empt
y.315886870
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.1949795520
Short name T1130
Test name
Test status
Simulation time 7296642445 ps
CPU time 51.06 seconds
Started Apr 28 12:59:37 PM PDT 24
Finished Apr 28 01:00:29 PM PDT 24
Peak memory 641364 kb
Host smart-b39d6ded-2026-4f0b-b768-1b796a6130c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949795520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.1949795520
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.2182983998
Short name T387
Test name
Test status
Simulation time 13688758881 ps
CPU time 37.9 seconds
Started Apr 28 12:59:40 PM PDT 24
Finished Apr 28 01:00:19 PM PDT 24
Peak memory 490632 kb
Host smart-e648580e-d740-409f-8d63-a2d9e00e6d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182983998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.2182983998
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.29726358
Short name T1155
Test name
Test status
Simulation time 314328088 ps
CPU time 0.95 seconds
Started Apr 28 12:59:22 PM PDT 24
Finished Apr 28 12:59:23 PM PDT 24
Peak memory 203952 kb
Host smart-983713ed-0efa-4d5f-8129-81a859153aa3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29726358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fmt
.29726358
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.224589876
Short name T896
Test name
Test status
Simulation time 356149509 ps
CPU time 4.53 seconds
Started Apr 28 12:59:28 PM PDT 24
Finished Apr 28 12:59:33 PM PDT 24
Peak memory 204160 kb
Host smart-140220df-9486-487f-8a99-c320f0d7d298
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224589876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.
224589876
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.3366393196
Short name T664
Test name
Test status
Simulation time 14279600064 ps
CPU time 75.92 seconds
Started Apr 28 12:59:29 PM PDT 24
Finished Apr 28 01:00:45 PM PDT 24
Peak memory 1002484 kb
Host smart-58a7824f-2723-4ee3-9bcd-65c90de38fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366393196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.3366393196
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.2426385740
Short name T542
Test name
Test status
Simulation time 230056131 ps
CPU time 3.28 seconds
Started Apr 28 12:59:32 PM PDT 24
Finished Apr 28 12:59:36 PM PDT 24
Peak memory 203984 kb
Host smart-a2488a16-964e-478d-9e3d-684d9d2a72be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426385740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.2426385740
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.3305783885
Short name T235
Test name
Test status
Simulation time 3505692019 ps
CPU time 40.65 seconds
Started Apr 28 12:59:31 PM PDT 24
Finished Apr 28 01:00:12 PM PDT 24
Peak memory 419364 kb
Host smart-00686079-3ecf-48b8-9efd-27ce06859a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305783885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.3305783885
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.1310346104
Short name T214
Test name
Test status
Simulation time 59506369 ps
CPU time 0.69 seconds
Started Apr 28 12:59:22 PM PDT 24
Finished Apr 28 12:59:23 PM PDT 24
Peak memory 203764 kb
Host smart-88d5f059-64ae-470f-b134-7561a59b4c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310346104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.1310346104
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.4110299645
Short name T65
Test name
Test status
Simulation time 12646195283 ps
CPU time 170.28 seconds
Started Apr 28 12:59:28 PM PDT 24
Finished Apr 28 01:02:18 PM PDT 24
Peak memory 751108 kb
Host smart-1a72b261-4634-41d9-afad-6e56a0c4955e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110299645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.4110299645
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.4005250816
Short name T190
Test name
Test status
Simulation time 2753355208 ps
CPU time 26.8 seconds
Started Apr 28 12:59:32 PM PDT 24
Finished Apr 28 01:00:00 PM PDT 24
Peak memory 301176 kb
Host smart-23be935a-4ec4-4cfa-af87-90c5191daec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005250816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.4005250816
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.3538192202
Short name T894
Test name
Test status
Simulation time 4148689654 ps
CPU time 18.11 seconds
Started Apr 28 12:59:26 PM PDT 24
Finished Apr 28 12:59:45 PM PDT 24
Peak memory 220548 kb
Host smart-37c399b3-5863-459f-a3ad-29074f28a4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538192202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.3538192202
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.1513230703
Short name T244
Test name
Test status
Simulation time 2101750199 ps
CPU time 3.52 seconds
Started Apr 28 12:59:35 PM PDT 24
Finished Apr 28 12:59:39 PM PDT 24
Peak memory 204196 kb
Host smart-cc6458ce-f499-4fc4-8540-75086d769626
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513230703 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.1513230703
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.1623042990
Short name T819
Test name
Test status
Simulation time 10283563307 ps
CPU time 28.25 seconds
Started Apr 28 12:59:26 PM PDT 24
Finished Apr 28 12:59:55 PM PDT 24
Peak memory 360300 kb
Host smart-04fb7b9d-d137-4d41-b9cc-babcea0f4377
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623042990 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.1623042990
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.2646508684
Short name T1104
Test name
Test status
Simulation time 10109434191 ps
CPU time 69.27 seconds
Started Apr 28 12:59:30 PM PDT 24
Finished Apr 28 01:00:40 PM PDT 24
Peak memory 479012 kb
Host smart-ba752aac-1cff-4912-9114-a815cdb471c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646508684 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.2646508684
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.3945646071
Short name T531
Test name
Test status
Simulation time 2017746198 ps
CPU time 2.83 seconds
Started Apr 28 12:59:31 PM PDT 24
Finished Apr 28 12:59:34 PM PDT 24
Peak memory 204200 kb
Host smart-4b2a9c59-2f90-4bbf-84c1-55ea68ed0663
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945646071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.3945646071
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.834211194
Short name T397
Test name
Test status
Simulation time 900603776 ps
CPU time 4.52 seconds
Started Apr 28 12:59:26 PM PDT 24
Finished Apr 28 12:59:31 PM PDT 24
Peak memory 208108 kb
Host smart-0a053f0a-3437-447e-b3dc-03c7aced3118
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834211194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_intr_smoke.834211194
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.2102606995
Short name T1072
Test name
Test status
Simulation time 19644363428 ps
CPU time 15.5 seconds
Started Apr 28 12:59:32 PM PDT 24
Finished Apr 28 12:59:49 PM PDT 24
Peak memory 530724 kb
Host smart-37b86ba0-0812-462f-856d-60b5e6fff234
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102606995 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.2102606995
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.506983009
Short name T889
Test name
Test status
Simulation time 1203913414 ps
CPU time 16.9 seconds
Started Apr 28 12:59:27 PM PDT 24
Finished Apr 28 12:59:44 PM PDT 24
Peak memory 204012 kb
Host smart-176bf817-c014-46a1-a882-9a19fd559d13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506983009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_tar
get_smoke.506983009
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.1649837841
Short name T964
Test name
Test status
Simulation time 1439243177 ps
CPU time 20.86 seconds
Started Apr 28 12:59:26 PM PDT 24
Finished Apr 28 12:59:47 PM PDT 24
Peak memory 232580 kb
Host smart-c8c28afa-e6c3-4d0c-9257-fd77e16e79d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649837841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.1649837841
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.2775118210
Short name T411
Test name
Test status
Simulation time 65070271420 ps
CPU time 2688.85 seconds
Started Apr 28 12:59:32 PM PDT 24
Finished Apr 28 01:44:22 PM PDT 24
Peak memory 11409812 kb
Host smart-e37135e8-5a30-4c05-8884-63fc06c6aa77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775118210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.2775118210
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.3534178753
Short name T372
Test name
Test status
Simulation time 14316220265 ps
CPU time 196.78 seconds
Started Apr 28 12:59:36 PM PDT 24
Finished Apr 28 01:02:54 PM PDT 24
Peak memory 1780252 kb
Host smart-c7c8a527-e1b6-4673-8c75-d88b4468f11d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534178753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.3534178753
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.1278891767
Short name T1250
Test name
Test status
Simulation time 1361983542 ps
CPU time 7.31 seconds
Started Apr 28 12:59:32 PM PDT 24
Finished Apr 28 12:59:40 PM PDT 24
Peak memory 220188 kb
Host smart-d8f924ae-574c-4278-a0ee-a482871d04d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278891767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.1278891767
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.1588139065
Short name T585
Test name
Test status
Simulation time 19538970 ps
CPU time 0.6 seconds
Started Apr 28 12:59:40 PM PDT 24
Finished Apr 28 12:59:41 PM PDT 24
Peak memory 203688 kb
Host smart-3896a094-cacd-4eac-82c1-a20b6a64c23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588139065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.1588139065
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.3799671491
Short name T1305
Test name
Test status
Simulation time 71531852 ps
CPU time 1.5 seconds
Started Apr 28 12:59:34 PM PDT 24
Finished Apr 28 12:59:36 PM PDT 24
Peak memory 212436 kb
Host smart-302b379c-15c2-4e9f-a74b-85e68935155b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799671491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.3799671491
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.3447232400
Short name T426
Test name
Test status
Simulation time 328225403 ps
CPU time 15.7 seconds
Started Apr 28 12:59:35 PM PDT 24
Finished Apr 28 12:59:52 PM PDT 24
Peak memory 256940 kb
Host smart-cb0320b5-37d3-44f0-b506-570a172e7cc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447232400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.3447232400
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1043706163
Short name T1146
Test name
Test status
Simulation time 6202671610 ps
CPU time 51.22 seconds
Started Apr 28 12:59:36 PM PDT 24
Finished Apr 28 01:00:28 PM PDT 24
Peak memory 623248 kb
Host smart-ac8b0ccd-f64f-4d28-aab4-82347112b5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043706163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1043706163
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.3361826667
Short name T615
Test name
Test status
Simulation time 8106520158 ps
CPU time 139.19 seconds
Started Apr 28 12:59:36 PM PDT 24
Finished Apr 28 01:01:56 PM PDT 24
Peak memory 608036 kb
Host smart-4a8dd709-9e6e-4168-bf1d-65da1b252452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361826667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.3361826667
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.4244261155
Short name T526
Test name
Test status
Simulation time 153129725 ps
CPU time 1.06 seconds
Started Apr 28 12:59:41 PM PDT 24
Finished Apr 28 12:59:43 PM PDT 24
Peak memory 203988 kb
Host smart-0dede60f-2c09-46e5-b679-b83b745f9d3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244261155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.4244261155
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.1567118804
Short name T965
Test name
Test status
Simulation time 645392985 ps
CPU time 9.57 seconds
Started Apr 28 12:59:38 PM PDT 24
Finished Apr 28 12:59:48 PM PDT 24
Peak memory 234404 kb
Host smart-a7fe8d42-9385-478f-b944-9fef78a032d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567118804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.1567118804
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.1734820618
Short name T1163
Test name
Test status
Simulation time 4260382991 ps
CPU time 123.59 seconds
Started Apr 28 12:59:36 PM PDT 24
Finished Apr 28 01:01:41 PM PDT 24
Peak memory 1195544 kb
Host smart-0db04580-c301-40f1-a954-b3f2fcf63404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734820618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.1734820618
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.351562035
Short name T831
Test name
Test status
Simulation time 295206016 ps
CPU time 12.04 seconds
Started Apr 28 12:59:46 PM PDT 24
Finished Apr 28 12:59:59 PM PDT 24
Peak memory 204004 kb
Host smart-755beda2-73fd-4946-9049-81baf07bf3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351562035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.351562035
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.2953845831
Short name T1259
Test name
Test status
Simulation time 2907633799 ps
CPU time 36.97 seconds
Started Apr 28 12:59:40 PM PDT 24
Finished Apr 28 01:00:18 PM PDT 24
Peak memory 274572 kb
Host smart-92dc44a4-4c43-4c8e-94ce-d57eaf618339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953845831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.2953845831
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.3855558951
Short name T1249
Test name
Test status
Simulation time 25042223 ps
CPU time 0.64 seconds
Started Apr 28 12:59:45 PM PDT 24
Finished Apr 28 12:59:47 PM PDT 24
Peak memory 203800 kb
Host smart-c49383a7-0e37-4587-957b-2ee31e5166ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855558951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.3855558951
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.1170918501
Short name T369
Test name
Test status
Simulation time 7206490144 ps
CPU time 100.15 seconds
Started Apr 28 12:59:36 PM PDT 24
Finished Apr 28 01:01:17 PM PDT 24
Peak memory 204132 kb
Host smart-16909439-8069-4865-bd32-0b9b6fa3af51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170918501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.1170918501
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.1637571278
Short name T1277
Test name
Test status
Simulation time 751223438 ps
CPU time 12.17 seconds
Started Apr 28 12:59:46 PM PDT 24
Finished Apr 28 12:59:59 PM PDT 24
Peak memory 277316 kb
Host smart-8fd8e563-318c-4a80-ac0d-9712a0abd91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637571278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.1637571278
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.673419891
Short name T200
Test name
Test status
Simulation time 44127961737 ps
CPU time 234.17 seconds
Started Apr 28 12:59:38 PM PDT 24
Finished Apr 28 01:03:33 PM PDT 24
Peak memory 1033224 kb
Host smart-a6400ccd-f276-4801-923e-7496aebe00ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673419891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.673419891
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.848023573
Short name T1244
Test name
Test status
Simulation time 1364861709 ps
CPU time 30.56 seconds
Started Apr 28 12:59:42 PM PDT 24
Finished Apr 28 01:00:13 PM PDT 24
Peak memory 212176 kb
Host smart-91c4d908-f292-40cd-9da9-699a89e1c87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848023573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.848023573
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.2607702449
Short name T1161
Test name
Test status
Simulation time 1272757346 ps
CPU time 3.37 seconds
Started Apr 28 12:59:45 PM PDT 24
Finished Apr 28 12:59:49 PM PDT 24
Peak memory 204080 kb
Host smart-264b24a8-f68d-41d7-ae1f-a49e82cadeb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607702449 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.2607702449
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.875536364
Short name T836
Test name
Test status
Simulation time 10113891961 ps
CPU time 76.64 seconds
Started Apr 28 12:59:40 PM PDT 24
Finished Apr 28 01:00:59 PM PDT 24
Peak memory 435644 kb
Host smart-0e225aa4-111c-4340-a1ba-5b28784084bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875536364 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_acq.875536364
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.2362377222
Short name T759
Test name
Test status
Simulation time 10315783645 ps
CPU time 14.67 seconds
Started Apr 28 12:59:40 PM PDT 24
Finished Apr 28 12:59:55 PM PDT 24
Peak memory 274472 kb
Host smart-bf00553c-23d2-483f-beac-8a4c072ecdea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362377222 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.2362377222
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.1936174637
Short name T543
Test name
Test status
Simulation time 1910431857 ps
CPU time 2.73 seconds
Started Apr 28 12:59:40 PM PDT 24
Finished Apr 28 12:59:44 PM PDT 24
Peak memory 204188 kb
Host smart-8ceda06a-ae62-4481-8c3e-4c14ee0380e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936174637 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.1936174637
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.2139023505
Short name T493
Test name
Test status
Simulation time 1281691043 ps
CPU time 6.61 seconds
Started Apr 28 12:59:41 PM PDT 24
Finished Apr 28 12:59:49 PM PDT 24
Peak memory 217372 kb
Host smart-7b01b77d-8a85-46fb-a5b6-1a0b3632c69c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139023505 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.2139023505
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.886863010
Short name T599
Test name
Test status
Simulation time 27462929204 ps
CPU time 82.74 seconds
Started Apr 28 12:59:44 PM PDT 24
Finished Apr 28 01:01:08 PM PDT 24
Peak memory 1528584 kb
Host smart-beaea226-8bee-4377-b31b-9baf2881ae87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886863010 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.886863010
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.4027939287
Short name T775
Test name
Test status
Simulation time 2199451499 ps
CPU time 8.02 seconds
Started Apr 28 12:59:36 PM PDT 24
Finished Apr 28 12:59:45 PM PDT 24
Peak memory 204212 kb
Host smart-cc9dc179-ffcb-4228-8b52-a2dce1331853
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027939287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.4027939287
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.2918601689
Short name T266
Test name
Test status
Simulation time 1211559960 ps
CPU time 51.13 seconds
Started Apr 28 12:59:47 PM PDT 24
Finished Apr 28 01:00:39 PM PDT 24
Peak memory 204596 kb
Host smart-4369dc9c-f53e-4a90-a1f6-db4f759140f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918601689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.2918601689
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.1487426380
Short name T1242
Test name
Test status
Simulation time 49087758964 ps
CPU time 1006.38 seconds
Started Apr 28 12:59:39 PM PDT 24
Finished Apr 28 01:16:26 PM PDT 24
Peak memory 7095256 kb
Host smart-90f6f45a-5dd1-4b5e-a91c-6f813639ee07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487426380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.1487426380
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.1679457558
Short name T554
Test name
Test status
Simulation time 19042917577 ps
CPU time 142.44 seconds
Started Apr 28 12:59:45 PM PDT 24
Finished Apr 28 01:02:09 PM PDT 24
Peak memory 1131196 kb
Host smart-5c47c069-0622-4079-b429-0dfe24c2f313
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679457558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.1679457558
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.3583682140
Short name T1324
Test name
Test status
Simulation time 1612481906 ps
CPU time 7.46 seconds
Started Apr 28 12:59:38 PM PDT 24
Finished Apr 28 12:59:46 PM PDT 24
Peak memory 212360 kb
Host smart-6517dcbf-037c-4606-8688-176e40bb85e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583682140 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.3583682140
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.397887520
Short name T1225
Test name
Test status
Simulation time 95488752 ps
CPU time 1.31 seconds
Started Apr 28 12:59:41 PM PDT 24
Finished Apr 28 12:59:43 PM PDT 24
Peak memory 212472 kb
Host smart-d92b3ee1-4b72-4fe7-a587-c65ac640fb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397887520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.397887520
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3636701683
Short name T381
Test name
Test status
Simulation time 731087100 ps
CPU time 19.41 seconds
Started Apr 28 12:59:41 PM PDT 24
Finished Apr 28 01:00:02 PM PDT 24
Peak memory 279592 kb
Host smart-3f2e7c2e-fb2d-4d1e-97f9-60ab6caf203d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636701683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3636701683
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.2455330704
Short name T594
Test name
Test status
Simulation time 2684227034 ps
CPU time 41.34 seconds
Started Apr 28 12:59:43 PM PDT 24
Finished Apr 28 01:00:25 PM PDT 24
Peak memory 506944 kb
Host smart-d7c598ab-f0e1-4165-8801-d9b834c652ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455330704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.2455330704
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.3815726189
Short name T662
Test name
Test status
Simulation time 3690944291 ps
CPU time 47.22 seconds
Started Apr 28 12:59:47 PM PDT 24
Finished Apr 28 01:00:35 PM PDT 24
Peak memory 484368 kb
Host smart-ee45fdad-d8cf-47d3-b6d6-910c46e2fc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815726189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.3815726189
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.4006200265
Short name T950
Test name
Test status
Simulation time 294207205 ps
CPU time 1.1 seconds
Started Apr 28 12:59:47 PM PDT 24
Finished Apr 28 12:59:49 PM PDT 24
Peak memory 204132 kb
Host smart-a7c67b11-2d6d-453e-ba49-c009ac9e684f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006200265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.4006200265
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.1632724855
Short name T638
Test name
Test status
Simulation time 246107718 ps
CPU time 6.9 seconds
Started Apr 28 12:59:42 PM PDT 24
Finished Apr 28 12:59:50 PM PDT 24
Peak memory 223620 kb
Host smart-7b403cff-799c-4550-a730-8297305a1088
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632724855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.1632724855
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.821572431
Short name T1100
Test name
Test status
Simulation time 3867438449 ps
CPU time 111.69 seconds
Started Apr 28 12:59:40 PM PDT 24
Finished Apr 28 01:01:33 PM PDT 24
Peak memory 1128268 kb
Host smart-d50a5b91-1dc2-4f55-a747-2bcb0e71ccc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821572431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.821572431
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.2166017235
Short name T627
Test name
Test status
Simulation time 374921174 ps
CPU time 15.02 seconds
Started Apr 28 12:59:47 PM PDT 24
Finished Apr 28 01:00:03 PM PDT 24
Peak memory 204028 kb
Host smart-9c47eef3-7b5e-49de-870d-f0d3762002ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166017235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.2166017235
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.2596785811
Short name T1176
Test name
Test status
Simulation time 859948237 ps
CPU time 13.25 seconds
Started Apr 28 12:59:49 PM PDT 24
Finished Apr 28 01:00:03 PM PDT 24
Peak memory 277620 kb
Host smart-36b2917e-90b8-4388-a063-281b15df7151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596785811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.2596785811
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.3938600923
Short name T602
Test name
Test status
Simulation time 28505058 ps
CPU time 0.66 seconds
Started Apr 28 12:59:46 PM PDT 24
Finished Apr 28 12:59:47 PM PDT 24
Peak memory 203832 kb
Host smart-66d4bfb6-3846-43bb-997b-3a31217e0bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938600923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.3938600923
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.2319145725
Short name T853
Test name
Test status
Simulation time 25207253608 ps
CPU time 91.54 seconds
Started Apr 28 12:59:47 PM PDT 24
Finished Apr 28 01:01:19 PM PDT 24
Peak memory 219124 kb
Host smart-7eb4e6bc-0062-4e31-a73a-6e08ececd56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319145725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2319145725
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.3340368615
Short name T504
Test name
Test status
Simulation time 1395400403 ps
CPU time 71.62 seconds
Started Apr 28 12:59:44 PM PDT 24
Finished Apr 28 01:00:56 PM PDT 24
Peak memory 358424 kb
Host smart-c1a50e3e-0aac-4138-8a03-003a7c5c0ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340368615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.3340368615
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.2133826733
Short name T199
Test name
Test status
Simulation time 17626936307 ps
CPU time 630.77 seconds
Started Apr 28 12:59:45 PM PDT 24
Finished Apr 28 01:10:17 PM PDT 24
Peak memory 2112464 kb
Host smart-303dfffc-be07-496e-b574-d4e07631e3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133826733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.2133826733
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.3842247665
Short name T300
Test name
Test status
Simulation time 1192028348 ps
CPU time 26.07 seconds
Started Apr 28 12:59:39 PM PDT 24
Finished Apr 28 01:00:06 PM PDT 24
Peak memory 212308 kb
Host smart-64340103-87e6-4f62-aeae-ad466ee821e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842247665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3842247665
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.648079599
Short name T1319
Test name
Test status
Simulation time 721819774 ps
CPU time 3.32 seconds
Started Apr 28 12:59:46 PM PDT 24
Finished Apr 28 12:59:51 PM PDT 24
Peak memory 212348 kb
Host smart-d9c1b033-8ebc-4d5a-a174-fcaee8ef1462
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648079599 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.648079599
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.3534432868
Short name T881
Test name
Test status
Simulation time 10027727499 ps
CPU time 80.66 seconds
Started Apr 28 12:59:49 PM PDT 24
Finished Apr 28 01:01:10 PM PDT 24
Peak memory 569312 kb
Host smart-ce6541ce-1baf-4d40-84a0-f8337a526667
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534432868 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.3534432868
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.3034612408
Short name T1211
Test name
Test status
Simulation time 264312714 ps
CPU time 1.85 seconds
Started Apr 28 12:59:46 PM PDT 24
Finished Apr 28 12:59:49 PM PDT 24
Peak memory 204064 kb
Host smart-b2f91b3f-3165-493a-bb70-2d773641098a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034612408 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.3034612408
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.834755154
Short name T321
Test name
Test status
Simulation time 12842454957 ps
CPU time 6.64 seconds
Started Apr 28 12:59:50 PM PDT 24
Finished Apr 28 12:59:57 PM PDT 24
Peak memory 220376 kb
Host smart-0e54ba80-dcad-4bc9-9e38-b80554c73fc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834755154 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_intr_smoke.834755154
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.1675513283
Short name T1046
Test name
Test status
Simulation time 27182588053 ps
CPU time 69.39 seconds
Started Apr 28 12:59:45 PM PDT 24
Finished Apr 28 01:00:55 PM PDT 24
Peak memory 1346388 kb
Host smart-f239d413-2e1c-42d4-a5b0-f37fbdb3de09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675513283 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.1675513283
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.3144088938
Short name T103
Test name
Test status
Simulation time 731099958 ps
CPU time 12.21 seconds
Started Apr 28 12:59:50 PM PDT 24
Finished Apr 28 01:00:03 PM PDT 24
Peak memory 204128 kb
Host smart-0cc87257-d137-405e-838b-1f226b5526dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144088938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.3144088938
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.3889518811
Short name T859
Test name
Test status
Simulation time 8176027157 ps
CPU time 17.19 seconds
Started Apr 28 12:59:45 PM PDT 24
Finished Apr 28 01:00:03 PM PDT 24
Peak memory 204060 kb
Host smart-0379d209-2e99-410a-ba52-38524240e768
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889518811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.3889518811
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.3395452643
Short name T347
Test name
Test status
Simulation time 23952776233 ps
CPU time 1233.68 seconds
Started Apr 28 12:59:46 PM PDT 24
Finished Apr 28 01:20:20 PM PDT 24
Peak memory 2645488 kb
Host smart-e3080028-409f-4277-bc9d-7c6245c92a5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395452643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.3395452643
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.528950027
Short name T374
Test name
Test status
Simulation time 9425460434 ps
CPU time 6.78 seconds
Started Apr 28 12:59:44 PM PDT 24
Finished Apr 28 12:59:52 PM PDT 24
Peak memory 212460 kb
Host smart-515a678b-beac-4105-a2e2-7e9b8cdc07cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528950027 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_timeout.528950027
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2403362956
Short name T1169
Test name
Test status
Simulation time 24354631 ps
CPU time 0.61 seconds
Started Apr 28 12:59:59 PM PDT 24
Finished Apr 28 01:00:01 PM PDT 24
Peak memory 203700 kb
Host smart-cd9e1693-b3ad-4b7c-994f-304e26e5b80e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403362956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2403362956
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.3093240309
Short name T935
Test name
Test status
Simulation time 336313448 ps
CPU time 1.53 seconds
Started Apr 28 12:59:55 PM PDT 24
Finished Apr 28 12:59:57 PM PDT 24
Peak memory 212324 kb
Host smart-3d0adfec-91e4-4bda-83ff-71035dca81fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093240309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.3093240309
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.4156994342
Short name T1043
Test name
Test status
Simulation time 276254520 ps
CPU time 5.65 seconds
Started Apr 28 12:59:48 PM PDT 24
Finished Apr 28 12:59:54 PM PDT 24
Peak memory 244656 kb
Host smart-52c99edb-f3c9-45dc-a30c-b43a24596577
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156994342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.4156994342
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.1788347483
Short name T907
Test name
Test status
Simulation time 2365247306 ps
CPU time 83.89 seconds
Started Apr 28 12:59:54 PM PDT 24
Finished Apr 28 01:01:18 PM PDT 24
Peak memory 745156 kb
Host smart-97e813c5-ae1e-4590-87d1-2ee6a7ffd2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788347483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1788347483
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.2195347649
Short name T626
Test name
Test status
Simulation time 5643532242 ps
CPU time 41.93 seconds
Started Apr 28 12:59:50 PM PDT 24
Finished Apr 28 01:00:33 PM PDT 24
Peak memory 493624 kb
Host smart-a7bd98e0-894a-47aa-bce8-8c0c8cb7ccd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195347649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.2195347649
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.3905309002
Short name T1019
Test name
Test status
Simulation time 218248996 ps
CPU time 0.85 seconds
Started Apr 28 12:59:48 PM PDT 24
Finished Apr 28 12:59:50 PM PDT 24
Peak memory 203840 kb
Host smart-626780fe-6a1a-46d2-9088-18c312b0ee52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905309002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.3905309002
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.1766671546
Short name T692
Test name
Test status
Simulation time 1250556177 ps
CPU time 6.68 seconds
Started Apr 28 12:59:51 PM PDT 24
Finished Apr 28 12:59:58 PM PDT 24
Peak memory 204144 kb
Host smart-70906d94-239b-44c5-a804-70f022cedd03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766671546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.1766671546
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.3788278785
Short name T1290
Test name
Test status
Simulation time 10539188639 ps
CPU time 100.22 seconds
Started Apr 28 12:59:52 PM PDT 24
Finished Apr 28 01:01:33 PM PDT 24
Peak memory 1228504 kb
Host smart-6479ad0a-cbf0-44e2-9a0c-1e9cb7ab2ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788278785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.3788278785
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.3843831936
Short name T1278
Test name
Test status
Simulation time 2108927389 ps
CPU time 8.08 seconds
Started Apr 28 12:59:56 PM PDT 24
Finished Apr 28 01:00:05 PM PDT 24
Peak memory 204216 kb
Host smart-89441ef1-13b4-4adb-ab85-ebc26997cbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843831936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.3843831936
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.4203125638
Short name T1356
Test name
Test status
Simulation time 3480130082 ps
CPU time 73.76 seconds
Started Apr 28 01:00:10 PM PDT 24
Finished Apr 28 01:01:24 PM PDT 24
Peak memory 329132 kb
Host smart-56d7eddd-1fe3-4adf-bccb-ab959754cdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203125638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.4203125638
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.2352598403
Short name T326
Test name
Test status
Simulation time 29258438 ps
CPU time 0.71 seconds
Started Apr 28 12:59:55 PM PDT 24
Finished Apr 28 12:59:57 PM PDT 24
Peak memory 203700 kb
Host smart-6ef0b826-4c77-4143-b756-aee7de4bfd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352598403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.2352598403
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.1744490141
Short name T953
Test name
Test status
Simulation time 1377970429 ps
CPU time 19.81 seconds
Started Apr 28 12:59:51 PM PDT 24
Finished Apr 28 01:00:11 PM PDT 24
Peak memory 212204 kb
Host smart-5eba5505-fd03-4e25-b4b9-4fce33518d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744490141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.1744490141
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.3587427877
Short name T983
Test name
Test status
Simulation time 1641451495 ps
CPU time 23.9 seconds
Started Apr 28 12:59:45 PM PDT 24
Finished Apr 28 01:00:10 PM PDT 24
Peak memory 296128 kb
Host smart-5debb7b9-1752-45b7-bf39-bb22a1b9b195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587427877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.3587427877
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.2080657232
Short name T202
Test name
Test status
Simulation time 67276343774 ps
CPU time 901.6 seconds
Started Apr 28 12:59:56 PM PDT 24
Finished Apr 28 01:14:59 PM PDT 24
Peak memory 2182140 kb
Host smart-36c29b8c-f963-4cac-9aea-017a9c44d6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080657232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.2080657232
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.2278356038
Short name T503
Test name
Test status
Simulation time 793780930 ps
CPU time 13.19 seconds
Started Apr 28 12:59:55 PM PDT 24
Finished Apr 28 01:00:09 PM PDT 24
Peak memory 228684 kb
Host smart-ae3e6d4e-237d-4d8f-a0e1-b3421eac3bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278356038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.2278356038
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.3369490466
Short name T702
Test name
Test status
Simulation time 4006435307 ps
CPU time 4.45 seconds
Started Apr 28 12:59:50 PM PDT 24
Finished Apr 28 12:59:56 PM PDT 24
Peak memory 212484 kb
Host smart-fb4f3b34-dd73-470c-95d9-e28585f088a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369490466 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.3369490466
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.2963957632
Short name T1011
Test name
Test status
Simulation time 10078766673 ps
CPU time 16.12 seconds
Started Apr 28 12:59:49 PM PDT 24
Finished Apr 28 01:00:06 PM PDT 24
Peak memory 270108 kb
Host smart-7b77c6e3-a946-427b-a9d6-11c31156db50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963957632 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.2963957632
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.712059611
Short name T1219
Test name
Test status
Simulation time 10051122785 ps
CPU time 76.62 seconds
Started Apr 28 12:59:54 PM PDT 24
Finished Apr 28 01:01:11 PM PDT 24
Peak memory 588500 kb
Host smart-b5d8016b-bf91-44c9-982b-f142df2f8604
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712059611 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_fifo_reset_tx.712059611
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.3894670910
Short name T951
Test name
Test status
Simulation time 6443933180 ps
CPU time 7.58 seconds
Started Apr 28 01:00:00 PM PDT 24
Finished Apr 28 01:00:08 PM PDT 24
Peak memory 220396 kb
Host smart-0cde8b74-0587-4789-856b-12cdc3d32c6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894670910 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.3894670910
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.208611156
Short name T684
Test name
Test status
Simulation time 21898063824 ps
CPU time 60.12 seconds
Started Apr 28 12:59:50 PM PDT 24
Finished Apr 28 01:00:51 PM PDT 24
Peak memory 1334236 kb
Host smart-218aa415-88b5-4675-aab3-6fd71e6a8b8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208611156 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.208611156
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.1901242581
Short name T982
Test name
Test status
Simulation time 876142675 ps
CPU time 13.97 seconds
Started Apr 28 12:59:47 PM PDT 24
Finished Apr 28 01:00:02 PM PDT 24
Peak memory 204040 kb
Host smart-241f1eb1-7cb9-4c74-93db-7f77a6cd10b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901242581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.1901242581
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.658718337
Short name T270
Test name
Test status
Simulation time 3609786084 ps
CPU time 81.54 seconds
Started Apr 28 12:59:50 PM PDT 24
Finished Apr 28 01:01:13 PM PDT 24
Peak memory 207852 kb
Host smart-141a33d5-64fa-49f0-aa90-88f2c74297cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658718337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_rd.658718337
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.1572818246
Short name T1339
Test name
Test status
Simulation time 10372792204 ps
CPU time 5.99 seconds
Started Apr 28 12:59:51 PM PDT 24
Finished Apr 28 12:59:57 PM PDT 24
Peak memory 204040 kb
Host smart-56c50611-1e1e-456f-8658-86a21e69b694
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572818246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.1572818246
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.770202398
Short name T1240
Test name
Test status
Simulation time 20607879796 ps
CPU time 1618.62 seconds
Started Apr 28 12:59:55 PM PDT 24
Finished Apr 28 01:26:55 PM PDT 24
Peak memory 5023776 kb
Host smart-0b1a8777-0aae-4d91-b7c9-c9b427cf50f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770202398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_t
arget_stretch.770202398
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.3607805245
Short name T735
Test name
Test status
Simulation time 4973635278 ps
CPU time 6.24 seconds
Started Apr 28 12:59:52 PM PDT 24
Finished Apr 28 12:59:59 PM PDT 24
Peak memory 204280 kb
Host smart-545bcda7-72ae-467e-8260-48d0694d576a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607805245 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.3607805245
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.3896917890
Short name T1160
Test name
Test status
Simulation time 44270079 ps
CPU time 0.61 seconds
Started Apr 28 12:59:56 PM PDT 24
Finished Apr 28 12:59:57 PM PDT 24
Peak memory 203756 kb
Host smart-22949308-ff3f-4546-9229-24b979f71da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896917890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.3896917890
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.3593518854
Short name T383
Test name
Test status
Simulation time 103507608 ps
CPU time 1.38 seconds
Started Apr 28 12:59:54 PM PDT 24
Finished Apr 28 12:59:56 PM PDT 24
Peak memory 215300 kb
Host smart-d6a4534b-34c5-4f97-b61a-043113e59136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593518854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.3593518854
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.2255128456
Short name T764
Test name
Test status
Simulation time 1464917882 ps
CPU time 7.14 seconds
Started Apr 28 12:59:58 PM PDT 24
Finished Apr 28 01:00:05 PM PDT 24
Peak memory 225200 kb
Host smart-ac6bf999-53ab-414c-bc4f-f309a7dbcdbb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255128456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.2255128456
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.837587825
Short name T1269
Test name
Test status
Simulation time 2816141075 ps
CPU time 39.37 seconds
Started Apr 28 12:59:50 PM PDT 24
Finished Apr 28 01:00:30 PM PDT 24
Peak memory 541060 kb
Host smart-52460b25-e974-4602-9c7c-884f12dbc774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837587825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.837587825
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.1370422053
Short name T1241
Test name
Test status
Simulation time 8550140079 ps
CPU time 64.52 seconds
Started Apr 28 12:59:55 PM PDT 24
Finished Apr 28 01:01:00 PM PDT 24
Peak memory 735960 kb
Host smart-06981839-a2f7-41f6-8f79-b48be00616d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370422053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.1370422053
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.3692314027
Short name T1279
Test name
Test status
Simulation time 204333337 ps
CPU time 0.92 seconds
Started Apr 28 12:59:50 PM PDT 24
Finished Apr 28 12:59:51 PM PDT 24
Peak memory 204064 kb
Host smart-d3d6ffdd-6c56-4c85-8bca-8c6df202f0b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692314027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.3692314027
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.3336247212
Short name T453
Test name
Test status
Simulation time 584702757 ps
CPU time 3.76 seconds
Started Apr 28 12:59:52 PM PDT 24
Finished Apr 28 12:59:56 PM PDT 24
Peak memory 204052 kb
Host smart-9058b250-e14d-482b-866e-e0198c3affd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336247212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.3336247212
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.2914242862
Short name T1315
Test name
Test status
Simulation time 4046731915 ps
CPU time 281.66 seconds
Started Apr 28 12:59:54 PM PDT 24
Finished Apr 28 01:04:37 PM PDT 24
Peak memory 1123076 kb
Host smart-100d6836-ecf9-4649-846d-c110713ab0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914242862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.2914242862
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.2312233883
Short name T236
Test name
Test status
Simulation time 1222828577 ps
CPU time 5.26 seconds
Started Apr 28 12:59:57 PM PDT 24
Finished Apr 28 01:00:03 PM PDT 24
Peak memory 204120 kb
Host smart-3556302a-b6ed-4a9f-b347-d439b635a652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312233883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2312233883
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.3875675146
Short name T466
Test name
Test status
Simulation time 3206809635 ps
CPU time 28.12 seconds
Started Apr 28 12:59:54 PM PDT 24
Finished Apr 28 01:00:23 PM PDT 24
Peak memory 372704 kb
Host smart-cb5c98dd-bccf-408e-adfe-f8c97678d76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875675146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.3875675146
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.857047169
Short name T1031
Test name
Test status
Simulation time 16133711 ps
CPU time 0.64 seconds
Started Apr 28 12:59:54 PM PDT 24
Finished Apr 28 12:59:55 PM PDT 24
Peak memory 203844 kb
Host smart-d5e0b3bd-44b0-40c8-9fbc-c045571659fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857047169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.857047169
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.1539760559
Short name T803
Test name
Test status
Simulation time 2999037640 ps
CPU time 28.92 seconds
Started Apr 28 12:59:55 PM PDT 24
Finished Apr 28 01:00:25 PM PDT 24
Peak memory 403660 kb
Host smart-b88b4a78-8a5e-40e4-803e-50670f3455a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539760559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.1539760559
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.420270902
Short name T174
Test name
Test status
Simulation time 17263736864 ps
CPU time 2027.63 seconds
Started Apr 28 12:59:59 PM PDT 24
Finished Apr 28 01:33:48 PM PDT 24
Peak memory 1909444 kb
Host smart-cfecdc2b-b89d-48f8-854f-13eacdb560b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420270902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.420270902
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.1577259294
Short name T856
Test name
Test status
Simulation time 2196283246 ps
CPU time 13.21 seconds
Started Apr 28 12:59:51 PM PDT 24
Finished Apr 28 01:00:05 PM PDT 24
Peak memory 228764 kb
Host smart-3e057267-4139-434e-b983-f385dd47942a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577259294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.1577259294
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.1048372469
Short name T465
Test name
Test status
Simulation time 2894048763 ps
CPU time 4 seconds
Started Apr 28 12:59:58 PM PDT 24
Finished Apr 28 01:00:03 PM PDT 24
Peak memory 212440 kb
Host smart-3e2b682f-348e-4821-885c-fc6fb97839ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048372469 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.1048372469
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.502105034
Short name T1285
Test name
Test status
Simulation time 10253712175 ps
CPU time 15.15 seconds
Started Apr 28 12:59:56 PM PDT 24
Finished Apr 28 01:00:12 PM PDT 24
Peak memory 284944 kb
Host smart-c8a87a93-10bb-43a1-bc8a-44b3f37de001
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502105034 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_acq.502105034
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.2355366736
Short name T50
Test name
Test status
Simulation time 10099904241 ps
CPU time 36.12 seconds
Started Apr 28 12:59:58 PM PDT 24
Finished Apr 28 01:00:35 PM PDT 24
Peak memory 395340 kb
Host smart-aeb7b98a-294f-4d55-9458-1bb928996e31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355366736 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.2355366736
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.1636663139
Short name T479
Test name
Test status
Simulation time 2793044980 ps
CPU time 2.87 seconds
Started Apr 28 12:59:59 PM PDT 24
Finished Apr 28 01:00:03 PM PDT 24
Peak memory 204208 kb
Host smart-331b911a-0a6c-47a2-855b-41702a13bed8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636663139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.1636663139
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.3863290716
Short name T1322
Test name
Test status
Simulation time 1477494140 ps
CPU time 3.92 seconds
Started Apr 28 12:59:59 PM PDT 24
Finished Apr 28 01:00:04 PM PDT 24
Peak memory 204008 kb
Host smart-3a6561fc-8720-47f6-a323-c042375cfd43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863290716 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.3863290716
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.4276271935
Short name T284
Test name
Test status
Simulation time 12206521281 ps
CPU time 207.7 seconds
Started Apr 28 12:59:56 PM PDT 24
Finished Apr 28 01:03:25 PM PDT 24
Peak memory 2951804 kb
Host smart-9463c359-c2b2-49ef-b454-05a88fcf8286
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276271935 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.4276271935
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.1278645090
Short name T302
Test name
Test status
Simulation time 947257988 ps
CPU time 35.57 seconds
Started Apr 28 12:59:49 PM PDT 24
Finished Apr 28 01:00:25 PM PDT 24
Peak memory 204116 kb
Host smart-de3ec490-9af6-49bf-a1ca-4e5050f6556d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278645090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.1278645090
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.1377537638
Short name T793
Test name
Test status
Simulation time 3270926470 ps
CPU time 16.47 seconds
Started Apr 28 12:59:59 PM PDT 24
Finished Apr 28 01:00:17 PM PDT 24
Peak memory 209940 kb
Host smart-5a40842b-676c-4259-920b-7d5c3b18506d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377537638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.1377537638
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.2406987073
Short name T600
Test name
Test status
Simulation time 30250248572 ps
CPU time 76.21 seconds
Started Apr 28 12:59:59 PM PDT 24
Finished Apr 28 01:01:16 PM PDT 24
Peak memory 1337672 kb
Host smart-67f5ad26-6c28-4ed5-ad82-a8a09fb16030
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406987073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.2406987073
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1253988302
Short name T1328
Test name
Test status
Simulation time 12444984113 ps
CPU time 1231.03 seconds
Started Apr 28 12:59:55 PM PDT 24
Finished Apr 28 01:20:27 PM PDT 24
Peak memory 2725776 kb
Host smart-f98eb140-db94-4c8b-9527-f355362fe4d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253988302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1253988302
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.2001824604
Short name T288
Test name
Test status
Simulation time 1190005124 ps
CPU time 6.48 seconds
Started Apr 28 12:59:56 PM PDT 24
Finished Apr 28 01:00:03 PM PDT 24
Peak memory 216700 kb
Host smart-6c2b4485-3132-4baa-baee-6cb099ca221a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001824604 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.2001824604
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.1052642836
Short name T433
Test name
Test status
Simulation time 16936921 ps
CPU time 0.62 seconds
Started Apr 28 01:00:08 PM PDT 24
Finished Apr 28 01:00:09 PM PDT 24
Peak memory 203860 kb
Host smart-2e442743-ab77-43f7-ae9c-0231dcace679
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052642836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.1052642836
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.2775639169
Short name T540
Test name
Test status
Simulation time 80739044 ps
CPU time 1.35 seconds
Started Apr 28 12:59:56 PM PDT 24
Finished Apr 28 12:59:58 PM PDT 24
Peak memory 212464 kb
Host smart-92060097-e0f5-4c35-a719-70aa56ac93c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775639169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.2775639169
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.714705758
Short name T716
Test name
Test status
Simulation time 328621289 ps
CPU time 7.46 seconds
Started Apr 28 12:59:58 PM PDT 24
Finished Apr 28 01:00:06 PM PDT 24
Peak memory 273348 kb
Host smart-dff2e370-58cd-46f9-b6de-30e4c291d186
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714705758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empt
y.714705758
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.317342839
Short name T1004
Test name
Test status
Simulation time 4205057576 ps
CPU time 58.15 seconds
Started Apr 28 12:59:55 PM PDT 24
Finished Apr 28 01:00:54 PM PDT 24
Peak memory 600128 kb
Host smart-59e94920-5058-4e48-8799-3d7b33bd0a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317342839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.317342839
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.2532537410
Short name T90
Test name
Test status
Simulation time 2087558379 ps
CPU time 72.68 seconds
Started Apr 28 12:59:58 PM PDT 24
Finished Apr 28 01:01:11 PM PDT 24
Peak memory 688564 kb
Host smart-1b9c99c3-7f48-46a5-830f-bce2ff26f620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532537410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.2532537410
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.1030195135
Short name T710
Test name
Test status
Simulation time 92593201 ps
CPU time 1.13 seconds
Started Apr 28 12:59:58 PM PDT 24
Finished Apr 28 01:00:00 PM PDT 24
Peak memory 204108 kb
Host smart-efd736ec-6f99-4cfb-880e-277d0684058f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030195135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.1030195135
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.4200321333
Short name T865
Test name
Test status
Simulation time 125858369 ps
CPU time 6.89 seconds
Started Apr 28 12:59:58 PM PDT 24
Finished Apr 28 01:00:06 PM PDT 24
Peak memory 224156 kb
Host smart-ae1d843a-fe4e-4257-b8ff-c0e0778a6e9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200321333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.4200321333
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.1096572665
Short name T1320
Test name
Test status
Simulation time 3885237404 ps
CPU time 277.2 seconds
Started Apr 28 01:00:01 PM PDT 24
Finished Apr 28 01:04:39 PM PDT 24
Peak memory 1107368 kb
Host smart-71cef7d1-35f8-47fe-af10-2f5fed028051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096572665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.1096572665
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.1920913436
Short name T1082
Test name
Test status
Simulation time 1914521347 ps
CPU time 6.28 seconds
Started Apr 28 01:00:01 PM PDT 24
Finished Apr 28 01:00:08 PM PDT 24
Peak memory 204044 kb
Host smart-30fc93df-1a09-40ba-95b8-1fb78f36818f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920913436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1920913436
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.1177297611
Short name T63
Test name
Test status
Simulation time 6102992011 ps
CPU time 14.06 seconds
Started Apr 28 12:59:59 PM PDT 24
Finished Apr 28 01:00:14 PM PDT 24
Peak memory 292688 kb
Host smart-62fb0654-8808-4fa8-8f6a-5fda2f8d3807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177297611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.1177297611
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.2153055865
Short name T1280
Test name
Test status
Simulation time 43704631 ps
CPU time 0.68 seconds
Started Apr 28 12:59:58 PM PDT 24
Finished Apr 28 01:00:00 PM PDT 24
Peak memory 203852 kb
Host smart-68c38ab9-6453-4024-939b-9951dc7245c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153055865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.2153055865
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.1624825306
Short name T963
Test name
Test status
Simulation time 1124653633 ps
CPU time 2.26 seconds
Started Apr 28 12:59:54 PM PDT 24
Finished Apr 28 12:59:57 PM PDT 24
Peak memory 220420 kb
Host smart-775e6f1b-d6d8-47f8-81a1-5b228ea4d1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624825306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.1624825306
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.1097076348
Short name T1029
Test name
Test status
Simulation time 9152993218 ps
CPU time 51.97 seconds
Started Apr 28 12:59:54 PM PDT 24
Finished Apr 28 01:00:47 PM PDT 24
Peak memory 317732 kb
Host smart-8e653930-b61f-4579-b6bc-c4a3544e8556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097076348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1097076348
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.1461989501
Short name T195
Test name
Test status
Simulation time 1741331948 ps
CPU time 27.93 seconds
Started Apr 28 12:59:55 PM PDT 24
Finished Apr 28 01:00:24 PM PDT 24
Peak memory 282236 kb
Host smart-ced808f9-ca42-45af-a28a-9456b784c057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461989501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.1461989501
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.3560248794
Short name T257
Test name
Test status
Simulation time 1801751345 ps
CPU time 21.14 seconds
Started Apr 28 12:59:57 PM PDT 24
Finished Apr 28 01:00:19 PM PDT 24
Peak memory 212376 kb
Host smart-3343e614-c33c-4475-ae9d-50eaefa63305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560248794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3560248794
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.78116211
Short name T515
Test name
Test status
Simulation time 2785245928 ps
CPU time 3.53 seconds
Started Apr 28 01:00:01 PM PDT 24
Finished Apr 28 01:00:05 PM PDT 24
Peak memory 204240 kb
Host smart-912b04d5-fcfa-4f81-8e9b-6b41befa63dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78116211 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_bad_addr.78116211
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.4240987966
Short name T899
Test name
Test status
Simulation time 10664283652 ps
CPU time 5.16 seconds
Started Apr 28 12:59:57 PM PDT 24
Finished Apr 28 01:00:03 PM PDT 24
Peak memory 228112 kb
Host smart-47bcfa2c-33a0-43cb-aef5-0985103ac4b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240987966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.4240987966
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.2308653133
Short name T1109
Test name
Test status
Simulation time 10082792153 ps
CPU time 79.49 seconds
Started Apr 28 01:00:01 PM PDT 24
Finished Apr 28 01:01:21 PM PDT 24
Peak memory 567084 kb
Host smart-7e920961-d857-4e98-abd2-eee7b5bd325a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308653133 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.2308653133
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.18420090
Short name T280
Test name
Test status
Simulation time 2595826747 ps
CPU time 2.68 seconds
Started Apr 28 01:00:03 PM PDT 24
Finished Apr 28 01:00:06 PM PDT 24
Peak memory 204136 kb
Host smart-c3f3905e-d91e-4b90-8f07-279a71ed963d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18420090 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.i2c_target_hrst.18420090
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.3918127609
Short name T1120
Test name
Test status
Simulation time 827114223 ps
CPU time 4.17 seconds
Started Apr 28 12:59:56 PM PDT 24
Finished Apr 28 01:00:01 PM PDT 24
Peak memory 204056 kb
Host smart-b54713d5-ba9d-49f3-8114-f7f4aa6ec967
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918127609 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.3918127609
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.4125390855
Short name T1313
Test name
Test status
Simulation time 17088960137 ps
CPU time 250.87 seconds
Started Apr 28 12:59:56 PM PDT 24
Finished Apr 28 01:04:07 PM PDT 24
Peak memory 2512668 kb
Host smart-0c2662b0-a9c5-4994-880e-71e9bd9f31dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125390855 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.4125390855
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1466248193
Short name T106
Test name
Test status
Simulation time 1337358214 ps
CPU time 48.34 seconds
Started Apr 28 12:59:55 PM PDT 24
Finished Apr 28 01:00:44 PM PDT 24
Peak memory 204036 kb
Host smart-88ea06a7-78c2-40b2-8f62-6bf8d9074ab7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466248193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1466248193
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.3960258230
Short name T154
Test name
Test status
Simulation time 14345398042 ps
CPU time 18.27 seconds
Started Apr 28 12:59:55 PM PDT 24
Finished Apr 28 01:00:14 PM PDT 24
Peak memory 216320 kb
Host smart-448934c6-17be-421c-8a13-267171535f93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960258230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.3960258230
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.3329735803
Short name T124
Test name
Test status
Simulation time 48451749947 ps
CPU time 349.36 seconds
Started Apr 28 12:59:54 PM PDT 24
Finished Apr 28 01:05:44 PM PDT 24
Peak memory 3497984 kb
Host smart-115c4246-01dc-4350-aab2-3f860613ed7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329735803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.3329735803
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.406545491
Short name T263
Test name
Test status
Simulation time 28491497116 ps
CPU time 106.98 seconds
Started Apr 28 12:59:56 PM PDT 24
Finished Apr 28 01:01:44 PM PDT 24
Peak memory 440892 kb
Host smart-dce8f02f-bd5f-4379-8bd9-cbca10d7dec9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406545491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_t
arget_stretch.406545491
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.983468930
Short name T725
Test name
Test status
Simulation time 4546569085 ps
CPU time 6.23 seconds
Started Apr 28 12:59:58 PM PDT 24
Finished Apr 28 01:00:05 PM PDT 24
Peak memory 204312 kb
Host smart-dbca83a6-1b26-4d3f-89c1-36bd6f41a584
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983468930 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_timeout.983468930
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_unexp_stop.2035670959
Short name T645
Test name
Test status
Simulation time 3938123911 ps
CPU time 4.78 seconds
Started Apr 28 12:59:57 PM PDT 24
Finished Apr 28 01:00:02 PM PDT 24
Peak memory 206992 kb
Host smart-26ad5416-b40f-4780-94f4-be71567946cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035670959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.i2c_target_unexp_stop.2035670959
Directory /workspace/15.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/16.i2c_alert_test.561013574
Short name T448
Test name
Test status
Simulation time 40626492 ps
CPU time 0.61 seconds
Started Apr 28 01:00:07 PM PDT 24
Finished Apr 28 01:00:09 PM PDT 24
Peak memory 203888 kb
Host smart-98267b01-3f6a-4e5d-9644-12b87e1615af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561013574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.561013574
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.625861094
Short name T1332
Test name
Test status
Simulation time 394079938 ps
CPU time 1.29 seconds
Started Apr 28 01:00:07 PM PDT 24
Finished Apr 28 01:00:09 PM PDT 24
Peak memory 212300 kb
Host smart-2c2cdd2b-144e-476f-aa8c-ae755f6c8a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625861094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.625861094
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.1236848340
Short name T1303
Test name
Test status
Simulation time 278647787 ps
CPU time 5.32 seconds
Started Apr 28 01:00:00 PM PDT 24
Finished Apr 28 01:00:06 PM PDT 24
Peak memory 260604 kb
Host smart-4d1fcb05-4889-4dcf-bd13-27fd1ffdff06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236848340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.1236848340
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2893105
Short name T630
Test name
Test status
Simulation time 2275022554 ps
CPU time 78.39 seconds
Started Apr 28 01:00:00 PM PDT 24
Finished Apr 28 01:01:19 PM PDT 24
Peak memory 727072 kb
Host smart-3ce082d5-bc1f-459a-a2a1-2eb143a21df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2893105
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.1815683672
Short name T945
Test name
Test status
Simulation time 10920213481 ps
CPU time 53.49 seconds
Started Apr 28 01:00:03 PM PDT 24
Finished Apr 28 01:00:57 PM PDT 24
Peak memory 639256 kb
Host smart-f95d1d2c-f3c2-4304-bb59-a3a357fe207f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815683672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.1815683672
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.2582142921
Short name T1078
Test name
Test status
Simulation time 129789430 ps
CPU time 1.06 seconds
Started Apr 28 01:00:01 PM PDT 24
Finished Apr 28 01:00:03 PM PDT 24
Peak memory 204156 kb
Host smart-77f8b9bd-188f-4e6b-87eb-d4c9224ef267
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582142921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.2582142921
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.3261855446
Short name T773
Test name
Test status
Simulation time 506101380 ps
CPU time 7.37 seconds
Started Apr 28 01:00:00 PM PDT 24
Finished Apr 28 01:00:08 PM PDT 24
Peak memory 224252 kb
Host smart-0f43a5eb-1680-4d9d-9552-62b4cc430f4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261855446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.3261855446
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.496783634
Short name T820
Test name
Test status
Simulation time 14918274270 ps
CPU time 218.75 seconds
Started Apr 28 01:00:01 PM PDT 24
Finished Apr 28 01:03:40 PM PDT 24
Peak memory 985312 kb
Host smart-81427a2f-8353-4890-a127-65ea900ba33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496783634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.496783634
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.1200882986
Short name T528
Test name
Test status
Simulation time 516143119 ps
CPU time 8.07 seconds
Started Apr 28 01:00:08 PM PDT 24
Finished Apr 28 01:00:17 PM PDT 24
Peak memory 204172 kb
Host smart-3b97f18f-a67e-4465-a724-3648c2a01d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200882986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.1200882986
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.989951365
Short name T537
Test name
Test status
Simulation time 1279233871 ps
CPU time 19.68 seconds
Started Apr 28 01:00:07 PM PDT 24
Finished Apr 28 01:00:27 PM PDT 24
Peak memory 295244 kb
Host smart-319f4810-e4b5-4f17-85fa-b47f2b886a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989951365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.989951365
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.3089168196
Short name T621
Test name
Test status
Simulation time 46762674 ps
CPU time 0.72 seconds
Started Apr 28 01:00:00 PM PDT 24
Finished Apr 28 01:00:02 PM PDT 24
Peak memory 203856 kb
Host smart-b0bb1174-2d9b-4160-adfa-43ab944d7c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089168196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.3089168196
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.1389731384
Short name T221
Test name
Test status
Simulation time 3687327511 ps
CPU time 9.97 seconds
Started Apr 28 01:00:01 PM PDT 24
Finished Apr 28 01:00:12 PM PDT 24
Peak memory 236784 kb
Host smart-eb012fbd-8c0a-43f1-b2c3-067ae5f1e8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389731384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.1389731384
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.858521539
Short name T880
Test name
Test status
Simulation time 6072829305 ps
CPU time 67.91 seconds
Started Apr 28 01:00:02 PM PDT 24
Finished Apr 28 01:01:10 PM PDT 24
Peak memory 351360 kb
Host smart-97a23b63-a3a1-4c62-a26e-d3952a41ad7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858521539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.858521539
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.1710692755
Short name T1287
Test name
Test status
Simulation time 809021240 ps
CPU time 10.19 seconds
Started Apr 28 01:00:01 PM PDT 24
Finished Apr 28 01:00:12 PM PDT 24
Peak memory 228532 kb
Host smart-90ca1f60-4429-44dd-b0c3-9a8c55bc8639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710692755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.1710692755
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.1424799477
Short name T970
Test name
Test status
Simulation time 859724804 ps
CPU time 3.61 seconds
Started Apr 28 01:00:07 PM PDT 24
Finished Apr 28 01:00:11 PM PDT 24
Peak memory 204088 kb
Host smart-cd559b50-9d4d-47de-810c-c5fd6e0c33dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424799477 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.1424799477
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.1176603383
Short name T569
Test name
Test status
Simulation time 10219339174 ps
CPU time 13.36 seconds
Started Apr 28 01:00:05 PM PDT 24
Finished Apr 28 01:00:19 PM PDT 24
Peak memory 254292 kb
Host smart-668b911c-ceab-429d-82ce-735195cfcea2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176603383 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.1176603383
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.409586974
Short name T886
Test name
Test status
Simulation time 10036064666 ps
CPU time 70.09 seconds
Started Apr 28 01:00:05 PM PDT 24
Finished Apr 28 01:01:16 PM PDT 24
Peak memory 471312 kb
Host smart-e41d5488-616c-45ed-b999-8607cd5d6d68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409586974 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_fifo_reset_tx.409586974
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.666762309
Short name T26
Test name
Test status
Simulation time 469184838 ps
CPU time 2.49 seconds
Started Apr 28 01:00:14 PM PDT 24
Finished Apr 28 01:00:17 PM PDT 24
Peak memory 204072 kb
Host smart-065a1103-cd7f-428f-819a-283a5d0a16bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666762309 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.i2c_target_hrst.666762309
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.565471576
Short name T267
Test name
Test status
Simulation time 2927404382 ps
CPU time 3.95 seconds
Started Apr 28 01:00:07 PM PDT 24
Finished Apr 28 01:00:11 PM PDT 24
Peak memory 206400 kb
Host smart-e0ff04ff-aec4-4c5b-ba9a-8ddcfeeba25a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565471576 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_intr_smoke.565471576
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3074029810
Short name T464
Test name
Test status
Simulation time 2458708758 ps
CPU time 17.93 seconds
Started Apr 28 01:00:10 PM PDT 24
Finished Apr 28 01:00:28 PM PDT 24
Peak memory 734740 kb
Host smart-d56880b9-4886-47df-83a0-bfaa6a710786
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074029810 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3074029810
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.2805463869
Short name T525
Test name
Test status
Simulation time 4808630076 ps
CPU time 15.06 seconds
Started Apr 28 01:00:05 PM PDT 24
Finished Apr 28 01:00:20 PM PDT 24
Peak memory 204164 kb
Host smart-9d703f0b-a9ea-4cdc-ae69-ee064fc5b453
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805463869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.2805463869
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.2922006840
Short name T1152
Test name
Test status
Simulation time 14129719021 ps
CPU time 19.52 seconds
Started Apr 28 01:00:14 PM PDT 24
Finished Apr 28 01:00:34 PM PDT 24
Peak memory 231092 kb
Host smart-f9c47aa7-69a1-4ef4-8694-0c76185041ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922006840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.2922006840
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.4259297043
Short name T753
Test name
Test status
Simulation time 63683527837 ps
CPU time 730.26 seconds
Started Apr 28 01:00:06 PM PDT 24
Finished Apr 28 01:12:17 PM PDT 24
Peak memory 5443588 kb
Host smart-e3699acd-d380-4d2f-a6dd-4cb215c0db01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259297043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.4259297043
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.1389343040
Short name T1351
Test name
Test status
Simulation time 26197195199 ps
CPU time 2786.11 seconds
Started Apr 28 01:00:07 PM PDT 24
Finished Apr 28 01:46:34 PM PDT 24
Peak memory 4605112 kb
Host smart-b2672a8c-fc23-49ee-8ad6-1bb7570efe91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389343040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.1389343040
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.1138098941
Short name T1218
Test name
Test status
Simulation time 5649669293 ps
CPU time 6.32 seconds
Started Apr 28 01:00:08 PM PDT 24
Finished Apr 28 01:00:15 PM PDT 24
Peak memory 212472 kb
Host smart-60d9009e-2ba4-434c-bf49-876da2cd4c48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138098941 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.1138098941
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.783080762
Short name T391
Test name
Test status
Simulation time 39467395 ps
CPU time 0.62 seconds
Started Apr 28 01:00:16 PM PDT 24
Finished Apr 28 01:00:17 PM PDT 24
Peak memory 203732 kb
Host smart-4a0b0266-ad32-4e21-a691-a584b9b5fe25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783080762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.783080762
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.1524754607
Short name T635
Test name
Test status
Simulation time 338312049 ps
CPU time 1.53 seconds
Started Apr 28 01:00:13 PM PDT 24
Finished Apr 28 01:00:15 PM PDT 24
Peak memory 212476 kb
Host smart-c259f891-0adf-4d74-8e7b-7429a3d6ad0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524754607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.1524754607
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.1509314173
Short name T1095
Test name
Test status
Simulation time 212370284 ps
CPU time 9.78 seconds
Started Apr 28 01:00:10 PM PDT 24
Finished Apr 28 01:00:21 PM PDT 24
Peak memory 238484 kb
Host smart-2a9c415d-c918-4f7f-a27e-340f3de9981f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509314173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.1509314173
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.311326015
Short name T514
Test name
Test status
Simulation time 5715163627 ps
CPU time 27.73 seconds
Started Apr 28 01:00:10 PM PDT 24
Finished Apr 28 01:00:38 PM PDT 24
Peak memory 372316 kb
Host smart-cfd69626-e9ee-4728-ac65-897807996e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311326015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.311326015
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.2549105874
Short name T745
Test name
Test status
Simulation time 1471262115 ps
CPU time 48.81 seconds
Started Apr 28 01:00:09 PM PDT 24
Finished Apr 28 01:00:58 PM PDT 24
Peak memory 565572 kb
Host smart-4221335e-0513-4fc7-a25b-622fc2a93499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549105874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2549105874
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.3178209791
Short name T1203
Test name
Test status
Simulation time 154776531 ps
CPU time 0.85 seconds
Started Apr 28 01:00:09 PM PDT 24
Finished Apr 28 01:00:10 PM PDT 24
Peak memory 203860 kb
Host smart-e31bfadb-2b66-4ac3-85ad-df3f30ceb254
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178209791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.3178209791
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.3153174007
Short name T924
Test name
Test status
Simulation time 2709865974 ps
CPU time 4.92 seconds
Started Apr 28 01:00:09 PM PDT 24
Finished Apr 28 01:00:14 PM PDT 24
Peak memory 236440 kb
Host smart-0bed908b-250b-4450-a9e0-77171a6226f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153174007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.3153174007
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.2369820364
Short name T1103
Test name
Test status
Simulation time 4812724198 ps
CPU time 153.63 seconds
Started Apr 28 01:00:12 PM PDT 24
Finished Apr 28 01:02:46 PM PDT 24
Peak memory 803264 kb
Host smart-f002a6dc-8532-417a-835a-0fdcb3bc56a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369820364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2369820364
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.926669712
Short name T1040
Test name
Test status
Simulation time 901315653 ps
CPU time 9.29 seconds
Started Apr 28 01:00:19 PM PDT 24
Finished Apr 28 01:00:29 PM PDT 24
Peak memory 203336 kb
Host smart-69f6b0ba-33e0-425a-a8df-111fa2ecdabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926669712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.926669712
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.1991643187
Short name T652
Test name
Test status
Simulation time 1639176597 ps
CPU time 26.08 seconds
Started Apr 28 01:00:18 PM PDT 24
Finished Apr 28 01:00:44 PM PDT 24
Peak memory 349224 kb
Host smart-7c4b774c-990f-4c6c-aa2a-508f591224ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991643187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.1991643187
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.3531923058
Short name T1364
Test name
Test status
Simulation time 204546516 ps
CPU time 0.66 seconds
Started Apr 28 01:00:07 PM PDT 24
Finished Apr 28 01:00:09 PM PDT 24
Peak memory 203744 kb
Host smart-2f04eade-b77a-4ac8-8ab3-7ffd951e6fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531923058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.3531923058
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.1601971987
Short name T68
Test name
Test status
Simulation time 558322592 ps
CPU time 26.18 seconds
Started Apr 28 01:00:11 PM PDT 24
Finished Apr 28 01:00:38 PM PDT 24
Peak memory 293280 kb
Host smart-5e9a76c3-0d8c-43df-9171-1f5288374296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601971987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.1601971987
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.3908409435
Short name T261
Test name
Test status
Simulation time 1080912570 ps
CPU time 17.5 seconds
Started Apr 28 01:00:14 PM PDT 24
Finished Apr 28 01:00:32 PM PDT 24
Peak memory 300412 kb
Host smart-7769341a-a329-4e1a-9fa1-4f45ddf155c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908409435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3908409435
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.2754731609
Short name T1107
Test name
Test status
Simulation time 1010043231 ps
CPU time 42.21 seconds
Started Apr 28 01:00:10 PM PDT 24
Finished Apr 28 01:00:53 PM PDT 24
Peak memory 213564 kb
Host smart-de7893f0-8cdc-4900-abee-aed6388a6737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754731609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.2754731609
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.449520054
Short name T643
Test name
Test status
Simulation time 2889286058 ps
CPU time 3.19 seconds
Started Apr 28 01:00:17 PM PDT 24
Finished Apr 28 01:00:21 PM PDT 24
Peak memory 204204 kb
Host smart-fb60397b-ab0a-4da4-8e1e-f8921cb4df5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449520054 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.449520054
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.1748618481
Short name T1126
Test name
Test status
Simulation time 10524290969 ps
CPU time 8.2 seconds
Started Apr 28 01:00:14 PM PDT 24
Finished Apr 28 01:00:23 PM PDT 24
Peak memory 233592 kb
Host smart-eddf289b-78ad-4249-a280-aa81683f86a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748618481 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.1748618481
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.659920660
Short name T605
Test name
Test status
Simulation time 10282068554 ps
CPU time 9.23 seconds
Started Apr 28 01:00:15 PM PDT 24
Finished Apr 28 01:00:24 PM PDT 24
Peak memory 249732 kb
Host smart-3a93a396-6cf0-402c-a7c3-9acee3b8579d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659920660 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_fifo_reset_tx.659920660
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.3225097463
Short name T14
Test name
Test status
Simulation time 618071251 ps
CPU time 2.72 seconds
Started Apr 28 01:00:18 PM PDT 24
Finished Apr 28 01:00:21 PM PDT 24
Peak memory 204196 kb
Host smart-b8dd8118-fd77-4209-98ff-4266f85eeb66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225097463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.3225097463
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.1022861998
Short name T1257
Test name
Test status
Simulation time 761017200 ps
CPU time 4.23 seconds
Started Apr 28 01:00:12 PM PDT 24
Finished Apr 28 01:00:17 PM PDT 24
Peak memory 204192 kb
Host smart-1344bdd4-7de5-4a98-9043-7bcc6643a803
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022861998 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.1022861998
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.4034921113
Short name T1012
Test name
Test status
Simulation time 8500887388 ps
CPU time 5.64 seconds
Started Apr 28 01:00:13 PM PDT 24
Finished Apr 28 01:00:19 PM PDT 24
Peak memory 204032 kb
Host smart-31327439-3ef0-43ec-bd86-1f37e0c9e521
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034921113 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.4034921113
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.3420164896
Short name T679
Test name
Test status
Simulation time 1339761521 ps
CPU time 11.64 seconds
Started Apr 28 01:00:14 PM PDT 24
Finished Apr 28 01:00:27 PM PDT 24
Peak memory 204072 kb
Host smart-45547261-f529-4fde-b13c-23aea75a1752
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420164896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.3420164896
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.1568154893
Short name T795
Test name
Test status
Simulation time 2812773511 ps
CPU time 56.46 seconds
Started Apr 28 01:00:14 PM PDT 24
Finished Apr 28 01:01:11 PM PDT 24
Peak memory 206544 kb
Host smart-94733784-3da2-4e51-9f74-b66decbf567d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568154893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.1568154893
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.2408117108
Short name T786
Test name
Test status
Simulation time 53086104037 ps
CPU time 1251.24 seconds
Started Apr 28 01:00:13 PM PDT 24
Finished Apr 28 01:21:05 PM PDT 24
Peak memory 8429900 kb
Host smart-6b5592a4-095e-43f5-adaf-81de3696fa34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408117108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.2408117108
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.2776805006
Short name T203
Test name
Test status
Simulation time 29437777829 ps
CPU time 217.17 seconds
Started Apr 28 01:00:12 PM PDT 24
Finished Apr 28 01:03:50 PM PDT 24
Peak memory 1948336 kb
Host smart-e1666dad-7aee-494e-922a-7c6db587567b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776805006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.2776805006
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.3521875627
Short name T570
Test name
Test status
Simulation time 1474696206 ps
CPU time 7.69 seconds
Started Apr 28 01:00:16 PM PDT 24
Finished Apr 28 01:00:24 PM PDT 24
Peak memory 220284 kb
Host smart-5c6c55ec-f1ff-46b0-9ca7-8936676cc911
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521875627 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.3521875627
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.2441122371
Short name T1016
Test name
Test status
Simulation time 19257767 ps
CPU time 0.62 seconds
Started Apr 28 01:00:23 PM PDT 24
Finished Apr 28 01:00:24 PM PDT 24
Peak memory 203788 kb
Host smart-4366e6d8-9a7e-40d0-936e-dc751190a153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441122371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.2441122371
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.634394155
Short name T301
Test name
Test status
Simulation time 225944019 ps
CPU time 1.46 seconds
Started Apr 28 01:00:21 PM PDT 24
Finished Apr 28 01:00:23 PM PDT 24
Peak memory 215944 kb
Host smart-8dc65cbe-77a2-4371-acc7-42d3eb457517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634394155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.634394155
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.264815749
Short name T811
Test name
Test status
Simulation time 989464988 ps
CPU time 4.14 seconds
Started Apr 28 01:00:16 PM PDT 24
Finished Apr 28 01:00:21 PM PDT 24
Peak memory 246636 kb
Host smart-e8164d8e-7945-4aae-8a51-6e43be16b3cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264815749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empt
y.264815749
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.1600990759
Short name T1044
Test name
Test status
Simulation time 6163597167 ps
CPU time 40.64 seconds
Started Apr 28 01:00:19 PM PDT 24
Finished Apr 28 01:01:00 PM PDT 24
Peak memory 543668 kb
Host smart-095f8c46-c24f-4bd9-94e9-477c43d895d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600990759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.1600990759
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.695720006
Short name T1032
Test name
Test status
Simulation time 2083417150 ps
CPU time 75.03 seconds
Started Apr 28 01:00:17 PM PDT 24
Finished Apr 28 01:01:32 PM PDT 24
Peak memory 720272 kb
Host smart-9e794996-68c4-4520-8d2d-1fadb4b01af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695720006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.695720006
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.769864062
Short name T648
Test name
Test status
Simulation time 83523923 ps
CPU time 0.84 seconds
Started Apr 28 01:00:17 PM PDT 24
Finished Apr 28 01:00:18 PM PDT 24
Peak memory 203888 kb
Host smart-0ad38f33-ccc9-4ad6-9d2f-de3471e6c800
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769864062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fm
t.769864062
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.1216808181
Short name T126
Test name
Test status
Simulation time 8570670747 ps
CPU time 117.03 seconds
Started Apr 28 01:00:21 PM PDT 24
Finished Apr 28 01:02:18 PM PDT 24
Peak memory 1269464 kb
Host smart-52dbe493-e5cd-41ed-a7b3-f29271ab4cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216808181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.1216808181
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.975191465
Short name T1049
Test name
Test status
Simulation time 251073242 ps
CPU time 4 seconds
Started Apr 28 01:00:23 PM PDT 24
Finished Apr 28 01:00:28 PM PDT 24
Peak memory 204048 kb
Host smart-037230d5-b7ee-4ef7-a7fe-86fdb16cd1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975191465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.975191465
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.3385187583
Short name T1196
Test name
Test status
Simulation time 3586601955 ps
CPU time 37.75 seconds
Started Apr 28 01:00:22 PM PDT 24
Finished Apr 28 01:01:00 PM PDT 24
Peak memory 285492 kb
Host smart-246514dd-8adb-41fb-8033-ebb7ad0ecdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385187583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.3385187583
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.202660620
Short name T686
Test name
Test status
Simulation time 51138781 ps
CPU time 0.68 seconds
Started Apr 28 01:00:19 PM PDT 24
Finished Apr 28 01:00:20 PM PDT 24
Peak memory 203020 kb
Host smart-fa93b5e4-8c56-4f45-903d-8e4b20e688f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202660620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.202660620
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.1852485706
Short name T1054
Test name
Test status
Simulation time 7199575520 ps
CPU time 254.21 seconds
Started Apr 28 01:00:17 PM PDT 24
Finished Apr 28 01:04:32 PM PDT 24
Peak memory 914804 kb
Host smart-11b9e528-22e2-44d6-8154-c93bbf13ab93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852485706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1852485706
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.2170463202
Short name T1035
Test name
Test status
Simulation time 7461841969 ps
CPU time 35.92 seconds
Started Apr 28 01:00:17 PM PDT 24
Finished Apr 28 01:00:54 PM PDT 24
Peak memory 363056 kb
Host smart-667ed37b-31f3-4bb0-ac93-583c509c3465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170463202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2170463202
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.2763878531
Short name T668
Test name
Test status
Simulation time 48929056610 ps
CPU time 968.03 seconds
Started Apr 28 01:00:20 PM PDT 24
Finished Apr 28 01:16:29 PM PDT 24
Peak memory 1926984 kb
Host smart-fe045dd8-9cee-49ac-b07f-e459499212ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763878531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.2763878531
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.18583554
Short name T95
Test name
Test status
Simulation time 16122112379 ps
CPU time 17.44 seconds
Started Apr 28 01:00:21 PM PDT 24
Finished Apr 28 01:00:39 PM PDT 24
Peak memory 228656 kb
Host smart-2ce97747-85f2-40a6-a8e9-5ec31bcecaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18583554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.18583554
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.3327070844
Short name T1158
Test name
Test status
Simulation time 3461063073 ps
CPU time 3.01 seconds
Started Apr 28 01:00:24 PM PDT 24
Finished Apr 28 01:00:28 PM PDT 24
Peak memory 204168 kb
Host smart-21b84e46-8bb1-4692-9e18-96af9b2d91d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327070844 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.3327070844
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.127820020
Short name T868
Test name
Test status
Simulation time 10114257946 ps
CPU time 78.5 seconds
Started Apr 28 01:00:23 PM PDT 24
Finished Apr 28 01:01:43 PM PDT 24
Peak memory 423816 kb
Host smart-991aefe4-30ab-4b7a-9622-a48cb1aefc6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127820020 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_acq.127820020
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3809669787
Short name T1177
Test name
Test status
Simulation time 10083158347 ps
CPU time 76.81 seconds
Started Apr 28 01:00:21 PM PDT 24
Finished Apr 28 01:01:39 PM PDT 24
Peak memory 559228 kb
Host smart-efe9cea1-5c07-49d8-b448-5b2d8d6f117d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809669787 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3809669787
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.45192565
Short name T286
Test name
Test status
Simulation time 492244668 ps
CPU time 2.83 seconds
Started Apr 28 01:00:21 PM PDT 24
Finished Apr 28 01:00:25 PM PDT 24
Peak memory 204204 kb
Host smart-3ed56135-653d-498c-a198-207a537b6a99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45192565 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.i2c_target_hrst.45192565
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.715365308
Short name T32
Test name
Test status
Simulation time 907285114 ps
CPU time 4.02 seconds
Started Apr 28 01:00:22 PM PDT 24
Finished Apr 28 01:00:26 PM PDT 24
Peak memory 204116 kb
Host smart-099dfc4b-1fff-4820-baaa-42b232214f59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715365308 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_intr_smoke.715365308
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.2906690891
Short name T21
Test name
Test status
Simulation time 11046921294 ps
CPU time 12.58 seconds
Started Apr 28 01:00:23 PM PDT 24
Finished Apr 28 01:00:37 PM PDT 24
Peak memory 354540 kb
Host smart-02810657-19a9-498b-bd73-087b069de6e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906690891 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.2906690891
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.3820536207
Short name T861
Test name
Test status
Simulation time 2614476834 ps
CPU time 10.65 seconds
Started Apr 28 01:00:22 PM PDT 24
Finished Apr 28 01:00:33 PM PDT 24
Peak memory 204168 kb
Host smart-eb7922d9-b9d6-4b9e-bd7e-d7e65b351d41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820536207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.3820536207
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.2715535907
Short name T624
Test name
Test status
Simulation time 1179947708 ps
CPU time 17.4 seconds
Started Apr 28 01:00:21 PM PDT 24
Finished Apr 28 01:00:39 PM PDT 24
Peak memory 218496 kb
Host smart-5d9aa65c-dcb4-4ce4-b426-1debbef89036
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715535907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.2715535907
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.900921294
Short name T814
Test name
Test status
Simulation time 38901770255 ps
CPU time 68.13 seconds
Started Apr 28 01:00:24 PM PDT 24
Finished Apr 28 01:01:33 PM PDT 24
Peak memory 1174188 kb
Host smart-c79b500b-6211-4e8e-9882-a4bbd7d98f97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900921294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_wr.900921294
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.1471592019
Short name T445
Test name
Test status
Simulation time 7395339388 ps
CPU time 24.66 seconds
Started Apr 28 01:00:23 PM PDT 24
Finished Apr 28 01:00:48 PM PDT 24
Peak memory 511440 kb
Host smart-2fe6bcb5-4a33-414f-9cdf-6c5e9093f56c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471592019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.1471592019
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.166913268
Short name T279
Test name
Test status
Simulation time 2843110244 ps
CPU time 6.38 seconds
Started Apr 28 01:00:24 PM PDT 24
Finished Apr 28 01:00:31 PM PDT 24
Peak memory 217952 kb
Host smart-98178e2f-a5e7-4e82-ab91-59fb97e281df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166913268 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_timeout.166913268
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.1740864674
Short name T1018
Test name
Test status
Simulation time 14950468 ps
CPU time 0.61 seconds
Started Apr 28 01:00:32 PM PDT 24
Finished Apr 28 01:00:33 PM PDT 24
Peak memory 203860 kb
Host smart-27debf9d-84fc-4352-bb50-e1c45896833f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740864674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.1740864674
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.1909472371
Short name T1263
Test name
Test status
Simulation time 483129886 ps
CPU time 1.37 seconds
Started Apr 28 01:00:29 PM PDT 24
Finished Apr 28 01:00:31 PM PDT 24
Peak memory 220684 kb
Host smart-2a4b95f8-527b-4f4a-aa9c-aae394248560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909472371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.1909472371
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3685172747
Short name T277
Test name
Test status
Simulation time 638168223 ps
CPU time 30.6 seconds
Started Apr 28 01:00:25 PM PDT 24
Finished Apr 28 01:00:56 PM PDT 24
Peak memory 312896 kb
Host smart-9a61e074-f483-428a-b00a-0ab735f25b79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685172747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.3685172747
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.4289715452
Short name T581
Test name
Test status
Simulation time 1016489810 ps
CPU time 65.57 seconds
Started Apr 28 01:00:26 PM PDT 24
Finished Apr 28 01:01:32 PM PDT 24
Peak memory 453564 kb
Host smart-27f22b84-b680-4eae-8279-f0aa985c5faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289715452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.4289715452
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.2280036482
Short name T313
Test name
Test status
Simulation time 7174403619 ps
CPU time 133.13 seconds
Started Apr 28 01:00:22 PM PDT 24
Finished Apr 28 01:02:36 PM PDT 24
Peak memory 650060 kb
Host smart-ad8bb141-76af-40e0-a643-aaf4d2059063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280036482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.2280036482
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.2638600235
Short name T454
Test name
Test status
Simulation time 111120488 ps
CPU time 0.92 seconds
Started Apr 28 01:00:20 PM PDT 24
Finished Apr 28 01:00:22 PM PDT 24
Peak memory 203952 kb
Host smart-808b92e0-a3af-41f9-ad11-e974984e972c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638600235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.2638600235
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.3297680376
Short name T226
Test name
Test status
Simulation time 547405130 ps
CPU time 2.91 seconds
Started Apr 28 01:00:20 PM PDT 24
Finished Apr 28 01:00:24 PM PDT 24
Peak memory 204176 kb
Host smart-9022212b-4947-4ead-bd05-3317ea5fbc77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297680376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.3297680376
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.3474945081
Short name T1065
Test name
Test status
Simulation time 8941939561 ps
CPU time 145.42 seconds
Started Apr 28 01:00:22 PM PDT 24
Finished Apr 28 01:02:48 PM PDT 24
Peak memory 1317860 kb
Host smart-4af26510-856c-4b71-b62c-0bfc4b8eef0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474945081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3474945081
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.1251937080
Short name T1266
Test name
Test status
Simulation time 495697473 ps
CPU time 21.22 seconds
Started Apr 28 01:00:32 PM PDT 24
Finished Apr 28 01:00:54 PM PDT 24
Peak memory 204180 kb
Host smart-5d652fdc-2139-49b8-b73a-6ceafbe7a819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251937080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.1251937080
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_override.3889290004
Short name T342
Test name
Test status
Simulation time 26920667 ps
CPU time 0.62 seconds
Started Apr 28 01:00:21 PM PDT 24
Finished Apr 28 01:00:22 PM PDT 24
Peak memory 203860 kb
Host smart-c06c0ad3-2e36-4dfc-9001-8df129a03352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889290004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.3889290004
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.2508946511
Short name T636
Test name
Test status
Simulation time 5901031346 ps
CPU time 80.33 seconds
Started Apr 28 01:00:26 PM PDT 24
Finished Apr 28 01:01:47 PM PDT 24
Peak memory 765704 kb
Host smart-11b5a349-1977-4957-a697-2eea022c7321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508946511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.2508946511
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2452969073
Short name T828
Test name
Test status
Simulation time 1261243480 ps
CPU time 21.34 seconds
Started Apr 28 01:00:23 PM PDT 24
Finished Apr 28 01:00:45 PM PDT 24
Peak memory 346616 kb
Host smart-5e4e0ddf-a09b-439f-9702-986cf866434b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452969073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2452969073
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.451261565
Short name T1198
Test name
Test status
Simulation time 11892612361 ps
CPU time 589.27 seconds
Started Apr 28 01:00:28 PM PDT 24
Finished Apr 28 01:10:18 PM PDT 24
Peak memory 2869832 kb
Host smart-2d670ed6-2716-4370-938d-b531e4a80919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451261565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.451261565
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.1582399139
Short name T1354
Test name
Test status
Simulation time 818437803 ps
CPU time 11.74 seconds
Started Apr 28 01:00:27 PM PDT 24
Finished Apr 28 01:00:39 PM PDT 24
Peak memory 220284 kb
Host smart-783e506a-66db-4dc4-a420-c9aa46f8f927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582399139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.1582399139
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.3674161669
Short name T1085
Test name
Test status
Simulation time 736271980 ps
CPU time 3.48 seconds
Started Apr 28 01:00:28 PM PDT 24
Finished Apr 28 01:00:32 PM PDT 24
Peak memory 212332 kb
Host smart-3eac6de6-9109-4438-b940-0fcb4958075a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674161669 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.3674161669
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.522569041
Short name T467
Test name
Test status
Simulation time 10054654876 ps
CPU time 64.35 seconds
Started Apr 28 01:00:28 PM PDT 24
Finished Apr 28 01:01:33 PM PDT 24
Peak memory 490896 kb
Host smart-016a6b16-5326-40ce-9610-79834e0500e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522569041 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_acq.522569041
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.1112831705
Short name T37
Test name
Test status
Simulation time 10294168107 ps
CPU time 11.32 seconds
Started Apr 28 01:00:28 PM PDT 24
Finished Apr 28 01:00:40 PM PDT 24
Peak memory 286916 kb
Host smart-cdc1618a-73a8-4ec2-9d35-2da5aa44ecc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112831705 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.1112831705
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.1945615839
Short name T233
Test name
Test status
Simulation time 403191030 ps
CPU time 2.26 seconds
Started Apr 28 01:00:27 PM PDT 24
Finished Apr 28 01:00:29 PM PDT 24
Peak memory 204212 kb
Host smart-08749477-1749-4a5b-91be-9ea8764d8792
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945615839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.1945615839
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.3026551136
Short name T931
Test name
Test status
Simulation time 1766830328 ps
CPU time 4.5 seconds
Started Apr 28 01:00:28 PM PDT 24
Finished Apr 28 01:00:33 PM PDT 24
Peak memory 204204 kb
Host smart-391767f0-7576-4a95-b9c8-5f3da8973905
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026551136 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.3026551136
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.2914753016
Short name T483
Test name
Test status
Simulation time 4779806887 ps
CPU time 3.3 seconds
Started Apr 28 01:00:28 PM PDT 24
Finished Apr 28 01:00:32 PM PDT 24
Peak memory 204224 kb
Host smart-8733cf88-5990-4a26-a201-e0180632dc7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914753016 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.2914753016
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.271857979
Short name T639
Test name
Test status
Simulation time 752223496 ps
CPU time 9.36 seconds
Started Apr 28 01:00:29 PM PDT 24
Finished Apr 28 01:00:39 PM PDT 24
Peak memory 203944 kb
Host smart-5e911c45-3158-4ca1-9c81-1e80e8f17a6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271857979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_tar
get_smoke.271857979
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.1642350986
Short name T800
Test name
Test status
Simulation time 454375595 ps
CPU time 8.12 seconds
Started Apr 28 01:00:27 PM PDT 24
Finished Apr 28 01:00:36 PM PDT 24
Peak memory 204172 kb
Host smart-3bafe50a-8385-4480-bb4c-475248ebca99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642350986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.1642350986
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.377827694
Short name T1227
Test name
Test status
Simulation time 27379851824 ps
CPU time 6.28 seconds
Started Apr 28 01:00:28 PM PDT 24
Finished Apr 28 01:00:34 PM PDT 24
Peak memory 204300 kb
Host smart-f063d61b-7238-4245-b1f0-3d0c1c562e2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377827694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c
_target_stress_wr.377827694
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.1443242016
Short name T908
Test name
Test status
Simulation time 32927912906 ps
CPU time 2080.87 seconds
Started Apr 28 01:00:28 PM PDT 24
Finished Apr 28 01:35:10 PM PDT 24
Peak memory 7835340 kb
Host smart-d85f9d94-63ab-4e34-a974-a02b0270ec00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443242016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.1443242016
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.1382525807
Short name T711
Test name
Test status
Simulation time 1201595482 ps
CPU time 6.74 seconds
Started Apr 28 01:00:28 PM PDT 24
Finished Apr 28 01:00:36 PM PDT 24
Peak memory 212300 kb
Host smart-931646d2-aaf1-4a89-af8f-63e1f8830767
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382525807 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.1382525807
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.3067068318
Short name T1062
Test name
Test status
Simulation time 41881345 ps
CPU time 0.62 seconds
Started Apr 28 12:59:07 PM PDT 24
Finished Apr 28 12:59:09 PM PDT 24
Peak memory 203848 kb
Host smart-b5d8cc8f-c393-4e88-a0e3-f90f7e531db8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067068318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.3067068318
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.2036966582
Short name T406
Test name
Test status
Simulation time 280771815 ps
CPU time 1.42 seconds
Started Apr 28 12:58:55 PM PDT 24
Finished Apr 28 12:58:58 PM PDT 24
Peak memory 212448 kb
Host smart-5d1a1b2e-e5f0-4201-8474-7f72616e2ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036966582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.2036966582
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1117831313
Short name T392
Test name
Test status
Simulation time 254531223 ps
CPU time 12.82 seconds
Started Apr 28 12:58:57 PM PDT 24
Finished Apr 28 12:59:11 PM PDT 24
Peak memory 252628 kb
Host smart-f5a65b52-c776-4c84-9724-4c5ae7670e39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117831313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1117831313
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.1070172470
Short name T1030
Test name
Test status
Simulation time 2412677942 ps
CPU time 75.21 seconds
Started Apr 28 12:59:09 PM PDT 24
Finished Apr 28 01:00:28 PM PDT 24
Peak memory 470940 kb
Host smart-3493e269-b764-4a32-a5a3-50f723ee93df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070172470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.1070172470
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.1302637887
Short name T926
Test name
Test status
Simulation time 6565207358 ps
CPU time 44.51 seconds
Started Apr 28 12:58:56 PM PDT 24
Finished Apr 28 12:59:41 PM PDT 24
Peak memory 597668 kb
Host smart-834c06cd-9792-42fa-bad2-0f9e8030f8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302637887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.1302637887
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.1345160854
Short name T1207
Test name
Test status
Simulation time 114986489 ps
CPU time 1 seconds
Started Apr 28 12:59:02 PM PDT 24
Finished Apr 28 12:59:05 PM PDT 24
Peak memory 203808 kb
Host smart-47529adb-4323-4382-9dfb-9d8175bbf6ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345160854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.1345160854
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.2726200135
Short name T1
Test name
Test status
Simulation time 157316804 ps
CPU time 3.38 seconds
Started Apr 28 12:59:00 PM PDT 24
Finished Apr 28 12:59:04 PM PDT 24
Peak memory 204116 kb
Host smart-54c9ae05-048a-49cc-b704-60e7b1c7f827
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726200135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
2726200135
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.3746051038
Short name T182
Test name
Test status
Simulation time 7279264793 ps
CPU time 89.5 seconds
Started Apr 28 12:58:56 PM PDT 24
Finished Apr 28 01:00:27 PM PDT 24
Peak memory 1111028 kb
Host smart-0089c18d-ee1f-47d9-a5d0-55f965529b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746051038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.3746051038
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.1956861852
Short name T1187
Test name
Test status
Simulation time 201309899 ps
CPU time 8.11 seconds
Started Apr 28 12:59:12 PM PDT 24
Finished Apr 28 12:59:24 PM PDT 24
Peak memory 203980 kb
Host smart-e8a7b805-b74d-483c-af9a-14aff2fed357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956861852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.1956861852
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.1513890438
Short name T457
Test name
Test status
Simulation time 1626382409 ps
CPU time 30.8 seconds
Started Apr 28 12:59:02 PM PDT 24
Finished Apr 28 12:59:34 PM PDT 24
Peak memory 309812 kb
Host smart-96f2ef98-b08c-44d2-a31e-1b251c75a4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513890438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.1513890438
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.1019325028
Short name T207
Test name
Test status
Simulation time 28490306 ps
CPU time 0.7 seconds
Started Apr 28 12:59:01 PM PDT 24
Finished Apr 28 12:59:03 PM PDT 24
Peak memory 203720 kb
Host smart-c4f4b794-01f8-453c-bf65-581ccc147f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019325028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1019325028
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.1516635587
Short name T1224
Test name
Test status
Simulation time 20412914119 ps
CPU time 133.49 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 01:01:18 PM PDT 24
Peak memory 909092 kb
Host smart-01afdc84-777a-47b3-bf46-b82f58d18678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516635587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.1516635587
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.721029418
Short name T895
Test name
Test status
Simulation time 20517489741 ps
CPU time 83.59 seconds
Started Apr 28 12:58:54 PM PDT 24
Finished Apr 28 01:00:18 PM PDT 24
Peak memory 426424 kb
Host smart-9f38bae9-6c31-46ee-bb89-e0c840664d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721029418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.721029418
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.1976268453
Short name T1289
Test name
Test status
Simulation time 52816589763 ps
CPU time 376.49 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 01:05:21 PM PDT 24
Peak memory 1554036 kb
Host smart-6aa2222d-99b4-42ff-9a05-5ab129f9d66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976268453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.1976268453
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.1657122228
Short name T120
Test name
Test status
Simulation time 3430406760 ps
CPU time 38.89 seconds
Started Apr 28 12:59:02 PM PDT 24
Finished Apr 28 12:59:43 PM PDT 24
Peak memory 220280 kb
Host smart-767e9798-d08d-4a8b-b49f-125d2fb6c107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657122228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.1657122228
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2991348822
Short name T114
Test name
Test status
Simulation time 76252740 ps
CPU time 0.84 seconds
Started Apr 28 12:58:56 PM PDT 24
Finished Apr 28 12:58:58 PM PDT 24
Peak memory 221364 kb
Host smart-00004588-229a-4b92-b50b-8a6d37739281
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991348822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2991348822
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.4111827218
Short name T1153
Test name
Test status
Simulation time 2589803320 ps
CPU time 3.54 seconds
Started Apr 28 12:59:02 PM PDT 24
Finished Apr 28 12:59:07 PM PDT 24
Peak memory 204224 kb
Host smart-5ac3b318-cefa-4e30-9027-7cc512d96fcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111827218 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.4111827218
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.4004002091
Short name T333
Test name
Test status
Simulation time 10130373009 ps
CPU time 14.78 seconds
Started Apr 28 12:58:55 PM PDT 24
Finished Apr 28 12:59:11 PM PDT 24
Peak memory 277264 kb
Host smart-afbcec9f-fc8c-49fe-895d-10128fff22de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004002091 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.4004002091
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.2678824922
Short name T693
Test name
Test status
Simulation time 677812180 ps
CPU time 2.2 seconds
Started Apr 28 12:58:50 PM PDT 24
Finished Apr 28 12:58:53 PM PDT 24
Peak memory 204172 kb
Host smart-be9e2b86-82ac-4153-815b-2889620d357e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678824922 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.2678824922
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.4085537489
Short name T934
Test name
Test status
Simulation time 2396551265 ps
CPU time 5.96 seconds
Started Apr 28 12:58:59 PM PDT 24
Finished Apr 28 12:59:06 PM PDT 24
Peak memory 218336 kb
Host smart-f1307900-07ac-403e-9d52-7503622b421a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085537489 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.4085537489
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.4004041051
Short name T546
Test name
Test status
Simulation time 20532863688 ps
CPU time 56.13 seconds
Started Apr 28 12:58:56 PM PDT 24
Finished Apr 28 12:59:54 PM PDT 24
Peak memory 911884 kb
Host smart-9904d3f6-503f-43d5-86bd-ff7ec1335888
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004041051 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.4004041051
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.746411408
Short name T985
Test name
Test status
Simulation time 1198207035 ps
CPU time 15.76 seconds
Started Apr 28 12:59:01 PM PDT 24
Finished Apr 28 12:59:17 PM PDT 24
Peak memory 204152 kb
Host smart-dcb4912e-c193-449f-b86f-04081762a22e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746411408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_targ
et_smoke.746411408
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.195922344
Short name T633
Test name
Test status
Simulation time 1544584317 ps
CPU time 13.81 seconds
Started Apr 28 12:59:05 PM PDT 24
Finished Apr 28 12:59:21 PM PDT 24
Peak memory 208560 kb
Host smart-ded38332-6363-4933-8166-0e23f5ce1384
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195922344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_rd.195922344
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.1841136456
Short name T576
Test name
Test status
Simulation time 43106988466 ps
CPU time 689.73 seconds
Started Apr 28 12:59:01 PM PDT 24
Finished Apr 28 01:10:32 PM PDT 24
Peak memory 5801776 kb
Host smart-6d9a2ebe-f621-458e-9861-e74b33064065
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841136456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.1841136456
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.95688210
Short name T352
Test name
Test status
Simulation time 15985178009 ps
CPU time 97.39 seconds
Started Apr 28 12:59:08 PM PDT 24
Finished Apr 28 01:00:47 PM PDT 24
Peak memory 969980 kb
Host smart-8db69d74-83fa-445e-a82a-142c8e8f31b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95688210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_stretch.95688210
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.1782163850
Short name T1217
Test name
Test status
Simulation time 5537955311 ps
CPU time 6.59 seconds
Started Apr 28 12:59:09 PM PDT 24
Finished Apr 28 12:59:18 PM PDT 24
Peak memory 204300 kb
Host smart-0d1e75d7-ef05-47e5-9f02-651500412e41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782163850 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.1782163850
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_unexp_stop.2763113371
Short name T511
Test name
Test status
Simulation time 3132405860 ps
CPU time 4.18 seconds
Started Apr 28 12:58:54 PM PDT 24
Finished Apr 28 12:58:59 PM PDT 24
Peak memory 205528 kb
Host smart-41021d3b-7f7e-4ade-819b-2bd7990fff4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763113371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.i2c_target_unexp_stop.2763113371
Directory /workspace/2.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1533432068
Short name T541
Test name
Test status
Simulation time 17218753 ps
CPU time 0.6 seconds
Started Apr 28 01:00:37 PM PDT 24
Finished Apr 28 01:00:38 PM PDT 24
Peak memory 203924 kb
Host smart-1493a901-3f65-43c9-8375-2156d6c1378e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533432068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1533432068
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.913268959
Short name T1248
Test name
Test status
Simulation time 125405897 ps
CPU time 1.46 seconds
Started Apr 28 01:00:36 PM PDT 24
Finished Apr 28 01:00:39 PM PDT 24
Peak memory 212476 kb
Host smart-9475265a-b227-4520-889e-4cfb1673a5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913268959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.913268959
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.43838874
Short name T614
Test name
Test status
Simulation time 778347463 ps
CPU time 10.18 seconds
Started Apr 28 01:00:36 PM PDT 24
Finished Apr 28 01:00:46 PM PDT 24
Peak memory 234360 kb
Host smart-3878649d-63c0-4439-b7c9-7b31f8e23234
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43838874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empty
.43838874
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.1681720672
Short name T328
Test name
Test status
Simulation time 7829049064 ps
CPU time 46.22 seconds
Started Apr 28 01:00:32 PM PDT 24
Finished Apr 28 01:01:19 PM PDT 24
Peak memory 484664 kb
Host smart-06292fc0-a0e5-40e8-8347-ee19c0ee199f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681720672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.1681720672
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.3095187029
Short name T379
Test name
Test status
Simulation time 4715594909 ps
CPU time 82.09 seconds
Started Apr 28 01:00:33 PM PDT 24
Finished Apr 28 01:01:56 PM PDT 24
Peak memory 507696 kb
Host smart-e473ccda-c0b4-426a-9d19-b0639f5b0e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095187029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3095187029
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.16495966
Short name T502
Test name
Test status
Simulation time 296537024 ps
CPU time 1.15 seconds
Started Apr 28 01:00:37 PM PDT 24
Finished Apr 28 01:00:39 PM PDT 24
Peak memory 204188 kb
Host smart-f4ac12c1-4f33-456a-b6a4-1f88f8947d8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16495966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fmt
.16495966
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.2331469242
Short name T792
Test name
Test status
Simulation time 327612599 ps
CPU time 8.55 seconds
Started Apr 28 01:00:33 PM PDT 24
Finished Apr 28 01:00:42 PM PDT 24
Peak memory 204088 kb
Host smart-52ffee4d-bb3a-4e8c-9282-de8094ec622b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331469242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.2331469242
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.686485657
Short name T181
Test name
Test status
Simulation time 4447636884 ps
CPU time 114.17 seconds
Started Apr 28 01:00:33 PM PDT 24
Finished Apr 28 01:02:27 PM PDT 24
Peak memory 1279764 kb
Host smart-cc93f6bf-4012-43c7-9250-b37e59533bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686485657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.686485657
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.671823655
Short name T69
Test name
Test status
Simulation time 175729087 ps
CPU time 2.94 seconds
Started Apr 28 01:00:38 PM PDT 24
Finished Apr 28 01:00:42 PM PDT 24
Peak memory 204204 kb
Host smart-e315bea7-89a7-4b71-87aa-4183eb19c035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671823655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.671823655
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.2698676922
Short name T1181
Test name
Test status
Simulation time 6173236004 ps
CPU time 24.06 seconds
Started Apr 28 01:00:36 PM PDT 24
Finished Apr 28 01:01:01 PM PDT 24
Peak memory 294904 kb
Host smart-024331eb-f49c-496e-bb68-fcbfc3e15d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698676922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.2698676922
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.688557659
Short name T704
Test name
Test status
Simulation time 39339653 ps
CPU time 0.63 seconds
Started Apr 28 01:00:32 PM PDT 24
Finished Apr 28 01:00:33 PM PDT 24
Peak memory 203748 kb
Host smart-ef153fff-986a-4cea-9754-dab456f3dff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688557659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.688557659
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.2671266902
Short name T219
Test name
Test status
Simulation time 73618920608 ps
CPU time 329.07 seconds
Started Apr 28 01:00:35 PM PDT 24
Finished Apr 28 01:06:04 PM PDT 24
Peak memory 204304 kb
Host smart-49a27cf5-2290-4da0-a0d6-72f282a0296f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671266902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2671266902
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1273354837
Short name T1213
Test name
Test status
Simulation time 995643381 ps
CPU time 47.08 seconds
Started Apr 28 01:00:32 PM PDT 24
Finished Apr 28 01:01:20 PM PDT 24
Peak memory 315572 kb
Host smart-d20754c7-8416-4257-a0e5-fe4f64ae4c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273354837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1273354837
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.1348483320
Short name T1053
Test name
Test status
Simulation time 155469536667 ps
CPU time 929.07 seconds
Started Apr 28 01:00:35 PM PDT 24
Finished Apr 28 01:16:05 PM PDT 24
Peak memory 2046248 kb
Host smart-1f316613-32d7-416c-b8df-b586d19ebb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348483320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.1348483320
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.3158196792
Short name T488
Test name
Test status
Simulation time 1472457045 ps
CPU time 16.64 seconds
Started Apr 28 01:00:32 PM PDT 24
Finished Apr 28 01:00:49 PM PDT 24
Peak memory 212384 kb
Host smart-aab8cd05-acdc-4de4-94d3-f7cb3bbb1d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158196792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.3158196792
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.3421410823
Short name T647
Test name
Test status
Simulation time 9293622800 ps
CPU time 4.59 seconds
Started Apr 28 01:00:37 PM PDT 24
Finished Apr 28 01:00:43 PM PDT 24
Peak memory 212496 kb
Host smart-0c1a1184-fdd7-4234-bbab-8594d58633a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421410823 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3421410823
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.370408427
Short name T701
Test name
Test status
Simulation time 11052075499 ps
CPU time 6.06 seconds
Started Apr 28 01:00:37 PM PDT 24
Finished Apr 28 01:00:44 PM PDT 24
Peak memory 224812 kb
Host smart-cfcaa1fa-4f37-4726-b49a-e0e5859b250e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370408427 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_acq.370408427
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.899531930
Short name T325
Test name
Test status
Simulation time 10060292759 ps
CPU time 75.78 seconds
Started Apr 28 01:00:39 PM PDT 24
Finished Apr 28 01:01:56 PM PDT 24
Peak memory 558216 kb
Host smart-831fe2c0-6358-44e0-95cc-cb22e5b20b21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899531930 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_fifo_reset_tx.899531930
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.2959486963
Short name T933
Test name
Test status
Simulation time 2416665083 ps
CPU time 2.41 seconds
Started Apr 28 01:00:38 PM PDT 24
Finished Apr 28 01:00:41 PM PDT 24
Peak memory 204244 kb
Host smart-f67e78d1-3314-42b6-ba90-a604f0308b1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959486963 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.2959486963
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.2439993243
Short name T327
Test name
Test status
Simulation time 1762449402 ps
CPU time 4.26 seconds
Started Apr 28 01:00:36 PM PDT 24
Finished Apr 28 01:00:41 PM PDT 24
Peak memory 204232 kb
Host smart-9bd441c8-cc29-4bde-99f7-8b0b0b847ac5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439993243 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.2439993243
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.2751572205
Short name T812
Test name
Test status
Simulation time 2789637866 ps
CPU time 2.18 seconds
Started Apr 28 01:00:36 PM PDT 24
Finished Apr 28 01:00:39 PM PDT 24
Peak memory 204128 kb
Host smart-093c7403-eb44-4b4e-89fe-faa663bb4ea5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751572205 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.2751572205
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.3632553707
Short name T243
Test name
Test status
Simulation time 1769027509 ps
CPU time 26.38 seconds
Started Apr 28 01:00:34 PM PDT 24
Finished Apr 28 01:01:00 PM PDT 24
Peak memory 203952 kb
Host smart-11bb30ef-0f66-4a26-aae5-40c35c843156
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632553707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.3632553707
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.1463170422
Short name T1134
Test name
Test status
Simulation time 11674310134 ps
CPU time 27.29 seconds
Started Apr 28 01:00:34 PM PDT 24
Finished Apr 28 01:01:02 PM PDT 24
Peak memory 238024 kb
Host smart-916f10ac-b30d-4703-af06-23b0670647e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463170422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.1463170422
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.4006008850
Short name T651
Test name
Test status
Simulation time 15466855745 ps
CPU time 14.66 seconds
Started Apr 28 01:00:32 PM PDT 24
Finished Apr 28 01:00:47 PM PDT 24
Peak memory 204248 kb
Host smart-22b2674c-96da-4788-b873-f8b82cec1cc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006008850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.4006008850
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.1271685554
Short name T1173
Test name
Test status
Simulation time 27534797130 ps
CPU time 467.41 seconds
Started Apr 28 01:00:35 PM PDT 24
Finished Apr 28 01:08:22 PM PDT 24
Peak memory 1475616 kb
Host smart-f0acfafe-274c-401f-9dc4-13d24d7e3a2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271685554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.1271685554
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.3587177318
Short name T385
Test name
Test status
Simulation time 5701833016 ps
CPU time 7.18 seconds
Started Apr 28 01:00:38 PM PDT 24
Finished Apr 28 01:00:46 PM PDT 24
Peak memory 220488 kb
Host smart-9751a2f9-af47-428e-aea3-0467e000eab6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587177318 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.3587177318
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.1455563259
Short name T19
Test name
Test status
Simulation time 1831459337 ps
CPU time 6.33 seconds
Started Apr 28 01:00:37 PM PDT 24
Finished Apr 28 01:00:44 PM PDT 24
Peak memory 204040 kb
Host smart-74719f19-2815-4474-a570-d8d95134fd59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455563259 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.i2c_target_unexp_stop.1455563259
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.1820000960
Short name T1037
Test name
Test status
Simulation time 50017197 ps
CPU time 0.63 seconds
Started Apr 28 01:00:42 PM PDT 24
Finished Apr 28 01:00:43 PM PDT 24
Peak memory 203896 kb
Host smart-429cc0a4-78ca-4b7f-9474-f4875f6d9923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820000960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.1820000960
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.846908550
Short name T971
Test name
Test status
Simulation time 109461127 ps
CPU time 1.66 seconds
Started Apr 28 01:00:36 PM PDT 24
Finished Apr 28 01:00:38 PM PDT 24
Peak memory 212348 kb
Host smart-8738e1bc-9ffe-409a-8441-d57a382d7172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846908550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.846908550
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.3033033193
Short name T919
Test name
Test status
Simulation time 535755621 ps
CPU time 8.54 seconds
Started Apr 28 01:00:38 PM PDT 24
Finished Apr 28 01:00:47 PM PDT 24
Peak memory 296908 kb
Host smart-ab00e1b1-5068-45ce-9af4-a7aa009e5ecf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033033193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.3033033193
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.1930011456
Short name T776
Test name
Test status
Simulation time 5463559904 ps
CPU time 64.88 seconds
Started Apr 28 01:00:39 PM PDT 24
Finished Apr 28 01:01:45 PM PDT 24
Peak memory 695656 kb
Host smart-85b36987-091d-4c44-810c-e1b62831b3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930011456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.1930011456
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.1605699473
Short name T388
Test name
Test status
Simulation time 1479959002 ps
CPU time 33.39 seconds
Started Apr 28 01:00:37 PM PDT 24
Finished Apr 28 01:01:12 PM PDT 24
Peak memory 481296 kb
Host smart-0e905fae-9d31-457b-a0cc-af931427546f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605699473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.1605699473
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.2548024506
Short name T393
Test name
Test status
Simulation time 317284067 ps
CPU time 0.92 seconds
Started Apr 28 01:00:37 PM PDT 24
Finished Apr 28 01:00:38 PM PDT 24
Peak memory 204000 kb
Host smart-fbfbf921-e344-407d-87bb-21138c5f35b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548024506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.2548024506
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.2781288723
Short name T1028
Test name
Test status
Simulation time 352526658 ps
CPU time 4.29 seconds
Started Apr 28 01:00:39 PM PDT 24
Finished Apr 28 01:00:44 PM PDT 24
Peak memory 203996 kb
Host smart-1f362b0f-c665-4427-be52-b496e075f69e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781288723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.2781288723
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.467944240
Short name T1231
Test name
Test status
Simulation time 13686758915 ps
CPU time 225.75 seconds
Started Apr 28 01:00:37 PM PDT 24
Finished Apr 28 01:04:24 PM PDT 24
Peak memory 968568 kb
Host smart-b967598e-6fa0-46eb-89d8-845fdd4afabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467944240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.467944240
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.376494809
Short name T646
Test name
Test status
Simulation time 883562227 ps
CPU time 18.12 seconds
Started Apr 28 01:00:41 PM PDT 24
Finished Apr 28 01:01:00 PM PDT 24
Peak memory 204120 kb
Host smart-b6c1e6de-1197-4aa7-b393-ceb33361e865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376494809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.376494809
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.32288537
Short name T1210
Test name
Test status
Simulation time 7940198041 ps
CPU time 49.13 seconds
Started Apr 28 01:00:45 PM PDT 24
Finished Apr 28 01:01:35 PM PDT 24
Peak memory 296804 kb
Host smart-224c01be-3517-4452-8861-7e8d7541a685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32288537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.32288537
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.1684113851
Short name T1084
Test name
Test status
Simulation time 25384765 ps
CPU time 0.68 seconds
Started Apr 28 01:00:36 PM PDT 24
Finished Apr 28 01:00:38 PM PDT 24
Peak memory 203852 kb
Host smart-64cddce1-ae59-4099-a807-79f5522e2742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684113851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1684113851
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.3089678364
Short name T597
Test name
Test status
Simulation time 6664152434 ps
CPU time 197.98 seconds
Started Apr 28 01:00:41 PM PDT 24
Finished Apr 28 01:04:00 PM PDT 24
Peak memory 871008 kb
Host smart-f24705d5-7343-4289-974a-a513852e2ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089678364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.3089678364
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.424600039
Short name T1291
Test name
Test status
Simulation time 4558371369 ps
CPU time 56.13 seconds
Started Apr 28 01:00:38 PM PDT 24
Finished Apr 28 01:01:35 PM PDT 24
Peak memory 342148 kb
Host smart-e479eb16-1b34-4994-9f00-3475f839a923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424600039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.424600039
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.1503356321
Short name T1365
Test name
Test status
Simulation time 13627406397 ps
CPU time 69.42 seconds
Started Apr 28 01:00:36 PM PDT 24
Finished Apr 28 01:01:47 PM PDT 24
Peak memory 447940 kb
Host smart-0f07db73-17d8-40ee-8aaf-1c2108634567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503356321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.1503356321
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.1907135579
Short name T359
Test name
Test status
Simulation time 1813367246 ps
CPU time 12.81 seconds
Started Apr 28 01:00:39 PM PDT 24
Finished Apr 28 01:00:53 PM PDT 24
Peak memory 218292 kb
Host smart-68ebf3c8-a839-4e4c-a75e-2ebb450e8bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907135579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.1907135579
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1519608093
Short name T1343
Test name
Test status
Simulation time 10227177683 ps
CPU time 8.09 seconds
Started Apr 28 01:00:44 PM PDT 24
Finished Apr 28 01:00:53 PM PDT 24
Peak memory 245380 kb
Host smart-bcaff6a4-da77-4359-bb5a-9eef27252653
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519608093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.1519608093
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.4179859504
Short name T591
Test name
Test status
Simulation time 10077278892 ps
CPU time 66.99 seconds
Started Apr 28 01:00:49 PM PDT 24
Finished Apr 28 01:01:56 PM PDT 24
Peak memory 552764 kb
Host smart-85b303c6-3730-4bda-8d58-0274a4f62048
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179859504 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.4179859504
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.142053786
Short name T1141
Test name
Test status
Simulation time 1562260160 ps
CPU time 2.31 seconds
Started Apr 28 01:00:42 PM PDT 24
Finished Apr 28 01:00:45 PM PDT 24
Peak memory 204140 kb
Host smart-d67b3df3-49d5-40dc-8d3e-5ca58bb185b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142053786 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.i2c_target_hrst.142053786
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.1618237334
Short name T560
Test name
Test status
Simulation time 1525194674 ps
CPU time 3.96 seconds
Started Apr 28 01:00:49 PM PDT 24
Finished Apr 28 01:00:53 PM PDT 24
Peak memory 204204 kb
Host smart-81806ee7-3f20-4e92-963d-abfa40c7780a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618237334 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.1618237334
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.1348731657
Short name T813
Test name
Test status
Simulation time 23021733598 ps
CPU time 485.54 seconds
Started Apr 28 01:00:45 PM PDT 24
Finished Apr 28 01:08:51 PM PDT 24
Peak memory 4730848 kb
Host smart-0b4a933c-5b5d-4923-b24e-fe1e58809e3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348731657 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.1348731657
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.3676133177
Short name T562
Test name
Test status
Simulation time 888777285 ps
CPU time 11.92 seconds
Started Apr 28 01:00:39 PM PDT 24
Finished Apr 28 01:00:52 PM PDT 24
Peak memory 204156 kb
Host smart-9a5494a3-6113-45ca-9017-85ac3d1287c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676133177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.3676133177
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.1375414625
Short name T446
Test name
Test status
Simulation time 6110112193 ps
CPU time 56.6 seconds
Started Apr 28 01:00:41 PM PDT 24
Finished Apr 28 01:01:38 PM PDT 24
Peak memory 205304 kb
Host smart-49ac2e03-8723-403f-9735-05aedae3d760
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375414625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.1375414625
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.14763294
Short name T571
Test name
Test status
Simulation time 69149318186 ps
CPU time 222.11 seconds
Started Apr 28 01:00:44 PM PDT 24
Finished Apr 28 01:04:27 PM PDT 24
Peak memory 2294024 kb
Host smart-373aaaa2-5df9-4c44-a4af-2f150653500b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14763294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stress_wr.14763294
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.1227980636
Short name T394
Test name
Test status
Simulation time 12095797471 ps
CPU time 419.35 seconds
Started Apr 28 01:00:44 PM PDT 24
Finished Apr 28 01:07:44 PM PDT 24
Peak memory 1401636 kb
Host smart-085bac29-ad68-4828-887b-9168eb942246
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227980636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.1227980636
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.135648930
Short name T293
Test name
Test status
Simulation time 4377294358 ps
CPU time 5.71 seconds
Started Apr 28 01:00:42 PM PDT 24
Finished Apr 28 01:00:48 PM PDT 24
Peak memory 220484 kb
Host smart-c5f254d4-c1ca-4615-b99c-0ed4c70c4171
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135648930 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_timeout.135648930
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_unexp_stop.3085764117
Short name T18
Test name
Test status
Simulation time 3169345217 ps
CPU time 3.38 seconds
Started Apr 28 01:00:42 PM PDT 24
Finished Apr 28 01:00:46 PM PDT 24
Peak memory 204108 kb
Host smart-75ae4818-d880-492f-800a-4e47442d9d52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085764117 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.i2c_target_unexp_stop.3085764117
Directory /workspace/21.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1221283509
Short name T447
Test name
Test status
Simulation time 81070842 ps
CPU time 0.62 seconds
Started Apr 28 01:00:54 PM PDT 24
Finished Apr 28 01:00:56 PM PDT 24
Peak memory 203860 kb
Host smart-d9aa5295-975b-4070-84b9-b833051607e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221283509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1221283509
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.1115024129
Short name T691
Test name
Test status
Simulation time 111789350 ps
CPU time 1.5 seconds
Started Apr 28 01:00:47 PM PDT 24
Finished Apr 28 01:00:49 PM PDT 24
Peak memory 212268 kb
Host smart-3c31197e-fa3e-4910-9689-662d834f2d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115024129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.1115024129
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.3435671657
Short name T1048
Test name
Test status
Simulation time 377820680 ps
CPU time 7.31 seconds
Started Apr 28 01:00:42 PM PDT 24
Finished Apr 28 01:00:50 PM PDT 24
Peak memory 260364 kb
Host smart-c6ad0b18-1feb-4b2a-b2cc-78484de8f51d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435671657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.3435671657
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.3671529546
Short name T796
Test name
Test status
Simulation time 21656892599 ps
CPU time 33.31 seconds
Started Apr 28 01:00:43 PM PDT 24
Finished Apr 28 01:01:16 PM PDT 24
Peak memory 427028 kb
Host smart-446a1b5a-4664-4c9d-b667-8d609a41c5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671529546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.3671529546
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.107733530
Short name T719
Test name
Test status
Simulation time 5142824755 ps
CPU time 56.97 seconds
Started Apr 28 01:00:46 PM PDT 24
Finished Apr 28 01:01:43 PM PDT 24
Peak memory 598716 kb
Host smart-990d11ae-a902-4ae4-b0b5-187cc8b7695a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107733530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.107733530
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.2565712606
Short name T1123
Test name
Test status
Simulation time 449918063 ps
CPU time 2.81 seconds
Started Apr 28 01:00:43 PM PDT 24
Finished Apr 28 01:00:47 PM PDT 24
Peak memory 203984 kb
Host smart-e67e5e92-6bc0-4b78-bb4b-7d01696d78e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565712606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.2565712606
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.3039543261
Short name T694
Test name
Test status
Simulation time 17120767214 ps
CPU time 336.28 seconds
Started Apr 28 01:00:48 PM PDT 24
Finished Apr 28 01:06:25 PM PDT 24
Peak memory 1268276 kb
Host smart-53660a34-e56f-4d83-84a9-c39e03717f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039543261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.3039543261
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.19483850
Short name T1264
Test name
Test status
Simulation time 1563285520 ps
CPU time 18.2 seconds
Started Apr 28 01:00:49 PM PDT 24
Finished Apr 28 01:01:08 PM PDT 24
Peak memory 204152 kb
Host smart-e0111c3d-9aeb-482c-aa6f-3d074798acab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19483850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.19483850
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_override.196136500
Short name T932
Test name
Test status
Simulation time 93963222 ps
CPU time 0.68 seconds
Started Apr 28 01:00:45 PM PDT 24
Finished Apr 28 01:00:47 PM PDT 24
Peak memory 203792 kb
Host smart-144cf27e-5503-4078-9ddb-22bd87535679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196136500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.196136500
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.653106572
Short name T1188
Test name
Test status
Simulation time 7205002817 ps
CPU time 40.85 seconds
Started Apr 28 01:00:43 PM PDT 24
Finished Apr 28 01:01:25 PM PDT 24
Peak memory 454752 kb
Host smart-ed489eb0-99d3-48e9-9c6d-852b88be4850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653106572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.653106572
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.1275552098
Short name T1304
Test name
Test status
Simulation time 65262074557 ps
CPU time 1228.28 seconds
Started Apr 28 01:00:44 PM PDT 24
Finished Apr 28 01:21:14 PM PDT 24
Peak memory 2520228 kb
Host smart-98848408-1c6c-4994-a9f7-4ae8d6cd6154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275552098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.1275552098
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.1483221633
Short name T249
Test name
Test status
Simulation time 4185811450 ps
CPU time 30.59 seconds
Started Apr 28 01:00:43 PM PDT 24
Finished Apr 28 01:01:14 PM PDT 24
Peak memory 212460 kb
Host smart-7d04850e-3323-411f-92dc-288304effd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483221633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.1483221633
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.2736389336
Short name T1001
Test name
Test status
Simulation time 958076091 ps
CPU time 4.64 seconds
Started Apr 28 01:00:50 PM PDT 24
Finished Apr 28 01:00:55 PM PDT 24
Peak memory 212332 kb
Host smart-66da3f9c-5bf6-41fd-8b3e-44462ca761e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736389336 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.2736389336
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.1925737733
Short name T1017
Test name
Test status
Simulation time 10088797168 ps
CPU time 62.86 seconds
Started Apr 28 01:00:47 PM PDT 24
Finished Apr 28 01:01:51 PM PDT 24
Peak memory 437736 kb
Host smart-110ad7bd-f347-461d-9c0e-450721f4fb1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925737733 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.1925737733
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.741908641
Short name T109
Test name
Test status
Simulation time 10679913603 ps
CPU time 3.6 seconds
Started Apr 28 01:00:48 PM PDT 24
Finished Apr 28 01:00:52 PM PDT 24
Peak memory 219720 kb
Host smart-edad0be2-73bc-43d3-8850-cdd7a455d526
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741908641 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_fifo_reset_tx.741908641
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.381375980
Short name T1333
Test name
Test status
Simulation time 8945519339 ps
CPU time 2.76 seconds
Started Apr 28 01:00:50 PM PDT 24
Finished Apr 28 01:00:53 PM PDT 24
Peak memory 204308 kb
Host smart-ebf8debb-3b63-40b7-b251-5abce9df242f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381375980 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_hrst.381375980
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.2708668884
Short name T695
Test name
Test status
Simulation time 1283005167 ps
CPU time 5.8 seconds
Started Apr 28 01:00:47 PM PDT 24
Finished Apr 28 01:00:54 PM PDT 24
Peak memory 216284 kb
Host smart-6e0f3a90-523f-433c-8038-e2144abfe737
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708668884 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.2708668884
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.3433325258
Short name T100
Test name
Test status
Simulation time 10319649041 ps
CPU time 18.84 seconds
Started Apr 28 01:00:49 PM PDT 24
Finished Apr 28 01:01:09 PM PDT 24
Peak memory 683512 kb
Host smart-709eeffa-c37c-4d70-95a7-2e90efa47ee4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433325258 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.3433325258
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.277641165
Short name T104
Test name
Test status
Simulation time 1646188623 ps
CPU time 16.88 seconds
Started Apr 28 01:00:46 PM PDT 24
Finished Apr 28 01:01:03 PM PDT 24
Peak memory 203980 kb
Host smart-2b717efb-3f34-452d-9599-c86d51376f68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277641165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.277641165
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.3931808349
Short name T239
Test name
Test status
Simulation time 7792577229 ps
CPU time 15.91 seconds
Started Apr 28 01:00:48 PM PDT 24
Finished Apr 28 01:01:04 PM PDT 24
Peak memory 216076 kb
Host smart-61a5dabd-c426-4ab5-8ccf-e5bfa28fd15b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931808349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.3931808349
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.2258460361
Short name T663
Test name
Test status
Simulation time 34256547829 ps
CPU time 362.28 seconds
Started Apr 28 01:00:44 PM PDT 24
Finished Apr 28 01:06:47 PM PDT 24
Peak memory 3673640 kb
Host smart-ff8ca549-c1a8-4d07-ab53-06586026bd27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258460361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.2258460361
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.670445838
Short name T789
Test name
Test status
Simulation time 23652037921 ps
CPU time 207.2 seconds
Started Apr 28 01:00:43 PM PDT 24
Finished Apr 28 01:04:11 PM PDT 24
Peak memory 1546356 kb
Host smart-2d39c8ba-2285-4c5c-93d8-2bccc9e3e379
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670445838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_t
arget_stretch.670445838
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.1529604465
Short name T835
Test name
Test status
Simulation time 6338331857 ps
CPU time 6.23 seconds
Started Apr 28 01:00:51 PM PDT 24
Finished Apr 28 01:00:57 PM PDT 24
Peak memory 212492 kb
Host smart-4ecb5868-8175-4dfb-bf8f-221a615a6818
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529604465 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.1529604465
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.1442089441
Short name T666
Test name
Test status
Simulation time 39713125 ps
CPU time 0.58 seconds
Started Apr 28 01:01:04 PM PDT 24
Finished Apr 28 01:01:05 PM PDT 24
Peak memory 203900 kb
Host smart-8cc9ef8f-bc46-4784-a95c-183a87d9aa92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442089441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.1442089441
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.651005514
Short name T1020
Test name
Test status
Simulation time 200195882 ps
CPU time 1.37 seconds
Started Apr 28 01:00:52 PM PDT 24
Finished Apr 28 01:00:54 PM PDT 24
Peak memory 204136 kb
Host smart-e5ddd08b-51e9-43ce-a709-2e6b689a4460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651005514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.651005514
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.3716241270
Short name T718
Test name
Test status
Simulation time 6415465038 ps
CPU time 6.02 seconds
Started Apr 28 01:00:55 PM PDT 24
Finished Apr 28 01:01:01 PM PDT 24
Peak memory 260524 kb
Host smart-b65a2d19-0384-4b64-8e7b-dfcd828f3b62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716241270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.3716241270
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.361487096
Short name T57
Test name
Test status
Simulation time 1588071613 ps
CPU time 52.02 seconds
Started Apr 28 01:01:03 PM PDT 24
Finished Apr 28 01:01:56 PM PDT 24
Peak memory 568036 kb
Host smart-dc63ac10-eec9-4eec-b6fc-a372d7329fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361487096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.361487096
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.3905496132
Short name T354
Test name
Test status
Simulation time 1723457440 ps
CPU time 58.21 seconds
Started Apr 28 01:00:48 PM PDT 24
Finished Apr 28 01:01:47 PM PDT 24
Peak memory 630000 kb
Host smart-38336d34-c471-4076-b05f-bb838acf8a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905496132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.3905496132
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.2848106010
Short name T622
Test name
Test status
Simulation time 117319834 ps
CPU time 0.85 seconds
Started Apr 28 01:00:50 PM PDT 24
Finished Apr 28 01:00:51 PM PDT 24
Peak memory 203880 kb
Host smart-da53b9a1-8683-4d4a-bb7e-c9359eec8d12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848106010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.2848106010
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1635739384
Short name T92
Test name
Test status
Simulation time 176996971 ps
CPU time 5.02 seconds
Started Apr 28 01:01:04 PM PDT 24
Finished Apr 28 01:01:10 PM PDT 24
Peak memory 234616 kb
Host smart-13db2904-1268-46b0-9e69-13a4ef848233
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635739384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.1635739384
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.4113538046
Short name T817
Test name
Test status
Simulation time 3548909713 ps
CPU time 103.7 seconds
Started Apr 28 01:00:47 PM PDT 24
Finished Apr 28 01:02:31 PM PDT 24
Peak memory 1087348 kb
Host smart-1b640a2d-db3c-4680-9587-1383730c7490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113538046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.4113538046
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.395961951
Short name T463
Test name
Test status
Simulation time 966646184 ps
CPU time 9.25 seconds
Started Apr 28 01:00:59 PM PDT 24
Finished Apr 28 01:01:09 PM PDT 24
Peak memory 204188 kb
Host smart-db7f08a6-0952-4534-b31f-4d9d93569488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395961951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.395961951
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.2978140564
Short name T1230
Test name
Test status
Simulation time 8924978652 ps
CPU time 29.81 seconds
Started Apr 28 01:00:58 PM PDT 24
Finished Apr 28 01:01:29 PM PDT 24
Peak memory 354464 kb
Host smart-0896e739-f5d1-4a9c-ae95-7c4c149a993a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978140564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.2978140564
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.2791932872
Short name T875
Test name
Test status
Simulation time 34648902 ps
CPU time 0.64 seconds
Started Apr 28 01:00:50 PM PDT 24
Finished Apr 28 01:00:51 PM PDT 24
Peak memory 203840 kb
Host smart-22a48435-ebee-4f11-933a-100439034c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791932872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.2791932872
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.1665164293
Short name T220
Test name
Test status
Simulation time 25637393522 ps
CPU time 1001.56 seconds
Started Apr 28 01:00:54 PM PDT 24
Finished Apr 28 01:17:37 PM PDT 24
Peak memory 204240 kb
Host smart-dd31ffcb-b8d2-46e8-b2ff-dda20d9f8751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665164293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.1665164293
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.3928533911
Short name T774
Test name
Test status
Simulation time 1662095240 ps
CPU time 67.99 seconds
Started Apr 28 01:00:47 PM PDT 24
Finished Apr 28 01:01:56 PM PDT 24
Peak memory 335836 kb
Host smart-07f7ad15-837d-41d7-8430-07942aadbf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928533911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.3928533911
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.1350199689
Short name T194
Test name
Test status
Simulation time 5534957975 ps
CPU time 12.79 seconds
Started Apr 28 01:00:56 PM PDT 24
Finished Apr 28 01:01:09 PM PDT 24
Peak memory 232624 kb
Host smart-0f7a7785-436f-4343-bbbc-29470fa62c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350199689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.1350199689
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.1296817110
Short name T251
Test name
Test status
Simulation time 852642253 ps
CPU time 38.38 seconds
Started Apr 28 01:00:54 PM PDT 24
Finished Apr 28 01:01:32 PM PDT 24
Peak memory 212636 kb
Host smart-f5fa341e-ac43-42d8-80ed-9240b28f65e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296817110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.1296817110
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.938663122
Short name T1136
Test name
Test status
Simulation time 10144004528 ps
CPU time 10.94 seconds
Started Apr 28 01:00:54 PM PDT 24
Finished Apr 28 01:01:06 PM PDT 24
Peak memory 240928 kb
Host smart-e2735cd9-88f3-4b1d-9e5c-25e618f5d30a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938663122 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_acq.938663122
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.1770025691
Short name T1089
Test name
Test status
Simulation time 10943107961 ps
CPU time 5.14 seconds
Started Apr 28 01:00:54 PM PDT 24
Finished Apr 28 01:01:00 PM PDT 24
Peak memory 241244 kb
Host smart-d28ba4ce-b0b0-4228-80f1-9f746fb80302
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770025691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.1770025691
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.3738803408
Short name T991
Test name
Test status
Simulation time 295024655 ps
CPU time 2.1 seconds
Started Apr 28 01:01:04 PM PDT 24
Finished Apr 28 01:01:07 PM PDT 24
Peak memory 204192 kb
Host smart-f68aad61-9228-4582-8556-119ce8ba37f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738803408 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.3738803408
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.355368053
Short name T758
Test name
Test status
Simulation time 11983842038 ps
CPU time 6.89 seconds
Started Apr 28 01:00:55 PM PDT 24
Finished Apr 28 01:01:02 PM PDT 24
Peak memory 213060 kb
Host smart-931f6539-2daf-4764-b057-9b5c8938aaea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355368053 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.355368053
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.653637479
Short name T470
Test name
Test status
Simulation time 3813434935 ps
CPU time 5.7 seconds
Started Apr 28 01:01:03 PM PDT 24
Finished Apr 28 01:01:10 PM PDT 24
Peak memory 357812 kb
Host smart-e693e22e-38f8-46d6-bfff-d973f720e305
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653637479 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.653637479
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.3518639180
Short name T461
Test name
Test status
Simulation time 1438909844 ps
CPU time 9.52 seconds
Started Apr 28 01:00:55 PM PDT 24
Finished Apr 28 01:01:05 PM PDT 24
Peak memory 204156 kb
Host smart-4928d388-5f7a-4fa3-98cd-7a1381def736
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518639180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.3518639180
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2259748026
Short name T1068
Test name
Test status
Simulation time 1452001711 ps
CPU time 20.13 seconds
Started Apr 28 01:01:05 PM PDT 24
Finished Apr 28 01:01:26 PM PDT 24
Peak memory 225152 kb
Host smart-bf435987-32d6-4d63-b0dd-c846b9d83061
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259748026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2259748026
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.2238218465
Short name T939
Test name
Test status
Simulation time 20255342772 ps
CPU time 37.19 seconds
Started Apr 28 01:00:56 PM PDT 24
Finished Apr 28 01:01:33 PM PDT 24
Peak memory 204164 kb
Host smart-c265f352-2a0b-48b8-aabe-f551bde60a70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238218465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.2238218465
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.1501551545
Short name T747
Test name
Test status
Simulation time 4995690329 ps
CPU time 23.91 seconds
Started Apr 28 01:00:52 PM PDT 24
Finished Apr 28 01:01:17 PM PDT 24
Peak memory 270660 kb
Host smart-51620091-58ec-4bfe-a4e2-0b8271c1fb44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501551545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.1501551545
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.2553276589
Short name T1245
Test name
Test status
Simulation time 2634784206 ps
CPU time 6.83 seconds
Started Apr 28 01:00:54 PM PDT 24
Finished Apr 28 01:01:02 PM PDT 24
Peak memory 212312 kb
Host smart-f37fdec4-9ec4-497d-9d0f-45483116108f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553276589 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.2553276589
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_unexp_stop.1028766299
Short name T1262
Test name
Test status
Simulation time 19250059761 ps
CPU time 6.63 seconds
Started Apr 28 01:00:56 PM PDT 24
Finished Apr 28 01:01:03 PM PDT 24
Peak memory 212432 kb
Host smart-7e51b47c-ee4c-4c24-86db-63e624ea9dd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028766299 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.i2c_target_unexp_stop.1028766299
Directory /workspace/23.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/24.i2c_alert_test.1666732126
Short name T1254
Test name
Test status
Simulation time 28248283 ps
CPU time 0.63 seconds
Started Apr 28 01:01:03 PM PDT 24
Finished Apr 28 01:01:04 PM PDT 24
Peak memory 203888 kb
Host smart-3e785ae9-2522-4a4c-a225-409605f6eeed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666732126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.1666732126
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.1617060186
Short name T316
Test name
Test status
Simulation time 107286811 ps
CPU time 1.41 seconds
Started Apr 28 01:00:57 PM PDT 24
Finished Apr 28 01:00:58 PM PDT 24
Peak memory 212480 kb
Host smart-ea5b7a76-93db-4e72-bde9-6d5674e0e57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617060186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.1617060186
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.1590999159
Short name T271
Test name
Test status
Simulation time 361208257 ps
CPU time 7.2 seconds
Started Apr 28 01:00:59 PM PDT 24
Finished Apr 28 01:01:06 PM PDT 24
Peak memory 283708 kb
Host smart-762e4d1f-c065-48c1-b1fe-6feeee770acf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590999159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.1590999159
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.16873774
Short name T1154
Test name
Test status
Simulation time 15655107871 ps
CPU time 53.63 seconds
Started Apr 28 01:01:01 PM PDT 24
Finished Apr 28 01:01:55 PM PDT 24
Peak memory 541788 kb
Host smart-01fe8714-a26b-4394-b11b-8733f687f8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16873774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.16873774
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.3535211569
Short name T390
Test name
Test status
Simulation time 3152526236 ps
CPU time 109.66 seconds
Started Apr 28 01:00:58 PM PDT 24
Finished Apr 28 01:02:48 PM PDT 24
Peak memory 589220 kb
Host smart-dd0b58fe-5b00-429f-ae0b-8afa451c98e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535211569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.3535211569
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.147596614
Short name T38
Test name
Test status
Simulation time 340814381 ps
CPU time 1 seconds
Started Apr 28 01:01:05 PM PDT 24
Finished Apr 28 01:01:07 PM PDT 24
Peak memory 204164 kb
Host smart-82942863-54d8-4d4f-85ca-4ae5293e1a70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147596614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fm
t.147596614
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.3632101864
Short name T1253
Test name
Test status
Simulation time 222572587 ps
CPU time 2.66 seconds
Started Apr 28 01:00:59 PM PDT 24
Finished Apr 28 01:01:02 PM PDT 24
Peak memory 204204 kb
Host smart-14b7c42c-9143-489b-891d-f77be677b57e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632101864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.3632101864
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1165475382
Short name T1212
Test name
Test status
Simulation time 2656938354 ps
CPU time 71.73 seconds
Started Apr 28 01:01:04 PM PDT 24
Finished Apr 28 01:02:17 PM PDT 24
Peak memory 835256 kb
Host smart-df344c9a-ff67-4b65-8cb5-2e8baf797af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165475382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1165475382
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.147714877
Short name T565
Test name
Test status
Simulation time 208646283 ps
CPU time 8.14 seconds
Started Apr 28 01:01:04 PM PDT 24
Finished Apr 28 01:01:13 PM PDT 24
Peak memory 204040 kb
Host smart-48912689-a95b-44e0-aaae-ac990d4ae206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147714877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.147714877
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.3191616400
Short name T234
Test name
Test status
Simulation time 6847278061 ps
CPU time 61.61 seconds
Started Apr 28 01:01:02 PM PDT 24
Finished Apr 28 01:02:04 PM PDT 24
Peak memory 323776 kb
Host smart-3bb60cff-1dc3-49e8-ae2a-7a86ae5939ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191616400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.3191616400
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.2496433635
Short name T210
Test name
Test status
Simulation time 46768861 ps
CPU time 0.66 seconds
Started Apr 28 01:00:57 PM PDT 24
Finished Apr 28 01:00:58 PM PDT 24
Peak memory 203840 kb
Host smart-8ddc607f-2f1e-4a22-9fc8-eb4df0e37bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496433635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.2496433635
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.3695808183
Short name T955
Test name
Test status
Simulation time 1977430787 ps
CPU time 24.08 seconds
Started Apr 28 01:01:00 PM PDT 24
Finished Apr 28 01:01:25 PM PDT 24
Peak memory 319176 kb
Host smart-ac7d478a-51c2-4c2e-beeb-17c6a1d70234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695808183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.3695808183
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.2161099729
Short name T901
Test name
Test status
Simulation time 4668621957 ps
CPU time 16.67 seconds
Started Apr 28 01:00:59 PM PDT 24
Finished Apr 28 01:01:16 PM PDT 24
Peak memory 260472 kb
Host smart-97ad2019-1fb3-40f7-8be3-05afe307144e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161099729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.2161099729
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.4272651887
Short name T999
Test name
Test status
Simulation time 43301599209 ps
CPU time 763.45 seconds
Started Apr 28 01:00:59 PM PDT 24
Finished Apr 28 01:13:43 PM PDT 24
Peak memory 1223048 kb
Host smart-e789fded-92fb-4532-b391-13d4aa728179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272651887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.4272651887
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.218296132
Short name T549
Test name
Test status
Simulation time 2020563117 ps
CPU time 18.79 seconds
Started Apr 28 01:01:04 PM PDT 24
Finished Apr 28 01:01:23 PM PDT 24
Peak memory 212384 kb
Host smart-1a52bc0a-d4e5-4bda-96ec-b6d0ac2fc5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218296132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.218296132
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.162829872
Short name T478
Test name
Test status
Simulation time 842802356 ps
CPU time 3.44 seconds
Started Apr 28 01:01:02 PM PDT 24
Finished Apr 28 01:01:06 PM PDT 24
Peak memory 204144 kb
Host smart-61486f62-a53c-420e-9453-99257ba89f5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162829872 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.162829872
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.435046908
Short name T522
Test name
Test status
Simulation time 10058718502 ps
CPU time 66.78 seconds
Started Apr 28 01:00:58 PM PDT 24
Finished Apr 28 01:02:05 PM PDT 24
Peak memory 426220 kb
Host smart-b30ced31-4676-41fe-aa74-5a80aab24617
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435046908 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_acq.435046908
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.721525967
Short name T1172
Test name
Test status
Simulation time 10314801680 ps
CPU time 13.97 seconds
Started Apr 28 01:01:07 PM PDT 24
Finished Apr 28 01:01:21 PM PDT 24
Peak memory 264320 kb
Host smart-f1606f8e-ace4-43a3-b5d3-4473fbc3430a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721525967 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_fifo_reset_tx.721525967
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.1126214886
Short name T739
Test name
Test status
Simulation time 1704509204 ps
CPU time 2.53 seconds
Started Apr 28 01:01:04 PM PDT 24
Finished Apr 28 01:01:08 PM PDT 24
Peak memory 204076 kb
Host smart-870dda8c-f008-448d-9c53-9ca6a5d2d6a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126214886 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.1126214886
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.2244960613
Short name T452
Test name
Test status
Simulation time 1653604431 ps
CPU time 2.67 seconds
Started Apr 28 01:01:00 PM PDT 24
Finished Apr 28 01:01:03 PM PDT 24
Peak memory 204076 kb
Host smart-fcf492ae-ab36-405b-ad72-d166b0b6d94d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244960613 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.2244960613
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.233513926
Short name T1228
Test name
Test status
Simulation time 12415319994 ps
CPU time 41.51 seconds
Started Apr 28 01:00:59 PM PDT 24
Finished Apr 28 01:01:41 PM PDT 24
Peak memory 806544 kb
Host smart-f95cd524-8468-4131-b7e5-1780a5b6c439
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233513926 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.233513926
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.2754025593
Short name T952
Test name
Test status
Simulation time 1174890737 ps
CPU time 14.17 seconds
Started Apr 28 01:01:00 PM PDT 24
Finished Apr 28 01:01:15 PM PDT 24
Peak memory 204072 kb
Host smart-8e9ab8b2-8895-45a3-a79b-542ad36adc7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754025593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.2754025593
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.3981940955
Short name T598
Test name
Test status
Simulation time 1128218044 ps
CPU time 24.33 seconds
Started Apr 28 01:01:00 PM PDT 24
Finished Apr 28 01:01:24 PM PDT 24
Peak memory 204140 kb
Host smart-778f28db-0e07-4e90-8c87-2e7b12bfb2be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981940955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.3981940955
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.1546854199
Short name T101
Test name
Test status
Simulation time 48465960493 ps
CPU time 365.98 seconds
Started Apr 28 01:01:00 PM PDT 24
Finished Apr 28 01:07:06 PM PDT 24
Peak memory 3619100 kb
Host smart-32da9312-0efa-40fb-a8e3-dd554e43e74d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546854199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.1546854199
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.3906779211
Short name T1070
Test name
Test status
Simulation time 41182697933 ps
CPU time 285.66 seconds
Started Apr 28 01:00:59 PM PDT 24
Finished Apr 28 01:05:46 PM PDT 24
Peak memory 2077256 kb
Host smart-0b550684-d243-4abf-a8de-61a268a9db43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906779211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.3906779211
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2530654856
Short name T538
Test name
Test status
Simulation time 5554537657 ps
CPU time 6.88 seconds
Started Apr 28 01:00:58 PM PDT 24
Finished Apr 28 01:01:05 PM PDT 24
Peak memory 220508 kb
Host smart-eddb684c-b37f-4547-b26b-74e075acf622
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530654856 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2530654856
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_unexp_stop.18191581
Short name T810
Test name
Test status
Simulation time 4592285630 ps
CPU time 6.93 seconds
Started Apr 28 01:00:59 PM PDT 24
Finished Apr 28 01:01:07 PM PDT 24
Peak memory 212496 kb
Host smart-27228da2-0aa1-4e22-91c0-388445f829ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18191581 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_unexp_stop.18191581
Directory /workspace/24.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/25.i2c_alert_test.2484151884
Short name T294
Test name
Test status
Simulation time 35622743 ps
CPU time 0.6 seconds
Started Apr 28 01:01:08 PM PDT 24
Finished Apr 28 01:01:10 PM PDT 24
Peak memory 203804 kb
Host smart-1e34c6ca-3ba4-40b9-80b3-48048edcb02b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484151884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.2484151884
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.1872980171
Short name T947
Test name
Test status
Simulation time 86808787 ps
CPU time 1.42 seconds
Started Apr 28 01:01:04 PM PDT 24
Finished Apr 28 01:01:06 PM PDT 24
Peak memory 212440 kb
Host smart-e433fb22-260c-4a72-8e1c-bd2b9b3777b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872980171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.1872980171
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2481405184
Short name T589
Test name
Test status
Simulation time 357838621 ps
CPU time 6.52 seconds
Started Apr 28 01:01:04 PM PDT 24
Finished Apr 28 01:01:12 PM PDT 24
Peak memory 282028 kb
Host smart-c8acaec6-3da0-48ee-a4e5-954f1d8674c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481405184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2481405184
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.61007714
Short name T1174
Test name
Test status
Simulation time 2424651773 ps
CPU time 176.57 seconds
Started Apr 28 01:01:02 PM PDT 24
Finished Apr 28 01:03:59 PM PDT 24
Peak memory 783504 kb
Host smart-81d9f47c-f340-4bb3-ad99-7426453b2121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61007714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.61007714
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.541065937
Short name T89
Test name
Test status
Simulation time 9047021820 ps
CPU time 71.05 seconds
Started Apr 28 01:01:07 PM PDT 24
Finished Apr 28 01:02:18 PM PDT 24
Peak memory 746696 kb
Host smart-a76b2497-1b4c-4986-8c37-bb16fd0d196a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541065937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.541065937
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.1454812676
Short name T1122
Test name
Test status
Simulation time 586548101 ps
CPU time 1.01 seconds
Started Apr 28 01:01:05 PM PDT 24
Finished Apr 28 01:01:07 PM PDT 24
Peak memory 203996 kb
Host smart-ae3e31ee-ce8a-4faf-8f99-ef35833dc831
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454812676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.1454812676
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.3876897735
Short name T678
Test name
Test status
Simulation time 242339451 ps
CPU time 6.54 seconds
Started Apr 28 01:01:03 PM PDT 24
Finished Apr 28 01:01:11 PM PDT 24
Peak memory 203980 kb
Host smart-8381ec35-c8f3-4f0f-8c89-2e1da7bc9644
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876897735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.3876897735
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.1634360287
Short name T949
Test name
Test status
Simulation time 4302134506 ps
CPU time 105.46 seconds
Started Apr 28 01:01:02 PM PDT 24
Finished Apr 28 01:02:48 PM PDT 24
Peak memory 1217288 kb
Host smart-2e45f77c-f769-41c6-8d36-23a54476814d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634360287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.1634360287
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.2012120975
Short name T676
Test name
Test status
Simulation time 935879316 ps
CPU time 4.1 seconds
Started Apr 28 01:01:12 PM PDT 24
Finished Apr 28 01:01:17 PM PDT 24
Peak memory 204144 kb
Host smart-3a09f872-a329-4955-a291-39dd0ef0e8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012120975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.2012120975
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.3988423385
Short name T436
Test name
Test status
Simulation time 1783727379 ps
CPU time 29.58 seconds
Started Apr 28 01:01:08 PM PDT 24
Finished Apr 28 01:01:38 PM PDT 24
Peak memory 331248 kb
Host smart-fdef9d8f-2654-4daa-b6c2-69f618aa48ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988423385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.3988423385
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.357958944
Short name T561
Test name
Test status
Simulation time 28052152 ps
CPU time 0.66 seconds
Started Apr 28 01:01:04 PM PDT 24
Finished Apr 28 01:01:05 PM PDT 24
Peak memory 203716 kb
Host smart-7528d3d2-0f7b-4cb3-9ebe-ed666d131840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357958944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.357958944
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1215361014
Short name T76
Test name
Test status
Simulation time 25106714170 ps
CPU time 63.77 seconds
Started Apr 28 01:01:04 PM PDT 24
Finished Apr 28 01:02:09 PM PDT 24
Peak memory 204112 kb
Host smart-f1e84eaa-5dc9-476d-968b-710fa95ee074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215361014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1215361014
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.2741431549
Short name T922
Test name
Test status
Simulation time 1382212725 ps
CPU time 68.55 seconds
Started Apr 28 01:01:06 PM PDT 24
Finished Apr 28 01:02:15 PM PDT 24
Peak memory 359328 kb
Host smart-3bf78eee-d05a-4f3b-9f2e-efa9d97a9dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741431549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.2741431549
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.501343259
Short name T259
Test name
Test status
Simulation time 12345247638 ps
CPU time 461.77 seconds
Started Apr 28 01:01:04 PM PDT 24
Finished Apr 28 01:08:47 PM PDT 24
Peak memory 1159708 kb
Host smart-093b8f18-c63b-4c17-b087-5aa13a2f5b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501343259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.501343259
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.1146566917
Short name T254
Test name
Test status
Simulation time 11730839143 ps
CPU time 32.24 seconds
Started Apr 28 01:01:02 PM PDT 24
Finished Apr 28 01:01:35 PM PDT 24
Peak memory 212416 kb
Host smart-4a6014ac-93fd-4022-a5fa-7e486dd0b396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146566917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.1146566917
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.1133656460
Short name T1119
Test name
Test status
Simulation time 950148852 ps
CPU time 3.95 seconds
Started Apr 28 01:01:07 PM PDT 24
Finished Apr 28 01:01:11 PM PDT 24
Peak memory 212376 kb
Host smart-830a35e0-08a2-45a4-b6da-76bbccebe833
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133656460 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.1133656460
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.2469163098
Short name T696
Test name
Test status
Simulation time 10054370891 ps
CPU time 64.03 seconds
Started Apr 28 01:01:11 PM PDT 24
Finished Apr 28 01:02:16 PM PDT 24
Peak memory 419884 kb
Host smart-f26a5d24-c492-4764-8eea-919f2739bbfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469163098 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.2469163098
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3486674249
Short name T346
Test name
Test status
Simulation time 10093397308 ps
CPU time 33.79 seconds
Started Apr 28 01:01:11 PM PDT 24
Finished Apr 28 01:01:46 PM PDT 24
Peak memory 338456 kb
Host smart-397dd8a0-b7bf-43c7-9ba7-e28fbb0baf4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486674249 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3486674249
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.3340033815
Short name T1156
Test name
Test status
Simulation time 528024570 ps
CPU time 2.86 seconds
Started Apr 28 01:01:12 PM PDT 24
Finished Apr 28 01:01:15 PM PDT 24
Peak memory 204140 kb
Host smart-ecd16411-1b2e-4b77-8122-0dac682afa3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340033815 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.3340033815
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.2814113791
Short name T485
Test name
Test status
Simulation time 4723670948 ps
CPU time 4.83 seconds
Started Apr 28 01:01:12 PM PDT 24
Finished Apr 28 01:01:17 PM PDT 24
Peak memory 212428 kb
Host smart-2f61b5a8-6e45-49a3-ac37-b2bd07d53754
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814113791 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.2814113791
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.2948578885
Short name T722
Test name
Test status
Simulation time 4396332984 ps
CPU time 9 seconds
Started Apr 28 01:01:08 PM PDT 24
Finished Apr 28 01:01:17 PM PDT 24
Peak memory 204264 kb
Host smart-9bb3a8dc-f3a1-4ff2-8867-baf769c6d050
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948578885 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.2948578885
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.109421452
Short name T1118
Test name
Test status
Simulation time 456198839 ps
CPU time 6.59 seconds
Started Apr 28 01:01:05 PM PDT 24
Finished Apr 28 01:01:12 PM PDT 24
Peak memory 204148 kb
Host smart-edd4471f-0613-4228-8e69-a76c1cbde01b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109421452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_tar
get_smoke.109421452
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.1227189764
Short name T440
Test name
Test status
Simulation time 5771412853 ps
CPU time 7.84 seconds
Started Apr 28 01:01:04 PM PDT 24
Finished Apr 28 01:01:13 PM PDT 24
Peak memory 209480 kb
Host smart-bfa2eea7-35f9-4687-b522-e83c90ba507a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227189764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.1227189764
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.128076063
Short name T487
Test name
Test status
Simulation time 43534896673 ps
CPU time 85.19 seconds
Started Apr 28 01:01:05 PM PDT 24
Finished Apr 28 01:02:31 PM PDT 24
Peak memory 1316324 kb
Host smart-fb5027a6-1c4b-4bee-9698-a9bd223f32b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128076063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_wr.128076063
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.3396609621
Short name T314
Test name
Test status
Simulation time 7502009602 ps
CPU time 166.22 seconds
Started Apr 28 01:01:03 PM PDT 24
Finished Apr 28 01:03:50 PM PDT 24
Peak memory 1647108 kb
Host smart-6208b075-71f2-4d9e-9c5d-c9b464b8adf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396609621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.3396609621
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.1920321229
Short name T1166
Test name
Test status
Simulation time 1019687115 ps
CPU time 5.66 seconds
Started Apr 28 01:01:06 PM PDT 24
Finished Apr 28 01:01:13 PM PDT 24
Peak memory 217984 kb
Host smart-210a10f8-8a21-4a9f-81a0-053285ca1dee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920321229 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.1920321229
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.285330851
Short name T357
Test name
Test status
Simulation time 26265915 ps
CPU time 0.64 seconds
Started Apr 28 01:01:14 PM PDT 24
Finished Apr 28 01:01:15 PM PDT 24
Peak memory 203920 kb
Host smart-2de12769-bd87-4f32-9247-d0781f0aef04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285330851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.285330851
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.3773955958
Short name T1282
Test name
Test status
Simulation time 780003175 ps
CPU time 1.43 seconds
Started Apr 28 01:01:15 PM PDT 24
Finished Apr 28 01:01:17 PM PDT 24
Peak memory 212476 kb
Host smart-610479e2-6635-4e1c-b295-aca68c7e6722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773955958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.3773955958
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.996237586
Short name T1341
Test name
Test status
Simulation time 270522119 ps
CPU time 5.93 seconds
Started Apr 28 01:01:09 PM PDT 24
Finished Apr 28 01:01:15 PM PDT 24
Peak memory 257852 kb
Host smart-8b433255-9bde-4e21-b144-ae5c37e9346d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996237586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empt
y.996237586
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.900303451
Short name T378
Test name
Test status
Simulation time 3350151757 ps
CPU time 52.29 seconds
Started Apr 28 01:01:12 PM PDT 24
Finished Apr 28 01:02:05 PM PDT 24
Peak memory 568388 kb
Host smart-b7746439-2880-4423-8a23-9cc6315c6a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900303451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.900303451
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.2558476349
Short name T675
Test name
Test status
Simulation time 1485063969 ps
CPU time 101.56 seconds
Started Apr 28 01:01:08 PM PDT 24
Finished Apr 28 01:02:50 PM PDT 24
Peak memory 555160 kb
Host smart-9855d2ed-6e84-4123-911f-4339b03e106b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558476349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.2558476349
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.3136594381
Short name T371
Test name
Test status
Simulation time 686141766 ps
CPU time 1.1 seconds
Started Apr 28 01:01:09 PM PDT 24
Finished Apr 28 01:01:10 PM PDT 24
Peak memory 204072 kb
Host smart-b4c11b41-353f-4e54-a9b4-df3661d42384
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136594381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.3136594381
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.2108027125
Short name T925
Test name
Test status
Simulation time 262499416 ps
CPU time 6.47 seconds
Started Apr 28 01:01:08 PM PDT 24
Finished Apr 28 01:01:15 PM PDT 24
Peak memory 204148 kb
Host smart-4f60dfb4-4e41-4b94-9d04-7d268c652fb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108027125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.2108027125
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.560824574
Short name T1075
Test name
Test status
Simulation time 4162084094 ps
CPU time 265.31 seconds
Started Apr 28 01:01:10 PM PDT 24
Finished Apr 28 01:05:36 PM PDT 24
Peak memory 1087044 kb
Host smart-3fa94a01-29fb-403b-b8ff-46a1cf7398fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560824574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.560824574
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.1165635165
Short name T422
Test name
Test status
Simulation time 392923099 ps
CPU time 16.53 seconds
Started Apr 28 01:01:14 PM PDT 24
Finished Apr 28 01:01:31 PM PDT 24
Peak memory 204212 kb
Host smart-d4fd9aa3-e177-4c9a-82de-2e4d5ec91792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165635165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.1165635165
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.3840773670
Short name T509
Test name
Test status
Simulation time 5072067500 ps
CPU time 20.84 seconds
Started Apr 28 01:01:15 PM PDT 24
Finished Apr 28 01:01:37 PM PDT 24
Peak memory 347168 kb
Host smart-5bb2ea47-fb95-44f8-b04a-e7e97e9d817f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840773670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.3840773670
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.1436793549
Short name T1008
Test name
Test status
Simulation time 75230536 ps
CPU time 0.67 seconds
Started Apr 28 01:01:12 PM PDT 24
Finished Apr 28 01:01:13 PM PDT 24
Peak memory 203804 kb
Host smart-2c0ceddd-14b7-485b-8b59-99e1752d531e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436793549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.1436793549
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.420706643
Short name T218
Test name
Test status
Simulation time 48686920680 ps
CPU time 2137.45 seconds
Started Apr 28 01:01:14 PM PDT 24
Finished Apr 28 01:36:53 PM PDT 24
Peak memory 5142940 kb
Host smart-d3b32707-2497-46f4-bbc0-1a68f2e76d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420706643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.420706643
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.4263836846
Short name T822
Test name
Test status
Simulation time 3410611691 ps
CPU time 15.41 seconds
Started Apr 28 01:01:11 PM PDT 24
Finished Apr 28 01:01:27 PM PDT 24
Peak memory 286792 kb
Host smart-8ffb1f13-38fe-45df-882f-8900b2b48bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263836846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.4263836846
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.2365274358
Short name T961
Test name
Test status
Simulation time 70447739565 ps
CPU time 966.38 seconds
Started Apr 28 01:01:14 PM PDT 24
Finished Apr 28 01:17:21 PM PDT 24
Peak memory 3580208 kb
Host smart-f86ebe1b-8673-42b3-a10a-7417836305de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365274358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.2365274358
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.182831412
Short name T318
Test name
Test status
Simulation time 887695462 ps
CPU time 19.58 seconds
Started Apr 28 01:01:15 PM PDT 24
Finished Apr 28 01:01:36 PM PDT 24
Peak memory 212300 kb
Host smart-17d84c30-684d-4266-aad5-edc1dbe8fd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182831412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.182831412
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.3736176580
Short name T839
Test name
Test status
Simulation time 2967839395 ps
CPU time 3.74 seconds
Started Apr 28 01:01:13 PM PDT 24
Finished Apr 28 01:01:17 PM PDT 24
Peak memory 204104 kb
Host smart-03fa4872-ce10-43e4-b175-d1f1e8899f4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736176580 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.3736176580
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.605184046
Short name T749
Test name
Test status
Simulation time 10042157719 ps
CPU time 63.72 seconds
Started Apr 28 01:01:15 PM PDT 24
Finished Apr 28 01:02:20 PM PDT 24
Peak memory 415752 kb
Host smart-36fa1b32-3fe1-4734-80f9-b9833fce1adc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605184046 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_acq.605184046
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.3058776942
Short name T1274
Test name
Test status
Simulation time 820519256 ps
CPU time 2.39 seconds
Started Apr 28 01:01:14 PM PDT 24
Finished Apr 28 01:01:18 PM PDT 24
Peak memory 204008 kb
Host smart-12fe9cab-b992-4458-8bd9-0fa62f157b3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058776942 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.3058776942
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.357430138
Short name T1335
Test name
Test status
Simulation time 2314720304 ps
CPU time 5.53 seconds
Started Apr 28 01:01:14 PM PDT 24
Finished Apr 28 01:01:21 PM PDT 24
Peak memory 212348 kb
Host smart-b08fa7ed-5243-4ba2-a69c-7ba9c2d9cbc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357430138 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_intr_smoke.357430138
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.3526319902
Short name T1170
Test name
Test status
Simulation time 16441319759 ps
CPU time 99.19 seconds
Started Apr 28 01:01:12 PM PDT 24
Finished Apr 28 01:02:52 PM PDT 24
Peak memory 1589920 kb
Host smart-77e78bce-145c-4d3c-9cbe-e801841065fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526319902 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.3526319902
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.4257428242
Short name T730
Test name
Test status
Simulation time 837875440 ps
CPU time 31.1 seconds
Started Apr 28 01:01:15 PM PDT 24
Finished Apr 28 01:01:46 PM PDT 24
Peak memory 204132 kb
Host smart-2b70f568-51f4-4fe8-82d6-207c74e9e6eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257428242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.4257428242
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.2342121252
Short name T1128
Test name
Test status
Simulation time 1364615940 ps
CPU time 22.17 seconds
Started Apr 28 01:01:15 PM PDT 24
Finished Apr 28 01:01:38 PM PDT 24
Peak memory 225988 kb
Host smart-d76c6203-f079-4377-ad5e-9fff21f358a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342121252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.2342121252
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.1919897637
Short name T1105
Test name
Test status
Simulation time 54745707085 ps
CPU time 175.73 seconds
Started Apr 28 01:01:18 PM PDT 24
Finished Apr 28 01:04:15 PM PDT 24
Peak memory 2127896 kb
Host smart-6564cbf0-42fb-40d4-9a31-36ad15717e6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919897637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.1919897637
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.1482045428
Short name T305
Test name
Test status
Simulation time 24410664735 ps
CPU time 171.34 seconds
Started Apr 28 01:01:13 PM PDT 24
Finished Apr 28 01:04:05 PM PDT 24
Peak memory 1457044 kb
Host smart-8c6c13a6-8a02-4bb8-8560-ca70f75fd1e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482045428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.1482045428
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.3768950414
Short name T960
Test name
Test status
Simulation time 1221857203 ps
CPU time 6.13 seconds
Started Apr 28 01:01:14 PM PDT 24
Finished Apr 28 01:01:20 PM PDT 24
Peak memory 204120 kb
Host smart-2e8b0b43-9a27-4de6-a1a2-4c43fbe41bf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768950414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.3768950414
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.609761865
Short name T1349
Test name
Test status
Simulation time 55082248 ps
CPU time 0.62 seconds
Started Apr 28 01:01:24 PM PDT 24
Finished Apr 28 01:01:26 PM PDT 24
Peak memory 203860 kb
Host smart-2c0ef462-65c2-4978-9c5c-eeb576c641d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609761865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.609761865
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.3051240365
Short name T533
Test name
Test status
Simulation time 89236275 ps
CPU time 1.55 seconds
Started Apr 28 01:01:20 PM PDT 24
Finished Apr 28 01:01:22 PM PDT 24
Peak memory 212508 kb
Host smart-ff3e69c4-b909-4b83-bffb-5df7caf35d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051240365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3051240365
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.1540489934
Short name T653
Test name
Test status
Simulation time 490170975 ps
CPU time 8.64 seconds
Started Apr 28 01:01:18 PM PDT 24
Finished Apr 28 01:01:27 PM PDT 24
Peak memory 300312 kb
Host smart-e7906c05-a4b8-4b0b-8751-b6d27cd4204c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540489934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.1540489934
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.3506906273
Short name T107
Test name
Test status
Simulation time 8014367934 ps
CPU time 40.99 seconds
Started Apr 28 01:01:22 PM PDT 24
Finished Apr 28 01:02:03 PM PDT 24
Peak memory 501988 kb
Host smart-d1745522-b1c8-4dfc-9bd2-27899a1f043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506906273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3506906273
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.4127654198
Short name T587
Test name
Test status
Simulation time 1309139411 ps
CPU time 33.79 seconds
Started Apr 28 01:01:19 PM PDT 24
Finished Apr 28 01:01:54 PM PDT 24
Peak memory 515128 kb
Host smart-15de4e90-8a69-4133-a679-479bfcf71c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127654198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.4127654198
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2378439417
Short name T1202
Test name
Test status
Simulation time 86952567 ps
CPU time 0.85 seconds
Started Apr 28 01:01:23 PM PDT 24
Finished Apr 28 01:01:24 PM PDT 24
Peak memory 203956 kb
Host smart-721aab64-2d9e-43d6-bac5-b33723df5d67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378439417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.2378439417
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.137355478
Short name T690
Test name
Test status
Simulation time 266945868 ps
CPU time 5.24 seconds
Started Apr 28 01:01:22 PM PDT 24
Finished Apr 28 01:01:28 PM PDT 24
Peak memory 204024 kb
Host smart-9e72d14a-087c-464d-8f93-4ed929d59e47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137355478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.
137355478
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3601580116
Short name T1271
Test name
Test status
Simulation time 6050390904 ps
CPU time 174.96 seconds
Started Apr 28 01:01:21 PM PDT 24
Finished Apr 28 01:04:16 PM PDT 24
Peak memory 823104 kb
Host smart-57a50d1a-ec68-4ffb-ad21-25e74d32dbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601580116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3601580116
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.706068512
Short name T1039
Test name
Test status
Simulation time 336460866 ps
CPU time 7.2 seconds
Started Apr 28 01:01:23 PM PDT 24
Finished Apr 28 01:01:31 PM PDT 24
Peak memory 204060 kb
Host smart-c62d66fe-725f-4aba-9d76-ff143692c91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706068512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.706068512
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.2754250528
Short name T330
Test name
Test status
Simulation time 2034394007 ps
CPU time 18.97 seconds
Started Apr 28 01:01:23 PM PDT 24
Finished Apr 28 01:01:43 PM PDT 24
Peak memory 314968 kb
Host smart-85b69821-5de6-4e23-8721-35bfb5cb0478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754250528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.2754250528
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.1455232430
Short name T604
Test name
Test status
Simulation time 21344025 ps
CPU time 0.64 seconds
Started Apr 28 01:01:18 PM PDT 24
Finished Apr 28 01:01:19 PM PDT 24
Peak memory 203728 kb
Host smart-15d4dda8-15a5-4f24-9908-41d0094b3a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455232430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.1455232430
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.1912829157
Short name T575
Test name
Test status
Simulation time 26805951545 ps
CPU time 74.82 seconds
Started Apr 28 01:01:18 PM PDT 24
Finished Apr 28 01:02:34 PM PDT 24
Peak memory 273012 kb
Host smart-641f085e-176f-4892-99a7-c7cd7bff6ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912829157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.1912829157
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.2856372221
Short name T1233
Test name
Test status
Simulation time 1405120468 ps
CPU time 19.4 seconds
Started Apr 28 01:01:14 PM PDT 24
Finished Apr 28 01:01:34 PM PDT 24
Peak memory 313880 kb
Host smart-ceac1fa4-89f0-4988-b776-ec0bb10fdd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856372221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.2856372221
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.1796315729
Short name T1316
Test name
Test status
Simulation time 106757254250 ps
CPU time 185.34 seconds
Started Apr 28 01:01:18 PM PDT 24
Finished Apr 28 01:04:24 PM PDT 24
Peak memory 844452 kb
Host smart-80b03fc5-b7d7-4837-8ded-1cd3e1957de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796315729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.1796315729
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.1901034646
Short name T930
Test name
Test status
Simulation time 649193861 ps
CPU time 30.78 seconds
Started Apr 28 01:01:19 PM PDT 24
Finished Apr 28 01:01:51 PM PDT 24
Peak memory 212400 kb
Host smart-cc870fdb-93b5-4dbc-a9c6-92b93f9197b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901034646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.1901034646
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.4196017723
Short name T1327
Test name
Test status
Simulation time 3968017414 ps
CPU time 4.65 seconds
Started Apr 28 01:01:28 PM PDT 24
Finished Apr 28 01:01:34 PM PDT 24
Peak memory 212580 kb
Host smart-2e24da53-5a41-4fe2-874e-c066f05f56f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196017723 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.4196017723
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.75091391
Short name T884
Test name
Test status
Simulation time 10044112410 ps
CPU time 47.48 seconds
Started Apr 28 01:01:19 PM PDT 24
Finished Apr 28 01:02:07 PM PDT 24
Peak memory 357924 kb
Host smart-86a94af0-4e27-4f4b-8377-d34ee910bdc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75091391 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_fifo_reset_acq.75091391
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.3930328463
Short name T766
Test name
Test status
Simulation time 398410856 ps
CPU time 2.63 seconds
Started Apr 28 01:01:28 PM PDT 24
Finished Apr 28 01:01:32 PM PDT 24
Peak memory 204164 kb
Host smart-24a02aea-8807-429d-807d-918b778ae3f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930328463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.3930328463
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.2130166526
Short name T827
Test name
Test status
Simulation time 2998313406 ps
CPU time 4.45 seconds
Started Apr 28 01:01:22 PM PDT 24
Finished Apr 28 01:01:27 PM PDT 24
Peak memory 204208 kb
Host smart-8897ff51-5dd8-4e76-b18f-de2f442fe41c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130166526 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.2130166526
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.3478826876
Short name T1106
Test name
Test status
Simulation time 5635850445 ps
CPU time 6.79 seconds
Started Apr 28 01:01:26 PM PDT 24
Finished Apr 28 01:01:33 PM PDT 24
Peak memory 204216 kb
Host smart-e8fa8be4-d1ed-4c45-9539-f0732cdeb924
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478826876 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.3478826876
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.3544074108
Short name T1013
Test name
Test status
Simulation time 1654147500 ps
CPU time 5.34 seconds
Started Apr 28 01:01:22 PM PDT 24
Finished Apr 28 01:01:28 PM PDT 24
Peak memory 203944 kb
Host smart-607ae73a-09c5-49af-aaf1-2692dcb006f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544074108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.3544074108
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.547806674
Short name T13
Test name
Test status
Simulation time 102474822578 ps
CPU time 36.07 seconds
Started Apr 28 01:01:28 PM PDT 24
Finished Apr 28 01:02:05 PM PDT 24
Peak memory 251540 kb
Host smart-d7b974ee-ac03-4da9-af02-3e16fc73f156
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547806674 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.i2c_target_stress_all.547806674
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.3759340253
Short name T1148
Test name
Test status
Simulation time 779690013 ps
CPU time 11.1 seconds
Started Apr 28 01:01:19 PM PDT 24
Finished Apr 28 01:01:31 PM PDT 24
Peak memory 215436 kb
Host smart-2a2d91bf-0af5-4e2a-b0de-2aea61b8c929
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759340253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.3759340253
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.1357327616
Short name T311
Test name
Test status
Simulation time 28744148286 ps
CPU time 161.68 seconds
Started Apr 28 01:01:19 PM PDT 24
Finished Apr 28 01:04:01 PM PDT 24
Peak memory 2139520 kb
Host smart-6cd8e5aa-7ae9-44a8-9778-5b2540891cbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357327616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.1357327616
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.723962358
Short name T891
Test name
Test status
Simulation time 32031448513 ps
CPU time 2634.15 seconds
Started Apr 28 01:01:18 PM PDT 24
Finished Apr 28 01:45:14 PM PDT 24
Peak memory 7693260 kb
Host smart-b7a6b97a-4abc-462e-a8c8-86b054e95720
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723962358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_t
arget_stretch.723962358
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3070013447
Short name T1226
Test name
Test status
Simulation time 3174977934 ps
CPU time 6.39 seconds
Started Apr 28 01:01:18 PM PDT 24
Finished Apr 28 01:01:25 PM PDT 24
Peak memory 204276 kb
Host smart-88579f73-7c02-49e5-9036-f5483c948d98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070013447 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3070013447
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.2984899293
Short name T1184
Test name
Test status
Simulation time 24990347 ps
CPU time 0.62 seconds
Started Apr 28 01:01:30 PM PDT 24
Finished Apr 28 01:01:31 PM PDT 24
Peak memory 203924 kb
Host smart-9e2b1eed-1be0-430d-bb5e-d8c5e1d61a08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984899293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.2984899293
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.2080362743
Short name T1251
Test name
Test status
Simulation time 88158744 ps
CPU time 1.31 seconds
Started Apr 28 01:01:23 PM PDT 24
Finished Apr 28 01:01:25 PM PDT 24
Peak memory 212468 kb
Host smart-aeea9f54-9631-49f6-9629-a64f209395f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080362743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.2080362743
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.1660410494
Short name T272
Test name
Test status
Simulation time 295678352 ps
CPU time 5.25 seconds
Started Apr 28 01:01:23 PM PDT 24
Finished Apr 28 01:01:29 PM PDT 24
Peak memory 254936 kb
Host smart-6287dcf8-d6d9-474f-9240-ba216375a887
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660410494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.1660410494
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.2976465504
Short name T738
Test name
Test status
Simulation time 1355797372 ps
CPU time 43.05 seconds
Started Apr 28 01:01:22 PM PDT 24
Finished Apr 28 01:02:06 PM PDT 24
Peak memory 516768 kb
Host smart-ea235181-9961-44d7-a422-3c05680c7c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976465504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.2976465504
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.3125171944
Short name T729
Test name
Test status
Simulation time 1388024485 ps
CPU time 31.72 seconds
Started Apr 28 01:01:25 PM PDT 24
Finished Apr 28 01:01:58 PM PDT 24
Peak memory 422584 kb
Host smart-48c42e56-fd38-4e36-89ba-529a92c43871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125171944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3125171944
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.3481849561
Short name T229
Test name
Test status
Simulation time 82734819 ps
CPU time 1.04 seconds
Started Apr 28 01:01:24 PM PDT 24
Finished Apr 28 01:01:27 PM PDT 24
Peak memory 203980 kb
Host smart-7ac577b1-d0d0-4a0d-9f73-8674ebfd54ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481849561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.3481849561
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.398578757
Short name T377
Test name
Test status
Simulation time 177381136 ps
CPU time 2.34 seconds
Started Apr 28 01:01:24 PM PDT 24
Finished Apr 28 01:01:27 PM PDT 24
Peak memory 204152 kb
Host smart-726b3602-04d7-4d15-aa0f-fc68ba9b389e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398578757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.
398578757
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.2691329116
Short name T177
Test name
Test status
Simulation time 2340558854 ps
CPU time 49.45 seconds
Started Apr 28 01:01:25 PM PDT 24
Finished Apr 28 01:02:15 PM PDT 24
Peak memory 759608 kb
Host smart-0d931df9-5bf2-4324-ac23-0c0cfdff81fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691329116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.2691329116
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.3013555055
Short name T616
Test name
Test status
Simulation time 1652678137 ps
CPU time 17.02 seconds
Started Apr 28 01:01:29 PM PDT 24
Finished Apr 28 01:01:47 PM PDT 24
Peak memory 204196 kb
Host smart-59770f01-b1fc-4287-8ba7-61f2d00800c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013555055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.3013555055
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.2365060044
Short name T496
Test name
Test status
Simulation time 1630568682 ps
CPU time 31.71 seconds
Started Apr 28 01:01:31 PM PDT 24
Finished Apr 28 01:02:03 PM PDT 24
Peak memory 367560 kb
Host smart-10922a43-adb4-427d-80c4-c6d65baa889f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365060044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.2365060044
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.144781606
Short name T332
Test name
Test status
Simulation time 28239060 ps
CPU time 0.65 seconds
Started Apr 28 01:01:23 PM PDT 24
Finished Apr 28 01:01:24 PM PDT 24
Peak memory 203804 kb
Host smart-66f00820-c83b-4333-b8fc-9c8b1e2f683b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144781606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.144781606
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.94835443
Short name T1268
Test name
Test status
Simulation time 7650783039 ps
CPU time 160.18 seconds
Started Apr 28 01:01:24 PM PDT 24
Finished Apr 28 01:04:06 PM PDT 24
Peak memory 278212 kb
Host smart-a9958b77-9e55-45d4-ab5c-e4e2b93066b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94835443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.94835443
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.3574541134
Short name T1127
Test name
Test status
Simulation time 1111025092 ps
CPU time 53.9 seconds
Started Apr 28 01:01:29 PM PDT 24
Finished Apr 28 01:02:24 PM PDT 24
Peak memory 332304 kb
Host smart-2a3aa33d-8b0a-457b-adda-fc9523059c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574541134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.3574541134
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.1353582771
Short name T1215
Test name
Test status
Simulation time 11873097677 ps
CPU time 143.99 seconds
Started Apr 28 01:01:24 PM PDT 24
Finished Apr 28 01:03:49 PM PDT 24
Peak memory 426104 kb
Host smart-9102941d-7945-49c3-8f24-4e755eea37b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353582771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.1353582771
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.1220901465
Short name T1293
Test name
Test status
Simulation time 2583787819 ps
CPU time 19.85 seconds
Started Apr 28 01:01:28 PM PDT 24
Finished Apr 28 01:01:48 PM PDT 24
Peak memory 212508 kb
Host smart-d5afbbde-41a6-465c-85c6-ae8bec6df646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220901465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.1220901465
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.3349444364
Short name T1186
Test name
Test status
Simulation time 2199179967 ps
CPU time 2.45 seconds
Started Apr 28 01:01:28 PM PDT 24
Finished Apr 28 01:01:32 PM PDT 24
Peak memory 204088 kb
Host smart-c6167452-893e-4963-a085-cb16cd99b796
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349444364 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.3349444364
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.3003641360
Short name T751
Test name
Test status
Simulation time 10082500835 ps
CPU time 64.93 seconds
Started Apr 28 01:01:34 PM PDT 24
Finished Apr 28 01:02:39 PM PDT 24
Peak memory 407868 kb
Host smart-2929db0e-5c03-44d9-b6d9-9ea862c6fd68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003641360 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.3003641360
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.3177575897
Short name T957
Test name
Test status
Simulation time 10389300647 ps
CPU time 8.81 seconds
Started Apr 28 01:01:32 PM PDT 24
Finished Apr 28 01:01:41 PM PDT 24
Peak memory 248668 kb
Host smart-abe4b94a-fc52-4b82-b5ee-bea96376422f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177575897 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.3177575897
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.826118743
Short name T25
Test name
Test status
Simulation time 1615451840 ps
CPU time 2.26 seconds
Started Apr 28 01:01:33 PM PDT 24
Finished Apr 28 01:01:35 PM PDT 24
Peak memory 204208 kb
Host smart-26305955-0b9e-4c7d-acfc-63e03343b017
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826118743 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.i2c_target_hrst.826118743
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.3032403531
Short name T505
Test name
Test status
Simulation time 2978294441 ps
CPU time 4.45 seconds
Started Apr 28 01:01:28 PM PDT 24
Finished Apr 28 01:01:33 PM PDT 24
Peak memory 204260 kb
Host smart-6de583cf-e7d9-4e57-83e1-d0b7872bf509
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032403531 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.3032403531
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.3431319828
Short name T1167
Test name
Test status
Simulation time 4182419104 ps
CPU time 2.44 seconds
Started Apr 28 01:01:28 PM PDT 24
Finished Apr 28 01:01:32 PM PDT 24
Peak memory 204060 kb
Host smart-fd728852-c2bf-4f1b-acbe-54eac417dce5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431319828 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.3431319828
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.2325843031
Short name T296
Test name
Test status
Simulation time 1997342857 ps
CPU time 18.49 seconds
Started Apr 28 01:01:23 PM PDT 24
Finished Apr 28 01:01:42 PM PDT 24
Peak memory 204044 kb
Host smart-58c12a51-8d74-49ca-8b50-66c79a00cb9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325843031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.2325843031
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.2957011106
Short name T806
Test name
Test status
Simulation time 1610807032 ps
CPU time 69.32 seconds
Started Apr 28 01:01:24 PM PDT 24
Finished Apr 28 01:02:35 PM PDT 24
Peak memory 207556 kb
Host smart-e7be3e0a-f84c-4f78-a9fe-8e2147bdd2e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957011106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.2957011106
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.1205385703
Short name T682
Test name
Test status
Simulation time 8335847757 ps
CPU time 4.52 seconds
Started Apr 28 01:01:24 PM PDT 24
Finished Apr 28 01:01:29 PM PDT 24
Peak memory 204204 kb
Host smart-e685e3f4-751b-4854-9601-b0c342a990f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205385703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.1205385703
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.2421426793
Short name T337
Test name
Test status
Simulation time 27049401088 ps
CPU time 526.4 seconds
Started Apr 28 01:01:25 PM PDT 24
Finished Apr 28 01:10:12 PM PDT 24
Peak memory 1514812 kb
Host smart-bf034b2d-752b-49b0-b43e-9bcf6eceeed3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421426793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.2421426793
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.1632263038
Short name T987
Test name
Test status
Simulation time 2725825468 ps
CPU time 6.99 seconds
Started Apr 28 01:01:28 PM PDT 24
Finished Apr 28 01:01:36 PM PDT 24
Peak memory 212452 kb
Host smart-bf0063f4-ce53-47e2-9267-4520deba3ca8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632263038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.1632263038
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3807260718
Short name T417
Test name
Test status
Simulation time 34415862 ps
CPU time 0.62 seconds
Started Apr 28 01:01:36 PM PDT 24
Finished Apr 28 01:01:38 PM PDT 24
Peak memory 203800 kb
Host smart-562982d9-02cf-42f0-a5f6-1c72d1c35290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807260718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3807260718
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.1242359332
Short name T1059
Test name
Test status
Simulation time 161485665 ps
CPU time 1.54 seconds
Started Apr 28 01:01:28 PM PDT 24
Finished Apr 28 01:01:31 PM PDT 24
Peak memory 212332 kb
Host smart-52a64fdf-2151-4baa-ab4c-41d459f04682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242359332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.1242359332
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.3443482509
Short name T473
Test name
Test status
Simulation time 1209484469 ps
CPU time 5.63 seconds
Started Apr 28 01:01:30 PM PDT 24
Finished Apr 28 01:01:36 PM PDT 24
Peak memory 265108 kb
Host smart-c932a519-4867-413f-a64c-bf7e0eb298b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443482509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.3443482509
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.2162240317
Short name T529
Test name
Test status
Simulation time 2366321716 ps
CPU time 90.17 seconds
Started Apr 28 01:01:29 PM PDT 24
Finished Apr 28 01:03:00 PM PDT 24
Peak memory 770196 kb
Host smart-ca4fcd2d-33f2-4a14-8c51-2b0c2e446876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162240317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.2162240317
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.2706270749
Short name T94
Test name
Test status
Simulation time 1188618818 ps
CPU time 79.18 seconds
Started Apr 28 01:01:30 PM PDT 24
Finished Apr 28 01:02:50 PM PDT 24
Peak memory 484244 kb
Host smart-ae407f06-48d5-443e-ab43-d37b2bb9cbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706270749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.2706270749
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1630827207
Short name T367
Test name
Test status
Simulation time 655523988 ps
CPU time 0.91 seconds
Started Apr 28 01:01:30 PM PDT 24
Finished Apr 28 01:01:31 PM PDT 24
Peak memory 203972 kb
Host smart-df4659bd-df4b-4ff8-86ff-1aadab75f499
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630827207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1630827207
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.2923679011
Short name T121
Test name
Test status
Simulation time 128721060 ps
CPU time 3.13 seconds
Started Apr 28 01:01:28 PM PDT 24
Finished Apr 28 01:01:32 PM PDT 24
Peak memory 221896 kb
Host smart-93286043-bbe7-4f31-8172-9b553c16dc34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923679011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.2923679011
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.1029620487
Short name T756
Test name
Test status
Simulation time 8970451484 ps
CPU time 337.12 seconds
Started Apr 28 01:01:29 PM PDT 24
Finished Apr 28 01:07:07 PM PDT 24
Peak memory 1276840 kb
Host smart-29c0b3e4-03e7-4f5a-aab7-e44e6eec2ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029620487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1029620487
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.1946278826
Short name T1047
Test name
Test status
Simulation time 390261529 ps
CPU time 14.75 seconds
Started Apr 28 01:01:34 PM PDT 24
Finished Apr 28 01:01:50 PM PDT 24
Peak memory 204152 kb
Host smart-e97f3249-8db3-48d9-8841-4c1ded9d1266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946278826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.1946278826
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.3749572422
Short name T954
Test name
Test status
Simulation time 1854945025 ps
CPU time 36.14 seconds
Started Apr 28 01:01:34 PM PDT 24
Finished Apr 28 01:02:11 PM PDT 24
Peak memory 358220 kb
Host smart-8b2a27ae-10b2-4332-a4c8-492023bc0f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749572422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.3749572422
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.4126049680
Short name T923
Test name
Test status
Simulation time 17096135 ps
CPU time 0.63 seconds
Started Apr 28 01:01:30 PM PDT 24
Finished Apr 28 01:01:32 PM PDT 24
Peak memory 203740 kb
Host smart-e3cd1221-2b9a-4fde-9ce1-55d47e78e987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126049680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.4126049680
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.2078742598
Short name T458
Test name
Test status
Simulation time 2862751806 ps
CPU time 30.39 seconds
Started Apr 28 01:01:30 PM PDT 24
Finished Apr 28 01:02:01 PM PDT 24
Peak memory 204172 kb
Host smart-2c5af7b3-3efd-4e60-a51f-f732f0a20b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078742598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.2078742598
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.2778638146
Short name T482
Test name
Test status
Simulation time 4338992145 ps
CPU time 13.14 seconds
Started Apr 28 01:01:32 PM PDT 24
Finished Apr 28 01:01:45 PM PDT 24
Peak memory 244756 kb
Host smart-9d60b3c5-0a17-42fe-8ca7-1c7870f435d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778638146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.2778638146
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.3001435181
Short name T768
Test name
Test status
Simulation time 406391921 ps
CPU time 6.4 seconds
Started Apr 28 01:01:32 PM PDT 24
Finished Apr 28 01:01:38 PM PDT 24
Peak memory 215612 kb
Host smart-2c53a43a-100e-481e-968d-3ffd4d36e628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001435181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.3001435181
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.1432176237
Short name T375
Test name
Test status
Simulation time 2494893488 ps
CPU time 2.46 seconds
Started Apr 28 01:01:35 PM PDT 24
Finished Apr 28 01:01:38 PM PDT 24
Peak memory 204168 kb
Host smart-d3d1d550-ecd8-4c62-8d00-848e744d69b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432176237 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.1432176237
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.4272631902
Short name T969
Test name
Test status
Simulation time 10238107338 ps
CPU time 13.48 seconds
Started Apr 28 01:01:35 PM PDT 24
Finished Apr 28 01:01:49 PM PDT 24
Peak memory 252884 kb
Host smart-20ab09bf-634b-4a45-9740-504784654573
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272631902 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.4272631902
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3710646962
Short name T336
Test name
Test status
Simulation time 10380948724 ps
CPU time 14.77 seconds
Started Apr 28 01:01:34 PM PDT 24
Finished Apr 28 01:01:49 PM PDT 24
Peak memory 289520 kb
Host smart-014f4dd3-3c77-4d6f-9731-6da6650d9d5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710646962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3710646962
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.2993947774
Short name T409
Test name
Test status
Simulation time 634968970 ps
CPU time 2.52 seconds
Started Apr 28 01:01:34 PM PDT 24
Finished Apr 28 01:01:37 PM PDT 24
Peak memory 204120 kb
Host smart-5a1685d7-8975-4403-906e-574a87e8d12d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993947774 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.2993947774
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.601329394
Short name T544
Test name
Test status
Simulation time 3090368450 ps
CPU time 2.83 seconds
Started Apr 28 01:01:35 PM PDT 24
Finished Apr 28 01:01:39 PM PDT 24
Peak memory 204200 kb
Host smart-7a30e73d-c3b5-4d5d-9cde-1523a608d2e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601329394 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_intr_smoke.601329394
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.3524638328
Short name T1142
Test name
Test status
Simulation time 19627879946 ps
CPU time 52.66 seconds
Started Apr 28 01:01:37 PM PDT 24
Finished Apr 28 01:02:31 PM PDT 24
Peak memory 1153096 kb
Host smart-e4529306-9c4f-43f8-905d-95c81eb6be73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524638328 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.3524638328
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.74457530
Short name T1114
Test name
Test status
Simulation time 1632195218 ps
CPU time 10.34 seconds
Started Apr 28 01:01:29 PM PDT 24
Finished Apr 28 01:01:40 PM PDT 24
Peak memory 203988 kb
Host smart-513f27d9-6ced-4f1a-b914-7ac6f8cd8bf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74457530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_targ
et_smoke.74457530
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.3749695656
Short name T1117
Test name
Test status
Simulation time 3314263650 ps
CPU time 12.56 seconds
Started Apr 28 01:01:37 PM PDT 24
Finished Apr 28 01:01:51 PM PDT 24
Peak memory 213864 kb
Host smart-dbb6cde6-1740-44ab-8b29-7bdc53ce4243
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749695656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.3749695656
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.561154675
Short name T1149
Test name
Test status
Simulation time 10813250616 ps
CPU time 22.56 seconds
Started Apr 28 01:01:36 PM PDT 24
Finished Apr 28 01:02:00 PM PDT 24
Peak memory 204120 kb
Host smart-741ba163-7c2c-4c3b-b247-dbebd50b5637
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561154675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_wr.561154675
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.3273649281
Short name T282
Test name
Test status
Simulation time 37305419887 ps
CPU time 262.64 seconds
Started Apr 28 01:01:35 PM PDT 24
Finished Apr 28 01:05:58 PM PDT 24
Peak memory 1874544 kb
Host smart-ad36aa47-5cff-47c0-b699-db3e0e9df521
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273649281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.3273649281
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.3002584792
Short name T642
Test name
Test status
Simulation time 21944091741 ps
CPU time 6.68 seconds
Started Apr 28 01:01:37 PM PDT 24
Finished Apr 28 01:01:45 PM PDT 24
Peak memory 220044 kb
Host smart-7fe32b60-e0d2-4c23-ab66-9a98bb654727
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002584792 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.3002584792
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.1108508190
Short name T110
Test name
Test status
Simulation time 24914082 ps
CPU time 0.59 seconds
Started Apr 28 12:59:09 PM PDT 24
Finished Apr 28 12:59:14 PM PDT 24
Peak memory 203796 kb
Host smart-a36274c1-35e3-44c5-bfeb-228c9638174c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108508190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.1108508190
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3948782546
Short name T365
Test name
Test status
Simulation time 68686493 ps
CPU time 1.19 seconds
Started Apr 28 12:59:14 PM PDT 24
Finished Apr 28 12:59:17 PM PDT 24
Peak memory 215164 kb
Host smart-582656ae-7ca3-4d8e-b1ef-3f2676cc013e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948782546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3948782546
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2722377932
Short name T269
Test name
Test status
Simulation time 331286804 ps
CPU time 7.4 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 12:59:12 PM PDT 24
Peak memory 275168 kb
Host smart-8d433b32-838b-4f16-9c4f-31d9f7b9bee4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722377932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2722377932
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.255057100
Short name T671
Test name
Test status
Simulation time 5109245835 ps
CPU time 129.13 seconds
Started Apr 28 12:58:59 PM PDT 24
Finished Apr 28 01:01:09 PM PDT 24
Peak memory 614484 kb
Host smart-184ec105-e9ae-4333-bca8-64c359be5e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255057100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.255057100
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.2912540198
Short name T967
Test name
Test status
Simulation time 9397776097 ps
CPU time 69.01 seconds
Started Apr 28 12:58:52 PM PDT 24
Finished Apr 28 01:00:02 PM PDT 24
Peak memory 767652 kb
Host smart-1750a7d0-eaed-4630-b987-5957befe01b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912540198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.2912540198
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.975997127
Short name T444
Test name
Test status
Simulation time 88608618 ps
CPU time 0.94 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 12:59:06 PM PDT 24
Peak memory 203980 kb
Host smart-7bcca481-0e3f-4024-9ec2-84d39ac7a640
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975997127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt
.975997127
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.261269147
Short name T521
Test name
Test status
Simulation time 774614376 ps
CPU time 5.02 seconds
Started Apr 28 12:58:52 PM PDT 24
Finished Apr 28 12:58:58 PM PDT 24
Peak memory 237396 kb
Host smart-7d5e7bf7-8e33-49f4-a7cf-1e6d95d26585
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261269147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.261269147
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.1291202593
Short name T2
Test name
Test status
Simulation time 13727604121 ps
CPU time 102.18 seconds
Started Apr 28 12:58:53 PM PDT 24
Finished Apr 28 01:00:36 PM PDT 24
Peak memory 1057216 kb
Host smart-b818eb99-a2ea-4327-ada2-4793851e9620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291202593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1291202593
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.3835527650
Short name T1189
Test name
Test status
Simulation time 398898035 ps
CPU time 5.98 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 12:59:11 PM PDT 24
Peak memory 204168 kb
Host smart-26d195b4-0949-46f3-a935-773db9f1fa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835527650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.3835527650
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.3002741248
Short name T402
Test name
Test status
Simulation time 2148086911 ps
CPU time 20.39 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 12:59:25 PM PDT 24
Peak memory 277252 kb
Host smart-f8de444d-aebb-4545-b020-7a05e9dd83da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002741248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.3002741248
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.3360924694
Short name T1347
Test name
Test status
Simulation time 43406002 ps
CPU time 0.64 seconds
Started Apr 28 12:58:55 PM PDT 24
Finished Apr 28 12:58:56 PM PDT 24
Peak memory 203864 kb
Host smart-f3f6e188-c3d9-431b-802f-20dce80011ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360924694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3360924694
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.1120632791
Short name T1113
Test name
Test status
Simulation time 3055815538 ps
CPU time 68.83 seconds
Started Apr 28 12:59:10 PM PDT 24
Finished Apr 28 01:00:23 PM PDT 24
Peak memory 262656 kb
Host smart-4c4d6f97-4df3-4f92-a7c8-b2d65576ec1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120632791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.1120632791
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.3215989942
Short name T665
Test name
Test status
Simulation time 6758285643 ps
CPU time 32.52 seconds
Started Apr 28 12:58:55 PM PDT 24
Finished Apr 28 12:59:28 PM PDT 24
Peak memory 360236 kb
Host smart-b872c686-f6cd-4b51-8f47-f5874a3f250d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215989942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.3215989942
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.3677626908
Short name T1137
Test name
Test status
Simulation time 7271339597 ps
CPU time 663.68 seconds
Started Apr 28 12:59:04 PM PDT 24
Finished Apr 28 01:10:10 PM PDT 24
Peak memory 1513368 kb
Host smart-a67382aa-1566-4f5d-bfaf-d7c0e42878f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677626908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.3677626908
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.4053587350
Short name T430
Test name
Test status
Simulation time 1538326460 ps
CPU time 7.53 seconds
Started Apr 28 12:59:04 PM PDT 24
Finished Apr 28 12:59:14 PM PDT 24
Peak memory 212392 kb
Host smart-216586d0-c960-47b5-98cf-f03a3957146f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053587350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.4053587350
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.3469744188
Short name T117
Test name
Test status
Simulation time 98083090 ps
CPU time 1.04 seconds
Started Apr 28 12:59:07 PM PDT 24
Finished Apr 28 12:59:10 PM PDT 24
Peak memory 222340 kb
Host smart-3eea6298-748c-408f-91a7-08f5128da15e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469744188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.3469744188
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.852853934
Short name T640
Test name
Test status
Simulation time 942864506 ps
CPU time 4.45 seconds
Started Apr 28 12:59:07 PM PDT 24
Finished Apr 28 12:59:13 PM PDT 24
Peak memory 203988 kb
Host smart-9b22b4d3-164f-46ae-99f6-a2ea95484595
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852853934 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.852853934
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.2209830101
Short name T55
Test name
Test status
Simulation time 10132820825 ps
CPU time 8.16 seconds
Started Apr 28 12:59:09 PM PDT 24
Finished Apr 28 12:59:21 PM PDT 24
Peak memory 258656 kb
Host smart-1ce55d42-925f-4f8b-aed9-d6d76ac85c4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209830101 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.2209830101
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.2805238168
Short name T688
Test name
Test status
Simulation time 10166936070 ps
CPU time 2.97 seconds
Started Apr 28 12:59:12 PM PDT 24
Finished Apr 28 12:59:18 PM PDT 24
Peak memory 204160 kb
Host smart-8015361a-d403-4a90-b450-ca0ef7efac40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805238168 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.2805238168
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3463873253
Short name T353
Test name
Test status
Simulation time 4036641414 ps
CPU time 5.33 seconds
Started Apr 28 12:59:07 PM PDT 24
Finished Apr 28 12:59:14 PM PDT 24
Peak memory 212412 kb
Host smart-9ca2e6e6-fef3-4315-968b-7bd4d2c6a94b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463873253 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3463873253
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.2321888293
Short name T846
Test name
Test status
Simulation time 10691437766 ps
CPU time 12.85 seconds
Started Apr 28 12:59:07 PM PDT 24
Finished Apr 28 12:59:23 PM PDT 24
Peak memory 517380 kb
Host smart-bd14e82d-440e-49dc-b606-7a0fc647f426
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321888293 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.2321888293
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.510634071
Short name T879
Test name
Test status
Simulation time 4923030437 ps
CPU time 24.06 seconds
Started Apr 28 12:58:54 PM PDT 24
Finished Apr 28 12:59:18 PM PDT 24
Peak memory 204144 kb
Host smart-28268aaa-82ee-4dcc-88d7-dbfe2b8ca7f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510634071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_targ
et_smoke.510634071
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.423263471
Short name T1193
Test name
Test status
Simulation time 16493297380 ps
CPU time 26.04 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 12:59:32 PM PDT 24
Peak memory 228568 kb
Host smart-b71463a4-e53a-473a-b135-19328f589f82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423263471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_rd.423263471
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.415705506
Short name T588
Test name
Test status
Simulation time 31346114086 ps
CPU time 87.33 seconds
Started Apr 28 12:58:57 PM PDT 24
Finished Apr 28 01:00:26 PM PDT 24
Peak memory 1475536 kb
Host smart-ef60726e-dbf1-49a8-b125-17485ec7a971
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415705506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_wr.415705506
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.102436024
Short name T897
Test name
Test status
Simulation time 1437981184 ps
CPU time 7.52 seconds
Started Apr 28 12:59:08 PM PDT 24
Finished Apr 28 12:59:18 PM PDT 24
Peak memory 220432 kb
Host smart-da61f0ea-b2cb-45d7-a52b-ccf8ae84a361
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102436024 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_timeout.102436024
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.1683213718
Short name T850
Test name
Test status
Simulation time 15256768 ps
CPU time 0.6 seconds
Started Apr 28 01:01:45 PM PDT 24
Finished Apr 28 01:01:46 PM PDT 24
Peak memory 203852 kb
Host smart-9d9cb32a-9e19-4c9b-9cc9-a47fa53f1920
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683213718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1683213718
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.3466631893
Short name T563
Test name
Test status
Simulation time 95879065 ps
CPU time 1.45 seconds
Started Apr 28 01:01:38 PM PDT 24
Finished Apr 28 01:01:40 PM PDT 24
Peak memory 215300 kb
Host smart-5163f549-bdac-46bb-8569-d414e4de7c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466631893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.3466631893
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.4010296147
Short name T268
Test name
Test status
Simulation time 3271814889 ps
CPU time 8.08 seconds
Started Apr 28 01:01:37 PM PDT 24
Finished Apr 28 01:01:45 PM PDT 24
Peak memory 234756 kb
Host smart-ae520e34-acdf-4dd4-af66-12ad447649cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010296147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.4010296147
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.4095951821
Short name T976
Test name
Test status
Simulation time 2217416104 ps
CPU time 152.06 seconds
Started Apr 28 01:01:36 PM PDT 24
Finished Apr 28 01:04:08 PM PDT 24
Peak memory 628448 kb
Host smart-d401d8c5-05e5-45ea-baff-b43ae39c54ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095951821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.4095951821
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.831450831
Short name T469
Test name
Test status
Simulation time 12092893808 ps
CPU time 179.22 seconds
Started Apr 28 01:01:36 PM PDT 24
Finished Apr 28 01:04:36 PM PDT 24
Peak memory 747992 kb
Host smart-1d7119d8-2f74-4df8-ad20-17f9a269ac8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831450831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.831450831
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.3563577309
Short name T1309
Test name
Test status
Simulation time 705536379 ps
CPU time 1.2 seconds
Started Apr 28 01:01:35 PM PDT 24
Finished Apr 28 01:01:37 PM PDT 24
Peak memory 204208 kb
Host smart-22d9d8d6-9df0-4f28-82c1-e0c4a4ec6552
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563577309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.3563577309
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.4195206305
Short name T119
Test name
Test status
Simulation time 174159578 ps
CPU time 8.26 seconds
Started Apr 28 01:01:35 PM PDT 24
Finished Apr 28 01:01:44 PM PDT 24
Peak memory 204124 kb
Host smart-9c3f6dd7-6374-46bc-a55a-02840628c108
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195206305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.4195206305
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.3868630597
Short name T1310
Test name
Test status
Simulation time 18372394068 ps
CPU time 316.46 seconds
Started Apr 28 01:01:37 PM PDT 24
Finished Apr 28 01:06:54 PM PDT 24
Peak memory 1187540 kb
Host smart-c9f286be-423b-48cf-8ead-8a673e36f47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868630597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3868630597
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.2307067652
Short name T672
Test name
Test status
Simulation time 456884482 ps
CPU time 5.36 seconds
Started Apr 28 01:01:45 PM PDT 24
Finished Apr 28 01:01:51 PM PDT 24
Peak memory 204132 kb
Host smart-9b2fff83-0681-4406-98d6-087c2c90f85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307067652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.2307067652
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.995630976
Short name T1258
Test name
Test status
Simulation time 9039043761 ps
CPU time 27.37 seconds
Started Apr 28 01:01:46 PM PDT 24
Finished Apr 28 01:02:14 PM PDT 24
Peak memory 414540 kb
Host smart-c4532208-5412-4339-a0d8-55c48ee24663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995630976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.995630976
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.3336561533
Short name T1267
Test name
Test status
Simulation time 19489512 ps
CPU time 0.64 seconds
Started Apr 28 01:01:35 PM PDT 24
Finished Apr 28 01:01:36 PM PDT 24
Peak memory 203860 kb
Host smart-cd8d774a-9e8e-4860-88c6-65f1e973b266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336561533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3336561533
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.2358785093
Short name T1353
Test name
Test status
Simulation time 48654008514 ps
CPU time 259.24 seconds
Started Apr 28 01:01:42 PM PDT 24
Finished Apr 28 01:06:02 PM PDT 24
Peak memory 1500336 kb
Host smart-09bf4cb3-8af5-428b-860f-42bab151780b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358785093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.2358785093
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.3726274905
Short name T573
Test name
Test status
Simulation time 1189404545 ps
CPU time 19.52 seconds
Started Apr 28 01:01:33 PM PDT 24
Finished Apr 28 01:01:53 PM PDT 24
Peak memory 333256 kb
Host smart-a62a1088-d665-4592-bc98-7a786d5c62eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726274905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.3726274905
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.3819464988
Short name T197
Test name
Test status
Simulation time 94977176569 ps
CPU time 1415.39 seconds
Started Apr 28 01:01:39 PM PDT 24
Finished Apr 28 01:25:16 PM PDT 24
Peak memory 3521648 kb
Host smart-d6e6ba3f-b4fd-4f8b-b113-3eca5a338b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819464988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.3819464988
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.3417218728
Short name T93
Test name
Test status
Simulation time 483556654 ps
CPU time 9.28 seconds
Started Apr 28 01:01:42 PM PDT 24
Finished Apr 28 01:01:51 PM PDT 24
Peak memory 212316 kb
Host smart-755235fe-bdbb-46e5-97d6-ada4336d4c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417218728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.3417218728
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.2751539590
Short name T264
Test name
Test status
Simulation time 2174572533 ps
CPU time 2.66 seconds
Started Apr 28 01:01:39 PM PDT 24
Finished Apr 28 01:01:43 PM PDT 24
Peak memory 204156 kb
Host smart-65247ab4-7f53-4eb2-9d64-8c22be07891a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751539590 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.2751539590
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.859177907
Short name T520
Test name
Test status
Simulation time 10430357009 ps
CPU time 14.08 seconds
Started Apr 28 01:01:42 PM PDT 24
Finished Apr 28 01:01:56 PM PDT 24
Peak memory 285320 kb
Host smart-5c163536-c407-45b3-905c-427dfac44abe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859177907 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_acq.859177907
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2497605840
Short name T1363
Test name
Test status
Simulation time 10031203407 ps
CPU time 90.52 seconds
Started Apr 28 01:01:38 PM PDT 24
Finished Apr 28 01:03:09 PM PDT 24
Peak memory 503996 kb
Host smart-5cdb8ad9-aa43-4da1-a300-da5f1765bc3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497605840 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2497605840
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.41950906
Short name T1064
Test name
Test status
Simulation time 1582005849 ps
CPU time 2.53 seconds
Started Apr 28 01:01:40 PM PDT 24
Finished Apr 28 01:01:44 PM PDT 24
Peak memory 204200 kb
Host smart-3fb771df-e1f4-4827-9ff3-c885a7952248
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41950906 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 30.i2c_target_hrst.41950906
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.1373584280
Short name T629
Test name
Test status
Simulation time 3933067809 ps
CPU time 4.88 seconds
Started Apr 28 01:01:39 PM PDT 24
Finished Apr 28 01:01:44 PM PDT 24
Peak memory 204136 kb
Host smart-b7eedadc-4f6a-405d-bc27-eef7f42f3ee9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373584280 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.1373584280
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.3434214747
Short name T1006
Test name
Test status
Simulation time 10931218305 ps
CPU time 51.13 seconds
Started Apr 28 01:01:42 PM PDT 24
Finished Apr 28 01:02:33 PM PDT 24
Peak memory 1329632 kb
Host smart-6d011bf1-7dd0-482e-8088-e7cae8d98466
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434214747 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.3434214747
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.1980487439
Short name T910
Test name
Test status
Simulation time 1697379947 ps
CPU time 12.02 seconds
Started Apr 28 01:01:39 PM PDT 24
Finished Apr 28 01:01:52 PM PDT 24
Peak memory 204116 kb
Host smart-e4ea8161-f817-43d8-9e4d-5dccccd754ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980487439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.1980487439
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.2714353194
Short name T1050
Test name
Test status
Simulation time 2080246325 ps
CPU time 19.5 seconds
Started Apr 28 01:01:40 PM PDT 24
Finished Apr 28 01:02:00 PM PDT 24
Peak memory 217944 kb
Host smart-4280167e-7ac9-4347-b105-0b35e95c6760
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714353194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.2714353194
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.4092026685
Short name T1125
Test name
Test status
Simulation time 23525130013 ps
CPU time 11.88 seconds
Started Apr 28 01:01:38 PM PDT 24
Finished Apr 28 01:01:50 PM PDT 24
Peak memory 248328 kb
Host smart-35673bd0-8e9c-45fa-9602-738d5f376040
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092026685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.4092026685
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.304637894
Short name T946
Test name
Test status
Simulation time 2433418207 ps
CPU time 5.86 seconds
Started Apr 28 01:01:40 PM PDT 24
Finished Apr 28 01:01:47 PM PDT 24
Peak memory 212392 kb
Host smart-ede67392-ea5d-47b8-a9c7-936428fe9944
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304637894 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_timeout.304637894
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.1861267456
Short name T1229
Test name
Test status
Simulation time 35899401 ps
CPU time 0.64 seconds
Started Apr 28 01:01:52 PM PDT 24
Finished Apr 28 01:01:54 PM PDT 24
Peak memory 203732 kb
Host smart-ed44749f-065a-4d26-bdec-acaa48a5599f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861267456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.1861267456
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.2504879127
Short name T772
Test name
Test status
Simulation time 198105521 ps
CPU time 1.47 seconds
Started Apr 28 01:01:53 PM PDT 24
Finished Apr 28 01:01:55 PM PDT 24
Peak memory 220632 kb
Host smart-ea18eb31-6f9c-41b6-a84b-a30bbd84bd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504879127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.2504879127
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2359782051
Short name T187
Test name
Test status
Simulation time 691682079 ps
CPU time 7.56 seconds
Started Apr 28 01:01:46 PM PDT 24
Finished Apr 28 01:01:54 PM PDT 24
Peak memory 273968 kb
Host smart-ec1a7ff7-90f3-432e-9b20-48862ceb51e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359782051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.2359782051
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.2925821406
Short name T1000
Test name
Test status
Simulation time 2787307895 ps
CPU time 68.93 seconds
Started Apr 28 01:01:47 PM PDT 24
Finished Apr 28 01:02:56 PM PDT 24
Peak memory 465640 kb
Host smart-0af18060-5c31-4ee8-a041-f269eea73e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925821406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.2925821406
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.308273035
Short name T869
Test name
Test status
Simulation time 4254795246 ps
CPU time 151.43 seconds
Started Apr 28 01:01:44 PM PDT 24
Finished Apr 28 01:04:16 PM PDT 24
Peak memory 654008 kb
Host smart-6027918d-0271-421f-b6f9-1ffaf3762aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308273035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.308273035
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.585510705
Short name T893
Test name
Test status
Simulation time 365772791 ps
CPU time 0.81 seconds
Started Apr 28 01:01:48 PM PDT 24
Finished Apr 28 01:01:49 PM PDT 24
Peak memory 203880 kb
Host smart-a86c1de3-e21a-4191-a62c-1c1ba021bba0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585510705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fm
t.585510705
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.762965798
Short name T815
Test name
Test status
Simulation time 264143216 ps
CPU time 3.09 seconds
Started Apr 28 01:01:47 PM PDT 24
Finished Apr 28 01:01:51 PM PDT 24
Peak memory 204052 kb
Host smart-a187afc9-8c5b-41c4-8315-912a2e4a3b6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762965798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.
762965798
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3323517328
Short name T185
Test name
Test status
Simulation time 21691874824 ps
CPU time 87.15 seconds
Started Apr 28 01:01:45 PM PDT 24
Finished Apr 28 01:03:13 PM PDT 24
Peak memory 1089356 kb
Host smart-07bb267a-59ce-4948-b456-0c4d6ebae3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323517328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3323517328
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.3237459357
Short name T601
Test name
Test status
Simulation time 350987237 ps
CPU time 4.37 seconds
Started Apr 28 01:01:51 PM PDT 24
Finished Apr 28 01:01:56 PM PDT 24
Peak memory 204040 kb
Host smart-35afcfb5-238e-4daa-bd08-43af1517d757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237459357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.3237459357
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.1420546715
Short name T290
Test name
Test status
Simulation time 9749124967 ps
CPU time 56.91 seconds
Started Apr 28 01:01:52 PM PDT 24
Finished Apr 28 01:02:50 PM PDT 24
Peak memory 532288 kb
Host smart-00ac032e-163b-4aa9-b12d-25aa87759ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420546715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.1420546715
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.4145712274
Short name T34
Test name
Test status
Simulation time 48307352 ps
CPU time 0.62 seconds
Started Apr 28 01:01:44 PM PDT 24
Finished Apr 28 01:01:45 PM PDT 24
Peak memory 203864 kb
Host smart-b46b9a6a-a246-4558-adb4-cc79c8beca47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145712274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.4145712274
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.439212196
Short name T348
Test name
Test status
Simulation time 1578794461 ps
CPU time 29.97 seconds
Started Apr 28 01:01:45 PM PDT 24
Finished Apr 28 01:02:16 PM PDT 24
Peak memory 377404 kb
Host smart-5f6c4afa-30f8-47b7-9e3e-35a4450d4f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439212196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.439212196
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.3076065296
Short name T915
Test name
Test status
Simulation time 6158768488 ps
CPU time 28.24 seconds
Started Apr 28 01:01:46 PM PDT 24
Finished Apr 28 01:02:14 PM PDT 24
Peak memory 310316 kb
Host smart-6752263f-1ad0-4111-9607-c31a53709ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076065296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.3076065296
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.1048920006
Short name T1021
Test name
Test status
Simulation time 62234924298 ps
CPU time 546.44 seconds
Started Apr 28 01:01:47 PM PDT 24
Finished Apr 28 01:10:54 PM PDT 24
Peak memory 2279148 kb
Host smart-16e68cd0-a27c-43a7-8f8f-e4275f57b134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048920006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.1048920006
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.2547487934
Short name T1216
Test name
Test status
Simulation time 3170289138 ps
CPU time 13.93 seconds
Started Apr 28 01:01:48 PM PDT 24
Finished Apr 28 01:02:02 PM PDT 24
Peak memory 219892 kb
Host smart-ea1c7bb3-984f-453e-a24f-ae4031245ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547487934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.2547487934
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.4151247400
Short name T613
Test name
Test status
Simulation time 15383347589 ps
CPU time 4.85 seconds
Started Apr 28 01:01:47 PM PDT 24
Finished Apr 28 01:01:52 PM PDT 24
Peak memory 204252 kb
Host smart-2fff832c-cd25-4968-bc32-c67e79cbfb3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151247400 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.4151247400
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.1392337191
Short name T1027
Test name
Test status
Simulation time 10121597041 ps
CPU time 13.49 seconds
Started Apr 28 01:01:44 PM PDT 24
Finished Apr 28 01:01:58 PM PDT 24
Peak memory 252204 kb
Host smart-ef52d6a6-a010-4126-a5d1-f56aaf90be92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392337191 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.1392337191
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.110919484
Short name T617
Test name
Test status
Simulation time 10573712044 ps
CPU time 13.24 seconds
Started Apr 28 01:01:53 PM PDT 24
Finished Apr 28 01:02:07 PM PDT 24
Peak memory 273212 kb
Host smart-05365296-4f99-4e7b-805f-bd56c8aecfaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110919484 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_fifo_reset_tx.110919484
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.3997230632
Short name T750
Test name
Test status
Simulation time 1492509442 ps
CPU time 2.4 seconds
Started Apr 28 01:01:51 PM PDT 24
Finished Apr 28 01:01:54 PM PDT 24
Peak memory 204068 kb
Host smart-4a0ac2b2-ce8b-44c2-ae33-dc7ab23b96b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997230632 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.3997230632
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.2976047608
Short name T361
Test name
Test status
Simulation time 2047547087 ps
CPU time 2.91 seconds
Started Apr 28 01:01:45 PM PDT 24
Finished Apr 28 01:01:48 PM PDT 24
Peak memory 204176 kb
Host smart-bc13b64c-1210-4515-ad40-e3a5cc9aa966
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976047608 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.2976047608
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.1252234664
Short name T911
Test name
Test status
Simulation time 16175556061 ps
CPU time 18.47 seconds
Started Apr 28 01:01:48 PM PDT 24
Finished Apr 28 01:02:07 PM PDT 24
Peak memory 442304 kb
Host smart-28477bec-7487-451a-9367-56aa5b08ec45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252234664 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.1252234664
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.2826079073
Short name T637
Test name
Test status
Simulation time 5978488914 ps
CPU time 15.95 seconds
Started Apr 28 01:01:47 PM PDT 24
Finished Apr 28 01:02:03 PM PDT 24
Peak memory 204088 kb
Host smart-a7da6170-bc5e-475e-b47e-5cafbe9b9de6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826079073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.2826079073
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.2723647323
Short name T306
Test name
Test status
Simulation time 2330950816 ps
CPU time 5.93 seconds
Started Apr 28 01:01:52 PM PDT 24
Finished Apr 28 01:01:59 PM PDT 24
Peak memory 206180 kb
Host smart-292bf4df-3f4a-4190-93e6-591f04234406
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723647323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.2723647323
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.2725174223
Short name T334
Test name
Test status
Simulation time 59782808221 ps
CPU time 1634.66 seconds
Started Apr 28 01:01:48 PM PDT 24
Finished Apr 28 01:29:03 PM PDT 24
Peak memory 8467688 kb
Host smart-770f4cae-727d-4557-9dcb-13716cf4ee89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725174223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.2725174223
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.2376138419
Short name T1092
Test name
Test status
Simulation time 7270827186 ps
CPU time 150.11 seconds
Started Apr 28 01:01:46 PM PDT 24
Finished Apr 28 01:04:17 PM PDT 24
Peak memory 1579260 kb
Host smart-64a87f94-03c1-49db-8b83-92cac8b46e9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376138419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.2376138419
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.288089827
Short name T186
Test name
Test status
Simulation time 1152052740 ps
CPU time 6.39 seconds
Started Apr 28 01:01:44 PM PDT 24
Finished Apr 28 01:01:51 PM PDT 24
Peak memory 220376 kb
Host smart-1e4edc85-04a9-46c8-9e59-7bf7a168a4bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288089827 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_timeout.288089827
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.194974041
Short name T1005
Test name
Test status
Simulation time 15554395 ps
CPU time 0.6 seconds
Started Apr 28 01:01:53 PM PDT 24
Finished Apr 28 01:01:54 PM PDT 24
Peak memory 203804 kb
Host smart-437200cb-9bf7-498f-b742-6d3bb5a08691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194974041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.194974041
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.4181532216
Short name T1026
Test name
Test status
Simulation time 92954783 ps
CPU time 1.16 seconds
Started Apr 28 01:01:50 PM PDT 24
Finished Apr 28 01:01:52 PM PDT 24
Peak memory 212452 kb
Host smart-cdec30c3-a9fc-450e-8742-415692fd6cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181532216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.4181532216
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.878365861
Short name T928
Test name
Test status
Simulation time 1094838069 ps
CPU time 13.45 seconds
Started Apr 28 01:01:49 PM PDT 24
Finished Apr 28 01:02:03 PM PDT 24
Peak memory 258100 kb
Host smart-f7ba67cd-3f42-4e1d-8bf4-cf9e2abf6274
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878365861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empt
y.878365861
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.396413038
Short name T674
Test name
Test status
Simulation time 2190619402 ps
CPU time 63.03 seconds
Started Apr 28 01:01:50 PM PDT 24
Finished Apr 28 01:02:53 PM PDT 24
Peak memory 655032 kb
Host smart-a504bc2c-7060-4e06-81c6-79027a8ee150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396413038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.396413038
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.1948976262
Short name T382
Test name
Test status
Simulation time 2670096013 ps
CPU time 86.78 seconds
Started Apr 28 01:01:49 PM PDT 24
Finished Apr 28 01:03:16 PM PDT 24
Peak memory 467936 kb
Host smart-a43929ab-2d64-4810-b2c3-900067e439b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948976262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1948976262
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.35491564
Short name T500
Test name
Test status
Simulation time 112090036 ps
CPU time 1.03 seconds
Started Apr 28 01:01:53 PM PDT 24
Finished Apr 28 01:01:55 PM PDT 24
Peak memory 203940 kb
Host smart-e908941e-9825-432c-b158-3a67bbd28e09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35491564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fmt
.35491564
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.489191968
Short name T1083
Test name
Test status
Simulation time 135518444 ps
CPU time 3.9 seconds
Started Apr 28 01:01:50 PM PDT 24
Finished Apr 28 01:01:55 PM PDT 24
Peak memory 225516 kb
Host smart-3fef723d-3657-4dbf-aaf1-bbf800ed05b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489191968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.
489191968
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.3249305750
Short name T1205
Test name
Test status
Simulation time 4047615627 ps
CPU time 280.37 seconds
Started Apr 28 01:01:49 PM PDT 24
Finished Apr 28 01:06:30 PM PDT 24
Peak memory 1107280 kb
Host smart-599e5d40-e618-40f7-b8d6-e01245d336c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249305750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.3249305750
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.13431657
Short name T721
Test name
Test status
Simulation time 1972191454 ps
CPU time 6.31 seconds
Started Apr 28 01:01:53 PM PDT 24
Finished Apr 28 01:02:01 PM PDT 24
Peak memory 204260 kb
Host smart-c3451a0a-24c1-4c91-a3aa-371857dec125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13431657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.13431657
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.1909898201
Short name T978
Test name
Test status
Simulation time 2026150341 ps
CPU time 36.26 seconds
Started Apr 28 01:01:56 PM PDT 24
Finished Apr 28 01:02:33 PM PDT 24
Peak memory 410684 kb
Host smart-4fe621c7-0e18-4ea1-a397-2f91e02e064b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909898201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.1909898201
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.832700761
Short name T211
Test name
Test status
Simulation time 143249384 ps
CPU time 0.62 seconds
Started Apr 28 01:01:50 PM PDT 24
Finished Apr 28 01:01:51 PM PDT 24
Peak memory 203868 kb
Host smart-3686dc4c-8f53-41e6-9272-b8bff52d2a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832700761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.832700761
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.3804520980
Short name T801
Test name
Test status
Simulation time 7341601300 ps
CPU time 39.89 seconds
Started Apr 28 01:01:51 PM PDT 24
Finished Apr 28 01:02:31 PM PDT 24
Peak memory 580036 kb
Host smart-72a5d9fd-773c-46ba-a859-eac233b50a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804520980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.3804520980
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.283953526
Short name T61
Test name
Test status
Simulation time 935450300 ps
CPU time 13.87 seconds
Started Apr 28 01:01:49 PM PDT 24
Finished Apr 28 01:02:04 PM PDT 24
Peak memory 280188 kb
Host smart-fd79aa6e-3fff-474a-85d1-86cfe88b4826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283953526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.283953526
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.486958574
Short name T398
Test name
Test status
Simulation time 3714518731 ps
CPU time 15.9 seconds
Started Apr 28 01:01:50 PM PDT 24
Finished Apr 28 01:02:06 PM PDT 24
Peak memory 228668 kb
Host smart-791b14b3-3e11-4d26-894f-80c64b09d890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486958574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.486958574
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.2012556945
Short name T909
Test name
Test status
Simulation time 502078242 ps
CPU time 2.62 seconds
Started Apr 28 01:01:56 PM PDT 24
Finished Apr 28 01:01:59 PM PDT 24
Peak memory 204176 kb
Host smart-e9c9e391-9506-4554-94f7-689c4bebc30b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012556945 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.2012556945
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.1450391526
Short name T883
Test name
Test status
Simulation time 10619756148 ps
CPU time 7.61 seconds
Started Apr 28 01:01:55 PM PDT 24
Finished Apr 28 01:02:04 PM PDT 24
Peak memory 252224 kb
Host smart-9765698a-1971-405f-9e12-55cfee9e6f10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450391526 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.1450391526
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.2838996532
Short name T1098
Test name
Test status
Simulation time 10065419579 ps
CPU time 72.4 seconds
Started Apr 28 01:01:56 PM PDT 24
Finished Apr 28 01:03:09 PM PDT 24
Peak memory 535360 kb
Host smart-2abd5975-e00d-4627-aac8-42d889fd25fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838996532 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.2838996532
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.105152949
Short name T1265
Test name
Test status
Simulation time 1156333956 ps
CPU time 2.21 seconds
Started Apr 28 01:01:54 PM PDT 24
Finished Apr 28 01:01:57 PM PDT 24
Peak memory 204084 kb
Host smart-46e1d2b8-2562-4e46-9f3e-6906ecef0fc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105152949 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.i2c_target_hrst.105152949
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.139644346
Short name T948
Test name
Test status
Simulation time 5296503002 ps
CPU time 4.79 seconds
Started Apr 28 01:01:49 PM PDT 24
Finished Apr 28 01:01:54 PM PDT 24
Peak memory 207448 kb
Host smart-a1afa11b-c271-4aff-8842-d635811590db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139644346 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_intr_smoke.139644346
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.2263682501
Short name T292
Test name
Test status
Simulation time 4757025164 ps
CPU time 8.91 seconds
Started Apr 28 01:01:53 PM PDT 24
Finished Apr 28 01:02:03 PM PDT 24
Peak memory 204200 kb
Host smart-66722968-3bfc-4e50-99f4-2a376cef1d83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263682501 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.2263682501
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.538137638
Short name T491
Test name
Test status
Simulation time 5866648198 ps
CPU time 53.58 seconds
Started Apr 28 01:01:50 PM PDT 24
Finished Apr 28 01:02:44 PM PDT 24
Peak memory 204268 kb
Host smart-bf06c748-19c5-4b3b-a20f-5cf2984b31e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538137638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_tar
get_smoke.538137638
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.788027439
Short name T376
Test name
Test status
Simulation time 22587726917 ps
CPU time 50.06 seconds
Started Apr 28 01:01:53 PM PDT 24
Finished Apr 28 01:02:44 PM PDT 24
Peak memory 208560 kb
Host smart-906c1ec2-1f7d-458c-a652-480400e1637e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788027439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c
_target_stress_rd.788027439
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.1733688076
Short name T995
Test name
Test status
Simulation time 26165308312 ps
CPU time 76.9 seconds
Started Apr 28 01:01:50 PM PDT 24
Finished Apr 28 01:03:08 PM PDT 24
Peak memory 1194244 kb
Host smart-2989c9d5-bc43-4961-9441-eaedf0d1ddcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733688076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.1733688076
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.3039441740
Short name T1270
Test name
Test status
Simulation time 23575366862 ps
CPU time 366.18 seconds
Started Apr 28 01:01:51 PM PDT 24
Finished Apr 28 01:07:58 PM PDT 24
Peak memory 1229280 kb
Host smart-dd1fdb0a-3531-484d-9159-05ea129761d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039441740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.3039441740
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.4098896066
Short name T864
Test name
Test status
Simulation time 10476141056 ps
CPU time 6.52 seconds
Started Apr 28 01:01:53 PM PDT 24
Finished Apr 28 01:02:01 PM PDT 24
Peak memory 212484 kb
Host smart-a5674494-f253-42b2-85e4-50297a2fbc02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098896066 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.4098896066
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.3004620075
Short name T788
Test name
Test status
Simulation time 37684252 ps
CPU time 0.62 seconds
Started Apr 28 01:02:06 PM PDT 24
Finished Apr 28 01:02:08 PM PDT 24
Peak memory 203784 kb
Host smart-3fb45a51-63b2-4117-9890-9c8993b321ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004620075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.3004620075
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.3354178560
Short name T441
Test name
Test status
Simulation time 1591635423 ps
CPU time 1.56 seconds
Started Apr 28 01:01:59 PM PDT 24
Finished Apr 28 01:02:02 PM PDT 24
Peak memory 212380 kb
Host smart-99dbddec-0ca7-4b95-a5e0-573fcdc7cd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354178560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.3354178560
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.1851562350
Short name T582
Test name
Test status
Simulation time 3676565462 ps
CPU time 5.9 seconds
Started Apr 28 01:01:55 PM PDT 24
Finished Apr 28 01:02:01 PM PDT 24
Peak memory 258436 kb
Host smart-772358dc-3d77-4ede-b513-1dd6ed8a7646
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851562350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.1851562350
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.3765021147
Short name T1326
Test name
Test status
Simulation time 3796276988 ps
CPU time 139.14 seconds
Started Apr 28 01:02:03 PM PDT 24
Finished Apr 28 01:04:22 PM PDT 24
Peak memory 665704 kb
Host smart-6b8b75f5-0f5f-41f1-a4ab-86634d505757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765021147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.3765021147
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2601882112
Short name T917
Test name
Test status
Simulation time 2102957190 ps
CPU time 135.15 seconds
Started Apr 28 01:01:59 PM PDT 24
Finished Apr 28 01:04:15 PM PDT 24
Peak memory 632060 kb
Host smart-569692af-35ad-4831-be55-cfffc49d6115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601882112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2601882112
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.547556548
Short name T673
Test name
Test status
Simulation time 116679801 ps
CPU time 0.99 seconds
Started Apr 28 01:01:59 PM PDT 24
Finished Apr 28 01:02:01 PM PDT 24
Peak memory 203968 kb
Host smart-d07f060b-3550-4cc6-b42e-be143b1d2dc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547556548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fm
t.547556548
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.3146850586
Short name T88
Test name
Test status
Simulation time 363127853 ps
CPU time 4.47 seconds
Started Apr 28 01:01:58 PM PDT 24
Finished Apr 28 01:02:03 PM PDT 24
Peak memory 236972 kb
Host smart-cbc65964-f231-47e1-ad4c-87f788eb89ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146850586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.3146850586
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.1406627271
Short name T1165
Test name
Test status
Simulation time 1204809432 ps
CPU time 5.07 seconds
Started Apr 28 01:02:04 PM PDT 24
Finished Apr 28 01:02:09 PM PDT 24
Peak memory 204200 kb
Host smart-82f722eb-3997-4495-99af-28a9de1b78ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406627271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.1406627271
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1755636828
Short name T1220
Test name
Test status
Simulation time 6593847050 ps
CPU time 80.56 seconds
Started Apr 28 01:02:04 PM PDT 24
Finished Apr 28 01:03:25 PM PDT 24
Peak memory 400404 kb
Host smart-bd0f1471-eb9c-4ed5-a2d7-976844ff2362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755636828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1755636828
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.1061220568
Short name T940
Test name
Test status
Simulation time 32362552 ps
CPU time 0.66 seconds
Started Apr 28 01:01:57 PM PDT 24
Finished Apr 28 01:01:58 PM PDT 24
Peak memory 203808 kb
Host smart-d6c7b550-ced9-4f09-9c69-703af18cb0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061220568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.1061220568
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.1666908686
Short name T60
Test name
Test status
Simulation time 1454656916 ps
CPU time 59.72 seconds
Started Apr 28 01:02:01 PM PDT 24
Finished Apr 28 01:03:02 PM PDT 24
Peak memory 220356 kb
Host smart-10d09b8f-4735-4090-b2da-74e703251f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666908686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.1666908686
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.3407724089
Short name T274
Test name
Test status
Simulation time 10635026825 ps
CPU time 33.85 seconds
Started Apr 28 01:01:59 PM PDT 24
Finished Apr 28 01:02:34 PM PDT 24
Peak memory 317360 kb
Host smart-58a335b6-7f5a-46ab-9949-e449c1d9fc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407724089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.3407724089
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.20526840
Short name T247
Test name
Test status
Simulation time 6866820375 ps
CPU time 346.24 seconds
Started Apr 28 01:02:01 PM PDT 24
Finished Apr 28 01:07:48 PM PDT 24
Peak memory 1651700 kb
Host smart-520bbf18-82cd-445b-9e7c-64af427398fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20526840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.20526840
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.1012403109
Short name T1023
Test name
Test status
Simulation time 469036213 ps
CPU time 10.36 seconds
Started Apr 28 01:02:00 PM PDT 24
Finished Apr 28 01:02:12 PM PDT 24
Peak memory 212276 kb
Host smart-dfdc2c46-01cf-4df4-82b9-eb8f02b8d27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012403109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.1012403109
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3813163603
Short name T7
Test name
Test status
Simulation time 677291856 ps
CPU time 3.29 seconds
Started Apr 28 01:02:02 PM PDT 24
Finished Apr 28 01:02:06 PM PDT 24
Peak memory 204092 kb
Host smart-d68ed7b4-386c-4796-b760-416e4d4be511
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813163603 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3813163603
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.215963780
Short name T386
Test name
Test status
Simulation time 10192237382 ps
CPU time 15.59 seconds
Started Apr 28 01:02:00 PM PDT 24
Finished Apr 28 01:02:17 PM PDT 24
Peak memory 261788 kb
Host smart-a00d82c1-5e23-483e-8770-842268179a2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215963780 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_acq.215963780
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.419086644
Short name T974
Test name
Test status
Simulation time 10474090375 ps
CPU time 9 seconds
Started Apr 28 01:02:00 PM PDT 24
Finished Apr 28 01:02:11 PM PDT 24
Peak memory 257704 kb
Host smart-8c9bb595-360c-47a3-a9f5-111e6f6503b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419086644 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.i2c_target_fifo_reset_tx.419086644
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.2505810294
Short name T790
Test name
Test status
Simulation time 713212987 ps
CPU time 2.26 seconds
Started Apr 28 01:02:01 PM PDT 24
Finished Apr 28 01:02:04 PM PDT 24
Peak memory 204152 kb
Host smart-645290db-41cf-44cf-838d-20e42c4db279
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505810294 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.2505810294
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.2715782753
Short name T1243
Test name
Test status
Simulation time 1427628425 ps
CPU time 3.83 seconds
Started Apr 28 01:02:01 PM PDT 24
Finished Apr 28 01:02:06 PM PDT 24
Peak memory 207420 kb
Host smart-85c8f5e2-cb64-4c3b-8348-68229c9af1c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715782753 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.2715782753
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.1673032876
Short name T1252
Test name
Test status
Simulation time 10930034519 ps
CPU time 9.49 seconds
Started Apr 28 01:02:03 PM PDT 24
Finished Apr 28 01:02:13 PM PDT 24
Peak memory 302632 kb
Host smart-5028e917-c51b-4de6-9df8-37b8a4e90b07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673032876 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.1673032876
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.1020987884
Short name T418
Test name
Test status
Simulation time 904788569 ps
CPU time 7.3 seconds
Started Apr 28 01:01:59 PM PDT 24
Finished Apr 28 01:02:06 PM PDT 24
Peak memory 203980 kb
Host smart-b2bf6154-d4fa-4a64-a2e3-0e662bad980f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020987884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.1020987884
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.3269644686
Short name T303
Test name
Test status
Simulation time 1825386419 ps
CPU time 37.11 seconds
Started Apr 28 01:02:00 PM PDT 24
Finished Apr 28 01:02:38 PM PDT 24
Peak memory 204164 kb
Host smart-6b42132b-1f96-49a1-aa02-230deaf059bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269644686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.3269644686
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.3135253243
Short name T22
Test name
Test status
Simulation time 26478310089 ps
CPU time 47.67 seconds
Started Apr 28 01:02:00 PM PDT 24
Finished Apr 28 01:02:49 PM PDT 24
Peak memory 869568 kb
Host smart-6aa5be15-7cae-4f0a-bc1b-96b78267c886
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135253243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.3135253243
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.3528677634
Short name T763
Test name
Test status
Simulation time 31253664360 ps
CPU time 235.6 seconds
Started Apr 28 01:02:05 PM PDT 24
Finished Apr 28 01:06:01 PM PDT 24
Peak memory 1731284 kb
Host smart-822536b2-612b-4fd7-96b8-b559dacfba61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528677634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.3528677634
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.764329242
Short name T273
Test name
Test status
Simulation time 1869372780 ps
CPU time 7.56 seconds
Started Apr 28 01:02:00 PM PDT 24
Finished Apr 28 01:02:09 PM PDT 24
Peak memory 220496 kb
Host smart-b33013a6-e1bb-466f-b31a-86cec51c1e31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764329242 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_timeout.764329242
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_unexp_stop.3844946840
Short name T996
Test name
Test status
Simulation time 1029598058 ps
CPU time 5.48 seconds
Started Apr 28 01:02:03 PM PDT 24
Finished Apr 28 01:02:09 PM PDT 24
Peak memory 217660 kb
Host smart-d2483223-6877-420a-8c21-220f759fee8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844946840 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.i2c_target_unexp_stop.3844946840
Directory /workspace/33.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/34.i2c_alert_test.437769008
Short name T1007
Test name
Test status
Simulation time 36259019 ps
CPU time 0.61 seconds
Started Apr 28 01:02:12 PM PDT 24
Finished Apr 28 01:02:13 PM PDT 24
Peak memory 203888 kb
Host smart-c1f52891-c66b-4185-8205-02826b504c6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437769008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.437769008
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.4049049124
Short name T283
Test name
Test status
Simulation time 155508297 ps
CPU time 1.42 seconds
Started Apr 28 01:02:04 PM PDT 24
Finished Apr 28 01:02:06 PM PDT 24
Peak memory 212484 kb
Host smart-9302a10d-db27-43c4-b27f-e6f9c44f6605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049049124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.4049049124
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.3578568069
Short name T842
Test name
Test status
Simulation time 233841776 ps
CPU time 12.86 seconds
Started Apr 28 01:02:08 PM PDT 24
Finished Apr 28 01:02:21 PM PDT 24
Peak memory 252176 kb
Host smart-2978159e-c60f-4ec0-8033-a35f595f0b90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578568069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.3578568069
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.1024691386
Short name T46
Test name
Test status
Simulation time 15341840438 ps
CPU time 134.63 seconds
Started Apr 28 01:02:10 PM PDT 24
Finished Apr 28 01:04:25 PM PDT 24
Peak memory 663752 kb
Host smart-952dcc57-1628-4b35-b785-84b86739b5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024691386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.1024691386
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.3809544526
Short name T670
Test name
Test status
Simulation time 4349970207 ps
CPU time 41.84 seconds
Started Apr 28 01:02:06 PM PDT 24
Finished Apr 28 01:02:49 PM PDT 24
Peak memory 531004 kb
Host smart-06800c03-a1c2-4c37-acd5-ae7745703941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809544526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3809544526
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3032791505
Short name T228
Test name
Test status
Simulation time 730961797 ps
CPU time 1.17 seconds
Started Apr 28 01:02:11 PM PDT 24
Finished Apr 28 01:02:13 PM PDT 24
Peak memory 204176 kb
Host smart-005ea8ea-a072-487d-835a-f0c68a044ea9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032791505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3032791505
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.3715411933
Short name T584
Test name
Test status
Simulation time 361262684 ps
CPU time 9.13 seconds
Started Apr 28 01:02:06 PM PDT 24
Finished Apr 28 01:02:16 PM PDT 24
Peak memory 203984 kb
Host smart-253f1d09-ff73-444f-86c1-a54fa693434d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715411933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.3715411933
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2826999990
Short name T255
Test name
Test status
Simulation time 3847711765 ps
CPU time 278.93 seconds
Started Apr 28 01:02:07 PM PDT 24
Finished Apr 28 01:06:46 PM PDT 24
Peak memory 1110968 kb
Host smart-4e997c71-89bd-46a8-861a-80e9396f3779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826999990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2826999990
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.472930640
Short name T462
Test name
Test status
Simulation time 629625019 ps
CPU time 26.63 seconds
Started Apr 28 01:02:12 PM PDT 24
Finished Apr 28 01:02:40 PM PDT 24
Peak memory 204148 kb
Host smart-6afc7ea6-3cb8-4dee-98f2-18801bb1df32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472930640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.472930640
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.718208652
Short name T1190
Test name
Test status
Simulation time 1629849314 ps
CPU time 72.33 seconds
Started Apr 28 01:02:10 PM PDT 24
Finished Apr 28 01:03:23 PM PDT 24
Peak memory 308492 kb
Host smart-bcc9179d-a933-4bf4-a048-7b6bf58efc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718208652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.718208652
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.709963538
Short name T1318
Test name
Test status
Simulation time 50951285 ps
CPU time 0.71 seconds
Started Apr 28 01:02:06 PM PDT 24
Finished Apr 28 01:02:07 PM PDT 24
Peak memory 203808 kb
Host smart-021ef650-3316-4b6f-ae8a-d330315d3db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709963538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.709963538
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.760967071
Short name T767
Test name
Test status
Simulation time 7051005076 ps
CPU time 436.69 seconds
Started Apr 28 01:02:05 PM PDT 24
Finished Apr 28 01:09:23 PM PDT 24
Peak memory 909700 kb
Host smart-aa396016-798f-44fe-936f-c6ca4cd3baad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760967071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.760967071
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.2529788735
Short name T705
Test name
Test status
Simulation time 2109110365 ps
CPU time 14.23 seconds
Started Apr 28 01:02:06 PM PDT 24
Finished Apr 28 01:02:21 PM PDT 24
Peak memory 298056 kb
Host smart-8503444e-60a2-4e3d-b10f-e3e22c547f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529788735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.2529788735
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.1637049186
Short name T755
Test name
Test status
Simulation time 7970458091 ps
CPU time 867.7 seconds
Started Apr 28 01:02:06 PM PDT 24
Finished Apr 28 01:16:35 PM PDT 24
Peak memory 1451760 kb
Host smart-705011a8-756b-4014-a233-96839c6fd824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637049186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.1637049186
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.4126099922
Short name T1147
Test name
Test status
Simulation time 334058694 ps
CPU time 5.32 seconds
Started Apr 28 01:02:11 PM PDT 24
Finished Apr 28 01:02:17 PM PDT 24
Peak memory 212372 kb
Host smart-e6e9fccf-1c4c-459a-b3c1-98d1133d963d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126099922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.4126099922
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.2661666546
Short name T634
Test name
Test status
Simulation time 882059377 ps
CPU time 4.07 seconds
Started Apr 28 01:02:11 PM PDT 24
Finished Apr 28 01:02:16 PM PDT 24
Peak memory 204172 kb
Host smart-d2ae9fc2-06ee-48ac-a034-b558eb86143b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661666546 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.2661666546
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.4173240818
Short name T54
Test name
Test status
Simulation time 10041914134 ps
CPU time 70.82 seconds
Started Apr 28 01:02:23 PM PDT 24
Finished Apr 28 01:03:34 PM PDT 24
Peak memory 519256 kb
Host smart-17a02f26-bb69-4484-b0fe-9bbda59e8ba1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173240818 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.4173240818
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.1639085765
Short name T53
Test name
Test status
Simulation time 11186059700 ps
CPU time 7.67 seconds
Started Apr 28 01:02:11 PM PDT 24
Finished Apr 28 01:02:19 PM PDT 24
Peak memory 246896 kb
Host smart-2a4f20f9-2dd3-4b20-949f-6e1e7d0dfb5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639085765 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.1639085765
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.3454458372
Short name T435
Test name
Test status
Simulation time 1354827475 ps
CPU time 2.26 seconds
Started Apr 28 01:02:11 PM PDT 24
Finished Apr 28 01:02:14 PM PDT 24
Peak memory 204024 kb
Host smart-b394c469-0e25-4d25-8087-830dcf3dc556
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454458372 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.3454458372
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.2849485584
Short name T1323
Test name
Test status
Simulation time 1705828401 ps
CPU time 4.54 seconds
Started Apr 28 01:02:04 PM PDT 24
Finished Apr 28 01:02:09 PM PDT 24
Peak memory 206404 kb
Host smart-64034b39-2981-4782-8071-db11c00cd44a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849485584 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.2849485584
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.2818149596
Short name T450
Test name
Test status
Simulation time 8406885372 ps
CPU time 11.85 seconds
Started Apr 28 01:02:05 PM PDT 24
Finished Apr 28 01:02:18 PM PDT 24
Peak memory 291708 kb
Host smart-7a838978-72f9-4e0f-96e9-6578b95f5c8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818149596 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.2818149596
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.2947664215
Short name T343
Test name
Test status
Simulation time 2477377323 ps
CPU time 6.95 seconds
Started Apr 28 01:02:07 PM PDT 24
Finished Apr 28 01:02:14 PM PDT 24
Peak memory 204064 kb
Host smart-7f26a49f-5c82-4eb1-9229-029ec656b179
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947664215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.2947664215
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.4138190919
Short name T698
Test name
Test status
Simulation time 6970285066 ps
CPU time 76.68 seconds
Started Apr 28 01:02:06 PM PDT 24
Finished Apr 28 01:03:24 PM PDT 24
Peak memory 207192 kb
Host smart-0c951e4d-bf0a-4e8b-8e2a-0e654d42e4cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138190919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.4138190919
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.4174397281
Short name T1288
Test name
Test status
Simulation time 25898213327 ps
CPU time 114.42 seconds
Started Apr 28 01:02:04 PM PDT 24
Finished Apr 28 01:03:59 PM PDT 24
Peak memory 1618480 kb
Host smart-840ecf3d-fdd7-4797-9d78-1ee25e57b064
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174397281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.4174397281
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.3468772607
Short name T778
Test name
Test status
Simulation time 20792343196 ps
CPU time 353.06 seconds
Started Apr 28 01:02:10 PM PDT 24
Finished Apr 28 01:08:04 PM PDT 24
Peak memory 2461944 kb
Host smart-294dde64-5022-45de-b7a1-617d6ea42d6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468772607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.3468772607
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.3115645812
Short name T97
Test name
Test status
Simulation time 10258666747 ps
CPU time 6.77 seconds
Started Apr 28 01:02:11 PM PDT 24
Finished Apr 28 01:02:19 PM PDT 24
Peak memory 215100 kb
Host smart-8504195e-b99e-414b-9d97-fb51eeea1b77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115645812 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.3115645812
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_unexp_stop.3954994032
Short name T943
Test name
Test status
Simulation time 2118070393 ps
CPU time 5.9 seconds
Started Apr 28 01:02:11 PM PDT 24
Finished Apr 28 01:02:18 PM PDT 24
Peak memory 204164 kb
Host smart-d3b38a71-da1a-4faa-9de9-9d30526f886a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954994032 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.i2c_target_unexp_stop.3954994032
Directory /workspace/34.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/35.i2c_alert_test.1303762411
Short name T1331
Test name
Test status
Simulation time 17699943 ps
CPU time 0.62 seconds
Started Apr 28 01:02:17 PM PDT 24
Finished Apr 28 01:02:18 PM PDT 24
Peak memory 203856 kb
Host smart-8b174760-6a18-400e-9ea9-a13fe83f2d9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303762411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.1303762411
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.3704242245
Short name T412
Test name
Test status
Simulation time 362330235 ps
CPU time 1.33 seconds
Started Apr 28 01:02:12 PM PDT 24
Finished Apr 28 01:02:14 PM PDT 24
Peak memory 212320 kb
Host smart-3285b21a-50dd-4054-a050-f735b62154b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704242245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.3704242245
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.2743278735
Short name T527
Test name
Test status
Simulation time 358073327 ps
CPU time 6.97 seconds
Started Apr 28 01:02:12 PM PDT 24
Finished Apr 28 01:02:20 PM PDT 24
Peak memory 276792 kb
Host smart-139bceca-a141-47f7-ad96-fcea936e9764
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743278735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.2743278735
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.3525872038
Short name T1144
Test name
Test status
Simulation time 2261847905 ps
CPU time 150.84 seconds
Started Apr 28 01:02:10 PM PDT 24
Finished Apr 28 01:04:42 PM PDT 24
Peak memory 693004 kb
Host smart-5a3b94f2-cd7b-4b84-9b5d-da7d4e50d54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525872038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.3525872038
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.377129219
Short name T364
Test name
Test status
Simulation time 1904742769 ps
CPU time 135.93 seconds
Started Apr 28 01:02:10 PM PDT 24
Finished Apr 28 01:04:27 PM PDT 24
Peak memory 655904 kb
Host smart-3e479ed2-ce4d-4f00-8e47-65669688cd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377129219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.377129219
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.558271261
Short name T794
Test name
Test status
Simulation time 692124392 ps
CPU time 1.11 seconds
Started Apr 28 01:02:10 PM PDT 24
Finished Apr 28 01:02:12 PM PDT 24
Peak memory 204024 kb
Host smart-cb7b409b-4abb-418b-986d-6d51dd5aaaa5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558271261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fm
t.558271261
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.2129866993
Short name T731
Test name
Test status
Simulation time 1116111533 ps
CPU time 3.6 seconds
Started Apr 28 01:02:11 PM PDT 24
Finished Apr 28 01:02:15 PM PDT 24
Peak memory 204164 kb
Host smart-cf98225c-f588-42f7-ba2f-9aa022902503
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129866993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.2129866993
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.2595868683
Short name T1088
Test name
Test status
Simulation time 13702439805 ps
CPU time 259.48 seconds
Started Apr 28 01:02:12 PM PDT 24
Finished Apr 28 01:06:32 PM PDT 24
Peak memory 1055556 kb
Host smart-15e26d5f-eb21-4646-a738-3290b91851fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595868683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.2595868683
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.122826524
Short name T1022
Test name
Test status
Simulation time 3237444924 ps
CPU time 32.94 seconds
Started Apr 28 01:02:19 PM PDT 24
Finished Apr 28 01:02:52 PM PDT 24
Peak memory 204064 kb
Host smart-8fee0c7d-b781-4824-8653-f729afd86400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122826524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.122826524
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.3862065241
Short name T339
Test name
Test status
Simulation time 2466440392 ps
CPU time 58.71 seconds
Started Apr 28 01:02:21 PM PDT 24
Finished Apr 28 01:03:20 PM PDT 24
Peak memory 297968 kb
Host smart-98a40608-2252-4007-8bb7-ade3ee530901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862065241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.3862065241
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.2759502864
Short name T206
Test name
Test status
Simulation time 34402618 ps
CPU time 0.66 seconds
Started Apr 28 01:02:34 PM PDT 24
Finished Apr 28 01:02:35 PM PDT 24
Peak memory 203732 kb
Host smart-2effbb00-fb99-4308-8a1b-c10d25ad96b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759502864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2759502864
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.3679745750
Short name T287
Test name
Test status
Simulation time 6320456469 ps
CPU time 240.89 seconds
Started Apr 28 01:02:11 PM PDT 24
Finished Apr 28 01:06:13 PM PDT 24
Peak memory 1386092 kb
Host smart-0c7ec284-a046-4ad3-b21a-1d3e7ff1edf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679745750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.3679745750
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.3661435692
Short name T595
Test name
Test status
Simulation time 3814378032 ps
CPU time 16.31 seconds
Started Apr 28 01:02:09 PM PDT 24
Finished Apr 28 01:02:26 PM PDT 24
Peak memory 296684 kb
Host smart-a7ae6720-e7c8-4fee-a72d-1a563a516a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661435692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.3661435692
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.3612942347
Short name T510
Test name
Test status
Simulation time 1389668005 ps
CPU time 6.51 seconds
Started Apr 28 01:02:12 PM PDT 24
Finished Apr 28 01:02:19 PM PDT 24
Peak memory 212336 kb
Host smart-e8fb60d4-1bd9-49da-8870-cbd0d7cad655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612942347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.3612942347
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.1182157207
Short name T459
Test name
Test status
Simulation time 6361890529 ps
CPU time 6.06 seconds
Started Apr 28 01:02:16 PM PDT 24
Finished Apr 28 01:02:22 PM PDT 24
Peak memory 212524 kb
Host smart-f2005356-0969-4aac-9e78-04c4d5f1c06b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182157207 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.1182157207
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.1722111187
Short name T962
Test name
Test status
Simulation time 10121160631 ps
CPU time 15.73 seconds
Started Apr 28 01:02:16 PM PDT 24
Finished Apr 28 01:02:32 PM PDT 24
Peak memory 278664 kb
Host smart-5ffb922e-6388-4d74-bdd3-08e4a1bb3185
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722111187 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.1722111187
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.4271508942
Short name T1066
Test name
Test status
Simulation time 10083691029 ps
CPU time 81.18 seconds
Started Apr 28 01:02:16 PM PDT 24
Finished Apr 28 01:03:38 PM PDT 24
Peak memory 478096 kb
Host smart-f35be080-6231-4c71-b682-e4e50000b8b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271508942 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.4271508942
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.391127258
Short name T1298
Test name
Test status
Simulation time 1847003985 ps
CPU time 2.58 seconds
Started Apr 28 01:02:14 PM PDT 24
Finished Apr 28 01:02:17 PM PDT 24
Peak memory 204064 kb
Host smart-0cc6e97f-7a2f-4538-a91a-fb7c6334acd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391127258 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.i2c_target_hrst.391127258
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.574625179
Short name T1150
Test name
Test status
Simulation time 1348955806 ps
CPU time 3.58 seconds
Started Apr 28 01:02:16 PM PDT 24
Finished Apr 28 01:02:20 PM PDT 24
Peak memory 204172 kb
Host smart-8a95185f-f2b9-4a57-8968-814e59f28ae0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574625179 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_intr_smoke.574625179
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.433981282
Short name T416
Test name
Test status
Simulation time 23967862794 ps
CPU time 19.59 seconds
Started Apr 28 01:02:17 PM PDT 24
Finished Apr 28 01:02:37 PM PDT 24
Peak memory 430512 kb
Host smart-8f755f88-99a7-49f4-99c9-bab984ac3755
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433981282 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.433981282
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.3582273661
Short name T507
Test name
Test status
Simulation time 844333740 ps
CPU time 33.53 seconds
Started Apr 28 01:02:09 PM PDT 24
Finished Apr 28 01:02:44 PM PDT 24
Peak memory 204108 kb
Host smart-5775f03d-1d23-4c4c-a176-8313f9e83069
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582273661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.3582273661
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.3981218112
Short name T241
Test name
Test status
Simulation time 6118617652 ps
CPU time 64.26 seconds
Started Apr 28 01:02:12 PM PDT 24
Finished Apr 28 01:03:17 PM PDT 24
Peak memory 208284 kb
Host smart-f02bffac-925d-4c8c-8aa4-0a4403052af3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981218112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.3981218112
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.2268322119
Short name T852
Test name
Test status
Simulation time 21394029457 ps
CPU time 14.17 seconds
Started Apr 28 01:02:10 PM PDT 24
Finished Apr 28 01:02:25 PM PDT 24
Peak memory 204208 kb
Host smart-09eacfd4-9e16-4747-8f11-c41cb710aead
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268322119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.2268322119
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.1073860054
Short name T240
Test name
Test status
Simulation time 33513557383 ps
CPU time 2981.7 seconds
Started Apr 28 01:02:09 PM PDT 24
Finished Apr 28 01:51:51 PM PDT 24
Peak memory 7905180 kb
Host smart-b593293a-f20b-482c-b4f1-43f4574ac2c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073860054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.1073860054
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.3463882460
Short name T612
Test name
Test status
Simulation time 1326775475 ps
CPU time 6.89 seconds
Started Apr 28 01:02:19 PM PDT 24
Finished Apr 28 01:02:26 PM PDT 24
Peak memory 218280 kb
Host smart-d8e6879f-07c8-4658-a8e6-4eac389a8140
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463882460 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.3463882460
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_unexp_stop.1322199770
Short name T1325
Test name
Test status
Simulation time 6916206365 ps
CPU time 4.74 seconds
Started Apr 28 01:02:16 PM PDT 24
Finished Apr 28 01:02:21 PM PDT 24
Peak memory 208712 kb
Host smart-db19a79e-f68b-4007-a4fe-f68065df4ce9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322199770 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.i2c_target_unexp_stop.1322199770
Directory /workspace/35.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/36.i2c_alert_test.366575710
Short name T832
Test name
Test status
Simulation time 16776872 ps
CPU time 0.61 seconds
Started Apr 28 01:02:26 PM PDT 24
Finished Apr 28 01:02:27 PM PDT 24
Peak memory 203920 kb
Host smart-b6875860-4062-4de5-a96a-fcbf66567eb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366575710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.366575710
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.680665144
Short name T1300
Test name
Test status
Simulation time 76334885 ps
CPU time 1.25 seconds
Started Apr 28 01:02:21 PM PDT 24
Finished Apr 28 01:02:22 PM PDT 24
Peak memory 212360 kb
Host smart-dbd5f331-c49f-4b25-9f0f-935a267f204a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680665144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.680665144
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.1685099433
Short name T1312
Test name
Test status
Simulation time 258008690 ps
CPU time 12.13 seconds
Started Apr 28 01:02:17 PM PDT 24
Finished Apr 28 01:02:30 PM PDT 24
Peak memory 242444 kb
Host smart-54443054-913a-480a-a429-2fe95877bc08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685099433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.1685099433
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2755264375
Short name T486
Test name
Test status
Simulation time 7566458641 ps
CPU time 132.98 seconds
Started Apr 28 01:02:21 PM PDT 24
Finished Apr 28 01:04:34 PM PDT 24
Peak memory 676864 kb
Host smart-4879d9ad-15ab-4c60-a863-05818b208e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755264375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2755264375
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.769348983
Short name T1071
Test name
Test status
Simulation time 9988208059 ps
CPU time 92.45 seconds
Started Apr 28 01:02:18 PM PDT 24
Finished Apr 28 01:03:51 PM PDT 24
Peak memory 800752 kb
Host smart-d7bbe72f-59f9-4232-818d-153b665ab4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769348983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.769348983
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3543305819
Short name T1042
Test name
Test status
Simulation time 117410647 ps
CPU time 0.89 seconds
Started Apr 28 01:02:16 PM PDT 24
Finished Apr 28 01:02:18 PM PDT 24
Peak memory 203948 kb
Host smart-0940c2e6-e2c1-4525-8b2c-bc974edb3b9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543305819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3543305819
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.4047232325
Short name T902
Test name
Test status
Simulation time 136211127 ps
CPU time 6.6 seconds
Started Apr 28 01:02:17 PM PDT 24
Finished Apr 28 01:02:24 PM PDT 24
Peak memory 204176 kb
Host smart-1d8d86ca-7231-487a-8899-5bc61a255c80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047232325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.4047232325
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.107769943
Short name T1129
Test name
Test status
Simulation time 5562298108 ps
CPU time 183.41 seconds
Started Apr 28 01:02:17 PM PDT 24
Finished Apr 28 01:05:21 PM PDT 24
Peak memory 869052 kb
Host smart-fc6c9e29-d7cd-4123-b1da-b3d1032f7350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107769943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.107769943
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.2224123494
Short name T717
Test name
Test status
Simulation time 5664508762 ps
CPU time 8.33 seconds
Started Apr 28 01:02:27 PM PDT 24
Finished Apr 28 01:02:36 PM PDT 24
Peak memory 204232 kb
Host smart-9ff260d2-cda4-4680-9045-3d7088a74eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224123494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.2224123494
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.822685668
Short name T481
Test name
Test status
Simulation time 14988899653 ps
CPU time 52.68 seconds
Started Apr 28 01:02:21 PM PDT 24
Finished Apr 28 01:03:14 PM PDT 24
Peak memory 325232 kb
Host smart-5b7fd995-74e5-44ca-a0c2-a83fe701ae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822685668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.822685668
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.1736698838
Short name T572
Test name
Test status
Simulation time 47130151 ps
CPU time 0.65 seconds
Started Apr 28 01:02:22 PM PDT 24
Finished Apr 28 01:02:23 PM PDT 24
Peak memory 203840 kb
Host smart-ada49081-bdcb-4ff7-909d-ce783dd5e199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736698838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.1736698838
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.721829664
Short name T1080
Test name
Test status
Simulation time 28475663312 ps
CPU time 157.5 seconds
Started Apr 28 01:02:22 PM PDT 24
Finished Apr 28 01:05:00 PM PDT 24
Peak memory 756792 kb
Host smart-09810c81-ef96-47a3-99f2-e5ee5b95672a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721829664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.721829664
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.27216881
Short name T356
Test name
Test status
Simulation time 1266456737 ps
CPU time 19.05 seconds
Started Apr 28 01:02:16 PM PDT 24
Finished Apr 28 01:02:36 PM PDT 24
Peak memory 327540 kb
Host smart-0e5c5290-2cf1-4d00-a095-cf85811d30bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27216881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.27216881
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.907017624
Short name T866
Test name
Test status
Simulation time 59267933180 ps
CPU time 162.72 seconds
Started Apr 28 01:02:23 PM PDT 24
Finished Apr 28 01:05:06 PM PDT 24
Peak memory 1060316 kb
Host smart-9f5419bc-5e86-4b0e-ad56-78d7c61490d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907017624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.907017624
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.3015561451
Short name T816
Test name
Test status
Simulation time 469354679 ps
CPU time 7.6 seconds
Started Apr 28 01:02:22 PM PDT 24
Finished Apr 28 01:02:31 PM PDT 24
Peak memory 220508 kb
Host smart-343d9df9-65c0-40b6-8e5f-4c0bcc5fa3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015561451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.3015561451
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.381908744
Short name T892
Test name
Test status
Simulation time 3750416244 ps
CPU time 4.57 seconds
Started Apr 28 01:02:22 PM PDT 24
Finished Apr 28 01:02:27 PM PDT 24
Peak memory 212440 kb
Host smart-740aa6f9-6d07-4ac6-a884-88fb7dad5249
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381908744 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.381908744
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.2873776507
Short name T425
Test name
Test status
Simulation time 10340895284 ps
CPU time 13.05 seconds
Started Apr 28 01:02:21 PM PDT 24
Finished Apr 28 01:02:35 PM PDT 24
Peak memory 263680 kb
Host smart-8efe5380-13ab-4209-9344-a7906e353d7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873776507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.2873776507
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.2211690077
Short name T439
Test name
Test status
Simulation time 10675824527 ps
CPU time 8.01 seconds
Started Apr 28 01:02:24 PM PDT 24
Finished Apr 28 01:02:32 PM PDT 24
Peak memory 231096 kb
Host smart-d167adea-4da4-4973-b9f0-2ae5f16c3c94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211690077 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.2211690077
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.9067288
Short name T1086
Test name
Test status
Simulation time 886311026 ps
CPU time 2.88 seconds
Started Apr 28 01:02:23 PM PDT 24
Finished Apr 28 01:02:27 PM PDT 24
Peak memory 204076 kb
Host smart-e5516ba1-877c-4059-b06b-4c23d4a60e5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9067288 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.i2c_target_hrst.9067288
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.1524418250
Short name T3
Test name
Test status
Simulation time 9999943247 ps
CPU time 4.69 seconds
Started Apr 28 01:02:22 PM PDT 24
Finished Apr 28 01:02:27 PM PDT 24
Peak memory 204160 kb
Host smart-c7507a41-18ec-4241-8c13-cc25e7bf1597
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524418250 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.1524418250
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.4061342701
Short name T903
Test name
Test status
Simulation time 8829125394 ps
CPU time 39.11 seconds
Started Apr 28 01:02:22 PM PDT 24
Finished Apr 28 01:03:01 PM PDT 24
Peak memory 1151524 kb
Host smart-8603e9cf-f413-49f7-b221-d8eaef39440f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061342701 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.4061342701
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.3487249154
Short name T1110
Test name
Test status
Simulation time 689044851 ps
CPU time 23.59 seconds
Started Apr 28 01:02:23 PM PDT 24
Finished Apr 28 01:02:47 PM PDT 24
Peak memory 204152 kb
Host smart-3a98c2b1-037f-4452-aa8c-50cb19eabaf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487249154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.3487249154
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.2236584121
Short name T289
Test name
Test status
Simulation time 1216197986 ps
CPU time 50.79 seconds
Started Apr 28 01:02:21 PM PDT 24
Finished Apr 28 01:03:13 PM PDT 24
Peak memory 204320 kb
Host smart-78934f7a-e8ed-45af-a692-d301a047fccc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236584121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.2236584121
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.3014440369
Short name T785
Test name
Test status
Simulation time 44198125730 ps
CPU time 62.28 seconds
Started Apr 28 01:02:22 PM PDT 24
Finished Apr 28 01:03:24 PM PDT 24
Peak memory 1021404 kb
Host smart-58776f94-b4a2-46c1-bcc0-e9463eb53cfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014440369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.3014440369
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.3825588875
Short name T1272
Test name
Test status
Simulation time 17841092574 ps
CPU time 363.19 seconds
Started Apr 28 01:02:24 PM PDT 24
Finished Apr 28 01:08:27 PM PDT 24
Peak memory 2201136 kb
Host smart-b5ca05c9-67cf-4d22-a366-81ac5966ec1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825588875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.3825588875
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.694618446
Short name T460
Test name
Test status
Simulation time 4629919412 ps
CPU time 5.86 seconds
Started Apr 28 01:02:23 PM PDT 24
Finished Apr 28 01:02:29 PM PDT 24
Peak memory 204192 kb
Host smart-879e5405-f8da-4d3e-b765-8e05910c8bbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694618446 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_timeout.694618446
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.1235382151
Short name T413
Test name
Test status
Simulation time 43839759 ps
CPU time 0.6 seconds
Started Apr 28 01:02:33 PM PDT 24
Finished Apr 28 01:02:35 PM PDT 24
Peak memory 203888 kb
Host smart-880c7193-f740-4608-84fb-8b8457de144d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235382151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.1235382151
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.304681439
Short name T1116
Test name
Test status
Simulation time 158902616 ps
CPU time 1.59 seconds
Started Apr 28 01:02:29 PM PDT 24
Finished Apr 28 01:02:31 PM PDT 24
Peak memory 212492 kb
Host smart-5803c3b8-9ce1-48aa-86fa-f1526caef01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304681439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.304681439
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.4196781195
Short name T1208
Test name
Test status
Simulation time 1359909147 ps
CPU time 15.99 seconds
Started Apr 28 01:02:27 PM PDT 24
Finished Apr 28 01:02:44 PM PDT 24
Peak memory 269664 kb
Host smart-9447b8f9-2156-4ba0-a13b-8f606189b366
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196781195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.4196781195
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.1039205765
Short name T298
Test name
Test status
Simulation time 7728489717 ps
CPU time 140.34 seconds
Started Apr 28 01:02:27 PM PDT 24
Finished Apr 28 01:04:48 PM PDT 24
Peak memory 686520 kb
Host smart-2b3bbe40-4dc9-433d-97b7-703feb960979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039205765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.1039205765
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.1491574903
Short name T1336
Test name
Test status
Simulation time 4197775559 ps
CPU time 127.53 seconds
Started Apr 28 01:02:25 PM PDT 24
Finished Apr 28 01:04:34 PM PDT 24
Peak memory 643376 kb
Host smart-98f2d72a-1072-4bfb-b517-5ec877f3bf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491574903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.1491574903
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.3966531282
Short name T74
Test name
Test status
Simulation time 341038772 ps
CPU time 0.87 seconds
Started Apr 28 01:02:27 PM PDT 24
Finished Apr 28 01:02:28 PM PDT 24
Peak memory 203868 kb
Host smart-cced357b-4422-46bf-a799-a98e4fd87da2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966531282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.3966531282
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.2710051881
Short name T1311
Test name
Test status
Simulation time 414672604 ps
CPU time 3.09 seconds
Started Apr 28 01:02:27 PM PDT 24
Finished Apr 28 01:02:31 PM PDT 24
Peak memory 218032 kb
Host smart-95e0e03d-c07d-4327-a1ea-ed4a04aaf91e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710051881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.2710051881
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.3428994668
Short name T256
Test name
Test status
Simulation time 6029621887 ps
CPU time 141.15 seconds
Started Apr 28 01:02:26 PM PDT 24
Finished Apr 28 01:04:48 PM PDT 24
Peak memory 729844 kb
Host smart-28f7f6d3-f7da-457f-be30-ee852b26aada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428994668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.3428994668
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.2961046632
Short name T498
Test name
Test status
Simulation time 959062282 ps
CPU time 5.58 seconds
Started Apr 28 01:02:32 PM PDT 24
Finished Apr 28 01:02:38 PM PDT 24
Peak memory 204164 kb
Host smart-8d512765-e0dc-46b9-88fa-053326c95f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961046632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.2961046632
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.980554810
Short name T556
Test name
Test status
Simulation time 3255064282 ps
CPU time 26.2 seconds
Started Apr 28 01:02:34 PM PDT 24
Finished Apr 28 01:03:00 PM PDT 24
Peak memory 349024 kb
Host smart-cd8644ee-e527-444a-b459-fbbb2adaa89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980554810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.980554810
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.3855975468
Short name T1355
Test name
Test status
Simulation time 17540846 ps
CPU time 0.69 seconds
Started Apr 28 01:02:27 PM PDT 24
Finished Apr 28 01:02:28 PM PDT 24
Peak memory 203852 kb
Host smart-6e0d23a2-4df3-43f5-b1d3-af677ac6f668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855975468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3855975468
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.633266359
Short name T998
Test name
Test status
Simulation time 772457934 ps
CPU time 33.25 seconds
Started Apr 28 01:02:26 PM PDT 24
Finished Apr 28 01:03:01 PM PDT 24
Peak memory 253256 kb
Host smart-120ff3fa-a9b6-49a8-a7fd-374f419d8d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633266359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.633266359
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.2495999026
Short name T660
Test name
Test status
Simulation time 6290680429 ps
CPU time 18.26 seconds
Started Apr 28 01:02:25 PM PDT 24
Finished Apr 28 01:02:44 PM PDT 24
Peak memory 285636 kb
Host smart-e328ee3e-3b38-4ba1-a3fd-592780da2682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495999026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.2495999026
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.3780370274
Short name T230
Test name
Test status
Simulation time 168017934169 ps
CPU time 1540.36 seconds
Started Apr 28 01:02:26 PM PDT 24
Finished Apr 28 01:28:07 PM PDT 24
Peak memory 2946992 kb
Host smart-c1bd523f-63a6-42c8-8105-bb9cc85c06fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780370274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.3780370274
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.2126263379
Short name T513
Test name
Test status
Simulation time 981048913 ps
CPU time 4.36 seconds
Started Apr 28 01:02:34 PM PDT 24
Finished Apr 28 01:02:39 PM PDT 24
Peak memory 212268 kb
Host smart-7b0f03d0-933d-4bb5-a329-bd4bb093e99b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126263379 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2126263379
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.886533750
Short name T706
Test name
Test status
Simulation time 10151441160 ps
CPU time 62.97 seconds
Started Apr 28 01:02:27 PM PDT 24
Finished Apr 28 01:03:30 PM PDT 24
Peak memory 421592 kb
Host smart-7e5aa836-1739-4de2-8a87-6f987d88f683
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886533750 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_acq.886533750
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.1179929407
Short name T1034
Test name
Test status
Simulation time 10548115507 ps
CPU time 14.84 seconds
Started Apr 28 01:02:30 PM PDT 24
Finished Apr 28 01:02:45 PM PDT 24
Peak memory 300484 kb
Host smart-822ead26-e910-4123-9478-1d6c6cbf2143
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179929407 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.1179929407
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.671826922
Short name T307
Test name
Test status
Simulation time 2065622424 ps
CPU time 2.77 seconds
Started Apr 28 01:02:33 PM PDT 24
Finished Apr 28 01:02:37 PM PDT 24
Peak memory 204092 kb
Host smart-ee563dd0-bae0-4b8f-8234-bde08da4939c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671826922 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.i2c_target_hrst.671826922
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.3797667014
Short name T501
Test name
Test status
Simulation time 4691379870 ps
CPU time 4.82 seconds
Started Apr 28 01:02:29 PM PDT 24
Finished Apr 28 01:02:34 PM PDT 24
Peak memory 219108 kb
Host smart-8b3083e5-e695-48b6-bcce-f455f20efbb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797667014 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.3797667014
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.1920021235
Short name T20
Test name
Test status
Simulation time 11928433810 ps
CPU time 12.4 seconds
Started Apr 28 01:02:28 PM PDT 24
Finished Apr 28 01:02:41 PM PDT 24
Peak memory 333432 kb
Host smart-37881945-ec0f-4ed9-8aa2-3db7494ddb2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920021235 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.1920021235
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.2811717703
Short name T781
Test name
Test status
Simulation time 798010573 ps
CPU time 30.51 seconds
Started Apr 28 01:02:29 PM PDT 24
Finished Apr 28 01:03:00 PM PDT 24
Peak memory 204116 kb
Host smart-4802def6-b0b2-4ae5-a32f-a65ae2cbd610
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811717703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.2811717703
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_all.3165966637
Short name T1329
Test name
Test status
Simulation time 98245158456 ps
CPU time 594.24 seconds
Started Apr 28 01:02:26 PM PDT 24
Finished Apr 28 01:12:22 PM PDT 24
Peak memory 3499568 kb
Host smart-8dc8511d-dbf7-4cbd-a181-8186d163b53a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165966637 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.i2c_target_stress_all.3165966637
Directory /workspace/37.i2c_target_stress_all/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.3105827972
Short name T1283
Test name
Test status
Simulation time 3437112426 ps
CPU time 15.59 seconds
Started Apr 28 01:02:27 PM PDT 24
Finished Apr 28 01:02:43 PM PDT 24
Peak memory 216372 kb
Host smart-055755ba-9c65-4610-839e-4d95931619a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105827972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.3105827972
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.616467238
Short name T315
Test name
Test status
Simulation time 37157809091 ps
CPU time 163.93 seconds
Started Apr 28 01:02:28 PM PDT 24
Finished Apr 28 01:05:12 PM PDT 24
Peak memory 2209916 kb
Host smart-82fe35ed-387b-4591-80cf-99a49f9a6334
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616467238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_wr.616467238
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.1448320829
Short name T779
Test name
Test status
Simulation time 24754505196 ps
CPU time 149.17 seconds
Started Apr 28 01:02:27 PM PDT 24
Finished Apr 28 01:04:57 PM PDT 24
Peak memory 1457388 kb
Host smart-bd94743b-09c9-4838-b954-1800a7c8d3b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448320829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.1448320829
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.3151211531
Short name T11
Test name
Test status
Simulation time 2910968781 ps
CPU time 7.09 seconds
Started Apr 28 01:02:27 PM PDT 24
Finished Apr 28 01:02:35 PM PDT 24
Peak memory 217460 kb
Host smart-8cea509b-aa1f-4031-81b3-0135f2323dc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151211531 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.3151211531
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.1821535
Short name T344
Test name
Test status
Simulation time 27282055 ps
CPU time 0.59 seconds
Started Apr 28 01:02:37 PM PDT 24
Finished Apr 28 01:02:38 PM PDT 24
Peak memory 203888 kb
Host smart-bf094029-2a80-4131-9614-7f33564a0aef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1821535
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.4142757293
Short name T632
Test name
Test status
Simulation time 363782662 ps
CPU time 1.44 seconds
Started Apr 28 01:02:32 PM PDT 24
Finished Apr 28 01:02:34 PM PDT 24
Peak memory 212372 kb
Host smart-9457106c-14e4-432a-b361-dd9f4e5d6a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142757293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.4142757293
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2270375481
Short name T215
Test name
Test status
Simulation time 1461943570 ps
CPU time 20.59 seconds
Started Apr 28 01:02:33 PM PDT 24
Finished Apr 28 01:02:54 PM PDT 24
Peak memory 291056 kb
Host smart-6cb085f5-e5aa-4849-8a2a-dc63a751de73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270375481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2270375481
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.945306593
Short name T309
Test name
Test status
Simulation time 8335203642 ps
CPU time 139.86 seconds
Started Apr 28 01:02:34 PM PDT 24
Finished Apr 28 01:04:55 PM PDT 24
Peak memory 657292 kb
Host smart-fd78ea89-bf49-44cf-8029-792ba5360f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945306593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.945306593
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.2667963319
Short name T727
Test name
Test status
Simulation time 7752816869 ps
CPU time 140.09 seconds
Started Apr 28 01:02:31 PM PDT 24
Finished Apr 28 01:04:52 PM PDT 24
Peak memory 668612 kb
Host smart-66593602-5f50-4379-9a75-93229dc2a250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667963319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2667963319
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.1938033865
Short name T862
Test name
Test status
Simulation time 148204370 ps
CPU time 1.06 seconds
Started Apr 28 01:02:32 PM PDT 24
Finished Apr 28 01:02:34 PM PDT 24
Peak memory 204064 kb
Host smart-cd3ff854-c874-4e83-ba02-0d0138e8e1e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938033865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.1938033865
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.4000657355
Short name T1093
Test name
Test status
Simulation time 357524308 ps
CPU time 3.95 seconds
Started Apr 28 01:02:35 PM PDT 24
Finished Apr 28 01:02:40 PM PDT 24
Peak memory 204216 kb
Host smart-074d05a3-c76e-47bb-a47d-353e4f8a8ed3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000657355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.4000657355
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.499678923
Short name T968
Test name
Test status
Simulation time 3424714240 ps
CPU time 49.28 seconds
Started Apr 28 01:02:34 PM PDT 24
Finished Apr 28 01:03:24 PM PDT 24
Peak memory 740408 kb
Host smart-9a465797-3d41-4176-aa1a-06bfab87e698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499678923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.499678923
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.1172018966
Short name T1234
Test name
Test status
Simulation time 387287740 ps
CPU time 15.91 seconds
Started Apr 28 01:02:41 PM PDT 24
Finished Apr 28 01:02:58 PM PDT 24
Peak memory 204144 kb
Host smart-30909e22-4e03-4206-966c-7c8f3b560255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172018966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.1172018966
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.3862682571
Short name T1094
Test name
Test status
Simulation time 5082274761 ps
CPU time 22.75 seconds
Started Apr 28 01:02:39 PM PDT 24
Finished Apr 28 01:03:03 PM PDT 24
Peak memory 283236 kb
Host smart-efe160ef-236f-4acf-924b-b457144cd0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862682571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.3862682571
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.3774105280
Short name T208
Test name
Test status
Simulation time 28196650 ps
CPU time 0.66 seconds
Started Apr 28 01:02:38 PM PDT 24
Finished Apr 28 01:02:39 PM PDT 24
Peak memory 203760 kb
Host smart-54f2f08a-dea7-40b7-9106-77b4957a1ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774105280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3774105280
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.649561414
Short name T64
Test name
Test status
Simulation time 19792829595 ps
CPU time 86.53 seconds
Started Apr 28 01:02:35 PM PDT 24
Finished Apr 28 01:04:02 PM PDT 24
Peak memory 212384 kb
Host smart-9e01b4e3-cb97-465d-9771-2c1837a35208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649561414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.649561414
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.4148543271
Short name T1273
Test name
Test status
Simulation time 1494240974 ps
CPU time 31.95 seconds
Started Apr 28 01:02:33 PM PDT 24
Finished Apr 28 01:03:06 PM PDT 24
Peak memory 367156 kb
Host smart-1a9e5d58-8d67-4859-8c0d-179ab8ed1b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148543271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.4148543271
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.1193468473
Short name T198
Test name
Test status
Simulation time 26137154477 ps
CPU time 213.14 seconds
Started Apr 28 01:02:36 PM PDT 24
Finished Apr 28 01:06:09 PM PDT 24
Peak memory 1000004 kb
Host smart-5d81cd2f-c89b-4408-841e-7f882549acab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193468473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.1193468473
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.3991669867
Short name T1164
Test name
Test status
Simulation time 6013902514 ps
CPU time 9.02 seconds
Started Apr 28 01:02:34 PM PDT 24
Finished Apr 28 01:02:44 PM PDT 24
Peak memory 219516 kb
Host smart-a98eb64e-88cc-426e-a4c4-9e5175cee75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991669867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.3991669867
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.4133014697
Short name T1099
Test name
Test status
Simulation time 4105444111 ps
CPU time 4.64 seconds
Started Apr 28 01:02:38 PM PDT 24
Finished Apr 28 01:02:43 PM PDT 24
Peak memory 212264 kb
Host smart-267849a2-d4f0-4706-ab4a-043a378f5a4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133014697 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.4133014697
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.1294243949
Short name T981
Test name
Test status
Simulation time 10447793916 ps
CPU time 13.36 seconds
Started Apr 28 01:02:38 PM PDT 24
Finished Apr 28 01:02:52 PM PDT 24
Peak memory 277304 kb
Host smart-82bd328e-af70-40ca-b142-ad309cb43fe3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294243949 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.1294243949
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.4060721269
Short name T988
Test name
Test status
Simulation time 10240923404 ps
CPU time 7.08 seconds
Started Apr 28 01:02:37 PM PDT 24
Finished Apr 28 01:02:44 PM PDT 24
Peak memory 241420 kb
Host smart-72ee03d6-fad9-4106-aabb-67edf5c86a34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060721269 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.4060721269
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.3376931070
Short name T898
Test name
Test status
Simulation time 1588915512 ps
CPU time 2.8 seconds
Started Apr 28 01:02:41 PM PDT 24
Finished Apr 28 01:02:44 PM PDT 24
Peak memory 204144 kb
Host smart-2821e681-75a2-4f5e-883a-195ba56db6ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376931070 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.3376931070
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.3041434558
Short name T295
Test name
Test status
Simulation time 2554637709 ps
CPU time 3.49 seconds
Started Apr 28 01:02:34 PM PDT 24
Finished Apr 28 01:02:38 PM PDT 24
Peak memory 204224 kb
Host smart-a6cb41b5-8eea-4921-bc74-d2bb0669ce73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041434558 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.3041434558
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.2076133291
Short name T858
Test name
Test status
Simulation time 8456206263 ps
CPU time 15.15 seconds
Started Apr 28 01:02:33 PM PDT 24
Finished Apr 28 01:02:48 PM PDT 24
Peak memory 603464 kb
Host smart-6bc87883-dfdc-4362-a90c-177ea46e8b0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076133291 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.2076133291
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.3587219594
Short name T1038
Test name
Test status
Simulation time 3600922737 ps
CPU time 13.69 seconds
Started Apr 28 01:02:35 PM PDT 24
Finished Apr 28 01:02:49 PM PDT 24
Peak memory 204216 kb
Host smart-a2c51016-f29b-4659-8456-00146a59bfc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587219594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.3587219594
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.3874711944
Short name T539
Test name
Test status
Simulation time 1347204376 ps
CPU time 18.48 seconds
Started Apr 28 01:02:34 PM PDT 24
Finished Apr 28 01:02:53 PM PDT 24
Peak memory 225884 kb
Host smart-c19c906d-0f34-4b1b-b4da-b48af2f712cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874711944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.3874711944
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.2356173804
Short name T366
Test name
Test status
Simulation time 37447679604 ps
CPU time 550.65 seconds
Started Apr 28 01:02:34 PM PDT 24
Finished Apr 28 01:11:46 PM PDT 24
Peak memory 4344692 kb
Host smart-3e0da8aa-4105-402a-82ca-875e3b7e68d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356173804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.2356173804
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.1690258860
Short name T929
Test name
Test status
Simulation time 21590428115 ps
CPU time 1384.09 seconds
Started Apr 28 01:02:34 PM PDT 24
Finished Apr 28 01:25:38 PM PDT 24
Peak memory 2620948 kb
Host smart-7c2b26ff-ed8b-4a49-a5c5-673a8bc5055a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690258860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.1690258860
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.3960130050
Short name T1232
Test name
Test status
Simulation time 4730156563 ps
CPU time 6.04 seconds
Started Apr 28 01:02:37 PM PDT 24
Finished Apr 28 01:02:44 PM PDT 24
Peak memory 212348 kb
Host smart-7035cd3f-02fc-4ed6-8253-e965fb42eae5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960130050 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.3960130050
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.3823015869
Short name T1221
Test name
Test status
Simulation time 32494483 ps
CPU time 0.61 seconds
Started Apr 28 01:02:43 PM PDT 24
Finished Apr 28 01:02:44 PM PDT 24
Peak memory 203856 kb
Host smart-26512984-0cfb-459e-93b8-a712ca75032c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823015869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3823015869
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.164027546
Short name T1025
Test name
Test status
Simulation time 768310236 ps
CPU time 1.29 seconds
Started Apr 28 01:02:38 PM PDT 24
Finished Apr 28 01:02:40 PM PDT 24
Peak memory 216404 kb
Host smart-268c3582-28a3-4378-9a64-6332da2a626c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164027546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.164027546
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.2620467039
Short name T740
Test name
Test status
Simulation time 1252523632 ps
CPU time 6.8 seconds
Started Apr 28 01:02:42 PM PDT 24
Finished Apr 28 01:02:49 PM PDT 24
Peak memory 262636 kb
Host smart-9b18ad2e-86ca-4969-bedb-19f0e8114183
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620467039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.2620467039
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.412692625
Short name T1201
Test name
Test status
Simulation time 8131704389 ps
CPU time 97.69 seconds
Started Apr 28 01:02:39 PM PDT 24
Finished Apr 28 01:04:17 PM PDT 24
Peak memory 510380 kb
Host smart-c94f09bc-a7ef-4e4c-a7ea-f48833b6fdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412692625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.412692625
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.3796150050
Short name T577
Test name
Test status
Simulation time 2101985195 ps
CPU time 59.67 seconds
Started Apr 28 01:02:37 PM PDT 24
Finished Apr 28 01:03:38 PM PDT 24
Peak memory 724652 kb
Host smart-56f53dd9-a8ff-4fad-a93c-573ce4870325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796150050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.3796150050
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.2633813714
Short name T480
Test name
Test status
Simulation time 133724759 ps
CPU time 1.17 seconds
Started Apr 28 01:02:40 PM PDT 24
Finished Apr 28 01:02:42 PM PDT 24
Peak memory 204032 kb
Host smart-0d3259a7-d018-4a19-b1a8-0f3cfbcaba0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633813714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.2633813714
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.3305702238
Short name T1292
Test name
Test status
Simulation time 2000058609 ps
CPU time 3.72 seconds
Started Apr 28 01:02:37 PM PDT 24
Finished Apr 28 01:02:42 PM PDT 24
Peak memory 204032 kb
Host smart-bca0e482-ac2c-4090-9d80-f3c91048cd92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305702238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.3305702238
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.1509951137
Short name T921
Test name
Test status
Simulation time 2585558279 ps
CPU time 58.15 seconds
Started Apr 28 01:02:39 PM PDT 24
Finished Apr 28 01:03:38 PM PDT 24
Peak memory 807228 kb
Host smart-0f6bb611-3fa8-4bf2-9002-658de72c36be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509951137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1509951137
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.2995511226
Short name T736
Test name
Test status
Simulation time 862252892 ps
CPU time 16.89 seconds
Started Apr 28 01:02:43 PM PDT 24
Finished Apr 28 01:03:00 PM PDT 24
Peak memory 204096 kb
Host smart-2e9ebc82-86d6-45ba-b9ac-c93ff67c01ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995511226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.2995511226
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.3136779209
Short name T118
Test name
Test status
Simulation time 14101614418 ps
CPU time 24.59 seconds
Started Apr 28 01:02:41 PM PDT 24
Finished Apr 28 01:03:06 PM PDT 24
Peak memory 302396 kb
Host smart-e6364436-d34f-4892-a4e1-dc957bcc0eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136779209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.3136779209
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.2473391127
Short name T958
Test name
Test status
Simulation time 44611024 ps
CPU time 0.65 seconds
Started Apr 28 01:02:38 PM PDT 24
Finished Apr 28 01:02:39 PM PDT 24
Peak memory 203812 kb
Host smart-42280c69-9ce3-4321-b6e9-40372e73f3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473391127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.2473391127
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.3069113630
Short name T78
Test name
Test status
Simulation time 8288610434 ps
CPU time 18.85 seconds
Started Apr 28 01:02:39 PM PDT 24
Finished Apr 28 01:02:59 PM PDT 24
Peak memory 249748 kb
Host smart-bb371814-184a-4936-9733-ac1608ef2224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069113630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.3069113630
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.103947103
Short name T1222
Test name
Test status
Simulation time 15012697774 ps
CPU time 80.6 seconds
Started Apr 28 01:02:37 PM PDT 24
Finished Apr 28 01:03:58 PM PDT 24
Peak memory 317272 kb
Host smart-fe3ff221-f937-4d70-9a2a-7bbbbfaf2425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103947103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.103947103
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.3045170585
Short name T606
Test name
Test status
Simulation time 806045613 ps
CPU time 35.19 seconds
Started Apr 28 01:02:41 PM PDT 24
Finished Apr 28 01:03:16 PM PDT 24
Peak memory 212344 kb
Host smart-b9f51878-33f5-4cbd-a9a9-6456c67b752e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045170585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.3045170585
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.667719315
Short name T1209
Test name
Test status
Simulation time 1460201196 ps
CPU time 3.83 seconds
Started Apr 28 01:02:49 PM PDT 24
Finished Apr 28 01:02:53 PM PDT 24
Peak memory 212376 kb
Host smart-0adbe2ec-e1c7-4646-9747-6d2af6bbb7e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667719315 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.667719315
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2674496917
Short name T1061
Test name
Test status
Simulation time 11298366883 ps
CPU time 6.65 seconds
Started Apr 28 01:02:48 PM PDT 24
Finished Apr 28 01:02:56 PM PDT 24
Peak memory 248832 kb
Host smart-49287e3b-3fcb-4a89-bab0-e0701d995045
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674496917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.2674496917
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.3140790939
Short name T1015
Test name
Test status
Simulation time 10146388302 ps
CPU time 27.49 seconds
Started Apr 28 01:02:46 PM PDT 24
Finished Apr 28 01:03:14 PM PDT 24
Peak memory 343928 kb
Host smart-3517e180-0cab-4aaf-91dc-ea18b6346f08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140790939 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.3140790939
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.1859053413
Short name T281
Test name
Test status
Simulation time 762549020 ps
CPU time 2.45 seconds
Started Apr 28 01:02:43 PM PDT 24
Finished Apr 28 01:02:46 PM PDT 24
Peak memory 204212 kb
Host smart-fc7d65f4-2622-4a5f-a3b4-af73ed467e51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859053413 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.1859053413
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.1670611615
Short name T1255
Test name
Test status
Simulation time 1788597415 ps
CPU time 4.53 seconds
Started Apr 28 01:02:37 PM PDT 24
Finished Apr 28 01:02:42 PM PDT 24
Peak memory 204216 kb
Host smart-4f8aee88-f02c-4913-936a-2c639251769c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670611615 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.1670611615
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.2654205052
Short name T610
Test name
Test status
Simulation time 14170652217 ps
CPU time 25.02 seconds
Started Apr 28 01:02:39 PM PDT 24
Finished Apr 28 01:03:05 PM PDT 24
Peak memory 548024 kb
Host smart-242db2aa-ab7a-4ed9-9e53-efea990e48a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654205052 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.2654205052
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.613550057
Short name T1247
Test name
Test status
Simulation time 2952292826 ps
CPU time 10.77 seconds
Started Apr 28 01:02:36 PM PDT 24
Finished Apr 28 01:02:48 PM PDT 24
Peak memory 204076 kb
Host smart-19c366db-2206-462d-bfb0-839fbcc86d28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613550057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_tar
get_smoke.613550057
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.1492786422
Short name T1175
Test name
Test status
Simulation time 1035102150 ps
CPU time 9.47 seconds
Started Apr 28 01:02:41 PM PDT 24
Finished Apr 28 01:02:51 PM PDT 24
Peak memory 204128 kb
Host smart-e6470474-86b6-4b9b-a8b7-b1dbbfcf8a3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492786422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.1492786422
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.2835313932
Short name T887
Test name
Test status
Simulation time 61211004694 ps
CPU time 1900.34 seconds
Started Apr 28 01:02:42 PM PDT 24
Finished Apr 28 01:34:23 PM PDT 24
Peak memory 10379760 kb
Host smart-e1a8d909-b3cd-41a0-b776-866505663679
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835313932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.2835313932
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.29628199
Short name T494
Test name
Test status
Simulation time 30339674172 ps
CPU time 2548.95 seconds
Started Apr 28 01:02:40 PM PDT 24
Finished Apr 28 01:45:10 PM PDT 24
Peak memory 4511204 kb
Host smart-9f0aedb0-ce62-4ac4-be75-707d492b193c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29628199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_stretch.29628199
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.2517737215
Short name T188
Test name
Test status
Simulation time 1075662279 ps
CPU time 6.45 seconds
Started Apr 28 01:02:41 PM PDT 24
Finished Apr 28 01:02:48 PM PDT 24
Peak memory 212368 kb
Host smart-910c4410-2353-4bd6-ad65-fad815b85279
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517737215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.2517737215
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_unexp_stop.1776089963
Short name T28
Test name
Test status
Simulation time 1315551303 ps
CPU time 6.12 seconds
Started Apr 28 01:02:43 PM PDT 24
Finished Apr 28 01:02:50 PM PDT 24
Peak memory 205844 kb
Host smart-8c2cf832-fbe8-4a53-a799-49c6f40db2d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776089963 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.i2c_target_unexp_stop.1776089963
Directory /workspace/39.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/4.i2c_alert_test.1780664459
Short name T657
Test name
Test status
Simulation time 66681411 ps
CPU time 0.6 seconds
Started Apr 28 12:59:07 PM PDT 24
Finished Apr 28 12:59:09 PM PDT 24
Peak memory 203640 kb
Host smart-8741f3c1-e890-4bdd-b3a3-5dd757833ec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780664459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.1780664459
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.938318050
Short name T854
Test name
Test status
Simulation time 261956935 ps
CPU time 1.32 seconds
Started Apr 28 12:59:04 PM PDT 24
Finished Apr 28 12:59:07 PM PDT 24
Peak memory 212404 kb
Host smart-817ec916-26c6-4004-a6d2-613186ad3d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938318050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.938318050
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.845543268
Short name T757
Test name
Test status
Simulation time 1120631870 ps
CPU time 6.94 seconds
Started Apr 28 12:59:02 PM PDT 24
Finished Apr 28 12:59:11 PM PDT 24
Peak memory 265592 kb
Host smart-10024d6b-cba3-4da1-835f-26ce316dc504
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845543268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty
.845543268
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.3548020623
Short name T618
Test name
Test status
Simulation time 5222995478 ps
CPU time 86.61 seconds
Started Apr 28 12:59:02 PM PDT 24
Finished Apr 28 01:00:31 PM PDT 24
Peak memory 528360 kb
Host smart-eb658716-f227-422a-9a29-2956aa6d5caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548020623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3548020623
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.205559484
Short name T1348
Test name
Test status
Simulation time 2524189001 ps
CPU time 36.28 seconds
Started Apr 28 12:59:10 PM PDT 24
Finished Apr 28 12:59:50 PM PDT 24
Peak memory 453832 kb
Host smart-894bc1b2-5888-445f-8b96-ca0c38d4e838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205559484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.205559484
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.449800787
Short name T807
Test name
Test status
Simulation time 199655741 ps
CPU time 0.97 seconds
Started Apr 28 12:58:59 PM PDT 24
Finished Apr 28 12:59:01 PM PDT 24
Peak memory 204024 kb
Host smart-d9569c90-a47f-41ea-b756-80699c5a17ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449800787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt
.449800787
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.820809615
Short name T123
Test name
Test status
Simulation time 241454812 ps
CPU time 7.24 seconds
Started Apr 28 12:59:04 PM PDT 24
Finished Apr 28 12:59:13 PM PDT 24
Peak memory 204080 kb
Host smart-d25ad009-ad72-42b0-ad04-4e60fc9c2d2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820809615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.820809615
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.882319352
Short name T10
Test name
Test status
Simulation time 4936393469 ps
CPU time 230.02 seconds
Started Apr 28 12:59:15 PM PDT 24
Finished Apr 28 01:03:07 PM PDT 24
Peak memory 1000660 kb
Host smart-f1ac8188-8103-4550-a03a-65ef19e077c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882319352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.882319352
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.1130470317
Short name T804
Test name
Test status
Simulation time 1148752023 ps
CPU time 23.63 seconds
Started Apr 28 12:59:02 PM PDT 24
Finished Apr 28 12:59:28 PM PDT 24
Peak memory 204168 kb
Host smart-397088a0-7397-44aa-a95f-4c7f5883c6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130470317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.1130470317
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.425478765
Short name T1334
Test name
Test status
Simulation time 1970882914 ps
CPU time 86.9 seconds
Started Apr 28 12:59:05 PM PDT 24
Finished Apr 28 01:00:34 PM PDT 24
Peak memory 362000 kb
Host smart-56001aa2-d435-4606-a8ba-55ee123a3d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425478765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.425478765
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.1186856061
Short name T557
Test name
Test status
Simulation time 89465571 ps
CPU time 0.67 seconds
Started Apr 28 12:59:05 PM PDT 24
Finished Apr 28 12:59:08 PM PDT 24
Peak memory 203832 kb
Host smart-a75b45c4-a279-4a6a-babd-27b2c997a20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186856061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.1186856061
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.205525651
Short name T876
Test name
Test status
Simulation time 7045031849 ps
CPU time 101.47 seconds
Started Apr 28 12:59:02 PM PDT 24
Finished Apr 28 01:00:45 PM PDT 24
Peak memory 589408 kb
Host smart-49641af1-9d79-4e60-8b4c-9965c3aca337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205525651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.205525651
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.2722534083
Short name T276
Test name
Test status
Simulation time 889494143 ps
CPU time 17.71 seconds
Started Apr 28 12:59:06 PM PDT 24
Finished Apr 28 12:59:26 PM PDT 24
Peak memory 306416 kb
Host smart-6932b991-9823-47b6-8fb7-9b5ed9b5bee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722534083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.2722534083
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.369570737
Short name T260
Test name
Test status
Simulation time 6586079055 ps
CPU time 500.53 seconds
Started Apr 28 12:59:12 PM PDT 24
Finished Apr 28 01:07:36 PM PDT 24
Peak memory 1178168 kb
Host smart-11ed3127-c10a-434c-ab61-dcd06ab73fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369570737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.369570737
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.2370969499
Short name T712
Test name
Test status
Simulation time 965296049 ps
CPU time 9.45 seconds
Started Apr 28 12:59:15 PM PDT 24
Finished Apr 28 12:59:26 PM PDT 24
Peak memory 214220 kb
Host smart-970cc6c3-c27a-4ae3-b6ed-bb0e19286ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370969499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.2370969499
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.2313590513
Short name T116
Test name
Test status
Simulation time 652411460 ps
CPU time 0.81 seconds
Started Apr 28 12:59:11 PM PDT 24
Finished Apr 28 12:59:15 PM PDT 24
Peak memory 221480 kb
Host smart-713d7050-92ba-43db-aa66-6978145c1e98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313590513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2313590513
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.3036498002
Short name T748
Test name
Test status
Simulation time 2412347664 ps
CPU time 3.25 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 12:59:09 PM PDT 24
Peak memory 204240 kb
Host smart-6f723fc6-0637-4b5e-b218-bd67dff82ff8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036498002 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.3036498002
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.3753128897
Short name T1260
Test name
Test status
Simulation time 10137766121 ps
CPU time 24.34 seconds
Started Apr 28 12:59:06 PM PDT 24
Finished Apr 28 12:59:33 PM PDT 24
Peak memory 280824 kb
Host smart-d19dcaab-ad12-44f5-9ae4-4cdcb0cc0333
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753128897 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.3753128897
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.1798339933
Short name T623
Test name
Test status
Simulation time 10104250521 ps
CPU time 76.44 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 01:00:22 PM PDT 24
Peak memory 563408 kb
Host smart-87ac8f1c-6ecf-4e8c-8f8b-812fbc84472b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798339933 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.1798339933
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.2674963379
Short name T449
Test name
Test status
Simulation time 1868484138 ps
CPU time 2.46 seconds
Started Apr 28 12:59:09 PM PDT 24
Finished Apr 28 12:59:15 PM PDT 24
Peak memory 204156 kb
Host smart-2a94a485-1de5-4c1b-8f61-e3095ecbd832
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674963379 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.2674963379
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.962523233
Short name T404
Test name
Test status
Simulation time 4262570196 ps
CPU time 5.03 seconds
Started Apr 28 12:59:06 PM PDT 24
Finished Apr 28 12:59:13 PM PDT 24
Peak memory 214596 kb
Host smart-b2106f82-faed-43d8-821f-088c56b52a02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962523233 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_intr_smoke.962523233
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.2114880762
Short name T30
Test name
Test status
Simulation time 18239770171 ps
CPU time 306.43 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 01:04:11 PM PDT 24
Peak memory 2952392 kb
Host smart-6b3a64b3-89ef-40e8-b2db-e560679adfcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114880762 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.2114880762
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.2031650643
Short name T558
Test name
Test status
Simulation time 7259855182 ps
CPU time 11.49 seconds
Started Apr 28 12:59:05 PM PDT 24
Finished Apr 28 12:59:18 PM PDT 24
Peak memory 204128 kb
Host smart-441f5f8b-4b54-4f60-aaa3-b02fdece89d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031650643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.2031650643
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.3448812057
Short name T777
Test name
Test status
Simulation time 3324553434 ps
CPU time 7.69 seconds
Started Apr 28 12:59:08 PM PDT 24
Finished Apr 28 12:59:19 PM PDT 24
Peak memory 204240 kb
Host smart-45152c4f-6a07-41b5-a59b-9a24e3ebe795
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448812057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.3448812057
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2572204997
Short name T809
Test name
Test status
Simulation time 28208490845 ps
CPU time 41.05 seconds
Started Apr 28 12:59:04 PM PDT 24
Finished Apr 28 12:59:47 PM PDT 24
Peak memory 811216 kb
Host smart-ed7c2d64-fe88-4ea5-8081-160ed03d0b48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572204997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2572204997
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.1246751360
Short name T1133
Test name
Test status
Simulation time 22759228614 ps
CPU time 1752.92 seconds
Started Apr 28 12:59:11 PM PDT 24
Finished Apr 28 01:28:28 PM PDT 24
Peak memory 5353536 kb
Host smart-6db48169-f755-4636-8e3f-8b984f801d94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246751360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.1246751360
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.4244612411
Short name T432
Test name
Test status
Simulation time 7275816566 ps
CPU time 6.42 seconds
Started Apr 28 12:58:58 PM PDT 24
Finished Apr 28 12:59:05 PM PDT 24
Peak memory 216980 kb
Host smart-37783c1d-3990-40e4-8606-363a4f0c90f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244612411 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.4244612411
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.356074787
Short name T871
Test name
Test status
Simulation time 45058010 ps
CPU time 0.66 seconds
Started Apr 28 01:02:50 PM PDT 24
Finished Apr 28 01:02:51 PM PDT 24
Peak memory 203764 kb
Host smart-2432970b-43d0-4f6a-b455-002ac7cce0fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356074787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.356074787
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.25628405
Short name T516
Test name
Test status
Simulation time 1597832824 ps
CPU time 1.37 seconds
Started Apr 28 01:02:43 PM PDT 24
Finished Apr 28 01:02:45 PM PDT 24
Peak memory 212444 kb
Host smart-1348ad77-01bb-4ab0-976e-fcebbd0359b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25628405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.25628405
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.1497573537
Short name T579
Test name
Test status
Simulation time 1916025121 ps
CPU time 4.29 seconds
Started Apr 28 01:02:47 PM PDT 24
Finished Apr 28 01:02:51 PM PDT 24
Peak memory 250848 kb
Host smart-77af3b5b-d39c-456c-9d9e-7f83801620c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497573537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.1497573537
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.2999168030
Short name T420
Test name
Test status
Simulation time 1256730665 ps
CPU time 60.76 seconds
Started Apr 28 01:02:45 PM PDT 24
Finished Apr 28 01:03:46 PM PDT 24
Peak memory 445524 kb
Host smart-90159a53-49b5-419b-9491-e93ffd044557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999168030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.2999168030
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.1617793164
Short name T358
Test name
Test status
Simulation time 1984740481 ps
CPU time 143.22 seconds
Started Apr 28 01:02:45 PM PDT 24
Finished Apr 28 01:05:08 PM PDT 24
Peak memory 645364 kb
Host smart-2f4bda7d-9556-4add-bab2-9d056c962f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617793164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1617793164
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.1431054796
Short name T75
Test name
Test status
Simulation time 112315457 ps
CPU time 0.95 seconds
Started Apr 28 01:02:44 PM PDT 24
Finished Apr 28 01:02:46 PM PDT 24
Peak memory 203988 kb
Host smart-397f1f11-c875-4d94-b7a6-292d0a5ede08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431054796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.1431054796
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.2058887068
Short name T431
Test name
Test status
Simulation time 588298314 ps
CPU time 4.24 seconds
Started Apr 28 01:02:42 PM PDT 24
Finished Apr 28 01:02:47 PM PDT 24
Peak memory 229300 kb
Host smart-c4f536eb-2288-4bae-ac83-5f4a36eec72a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058887068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.2058887068
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.2542601901
Short name T310
Test name
Test status
Simulation time 2889405983 ps
CPU time 201.73 seconds
Started Apr 28 01:02:45 PM PDT 24
Finished Apr 28 01:06:07 PM PDT 24
Peak memory 898296 kb
Host smart-1d103b7b-d413-4368-bca3-5af2edd14402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542601901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.2542601901
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.1168191439
Short name T523
Test name
Test status
Simulation time 3563304516 ps
CPU time 5.08 seconds
Started Apr 28 01:02:50 PM PDT 24
Finished Apr 28 01:02:56 PM PDT 24
Peak memory 204284 kb
Host smart-af679d36-c441-4bf1-88b4-c2a4bf053dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168191439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.1168191439
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.1874430467
Short name T1168
Test name
Test status
Simulation time 3176978551 ps
CPU time 20.85 seconds
Started Apr 28 01:02:50 PM PDT 24
Finished Apr 28 01:03:11 PM PDT 24
Peak memory 265376 kb
Host smart-6604f27d-7193-4077-bbbf-1caf5de1321c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874430467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.1874430467
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.3256667229
Short name T555
Test name
Test status
Simulation time 39028201 ps
CPU time 0.64 seconds
Started Apr 28 01:02:42 PM PDT 24
Finished Apr 28 01:02:43 PM PDT 24
Peak memory 203672 kb
Host smart-2dda5f4d-1f3a-45fa-963f-d4df01346e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256667229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3256667229
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.1863685333
Short name T956
Test name
Test status
Simulation time 3202741868 ps
CPU time 63.71 seconds
Started Apr 28 01:02:43 PM PDT 24
Finished Apr 28 01:03:47 PM PDT 24
Peak memory 215212 kb
Host smart-5f53dd85-be6a-4e67-a4ab-2ab41086dc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863685333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.1863685333
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.3297513358
Short name T438
Test name
Test status
Simulation time 4838629124 ps
CPU time 52.68 seconds
Started Apr 28 01:02:52 PM PDT 24
Finished Apr 28 01:03:45 PM PDT 24
Peak memory 261284 kb
Host smart-28d0f332-27e4-488a-8b0f-e3c02bbbc8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297513358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.3297513358
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.1389155270
Short name T1338
Test name
Test status
Simulation time 89819884682 ps
CPU time 539.64 seconds
Started Apr 28 01:02:42 PM PDT 24
Finished Apr 28 01:11:42 PM PDT 24
Peak memory 2001764 kb
Host smart-16abcbdc-323c-48e6-bd4a-02a4a7a3fbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389155270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.1389155270
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.784796622
Short name T797
Test name
Test status
Simulation time 531114279 ps
CPU time 10.42 seconds
Started Apr 28 01:02:45 PM PDT 24
Finished Apr 28 01:02:56 PM PDT 24
Peak memory 215500 kb
Host smart-7f109084-0d92-4251-94dc-6b0eb161cb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784796622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.784796622
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.2888123974
Short name T770
Test name
Test status
Simulation time 520360501 ps
CPU time 2.85 seconds
Started Apr 28 01:02:53 PM PDT 24
Finished Apr 28 01:02:56 PM PDT 24
Peak memory 204200 kb
Host smart-2c39ab8f-c613-4d65-9d54-e8e39ecdadba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888123974 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.2888123974
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.4225218329
Short name T86
Test name
Test status
Simulation time 10034564828 ps
CPU time 76.41 seconds
Started Apr 28 01:02:48 PM PDT 24
Finished Apr 28 01:04:05 PM PDT 24
Peak memory 465732 kb
Host smart-0f8e5f04-e250-46e0-b36f-abd51ae75fe4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225218329 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.4225218329
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.3140037312
Short name T681
Test name
Test status
Simulation time 10053414878 ps
CPU time 79.52 seconds
Started Apr 28 01:02:49 PM PDT 24
Finished Apr 28 01:04:09 PM PDT 24
Peak memory 464564 kb
Host smart-c6b4dd46-ae09-4aff-9c60-bd943b575d1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140037312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.3140037312
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.642660503
Short name T1108
Test name
Test status
Simulation time 496003274 ps
CPU time 1.88 seconds
Started Apr 28 01:02:50 PM PDT 24
Finished Apr 28 01:02:52 PM PDT 24
Peak memory 204096 kb
Host smart-988931ba-160e-43e0-bd16-5b8d7b29d555
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642660503 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.i2c_target_hrst.642660503
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.3792047857
Short name T308
Test name
Test status
Simulation time 2869428069 ps
CPU time 3.97 seconds
Started Apr 28 01:02:50 PM PDT 24
Finished Apr 28 01:02:55 PM PDT 24
Peak memory 207848 kb
Host smart-262fce1b-7097-4abf-9fc7-4fe1ae150c05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792047857 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.3792047857
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.127329298
Short name T415
Test name
Test status
Simulation time 18366256787 ps
CPU time 44.63 seconds
Started Apr 28 01:02:53 PM PDT 24
Finished Apr 28 01:03:38 PM PDT 24
Peak memory 1127404 kb
Host smart-4f97d300-df93-4701-a670-c7898fbd9128
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127329298 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.127329298
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.1651277592
Short name T744
Test name
Test status
Simulation time 975908078 ps
CPU time 35.44 seconds
Started Apr 28 01:02:41 PM PDT 24
Finished Apr 28 01:03:17 PM PDT 24
Peak memory 204160 kb
Host smart-d3eb1d73-e290-417a-b48b-b65ef9b97170
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651277592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.1651277592
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2833614703
Short name T451
Test name
Test status
Simulation time 277269779 ps
CPU time 11.43 seconds
Started Apr 28 01:02:52 PM PDT 24
Finished Apr 28 01:03:04 PM PDT 24
Peak memory 204156 kb
Host smart-b1225bc8-e79c-413f-9516-384898035db7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833614703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2833614703
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.1408833301
Short name T1010
Test name
Test status
Simulation time 44209919281 ps
CPU time 819.47 seconds
Started Apr 28 01:02:48 PM PDT 24
Finished Apr 28 01:16:28 PM PDT 24
Peak memory 6263164 kb
Host smart-d78181e6-0f3a-4daf-8368-39d2d9014e7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408833301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.1408833301
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.176826828
Short name T843
Test name
Test status
Simulation time 32069689500 ps
CPU time 583.47 seconds
Started Apr 28 01:02:50 PM PDT 24
Finished Apr 28 01:12:34 PM PDT 24
Peak memory 1716584 kb
Host smart-0d214342-b199-4bc9-af53-17d7bc6646c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176826828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_t
arget_stretch.176826828
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.1810333491
Short name T434
Test name
Test status
Simulation time 1796737653 ps
CPU time 5.81 seconds
Started Apr 28 01:02:49 PM PDT 24
Finished Apr 28 01:02:55 PM PDT 24
Peak memory 220240 kb
Host smart-cbbd421a-d151-43a2-aec0-7ea4eed69706
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810333491 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.1810333491
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.2998432970
Short name T442
Test name
Test status
Simulation time 19512793 ps
CPU time 0.65 seconds
Started Apr 28 01:03:02 PM PDT 24
Finished Apr 28 01:03:03 PM PDT 24
Peak memory 203788 kb
Host smart-bc59088d-73b6-4841-931b-bedb0b17f90d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998432970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.2998432970
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.4044283935
Short name T848
Test name
Test status
Simulation time 90667819 ps
CPU time 1.29 seconds
Started Apr 28 01:02:52 PM PDT 24
Finished Apr 28 01:02:54 PM PDT 24
Peak memory 212384 kb
Host smart-0483b091-2aff-4395-b330-87b5c9433fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044283935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.4044283935
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.1126672866
Short name T345
Test name
Test status
Simulation time 1998022746 ps
CPU time 22.11 seconds
Started Apr 28 01:02:59 PM PDT 24
Finished Apr 28 01:03:21 PM PDT 24
Peak memory 293544 kb
Host smart-7d88753e-ed10-4d55-bfc3-e8842ec07661
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126672866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.1126672866
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.2288298004
Short name T331
Test name
Test status
Simulation time 4214871662 ps
CPU time 81.01 seconds
Started Apr 28 01:02:54 PM PDT 24
Finished Apr 28 01:04:16 PM PDT 24
Peak memory 727980 kb
Host smart-e87ff637-4820-41d1-bdb5-c2a269e50a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288298004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2288298004
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.2325221123
Short name T979
Test name
Test status
Simulation time 3847302857 ps
CPU time 55.32 seconds
Started Apr 28 01:02:49 PM PDT 24
Finished Apr 28 01:03:45 PM PDT 24
Peak memory 620428 kb
Host smart-a5c95613-ef24-4125-b1b8-667e861ab710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325221123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.2325221123
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.401538676
Short name T545
Test name
Test status
Simulation time 533772480 ps
CPU time 1.04 seconds
Started Apr 28 01:02:53 PM PDT 24
Finished Apr 28 01:02:55 PM PDT 24
Peak memory 203952 kb
Host smart-deb09899-c8b1-4220-9d7a-ae7be4f45074
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401538676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fm
t.401538676
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.3608432363
Short name T791
Test name
Test status
Simulation time 431620066 ps
CPU time 10.39 seconds
Started Apr 28 01:02:54 PM PDT 24
Finished Apr 28 01:03:05 PM PDT 24
Peak memory 203992 kb
Host smart-c88807df-08e1-4380-aac5-71a0a6036664
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608432363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.3608432363
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.1890271630
Short name T944
Test name
Test status
Simulation time 2555215584 ps
CPU time 56.38 seconds
Started Apr 28 01:02:51 PM PDT 24
Finished Apr 28 01:03:49 PM PDT 24
Peak memory 836772 kb
Host smart-f385a08f-dc87-4223-9ec2-5328fd0eb103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890271630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1890271630
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.792244453
Short name T611
Test name
Test status
Simulation time 1589367932 ps
CPU time 6.05 seconds
Started Apr 28 01:03:06 PM PDT 24
Finished Apr 28 01:03:13 PM PDT 24
Peak memory 204240 kb
Host smart-3387d84b-3b74-4510-a14f-0c43c5890785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792244453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.792244453
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.1352150993
Short name T456
Test name
Test status
Simulation time 1009821424 ps
CPU time 15.56 seconds
Started Apr 28 01:02:52 PM PDT 24
Finished Apr 28 01:03:08 PM PDT 24
Peak memory 302272 kb
Host smart-a3bdc456-f25e-4909-a883-94a622127712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352150993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.1352150993
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.2360492591
Short name T213
Test name
Test status
Simulation time 19832637 ps
CPU time 0.66 seconds
Started Apr 28 01:02:53 PM PDT 24
Finished Apr 28 01:02:54 PM PDT 24
Peak memory 203824 kb
Host smart-5f4793c5-dbf1-4dfd-a5c3-3dff7ab4f85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360492591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.2360492591
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.701153713
Short name T567
Test name
Test status
Simulation time 30180837377 ps
CPU time 248.21 seconds
Started Apr 28 01:02:53 PM PDT 24
Finished Apr 28 01:07:02 PM PDT 24
Peak memory 340332 kb
Host smart-65568967-e59b-40c2-a4ae-297e46cd924b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701153713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.701153713
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.3413013463
Short name T1135
Test name
Test status
Simulation time 4960160867 ps
CPU time 59.69 seconds
Started Apr 28 01:02:51 PM PDT 24
Finished Apr 28 01:03:51 PM PDT 24
Peak memory 339036 kb
Host smart-344c2c7f-5b45-4af1-b359-391b80e6432b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413013463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.3413013463
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.2902251601
Short name T66
Test name
Test status
Simulation time 6363914416 ps
CPU time 537.9 seconds
Started Apr 28 01:02:56 PM PDT 24
Finished Apr 28 01:11:54 PM PDT 24
Peak memory 1117208 kb
Host smart-73ac8708-316b-46c1-a107-3a1227e42f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902251601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.2902251601
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.3634662504
Short name T252
Test name
Test status
Simulation time 1241366370 ps
CPU time 27.01 seconds
Started Apr 28 01:02:57 PM PDT 24
Finished Apr 28 01:03:24 PM PDT 24
Peak memory 212312 kb
Host smart-889863b0-f575-4e32-ac29-9679308b698e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634662504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3634662504
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.3366267721
Short name T246
Test name
Test status
Simulation time 3794630891 ps
CPU time 4.46 seconds
Started Apr 28 01:02:54 PM PDT 24
Finished Apr 28 01:02:59 PM PDT 24
Peak memory 212416 kb
Host smart-95d377a8-3098-4406-a3d0-ac2013186a04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366267721 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.3366267721
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.3542853178
Short name T419
Test name
Test status
Simulation time 10041937356 ps
CPU time 60.01 seconds
Started Apr 28 01:02:54 PM PDT 24
Finished Apr 28 01:03:55 PM PDT 24
Peak memory 416008 kb
Host smart-4ffd6094-2317-44be-9c35-6c147b6ba59f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542853178 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.3542853178
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.2063195959
Short name T49
Test name
Test status
Simulation time 10190656217 ps
CPU time 29.17 seconds
Started Apr 28 01:02:54 PM PDT 24
Finished Apr 28 01:03:23 PM PDT 24
Peak memory 366824 kb
Host smart-6adabb62-483b-4cf0-8682-790bdb58867b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063195959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.2063195959
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.4128605334
Short name T1051
Test name
Test status
Simulation time 397409864 ps
CPU time 2.73 seconds
Started Apr 28 01:02:54 PM PDT 24
Finished Apr 28 01:02:58 PM PDT 24
Peak memory 204188 kb
Host smart-f69a87ce-f424-4dfd-a521-c513feddb2c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128605334 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.4128605334
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.3153346623
Short name T410
Test name
Test status
Simulation time 2043600658 ps
CPU time 5.25 seconds
Started Apr 28 01:02:54 PM PDT 24
Finished Apr 28 01:03:00 PM PDT 24
Peak memory 218196 kb
Host smart-f0b205f4-26c8-4e81-9f4a-ec879045543d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153346623 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.3153346623
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.2961682334
Short name T1352
Test name
Test status
Simulation time 5290178107 ps
CPU time 11.71 seconds
Started Apr 28 01:02:53 PM PDT 24
Finished Apr 28 01:03:05 PM PDT 24
Peak memory 204196 kb
Host smart-c2778363-b9d9-4709-a2e0-f3f616128253
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961682334 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.2961682334
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.4212449488
Short name T821
Test name
Test status
Simulation time 1891383086 ps
CPU time 20.95 seconds
Started Apr 28 01:02:58 PM PDT 24
Finished Apr 28 01:03:20 PM PDT 24
Peak memory 204140 kb
Host smart-c5a9191e-d548-4f8e-8a92-0d57e9884956
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212449488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.4212449488
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.896013707
Short name T658
Test name
Test status
Simulation time 17756829953 ps
CPU time 22.35 seconds
Started Apr 28 01:02:56 PM PDT 24
Finished Apr 28 01:03:19 PM PDT 24
Peak memory 218196 kb
Host smart-8a9c79c9-8e0e-48f4-9cb2-83a47525cb9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896013707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_rd.896013707
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.4164370706
Short name T324
Test name
Test status
Simulation time 34258401416 ps
CPU time 56.35 seconds
Started Apr 28 01:02:53 PM PDT 24
Finished Apr 28 01:03:50 PM PDT 24
Peak memory 976368 kb
Host smart-8a8cc6e3-0e54-4b28-8581-c3f031be81d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164370706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.4164370706
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.3431398944
Short name T1182
Test name
Test status
Simulation time 25985050719 ps
CPU time 1588.41 seconds
Started Apr 28 01:02:57 PM PDT 24
Finished Apr 28 01:29:26 PM PDT 24
Peak memory 6383720 kb
Host smart-b11687c2-e2d3-4d45-9103-234e61e9763f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431398944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.3431398944
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.28928633
Short name T1091
Test name
Test status
Simulation time 1380266848 ps
CPU time 6.8 seconds
Started Apr 28 01:02:54 PM PDT 24
Finished Apr 28 01:03:02 PM PDT 24
Peak memory 212284 kb
Host smart-58e40e19-40d3-4af9-98a2-c88e3a6ef0ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28928633 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_timeout.28928633
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.2909592419
Short name T4
Test name
Test status
Simulation time 44650591 ps
CPU time 0.58 seconds
Started Apr 28 01:03:03 PM PDT 24
Finished Apr 28 01:03:05 PM PDT 24
Peak memory 203816 kb
Host smart-f4666186-2111-420a-b388-6290289b2683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909592419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.2909592419
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.1772410746
Short name T322
Test name
Test status
Simulation time 104729875 ps
CPU time 1.4 seconds
Started Apr 28 01:03:07 PM PDT 24
Finished Apr 28 01:03:10 PM PDT 24
Peak memory 212504 kb
Host smart-ad3ab8ed-c869-4e95-97fd-45648b90af6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772410746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.1772410746
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.2890453848
Short name T699
Test name
Test status
Simulation time 921913478 ps
CPU time 5.92 seconds
Started Apr 28 01:02:59 PM PDT 24
Finished Apr 28 01:03:05 PM PDT 24
Peak memory 266372 kb
Host smart-a66eeae8-07af-4fa7-beb9-59be06619166
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890453848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.2890453848
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.2759156963
Short name T1345
Test name
Test status
Simulation time 15576478841 ps
CPU time 135.28 seconds
Started Apr 28 01:03:00 PM PDT 24
Finished Apr 28 01:05:16 PM PDT 24
Peak memory 668672 kb
Host smart-d38f2da5-7e7a-43d6-b527-2b6029f37eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759156963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.2759156963
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.4048275677
Short name T42
Test name
Test status
Simulation time 6390013831 ps
CPU time 33.61 seconds
Started Apr 28 01:03:01 PM PDT 24
Finished Apr 28 01:03:35 PM PDT 24
Peak memory 520788 kb
Host smart-513874dc-864d-43f9-8553-f400db95bb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048275677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.4048275677
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.3222910633
Short name T122
Test name
Test status
Simulation time 123604869 ps
CPU time 0.96 seconds
Started Apr 28 01:03:07 PM PDT 24
Finished Apr 28 01:03:08 PM PDT 24
Peak memory 204008 kb
Host smart-ba045041-51c8-4007-b313-5b1dc2aa98dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222910633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.3222910633
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.1810474835
Short name T1223
Test name
Test status
Simulation time 206712971 ps
CPU time 2.57 seconds
Started Apr 28 01:03:02 PM PDT 24
Finished Apr 28 01:03:05 PM PDT 24
Peak memory 204120 kb
Host smart-e1f4f0e3-0dc9-47b7-8807-ce387723fb74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810474835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.1810474835
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.4119021093
Short name T189
Test name
Test status
Simulation time 2717973184 ps
CPU time 73.47 seconds
Started Apr 28 01:03:01 PM PDT 24
Finished Apr 28 01:04:15 PM PDT 24
Peak memory 850648 kb
Host smart-dc7f2b36-832f-457d-9fca-317eaf95ed41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119021093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.4119021093
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.3160503866
Short name T904
Test name
Test status
Simulation time 1087426329 ps
CPU time 4.78 seconds
Started Apr 28 01:03:11 PM PDT 24
Finished Apr 28 01:03:16 PM PDT 24
Peak memory 204204 kb
Host smart-cd9a1f58-cc57-44a1-bd9c-34210d36c4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160503866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.3160503866
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.3496013967
Short name T765
Test name
Test status
Simulation time 22724300218 ps
CPU time 18.37 seconds
Started Apr 28 01:03:08 PM PDT 24
Finished Apr 28 01:03:27 PM PDT 24
Peak memory 298412 kb
Host smart-7c986fd5-ec2f-4991-8815-e29f7f4b881e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496013967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.3496013967
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.2536430099
Short name T492
Test name
Test status
Simulation time 27745403 ps
CPU time 0.67 seconds
Started Apr 28 01:03:04 PM PDT 24
Finished Apr 28 01:03:05 PM PDT 24
Peak memory 203844 kb
Host smart-8ca51997-79e9-4707-a7bb-dabfc7fa9d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536430099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2536430099
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.2233676900
Short name T885
Test name
Test status
Simulation time 7791905779 ps
CPU time 187.96 seconds
Started Apr 28 01:02:59 PM PDT 24
Finished Apr 28 01:06:08 PM PDT 24
Peak memory 1028980 kb
Host smart-728da067-a25f-4849-a6ca-6b25c6be331a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233676900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2233676900
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.3928044387
Short name T424
Test name
Test status
Simulation time 3128649763 ps
CPU time 11.34 seconds
Started Apr 28 01:02:59 PM PDT 24
Finished Apr 28 01:03:10 PM PDT 24
Peak memory 248468 kb
Host smart-61576985-beac-48dd-bf77-6cb6fccaef2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928044387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.3928044387
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.2140331844
Short name T732
Test name
Test status
Simulation time 8718393627 ps
CPU time 6.71 seconds
Started Apr 28 01:03:01 PM PDT 24
Finished Apr 28 01:03:09 PM PDT 24
Peak memory 212416 kb
Host smart-b03a6091-a144-46d6-ab09-0f4ed5641276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140331844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.2140331844
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.2636654437
Short name T566
Test name
Test status
Simulation time 1889517233 ps
CPU time 4.81 seconds
Started Apr 28 01:03:03 PM PDT 24
Finished Apr 28 01:03:08 PM PDT 24
Peak memory 212384 kb
Host smart-0ab1ac73-4951-41d4-b818-cea3f6f36eb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636654437 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.2636654437
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1610945065
Short name T724
Test name
Test status
Simulation time 10092487745 ps
CPU time 24.37 seconds
Started Apr 28 01:03:03 PM PDT 24
Finished Apr 28 01:03:28 PM PDT 24
Peak memory 306184 kb
Host smart-8c3daff6-7657-4943-87c2-2ae5fbb8d858
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610945065 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1610945065
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.2193538127
Short name T760
Test name
Test status
Simulation time 10096063988 ps
CPU time 79.56 seconds
Started Apr 28 01:03:03 PM PDT 24
Finished Apr 28 01:04:23 PM PDT 24
Peak memory 531484 kb
Host smart-03f2ae26-1797-49dc-94d5-3d68e857a160
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193538127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.2193538127
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.2374404834
Short name T830
Test name
Test status
Simulation time 431610400 ps
CPU time 2.58 seconds
Started Apr 28 01:03:03 PM PDT 24
Finished Apr 28 01:03:06 PM PDT 24
Peak memory 204080 kb
Host smart-4db4946b-2e2a-4ee3-9666-a2417f9f4419
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374404834 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.2374404834
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.571333925
Short name T351
Test name
Test status
Simulation time 1119612589 ps
CPU time 5.34 seconds
Started Apr 28 01:03:00 PM PDT 24
Finished Apr 28 01:03:05 PM PDT 24
Peak memory 208884 kb
Host smart-89ba8216-8169-4c8f-81ae-f3a886ecdf27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571333925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_intr_smoke.571333925
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.2522858555
Short name T471
Test name
Test status
Simulation time 3538166703 ps
CPU time 13.35 seconds
Started Apr 28 01:03:02 PM PDT 24
Finished Apr 28 01:03:15 PM PDT 24
Peak memory 592856 kb
Host smart-068f5b92-9e52-428c-9ee3-1f5e74ef1148
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522858555 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.2522858555
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.1016130204
Short name T335
Test name
Test status
Simulation time 4709841753 ps
CPU time 17.41 seconds
Started Apr 28 01:03:04 PM PDT 24
Finished Apr 28 01:03:22 PM PDT 24
Peak memory 204228 kb
Host smart-0ca9ff10-d647-42d1-8b17-7895d46e5836
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016130204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.1016130204
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.655018201
Short name T752
Test name
Test status
Simulation time 3231410466 ps
CPU time 10.36 seconds
Started Apr 28 01:03:03 PM PDT 24
Finished Apr 28 01:03:14 PM PDT 24
Peak memory 214508 kb
Host smart-a8fffd4d-90a7-4f70-97dc-56d9c8e9f134
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655018201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_rd.655018201
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.3525731502
Short name T771
Test name
Test status
Simulation time 26443019875 ps
CPU time 110.86 seconds
Started Apr 28 01:03:00 PM PDT 24
Finished Apr 28 01:04:51 PM PDT 24
Peak memory 1637956 kb
Host smart-c8a1eeb0-9da2-468e-a5c8-a4d2bed6447d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525731502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.3525731502
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.3781239997
Short name T1306
Test name
Test status
Simulation time 15547140810 ps
CPU time 50.56 seconds
Started Apr 28 01:02:59 PM PDT 24
Finished Apr 28 01:03:51 PM PDT 24
Peak memory 634224 kb
Host smart-0b904b4a-aa3b-4d7b-9c6b-9b0c44ca7d88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781239997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.3781239997
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.2644680114
Short name T1162
Test name
Test status
Simulation time 1492110004 ps
CPU time 7.09 seconds
Started Apr 28 01:03:06 PM PDT 24
Finished Apr 28 01:03:14 PM PDT 24
Peak memory 212440 kb
Host smart-a7dc3709-c6d2-4399-b7fd-ad0055092672
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644680114 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.2644680114
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.3718512167
Short name T1063
Test name
Test status
Simulation time 42302531 ps
CPU time 0.64 seconds
Started Apr 28 01:03:13 PM PDT 24
Finished Apr 28 01:03:14 PM PDT 24
Peak memory 203888 kb
Host smart-bd2b1131-d9e8-4475-b045-ea841b343701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718512167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.3718512167
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.4047602605
Short name T1111
Test name
Test status
Simulation time 144646095 ps
CPU time 1.29 seconds
Started Apr 28 01:03:11 PM PDT 24
Finished Apr 28 01:03:13 PM PDT 24
Peak memory 212480 kb
Host smart-842e673e-b805-4ae2-bda8-4ad104ee1dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047602605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.4047602605
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.3922402738
Short name T805
Test name
Test status
Simulation time 586844812 ps
CPU time 5.38 seconds
Started Apr 28 01:03:07 PM PDT 24
Finished Apr 28 01:03:13 PM PDT 24
Peak memory 253648 kb
Host smart-549d0668-0430-4b8b-a9a4-7feae61101be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922402738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.3922402738
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.1944590823
Short name T552
Test name
Test status
Simulation time 9517697905 ps
CPU time 45.55 seconds
Started Apr 28 01:03:04 PM PDT 24
Finished Apr 28 01:03:50 PM PDT 24
Peak memory 266384 kb
Host smart-cbb97c23-1e72-4e94-a1ae-e9c841dab2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944590823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.1944590823
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.715111060
Short name T873
Test name
Test status
Simulation time 4505509374 ps
CPU time 73.19 seconds
Started Apr 28 01:03:06 PM PDT 24
Finished Apr 28 01:04:20 PM PDT 24
Peak memory 471508 kb
Host smart-b647d1db-0657-443b-9045-cf693af488a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715111060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.715111060
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.3241856030
Short name T559
Test name
Test status
Simulation time 482688766 ps
CPU time 1 seconds
Started Apr 28 01:03:03 PM PDT 24
Finished Apr 28 01:03:04 PM PDT 24
Peak memory 203940 kb
Host smart-da6ad54c-c45f-43d2-bd46-9f18fc165d49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241856030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.3241856030
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.3280326647
Short name T225
Test name
Test status
Simulation time 110585958 ps
CPU time 6.05 seconds
Started Apr 28 01:03:07 PM PDT 24
Finished Apr 28 01:03:14 PM PDT 24
Peak memory 219264 kb
Host smart-cdd5ae2c-7c91-457a-9b46-2b2b54d755e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280326647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.3280326647
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.2429318459
Short name T1199
Test name
Test status
Simulation time 7714131776 ps
CPU time 83.96 seconds
Started Apr 28 01:03:10 PM PDT 24
Finished Apr 28 01:04:35 PM PDT 24
Peak memory 1008948 kb
Host smart-8e304505-a057-423e-b342-5a8dac919c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429318459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.2429318459
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.2650997843
Short name T973
Test name
Test status
Simulation time 367773315 ps
CPU time 14.62 seconds
Started Apr 28 01:03:09 PM PDT 24
Finished Apr 28 01:03:24 PM PDT 24
Peak memory 204132 kb
Host smart-03331eee-aca3-4abe-8f97-ce2b16889b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650997843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.2650997843
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.2157801747
Short name T437
Test name
Test status
Simulation time 3272095962 ps
CPU time 81.88 seconds
Started Apr 28 01:03:10 PM PDT 24
Finished Apr 28 01:04:32 PM PDT 24
Peak memory 428520 kb
Host smart-5be020a1-4eaa-47f9-ae79-53c7bc09c4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157801747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.2157801747
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.2230438049
Short name T1286
Test name
Test status
Simulation time 18826369 ps
CPU time 0.64 seconds
Started Apr 28 01:03:07 PM PDT 24
Finished Apr 28 01:03:08 PM PDT 24
Peak memory 203876 kb
Host smart-f5ef3d1d-dec2-472d-bb7f-a3d98b54408b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230438049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.2230438049
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.2490511229
Short name T734
Test name
Test status
Simulation time 2977988486 ps
CPU time 42.92 seconds
Started Apr 28 01:03:04 PM PDT 24
Finished Apr 28 01:03:48 PM PDT 24
Peak memory 234660 kb
Host smart-5e538f7a-3f45-4858-84ca-75d4acbf5b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490511229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.2490511229
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.4024001945
Short name T1346
Test name
Test status
Simulation time 1202017892 ps
CPU time 22.77 seconds
Started Apr 28 01:03:11 PM PDT 24
Finished Apr 28 01:03:35 PM PDT 24
Peak memory 318160 kb
Host smart-6b7ff509-8a4c-40a1-b6c0-686e6c6c5b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024001945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.4024001945
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.3871483316
Short name T196
Test name
Test status
Simulation time 13458659789 ps
CPU time 69.46 seconds
Started Apr 28 01:03:11 PM PDT 24
Finished Apr 28 01:04:21 PM PDT 24
Peak memory 635960 kb
Host smart-659439f9-44e4-4a2b-9388-bc4a17a6211c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871483316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.3871483316
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.944941714
Short name T362
Test name
Test status
Simulation time 784511255 ps
CPU time 14.69 seconds
Started Apr 28 01:03:04 PM PDT 24
Finished Apr 28 01:03:19 PM PDT 24
Peak memory 215868 kb
Host smart-6a9c47a5-76bc-46e7-ae31-1a066712db0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944941714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.944941714
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.1913635059
Short name T472
Test name
Test status
Simulation time 3357317188 ps
CPU time 4.23 seconds
Started Apr 28 01:03:09 PM PDT 24
Finished Apr 28 01:03:14 PM PDT 24
Peak memory 212340 kb
Host smart-aa8ad36f-e7af-4cbe-a02e-1b6493da2a65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913635059 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.1913635059
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.353892262
Short name T1307
Test name
Test status
Simulation time 10085561250 ps
CPU time 62 seconds
Started Apr 28 01:03:10 PM PDT 24
Finished Apr 28 01:04:12 PM PDT 24
Peak memory 403972 kb
Host smart-b2b65c95-628b-497b-a130-52c2860087e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353892262 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_acq.353892262
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.2758589837
Short name T349
Test name
Test status
Simulation time 10220791822 ps
CPU time 32.01 seconds
Started Apr 28 01:03:10 PM PDT 24
Finished Apr 28 01:03:43 PM PDT 24
Peak memory 339404 kb
Host smart-abefe807-e04b-4a8b-aaf8-fdbe6def6859
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758589837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.2758589837
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.2431230685
Short name T1090
Test name
Test status
Simulation time 375520882 ps
CPU time 2.15 seconds
Started Apr 28 01:03:09 PM PDT 24
Finished Apr 28 01:03:12 PM PDT 24
Peak memory 204116 kb
Host smart-d32da0c7-7c54-4987-890a-6cadf9cc1431
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431230685 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.2431230685
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.696062706
Short name T1112
Test name
Test status
Simulation time 764769018 ps
CPU time 4.46 seconds
Started Apr 28 01:03:09 PM PDT 24
Finished Apr 28 01:03:14 PM PDT 24
Peak memory 213888 kb
Host smart-4aabec0c-538a-4a9b-a4be-eab7f39a5182
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696062706 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_intr_smoke.696062706
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.4283077566
Short name T291
Test name
Test status
Simulation time 7582459920 ps
CPU time 3.56 seconds
Started Apr 28 01:03:11 PM PDT 24
Finished Apr 28 01:03:15 PM PDT 24
Peak memory 204224 kb
Host smart-4a05e4a6-fb02-4ed7-9399-332aa46cd3c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283077566 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.4283077566
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.897054364
Short name T1079
Test name
Test status
Simulation time 1401947536 ps
CPU time 20.45 seconds
Started Apr 28 01:03:09 PM PDT 24
Finished Apr 28 01:03:29 PM PDT 24
Peak memory 204104 kb
Host smart-ca2b14c3-0eea-4508-8795-dc64ad3ac7d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897054364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_tar
get_smoke.897054364
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.811167945
Short name T512
Test name
Test status
Simulation time 3966855561 ps
CPU time 40.82 seconds
Started Apr 28 01:03:08 PM PDT 24
Finished Apr 28 01:03:49 PM PDT 24
Peak memory 204056 kb
Host smart-fcb0d81b-cc25-4220-9938-12024061e68f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811167945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_rd.811167945
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.2136512230
Short name T683
Test name
Test status
Simulation time 37193217233 ps
CPU time 100.26 seconds
Started Apr 28 01:03:08 PM PDT 24
Finished Apr 28 01:04:49 PM PDT 24
Peak memory 1613196 kb
Host smart-c52352e8-6c6a-4cf3-9156-0d29341f449f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136512230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.2136512230
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.1880485344
Short name T489
Test name
Test status
Simulation time 7920161508 ps
CPU time 27.45 seconds
Started Apr 28 01:03:10 PM PDT 24
Finished Apr 28 01:03:38 PM PDT 24
Peak memory 497552 kb
Host smart-21391a40-bb17-4327-abd1-dda93ba06341
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880485344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.1880485344
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.140206601
Short name T972
Test name
Test status
Simulation time 1569215255 ps
CPU time 6.92 seconds
Started Apr 28 01:03:10 PM PDT 24
Finished Apr 28 01:03:18 PM PDT 24
Peak memory 209100 kb
Host smart-e8f96206-ab38-47ff-860a-05e1f32acd38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140206601 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_timeout.140206601
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.1253591081
Short name T421
Test name
Test status
Simulation time 18337903 ps
CPU time 0.61 seconds
Started Apr 28 01:03:19 PM PDT 24
Finished Apr 28 01:03:20 PM PDT 24
Peak memory 203748 kb
Host smart-6f2c0544-9d48-484f-a12f-ae4b68519449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253591081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.1253591081
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.1188178398
Short name T1003
Test name
Test status
Simulation time 224885498 ps
CPU time 1.54 seconds
Started Apr 28 01:03:16 PM PDT 24
Finished Apr 28 01:03:18 PM PDT 24
Peak memory 204256 kb
Host smart-6bdc8452-3fc9-42e6-bc18-aa42f1d0751c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188178398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.1188178398
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.3500487685
Short name T715
Test name
Test status
Simulation time 1660952386 ps
CPU time 6.46 seconds
Started Apr 28 01:03:15 PM PDT 24
Finished Apr 28 01:03:22 PM PDT 24
Peak memory 240772 kb
Host smart-4baf9d6d-d71a-4e61-92f5-7e959525c54d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500487685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.3500487685
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2573534729
Short name T641
Test name
Test status
Simulation time 6314320960 ps
CPU time 112.1 seconds
Started Apr 28 01:03:19 PM PDT 24
Finished Apr 28 01:05:12 PM PDT 24
Peak memory 598604 kb
Host smart-2ee241d7-a775-40f4-bae2-e7a6a3f9f9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573534729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2573534729
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.3883304374
Short name T1191
Test name
Test status
Simulation time 3983670173 ps
CPU time 66.39 seconds
Started Apr 28 01:03:13 PM PDT 24
Finished Apr 28 01:04:20 PM PDT 24
Peak memory 659684 kb
Host smart-32941a01-ede6-4e74-a231-08ccc93faf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883304374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.3883304374
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.3189082
Short name T860
Test name
Test status
Simulation time 143050613 ps
CPU time 0.79 seconds
Started Apr 28 01:03:16 PM PDT 24
Finished Apr 28 01:03:18 PM PDT 24
Peak memory 203780 kb
Host smart-e0bb8d3d-56ae-438f-9f00-1ccb97e7ece2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fmt.3189082
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.1927909169
Short name T59
Test name
Test status
Simulation time 280141553 ps
CPU time 7.45 seconds
Started Apr 28 01:03:14 PM PDT 24
Finished Apr 28 01:03:22 PM PDT 24
Peak memory 204168 kb
Host smart-5a13471e-ce90-4c8f-85d7-077091fae733
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927909169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.1927909169
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.260904306
Short name T1344
Test name
Test status
Simulation time 2993964778 ps
CPU time 64.04 seconds
Started Apr 28 01:03:13 PM PDT 24
Finished Apr 28 01:04:17 PM PDT 24
Peak memory 885976 kb
Host smart-8a62008e-e073-42a4-9d9b-6de4acf105cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260904306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.260904306
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.1056064442
Short name T231
Test name
Test status
Simulation time 761158647 ps
CPU time 15.34 seconds
Started Apr 28 01:03:22 PM PDT 24
Finished Apr 28 01:03:38 PM PDT 24
Peak memory 204196 kb
Host smart-38846540-eac8-4a02-92e1-19d85355f2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056064442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.1056064442
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.898944905
Short name T1295
Test name
Test status
Simulation time 2560193527 ps
CPU time 17.15 seconds
Started Apr 28 01:03:18 PM PDT 24
Finished Apr 28 01:03:36 PM PDT 24
Peak memory 279348 kb
Host smart-0243b806-1cda-497a-8911-27cfde35d086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898944905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.898944905
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.4045119259
Short name T1145
Test name
Test status
Simulation time 27717872 ps
CPU time 0.67 seconds
Started Apr 28 01:03:09 PM PDT 24
Finished Apr 28 01:03:10 PM PDT 24
Peak memory 203736 kb
Host smart-c999465b-b19b-4856-a97c-33b5c888550c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045119259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.4045119259
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.690958531
Short name T360
Test name
Test status
Simulation time 2868604185 ps
CPU time 163.74 seconds
Started Apr 28 01:03:14 PM PDT 24
Finished Apr 28 01:05:58 PM PDT 24
Peak memory 628604 kb
Host smart-2f55c5d5-933e-44a7-a5e8-c6d67fa83562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690958531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.690958531
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.871400987
Short name T99
Test name
Test status
Simulation time 1249659695 ps
CPU time 21.69 seconds
Started Apr 28 01:03:09 PM PDT 24
Finished Apr 28 01:03:32 PM PDT 24
Peak memory 311316 kb
Host smart-03c3833e-d463-411b-a8a8-755fd23f3a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871400987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.871400987
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.586558311
Short name T248
Test name
Test status
Simulation time 15788626447 ps
CPU time 689.27 seconds
Started Apr 28 01:03:17 PM PDT 24
Finished Apr 28 01:14:47 PM PDT 24
Peak memory 1163580 kb
Host smart-cd06a4e2-d2fd-406b-b2af-a4cd8136f103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586558311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.586558311
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.1761718606
Short name T1009
Test name
Test status
Simulation time 1873615034 ps
CPU time 7.99 seconds
Started Apr 28 01:03:17 PM PDT 24
Finished Apr 28 01:03:25 PM PDT 24
Peak memory 220344 kb
Host smart-8b121366-fccf-45c1-86fa-27f19359aac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761718606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1761718606
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3313031664
Short name T408
Test name
Test status
Simulation time 3672376208 ps
CPU time 3.98 seconds
Started Apr 28 01:03:22 PM PDT 24
Finished Apr 28 01:03:26 PM PDT 24
Peak memory 212324 kb
Host smart-a4b567ae-ee2f-424a-81b1-f297465927f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313031664 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3313031664
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.1962968241
Short name T680
Test name
Test status
Simulation time 10167271007 ps
CPU time 30.04 seconds
Started Apr 28 01:03:20 PM PDT 24
Finished Apr 28 01:03:51 PM PDT 24
Peak memory 320800 kb
Host smart-d7884517-a032-48d9-9d0e-05844e19cdac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962968241 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.1962968241
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1061784616
Short name T568
Test name
Test status
Simulation time 10227333006 ps
CPU time 11.95 seconds
Started Apr 28 01:03:21 PM PDT 24
Finished Apr 28 01:03:34 PM PDT 24
Peak memory 280848 kb
Host smart-c3998ea6-8d48-4b99-8cbc-5b6e771cf893
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061784616 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1061784616
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.4055933641
Short name T9
Test name
Test status
Simulation time 495058303 ps
CPU time 2.98 seconds
Started Apr 28 01:03:18 PM PDT 24
Finished Apr 28 01:03:22 PM PDT 24
Peak memory 204076 kb
Host smart-29404492-d2eb-4168-9abe-941d20e7cc39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055933641 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.4055933641
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.804298800
Short name T1195
Test name
Test status
Simulation time 912484386 ps
CPU time 4.66 seconds
Started Apr 28 01:03:16 PM PDT 24
Finished Apr 28 01:03:21 PM PDT 24
Peak memory 204136 kb
Host smart-d08d6434-8536-4973-acda-f8afdfc3d6ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804298800 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_intr_smoke.804298800
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.3696658336
Short name T845
Test name
Test status
Simulation time 3761441342 ps
CPU time 8.06 seconds
Started Apr 28 01:03:14 PM PDT 24
Finished Apr 28 01:03:23 PM PDT 24
Peak memory 204208 kb
Host smart-c1823440-861c-4090-a6f4-3a4e1ef7a376
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696658336 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.3696658336
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.109288987
Short name T916
Test name
Test status
Simulation time 3322547320 ps
CPU time 30.02 seconds
Started Apr 28 01:03:14 PM PDT 24
Finished Apr 28 01:03:45 PM PDT 24
Peak memory 204112 kb
Host smart-b7ab0334-4e4b-4215-a629-57cb7663b1d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109288987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_tar
get_smoke.109288987
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.167718306
Short name T586
Test name
Test status
Simulation time 2105146730 ps
CPU time 19.84 seconds
Started Apr 28 01:03:13 PM PDT 24
Finished Apr 28 01:03:34 PM PDT 24
Peak memory 204132 kb
Host smart-58cd6736-66cd-4ec7-a129-f8528b7f5437
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167718306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_rd.167718306
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.1235518476
Short name T1138
Test name
Test status
Simulation time 33674571444 ps
CPU time 13.18 seconds
Started Apr 28 01:03:16 PM PDT 24
Finished Apr 28 01:03:30 PM PDT 24
Peak memory 369280 kb
Host smart-daf7a061-8376-4144-941b-ab00eba6e2c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235518476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.1235518476
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.2093992455
Short name T709
Test name
Test status
Simulation time 14078830540 ps
CPU time 122.69 seconds
Started Apr 28 01:03:15 PM PDT 24
Finished Apr 28 01:05:19 PM PDT 24
Peak memory 642040 kb
Host smart-818e9128-d483-4b1a-a0af-5171fff27de9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093992455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.2093992455
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.1972056925
Short name T1261
Test name
Test status
Simulation time 1239658018 ps
CPU time 5.79 seconds
Started Apr 28 01:03:13 PM PDT 24
Finished Apr 28 01:03:19 PM PDT 24
Peak memory 212404 kb
Host smart-816cc991-db79-4307-997b-63ce5e603ee4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972056925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.1972056925
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.1082420453
Short name T297
Test name
Test status
Simulation time 15817173 ps
CPU time 0.63 seconds
Started Apr 28 01:03:25 PM PDT 24
Finished Apr 28 01:03:26 PM PDT 24
Peak memory 203884 kb
Host smart-5680674c-240a-405e-a8eb-04cbcba58af9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082420453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1082420453
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.1221024672
Short name T1151
Test name
Test status
Simulation time 153102930 ps
CPU time 1.48 seconds
Started Apr 28 01:03:20 PM PDT 24
Finished Apr 28 01:03:22 PM PDT 24
Peak memory 212384 kb
Host smart-b0a49793-287c-435a-8e6b-d006d16a8953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221024672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.1221024672
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.78975608
Short name T1058
Test name
Test status
Simulation time 454537257 ps
CPU time 3.8 seconds
Started Apr 28 01:03:19 PM PDT 24
Finished Apr 28 01:03:23 PM PDT 24
Peak memory 232024 kb
Host smart-36ac54f4-56e3-4762-8883-a298b13a3717
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78975608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empty
.78975608
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.3025517889
Short name T707
Test name
Test status
Simulation time 2192012705 ps
CPU time 41.16 seconds
Started Apr 28 01:03:19 PM PDT 24
Finished Apr 28 01:04:01 PM PDT 24
Peak memory 465904 kb
Host smart-8953d45e-9d59-4751-8e2f-93bd5e191989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025517889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3025517889
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.3585513025
Short name T783
Test name
Test status
Simulation time 2087909127 ps
CPU time 154.92 seconds
Started Apr 28 01:03:19 PM PDT 24
Finished Apr 28 01:05:55 PM PDT 24
Peak memory 720204 kb
Host smart-db956f9a-667a-4a32-b62e-72a7eda07689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585513025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.3585513025
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.1725217367
Short name T700
Test name
Test status
Simulation time 925167443 ps
CPU time 1.04 seconds
Started Apr 28 01:03:21 PM PDT 24
Finished Apr 28 01:03:22 PM PDT 24
Peak memory 203976 kb
Host smart-80cdbdbd-5f65-4031-b7e9-7a03b342637e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725217367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.1725217367
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.523355754
Short name T992
Test name
Test status
Simulation time 2022140912 ps
CPU time 3.02 seconds
Started Apr 28 01:03:20 PM PDT 24
Finished Apr 28 01:03:24 PM PDT 24
Peak memory 204168 kb
Host smart-486c6c4d-aeb7-4560-aab2-3f071406576b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523355754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.
523355754
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.4683665
Short name T837
Test name
Test status
Simulation time 9678716666 ps
CPU time 47.96 seconds
Started Apr 28 01:03:22 PM PDT 24
Finished Apr 28 01:04:11 PM PDT 24
Peak memory 756108 kb
Host smart-f91c3371-0588-42d4-b8db-359fb8974e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4683665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.4683665
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.3389954766
Short name T1101
Test name
Test status
Simulation time 4315636157 ps
CPU time 3.67 seconds
Started Apr 28 01:03:27 PM PDT 24
Finished Apr 28 01:03:31 PM PDT 24
Peak memory 204096 kb
Host smart-b77353e7-47b6-4a1c-a608-2c17b0055881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389954766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.3389954766
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.189132455
Short name T625
Test name
Test status
Simulation time 1700064403 ps
CPU time 81.9 seconds
Started Apr 28 01:03:26 PM PDT 24
Finished Apr 28 01:04:49 PM PDT 24
Peak memory 350260 kb
Host smart-c1c6e07a-e1f8-4fba-95e0-855a2a6267ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189132455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.189132455
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_perf.2728414569
Short name T620
Test name
Test status
Simulation time 2935183052 ps
CPU time 32.22 seconds
Started Apr 28 01:03:20 PM PDT 24
Finished Apr 28 01:03:53 PM PDT 24
Peak memory 212444 kb
Host smart-7b499dea-d3d0-4305-8329-b6987412cf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728414569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.2728414569
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.4211864227
Short name T355
Test name
Test status
Simulation time 759766386 ps
CPU time 34.61 seconds
Started Apr 28 01:03:18 PM PDT 24
Finished Apr 28 01:03:53 PM PDT 24
Peak memory 268880 kb
Host smart-5c67a182-df0a-4e40-98c9-2c59ee437698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211864227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.4211864227
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.1182170518
Short name T183
Test name
Test status
Simulation time 15686702903 ps
CPU time 471.43 seconds
Started Apr 28 01:03:21 PM PDT 24
Finished Apr 28 01:11:13 PM PDT 24
Peak memory 2247304 kb
Host smart-947a89da-ae30-4524-bb74-d8a033af3a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182170518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.1182170518
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.2552130502
Short name T583
Test name
Test status
Simulation time 2594157154 ps
CPU time 31.03 seconds
Started Apr 28 01:03:21 PM PDT 24
Finished Apr 28 01:03:52 PM PDT 24
Peak memory 213348 kb
Host smart-82cedf21-8367-4aba-8f76-23efef500c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552130502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.2552130502
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.633677444
Short name T1350
Test name
Test status
Simulation time 686222513 ps
CPU time 3.67 seconds
Started Apr 28 01:03:26 PM PDT 24
Finished Apr 28 01:03:30 PM PDT 24
Peak memory 204040 kb
Host smart-50058d3b-8142-4ef1-b354-5595de8f8d46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633677444 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.633677444
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1250708295
Short name T1102
Test name
Test status
Simulation time 10068566122 ps
CPU time 64.49 seconds
Started Apr 28 01:03:23 PM PDT 24
Finished Apr 28 01:04:28 PM PDT 24
Peak memory 504828 kb
Host smart-6ebe2098-64a7-44ea-80ba-4833bcdc200c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250708295 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1250708295
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.3299793468
Short name T1200
Test name
Test status
Simulation time 10040366922 ps
CPU time 84.95 seconds
Started Apr 28 01:03:24 PM PDT 24
Finished Apr 28 01:04:49 PM PDT 24
Peak memory 503360 kb
Host smart-963c6be2-dc29-400a-9db7-dc12822d8f1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299793468 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.3299793468
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.3851638580
Short name T874
Test name
Test status
Simulation time 427059474 ps
CPU time 2.59 seconds
Started Apr 28 01:03:25 PM PDT 24
Finished Apr 28 01:03:28 PM PDT 24
Peak memory 204180 kb
Host smart-c0f8b3fd-1a33-4d44-ad46-a9929eb16e82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851638580 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.3851638580
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1174770291
Short name T977
Test name
Test status
Simulation time 1139021131 ps
CPU time 5.31 seconds
Started Apr 28 01:03:22 PM PDT 24
Finished Apr 28 01:03:28 PM PDT 24
Peak memory 204080 kb
Host smart-ed3b6c01-17dd-4f9d-b02f-00186c988f37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174770291 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1174770291
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.4079735565
Short name T495
Test name
Test status
Simulation time 12515148665 ps
CPU time 71.2 seconds
Started Apr 28 01:03:26 PM PDT 24
Finished Apr 28 01:04:37 PM PDT 24
Peak memory 1526232 kb
Host smart-b96736cf-d499-4d07-bdf4-5b73f13e40f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079735565 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.4079735565
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.2908603884
Short name T808
Test name
Test status
Simulation time 4933238870 ps
CPU time 13.1 seconds
Started Apr 28 01:03:21 PM PDT 24
Finished Apr 28 01:03:35 PM PDT 24
Peak memory 204232 kb
Host smart-616f9c99-301b-4ca4-974e-de3b369ecdf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908603884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.2908603884
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.3147332970
Short name T754
Test name
Test status
Simulation time 355369872 ps
CPU time 6.7 seconds
Started Apr 28 01:03:20 PM PDT 24
Finished Apr 28 01:03:27 PM PDT 24
Peak memory 204140 kb
Host smart-815202d7-0c19-41dc-8808-a5d94b9cbdce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147332970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.3147332970
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.891120128
Short name T959
Test name
Test status
Simulation time 7384418902 ps
CPU time 4.49 seconds
Started Apr 28 01:03:20 PM PDT 24
Finished Apr 28 01:03:25 PM PDT 24
Peak memory 204040 kb
Host smart-0ecde548-abe3-4e75-8d3c-3d6037ab02cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891120128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_wr.891120128
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.1503595436
Short name T847
Test name
Test status
Simulation time 16902092314 ps
CPU time 131.41 seconds
Started Apr 28 01:03:24 PM PDT 24
Finished Apr 28 01:05:37 PM PDT 24
Peak memory 664484 kb
Host smart-d08c8bff-adc8-4f8f-ad24-b40f1adf8243
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503595436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.1503595436
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.765497494
Short name T708
Test name
Test status
Simulation time 8272401422 ps
CPU time 6.61 seconds
Started Apr 28 01:03:24 PM PDT 24
Finished Apr 28 01:03:31 PM PDT 24
Peak memory 212292 kb
Host smart-c3ef3ed5-e6e4-44f4-b146-ce6855e725d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765497494 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_timeout.765497494
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.207671421
Short name T687
Test name
Test status
Simulation time 20297726 ps
CPU time 0.6 seconds
Started Apr 28 01:03:30 PM PDT 24
Finished Apr 28 01:03:31 PM PDT 24
Peak memory 203728 kb
Host smart-bb041c90-94a3-4d4a-a800-a72415bcb9e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207671421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.207671421
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.1479499670
Short name T855
Test name
Test status
Simulation time 79033582 ps
CPU time 1.33 seconds
Started Apr 28 01:03:30 PM PDT 24
Finished Apr 28 01:03:32 PM PDT 24
Peak memory 212464 kb
Host smart-f9f38ab7-6675-45b7-94e6-88da8a8b4e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479499670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.1479499670
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.3761505179
Short name T631
Test name
Test status
Simulation time 368275085 ps
CPU time 7.94 seconds
Started Apr 28 01:03:24 PM PDT 24
Finished Apr 28 01:03:33 PM PDT 24
Peak memory 279600 kb
Host smart-200cb51f-2f4f-42f1-9244-ee37388d02a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761505179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.3761505179
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.827878718
Short name T389
Test name
Test status
Simulation time 1947741441 ps
CPU time 132.67 seconds
Started Apr 28 01:03:25 PM PDT 24
Finished Apr 28 01:05:38 PM PDT 24
Peak memory 668852 kb
Host smart-1e07bae9-875f-4ec9-a8b2-fab167000096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827878718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.827878718
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.2092586550
Short name T476
Test name
Test status
Simulation time 3614210006 ps
CPU time 129.65 seconds
Started Apr 28 01:03:33 PM PDT 24
Finished Apr 28 01:05:43 PM PDT 24
Peak memory 643400 kb
Host smart-e36adb8f-b4d5-4b66-bdb4-2e44eebb8737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092586550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2092586550
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.2120819678
Short name T400
Test name
Test status
Simulation time 194131454 ps
CPU time 0.89 seconds
Started Apr 28 01:03:24 PM PDT 24
Finished Apr 28 01:03:26 PM PDT 24
Peak memory 203852 kb
Host smart-41681f3c-27c5-423a-9288-4f9c48dcaa17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120819678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.2120819678
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.3731405169
Short name T937
Test name
Test status
Simulation time 491437743 ps
CPU time 3.18 seconds
Started Apr 28 01:03:24 PM PDT 24
Finished Apr 28 01:03:28 PM PDT 24
Peak memory 223944 kb
Host smart-e4607ae7-9c6f-484a-b86b-fdc5b6242f08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731405169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.3731405169
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.2191740978
Short name T1097
Test name
Test status
Simulation time 16295440923 ps
CPU time 301.75 seconds
Started Apr 28 01:03:24 PM PDT 24
Finished Apr 28 01:08:27 PM PDT 24
Peak memory 1134988 kb
Host smart-23789322-dbce-43da-881e-a2ab03750416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191740978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.2191740978
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.2453297263
Short name T1359
Test name
Test status
Simulation time 839460405 ps
CPU time 2.94 seconds
Started Apr 28 01:03:31 PM PDT 24
Finished Apr 28 01:03:35 PM PDT 24
Peak memory 204148 kb
Host smart-3d0cd797-77fd-4d09-8627-957d34ff04f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453297263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.2453297263
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.3167935198
Short name T323
Test name
Test status
Simulation time 1622519080 ps
CPU time 73.31 seconds
Started Apr 28 01:03:30 PM PDT 24
Finished Apr 28 01:04:44 PM PDT 24
Peak memory 301192 kb
Host smart-4c3f4a67-a4ec-461d-abc3-74b059a38cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167935198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.3167935198
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.2813378428
Short name T1276
Test name
Test status
Simulation time 16569520 ps
CPU time 0.64 seconds
Started Apr 28 01:03:25 PM PDT 24
Finished Apr 28 01:03:26 PM PDT 24
Peak memory 203860 kb
Host smart-715e984a-210c-475c-89ac-5a80d1e1a536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813378428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.2813378428
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.2881856253
Short name T77
Test name
Test status
Simulation time 53818145778 ps
CPU time 128.7 seconds
Started Apr 28 01:03:23 PM PDT 24
Finished Apr 28 01:05:32 PM PDT 24
Peak memory 430316 kb
Host smart-d98005e2-b349-481a-8eb3-274478b4344b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881856253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.2881856253
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.479519492
Short name T829
Test name
Test status
Simulation time 5364640530 ps
CPU time 19.6 seconds
Started Apr 28 01:03:26 PM PDT 24
Finished Apr 28 01:03:46 PM PDT 24
Peak memory 295560 kb
Host smart-3e50347c-1ba9-4894-9b8c-2eede6bc434d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479519492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.479519492
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.2016005045
Short name T150
Test name
Test status
Simulation time 17459667953 ps
CPU time 153.27 seconds
Started Apr 28 01:03:32 PM PDT 24
Finished Apr 28 01:06:06 PM PDT 24
Peak memory 860248 kb
Host smart-b9bc27e7-02ba-435a-890b-7332e9ef1de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016005045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.2016005045
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.1277780787
Short name T564
Test name
Test status
Simulation time 816475358 ps
CPU time 7.63 seconds
Started Apr 28 01:03:32 PM PDT 24
Finished Apr 28 01:03:40 PM PDT 24
Peak memory 212352 kb
Host smart-cd7f2d27-54d8-4ad2-a15a-e8daa5f9cdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277780787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.1277780787
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.3400740814
Short name T1281
Test name
Test status
Simulation time 1327337465 ps
CPU time 3.69 seconds
Started Apr 28 01:03:34 PM PDT 24
Finished Apr 28 01:03:39 PM PDT 24
Peak memory 204136 kb
Host smart-20a91a30-b4e1-4216-8a48-b35fe065b68c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400740814 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.3400740814
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.2675674012
Short name T857
Test name
Test status
Simulation time 10120645461 ps
CPU time 67.9 seconds
Started Apr 28 01:03:34 PM PDT 24
Finished Apr 28 01:04:43 PM PDT 24
Peak memory 485412 kb
Host smart-eeb25750-c4e6-4b0c-a9d3-0fc541569215
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675674012 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.2675674012
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.262429489
Short name T1124
Test name
Test status
Simulation time 10079848905 ps
CPU time 29.83 seconds
Started Apr 28 01:03:32 PM PDT 24
Finished Apr 28 01:04:02 PM PDT 24
Peak memory 366312 kb
Host smart-90e69261-51e9-4013-aeb8-515489110b58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262429489 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_tx.262429489
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.792294955
Short name T468
Test name
Test status
Simulation time 421776157 ps
CPU time 2.34 seconds
Started Apr 28 01:03:30 PM PDT 24
Finished Apr 28 01:03:33 PM PDT 24
Peak memory 204040 kb
Host smart-42153c55-6ec1-4dce-95ee-583d88e8a993
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792294955 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.i2c_target_hrst.792294955
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.2195386116
Short name T823
Test name
Test status
Simulation time 2121731440 ps
CPU time 5.31 seconds
Started Apr 28 01:03:33 PM PDT 24
Finished Apr 28 01:03:39 PM PDT 24
Peak memory 204148 kb
Host smart-ef33fdeb-4e8a-4197-8b38-b45702931185
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195386116 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.2195386116
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.2256006912
Short name T713
Test name
Test status
Simulation time 7705881060 ps
CPU time 16.18 seconds
Started Apr 28 01:03:30 PM PDT 24
Finished Apr 28 01:03:47 PM PDT 24
Peak memory 298084 kb
Host smart-5bdfcb5c-0588-495e-ac15-3438ffc7c4d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256006912 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.2256006912
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.660928995
Short name T484
Test name
Test status
Simulation time 801863017 ps
CPU time 9.44 seconds
Started Apr 28 01:03:32 PM PDT 24
Finished Apr 28 01:03:42 PM PDT 24
Peak memory 204156 kb
Host smart-1f798529-3232-47b2-8de6-1de888272787
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660928995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_tar
get_smoke.660928995
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.395563329
Short name T8
Test name
Test status
Simulation time 7345775462 ps
CPU time 75.25 seconds
Started Apr 28 01:03:32 PM PDT 24
Finished Apr 28 01:04:48 PM PDT 24
Peak memory 207472 kb
Host smart-2a1b6c51-735e-40cb-9b3c-ca7f6dbdfa7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395563329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_rd.395563329
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.1134474054
Short name T733
Test name
Test status
Simulation time 30905454982 ps
CPU time 233.17 seconds
Started Apr 28 01:03:31 PM PDT 24
Finished Apr 28 01:07:25 PM PDT 24
Peak memory 2781960 kb
Host smart-f79dd354-d5f4-4153-a3f0-778771f13205
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134474054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.1134474054
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.4192245966
Short name T844
Test name
Test status
Simulation time 1376893707 ps
CPU time 6.82 seconds
Started Apr 28 01:03:30 PM PDT 24
Finished Apr 28 01:03:37 PM PDT 24
Peak memory 219364 kb
Host smart-7dd7cdb2-7ff3-4dd5-8a41-1431b6b3386c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192245966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.4192245966
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.479347881
Short name T111
Test name
Test status
Simulation time 34750161 ps
CPU time 0.59 seconds
Started Apr 28 01:03:42 PM PDT 24
Finished Apr 28 01:03:43 PM PDT 24
Peak memory 203856 kb
Host smart-76d3758b-8538-4c74-833a-3759d876d15c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479347881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.479347881
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.2364384241
Short name T872
Test name
Test status
Simulation time 394338088 ps
CPU time 1.46 seconds
Started Apr 28 01:03:35 PM PDT 24
Finished Apr 28 01:03:37 PM PDT 24
Peak memory 212452 kb
Host smart-3230a656-57c3-4b85-a653-1c58fe4a5f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364384241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.2364384241
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.3521831540
Short name T650
Test name
Test status
Simulation time 346670886 ps
CPU time 17.93 seconds
Started Apr 28 01:03:35 PM PDT 24
Finished Apr 28 01:03:54 PM PDT 24
Peak memory 276260 kb
Host smart-7c074d33-c46d-44d1-8588-d263c4c8f198
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521831540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.3521831540
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1058824078
Short name T551
Test name
Test status
Simulation time 4533505073 ps
CPU time 65.36 seconds
Started Apr 28 01:03:35 PM PDT 24
Finished Apr 28 01:04:41 PM PDT 24
Peak memory 398400 kb
Host smart-897513e4-f011-446b-860e-1720d2a32f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058824078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1058824078
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.2483673896
Short name T966
Test name
Test status
Simulation time 1734932582 ps
CPU time 112.86 seconds
Started Apr 28 01:03:35 PM PDT 24
Finished Apr 28 01:05:29 PM PDT 24
Peak memory 551664 kb
Host smart-9765b45f-a62a-432f-af84-5b44685d385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483673896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.2483673896
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1061262462
Short name T762
Test name
Test status
Simulation time 128253618 ps
CPU time 0.79 seconds
Started Apr 28 01:03:36 PM PDT 24
Finished Apr 28 01:03:38 PM PDT 24
Peak memory 203908 kb
Host smart-1848292f-d1d5-4d7a-8d3b-f8afb70999fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061262462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.1061262462
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.4152266219
Short name T938
Test name
Test status
Simulation time 332888163 ps
CPU time 8.97 seconds
Started Apr 28 01:03:35 PM PDT 24
Finished Apr 28 01:03:45 PM PDT 24
Peak memory 233304 kb
Host smart-89979df6-6fc7-4e45-8c41-b1009c7450d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152266219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.4152266219
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.1417115724
Short name T838
Test name
Test status
Simulation time 15698413349 ps
CPU time 111.26 seconds
Started Apr 28 01:03:37 PM PDT 24
Finished Apr 28 01:05:29 PM PDT 24
Peak memory 1140592 kb
Host smart-e9fa452f-4fb8-4b1b-be1a-e3246e207ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417115724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1417115724
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.769021165
Short name T720
Test name
Test status
Simulation time 400899847 ps
CPU time 4.83 seconds
Started Apr 28 01:03:40 PM PDT 24
Finished Apr 28 01:03:47 PM PDT 24
Peak memory 204032 kb
Host smart-3610c499-cd43-4e5b-92f0-468ee235aac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769021165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.769021165
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.2817313680
Short name T67
Test name
Test status
Simulation time 1271188915 ps
CPU time 60.32 seconds
Started Apr 28 01:03:40 PM PDT 24
Finished Apr 28 01:04:41 PM PDT 24
Peak memory 309836 kb
Host smart-ab8207c8-9ca6-4ee5-97ae-2363ed0c5e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817313680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.2817313680
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.2933324736
Short name T285
Test name
Test status
Simulation time 27216558 ps
CPU time 0.63 seconds
Started Apr 28 01:03:35 PM PDT 24
Finished Apr 28 01:03:36 PM PDT 24
Peak memory 203872 kb
Host smart-9da63c0c-de6c-439b-b6cd-5476aad7a656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933324736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2933324736
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.2578113371
Short name T1236
Test name
Test status
Simulation time 5128251170 ps
CPU time 137.38 seconds
Started Apr 28 01:03:37 PM PDT 24
Finished Apr 28 01:05:55 PM PDT 24
Peak memory 252436 kb
Host smart-3267bfe2-feae-4691-bb24-be429ac8c309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578113371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2578113371
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.3749366856
Short name T455
Test name
Test status
Simulation time 1250899594 ps
CPU time 57.77 seconds
Started Apr 28 01:03:35 PM PDT 24
Finished Apr 28 01:04:34 PM PDT 24
Peak memory 311268 kb
Host smart-794216e4-54ef-49f7-b570-9740c6e007c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749366856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3749366856
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.2318588737
Short name T1159
Test name
Test status
Simulation time 47473857872 ps
CPU time 731.26 seconds
Started Apr 28 01:03:34 PM PDT 24
Finished Apr 28 01:15:46 PM PDT 24
Peak memory 2375008 kb
Host smart-4bbf88c0-ac8e-4cad-9a02-ec82a8225413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318588737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.2318588737
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.2967526357
Short name T40
Test name
Test status
Simulation time 696945759 ps
CPU time 10.9 seconds
Started Apr 28 01:03:34 PM PDT 24
Finished Apr 28 01:03:46 PM PDT 24
Peak memory 228676 kb
Host smart-75100a67-bfe0-44c6-88b8-bbb272ae3914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967526357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.2967526357
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.815818717
Short name T1033
Test name
Test status
Simulation time 716791417 ps
CPU time 3.16 seconds
Started Apr 28 01:03:42 PM PDT 24
Finished Apr 28 01:03:46 PM PDT 24
Peak memory 204140 kb
Host smart-c6f16f3c-638d-4f64-ac84-34efb4564ba5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815818717 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.815818717
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.3182994841
Short name T608
Test name
Test status
Simulation time 10309390285 ps
CPU time 12.03 seconds
Started Apr 28 01:03:39 PM PDT 24
Finished Apr 28 01:03:53 PM PDT 24
Peak memory 265664 kb
Host smart-ea03decb-d495-412d-83aa-58fbba49f08f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182994841 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.3182994841
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.2272912100
Short name T1157
Test name
Test status
Simulation time 10327270373 ps
CPU time 8.08 seconds
Started Apr 28 01:03:39 PM PDT 24
Finished Apr 28 01:03:48 PM PDT 24
Peak memory 248184 kb
Host smart-71d2267d-76e1-424c-a15e-c879b29636e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272912100 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.2272912100
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.48542915
Short name T16
Test name
Test status
Simulation time 364123699 ps
CPU time 2.3 seconds
Started Apr 28 01:03:40 PM PDT 24
Finished Apr 28 01:03:44 PM PDT 24
Peak memory 204180 kb
Host smart-dea5f01b-9499-4484-ab45-989c57b4c7a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48542915 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.i2c_target_hrst.48542915
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.1537516252
Short name T984
Test name
Test status
Simulation time 18957831945 ps
CPU time 6.15 seconds
Started Apr 28 01:03:38 PM PDT 24
Finished Apr 28 01:03:44 PM PDT 24
Peak memory 212400 kb
Host smart-88301b21-a2b5-4c5a-997b-f847c27a5a3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537516252 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.1537516252
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.800487549
Short name T697
Test name
Test status
Simulation time 11153319950 ps
CPU time 10.3 seconds
Started Apr 28 01:03:41 PM PDT 24
Finished Apr 28 01:03:53 PM PDT 24
Peak memory 309492 kb
Host smart-e28951f8-f1b3-4bd9-8eae-e0a156a119d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800487549 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.800487549
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.332235149
Short name T43
Test name
Test status
Simulation time 3578254136 ps
CPU time 14.39 seconds
Started Apr 28 01:03:35 PM PDT 24
Finished Apr 28 01:03:50 PM PDT 24
Peak memory 204192 kb
Host smart-d8e7a590-9182-406d-916c-18cd3bf2f349
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332235149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_tar
get_smoke.332235149
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.2186596168
Short name T609
Test name
Test status
Simulation time 18333238765 ps
CPU time 19.65 seconds
Started Apr 28 01:03:37 PM PDT 24
Finished Apr 28 01:03:58 PM PDT 24
Peak memory 234160 kb
Host smart-7111287e-0a43-41a9-b9f8-f2740e11236c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186596168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.2186596168
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.3240622467
Short name T592
Test name
Test status
Simulation time 22483014717 ps
CPU time 9.74 seconds
Started Apr 28 01:03:35 PM PDT 24
Finished Apr 28 01:03:45 PM PDT 24
Peak memory 204120 kb
Host smart-144dc013-1194-4dd5-a7d8-c1fbaeb7f2a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240622467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.3240622467
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.2106862690
Short name T396
Test name
Test status
Simulation time 31596830941 ps
CPU time 252.11 seconds
Started Apr 28 01:03:35 PM PDT 24
Finished Apr 28 01:07:48 PM PDT 24
Peak memory 2077324 kb
Host smart-86c4f215-979e-48c4-b558-8a8394f22cd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106862690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.2106862690
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1173731536
Short name T1337
Test name
Test status
Simulation time 1295018310 ps
CPU time 5.78 seconds
Started Apr 28 01:03:41 PM PDT 24
Finished Apr 28 01:03:48 PM PDT 24
Peak memory 204072 kb
Host smart-7d9abfaa-8804-4fbe-a0ba-22359d5410d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173731536 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1173731536
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.1070197987
Short name T407
Test name
Test status
Simulation time 19264394 ps
CPU time 0.62 seconds
Started Apr 28 01:03:51 PM PDT 24
Finished Apr 28 01:03:53 PM PDT 24
Peak memory 203816 kb
Host smart-ad21ba05-4ea5-4f79-9c08-0a5755ac7407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070197987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.1070197987
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.2056883245
Short name T475
Test name
Test status
Simulation time 1333576573 ps
CPU time 1.39 seconds
Started Apr 28 01:03:45 PM PDT 24
Finished Apr 28 01:03:47 PM PDT 24
Peak memory 212276 kb
Host smart-879de22e-fd6c-4baa-bf98-40adc4a4bbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056883245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.2056883245
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3012660907
Short name T980
Test name
Test status
Simulation time 868054962 ps
CPU time 5.91 seconds
Started Apr 28 01:03:40 PM PDT 24
Finished Apr 28 01:03:48 PM PDT 24
Peak memory 254188 kb
Host smart-eca32f90-0414-43ad-b797-5208ca26f240
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012660907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3012660907
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.2725800061
Short name T824
Test name
Test status
Simulation time 1956199290 ps
CPU time 49.51 seconds
Started Apr 28 01:03:43 PM PDT 24
Finished Apr 28 01:04:33 PM PDT 24
Peak memory 559664 kb
Host smart-6aece965-5c4d-46d5-8932-c39d8709ecd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725800061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.2725800061
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.3682989075
Short name T91
Test name
Test status
Simulation time 3811631161 ps
CPU time 137.59 seconds
Started Apr 28 01:03:42 PM PDT 24
Finished Apr 28 01:06:01 PM PDT 24
Peak memory 660728 kb
Host smart-abc37358-98c6-459d-84ee-1d99a56f1c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682989075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3682989075
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.399523874
Short name T443
Test name
Test status
Simulation time 342448423 ps
CPU time 0.86 seconds
Started Apr 28 01:03:39 PM PDT 24
Finished Apr 28 01:03:41 PM PDT 24
Peak memory 203956 kb
Host smart-0022790a-eac8-4c53-b104-5113a2a3f9ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399523874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fm
t.399523874
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.925692795
Short name T224
Test name
Test status
Simulation time 239101869 ps
CPU time 2.93 seconds
Started Apr 28 01:03:39 PM PDT 24
Finished Apr 28 01:03:43 PM PDT 24
Peak memory 221392 kb
Host smart-b4465938-3689-463e-a9ea-f5ff86effae9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925692795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.
925692795
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.3838323030
Short name T499
Test name
Test status
Simulation time 9662577233 ps
CPU time 56.1 seconds
Started Apr 28 01:03:40 PM PDT 24
Finished Apr 28 01:04:38 PM PDT 24
Peak memory 723200 kb
Host smart-fc1d084d-3d10-487d-b523-2a18cd7db4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838323030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.3838323030
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.1625956748
Short name T1297
Test name
Test status
Simulation time 1548054132 ps
CPU time 4.41 seconds
Started Apr 28 01:03:45 PM PDT 24
Finished Apr 28 01:03:49 PM PDT 24
Peak memory 204108 kb
Host smart-f7a4ef49-552a-478e-8c69-ac6c74c72163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625956748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.1625956748
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.8182722
Short name T649
Test name
Test status
Simulation time 27401661051 ps
CPU time 33.4 seconds
Started Apr 28 01:03:50 PM PDT 24
Finished Apr 28 01:04:24 PM PDT 24
Peak memory 342184 kb
Host smart-bbbbfc77-608d-4a1a-b672-a868e36cfe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8182722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.8182722
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.1639802446
Short name T1055
Test name
Test status
Simulation time 147267715 ps
CPU time 0.62 seconds
Started Apr 28 01:03:40 PM PDT 24
Finished Apr 28 01:03:42 PM PDT 24
Peak memory 203864 kb
Host smart-eb3fe6e1-37a5-4586-9218-ad3c0050bfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639802446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.1639802446
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.2400061127
Short name T524
Test name
Test status
Simulation time 8153871677 ps
CPU time 41.68 seconds
Started Apr 28 01:03:42 PM PDT 24
Finished Apr 28 01:04:25 PM PDT 24
Peak memory 212376 kb
Host smart-75f1e0be-e43a-4661-913a-af8d31f936b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400061127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.2400061127
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.845311350
Short name T80
Test name
Test status
Simulation time 3839685965 ps
CPU time 48.47 seconds
Started Apr 28 01:03:40 PM PDT 24
Finished Apr 28 01:04:30 PM PDT 24
Peak memory 299564 kb
Host smart-c240dc67-2d16-4b3a-b759-12daeec7f749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845311350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.845311350
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.3979245111
Short name T619
Test name
Test status
Simulation time 2371240392 ps
CPU time 6.67 seconds
Started Apr 28 01:03:41 PM PDT 24
Finished Apr 28 01:03:49 PM PDT 24
Peak memory 214176 kb
Host smart-346b8927-2aa2-48f3-bd36-1ffe24b80a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979245111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.3979245111
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.1263940415
Short name T1081
Test name
Test status
Simulation time 1176647767 ps
CPU time 5.08 seconds
Started Apr 28 01:03:49 PM PDT 24
Finished Apr 28 01:03:54 PM PDT 24
Peak memory 212504 kb
Host smart-464c771e-f848-44e1-ab50-edfe6c7222b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263940415 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1263940415
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.2219584775
Short name T58
Test name
Test status
Simulation time 10057252296 ps
CPU time 41.26 seconds
Started Apr 28 01:03:46 PM PDT 24
Finished Apr 28 01:04:27 PM PDT 24
Peak memory 410996 kb
Host smart-c3b6cd89-55be-4546-bc8a-d867def63a75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219584775 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.2219584775
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.2845801243
Short name T56
Test name
Test status
Simulation time 10135340722 ps
CPU time 32.33 seconds
Started Apr 28 01:03:47 PM PDT 24
Finished Apr 28 01:04:20 PM PDT 24
Peak memory 376204 kb
Host smart-6e923029-b711-4582-8902-217efaff0f40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845801243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.2845801243
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.1878505060
Short name T405
Test name
Test status
Simulation time 2479427055 ps
CPU time 2.74 seconds
Started Apr 28 01:03:48 PM PDT 24
Finished Apr 28 01:03:51 PM PDT 24
Peak memory 204248 kb
Host smart-e55762ed-9312-4291-bb7a-1d2b5c1125b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878505060 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.1878505060
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.4231556075
Short name T1074
Test name
Test status
Simulation time 1580357814 ps
CPU time 3.94 seconds
Started Apr 28 01:03:45 PM PDT 24
Finished Apr 28 01:03:49 PM PDT 24
Peak memory 204096 kb
Host smart-4dec3719-5c8a-49f0-a71c-d3fa7d4b9b09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231556075 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.4231556075
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.314673201
Short name T1014
Test name
Test status
Simulation time 2734654592 ps
CPU time 2.01 seconds
Started Apr 28 01:03:47 PM PDT 24
Finished Apr 28 01:03:49 PM PDT 24
Peak memory 204188 kb
Host smart-463318b8-fb0d-4c7b-b92d-3622ee0d4411
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314673201 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.314673201
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.1858528106
Short name T550
Test name
Test status
Simulation time 2528016283 ps
CPU time 7.58 seconds
Started Apr 28 01:03:47 PM PDT 24
Finished Apr 28 01:03:56 PM PDT 24
Peak memory 204212 kb
Host smart-378868eb-3174-4cbf-955e-dcd70ac71579
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858528106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.1858528106
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.3327251481
Short name T1194
Test name
Test status
Simulation time 783518174 ps
CPU time 30.66 seconds
Started Apr 28 01:03:45 PM PDT 24
Finished Apr 28 01:04:16 PM PDT 24
Peak memory 204124 kb
Host smart-cebc25d5-93c9-452f-a4d1-2e1ded260b8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327251481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.3327251481
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3913536185
Short name T912
Test name
Test status
Simulation time 39703298400 ps
CPU time 71.56 seconds
Started Apr 28 01:03:51 PM PDT 24
Finished Apr 28 01:05:04 PM PDT 24
Peak memory 1227812 kb
Host smart-2e0e6622-672f-42cb-a510-70803316021d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913536185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3913536185
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.1508198649
Short name T728
Test name
Test status
Simulation time 23712178189 ps
CPU time 1892.88 seconds
Started Apr 28 01:03:47 PM PDT 24
Finished Apr 28 01:35:21 PM PDT 24
Peak memory 5854224 kb
Host smart-6d8d9e65-c6e8-4ac7-b469-edb2530dbf04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508198649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.1508198649
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.3481766055
Short name T12
Test name
Test status
Simulation time 4979239517 ps
CPU time 6.76 seconds
Started Apr 28 01:03:46 PM PDT 24
Finished Apr 28 01:03:53 PM PDT 24
Peak memory 213296 kb
Host smart-b81f7df7-f262-4b63-8bba-e602b4f782e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481766055 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.3481766055
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.4076216482
Short name T607
Test name
Test status
Simulation time 18877476 ps
CPU time 0.63 seconds
Started Apr 28 01:04:02 PM PDT 24
Finished Apr 28 01:04:03 PM PDT 24
Peak memory 203856 kb
Host smart-4316b4b2-ba5a-4079-9c77-9758f8087390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076216482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.4076216482
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.2652361606
Short name T265
Test name
Test status
Simulation time 329333165 ps
CPU time 1.45 seconds
Started Apr 28 01:03:56 PM PDT 24
Finished Apr 28 01:03:58 PM PDT 24
Peak memory 220536 kb
Host smart-2daa6927-7322-422d-b528-e6f08a3581e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652361606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.2652361606
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.918493910
Short name T1052
Test name
Test status
Simulation time 1570058234 ps
CPU time 21.04 seconds
Started Apr 28 01:03:52 PM PDT 24
Finished Apr 28 01:04:14 PM PDT 24
Peak memory 287268 kb
Host smart-fea48eff-47f7-47e5-9392-f63552178812
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918493910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empt
y.918493910
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.1753666436
Short name T920
Test name
Test status
Simulation time 2194063076 ps
CPU time 158.2 seconds
Started Apr 28 01:03:52 PM PDT 24
Finished Apr 28 01:06:31 PM PDT 24
Peak memory 725504 kb
Host smart-e961b804-e7bb-4f56-ae64-6c1d1ad20a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753666436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.1753666436
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.3869376903
Short name T108
Test name
Test status
Simulation time 2726480154 ps
CPU time 34.73 seconds
Started Apr 28 01:03:51 PM PDT 24
Finished Apr 28 01:04:27 PM PDT 24
Peak memory 527812 kb
Host smart-8bfe640e-bf39-4cbf-9a60-5e3f17235c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869376903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.3869376903
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.1822414515
Short name T1045
Test name
Test status
Simulation time 424331691 ps
CPU time 0.99 seconds
Started Apr 28 01:03:53 PM PDT 24
Finished Apr 28 01:03:54 PM PDT 24
Peak memory 204148 kb
Host smart-a0ae441e-805e-4c24-b276-88d30af6691b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822414515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.1822414515
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.2706719568
Short name T1171
Test name
Test status
Simulation time 125945183 ps
CPU time 7.34 seconds
Started Apr 28 01:03:53 PM PDT 24
Finished Apr 28 01:04:01 PM PDT 24
Peak memory 224264 kb
Host smart-668f99ab-e136-4bd4-ac83-b21c2fb7995c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706719568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.2706719568
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.167851888
Short name T742
Test name
Test status
Simulation time 14475295745 ps
CPU time 246.81 seconds
Started Apr 28 01:03:46 PM PDT 24
Finished Apr 28 01:07:53 PM PDT 24
Peak memory 1069664 kb
Host smart-76ed9a68-f123-4f22-ab70-bd13a3f1659d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167851888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.167851888
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.811454487
Short name T603
Test name
Test status
Simulation time 2289412370 ps
CPU time 14.29 seconds
Started Apr 28 01:03:58 PM PDT 24
Finished Apr 28 01:04:13 PM PDT 24
Peak memory 204252 kb
Host smart-33955e81-cd19-4f6a-bad3-d6b0404116f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811454487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.811454487
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.3730852934
Short name T787
Test name
Test status
Simulation time 3253059402 ps
CPU time 31.09 seconds
Started Apr 28 01:04:00 PM PDT 24
Finished Apr 28 01:04:32 PM PDT 24
Peak memory 313320 kb
Host smart-1255f579-6249-48cc-9513-14c81011ab4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730852934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.3730852934
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_perf.3502973463
Short name T578
Test name
Test status
Simulation time 3258519262 ps
CPU time 34.65 seconds
Started Apr 28 01:03:51 PM PDT 24
Finished Apr 28 01:04:26 PM PDT 24
Peak memory 228552 kb
Host smart-acaf0caf-9f33-4cf3-be91-7f6947c5ad60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502973463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.3502973463
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.2284845104
Short name T278
Test name
Test status
Simulation time 1395929824 ps
CPU time 28.12 seconds
Started Apr 28 01:03:51 PM PDT 24
Finished Apr 28 01:04:19 PM PDT 24
Peak memory 340096 kb
Host smart-554e344f-9ad9-451e-93a4-aad47bfdb9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284845104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.2284845104
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.2159025490
Short name T1077
Test name
Test status
Simulation time 4446825231 ps
CPU time 167.13 seconds
Started Apr 28 01:03:52 PM PDT 24
Finished Apr 28 01:06:39 PM PDT 24
Peak memory 957208 kb
Host smart-76d96eb6-c468-4d7e-aa06-ade36317ee18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159025490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.2159025490
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.3160583209
Short name T340
Test name
Test status
Simulation time 685419109 ps
CPU time 10.19 seconds
Started Apr 28 01:03:53 PM PDT 24
Finished Apr 28 01:04:04 PM PDT 24
Peak memory 215964 kb
Host smart-ca00bd09-3db5-4f5e-8b76-2a53dfabba33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160583209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.3160583209
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.1804151580
Short name T1214
Test name
Test status
Simulation time 550769386 ps
CPU time 3.14 seconds
Started Apr 28 01:03:58 PM PDT 24
Finished Apr 28 01:04:02 PM PDT 24
Peak memory 204008 kb
Host smart-636322eb-8480-483b-b542-78a6ab9f1b34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804151580 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.1804151580
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.1062658999
Short name T102
Test name
Test status
Simulation time 10377558761 ps
CPU time 10.82 seconds
Started Apr 28 01:03:51 PM PDT 24
Finished Apr 28 01:04:02 PM PDT 24
Peak memory 253412 kb
Host smart-669fb754-a86f-4703-9d66-0b4659924f5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062658999 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.1062658999
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.971968480
Short name T262
Test name
Test status
Simulation time 10175574732 ps
CPU time 7.97 seconds
Started Apr 28 01:04:02 PM PDT 24
Finished Apr 28 01:04:11 PM PDT 24
Peak memory 253812 kb
Host smart-15d79d48-5895-4a96-830b-ff817c17da58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971968480 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_fifo_reset_tx.971968480
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.2920225921
Short name T1330
Test name
Test status
Simulation time 1658611637 ps
CPU time 2.38 seconds
Started Apr 28 01:04:02 PM PDT 24
Finished Apr 28 01:04:06 PM PDT 24
Peak memory 204148 kb
Host smart-dadeb815-5a91-4ba5-8577-1def094c5b8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920225921 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.2920225921
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.3251071310
Short name T1302
Test name
Test status
Simulation time 3104646162 ps
CPU time 5.69 seconds
Started Apr 28 01:03:53 PM PDT 24
Finished Apr 28 01:03:59 PM PDT 24
Peak memory 220376 kb
Host smart-8b800949-6854-44f3-a532-e04c4cdaa7fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251071310 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.3251071310
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.1532446843
Short name T1362
Test name
Test status
Simulation time 8028334505 ps
CPU time 107.74 seconds
Started Apr 28 01:03:53 PM PDT 24
Finished Apr 28 01:05:42 PM PDT 24
Peak memory 2038976 kb
Host smart-efc7a45e-9742-4aed-ac37-ad02660d0374
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532446843 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.1532446843
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.2749300541
Short name T1139
Test name
Test status
Simulation time 1225745437 ps
CPU time 14.85 seconds
Started Apr 28 01:03:53 PM PDT 24
Finished Apr 28 01:04:08 PM PDT 24
Peak memory 204108 kb
Host smart-628fe165-5d2a-43a8-9acf-456bee3f6985
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749300541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.2749300541
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.850281947
Short name T851
Test name
Test status
Simulation time 1255405090 ps
CPU time 4.65 seconds
Started Apr 28 01:03:52 PM PDT 24
Finished Apr 28 01:03:58 PM PDT 24
Peak memory 204160 kb
Host smart-7c56479f-efed-413d-b4ea-e4c3dc53ec1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850281947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_rd.850281947
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.2636113479
Short name T29
Test name
Test status
Simulation time 68004311891 ps
CPU time 858.48 seconds
Started Apr 28 01:03:53 PM PDT 24
Finished Apr 28 01:18:12 PM PDT 24
Peak memory 6069308 kb
Host smart-75af7170-0091-4368-be2e-23c170bca026
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636113479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.2636113479
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.550582630
Short name T1087
Test name
Test status
Simulation time 23912379624 ps
CPU time 71.51 seconds
Started Apr 28 01:03:51 PM PDT 24
Finished Apr 28 01:05:03 PM PDT 24
Peak memory 707492 kb
Host smart-171f0dde-0a96-403c-9e82-08ec3f7898ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550582630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_t
arget_stretch.550582630
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.1165895804
Short name T782
Test name
Test status
Simulation time 1165030045 ps
CPU time 6.37 seconds
Started Apr 28 01:03:53 PM PDT 24
Finished Apr 28 01:04:00 PM PDT 24
Peak memory 216380 kb
Host smart-9ce5b776-8f02-42cb-ae34-4aca3386ee0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165895804 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.1165895804
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.1376724499
Short name T780
Test name
Test status
Simulation time 17260904 ps
CPU time 0.6 seconds
Started Apr 28 12:59:11 PM PDT 24
Finished Apr 28 12:59:15 PM PDT 24
Peak memory 203792 kb
Host smart-d867a246-33f5-4271-b8ec-d2fd2016d636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376724499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.1376724499
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.1904030587
Short name T1296
Test name
Test status
Simulation time 426249105 ps
CPU time 1.59 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 12:59:07 PM PDT 24
Peak memory 220540 kb
Host smart-49229c4f-4d96-495b-ad96-0f274a39d35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904030587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.1904030587
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.209044063
Short name T913
Test name
Test status
Simulation time 908953381 ps
CPU time 5.56 seconds
Started Apr 28 12:59:00 PM PDT 24
Finished Apr 28 12:59:06 PM PDT 24
Peak memory 244308 kb
Host smart-11d565cc-eb64-4567-b1d3-9a4d0c772a02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209044063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty
.209044063
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.1500419773
Short name T98
Test name
Test status
Simulation time 1174730929 ps
CPU time 71.66 seconds
Started Apr 28 12:59:05 PM PDT 24
Finished Apr 28 01:00:18 PM PDT 24
Peak memory 469072 kb
Host smart-0c6fec91-7543-4d23-8c37-74dd85a5c1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500419773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.1500419773
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1466409207
Short name T319
Test name
Test status
Simulation time 1819763745 ps
CPU time 56.44 seconds
Started Apr 28 12:59:04 PM PDT 24
Finished Apr 28 01:00:02 PM PDT 24
Peak memory 656636 kb
Host smart-0c60a788-e873-428c-b907-95f329ad87f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466409207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1466409207
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.4011984495
Short name T784
Test name
Test status
Simulation time 493870719 ps
CPU time 1.08 seconds
Started Apr 28 12:59:10 PM PDT 24
Finished Apr 28 12:59:15 PM PDT 24
Peak memory 203984 kb
Host smart-ca6d54ff-35b3-4f8d-ace1-b666fdaf1c67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011984495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.4011984495
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.1987216820
Short name T574
Test name
Test status
Simulation time 140463293 ps
CPU time 4.07 seconds
Started Apr 28 12:59:02 PM PDT 24
Finished Apr 28 12:59:07 PM PDT 24
Peak memory 226700 kb
Host smart-7ccbf2ec-c3b4-4748-9973-f8d4c4e87631
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987216820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
1987216820
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.3904867061
Short name T179
Test name
Test status
Simulation time 3440384712 ps
CPU time 86.29 seconds
Started Apr 28 12:59:11 PM PDT 24
Finished Apr 28 01:00:41 PM PDT 24
Peak memory 1038300 kb
Host smart-a865058a-e9a1-4bdd-9ac1-70d533442a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904867061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3904867061
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.1852432315
Short name T677
Test name
Test status
Simulation time 394518213 ps
CPU time 2.91 seconds
Started Apr 28 12:59:05 PM PDT 24
Finished Apr 28 12:59:09 PM PDT 24
Peak memory 204132 kb
Host smart-4c435d40-8538-459e-9fef-06f86beca493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852432315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.1852432315
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.2510290943
Short name T423
Test name
Test status
Simulation time 1616203581 ps
CPU time 77.47 seconds
Started Apr 28 12:59:08 PM PDT 24
Finished Apr 28 01:00:28 PM PDT 24
Peak memory 343648 kb
Host smart-deed4c7e-ec49-41a9-9275-e45e203c3404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510290943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.2510290943
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.2214599629
Short name T877
Test name
Test status
Simulation time 22887382 ps
CPU time 0.65 seconds
Started Apr 28 12:59:08 PM PDT 24
Finished Apr 28 12:59:11 PM PDT 24
Peak memory 203804 kb
Host smart-229ec1e6-a3c3-4a4c-b8c9-67d456ddea52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214599629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.2214599629
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.1505817243
Short name T826
Test name
Test status
Simulation time 25885926536 ps
CPU time 57.31 seconds
Started Apr 28 12:58:56 PM PDT 24
Finished Apr 28 12:59:54 PM PDT 24
Peak memory 204236 kb
Host smart-fc7aa73a-6940-4797-8aca-ddcba45ab385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505817243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.1505817243
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.1699629124
Short name T373
Test name
Test status
Simulation time 2331389703 ps
CPU time 17.21 seconds
Started Apr 28 12:59:04 PM PDT 24
Finished Apr 28 12:59:23 PM PDT 24
Peak memory 300840 kb
Host smart-bb159dbf-bee7-4cd9-8275-decf3ced9e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699629124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.1699629124
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.4048403651
Short name T1340
Test name
Test status
Simulation time 46003382316 ps
CPU time 388.11 seconds
Started Apr 28 12:59:10 PM PDT 24
Finished Apr 28 01:05:42 PM PDT 24
Peak memory 1980440 kb
Host smart-19b5fa23-ac0c-46ea-9dc3-17a9ad683f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048403651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.4048403651
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.3879391717
Short name T1314
Test name
Test status
Simulation time 1060965708 ps
CPU time 23.99 seconds
Started Apr 28 12:59:08 PM PDT 24
Finished Apr 28 12:59:34 PM PDT 24
Peak memory 212232 kb
Host smart-b0913f9f-ce72-4100-8a72-9dc35a43f4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879391717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.3879391717
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.850590618
Short name T840
Test name
Test status
Simulation time 928495139 ps
CPU time 4.23 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 12:59:10 PM PDT 24
Peak memory 212300 kb
Host smart-0dd17642-f9ba-422b-af93-25e013bf1eb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850590618 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.850590618
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.1282002885
Short name T87
Test name
Test status
Simulation time 10195517808 ps
CPU time 34.11 seconds
Started Apr 28 12:59:10 PM PDT 24
Finished Apr 28 12:59:48 PM PDT 24
Peak memory 377644 kb
Host smart-b2616cb2-a185-426e-af61-c5f6b2b195ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282002885 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.1282002885
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.3694461644
Short name T659
Test name
Test status
Simulation time 10111530782 ps
CPU time 12.35 seconds
Started Apr 28 12:59:04 PM PDT 24
Finished Apr 28 12:59:18 PM PDT 24
Peak memory 258608 kb
Host smart-211a9b64-6344-4efc-9c08-1b022650121d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694461644 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.3694461644
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.353580617
Short name T553
Test name
Test status
Simulation time 897195824 ps
CPU time 2.76 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 12:59:08 PM PDT 24
Peak memory 204220 kb
Host smart-4f20741c-d022-4f2c-a4f7-13d94fae4255
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353580617 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.i2c_target_hrst.353580617
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.1174458911
Short name T33
Test name
Test status
Simulation time 1330883040 ps
CPU time 6.78 seconds
Started Apr 28 12:59:08 PM PDT 24
Finished Apr 28 12:59:19 PM PDT 24
Peak memory 220444 kb
Host smart-81dee3e9-cbdb-4eaa-972f-2cd72e9a420b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174458911 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.1174458911
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.2144456235
Short name T942
Test name
Test status
Simulation time 22797698076 ps
CPU time 36.63 seconds
Started Apr 28 12:59:03 PM PDT 24
Finished Apr 28 12:59:42 PM PDT 24
Peak memory 901560 kb
Host smart-ad31007d-bd31-48f0-b95a-634cea9ad0d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144456235 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.2144456235
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.3416334962
Short name T689
Test name
Test status
Simulation time 4009242885 ps
CPU time 12.47 seconds
Started Apr 28 12:59:01 PM PDT 24
Finished Apr 28 12:59:14 PM PDT 24
Peak memory 204212 kb
Host smart-d73ed5b1-7b19-481a-9c03-b5281a595777
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416334962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.3416334962
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.1771795811
Short name T506
Test name
Test status
Simulation time 1750660241 ps
CPU time 31.97 seconds
Started Apr 28 12:59:07 PM PDT 24
Finished Apr 28 12:59:41 PM PDT 24
Peak memory 224728 kb
Host smart-3d9861ec-070d-4c4a-86a0-37c1c29fc525
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771795811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.1771795811
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.532897026
Short name T368
Test name
Test status
Simulation time 28267223617 ps
CPU time 67.86 seconds
Started Apr 28 12:59:08 PM PDT 24
Finished Apr 28 01:00:18 PM PDT 24
Peak memory 1122236 kb
Host smart-656f8609-3865-4149-b44e-c566602b0e29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532897026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_wr.532897026
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.3418581139
Short name T414
Test name
Test status
Simulation time 9181040309 ps
CPU time 114.15 seconds
Started Apr 28 12:59:04 PM PDT 24
Finished Apr 28 01:01:01 PM PDT 24
Peak memory 1111556 kb
Host smart-eccbda54-1f88-4ccf-b8b9-e08cc9e6e1c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418581139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.3418581139
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.2465455840
Short name T900
Test name
Test status
Simulation time 4460800829 ps
CPU time 5.63 seconds
Started Apr 28 12:59:09 PM PDT 24
Finished Apr 28 12:59:18 PM PDT 24
Peak memory 212392 kb
Host smart-1d518f23-76ad-483c-a495-72ea28273067
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465455840 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.2465455840
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.2369171052
Short name T941
Test name
Test status
Simulation time 43324967 ps
CPU time 0.6 seconds
Started Apr 28 12:59:11 PM PDT 24
Finished Apr 28 12:59:15 PM PDT 24
Peak memory 203860 kb
Host smart-09c022cf-8f58-47a7-8cf7-a6c50a2ff559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369171052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2369171052
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.2467045207
Short name T1204
Test name
Test status
Simulation time 107008969 ps
CPU time 1.56 seconds
Started Apr 28 12:59:02 PM PDT 24
Finished Apr 28 12:59:06 PM PDT 24
Peak memory 220644 kb
Host smart-be51d722-0fb3-442b-8487-8047c28240e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467045207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.2467045207
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.3872761028
Short name T304
Test name
Test status
Simulation time 395854776 ps
CPU time 4.29 seconds
Started Apr 28 12:59:10 PM PDT 24
Finished Apr 28 12:59:17 PM PDT 24
Peak memory 240080 kb
Host smart-0c5869b3-51d7-4e8c-bfbd-53391a87c9a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872761028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.3872761028
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.2223244339
Short name T84
Test name
Test status
Simulation time 16146240598 ps
CPU time 130.13 seconds
Started Apr 28 12:59:09 PM PDT 24
Finished Apr 28 01:01:22 PM PDT 24
Peak memory 645188 kb
Host smart-30c9a6a4-72a7-443f-bfcf-a75590f9258d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223244339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2223244339
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.2058168572
Short name T769
Test name
Test status
Simulation time 1155316632 ps
CPU time 75.76 seconds
Started Apr 28 12:59:09 PM PDT 24
Finished Apr 28 01:00:29 PM PDT 24
Peak memory 479432 kb
Host smart-3e1900a6-734c-43a0-b622-09e9a8c08b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058168572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.2058168572
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.1529924594
Short name T125
Test name
Test status
Simulation time 126679728 ps
CPU time 0.75 seconds
Started Apr 28 12:59:05 PM PDT 24
Finished Apr 28 12:59:08 PM PDT 24
Peak memory 204008 kb
Host smart-45bdc05c-e825-42c0-85ac-586c4e8dc4f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529924594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.1529924594
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3390786437
Short name T1002
Test name
Test status
Simulation time 219720120 ps
CPU time 3.09 seconds
Started Apr 28 12:59:11 PM PDT 24
Finished Apr 28 12:59:18 PM PDT 24
Peak memory 220804 kb
Host smart-bb170c72-deb5-4d77-90ce-0465b641d2b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390786437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
3390786437
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.3300210270
Short name T184
Test name
Test status
Simulation time 10471587398 ps
CPU time 55.53 seconds
Started Apr 28 12:59:11 PM PDT 24
Finished Apr 28 01:00:10 PM PDT 24
Peak memory 830576 kb
Host smart-1ab4697a-5903-49a8-97cb-44dfbc7551a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300210270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.3300210270
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.1360626230
Short name T1308
Test name
Test status
Simulation time 634867080 ps
CPU time 11.16 seconds
Started Apr 28 12:59:18 PM PDT 24
Finished Apr 28 12:59:30 PM PDT 24
Peak memory 204200 kb
Host smart-1bd1d234-78ad-4524-aa1e-a3f41f52ea95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360626230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.1360626230
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.1775080681
Short name T906
Test name
Test status
Simulation time 4580284556 ps
CPU time 25.86 seconds
Started Apr 28 12:59:06 PM PDT 24
Finished Apr 28 12:59:34 PM PDT 24
Peak memory 351452 kb
Host smart-4844a03f-0faf-4e9c-929a-21bb85a9e7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775080681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.1775080681
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.2574531548
Short name T1057
Test name
Test status
Simulation time 101994205 ps
CPU time 0.61 seconds
Started Apr 28 12:59:12 PM PDT 24
Finished Apr 28 12:59:16 PM PDT 24
Peak memory 203788 kb
Host smart-5d5dbc28-c0a0-4bf0-b621-d156aa23194a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574531548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.2574531548
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.1270415781
Short name T1192
Test name
Test status
Simulation time 5238267906 ps
CPU time 59.9 seconds
Started Apr 28 12:59:08 PM PDT 24
Finished Apr 28 01:00:11 PM PDT 24
Peak memory 231548 kb
Host smart-38b6995f-b2f2-465f-8a41-1cfc30d60df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270415781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.1270415781
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.2094294394
Short name T1206
Test name
Test status
Simulation time 4794311941 ps
CPU time 21.82 seconds
Started Apr 28 12:59:04 PM PDT 24
Finished Apr 28 12:59:28 PM PDT 24
Peak memory 301736 kb
Host smart-2570bd0a-a70c-4d1f-a0e0-f96d080ecbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094294394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.2094294394
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.2692423435
Short name T258
Test name
Test status
Simulation time 15999489514 ps
CPU time 1767.97 seconds
Started Apr 28 12:59:11 PM PDT 24
Finished Apr 28 01:28:42 PM PDT 24
Peak memory 1988232 kb
Host smart-c53518d6-6fe0-4edb-8790-2fe6f691b23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692423435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.2692423435
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.3142744753
Short name T253
Test name
Test status
Simulation time 864481906 ps
CPU time 16.27 seconds
Started Apr 28 12:59:05 PM PDT 24
Finished Apr 28 12:59:24 PM PDT 24
Peak memory 218512 kb
Host smart-42fc5020-b77a-49bd-ae86-578829543ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142744753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.3142744753
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.1603497316
Short name T536
Test name
Test status
Simulation time 817124227 ps
CPU time 3.71 seconds
Started Apr 28 12:59:12 PM PDT 24
Finished Apr 28 12:59:19 PM PDT 24
Peak memory 204236 kb
Host smart-efd921cb-3d4e-4324-97aa-591adeb2bfce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603497316 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.1603497316
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2189816093
Short name T761
Test name
Test status
Simulation time 10178427865 ps
CPU time 64.35 seconds
Started Apr 28 12:59:04 PM PDT 24
Finished Apr 28 01:00:11 PM PDT 24
Peak memory 528076 kb
Host smart-fb5d87aa-042e-4f19-ab51-111e2c6949b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189816093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2189816093
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.1427501713
Short name T685
Test name
Test status
Simulation time 10067794151 ps
CPU time 60.99 seconds
Started Apr 28 12:59:02 PM PDT 24
Finished Apr 28 01:00:04 PM PDT 24
Peak memory 433032 kb
Host smart-20c393de-5808-4568-851d-789054278071
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427501713 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.1427501713
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.784960437
Short name T927
Test name
Test status
Simulation time 1854518193 ps
CPU time 2.53 seconds
Started Apr 28 12:59:19 PM PDT 24
Finished Apr 28 12:59:22 PM PDT 24
Peak memory 204164 kb
Host smart-a29e348d-6134-4cb5-869e-9c9502ac60e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784960437 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.i2c_target_hrst.784960437
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.2322538012
Short name T1069
Test name
Test status
Simulation time 695373399 ps
CPU time 3.43 seconds
Started Apr 28 12:59:08 PM PDT 24
Finished Apr 28 12:59:15 PM PDT 24
Peak memory 204024 kb
Host smart-2a4de655-ef7c-4b7c-ba5a-d03cab670160
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322538012 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.2322538012
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.51561727
Short name T317
Test name
Test status
Simulation time 21088586872 ps
CPU time 413.85 seconds
Started Apr 28 12:59:08 PM PDT 24
Finished Apr 28 01:06:05 PM PDT 24
Peak memory 3727236 kb
Host smart-a6fa8acc-5bc6-4708-b92c-605be58d4b1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51561727 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.51561727
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.3059247121
Short name T299
Test name
Test status
Simulation time 910581483 ps
CPU time 14.21 seconds
Started Apr 28 12:59:04 PM PDT 24
Finished Apr 28 12:59:21 PM PDT 24
Peak memory 204104 kb
Host smart-7abc0e39-e67b-4afa-ad0a-3167bc31d68d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059247121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.3059247121
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.3318754270
Short name T238
Test name
Test status
Simulation time 3970055876 ps
CPU time 34.84 seconds
Started Apr 28 12:59:11 PM PDT 24
Finished Apr 28 12:59:49 PM PDT 24
Peak memory 204228 kb
Host smart-b15f430b-e896-4415-bf62-9d6d30d4302a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318754270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.3318754270
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.2601843844
Short name T245
Test name
Test status
Simulation time 52051776961 ps
CPU time 1576.99 seconds
Started Apr 28 12:59:10 PM PDT 24
Finished Apr 28 01:25:31 PM PDT 24
Peak memory 8135508 kb
Host smart-168bbe1d-9521-4192-b206-4f86129083bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601843844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.2601843844
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.1695377561
Short name T191
Test name
Test status
Simulation time 36002841274 ps
CPU time 815.52 seconds
Started Apr 28 12:59:12 PM PDT 24
Finished Apr 28 01:12:51 PM PDT 24
Peak memory 2132376 kb
Host smart-3f01304b-94ad-4afc-9709-cfec2d44f22f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695377561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.1695377561
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.3939992117
Short name T1140
Test name
Test status
Simulation time 2666242223 ps
CPU time 6.88 seconds
Started Apr 28 12:59:08 PM PDT 24
Finished Apr 28 12:59:17 PM PDT 24
Peak memory 220312 kb
Host smart-c010a5b5-8fb3-4cb3-aa11-c3ea6ea980b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939992117 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.3939992117
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.2526463193
Short name T628
Test name
Test status
Simulation time 49890224 ps
CPU time 0.6 seconds
Started Apr 28 12:59:30 PM PDT 24
Finished Apr 28 12:59:31 PM PDT 24
Peak memory 203908 kb
Host smart-4770187f-cbe2-4e4b-8b89-951ad33d4143
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526463193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2526463193
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.2913604147
Short name T798
Test name
Test status
Simulation time 57452858 ps
CPU time 1.17 seconds
Started Apr 28 12:59:04 PM PDT 24
Finished Apr 28 12:59:08 PM PDT 24
Peak memory 212408 kb
Host smart-03c71f71-0305-4be3-ac63-f6133d4ee7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913604147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.2913604147
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.2763723905
Short name T1115
Test name
Test status
Simulation time 343420279 ps
CPU time 15.28 seconds
Started Apr 28 12:59:11 PM PDT 24
Finished Apr 28 12:59:30 PM PDT 24
Peak memory 236876 kb
Host smart-a5183e87-a339-49b1-9cb0-41a12ff18e02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763723905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.2763723905
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.2910203219
Short name T47
Test name
Test status
Simulation time 2124172356 ps
CPU time 64.02 seconds
Started Apr 28 12:59:07 PM PDT 24
Finished Apr 28 01:00:13 PM PDT 24
Peak memory 708688 kb
Host smart-e86016e5-6a66-43a0-942d-d53e87ecb680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910203219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.2910203219
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.2629958497
Short name T1357
Test name
Test status
Simulation time 4419401386 ps
CPU time 30.27 seconds
Started Apr 28 12:59:10 PM PDT 24
Finished Apr 28 12:59:43 PM PDT 24
Peak memory 488628 kb
Host smart-c0efc21f-b745-4637-aa3f-cf30cc9817a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629958497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2629958497
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.1277059960
Short name T1060
Test name
Test status
Simulation time 451577599 ps
CPU time 0.88 seconds
Started Apr 28 12:59:08 PM PDT 24
Finished Apr 28 12:59:12 PM PDT 24
Peak memory 203732 kb
Host smart-60f848ac-1bb9-465e-8260-9d6af2745caa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277059960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.1277059960
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.1760790400
Short name T1358
Test name
Test status
Simulation time 102691631 ps
CPU time 3.05 seconds
Started Apr 28 12:59:11 PM PDT 24
Finished Apr 28 12:59:18 PM PDT 24
Peak memory 217604 kb
Host smart-2cb4697c-1fbd-401c-8ed4-b27d7cdde6aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760790400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
1760790400
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.1054487926
Short name T802
Test name
Test status
Simulation time 4529723725 ps
CPU time 57.48 seconds
Started Apr 28 12:59:09 PM PDT 24
Finished Apr 28 01:00:10 PM PDT 24
Peak memory 719080 kb
Host smart-609ad7aa-4472-451b-a3bc-81db1bbcfa14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054487926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.1054487926
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.3224417138
Short name T530
Test name
Test status
Simulation time 1096089949 ps
CPU time 8.91 seconds
Started Apr 28 12:59:10 PM PDT 24
Finished Apr 28 12:59:23 PM PDT 24
Peak memory 204196 kb
Host smart-ada99788-7b9d-4ee5-9e41-54861c8be6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224417138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3224417138
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.52216573
Short name T39
Test name
Test status
Simulation time 3458958016 ps
CPU time 26.98 seconds
Started Apr 28 12:59:13 PM PDT 24
Finished Apr 28 12:59:43 PM PDT 24
Peak memory 330116 kb
Host smart-8a96a925-10dd-4de3-9ba7-eed2a291b7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52216573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.52216573
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.107497917
Short name T429
Test name
Test status
Simulation time 49083923 ps
CPU time 0.65 seconds
Started Apr 28 12:59:10 PM PDT 24
Finished Apr 28 12:59:14 PM PDT 24
Peak memory 203716 kb
Host smart-bfa4ffc0-0f69-47d0-9717-d9cff979bd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107497917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.107497917
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.819653006
Short name T1076
Test name
Test status
Simulation time 49871943886 ps
CPU time 94.2 seconds
Started Apr 28 12:59:12 PM PDT 24
Finished Apr 28 01:00:50 PM PDT 24
Peak memory 220076 kb
Host smart-fd75cdff-7225-42d9-8630-f4e7360dd3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819653006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.819653006
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.2608080842
Short name T518
Test name
Test status
Simulation time 1300840524 ps
CPU time 62.57 seconds
Started Apr 28 12:59:10 PM PDT 24
Finished Apr 28 01:00:16 PM PDT 24
Peak memory 302572 kb
Host smart-e6e19526-45f1-410b-a545-ffa8b9883acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608080842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.2608080842
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.3186722458
Short name T1183
Test name
Test status
Simulation time 1708652037 ps
CPU time 8.36 seconds
Started Apr 28 12:59:08 PM PDT 24
Finished Apr 28 12:59:20 PM PDT 24
Peak memory 212364 kb
Host smart-860d2db9-a6a9-4e32-8be8-716b55e371a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186722458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.3186722458
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.704360998
Short name T96
Test name
Test status
Simulation time 823670613 ps
CPU time 2.64 seconds
Started Apr 28 12:59:13 PM PDT 24
Finished Apr 28 12:59:19 PM PDT 24
Peak memory 204152 kb
Host smart-3f3f831c-829c-46c6-b6d8-3323efbef32f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704360998 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.704360998
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.3766328367
Short name T914
Test name
Test status
Simulation time 10032748007 ps
CPU time 63.26 seconds
Started Apr 28 12:59:10 PM PDT 24
Finished Apr 28 01:00:17 PM PDT 24
Peak memory 443604 kb
Host smart-d7feb8f6-5763-4391-a920-dbf6b9f9228e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766328367 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.3766328367
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.3560306243
Short name T205
Test name
Test status
Simulation time 10308013835 ps
CPU time 14.01 seconds
Started Apr 28 12:59:22 PM PDT 24
Finished Apr 28 12:59:37 PM PDT 24
Peak memory 258308 kb
Host smart-a8ad070e-1309-4e61-8bea-02a0699885b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560306243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.3560306243
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.4076426824
Short name T1073
Test name
Test status
Simulation time 1794762354 ps
CPU time 2.48 seconds
Started Apr 28 12:59:07 PM PDT 24
Finished Apr 28 12:59:12 PM PDT 24
Peak memory 204204 kb
Host smart-f72b06c2-37e6-49ce-8948-4ad3a53064b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076426824 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.4076426824
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.401455626
Short name T350
Test name
Test status
Simulation time 6143012327 ps
CPU time 7.61 seconds
Started Apr 28 12:59:11 PM PDT 24
Finished Apr 28 12:59:22 PM PDT 24
Peak memory 222192 kb
Host smart-5137b01b-d35f-425f-a728-e377613bc6a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401455626 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_intr_smoke.401455626
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.1645242333
Short name T384
Test name
Test status
Simulation time 4186269021 ps
CPU time 1.99 seconds
Started Apr 28 12:59:14 PM PDT 24
Finished Apr 28 12:59:18 PM PDT 24
Peak memory 204232 kb
Host smart-cf380b15-a954-4062-96e4-687a2fca313a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645242333 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.1645242333
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.1704896134
Short name T399
Test name
Test status
Simulation time 1367358240 ps
CPU time 51.67 seconds
Started Apr 28 12:59:11 PM PDT 24
Finished Apr 28 01:00:07 PM PDT 24
Peak memory 204140 kb
Host smart-ebcc05c3-f038-4601-99f3-32257c8a0166
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704896134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.1704896134
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.3651401431
Short name T1256
Test name
Test status
Simulation time 1225581266 ps
CPU time 46.71 seconds
Started Apr 28 12:59:04 PM PDT 24
Finished Apr 28 12:59:53 PM PDT 24
Peak memory 204764 kb
Host smart-3befa8c6-2190-4ca7-a6e5-e322ba59113c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651401431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.3651401431
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.730155412
Short name T741
Test name
Test status
Simulation time 30428384648 ps
CPU time 11.13 seconds
Started Apr 28 12:59:19 PM PDT 24
Finished Apr 28 12:59:31 PM PDT 24
Peak memory 334772 kb
Host smart-88084f89-d27a-44bc-9686-c79575e0811f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730155412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_wr.730155412
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.3039337448
Short name T1235
Test name
Test status
Simulation time 16963239008 ps
CPU time 2676.78 seconds
Started Apr 28 12:59:09 PM PDT 24
Finished Apr 28 01:43:49 PM PDT 24
Peak memory 4069412 kb
Host smart-e0c1396c-2c97-4cf8-b9e5-999a646e097d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039337448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.3039337448
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1194966219
Short name T497
Test name
Test status
Simulation time 5507666069 ps
CPU time 6.89 seconds
Started Apr 28 12:59:13 PM PDT 24
Finished Apr 28 12:59:23 PM PDT 24
Peak memory 220088 kb
Host smart-4771eae2-a708-42c3-b6a6-a67477cb4ac3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194966219 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1194966219
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.1621453017
Short name T380
Test name
Test status
Simulation time 38666085 ps
CPU time 0.62 seconds
Started Apr 28 12:59:22 PM PDT 24
Finished Apr 28 12:59:24 PM PDT 24
Peak memory 203888 kb
Host smart-ffe1d9fc-487d-4003-8d07-cea376ca5238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621453017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.1621453017
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.3659122123
Short name T275
Test name
Test status
Simulation time 282970951 ps
CPU time 1.66 seconds
Started Apr 28 12:59:12 PM PDT 24
Finished Apr 28 12:59:17 PM PDT 24
Peak memory 212364 kb
Host smart-42f87dc2-d93a-4287-b770-c25191576394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659122123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.3659122123
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.410370597
Short name T329
Test name
Test status
Simulation time 246314841 ps
CPU time 5.12 seconds
Started Apr 28 12:59:08 PM PDT 24
Finished Apr 28 12:59:17 PM PDT 24
Peak memory 234396 kb
Host smart-f850889a-2892-42c0-979d-bfcb8d154d83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410370597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty
.410370597
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.793604645
Short name T1342
Test name
Test status
Simulation time 1532663958 ps
CPU time 35.1 seconds
Started Apr 28 12:59:30 PM PDT 24
Finished Apr 28 01:00:05 PM PDT 24
Peak memory 213736 kb
Host smart-39e1c6b6-e4ff-4246-a3b6-f1cf6b4af7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793604645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.793604645
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.1495147444
Short name T1360
Test name
Test status
Simulation time 2931530963 ps
CPU time 96.75 seconds
Started Apr 28 12:59:31 PM PDT 24
Finished Apr 28 01:01:08 PM PDT 24
Peak memory 536292 kb
Host smart-5c80fbf6-6740-4b2c-aa52-c40bce065ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495147444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.1495147444
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.3768882937
Short name T703
Test name
Test status
Simulation time 99096924 ps
CPU time 0.88 seconds
Started Apr 28 12:59:07 PM PDT 24
Finished Apr 28 12:59:10 PM PDT 24
Peak memory 204016 kb
Host smart-8a19ec2d-2add-4bdc-9f01-d5cebfe7eebd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768882937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.3768882937
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.614473150
Short name T799
Test name
Test status
Simulation time 132354116 ps
CPU time 3.76 seconds
Started Apr 28 12:59:12 PM PDT 24
Finished Apr 28 12:59:19 PM PDT 24
Peak memory 223564 kb
Host smart-8dc7e966-4927-4080-b2f4-2fdc1a314351
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614473150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.614473150
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.1188409960
Short name T997
Test name
Test status
Simulation time 50375169996 ps
CPU time 292.19 seconds
Started Apr 28 12:59:08 PM PDT 24
Finished Apr 28 01:04:03 PM PDT 24
Peak memory 1125436 kb
Host smart-24cb5b41-c230-4085-977b-210b59c37b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188409960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.1188409960
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.3561997698
Short name T993
Test name
Test status
Simulation time 827555030 ps
CPU time 3.33 seconds
Started Apr 28 12:59:19 PM PDT 24
Finished Apr 28 12:59:23 PM PDT 24
Peak memory 204188 kb
Host smart-ec47b68b-758b-4521-9683-a96c35390c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561997698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.3561997698
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.2924719466
Short name T427
Test name
Test status
Simulation time 2410931698 ps
CPU time 78.46 seconds
Started Apr 28 12:59:26 PM PDT 24
Finished Apr 28 01:00:44 PM PDT 24
Peak memory 333496 kb
Host smart-30152328-e2ad-487c-84f0-19bd404f845d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924719466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.2924719466
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.955218473
Short name T986
Test name
Test status
Simulation time 51379528 ps
CPU time 0.6 seconds
Started Apr 28 12:59:12 PM PDT 24
Finished Apr 28 12:59:16 PM PDT 24
Peak memory 203836 kb
Host smart-3d7bdafe-0071-41d5-b52c-1edd0c370437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955218473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.955218473
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1276482677
Short name T370
Test name
Test status
Simulation time 4941181770 ps
CPU time 194.49 seconds
Started Apr 28 12:59:12 PM PDT 24
Finished Apr 28 01:02:30 PM PDT 24
Peak memory 228692 kb
Host smart-ccd1847d-941b-4c6a-ae82-2e8d293a2ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276482677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1276482677
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.1352632911
Short name T890
Test name
Test status
Simulation time 2528235947 ps
CPU time 17.22 seconds
Started Apr 28 12:59:24 PM PDT 24
Finished Apr 28 12:59:42 PM PDT 24
Peak memory 293364 kb
Host smart-ff2b7999-64e4-44c1-b41f-4546fd4d6468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352632911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.1352632911
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.1969950478
Short name T1096
Test name
Test status
Simulation time 58938530503 ps
CPU time 432.94 seconds
Started Apr 28 12:59:14 PM PDT 24
Finished Apr 28 01:06:29 PM PDT 24
Peak memory 2361344 kb
Host smart-cd968a73-cf72-4ab9-a1de-dfce29d4817d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969950478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.1969950478
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.3744306960
Short name T994
Test name
Test status
Simulation time 403087982 ps
CPU time 17.72 seconds
Started Apr 28 12:59:13 PM PDT 24
Finished Apr 28 12:59:34 PM PDT 24
Peak memory 212388 kb
Host smart-742382f3-d09b-46fd-9b5e-1b51c5a109d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744306960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.3744306960
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.2058087215
Short name T1361
Test name
Test status
Simulation time 3558626546 ps
CPU time 2.55 seconds
Started Apr 28 12:59:16 PM PDT 24
Finished Apr 28 12:59:20 PM PDT 24
Peak memory 204312 kb
Host smart-b02b5b74-24af-4a72-917a-bf5d4b979a72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058087215 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.2058087215
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.60027232
Short name T849
Test name
Test status
Simulation time 10102554384 ps
CPU time 13.49 seconds
Started Apr 28 12:59:14 PM PDT 24
Finished Apr 28 12:59:30 PM PDT 24
Peak memory 257576 kb
Host smart-a123682d-3bbb-4ba0-9a5c-e03726d251fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60027232 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.i2c_target_fifo_reset_acq.60027232
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2460729056
Short name T1237
Test name
Test status
Simulation time 10092493045 ps
CPU time 19.47 seconds
Started Apr 28 12:59:20 PM PDT 24
Finished Apr 28 12:59:40 PM PDT 24
Peak memory 293268 kb
Host smart-925e0e5d-159f-4d67-ab7b-323e4c2116eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460729056 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2460729056
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.298264617
Short name T723
Test name
Test status
Simulation time 660436026 ps
CPU time 2.27 seconds
Started Apr 28 12:59:17 PM PDT 24
Finished Apr 28 12:59:20 PM PDT 24
Peak memory 204144 kb
Host smart-86c1c338-9a80-4368-bfde-e5e40853168e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298264617 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.i2c_target_hrst.298264617
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.3390577577
Short name T1294
Test name
Test status
Simulation time 1065708767 ps
CPU time 4.84 seconds
Started Apr 28 12:59:14 PM PDT 24
Finished Apr 28 12:59:21 PM PDT 24
Peak memory 209076 kb
Host smart-e170022d-c599-40c7-964e-c9a437a34ccd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390577577 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.3390577577
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.1558151839
Short name T863
Test name
Test status
Simulation time 23422029970 ps
CPU time 189.84 seconds
Started Apr 28 12:59:15 PM PDT 24
Finished Apr 28 01:02:26 PM PDT 24
Peak memory 2810956 kb
Host smart-7de2f0ef-31b8-4731-9ceb-c15d778506d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558151839 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.1558151839
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.493585519
Short name T918
Test name
Test status
Simulation time 1649738352 ps
CPU time 27.66 seconds
Started Apr 28 12:59:14 PM PDT 24
Finished Apr 28 12:59:44 PM PDT 24
Peak memory 204132 kb
Host smart-21ad0714-e784-47d7-9c96-7d111a101aa3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493585519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_targ
et_smoke.493585519
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.957129144
Short name T580
Test name
Test status
Simulation time 768970286 ps
CPU time 29.08 seconds
Started Apr 28 12:59:25 PM PDT 24
Finished Apr 28 12:59:54 PM PDT 24
Peak memory 204124 kb
Host smart-7116d87f-095e-42c0-b940-2af04baf8119
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957129144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_rd.957129144
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.4000826684
Short name T490
Test name
Test status
Simulation time 61422835651 ps
CPU time 245.83 seconds
Started Apr 28 12:59:13 PM PDT 24
Finished Apr 28 01:03:22 PM PDT 24
Peak memory 2582596 kb
Host smart-ea6985b7-c951-4ad7-9767-24c5f028b6dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000826684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.4000826684
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.4230031596
Short name T1317
Test name
Test status
Simulation time 29032047673 ps
CPU time 164.04 seconds
Started Apr 28 12:59:23 PM PDT 24
Finished Apr 28 01:02:08 PM PDT 24
Peak memory 1662472 kb
Host smart-87861e07-ebd9-4d41-a1dd-93a53a3905d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230031596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.4230031596
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.3950215176
Short name T1180
Test name
Test status
Simulation time 2703165066 ps
CPU time 7.14 seconds
Started Apr 28 12:59:14 PM PDT 24
Finished Apr 28 12:59:23 PM PDT 24
Peak memory 220484 kb
Host smart-45aef8c8-cb3f-458b-9293-b72f8c816854
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950215176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.3950215176
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.2819360356
Short name T1299
Test name
Test status
Simulation time 18784852 ps
CPU time 0.65 seconds
Started Apr 28 12:59:25 PM PDT 24
Finished Apr 28 12:59:26 PM PDT 24
Peak memory 203912 kb
Host smart-aced3479-91d6-4803-802f-54b7c23806a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819360356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.2819360356
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.3614981079
Short name T474
Test name
Test status
Simulation time 54187856 ps
CPU time 1.5 seconds
Started Apr 28 12:59:17 PM PDT 24
Finished Apr 28 12:59:19 PM PDT 24
Peak memory 212380 kb
Host smart-df7f5b8b-b44d-41ee-8a7f-ff020969f4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614981079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3614981079
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.1934950101
Short name T714
Test name
Test status
Simulation time 487249045 ps
CPU time 5.6 seconds
Started Apr 28 12:59:34 PM PDT 24
Finished Apr 28 12:59:40 PM PDT 24
Peak memory 254156 kb
Host smart-f5203cc1-7fed-4828-929e-ce9cf32ab7fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934950101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.1934950101
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.355849660
Short name T1131
Test name
Test status
Simulation time 9298354702 ps
CPU time 85.63 seconds
Started Apr 28 12:59:37 PM PDT 24
Finished Apr 28 01:01:03 PM PDT 24
Peak memory 485788 kb
Host smart-e4c6fde8-a502-439c-8ed4-0dd06e99b12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355849660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.355849660
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.613533277
Short name T1275
Test name
Test status
Simulation time 2118066567 ps
CPU time 159.28 seconds
Started Apr 28 12:59:25 PM PDT 24
Finished Apr 28 01:02:05 PM PDT 24
Peak memory 728580 kb
Host smart-caf1c714-3f55-4fff-98ec-dd266e9ca918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613533277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.613533277
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.436854653
Short name T743
Test name
Test status
Simulation time 250824610 ps
CPU time 1.07 seconds
Started Apr 28 12:59:36 PM PDT 24
Finished Apr 28 12:59:37 PM PDT 24
Peak memory 204080 kb
Host smart-ce268cc0-2bc3-45d3-8e62-44e81edef1cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436854653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt
.436854653
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2158170648
Short name T477
Test name
Test status
Simulation time 216807982 ps
CPU time 5.71 seconds
Started Apr 28 12:59:29 PM PDT 24
Finished Apr 28 12:59:35 PM PDT 24
Peak memory 242712 kb
Host smart-01850d88-52a8-463a-876a-0391bf383dda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158170648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
2158170648
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.1092958561
Short name T1132
Test name
Test status
Simulation time 25108485445 ps
CPU time 65.61 seconds
Started Apr 28 12:59:23 PM PDT 24
Finished Apr 28 01:00:29 PM PDT 24
Peak memory 890728 kb
Host smart-5390e6ad-3c42-4568-912c-b19044d81b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092958561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1092958561
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.1782968093
Short name T71
Test name
Test status
Simulation time 659172227 ps
CPU time 4.11 seconds
Started Apr 28 12:59:23 PM PDT 24
Finished Apr 28 12:59:28 PM PDT 24
Peak memory 204116 kb
Host smart-30982270-a454-477c-80b4-3c98331b8339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782968093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.1782968093
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.583514966
Short name T338
Test name
Test status
Simulation time 3167559491 ps
CPU time 32.78 seconds
Started Apr 28 12:59:38 PM PDT 24
Finished Apr 28 01:00:12 PM PDT 24
Peak memory 355776 kb
Host smart-8dbd8d1e-47c1-4d42-adbc-7ad197eec775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583514966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.583514966
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.26865008
Short name T212
Test name
Test status
Simulation time 52071998 ps
CPU time 0.63 seconds
Started Apr 28 12:59:31 PM PDT 24
Finished Apr 28 12:59:33 PM PDT 24
Peak memory 203836 kb
Host smart-bc5bd128-0061-43b6-93d4-bad55ca7a985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26865008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.26865008
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.1893900673
Short name T888
Test name
Test status
Simulation time 7081581070 ps
CPU time 69.5 seconds
Started Apr 28 12:59:28 PM PDT 24
Finished Apr 28 01:00:38 PM PDT 24
Peak memory 245660 kb
Host smart-12658f78-521e-4eaa-95ba-5d385eeb783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893900673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.1893900673
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.2082120477
Short name T644
Test name
Test status
Simulation time 5010904521 ps
CPU time 26.83 seconds
Started Apr 28 12:59:22 PM PDT 24
Finished Apr 28 12:59:50 PM PDT 24
Peak memory 380720 kb
Host smart-efa06a10-6785-4291-a0a9-2aa72353e2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082120477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2082120477
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.3831204860
Short name T656
Test name
Test status
Simulation time 777078717 ps
CPU time 33.44 seconds
Started Apr 28 12:59:19 PM PDT 24
Finished Apr 28 12:59:54 PM PDT 24
Peak memory 212220 kb
Host smart-6234d1c2-0faf-48fe-bf76-2c7a12268ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831204860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.3831204860
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.2245883586
Short name T519
Test name
Test status
Simulation time 1632419628 ps
CPU time 3.11 seconds
Started Apr 28 12:59:22 PM PDT 24
Finished Apr 28 12:59:26 PM PDT 24
Peak memory 204012 kb
Host smart-b342ae61-1a1f-4139-ad2f-2f207954f58f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245883586 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2245883586
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.896064680
Short name T1238
Test name
Test status
Simulation time 10056522059 ps
CPU time 75.52 seconds
Started Apr 28 12:59:33 PM PDT 24
Finished Apr 28 01:00:49 PM PDT 24
Peak memory 447300 kb
Host smart-6a0777c9-489f-4bf6-9459-67622425f531
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896064680 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_acq.896064680
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.2734576389
Short name T548
Test name
Test status
Simulation time 10297276676 ps
CPU time 13.48 seconds
Started Apr 28 12:59:35 PM PDT 24
Finished Apr 28 12:59:48 PM PDT 24
Peak memory 279124 kb
Host smart-f2bcd870-03be-4e9f-89cb-004df0863b60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734576389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.2734576389
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.2755354479
Short name T654
Test name
Test status
Simulation time 1183623630 ps
CPU time 2.02 seconds
Started Apr 28 12:59:19 PM PDT 24
Finished Apr 28 12:59:22 PM PDT 24
Peak memory 204204 kb
Host smart-969fe238-86a9-4c6d-aebc-6a1f3984980f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755354479 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.2755354479
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.3832773997
Short name T1036
Test name
Test status
Simulation time 3396720137 ps
CPU time 3.94 seconds
Started Apr 28 12:59:15 PM PDT 24
Finished Apr 28 12:59:21 PM PDT 24
Peak memory 204180 kb
Host smart-5e6233b1-3f69-44d9-8f44-d0dd5574edae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832773997 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.3832773997
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.2173223474
Short name T746
Test name
Test status
Simulation time 13712823380 ps
CPU time 101.18 seconds
Started Apr 28 12:59:19 PM PDT 24
Finished Apr 28 01:01:01 PM PDT 24
Peak memory 1736032 kb
Host smart-ff9ce51d-4c0e-434e-a1df-3920ca8f2a84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173223474 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.2173223474
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.2435706719
Short name T1056
Test name
Test status
Simulation time 13651039773 ps
CPU time 14.18 seconds
Started Apr 28 12:59:20 PM PDT 24
Finished Apr 28 12:59:34 PM PDT 24
Peak memory 204104 kb
Host smart-6cfb6329-5195-4617-8c53-3cfdb622cfda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435706719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.2435706719
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.1358852996
Short name T661
Test name
Test status
Simulation time 7123293366 ps
CPU time 9.6 seconds
Started Apr 28 12:59:22 PM PDT 24
Finished Apr 28 12:59:32 PM PDT 24
Peak memory 207164 kb
Host smart-ecb3553f-7390-44af-93fa-dc3941628d13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358852996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.1358852996
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.1854842355
Short name T1185
Test name
Test status
Simulation time 27079244086 ps
CPU time 87.05 seconds
Started Apr 28 12:59:32 PM PDT 24
Finished Apr 28 01:00:59 PM PDT 24
Peak memory 1403132 kb
Host smart-ea691668-cb5e-4c74-8d7d-a2aa37517b09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854842355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.1854842355
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.646006499
Short name T655
Test name
Test status
Simulation time 18164449208 ps
CPU time 100.33 seconds
Started Apr 28 12:59:28 PM PDT 24
Finished Apr 28 01:01:09 PM PDT 24
Peak memory 1109508 kb
Host smart-cefa9e9e-1ca8-48e2-bb49-ea621ab2867b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646006499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_ta
rget_stretch.646006499
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.2349065095
Short name T341
Test name
Test status
Simulation time 4955814475 ps
CPU time 5.87 seconds
Started Apr 28 12:59:21 PM PDT 24
Finished Apr 28 12:59:27 PM PDT 24
Peak memory 212376 kb
Host smart-f6f11705-be53-4294-b197-aeecff283854
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349065095 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.2349065095
Directory /workspace/9.i2c_target_timeout/latest
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