Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.41	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	6	54	90.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	6	54	90.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	801462	1			T1	2		T2	1974		T3	2
all_values[1]	801462	1			T1	2		T2	1974		T3	2
all_values[2]	801462	1			T1	2		T2	1974		T3	2
all_values[3]	801462	1			T1	2		T2	1974		T3	2
all_values[4]	801462	1			T1	2		T2	1974		T3	2
all_values[5]	801462	1			T1	2		T2	1974		T3	2
all_values[6]	801462	1			T1	2		T2	1974		T3	2
all_values[7]	801462	1			T1	2		T2	1974		T3	2
all_values[8]	801462	1			T1	2		T2	1974		T3	2
all_values[9]	801462	1			T1	2		T2	1974		T3	2
all_values[10]	801462	1			T1	2		T2	1974		T3	2
all_values[11]	801462	1			T1	2		T2	1974		T3	2
all_values[12]	801462	1			T1	2		T2	1974		T3	2
all_values[13]	801462	1			T1	2		T2	1974		T3	2
all_values[14]	801462	1			T1	2		T2	1974		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8627755

1

T1

26

T2

25776

T3

26

auto[1]

3394175

1

T1

4

T2

3834

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10540374

1

T1

30

T2

29610

T3

30

auto[1]

1481556

1

T55

946

T65

2325

T46

23295

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	6	54	90.00	6

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[14]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	87689	1			T2	716		T4	3		T7	62
all_values[0]	auto[0]	auto[1]	19844	1			T55	20		T65	9		T46	148
all_values[0]	auto[1]	auto[0]	609726	1			T1	2		T2	1258		T3	2
all_values[0]	auto[1]	auto[1]	84203	1			T55	44		T65	147		T46	1405
all_values[1]	auto[0]	auto[0]	704491	1			T1	2		T2	1974		T3	2
all_values[1]	auto[0]	auto[1]	96440	1			T55	60		T65	153		T46	1551
all_values[1]	auto[1]	auto[0]	281	1			T59	11		T214	44		T215	2
all_values[1]	auto[1]	auto[1]	250	1			T55	5		T65	1		T46	3
all_values[2]	auto[0]	auto[0]	704453	1			T1	2		T2	1974		T3	2
all_values[2]	auto[0]	auto[1]	96785	1			T55	54		T65	152		T46	1550
all_values[2]	auto[1]	auto[1]	224	1			T55	10		T65	3		T46	2
all_values[3]	auto[0]	auto[0]	710933	1			T1	2		T2	1974		T3	2
all_values[3]	auto[0]	auto[1]	90320	1			T55	56		T65	154		T46	1549
all_values[3]	auto[1]	auto[1]	209	1			T55	8		T65	1		T46	5
all_values[4]	auto[0]	auto[0]	709516	1			T1	2		T2	1974		T3	2
all_values[4]	auto[0]	auto[1]	91703	1			T55	58		T65	151		T46	1550
all_values[4]	auto[1]	auto[0]	27	1			T9	1		T69	1		T216	1
all_values[4]	auto[1]	auto[1]	216	1			T55	7		T65	4		T46	3
all_values[5]	auto[0]	auto[0]	699296	1			T1	2		T2	1974		T3	2
all_values[5]	auto[0]	auto[1]	101906	1			T55	54		T65	154		T46	1550
all_values[5]	auto[1]	auto[1]	260	1			T55	10		T65	2		T46	4
all_values[6]	auto[0]	auto[0]	170679	1			T1	2		T2	1973		T3	2
all_values[6]	auto[0]	auto[1]	17967	1			T55	53		T65	151		T46	1537
all_values[6]	auto[1]	auto[0]	533586	1			T2	1		T4	1		T7	14535
all_values[6]	auto[1]	auto[1]	79230	1			T55	11		T65	4		T46	16
all_values[7]	auto[0]	auto[0]	672435	1			T1	2		T2	1511		T3	2
all_values[7]	auto[0]	auto[1]	98700	1			T55	43		T65	72		T46	1198
all_values[7]	auto[1]	auto[0]	24985	1			T2	463		T7	145		T8	162
all_values[7]	auto[1]	auto[1]	5342	1			T55	17		T65	83		T46	354
all_values[8]	auto[0]	auto[0]	139428	1			T1	2		T2	1837		T3	2
all_values[8]	auto[0]	auto[1]	20243	1			T55	47		T65	101		T46	1501
all_values[8]	auto[1]	auto[0]	557995	1			T2	137		T7	14699		T8	8984
all_values[8]	auto[1]	auto[1]	83796	1			T55	17		T65	54		T46	51
all_values[9]	auto[0]	auto[0]	163201	1			T1	2		T2	1971		T3	2
all_values[9]	auto[0]	auto[1]	23458	1			T55	50		T65	148		T46	1532
all_values[9]	auto[1]	auto[0]	534218	1			T2	3		T6	1		T7	14549
all_values[9]	auto[1]	auto[1]	80585	1			T55	14		T65	7		T46	20
all_values[10]	auto[0]	auto[0]	708351	1			T1	2		T2	1974		T3	2
all_values[10]	auto[0]	auto[1]	92892	1			T55	59		T65	151		T46	1549
all_values[10]	auto[1]	auto[1]	219	1			T55	6		T65	4		T46	3
all_values[11]	auto[0]	auto[0]	2908	1			T2	2		T4	3		T7	9
all_values[11]	auto[0]	auto[1]	485	1			T55	19		T65	7		T46	5
all_values[11]	auto[1]	auto[0]	706648	1			T1	2		T2	1972		T3	2
all_values[11]	auto[1]	auto[1]	91421	1			T55	46		T65	149		T46	1549
all_values[12]	auto[0]	auto[0]	697666	1			T1	2		T2	1974		T3	2
all_values[12]	auto[0]	auto[1]	103567	1			T55	57		T65	153		T46	1550
all_values[12]	auto[1]	auto[1]	229	1			T55	8		T65	3		T46	2
all_values[13]	auto[0]	auto[0]	704216	1			T1	2		T2	1974		T3	2
all_values[13]	auto[0]	auto[1]	97010	1			T55	45		T65	153		T46	1547
all_values[13]	auto[1]	auto[0]	1	1			T217	1		-	-		-	-
all_values[13]	auto[1]	auto[1]	235	1			T55	3		T65	3		T46	7
all_values[14]	auto[0]	auto[0]	697645	1			T1	2		T2	1974		T3	2
all_values[14]	auto[0]	auto[1]	103528	1			T55	52		T65	151		T46	1549
all_values[14]	auto[1]	auto[1]	289	1			T55	13		T46	5		T47	1