Summary for Variable cp_acq_overflow
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for cp_acq_overflow
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3581 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_acq_threshold
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_acq_threshold
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3577 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
4 |
1 |
|
|
T33 |
1 |
|
T206 |
1 |
|
T207 |
2 |
Summary for Variable cp_acqrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_acqrst
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1040 |
1 |
|
|
T4 |
16 |
|
T39 |
2 |
|
T79 |
2 |
auto[1] |
2541 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_fmt_threshold
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_fmt_threshold
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
2920 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
661 |
1 |
|
|
T6 |
5 |
|
T39 |
2 |
|
T79 |
2 |
Summary for Variable cp_fmtrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_fmtrst
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
922 |
1 |
|
|
T4 |
8 |
|
T6 |
5 |
|
T39 |
2 |
auto[1] |
2659 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_rx_overflow
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for cp_rx_overflow
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3581 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_rx_threshold
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_rx_threshold
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3554 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
27 |
1 |
|
|
T39 |
1 |
|
T79 |
1 |
|
T208 |
1 |
Summary for Variable cp_rxrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_rxrst
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1263 |
1 |
|
|
T4 |
16 |
|
T6 |
5 |
|
T39 |
1 |
auto[1] |
2318 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_tx_threshold
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_tx_threshold
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3124 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
457 |
1 |
|
|
T6 |
5 |
|
T39 |
2 |
|
T79 |
2 |
Summary for Variable cp_txrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_txrst
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1040 |
1 |
|
|
T4 |
16 |
|
T6 |
5 |
|
T39 |
2 |
auto[1] |
2541 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Cross cp_fmt_threshold_cross
Samples crossed: cp_fmt_threshold cp_fmtrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_fmt_threshold_cross
Bins
cp_fmt_threshold | cp_fmtrst | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
368 |
1 |
|
|
T4 |
8 |
|
T73 |
7 |
|
T74 |
9 |
auto[0] |
auto[1] |
2552 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
auto[0] |
554 |
1 |
|
|
T6 |
5 |
|
T39 |
2 |
|
T79 |
2 |
auto[1] |
auto[1] |
107 |
1 |
|
|
T68 |
2 |
|
T55 |
1 |
|
T59 |
3 |
Summary for Cross cp_rx_threshold_cross
Samples crossed: cp_rx_threshold cp_rxrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
1 |
3 |
75.00 |
1 |
Automatically Generated Cross Bins for cp_rx_threshold_cross
Uncovered bins
cp_rx_threshold | cp_rxrst | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
cp_rx_threshold | cp_rxrst | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
1263 |
1 |
|
|
T4 |
16 |
|
T6 |
5 |
|
T39 |
1 |
auto[0] |
auto[1] |
2291 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
auto[1] |
27 |
1 |
|
|
T39 |
1 |
|
T79 |
1 |
|
T208 |
1 |
Summary for Cross cp_acq_threshold_cross
Samples crossed: cp_acq_threshold cp_fmtrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
1 |
3 |
75.00 |
1 |
Automatically Generated Cross Bins for cp_acq_threshold_cross
Uncovered bins
cp_acq_threshold | cp_fmtrst | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
cp_acq_threshold | cp_fmtrst | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
918 |
1 |
|
|
T4 |
8 |
|
T6 |
5 |
|
T39 |
2 |
auto[0] |
auto[1] |
2659 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
auto[0] |
4 |
1 |
|
|
T33 |
1 |
|
T206 |
1 |
|
T207 |
2 |
Summary for Cross cp_rx_overflow_cross
Samples crossed: cp_rx_overflow cp_rxrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
2 |
2 |
50.00 |
2 |
Automatically Generated Cross Bins for cp_rx_overflow_cross
Element holes
cp_rx_overflow | cp_rxrst | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
* |
-- |
-- |
2 |
|
Covered bins
cp_rx_overflow | cp_rxrst | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
1263 |
1 |
|
|
T4 |
16 |
|
T6 |
5 |
|
T39 |
1 |
auto[0] |
auto[1] |
2318 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Cross cp_acq_overflow_cross
Samples crossed: cp_acq_overflow cp_acqrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
2 |
2 |
50.00 |
2 |
Automatically Generated Cross Bins for cp_acq_overflow_cross
Element holes
cp_acq_overflow | cp_acqrst | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
* |
-- |
-- |
2 |
|
Covered bins
cp_acq_overflow | cp_acqrst | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
1040 |
1 |
|
|
T4 |
16 |
|
T39 |
2 |
|
T79 |
2 |
auto[0] |
auto[1] |
2541 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Cross cp_tx_threshold_cross
Samples crossed: cp_tx_threshold cp_txrst
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_tx_threshold_cross
Bins
cp_tx_threshold | cp_txrst | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
841 |
1 |
|
|
T4 |
16 |
|
T52 |
4 |
|
T56 |
4 |
auto[0] |
auto[1] |
2283 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
auto[1] |
auto[0] |
199 |
1 |
|
|
T6 |
5 |
|
T39 |
2 |
|
T79 |
2 |
auto[1] |
auto[1] |
258 |
1 |
|
|
T33 |
3 |
|
T34 |
5 |
|
T68 |
2 |