Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	801462	1			T1	2		T2	1974		T3	2
all_pins[1]	801462	1			T1	2		T2	1974		T3	2
all_pins[2]	801462	1			T1	2		T2	1974		T3	2
all_pins[3]	801462	1			T1	2		T2	1974		T3	2
all_pins[4]	801462	1			T1	2		T2	1974		T3	2
all_pins[5]	801462	1			T1	2		T2	1974		T3	2
all_pins[6]	801462	1			T1	2		T2	1974		T3	2
all_pins[7]	801462	1			T1	2		T2	1974		T3	2
all_pins[8]	801462	1			T1	2		T2	1974		T3	2
all_pins[9]	801462	1			T1	2		T2	1974		T3	2
all_pins[10]	801462	1			T1	2		T2	1974		T3	2
all_pins[11]	801462	1			T1	2		T2	1974		T3	2
all_pins[12]	801462	1			T1	2		T2	1974		T3	2
all_pins[13]	801462	1			T1	2		T2	1974		T3	2
all_pins[14]	801462	1			T1	2		T2	1974		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8632758	1			T1	26		T2	25751		T3	26
values[0x1]	3389172	1			T1	4		T2	3859		T3	4
transitions[0x0=>0x1]	2734700	1			T1	4		T2	3806		T3	4
transitions[0x1=>0x0]	2733672	1			T1	3		T2	3805		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	110640	1			T2	716		T4	3		T7	63
all_pins[0]	values[0x1]	690822	1			T1	2		T2	1258		T3	2
all_pins[0]	transitions[0x0=>0x1]	690412	1			T1	2		T2	1258		T3	2
all_pins[0]	transitions[0x1=>0x0]	79	1			T55	3		T46	2		T47	2
all_pins[1]	values[0x0]	800973	1			T1	2		T2	1974		T3	2
all_pins[1]	values[0x1]	489	1			T55	4		T59	14		T214	56
all_pins[1]	transitions[0x0=>0x1]	467	1			T55	4		T59	14		T214	56
all_pins[1]	transitions[0x1=>0x0]	87	1			T55	5		T65	2		T46	1
all_pins[2]	values[0x0]	801353	1			T1	2		T2	1974		T3	2
all_pins[2]	values[0x1]	109	1			T55	5		T65	2		T46	2
all_pins[2]	transitions[0x0=>0x1]	84	1			T55	3		T65	2		T46	1
all_pins[2]	transitions[0x1=>0x0]	78	1			T55	3		T65	1		T168	1
all_pins[3]	values[0x0]	801359	1			T1	2		T2	1974		T3	2
all_pins[3]	values[0x1]	103	1			T55	5		T65	1		T46	1
all_pins[3]	transitions[0x0=>0x1]	85	1			T55	4		T46	1		T168	1
all_pins[3]	transitions[0x1=>0x0]	133	1			T9	1		T55	3		T69	1
all_pins[4]	values[0x0]	801311	1			T1	2		T2	1974		T3	2
all_pins[4]	values[0x1]	151	1			T9	1		T55	4		T69	1
all_pins[4]	transitions[0x0=>0x1]	124	1			T9	1		T55	2		T69	1
all_pins[4]	transitions[0x1=>0x0]	101	1			T55	5		T65	1		T46	2
all_pins[5]	values[0x0]	801334	1			T1	2		T2	1974		T3	2
all_pins[5]	values[0x1]	128	1			T55	7		T65	1		T46	3
all_pins[5]	transitions[0x0=>0x1]	95	1			T55	5		T65	1		T46	3
all_pins[5]	transitions[0x1=>0x0]	612410	1			T2	1		T4	1		T7	14535
all_pins[6]	values[0x0]	189019	1			T1	2		T2	1973		T3	2
all_pins[6]	values[0x1]	612443	1			T2	1		T4	1		T7	14535
all_pins[6]	transitions[0x0=>0x1]	593296	1			T2	1		T4	1		T7	14363
all_pins[6]	transitions[0x1=>0x0]	14332	1			T2	486		T7	6		T40	55
all_pins[7]	values[0x0]	767983	1			T1	2		T2	1488		T3	2
all_pins[7]	values[0x1]	33479	1			T2	486		T7	178		T8	194
all_pins[7]	transitions[0x0=>0x1]	11443	1			T2	433		T40	49		T99	70
all_pins[7]	transitions[0x1=>0x0]	619498	1			T2	86		T7	14521		T8	8791
all_pins[8]	values[0x0]	159928	1			T1	2		T2	1835		T3	2
all_pins[8]	values[0x1]	641534	1			T2	139		T7	14699		T8	8985
all_pins[8]	transitions[0x0=>0x1]	28998	1			T2	139		T7	150		T8	962
all_pins[8]	transitions[0x1=>0x0]	2183	1			T2	3		T6	1		T9	3
all_pins[9]	values[0x0]	186743	1			T1	2		T2	1971		T3	2
all_pins[9]	values[0x1]	614719	1			T2	3		T6	1		T7	14549
all_pins[9]	transitions[0x0=>0x1]	614688	1			T2	3		T6	1		T7	14549
all_pins[9]	transitions[0x1=>0x0]	85	1			T55	1		T47	2		T249	1
all_pins[10]	values[0x0]	801346	1			T1	2		T2	1974		T3	2
all_pins[10]	values[0x1]	116	1			T55	1		T47	3		T48	2
all_pins[10]	transitions[0x0=>0x1]	75	1			T55	1		T47	1		T48	2
all_pins[10]	transitions[0x1=>0x0]	794667	1			T1	2		T2	1972		T3	2
all_pins[11]	values[0x0]	6754	1			T2	2		T4	3		T7	9
all_pins[11]	values[0x1]	794708	1			T1	2		T2	1972		T3	2
all_pins[11]	transitions[0x0=>0x1]	794672	1			T1	2		T2	1972		T3	2
all_pins[11]	transitions[0x1=>0x0]	80	1			T55	3		T65	2		T47	1
all_pins[12]	values[0x0]	801346	1			T1	2		T2	1974		T3	2
all_pins[12]	values[0x1]	116	1			T55	3		T65	2		T47	1
all_pins[12]	transitions[0x0=>0x1]	86	1			T55	2		T65	1		T47	1
all_pins[12]	transitions[0x1=>0x0]	88	1			T55	2		T65	1		T46	2
all_pins[13]	values[0x0]	801344	1			T1	2		T2	1974		T3	2
all_pins[13]	values[0x1]	118	1			T55	3		T65	2		T46	2
all_pins[13]	transitions[0x0=>0x1]	91	1			T55	3		T65	2		T46	2
all_pins[13]	transitions[0x1=>0x0]	110	1			T55	8		T48	4		T250	3
all_pins[14]	values[0x0]	801325	1			T1	2		T2	1974		T3	2
all_pins[14]	values[0x1]	137	1			T55	8		T48	5		T250	3
all_pins[14]	transitions[0x0=>0x1]	84	1			T55	6		T48	3		T250	3
all_pins[14]	transitions[0x1=>0x0]	689741	1			T1	1		T2	1257		T3	1