Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	535	1			T55	18		T65	7		T46	7
all_values[1]	535	1			T55	18		T65	7		T46	7
all_values[2]	535	1			T55	18		T65	7		T46	7
all_values[3]	535	1			T55	18		T65	7		T46	7
all_values[4]	535	1			T55	18		T65	7		T46	7
all_values[5]	535	1			T55	18		T65	7		T46	7
all_values[6]	535	1			T55	18		T65	7		T46	7
all_values[7]	535	1			T55	18		T65	7		T46	7
all_values[8]	535	1			T55	18		T65	7		T46	7
all_values[9]	535	1			T55	18		T65	7		T46	7
all_values[10]	535	1			T55	18		T65	7		T46	7
all_values[11]	535	1			T55	18		T65	7		T46	7
all_values[12]	535	1			T55	18		T65	7		T46	7
all_values[13]	535	1			T55	18		T65	7		T46	7
all_values[14]	535	1			T55	18		T65	7		T46	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4244

1

T55

130

T65

60

T46

62

auto[1]

3781

1

T55

140

T65

45

T46

43

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T55

22

T65

15

T46

15

auto[1]

6872

1

T55

248

T65

90

T46

90

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4710

1

T55

163

T65

59

T46

59

auto[1]

3315

1

T55

107

T65

46

T46

46

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	39	1			T46	1		T250	1		T166	2
all_values[0]	auto[0]	auto[0]	auto[1]	128	1			T55	5		T65	1		T46	1
all_values[0]	auto[0]	auto[1]	auto[0]	30	1			T55	1		T47	1		T48	1
all_values[0]	auto[0]	auto[1]	auto[1]	117	1			T55	4		T65	2		T46	2
all_values[0]	auto[1]	auto[0]	auto[1]	105	1			T55	2		T65	1		T46	2
all_values[0]	auto[1]	auto[1]	auto[1]	116	1			T55	6		T65	3		T46	1
all_values[1]	auto[0]	auto[0]	auto[0]	46	1			T65	1		T251	1		T245	1
all_values[1]	auto[0]	auto[0]	auto[1]	133	1			T55	6		T65	3		T46	1
all_values[1]	auto[0]	auto[1]	auto[0]	25	1			T65	1		T48	1		T249	1
all_values[1]	auto[0]	auto[1]	auto[1]	115	1			T55	7		T65	1		T46	3
all_values[1]	auto[1]	auto[0]	auto[1]	121	1			T55	1		T46	1		T47	1
all_values[1]	auto[1]	auto[1]	auto[1]	95	1			T55	4		T65	1		T46	2
all_values[2]	auto[0]	auto[0]	auto[0]	28	1			T65	1		T46	1		T168	1
all_values[2]	auto[0]	auto[0]	auto[1]	123	1			T55	4		T65	1		T46	1
all_values[2]	auto[0]	auto[1]	auto[0]	46	1			T55	1		T46	1		T48	2
all_values[2]	auto[0]	auto[1]	auto[1]	114	1			T55	3		T65	2		T46	2
all_values[2]	auto[1]	auto[0]	auto[1]	117	1			T55	3		T65	1		T47	2
all_values[2]	auto[1]	auto[1]	auto[1]	107	1			T55	7		T65	2		T46	2
all_values[3]	auto[0]	auto[0]	auto[0]	52	1			T65	1		T47	4		T168	1
all_values[3]	auto[0]	auto[0]	auto[1]	125	1			T55	5		T46	3		T47	1
all_values[3]	auto[0]	auto[1]	auto[0]	37	1			T55	1		T47	1		T168	1
all_values[3]	auto[0]	auto[1]	auto[1]	113	1			T55	6		T65	4		T168	1
all_values[3]	auto[1]	auto[0]	auto[1]	110	1			T55	2		T46	3		T47	1
all_values[3]	auto[1]	auto[1]	auto[1]	98	1			T55	4		T65	2		T46	1
all_values[4]	auto[0]	auto[0]	auto[0]	49	1			T65	1		T46	1		T47	1
all_values[4]	auto[0]	auto[0]	auto[1]	105	1			T55	6		T46	1		T168	2
all_values[4]	auto[0]	auto[1]	auto[0]	34	1			T47	4		T170	3		T171	1
all_values[4]	auto[0]	auto[1]	auto[1]	131	1			T55	5		T65	2		T46	2
all_values[4]	auto[1]	auto[0]	auto[1]	114	1			T55	4		T65	1		T46	2
all_values[4]	auto[1]	auto[1]	auto[1]	102	1			T55	3		T65	3		T46	1
all_values[5]	auto[0]	auto[0]	auto[0]	53	1			T168	1		T250	1		T252	1
all_values[5]	auto[0]	auto[0]	auto[1]	130	1			T55	1		T65	2		T46	2
all_values[5]	auto[0]	auto[1]	auto[0]	30	1			T55	1		T47	1		T249	1
all_values[5]	auto[0]	auto[1]	auto[1]	108	1			T55	7		T65	1		T46	2
all_values[5]	auto[1]	auto[0]	auto[1]	114	1			T55	5		T65	3		T46	2
all_values[5]	auto[1]	auto[1]	auto[1]	100	1			T55	4		T65	1		T46	1
all_values[6]	auto[0]	auto[0]	auto[0]	50	1			T65	1		T46	1		T250	1
all_values[6]	auto[0]	auto[0]	auto[1]	129	1			T55	5		T65	3		T46	1
all_values[6]	auto[0]	auto[1]	auto[0]	29	1			T55	1		T47	3		T252	1
all_values[6]	auto[0]	auto[1]	auto[1]	108	1			T55	4		T65	1		T47	1
all_values[6]	auto[1]	auto[0]	auto[1]	113	1			T55	5		T65	2		T46	3
all_values[6]	auto[1]	auto[1]	auto[1]	106	1			T55	3		T46	2		T168	3
all_values[7]	auto[0]	auto[0]	auto[0]	41	1			T55	3		T65	1		T46	1
all_values[7]	auto[0]	auto[0]	auto[1]	117	1			T55	4		T65	1		T47	3
all_values[7]	auto[0]	auto[1]	auto[0]	27	1			T55	2		T46	1		T168	1
all_values[7]	auto[0]	auto[1]	auto[1]	128	1			T55	5		T65	1		T46	3
all_values[7]	auto[1]	auto[0]	auto[1]	118	1			T55	2		T65	3		T47	3
all_values[7]	auto[1]	auto[1]	auto[1]	104	1			T55	2		T65	1		T46	2
all_values[8]	auto[0]	auto[0]	auto[0]	39	1			T65	1		T46	2		T169	1
all_values[8]	auto[0]	auto[0]	auto[1]	117	1			T55	5		T65	2		T46	2
all_values[8]	auto[0]	auto[1]	auto[0]	32	1			T55	1		T47	1		T48	1
all_values[8]	auto[0]	auto[1]	auto[1]	124	1			T55	5		T65	1		T46	1
all_values[8]	auto[1]	auto[0]	auto[1]	118	1			T55	4		T65	2		T46	2
all_values[8]	auto[1]	auto[1]	auto[1]	105	1			T55	3		T65	1		T47	3
all_values[9]	auto[0]	auto[0]	auto[0]	50	1			T65	1		T46	2		T47	2
all_values[9]	auto[0]	auto[0]	auto[1]	107	1			T55	4		T46	1		T47	2
all_values[9]	auto[0]	auto[1]	auto[0]	20	1			T55	1		T48	1		T249	1
all_values[9]	auto[0]	auto[1]	auto[1]	137	1			T55	5		T65	3		T46	1
all_values[9]	auto[1]	auto[0]	auto[1]	110	1			T55	6		T47	1		T168	2
all_values[9]	auto[1]	auto[1]	auto[1]	111	1			T55	2		T65	3		T46	3
all_values[10]	auto[0]	auto[0]	auto[0]	54	1			T65	1		T46	2		T168	3
all_values[10]	auto[0]	auto[0]	auto[1]	121	1			T55	9		T65	2		T46	2
all_values[10]	auto[0]	auto[1]	auto[0]	41	1			T168	4		T249	2		T250	1
all_values[10]	auto[0]	auto[1]	auto[1]	100	1			T55	3		T47	1		T48	2
all_values[10]	auto[1]	auto[0]	auto[1]	104	1			T55	4		T65	4		T46	3
all_values[10]	auto[1]	auto[1]	auto[1]	115	1			T55	2		T47	2		T48	3
all_values[11]	auto[0]	auto[0]	auto[0]	58	1			T166	1		T169	5		T251	2
all_values[11]	auto[0]	auto[0]	auto[1]	118	1			T55	6		T65	4		T46	1
all_values[11]	auto[0]	auto[1]	auto[0]	33	1			T47	1		T169	2		T242	1
all_values[11]	auto[0]	auto[1]	auto[1]	106	1			T55	5		T46	2		T168	2
all_values[11]	auto[1]	auto[0]	auto[1]	109	1			T55	3		T65	3		T46	3
all_values[11]	auto[1]	auto[1]	auto[1]	111	1			T55	4		T46	1		T47	2
all_values[12]	auto[0]	auto[0]	auto[0]	44	1			T46	1		T47	1		T168	1
all_values[12]	auto[0]	auto[0]	auto[1]	113	1			T55	8		T168	1		T48	1
all_values[12]	auto[0]	auto[1]	auto[0]	34	1			T46	1		T47	3		T249	1
all_values[12]	auto[0]	auto[1]	auto[1]	115	1			T55	2		T65	4		T46	3
all_values[12]	auto[1]	auto[0]	auto[1]	127	1			T55	6		T65	3		T46	2
all_values[12]	auto[1]	auto[1]	auto[1]	102	1			T55	2		T47	1		T168	3
all_values[13]	auto[0]	auto[0]	auto[0]	40	1			T55	2		T168	2		T48	1
all_values[13]	auto[0]	auto[0]	auto[1]	140	1			T55	1		T65	1		T46	2
all_values[13]	auto[0]	auto[1]	auto[0]	31	1			T55	8		T48	2		T249	2
all_values[13]	auto[0]	auto[1]	auto[1]	107	1			T55	4		T65	1		T46	1
all_values[13]	auto[1]	auto[0]	auto[1]	119	1			T55	2		T65	2		T46	3
all_values[13]	auto[1]	auto[1]	auto[1]	98	1			T55	1		T65	3		T46	1
all_values[14]	auto[0]	auto[0]	auto[0]	36	1			T65	5		T47	1		T168	1
all_values[14]	auto[0]	auto[0]	auto[1]	129	1			T55	5		T46	3		T47	4
all_values[14]	auto[0]	auto[1]	auto[0]	25	1			T168	4		T48	1		T253	2
all_values[14]	auto[0]	auto[1]	auto[1]	99	1			T55	2		T65	1		T46	1
all_values[14]	auto[1]	auto[0]	auto[1]	131	1			T55	2		T65	1		T46	3
all_values[14]	auto[1]	auto[1]	auto[1]	115	1			T55	9		T168	1		T48	6

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal