Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.63 97.19 92.04 97.66 83.74 94.53 98.67 91.60


Total test records in report: 1457
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T1303 /workspace/coverage/default/15.i2c_target_bad_addr.124870284 Apr 30 01:53:59 PM PDT 24 Apr 30 01:54:01 PM PDT 24 409644141 ps
T1304 /workspace/coverage/default/1.i2c_host_fifo_reset_rx.3569247075 Apr 30 01:52:38 PM PDT 24 Apr 30 01:52:47 PM PDT 24 749176857 ps
T1305 /workspace/coverage/default/8.i2c_host_override.3838900220 Apr 30 01:53:10 PM PDT 24 Apr 30 01:53:11 PM PDT 24 86971724 ps
T1306 /workspace/coverage/default/49.i2c_host_fifo_reset_rx.3044598181 Apr 30 01:58:17 PM PDT 24 Apr 30 01:58:22 PM PDT 24 140061057 ps
T1307 /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2021791490 Apr 30 01:57:17 PM PDT 24 Apr 30 01:57:31 PM PDT 24 10604468845 ps
T1308 /workspace/coverage/default/37.i2c_target_stress_wr.2289625866 Apr 30 01:56:47 PM PDT 24 Apr 30 02:00:01 PM PDT 24 29267700123 ps
T1309 /workspace/coverage/default/19.i2c_target_stress_wr.2044177026 Apr 30 01:54:30 PM PDT 24 Apr 30 01:54:52 PM PDT 24 10110525279 ps
T1310 /workspace/coverage/default/24.i2c_host_mode_toggle.496240726 Apr 30 01:55:13 PM PDT 24 Apr 30 01:55:50 PM PDT 24 1647626534 ps
T1311 /workspace/coverage/default/10.i2c_target_timeout.2014654717 Apr 30 01:53:27 PM PDT 24 Apr 30 01:53:33 PM PDT 24 1105122745 ps
T217 /workspace/coverage/default/12.i2c_target_unexp_stop.1448809179 Apr 30 01:53:41 PM PDT 24 Apr 30 01:53:46 PM PDT 24 755501956 ps
T1312 /workspace/coverage/default/0.i2c_target_timeout.1219321738 Apr 30 01:52:25 PM PDT 24 Apr 30 01:52:32 PM PDT 24 1121416876 ps
T1313 /workspace/coverage/default/41.i2c_target_timeout.2795664892 Apr 30 01:57:19 PM PDT 24 Apr 30 01:57:26 PM PDT 24 1471442894 ps
T1314 /workspace/coverage/default/24.i2c_target_fifo_reset_tx.4088100863 Apr 30 01:55:07 PM PDT 24 Apr 30 01:55:14 PM PDT 24 10643998491 ps
T1315 /workspace/coverage/default/0.i2c_target_smoke.1737182553 Apr 30 01:52:30 PM PDT 24 Apr 30 01:52:49 PM PDT 24 1378063938 ps
T1316 /workspace/coverage/default/18.i2c_host_override.2116608510 Apr 30 01:54:18 PM PDT 24 Apr 30 01:54:20 PM PDT 24 40806064 ps
T1317 /workspace/coverage/default/46.i2c_target_stress_rd.1004684500 Apr 30 01:57:58 PM PDT 24 Apr 30 01:58:02 PM PDT 24 250089126 ps
T1318 /workspace/coverage/default/6.i2c_target_bad_addr.1686758095 Apr 30 01:53:11 PM PDT 24 Apr 30 01:53:16 PM PDT 24 4217020772 ps
T1319 /workspace/coverage/default/31.i2c_host_error_intr.509023653 Apr 30 01:55:51 PM PDT 24 Apr 30 01:55:54 PM PDT 24 126025047 ps
T1320 /workspace/coverage/default/46.i2c_target_hrst.3358241057 Apr 30 01:57:59 PM PDT 24 Apr 30 01:58:02 PM PDT 24 687853176 ps
T1321 /workspace/coverage/default/17.i2c_target_intr_smoke.360397802 Apr 30 01:54:11 PM PDT 24 Apr 30 01:54:15 PM PDT 24 4725670552 ps
T1322 /workspace/coverage/default/25.i2c_host_perf.694465510 Apr 30 01:55:07 PM PDT 24 Apr 30 01:55:46 PM PDT 24 858610669 ps
T1323 /workspace/coverage/default/47.i2c_host_override.4017444543 Apr 30 01:58:00 PM PDT 24 Apr 30 01:58:01 PM PDT 24 46766061 ps
T1324 /workspace/coverage/default/12.i2c_host_smoke.4097708270 Apr 30 01:53:36 PM PDT 24 Apr 30 01:54:21 PM PDT 24 3743865941 ps
T1325 /workspace/coverage/default/10.i2c_target_stretch.1087807913 Apr 30 01:53:26 PM PDT 24 Apr 30 01:54:32 PM PDT 24 3381683206 ps
T1326 /workspace/coverage/default/23.i2c_target_bad_addr.3107006790 Apr 30 01:54:57 PM PDT 24 Apr 30 01:55:01 PM PDT 24 1553851315 ps
T1327 /workspace/coverage/default/7.i2c_host_fifo_reset_rx.465244843 Apr 30 01:53:00 PM PDT 24 Apr 30 01:53:06 PM PDT 24 415852579 ps
T1328 /workspace/coverage/default/31.i2c_host_fifo_reset_rx.1260496958 Apr 30 01:55:53 PM PDT 24 Apr 30 01:55:56 PM PDT 24 201362471 ps
T1329 /workspace/coverage/default/34.i2c_host_fifo_reset_rx.3470243151 Apr 30 01:56:20 PM PDT 24 Apr 30 01:56:28 PM PDT 24 528217028 ps
T1330 /workspace/coverage/default/33.i2c_target_intr_stress_wr.895880448 Apr 30 01:56:14 PM PDT 24 Apr 30 01:58:04 PM PDT 24 18350546132 ps
T1331 /workspace/coverage/default/1.i2c_host_mode_toggle.2423679827 Apr 30 01:52:42 PM PDT 24 Apr 30 01:53:20 PM PDT 24 5758064104 ps
T1332 /workspace/coverage/default/49.i2c_host_perf.313259181 Apr 30 01:58:19 PM PDT 24 Apr 30 01:58:53 PM PDT 24 6891598118 ps
T1333 /workspace/coverage/default/49.i2c_host_fifo_watermark.2771702364 Apr 30 01:58:18 PM PDT 24 Apr 30 02:00:25 PM PDT 24 4533929047 ps
T1334 /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.1389719202 Apr 30 01:57:24 PM PDT 24 Apr 30 01:57:41 PM PDT 24 334823730 ps
T1335 /workspace/coverage/default/37.i2c_target_timeout.964323837 Apr 30 01:56:47 PM PDT 24 Apr 30 01:56:55 PM PDT 24 3337162612 ps
T1336 /workspace/coverage/default/3.i2c_host_override.1602293885 Apr 30 01:52:39 PM PDT 24 Apr 30 01:52:41 PM PDT 24 63104674 ps
T1337 /workspace/coverage/default/26.i2c_target_fifo_reset_acq.1509572507 Apr 30 01:55:21 PM PDT 24 Apr 30 01:55:52 PM PDT 24 10189269729 ps
T1338 /workspace/coverage/default/21.i2c_target_stretch.450521161 Apr 30 01:54:41 PM PDT 24 Apr 30 01:55:14 PM PDT 24 3751387086 ps
T1339 /workspace/coverage/default/46.i2c_target_stretch.955500118 Apr 30 01:57:59 PM PDT 24 Apr 30 02:00:25 PM PDT 24 26060535723 ps
T1340 /workspace/coverage/default/5.i2c_target_hrst.466180008 Apr 30 01:52:53 PM PDT 24 Apr 30 01:52:55 PM PDT 24 6348466951 ps
T1341 /workspace/coverage/default/36.i2c_host_perf.1203239646 Apr 30 01:56:32 PM PDT 24 Apr 30 01:57:41 PM PDT 24 6243461708 ps
T1342 /workspace/coverage/default/38.i2c_host_fifo_watermark.2239962790 Apr 30 01:56:48 PM PDT 24 Apr 30 02:01:05 PM PDT 24 13798986561 ps
T1343 /workspace/coverage/default/11.i2c_target_fifo_reset_tx.946658292 Apr 30 01:53:34 PM PDT 24 Apr 30 01:53:38 PM PDT 24 13240612030 ps
T1344 /workspace/coverage/default/43.i2c_host_fifo_reset_rx.779285397 Apr 30 01:57:33 PM PDT 24 Apr 30 01:57:37 PM PDT 24 230101823 ps
T1345 /workspace/coverage/default/18.i2c_host_fifo_full.731871846 Apr 30 01:54:25 PM PDT 24 Apr 30 01:55:05 PM PDT 24 2516274031 ps
T1346 /workspace/coverage/default/31.i2c_target_stress_wr.2559176464 Apr 30 01:56:00 PM PDT 24 Apr 30 02:13:32 PM PDT 24 60517938985 ps
T1347 /workspace/coverage/default/48.i2c_target_stress_rd.2326291892 Apr 30 01:58:12 PM PDT 24 Apr 30 01:58:35 PM PDT 24 2208301560 ps
T1348 /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.519340854 Apr 30 01:54:50 PM PDT 24 Apr 30 01:54:57 PM PDT 24 3228849239 ps
T1349 /workspace/coverage/default/38.i2c_target_intr_stress_wr.2210394893 Apr 30 01:56:51 PM PDT 24 Apr 30 01:57:26 PM PDT 24 14871783596 ps
T1350 /workspace/coverage/default/0.i2c_target_stretch.990222620 Apr 30 01:52:24 PM PDT 24 Apr 30 01:54:33 PM PDT 24 5821458040 ps
T1351 /workspace/coverage/default/34.i2c_alert_test.2161134445 Apr 30 01:56:27 PM PDT 24 Apr 30 01:56:28 PM PDT 24 53619413 ps
T1352 /workspace/coverage/default/18.i2c_target_fifo_reset_acq.3613697694 Apr 30 01:54:25 PM PDT 24 Apr 30 01:54:35 PM PDT 24 10377820359 ps
T1353 /workspace/coverage/default/35.i2c_host_perf.553065423 Apr 30 01:56:26 PM PDT 24 Apr 30 02:52:19 PM PDT 24 18359211077 ps
T1354 /workspace/coverage/default/28.i2c_host_stretch_timeout.3047646439 Apr 30 01:55:35 PM PDT 24 Apr 30 01:55:58 PM PDT 24 627555002 ps
T1355 /workspace/coverage/default/44.i2c_host_perf.2815206390 Apr 30 01:57:41 PM PDT 24 Apr 30 01:58:10 PM PDT 24 2731453689 ps
T1356 /workspace/coverage/default/29.i2c_host_fifo_overflow.1904612052 Apr 30 01:55:42 PM PDT 24 Apr 30 01:56:20 PM PDT 24 1427194490 ps
T1357 /workspace/coverage/default/20.i2c_target_stress_rd.3903044907 Apr 30 01:54:33 PM PDT 24 Apr 30 01:54:45 PM PDT 24 758073347 ps
T1358 /workspace/coverage/default/32.i2c_target_timeout.891775576 Apr 30 01:56:04 PM PDT 24 Apr 30 01:56:11 PM PDT 24 2158848960 ps
T1359 /workspace/coverage/default/2.i2c_target_fifo_reset_tx.1225970092 Apr 30 01:52:42 PM PDT 24 Apr 30 01:53:53 PM PDT 24 10055222931 ps
T1360 /workspace/coverage/default/16.i2c_alert_test.918073034 Apr 30 01:54:06 PM PDT 24 Apr 30 01:54:07 PM PDT 24 19659616 ps
T175 /workspace/coverage/cover_reg_top/8.i2c_intr_test.1591271835 Apr 30 01:40:25 PM PDT 24 Apr 30 01:40:26 PM PDT 24 162284218 ps
T1361 /workspace/coverage/cover_reg_top/45.i2c_intr_test.2968092091 Apr 30 01:40:46 PM PDT 24 Apr 30 01:40:48 PM PDT 24 31271193 ps
T80 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.428203126 Apr 30 01:40:21 PM PDT 24 Apr 30 01:40:22 PM PDT 24 39278255 ps
T1362 /workspace/coverage/cover_reg_top/14.i2c_intr_test.2979773275 Apr 30 01:40:36 PM PDT 24 Apr 30 01:40:37 PM PDT 24 28099831 ps
T105 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.4135342506 Apr 30 01:40:41 PM PDT 24 Apr 30 01:40:43 PM PDT 24 30874531 ps
T81 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1365052752 Apr 30 01:40:33 PM PDT 24 Apr 30 01:40:34 PM PDT 24 17303190 ps
T82 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3376695598 Apr 30 01:40:32 PM PDT 24 Apr 30 01:40:34 PM PDT 24 71708909 ps
T1363 /workspace/coverage/cover_reg_top/4.i2c_intr_test.4197892605 Apr 30 01:40:27 PM PDT 24 Apr 30 01:40:28 PM PDT 24 15718441 ps
T106 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3026380165 Apr 30 01:40:36 PM PDT 24 Apr 30 01:40:38 PM PDT 24 81845923 ps
T151 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3675418866 Apr 30 01:40:26 PM PDT 24 Apr 30 01:40:27 PM PDT 24 52789556 ps
T1364 /workspace/coverage/cover_reg_top/29.i2c_intr_test.3180694143 Apr 30 01:40:42 PM PDT 24 Apr 30 01:40:43 PM PDT 24 23393619 ps
T120 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.764540238 Apr 30 01:40:36 PM PDT 24 Apr 30 01:40:39 PM PDT 24 284596245 ps
T1365 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1269485043 Apr 30 01:40:19 PM PDT 24 Apr 30 01:40:21 PM PDT 24 66303196 ps
T1366 /workspace/coverage/cover_reg_top/23.i2c_intr_test.619196193 Apr 30 01:40:46 PM PDT 24 Apr 30 01:40:47 PM PDT 24 49605196 ps
T1367 /workspace/coverage/cover_reg_top/32.i2c_intr_test.3478721822 Apr 30 01:40:41 PM PDT 24 Apr 30 01:40:42 PM PDT 24 28881682 ps
T1368 /workspace/coverage/cover_reg_top/31.i2c_intr_test.3463404840 Apr 30 01:40:41 PM PDT 24 Apr 30 01:40:42 PM PDT 24 14704654 ps
T119 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.467854623 Apr 30 01:40:35 PM PDT 24 Apr 30 01:40:37 PM PDT 24 52258081 ps
T1369 /workspace/coverage/cover_reg_top/28.i2c_intr_test.3073265792 Apr 30 01:40:44 PM PDT 24 Apr 30 01:40:45 PM PDT 24 19650785 ps
T121 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1634592483 Apr 30 01:40:26 PM PDT 24 Apr 30 01:40:28 PM PDT 24 267913135 ps
T140 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1700838137 Apr 30 01:40:27 PM PDT 24 Apr 30 01:40:28 PM PDT 24 25936145 ps
T122 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3051201117 Apr 30 01:40:33 PM PDT 24 Apr 30 01:40:36 PM PDT 24 199984846 ps
T129 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3818857838 Apr 30 01:40:29 PM PDT 24 Apr 30 01:40:30 PM PDT 24 37919294 ps
T156 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.817254406 Apr 30 01:40:19 PM PDT 24 Apr 30 01:40:21 PM PDT 24 423389274 ps
T1370 /workspace/coverage/cover_reg_top/49.i2c_intr_test.276235811 Apr 30 01:40:44 PM PDT 24 Apr 30 01:40:45 PM PDT 24 42651799 ps
T127 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.936334187 Apr 30 01:40:33 PM PDT 24 Apr 30 01:40:35 PM PDT 24 100850891 ps
T124 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1004573049 Apr 30 01:40:34 PM PDT 24 Apr 30 01:40:36 PM PDT 24 105003586 ps
T123 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3975889205 Apr 30 01:40:30 PM PDT 24 Apr 30 01:40:33 PM PDT 24 79796111 ps
T1371 /workspace/coverage/cover_reg_top/7.i2c_intr_test.1270394260 Apr 30 01:40:33 PM PDT 24 Apr 30 01:40:34 PM PDT 24 30722927 ps
T1372 /workspace/coverage/cover_reg_top/46.i2c_intr_test.3327585321 Apr 30 01:40:42 PM PDT 24 Apr 30 01:40:44 PM PDT 24 15803009 ps
T1373 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1392072418 Apr 30 01:40:25 PM PDT 24 Apr 30 01:40:27 PM PDT 24 19531881 ps
T1374 /workspace/coverage/cover_reg_top/38.i2c_intr_test.1690239706 Apr 30 01:40:45 PM PDT 24 Apr 30 01:40:46 PM PDT 24 138734037 ps
T136 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3004760594 Apr 30 01:40:35 PM PDT 24 Apr 30 01:40:37 PM PDT 24 83192073 ps
T1375 /workspace/coverage/cover_reg_top/41.i2c_intr_test.2188170491 Apr 30 01:40:43 PM PDT 24 Apr 30 01:40:44 PM PDT 24 108492358 ps
T141 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.923852147 Apr 30 01:40:31 PM PDT 24 Apr 30 01:40:32 PM PDT 24 67346896 ps
T152 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.762528239 Apr 30 01:40:25 PM PDT 24 Apr 30 01:40:27 PM PDT 24 51789211 ps
T1376 /workspace/coverage/cover_reg_top/48.i2c_intr_test.1617482778 Apr 30 01:40:43 PM PDT 24 Apr 30 01:40:45 PM PDT 24 17981216 ps
T126 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1693409131 Apr 30 01:40:28 PM PDT 24 Apr 30 01:40:31 PM PDT 24 46784814 ps
T1377 /workspace/coverage/cover_reg_top/10.i2c_intr_test.774400766 Apr 30 01:40:28 PM PDT 24 Apr 30 01:40:29 PM PDT 24 40854007 ps
T1378 /workspace/coverage/cover_reg_top/27.i2c_intr_test.2216136522 Apr 30 01:40:39 PM PDT 24 Apr 30 01:40:40 PM PDT 24 50332729 ps
T1379 /workspace/coverage/cover_reg_top/17.i2c_intr_test.2037265317 Apr 30 01:40:32 PM PDT 24 Apr 30 01:40:33 PM PDT 24 18419324 ps
T1380 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3883469363 Apr 30 01:40:34 PM PDT 24 Apr 30 01:40:36 PM PDT 24 19575319 ps
T125 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.43818874 Apr 30 01:40:35 PM PDT 24 Apr 30 01:40:37 PM PDT 24 214025790 ps
T135 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1176105467 Apr 30 01:40:35 PM PDT 24 Apr 30 01:40:37 PM PDT 24 30445045 ps
T157 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2453758499 Apr 30 01:40:34 PM PDT 24 Apr 30 01:40:36 PM PDT 24 90871423 ps
T153 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1868041213 Apr 30 01:40:26 PM PDT 24 Apr 30 01:40:28 PM PDT 24 44363915 ps
T158 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.4008099567 Apr 30 01:40:35 PM PDT 24 Apr 30 01:40:37 PM PDT 24 50782792 ps
T218 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1626342603 Apr 30 01:40:19 PM PDT 24 Apr 30 01:40:21 PM PDT 24 294576972 ps
T159 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3521389673 Apr 30 01:40:26 PM PDT 24 Apr 30 01:40:28 PM PDT 24 127554703 ps
T154 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1379723507 Apr 30 01:40:26 PM PDT 24 Apr 30 01:40:28 PM PDT 24 63017992 ps
T1381 /workspace/coverage/cover_reg_top/19.i2c_intr_test.881649585 Apr 30 01:40:44 PM PDT 24 Apr 30 01:40:45 PM PDT 24 22499123 ps
T1382 /workspace/coverage/cover_reg_top/40.i2c_intr_test.4153871404 Apr 30 01:40:45 PM PDT 24 Apr 30 01:40:46 PM PDT 24 52040183 ps
T142 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.282162477 Apr 30 01:40:21 PM PDT 24 Apr 30 01:40:22 PM PDT 24 23519889 ps
T259 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.721303516 Apr 30 01:40:19 PM PDT 24 Apr 30 01:40:20 PM PDT 24 35651805 ps
T1383 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3268349499 Apr 30 01:40:46 PM PDT 24 Apr 30 01:40:48 PM PDT 24 69544837 ps
T1384 /workspace/coverage/cover_reg_top/47.i2c_intr_test.3421288579 Apr 30 01:40:42 PM PDT 24 Apr 30 01:40:43 PM PDT 24 20546429 ps
T1385 /workspace/coverage/cover_reg_top/5.i2c_intr_test.222495555 Apr 30 01:40:26 PM PDT 24 Apr 30 01:40:27 PM PDT 24 20059493 ps
T155 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.233228985 Apr 30 01:40:25 PM PDT 24 Apr 30 01:40:27 PM PDT 24 313355193 ps
T143 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3235837809 Apr 30 01:40:24 PM PDT 24 Apr 30 01:40:25 PM PDT 24 22692343 ps
T1386 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2332553805 Apr 30 01:40:34 PM PDT 24 Apr 30 01:40:36 PM PDT 24 43069207 ps
T1387 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2160948275 Apr 30 01:40:19 PM PDT 24 Apr 30 01:40:21 PM PDT 24 32959461 ps
T1388 /workspace/coverage/cover_reg_top/37.i2c_intr_test.1046454435 Apr 30 01:40:42 PM PDT 24 Apr 30 01:40:43 PM PDT 24 63805778 ps
T1389 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2615051256 Apr 30 01:40:25 PM PDT 24 Apr 30 01:40:27 PM PDT 24 136544178 ps
T1390 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1569036116 Apr 30 01:40:19 PM PDT 24 Apr 30 01:40:23 PM PDT 24 245365203 ps
T144 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2759571835 Apr 30 01:40:26 PM PDT 24 Apr 30 01:40:28 PM PDT 24 19396373 ps
T1391 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1407493051 Apr 30 01:40:32 PM PDT 24 Apr 30 01:40:35 PM PDT 24 94779605 ps
T1392 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.474969290 Apr 30 01:40:21 PM PDT 24 Apr 30 01:40:24 PM PDT 24 396539628 ps
T1393 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2700848662 Apr 30 01:40:26 PM PDT 24 Apr 30 01:40:29 PM PDT 24 139015312 ps
T139 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3725860203 Apr 30 01:40:35 PM PDT 24 Apr 30 01:40:38 PM PDT 24 128029284 ps
T130 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2475214614 Apr 30 01:40:33 PM PDT 24 Apr 30 01:40:35 PM PDT 24 155032668 ps
T1394 /workspace/coverage/cover_reg_top/6.i2c_intr_test.1691380604 Apr 30 01:40:28 PM PDT 24 Apr 30 01:40:29 PM PDT 24 44163863 ps
T145 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3562064254 Apr 30 01:40:25 PM PDT 24 Apr 30 01:40:26 PM PDT 24 66998821 ps
T1395 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.336630446 Apr 30 01:40:26 PM PDT 24 Apr 30 01:40:28 PM PDT 24 85100965 ps
T146 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1095510126 Apr 30 01:40:18 PM PDT 24 Apr 30 01:40:21 PM PDT 24 137975941 ps
T128 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.721661510 Apr 30 01:40:18 PM PDT 24 Apr 30 01:40:20 PM PDT 24 304073344 ps
T260 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3899055707 Apr 30 01:40:19 PM PDT 24 Apr 30 01:40:21 PM PDT 24 27688196 ps
T137 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1168292634 Apr 30 01:40:30 PM PDT 24 Apr 30 01:40:33 PM PDT 24 300316762 ps
T1396 /workspace/coverage/cover_reg_top/11.i2c_intr_test.1806004152 Apr 30 01:40:26 PM PDT 24 Apr 30 01:40:28 PM PDT 24 17918039 ps
T1397 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2412452081 Apr 30 01:40:11 PM PDT 24 Apr 30 01:40:14 PM PDT 24 225032687 ps
T1398 /workspace/coverage/cover_reg_top/35.i2c_intr_test.1644413612 Apr 30 01:40:41 PM PDT 24 Apr 30 01:40:43 PM PDT 24 17307009 ps
T1399 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.878180207 Apr 30 01:40:33 PM PDT 24 Apr 30 01:40:35 PM PDT 24 45057629 ps
T1400 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2019485291 Apr 30 01:40:18 PM PDT 24 Apr 30 01:40:21 PM PDT 24 223791670 ps
T1401 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3177845894 Apr 30 01:40:31 PM PDT 24 Apr 30 01:40:32 PM PDT 24 118428962 ps
T1402 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3444983701 Apr 30 01:40:36 PM PDT 24 Apr 30 01:40:38 PM PDT 24 59050680 ps
T134 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.4151471321 Apr 30 01:40:26 PM PDT 24 Apr 30 01:40:28 PM PDT 24 260724606 ps
T1403 /workspace/coverage/cover_reg_top/44.i2c_intr_test.2028646366 Apr 30 01:40:44 PM PDT 24 Apr 30 01:40:46 PM PDT 24 15516555 ps
T1404 /workspace/coverage/cover_reg_top/3.i2c_intr_test.4161505171 Apr 30 01:40:25 PM PDT 24 Apr 30 01:40:27 PM PDT 24 16422026 ps
T1405 /workspace/coverage/cover_reg_top/12.i2c_intr_test.3464723429 Apr 30 01:40:27 PM PDT 24 Apr 30 01:40:29 PM PDT 24 22810872 ps
T1406 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1641328873 Apr 30 01:40:40 PM PDT 24 Apr 30 01:40:43 PM PDT 24 209380410 ps
T1407 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1981342929 Apr 30 01:40:26 PM PDT 24 Apr 30 01:40:28 PM PDT 24 73771774 ps
T1408 /workspace/coverage/cover_reg_top/9.i2c_intr_test.8741766 Apr 30 01:40:31 PM PDT 24 Apr 30 01:40:32 PM PDT 24 78683516 ps
T1409 /workspace/coverage/cover_reg_top/18.i2c_intr_test.2376610175 Apr 30 01:40:33 PM PDT 24 Apr 30 01:40:35 PM PDT 24 46795841 ps
T147 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1169062511 Apr 30 01:40:44 PM PDT 24 Apr 30 01:40:45 PM PDT 24 16783414 ps
T1410 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.737476308 Apr 30 01:40:33 PM PDT 24 Apr 30 01:40:34 PM PDT 24 81699118 ps
T133 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.962008399 Apr 30 01:40:26 PM PDT 24 Apr 30 01:40:28 PM PDT 24 220414318 ps
T1411 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.300919932 Apr 30 01:40:25 PM PDT 24 Apr 30 01:40:27 PM PDT 24 64453920 ps
T1412 /workspace/coverage/cover_reg_top/20.i2c_intr_test.1643904006 Apr 30 01:40:41 PM PDT 24 Apr 30 01:40:42 PM PDT 24 36141481 ps
T1413 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2106297329 Apr 30 01:40:19 PM PDT 24 Apr 30 01:40:21 PM PDT 24 25959919 ps
T1414 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1096772165 Apr 30 01:40:43 PM PDT 24 Apr 30 01:40:44 PM PDT 24 17185299 ps
T1415 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2926579900 Apr 30 01:40:27 PM PDT 24 Apr 30 01:40:28 PM PDT 24 19821527 ps
T1416 /workspace/coverage/cover_reg_top/30.i2c_intr_test.1843248020 Apr 30 01:40:42 PM PDT 24 Apr 30 01:40:44 PM PDT 24 14696739 ps
T219 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4141573760 Apr 30 01:40:28 PM PDT 24 Apr 30 01:40:30 PM PDT 24 208839775 ps
T1417 /workspace/coverage/cover_reg_top/22.i2c_intr_test.1257123699 Apr 30 01:40:41 PM PDT 24 Apr 30 01:40:43 PM PDT 24 40757086 ps
T1418 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1729488446 Apr 30 01:40:32 PM PDT 24 Apr 30 01:40:34 PM PDT 24 947600795 ps
T1419 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2400143145 Apr 30 01:40:25 PM PDT 24 Apr 30 01:40:27 PM PDT 24 70715023 ps
T1420 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2382085191 Apr 30 01:40:46 PM PDT 24 Apr 30 01:40:50 PM PDT 24 129170657 ps
T1421 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.4257552925 Apr 30 01:40:34 PM PDT 24 Apr 30 01:40:36 PM PDT 24 65065471 ps
T148 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.125256203 Apr 30 01:40:21 PM PDT 24 Apr 30 01:40:22 PM PDT 24 39341028 ps
T1422 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1620573161 Apr 30 01:40:34 PM PDT 24 Apr 30 01:40:35 PM PDT 24 85939035 ps
T1423 /workspace/coverage/cover_reg_top/0.i2c_intr_test.3141970101 Apr 30 01:40:18 PM PDT 24 Apr 30 01:40:19 PM PDT 24 48186954 ps
T1424 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1028308224 Apr 30 01:40:36 PM PDT 24 Apr 30 01:40:37 PM PDT 24 59892882 ps
T1425 /workspace/coverage/cover_reg_top/25.i2c_intr_test.1577515830 Apr 30 01:40:43 PM PDT 24 Apr 30 01:40:44 PM PDT 24 21822980 ps
T150 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.4001956032 Apr 30 01:40:18 PM PDT 24 Apr 30 01:40:20 PM PDT 24 336437152 ps
T1426 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1228253414 Apr 30 01:40:29 PM PDT 24 Apr 30 01:40:30 PM PDT 24 200692511 ps
T1427 /workspace/coverage/cover_reg_top/43.i2c_intr_test.1873267163 Apr 30 01:40:45 PM PDT 24 Apr 30 01:40:46 PM PDT 24 25305313 ps
T1428 /workspace/coverage/cover_reg_top/13.i2c_intr_test.37583188 Apr 30 01:40:35 PM PDT 24 Apr 30 01:40:36 PM PDT 24 51020626 ps
T1429 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1074814613 Apr 30 01:40:27 PM PDT 24 Apr 30 01:40:29 PM PDT 24 61194847 ps
T1430 /workspace/coverage/cover_reg_top/21.i2c_intr_test.1062964558 Apr 30 01:40:43 PM PDT 24 Apr 30 01:40:44 PM PDT 24 23906182 ps
T1431 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3341211795 Apr 30 01:40:28 PM PDT 24 Apr 30 01:40:30 PM PDT 24 73292522 ps
T1432 /workspace/coverage/cover_reg_top/34.i2c_intr_test.1618979243 Apr 30 01:40:45 PM PDT 24 Apr 30 01:40:47 PM PDT 24 15170192 ps
T1433 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1909496664 Apr 30 01:40:27 PM PDT 24 Apr 30 01:40:29 PM PDT 24 117479608 ps
T1434 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.4129186533 Apr 30 01:40:25 PM PDT 24 Apr 30 01:40:27 PM PDT 24 328908570 ps
T1435 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3667967247 Apr 30 01:40:28 PM PDT 24 Apr 30 01:40:30 PM PDT 24 210649602 ps
T1436 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.17131535 Apr 30 01:40:28 PM PDT 24 Apr 30 01:40:30 PM PDT 24 29699111 ps
T1437 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1017302852 Apr 30 01:40:46 PM PDT 24 Apr 30 01:40:47 PM PDT 24 65916590 ps
T149 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2639182886 Apr 30 01:40:34 PM PDT 24 Apr 30 01:40:35 PM PDT 24 51728315 ps
T1438 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.516917923 Apr 30 01:40:36 PM PDT 24 Apr 30 01:40:38 PM PDT 24 133862437 ps
T1439 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.869172472 Apr 30 01:40:17 PM PDT 24 Apr 30 01:40:18 PM PDT 24 84624647 ps
T1440 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2046439285 Apr 30 01:40:42 PM PDT 24 Apr 30 01:40:43 PM PDT 24 38839340 ps
T131 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2947452776 Apr 30 01:40:23 PM PDT 24 Apr 30 01:40:25 PM PDT 24 81476892 ps
T1441 /workspace/coverage/cover_reg_top/33.i2c_intr_test.1497399111 Apr 30 01:40:46 PM PDT 24 Apr 30 01:40:47 PM PDT 24 47548837 ps
T1442 /workspace/coverage/cover_reg_top/1.i2c_intr_test.4060408459 Apr 30 01:40:24 PM PDT 24 Apr 30 01:40:25 PM PDT 24 58210085 ps
T132 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2590063374 Apr 30 01:40:24 PM PDT 24 Apr 30 01:40:27 PM PDT 24 83951697 ps
T1443 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1243857066 Apr 30 01:40:33 PM PDT 24 Apr 30 01:40:35 PM PDT 24 177057991 ps
T1444 /workspace/coverage/cover_reg_top/24.i2c_intr_test.2090740353 Apr 30 01:40:43 PM PDT 24 Apr 30 01:40:45 PM PDT 24 17290244 ps
T1445 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4040802754 Apr 30 01:40:19 PM PDT 24 Apr 30 01:40:21 PM PDT 24 65967148 ps
T1446 /workspace/coverage/cover_reg_top/42.i2c_intr_test.1469346443 Apr 30 01:40:43 PM PDT 24 Apr 30 01:40:45 PM PDT 24 36585506 ps
T1447 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1031993682 Apr 30 01:40:33 PM PDT 24 Apr 30 01:40:34 PM PDT 24 50209658 ps
T1448 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3549376017 Apr 30 01:40:27 PM PDT 24 Apr 30 01:40:29 PM PDT 24 39717178 ps
T1449 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3464927753 Apr 30 01:40:31 PM PDT 24 Apr 30 01:40:33 PM PDT 24 69149860 ps
T1450 /workspace/coverage/cover_reg_top/26.i2c_intr_test.1512816750 Apr 30 01:40:40 PM PDT 24 Apr 30 01:40:41 PM PDT 24 58786441 ps
T1451 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.4028459314 Apr 30 01:40:17 PM PDT 24 Apr 30 01:40:21 PM PDT 24 467141285 ps
T1452 /workspace/coverage/cover_reg_top/39.i2c_intr_test.1961866346 Apr 30 01:40:44 PM PDT 24 Apr 30 01:40:45 PM PDT 24 15309494 ps
T1453 /workspace/coverage/cover_reg_top/16.i2c_intr_test.2274975127 Apr 30 01:40:34 PM PDT 24 Apr 30 01:40:36 PM PDT 24 19183806 ps
T1454 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.264043255 Apr 30 01:40:33 PM PDT 24 Apr 30 01:40:35 PM PDT 24 101992513 ps
T1455 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.435636698 Apr 30 01:40:30 PM PDT 24 Apr 30 01:40:32 PM PDT 24 36095756 ps
T1456 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.496470243 Apr 30 01:40:24 PM PDT 24 Apr 30 01:40:25 PM PDT 24 49183028 ps
T138 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.261069926 Apr 30 01:40:35 PM PDT 24 Apr 30 01:40:37 PM PDT 24 92662409 ps
T1457 /workspace/coverage/cover_reg_top/15.i2c_intr_test.1822238951 Apr 30 01:40:36 PM PDT 24 Apr 30 01:40:38 PM PDT 24 47737365 ps

Test location /workspace/coverage/default/31.i2c_host_perf.103764469
Short name T2
Test name
Test status
Simulation time 53706602014 ps
CPU time 519.14 seconds
Started Apr 30 01:55:52 PM PDT 24
Finished Apr 30 02:04:32 PM PDT 24
Peak memory 2206728 kb
Host smart-a816c0c4-8553-45c9-a944-166e75ee15bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103764469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.103764469
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1106221171
Short name T6
Test name
Test status
Simulation time 10573027629 ps
CPU time 8.13 seconds
Started Apr 30 01:57:55 PM PDT 24
Finished Apr 30 01:58:03 PM PDT 24
Peak memory 233440 kb
Host smart-fff7e52f-3542-4ea2-8c4f-dc277ee3f28c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106221171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1106221171
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.576041437
Short name T15
Test name
Test status
Simulation time 8666145439 ps
CPU time 10.03 seconds
Started Apr 30 01:52:43 PM PDT 24
Finished Apr 30 01:52:54 PM PDT 24
Peak memory 204352 kb
Host smart-10035a26-89d5-4f92-bc41-861268e73539
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576041437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.576041437
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.3071309019
Short name T55
Test name
Test status
Simulation time 31113762335 ps
CPU time 289.28 seconds
Started Apr 30 01:58:01 PM PDT 24
Finished Apr 30 02:02:51 PM PDT 24
Peak memory 1123648 kb
Host smart-cdf031e7-b34f-4b07-a77d-e1c809285b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071309019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.3071309019
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3026380165
Short name T106
Test name
Test status
Simulation time 81845923 ps
CPU time 1.02 seconds
Started Apr 30 01:40:36 PM PDT 24
Finished Apr 30 01:40:38 PM PDT 24
Peak memory 204140 kb
Host smart-07ce59bd-ddf4-4425-a405-3bd8648ca4b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026380165 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3026380165
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.3070696741
Short name T9
Test name
Test status
Simulation time 2131374224 ps
CPU time 6.05 seconds
Started Apr 30 01:53:38 PM PDT 24
Finished Apr 30 01:53:45 PM PDT 24
Peak memory 204124 kb
Host smart-60b21038-e682-46fa-a56b-20a91820ccc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070696741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.3070696741
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_override.517379211
Short name T184
Test name
Test status
Simulation time 86231257 ps
CPU time 0.72 seconds
Started Apr 30 01:52:18 PM PDT 24
Finished Apr 30 01:52:19 PM PDT 24
Peak memory 203804 kb
Host smart-f2528e6e-b0cb-4815-bc46-6adb45a17888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517379211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.517379211
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.2974218211
Short name T107
Test name
Test status
Simulation time 76601383 ps
CPU time 0.93 seconds
Started Apr 30 01:52:29 PM PDT 24
Finished Apr 30 01:52:30 PM PDT 24
Peak memory 221504 kb
Host smart-bd3b9752-a0c0-48dd-91f1-abe123427ebc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974218211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.2974218211
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.734906156
Short name T79
Test name
Test status
Simulation time 238961950 ps
CPU time 6.4 seconds
Started Apr 30 01:55:22 PM PDT 24
Finished Apr 30 01:55:29 PM PDT 24
Peak memory 221100 kb
Host smart-df27a8d9-725d-4d44-a49f-461e44d53ce8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734906156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.
734906156
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.765005355
Short name T1
Test name
Test status
Simulation time 15029110831 ps
CPU time 7.2 seconds
Started Apr 30 01:53:46 PM PDT 24
Finished Apr 30 01:53:54 PM PDT 24
Peak memory 228060 kb
Host smart-bbb17d23-d2a0-46c7-b024-bae2f059494d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765005355 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.765005355
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.1887536621
Short name T65
Test name
Test status
Simulation time 58049042942 ps
CPU time 1219.41 seconds
Started Apr 30 01:53:07 PM PDT 24
Finished Apr 30 02:13:27 PM PDT 24
Peak memory 3140228 kb
Host smart-32cbae34-62ae-4060-9b2e-f36a079c6036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887536621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.1887536621
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1700838137
Short name T140
Test name
Test status
Simulation time 25936145 ps
CPU time 0.82 seconds
Started Apr 30 01:40:27 PM PDT 24
Finished Apr 30 01:40:28 PM PDT 24
Peak memory 204080 kb
Host smart-c1d2bbf2-644d-47e3-a958-1e1229decb08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700838137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1700838137
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3725860203
Short name T139
Test name
Test status
Simulation time 128029284 ps
CPU time 2.45 seconds
Started Apr 30 01:40:35 PM PDT 24
Finished Apr 30 01:40:38 PM PDT 24
Peak memory 204192 kb
Host smart-92fd9038-f5ae-4a6c-8891-1e14ea79bb18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725860203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3725860203
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.1561584696
Short name T48
Test name
Test status
Simulation time 38420820122 ps
CPU time 1288.74 seconds
Started Apr 30 01:55:04 PM PDT 24
Finished Apr 30 02:16:33 PM PDT 24
Peak memory 1785296 kb
Host smart-9cfff68b-d806-4aa0-8f08-dfd464975a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561584696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.1561584696
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.351750741
Short name T26
Test name
Test status
Simulation time 2396510775 ps
CPU time 3.08 seconds
Started Apr 30 01:53:27 PM PDT 24
Finished Apr 30 01:53:31 PM PDT 24
Peak memory 204468 kb
Host smart-a4564dd6-e1e5-4926-ae80-73e35b0c630f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351750741 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.351750741
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.693797618
Short name T772
Test name
Test status
Simulation time 1496736087 ps
CPU time 2.55 seconds
Started Apr 30 01:57:52 PM PDT 24
Finished Apr 30 01:57:55 PM PDT 24
Peak memory 204148 kb
Host smart-1bae5734-c93a-44e4-9aa6-1726409b97a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693797618 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.i2c_target_hrst.693797618
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.170433818
Short name T68
Test name
Test status
Simulation time 11234826581 ps
CPU time 558.9 seconds
Started Apr 30 01:52:30 PM PDT 24
Finished Apr 30 02:01:50 PM PDT 24
Peak memory 2833080 kb
Host smart-ae0a6004-cbdc-4a8c-977c-863bf4bbea32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170433818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.170433818
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.2727818506
Short name T52
Test name
Test status
Simulation time 10138568249 ps
CPU time 61.16 seconds
Started Apr 30 01:54:37 PM PDT 24
Finished Apr 30 01:55:38 PM PDT 24
Peak memory 478104 kb
Host smart-e984e08c-a995-4782-9971-553bf6f9f40a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727818506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.2727818506
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1004573049
Short name T124
Test name
Test status
Simulation time 105003586 ps
CPU time 2.15 seconds
Started Apr 30 01:40:34 PM PDT 24
Finished Apr 30 01:40:36 PM PDT 24
Peak memory 204204 kb
Host smart-5d9c4160-61bc-459a-83f2-92263008133a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004573049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.1004573049
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.4287136916
Short name T47
Test name
Test status
Simulation time 55331822897 ps
CPU time 840.91 seconds
Started Apr 30 01:53:51 PM PDT 24
Finished Apr 30 02:07:53 PM PDT 24
Peak memory 2735316 kb
Host smart-f40caf64-644e-4c9f-ba4b-33eb05319bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287136916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.4287136916
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.2163077103
Short name T115
Test name
Test status
Simulation time 276333208 ps
CPU time 1.08 seconds
Started Apr 30 01:53:37 PM PDT 24
Finished Apr 30 01:53:38 PM PDT 24
Peak memory 204108 kb
Host smart-53f9cd81-26e5-4eea-9f6b-ecc601ba4582
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163077103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.2163077103
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_alert_test.1606640260
Short name T290
Test name
Test status
Simulation time 32507867 ps
CPU time 0.61 seconds
Started Apr 30 01:54:32 PM PDT 24
Finished Apr 30 01:54:33 PM PDT 24
Peak memory 203832 kb
Host smart-f2e10e58-5be8-44c4-920f-46fd7c0896f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606640260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.1606640260
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.2325411724
Short name T63
Test name
Test status
Simulation time 731066156 ps
CPU time 12.58 seconds
Started Apr 30 01:55:48 PM PDT 24
Finished Apr 30 01:56:01 PM PDT 24
Peak memory 279704 kb
Host smart-27496c67-ca0e-4d66-b81e-7531f318865b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325411724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.2325411724
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_target_unexp_stop.1448809179
Short name T217
Test name
Test status
Simulation time 755501956 ps
CPU time 4.9 seconds
Started Apr 30 01:53:41 PM PDT 24
Finished Apr 30 01:53:46 PM PDT 24
Peak memory 204180 kb
Host smart-fe4b4e6a-fed8-4b00-8c88-124155c1b4cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448809179 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.i2c_target_unexp_stop.1448809179
Directory /workspace/12.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.4190789816
Short name T251
Test name
Test status
Simulation time 25826516615 ps
CPU time 242.62 seconds
Started Apr 30 01:54:38 PM PDT 24
Finished Apr 30 01:58:41 PM PDT 24
Peak memory 1339620 kb
Host smart-43dfbaf6-cf36-446f-835a-439c9a34d92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190789816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.4190789816
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.2978601179
Short name T212
Test name
Test status
Simulation time 360152806 ps
CPU time 1.1 seconds
Started Apr 30 01:55:47 PM PDT 24
Finished Apr 30 01:55:48 PM PDT 24
Peak memory 203964 kb
Host smart-3e6c65ac-6973-4f7a-9412-114eac33a755
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978601179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.2978601179
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.2807588482
Short name T315
Test name
Test status
Simulation time 2783627257 ps
CPU time 6.76 seconds
Started Apr 30 01:53:47 PM PDT 24
Finished Apr 30 01:53:55 PM PDT 24
Peak memory 220540 kb
Host smart-53a3678a-390a-443d-9e62-87bd51a4f334
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807588482 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.2807588482
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_stress_all.479217224
Short name T236
Test name
Test status
Simulation time 105935040027 ps
CPU time 792.25 seconds
Started Apr 30 01:52:41 PM PDT 24
Finished Apr 30 02:05:54 PM PDT 24
Peak memory 3599924 kb
Host smart-9ee2de03-8faa-411f-96f3-7489b2737f97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479217224 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.i2c_target_stress_all.479217224
Directory /workspace/1.i2c_target_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.383941135
Short name T49
Test name
Test status
Simulation time 27986140749 ps
CPU time 2380.15 seconds
Started Apr 30 01:57:19 PM PDT 24
Finished Apr 30 02:37:00 PM PDT 24
Peak memory 3532236 kb
Host smart-44919d0a-2102-4495-998c-3a66eb62c92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383941135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.383941135
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.3708954359
Short name T207
Test name
Test status
Simulation time 10090195800 ps
CPU time 34.8 seconds
Started Apr 30 01:54:49 PM PDT 24
Finished Apr 30 01:55:24 PM PDT 24
Peak memory 325436 kb
Host smart-dd6ec423-4bb4-4798-aad4-b48c54d55567
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708954359 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.3708954359
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.3187068657
Short name T225
Test name
Test status
Simulation time 87466460 ps
CPU time 2 seconds
Started Apr 30 01:55:21 PM PDT 24
Finished Apr 30 01:55:23 PM PDT 24
Peak memory 220604 kb
Host smart-3cb7f9a9-d93b-4d8e-b42a-26b88c3bf566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187068657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.3187068657
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.3659424473
Short name T244
Test name
Test status
Simulation time 25971825510 ps
CPU time 636.86 seconds
Started Apr 30 01:52:38 PM PDT 24
Finished Apr 30 02:03:16 PM PDT 24
Peak memory 789888 kb
Host smart-8099c24b-44bf-4b71-b467-99485547c659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659424473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.3659424473
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.1327136402
Short name T59
Test name
Test status
Simulation time 30101846574 ps
CPU time 2470.91 seconds
Started Apr 30 01:57:33 PM PDT 24
Finished Apr 30 02:38:45 PM PDT 24
Peak memory 3055704 kb
Host smart-bd639f38-0339-41f3-98cd-fedf085bb5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327136402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.1327136402
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.1153363476
Short name T599
Test name
Test status
Simulation time 2301412509 ps
CPU time 2.42 seconds
Started Apr 30 01:58:23 PM PDT 24
Finished Apr 30 01:58:25 PM PDT 24
Peak memory 204256 kb
Host smart-b212cd3f-55ee-42a3-8229-ab9e000b391f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153363476 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.1153363476
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_host_perf.3004002066
Short name T72
Test name
Test status
Simulation time 1046635506 ps
CPU time 2.8 seconds
Started Apr 30 01:53:52 PM PDT 24
Finished Apr 30 01:53:56 PM PDT 24
Peak memory 227948 kb
Host smart-ecb6932f-c1d8-4b22-8e1b-51fe09bce688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004002066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.3004002066
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.3376695598
Short name T82
Test name
Test status
Simulation time 71708909 ps
CPU time 1.37 seconds
Started Apr 30 01:40:32 PM PDT 24
Finished Apr 30 01:40:34 PM PDT 24
Peak memory 204264 kb
Host smart-10146518-d44a-4100-baa0-8b070ef0ca17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376695598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.3376695598
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.2993587075
Short name T34
Test name
Test status
Simulation time 10133327448 ps
CPU time 68.94 seconds
Started Apr 30 01:57:15 PM PDT 24
Finished Apr 30 01:58:25 PM PDT 24
Peak memory 514712 kb
Host smart-58bdbab3-f16e-468c-9036-41f5b8f0389c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993587075 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.2993587075
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.721303516
Short name T259
Test name
Test status
Simulation time 35651805 ps
CPU time 0.74 seconds
Started Apr 30 01:40:19 PM PDT 24
Finished Apr 30 01:40:20 PM PDT 24
Peak memory 204016 kb
Host smart-00cd1859-0763-4a13-9df8-202caf643486
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721303516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.721303516
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.2070425244
Short name T227
Test name
Test status
Simulation time 751444686 ps
CPU time 2.42 seconds
Started Apr 30 01:52:41 PM PDT 24
Finished Apr 30 01:52:44 PM PDT 24
Peak memory 204356 kb
Host smart-07272a45-634e-431f-8a53-6b074e8dfefb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070425244 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.2070425244
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.2376511906
Short name T240
Test name
Test status
Simulation time 11644526670 ps
CPU time 244.87 seconds
Started Apr 30 01:53:26 PM PDT 24
Finished Apr 30 01:57:32 PM PDT 24
Peak memory 1018556 kb
Host smart-1972007b-da10-4758-a19f-c47de89d21a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376511906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.2376511906
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.2239872432
Short name T320
Test name
Test status
Simulation time 10149102627 ps
CPU time 38.14 seconds
Started Apr 30 01:53:53 PM PDT 24
Finished Apr 30 01:54:32 PM PDT 24
Peak memory 365684 kb
Host smart-de51f65b-1dd2-4823-9bbe-8e062bf524a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239872432 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.2239872432
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.544407840
Short name T229
Test name
Test status
Simulation time 19858025408 ps
CPU time 1347.5 seconds
Started Apr 30 01:56:06 PM PDT 24
Finished Apr 30 02:18:35 PM PDT 24
Peak memory 4606564 kb
Host smart-1983aa65-5f06-4734-b437-fa88e6905593
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544407840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_t
arget_stretch.544407840
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2590063374
Short name T132
Test name
Test status
Simulation time 83951697 ps
CPU time 2.26 seconds
Started Apr 30 01:40:24 PM PDT 24
Finished Apr 30 01:40:27 PM PDT 24
Peak memory 204264 kb
Host smart-ce6fd946-99b0-4f33-8fec-384eb794be1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590063374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2590063374
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.721661510
Short name T128
Test name
Test status
Simulation time 304073344 ps
CPU time 1.46 seconds
Started Apr 30 01:40:18 PM PDT 24
Finished Apr 30 01:40:20 PM PDT 24
Peak memory 204180 kb
Host smart-f95e53dd-f933-4fa9-827f-5f3816b427f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721661510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.721661510
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1168292634
Short name T137
Test name
Test status
Simulation time 300316762 ps
CPU time 2.13 seconds
Started Apr 30 01:40:30 PM PDT 24
Finished Apr 30 01:40:33 PM PDT 24
Peak memory 204276 kb
Host smart-5d6a36e1-4999-45e7-877c-a84e2dad566a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168292634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1168292634
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.3975889205
Short name T123
Test name
Test status
Simulation time 79796111 ps
CPU time 2.19 seconds
Started Apr 30 01:40:30 PM PDT 24
Finished Apr 30 01:40:33 PM PDT 24
Peak memory 204304 kb
Host smart-c2b19cd1-6bb5-4707-b772-c3701688b9dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975889205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.3975889205
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3004760594
Short name T136
Test name
Test status
Simulation time 83192073 ps
CPU time 1.45 seconds
Started Apr 30 01:40:35 PM PDT 24
Finished Apr 30 01:40:37 PM PDT 24
Peak memory 204280 kb
Host smart-cf99f50c-605b-4e81-a246-d24833977d65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004760594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.3004760594
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.764540238
Short name T120
Test name
Test status
Simulation time 284596245 ps
CPU time 2.18 seconds
Started Apr 30 01:40:36 PM PDT 24
Finished Apr 30 01:40:39 PM PDT 24
Peak memory 204240 kb
Host smart-abe2deca-61a0-4afe-8e31-4ae97c7572e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764540238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.764540238
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.1790927116
Short name T87
Test name
Test status
Simulation time 10084355341 ps
CPU time 60.58 seconds
Started Apr 30 01:53:41 PM PDT 24
Finished Apr 30 01:54:42 PM PDT 24
Peak memory 440148 kb
Host smart-1ef401c3-8a36-4728-ad1c-5926290abf8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790927116 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.1790927116
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.4001956032
Short name T150
Test name
Test status
Simulation time 336437152 ps
CPU time 2.25 seconds
Started Apr 30 01:40:18 PM PDT 24
Finished Apr 30 01:40:20 PM PDT 24
Peak memory 204280 kb
Host smart-0f6271ac-39d0-4444-bde2-6b8fd5dbd576
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001956032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.4001956032
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.4028459314
Short name T1451
Test name
Test status
Simulation time 467141285 ps
CPU time 3.26 seconds
Started Apr 30 01:40:17 PM PDT 24
Finished Apr 30 01:40:21 PM PDT 24
Peak memory 204276 kb
Host smart-3fbde1fb-9dac-4380-bd45-76fd355ad41b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028459314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.4028459314
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.125256203
Short name T148
Test name
Test status
Simulation time 39341028 ps
CPU time 0.68 seconds
Started Apr 30 01:40:21 PM PDT 24
Finished Apr 30 01:40:22 PM PDT 24
Peak memory 203980 kb
Host smart-5342a969-8672-4cd4-89d2-9f85860c85b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125256203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.125256203
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2106297329
Short name T1413
Test name
Test status
Simulation time 25959919 ps
CPU time 0.84 seconds
Started Apr 30 01:40:19 PM PDT 24
Finished Apr 30 01:40:21 PM PDT 24
Peak memory 204028 kb
Host smart-3e072eb2-f4e3-49a3-a6ca-7ba681ef12d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106297329 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2106297329
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.428203126
Short name T80
Test name
Test status
Simulation time 39278255 ps
CPU time 0.68 seconds
Started Apr 30 01:40:21 PM PDT 24
Finished Apr 30 01:40:22 PM PDT 24
Peak memory 203900 kb
Host smart-e2767036-daf8-4a21-b03f-664ce9dab04b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428203126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.428203126
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.3141970101
Short name T1423
Test name
Test status
Simulation time 48186954 ps
CPU time 0.68 seconds
Started Apr 30 01:40:18 PM PDT 24
Finished Apr 30 01:40:19 PM PDT 24
Peak memory 203972 kb
Host smart-d4985dbd-9791-45a3-961e-9efa8b117311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141970101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.3141970101
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.762528239
Short name T152
Test name
Test status
Simulation time 51789211 ps
CPU time 1.09 seconds
Started Apr 30 01:40:25 PM PDT 24
Finished Apr 30 01:40:27 PM PDT 24
Peak memory 204240 kb
Host smart-ee57ddf4-ee19-4c01-ba09-bc7ac2b781cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762528239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_out
standing.762528239
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.2412452081
Short name T1397
Test name
Test status
Simulation time 225032687 ps
CPU time 1.66 seconds
Started Apr 30 01:40:11 PM PDT 24
Finished Apr 30 01:40:14 PM PDT 24
Peak memory 204240 kb
Host smart-7a9b6d22-e459-4878-8f26-be751a1f5a8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412452081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2412452081
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.817254406
Short name T156
Test name
Test status
Simulation time 423389274 ps
CPU time 1.31 seconds
Started Apr 30 01:40:19 PM PDT 24
Finished Apr 30 01:40:21 PM PDT 24
Peak memory 204192 kb
Host smart-22022f3a-87d6-4231-a905-46997e02da87
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817254406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.817254406
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.1392072418
Short name T1373
Test name
Test status
Simulation time 19531881 ps
CPU time 0.71 seconds
Started Apr 30 01:40:25 PM PDT 24
Finished Apr 30 01:40:27 PM PDT 24
Peak memory 204056 kb
Host smart-dc177688-bc83-4b55-b9ec-63a316f3972a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392072418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.1392072418
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4040802754
Short name T1445
Test name
Test status
Simulation time 65967148 ps
CPU time 0.8 seconds
Started Apr 30 01:40:19 PM PDT 24
Finished Apr 30 01:40:21 PM PDT 24
Peak memory 204184 kb
Host smart-945b8dfe-e953-4773-b1e0-b85ff8602e8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040802754 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.4040802754
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3235837809
Short name T143
Test name
Test status
Simulation time 22692343 ps
CPU time 0.67 seconds
Started Apr 30 01:40:24 PM PDT 24
Finished Apr 30 01:40:25 PM PDT 24
Peak memory 203976 kb
Host smart-bb028fec-8d96-4512-ab5f-cd5d5bd73e44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235837809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.3235837809
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.4060408459
Short name T1442
Test name
Test status
Simulation time 58210085 ps
CPU time 0.67 seconds
Started Apr 30 01:40:24 PM PDT 24
Finished Apr 30 01:40:25 PM PDT 24
Peak memory 203992 kb
Host smart-dc6d2839-964d-4e00-be1a-83d92c288974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060408459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.4060408459
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1379723507
Short name T154
Test name
Test status
Simulation time 63017992 ps
CPU time 1.11 seconds
Started Apr 30 01:40:26 PM PDT 24
Finished Apr 30 01:40:28 PM PDT 24
Peak memory 204444 kb
Host smart-04c31e69-6726-4587-a070-a4d3197e915d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379723507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.1379723507
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2700848662
Short name T1393
Test name
Test status
Simulation time 139015312 ps
CPU time 2.29 seconds
Started Apr 30 01:40:26 PM PDT 24
Finished Apr 30 01:40:29 PM PDT 24
Peak memory 204204 kb
Host smart-ba257489-c321-4ebe-9437-47c2411e7ffd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700848662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2700848662
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.878180207
Short name T1399
Test name
Test status
Simulation time 45057629 ps
CPU time 0.98 seconds
Started Apr 30 01:40:33 PM PDT 24
Finished Apr 30 01:40:35 PM PDT 24
Peak memory 204352 kb
Host smart-48a30cc1-7e19-4e89-899d-2ac49821356d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878180207 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.878180207
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.737476308
Short name T1410
Test name
Test status
Simulation time 81699118 ps
CPU time 0.73 seconds
Started Apr 30 01:40:33 PM PDT 24
Finished Apr 30 01:40:34 PM PDT 24
Peak memory 204228 kb
Host smart-345f13c9-286e-4f12-b3c3-2972fddd886b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737476308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.737476308
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.774400766
Short name T1377
Test name
Test status
Simulation time 40854007 ps
CPU time 0.66 seconds
Started Apr 30 01:40:28 PM PDT 24
Finished Apr 30 01:40:29 PM PDT 24
Peak memory 203968 kb
Host smart-997e1d57-2f73-4eee-b949-daa4c7d37294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774400766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.774400766
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2400143145
Short name T1419
Test name
Test status
Simulation time 70715023 ps
CPU time 1.23 seconds
Started Apr 30 01:40:25 PM PDT 24
Finished Apr 30 01:40:27 PM PDT 24
Peak memory 204292 kb
Host smart-921a4234-7082-4c12-95aa-10d4533aa716
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400143145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.2400143145
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1176105467
Short name T135
Test name
Test status
Simulation time 30445045 ps
CPU time 1.48 seconds
Started Apr 30 01:40:35 PM PDT 24
Finished Apr 30 01:40:37 PM PDT 24
Peak memory 204260 kb
Host smart-b9ba8e6b-41c8-4593-ad08-af80b3a6af33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176105467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1176105467
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1909496664
Short name T1433
Test name
Test status
Simulation time 117479608 ps
CPU time 0.96 seconds
Started Apr 30 01:40:27 PM PDT 24
Finished Apr 30 01:40:29 PM PDT 24
Peak memory 204100 kb
Host smart-85873af3-50d8-46bf-99a7-7ca136dcd1ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909496664 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.1909496664
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1868041213
Short name T153
Test name
Test status
Simulation time 44363915 ps
CPU time 0.8 seconds
Started Apr 30 01:40:26 PM PDT 24
Finished Apr 30 01:40:28 PM PDT 24
Peak memory 204040 kb
Host smart-4f64423b-294b-4362-a06e-40c1b07a5da1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868041213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1868041213
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.1806004152
Short name T1396
Test name
Test status
Simulation time 17918039 ps
CPU time 0.65 seconds
Started Apr 30 01:40:26 PM PDT 24
Finished Apr 30 01:40:28 PM PDT 24
Peak memory 204000 kb
Host smart-176214c1-0959-4a3b-91f2-86bfba02ec70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806004152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1806004152
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.43818874
Short name T125
Test name
Test status
Simulation time 214025790 ps
CPU time 1.36 seconds
Started Apr 30 01:40:35 PM PDT 24
Finished Apr 30 01:40:37 PM PDT 24
Peak memory 204280 kb
Host smart-c2a1b5a7-f00b-4b5d-b6d6-62ce99f16c65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43818874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.43818874
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.467854623
Short name T119
Test name
Test status
Simulation time 52258081 ps
CPU time 0.92 seconds
Started Apr 30 01:40:35 PM PDT 24
Finished Apr 30 01:40:37 PM PDT 24
Peak memory 204168 kb
Host smart-b7361d26-0f5c-455c-8aa5-16e451617808
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467854623 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.467854623
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3177845894
Short name T1401
Test name
Test status
Simulation time 118428962 ps
CPU time 0.69 seconds
Started Apr 30 01:40:31 PM PDT 24
Finished Apr 30 01:40:32 PM PDT 24
Peak memory 203960 kb
Host smart-e20a4b71-4f2b-4619-806e-186958659a6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177845894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3177845894
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.3464723429
Short name T1405
Test name
Test status
Simulation time 22810872 ps
CPU time 0.68 seconds
Started Apr 30 01:40:27 PM PDT 24
Finished Apr 30 01:40:29 PM PDT 24
Peak memory 203944 kb
Host smart-56a36a21-baee-46d9-bd34-099ab9e03895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464723429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3464723429
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.1729488446
Short name T1418
Test name
Test status
Simulation time 947600795 ps
CPU time 1.55 seconds
Started Apr 30 01:40:32 PM PDT 24
Finished Apr 30 01:40:34 PM PDT 24
Peak memory 204192 kb
Host smart-740ed8cc-f9b9-4cf9-bab8-67a75a3c6851
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729488446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.1729488446
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1407493051
Short name T1391
Test name
Test status
Simulation time 94779605 ps
CPU time 2.52 seconds
Started Apr 30 01:40:32 PM PDT 24
Finished Apr 30 01:40:35 PM PDT 24
Peak memory 204420 kb
Host smart-589d079b-05c3-4bbe-8145-7418ab5149dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407493051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1407493051
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3444983701
Short name T1402
Test name
Test status
Simulation time 59050680 ps
CPU time 0.95 seconds
Started Apr 30 01:40:36 PM PDT 24
Finished Apr 30 01:40:38 PM PDT 24
Peak memory 204148 kb
Host smart-c67db078-fb22-446e-b91e-7d8007353571
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444983701 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.3444983701
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2639182886
Short name T149
Test name
Test status
Simulation time 51728315 ps
CPU time 0.67 seconds
Started Apr 30 01:40:34 PM PDT 24
Finished Apr 30 01:40:35 PM PDT 24
Peak memory 203980 kb
Host smart-181ef921-9bee-4497-8d72-bf0cc9a4578e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639182886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.2639182886
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.37583188
Short name T1428
Test name
Test status
Simulation time 51020626 ps
CPU time 0.66 seconds
Started Apr 30 01:40:35 PM PDT 24
Finished Apr 30 01:40:36 PM PDT 24
Peak memory 204000 kb
Host smart-2ee75691-a2ab-4686-965b-91f329e79f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37583188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.37583188
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1243857066
Short name T1443
Test name
Test status
Simulation time 177057991 ps
CPU time 1.24 seconds
Started Apr 30 01:40:33 PM PDT 24
Finished Apr 30 01:40:35 PM PDT 24
Peak memory 204248 kb
Host smart-08133ec7-8c96-4ac1-a45a-d9136420dfff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243857066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.1243857066
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3051201117
Short name T122
Test name
Test status
Simulation time 199984846 ps
CPU time 2.37 seconds
Started Apr 30 01:40:33 PM PDT 24
Finished Apr 30 01:40:36 PM PDT 24
Peak memory 204308 kb
Host smart-57b2897a-2964-4c26-bf5b-ffee68bc331e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051201117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3051201117
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.936334187
Short name T127
Test name
Test status
Simulation time 100850891 ps
CPU time 1.34 seconds
Started Apr 30 01:40:33 PM PDT 24
Finished Apr 30 01:40:35 PM PDT 24
Peak memory 212584 kb
Host smart-811cb154-386d-4165-b6a2-2d0ecfa63bb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936334187 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.936334187
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1365052752
Short name T81
Test name
Test status
Simulation time 17303190 ps
CPU time 0.7 seconds
Started Apr 30 01:40:33 PM PDT 24
Finished Apr 30 01:40:34 PM PDT 24
Peak memory 204004 kb
Host smart-5d0b03f6-1128-4ee3-8dac-bf02a95d8fce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365052752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1365052752
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.2979773275
Short name T1362
Test name
Test status
Simulation time 28099831 ps
CPU time 0.64 seconds
Started Apr 30 01:40:36 PM PDT 24
Finished Apr 30 01:40:37 PM PDT 24
Peak memory 203996 kb
Host smart-412b5ac0-adca-42a2-a2b2-b7af0c353416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979773275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.2979773275
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1028308224
Short name T1424
Test name
Test status
Simulation time 59892882 ps
CPU time 0.85 seconds
Started Apr 30 01:40:36 PM PDT 24
Finished Apr 30 01:40:37 PM PDT 24
Peak memory 204060 kb
Host smart-0ddb395e-3887-49c9-a548-19ed5e2f7c56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028308224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.1028308224
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2332553805
Short name T1386
Test name
Test status
Simulation time 43069207 ps
CPU time 1.15 seconds
Started Apr 30 01:40:34 PM PDT 24
Finished Apr 30 01:40:36 PM PDT 24
Peak memory 204204 kb
Host smart-f4fb9c14-61d8-47e1-9121-768f6bbab83e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332553805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2332553805
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.516917923
Short name T1438
Test name
Test status
Simulation time 133862437 ps
CPU time 0.81 seconds
Started Apr 30 01:40:36 PM PDT 24
Finished Apr 30 01:40:38 PM PDT 24
Peak memory 204172 kb
Host smart-00a9530c-399f-465b-b676-ad1073747714
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516917923 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.516917923
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.4257552925
Short name T1421
Test name
Test status
Simulation time 65065471 ps
CPU time 0.68 seconds
Started Apr 30 01:40:34 PM PDT 24
Finished Apr 30 01:40:36 PM PDT 24
Peak memory 204016 kb
Host smart-7e4ee2bb-47ec-4f37-88a0-f0f70eaf742b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257552925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.4257552925
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.1822238951
Short name T1457
Test name
Test status
Simulation time 47737365 ps
CPU time 0.67 seconds
Started Apr 30 01:40:36 PM PDT 24
Finished Apr 30 01:40:38 PM PDT 24
Peak memory 204008 kb
Host smart-36b1b2db-9ba3-4f0e-b274-5bead4c26b93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822238951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1822238951
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1031993682
Short name T1447
Test name
Test status
Simulation time 50209658 ps
CPU time 0.83 seconds
Started Apr 30 01:40:33 PM PDT 24
Finished Apr 30 01:40:34 PM PDT 24
Peak memory 204176 kb
Host smart-607a2458-b5c2-4e0d-95bc-a690d27c000d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031993682 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1031993682
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3883469363
Short name T1380
Test name
Test status
Simulation time 19575319 ps
CPU time 0.71 seconds
Started Apr 30 01:40:34 PM PDT 24
Finished Apr 30 01:40:36 PM PDT 24
Peak memory 203952 kb
Host smart-0c749bf4-70da-4e48-97ac-f69200ad34e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883469363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.3883469363
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.2274975127
Short name T1453
Test name
Test status
Simulation time 19183806 ps
CPU time 0.66 seconds
Started Apr 30 01:40:34 PM PDT 24
Finished Apr 30 01:40:36 PM PDT 24
Peak memory 203980 kb
Host smart-0b5c868b-ce3f-4b11-8646-4623b7a7cb29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274975127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2274975127
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.264043255
Short name T1454
Test name
Test status
Simulation time 101992513 ps
CPU time 1.41 seconds
Started Apr 30 01:40:33 PM PDT 24
Finished Apr 30 01:40:35 PM PDT 24
Peak memory 204284 kb
Host smart-ffaf5f0c-401a-49aa-ab6d-38acacde5723
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264043255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.264043255
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.1620573161
Short name T1422
Test name
Test status
Simulation time 85939035 ps
CPU time 0.66 seconds
Started Apr 30 01:40:34 PM PDT 24
Finished Apr 30 01:40:35 PM PDT 24
Peak memory 204004 kb
Host smart-cd65076d-db92-4a2b-8b6d-5122b333e87b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620573161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.1620573161
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.2037265317
Short name T1379
Test name
Test status
Simulation time 18419324 ps
CPU time 0.67 seconds
Started Apr 30 01:40:32 PM PDT 24
Finished Apr 30 01:40:33 PM PDT 24
Peak memory 203972 kb
Host smart-20438379-1f2c-4d2c-90f1-6b63f24ca784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037265317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2037265317
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.4135342506
Short name T105
Test name
Test status
Simulation time 30874531 ps
CPU time 1.39 seconds
Started Apr 30 01:40:41 PM PDT 24
Finished Apr 30 01:40:43 PM PDT 24
Peak memory 204276 kb
Host smart-892ff43e-74a7-476f-ba41-592658f57cc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135342506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.4135342506
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2475214614
Short name T130
Test name
Test status
Simulation time 155032668 ps
CPU time 1.43 seconds
Started Apr 30 01:40:33 PM PDT 24
Finished Apr 30 01:40:35 PM PDT 24
Peak memory 204264 kb
Host smart-0ca96269-ff5f-4803-939e-b5de7e103a54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475214614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.2475214614
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1017302852
Short name T1437
Test name
Test status
Simulation time 65916590 ps
CPU time 0.79 seconds
Started Apr 30 01:40:46 PM PDT 24
Finished Apr 30 01:40:47 PM PDT 24
Peak memory 204056 kb
Host smart-2e05d36c-f4fb-44f1-9bcb-c9ecd0c70862
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017302852 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1017302852
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2046439285
Short name T1440
Test name
Test status
Simulation time 38839340 ps
CPU time 0.68 seconds
Started Apr 30 01:40:42 PM PDT 24
Finished Apr 30 01:40:43 PM PDT 24
Peak memory 204036 kb
Host smart-6064b0d1-54b5-49eb-bd1b-e66adb67e277
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046439285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2046439285
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.2376610175
Short name T1409
Test name
Test status
Simulation time 46795841 ps
CPU time 0.67 seconds
Started Apr 30 01:40:33 PM PDT 24
Finished Apr 30 01:40:35 PM PDT 24
Peak memory 203404 kb
Host smart-e293e796-e61d-4805-ba18-852bf1a4ee07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376610175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.2376610175
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2453758499
Short name T157
Test name
Test status
Simulation time 90871423 ps
CPU time 2 seconds
Started Apr 30 01:40:34 PM PDT 24
Finished Apr 30 01:40:36 PM PDT 24
Peak memory 204300 kb
Host smart-7f5d52a7-d702-47af-8d89-76386a3b6189
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453758499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2453758499
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3268349499
Short name T1383
Test name
Test status
Simulation time 69544837 ps
CPU time 0.79 seconds
Started Apr 30 01:40:46 PM PDT 24
Finished Apr 30 01:40:48 PM PDT 24
Peak memory 204068 kb
Host smart-6f1689c5-03c2-4ee4-a48a-737c8c7c6bb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268349499 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3268349499
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.1169062511
Short name T147
Test name
Test status
Simulation time 16783414 ps
CPU time 0.7 seconds
Started Apr 30 01:40:44 PM PDT 24
Finished Apr 30 01:40:45 PM PDT 24
Peak memory 203984 kb
Host smart-5b094e28-edc9-4ed8-83f6-24cd88a34141
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169062511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.1169062511
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.881649585
Short name T1381
Test name
Test status
Simulation time 22499123 ps
CPU time 0.69 seconds
Started Apr 30 01:40:44 PM PDT 24
Finished Apr 30 01:40:45 PM PDT 24
Peak memory 203948 kb
Host smart-ad7380eb-0506-473a-ba52-086fb44dcc92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881649585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.881649585
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.2382085191
Short name T1420
Test name
Test status
Simulation time 129170657 ps
CPU time 2.63 seconds
Started Apr 30 01:40:46 PM PDT 24
Finished Apr 30 01:40:50 PM PDT 24
Peak memory 204280 kb
Host smart-1fdd332e-2494-499f-918b-f19ef2db2329
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382085191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2382085191
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.1641328873
Short name T1406
Test name
Test status
Simulation time 209380410 ps
CPU time 2.19 seconds
Started Apr 30 01:40:40 PM PDT 24
Finished Apr 30 01:40:43 PM PDT 24
Peak memory 204252 kb
Host smart-0d92a1d6-b12e-4f83-a28c-47da9869c36e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641328873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1641328873
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1569036116
Short name T1390
Test name
Test status
Simulation time 245365203 ps
CPU time 3.04 seconds
Started Apr 30 01:40:19 PM PDT 24
Finished Apr 30 01:40:23 PM PDT 24
Peak memory 204228 kb
Host smart-68185b5c-5d2b-4bef-a96a-bebc16c56903
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569036116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.1569036116
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2160948275
Short name T1387
Test name
Test status
Simulation time 32959461 ps
CPU time 1.39 seconds
Started Apr 30 01:40:19 PM PDT 24
Finished Apr 30 01:40:21 PM PDT 24
Peak memory 204220 kb
Host smart-be4a4ee8-91b3-4366-8b7b-4cd2716a0d29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160948275 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.2160948275
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.496470243
Short name T1456
Test name
Test status
Simulation time 49183028 ps
CPU time 0.73 seconds
Started Apr 30 01:40:24 PM PDT 24
Finished Apr 30 01:40:25 PM PDT 24
Peak memory 204060 kb
Host smart-33af8cda-502f-4f63-b613-760d44c9c1f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496470243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.496470243
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1269485043
Short name T1365
Test name
Test status
Simulation time 66303196 ps
CPU time 0.67 seconds
Started Apr 30 01:40:19 PM PDT 24
Finished Apr 30 01:40:21 PM PDT 24
Peak memory 203996 kb
Host smart-2232908b-752c-461b-a233-d73cf07e53ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269485043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1269485043
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2019485291
Short name T1400
Test name
Test status
Simulation time 223791670 ps
CPU time 2.37 seconds
Started Apr 30 01:40:18 PM PDT 24
Finished Apr 30 01:40:21 PM PDT 24
Peak memory 204300 kb
Host smart-c3f15ef5-3d7f-47e2-94e5-205dad1fe5cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019485291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.2019485291
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1626342603
Short name T218
Test name
Test status
Simulation time 294576972 ps
CPU time 1.38 seconds
Started Apr 30 01:40:19 PM PDT 24
Finished Apr 30 01:40:21 PM PDT 24
Peak memory 204272 kb
Host smart-2cb870fe-7653-47ef-9eef-b44e495250e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626342603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.1626342603
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.1643904006
Short name T1412
Test name
Test status
Simulation time 36141481 ps
CPU time 0.67 seconds
Started Apr 30 01:40:41 PM PDT 24
Finished Apr 30 01:40:42 PM PDT 24
Peak memory 204020 kb
Host smart-1200830b-5ab3-4e34-8c4a-db4f3c7ab20a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643904006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.1643904006
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.1062964558
Short name T1430
Test name
Test status
Simulation time 23906182 ps
CPU time 0.71 seconds
Started Apr 30 01:40:43 PM PDT 24
Finished Apr 30 01:40:44 PM PDT 24
Peak memory 203976 kb
Host smart-ce3b7d2e-db35-4c25-98e7-962ebd1d2ed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062964558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1062964558
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.1257123699
Short name T1417
Test name
Test status
Simulation time 40757086 ps
CPU time 0.66 seconds
Started Apr 30 01:40:41 PM PDT 24
Finished Apr 30 01:40:43 PM PDT 24
Peak memory 203988 kb
Host smart-dae6d461-2969-4ca1-946a-a22990cc835a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257123699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1257123699
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.619196193
Short name T1366
Test name
Test status
Simulation time 49605196 ps
CPU time 0.68 seconds
Started Apr 30 01:40:46 PM PDT 24
Finished Apr 30 01:40:47 PM PDT 24
Peak memory 204004 kb
Host smart-a38102a9-e88d-476c-856e-99b34881d662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619196193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.619196193
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.2090740353
Short name T1444
Test name
Test status
Simulation time 17290244 ps
CPU time 0.68 seconds
Started Apr 30 01:40:43 PM PDT 24
Finished Apr 30 01:40:45 PM PDT 24
Peak memory 203932 kb
Host smart-e1800e40-74e9-4a93-b423-e7dd1e37543a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090740353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2090740353
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.1577515830
Short name T1425
Test name
Test status
Simulation time 21822980 ps
CPU time 0.68 seconds
Started Apr 30 01:40:43 PM PDT 24
Finished Apr 30 01:40:44 PM PDT 24
Peak memory 203932 kb
Host smart-3294cb8f-96ba-48ba-81be-d8837727fb7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577515830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.1577515830
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.1512816750
Short name T1450
Test name
Test status
Simulation time 58786441 ps
CPU time 0.65 seconds
Started Apr 30 01:40:40 PM PDT 24
Finished Apr 30 01:40:41 PM PDT 24
Peak memory 204016 kb
Host smart-fdb8a277-8a37-426a-b425-64d2c08f43e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512816750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1512816750
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.2216136522
Short name T1378
Test name
Test status
Simulation time 50332729 ps
CPU time 0.66 seconds
Started Apr 30 01:40:39 PM PDT 24
Finished Apr 30 01:40:40 PM PDT 24
Peak memory 204008 kb
Host smart-1276277b-ca2b-42fa-b488-ec6101d9350a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216136522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2216136522
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.3073265792
Short name T1369
Test name
Test status
Simulation time 19650785 ps
CPU time 0.7 seconds
Started Apr 30 01:40:44 PM PDT 24
Finished Apr 30 01:40:45 PM PDT 24
Peak memory 203988 kb
Host smart-3415ddda-5c73-494f-b5ac-6e1c72e96d8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073265792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3073265792
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.3180694143
Short name T1364
Test name
Test status
Simulation time 23393619 ps
CPU time 0.73 seconds
Started Apr 30 01:40:42 PM PDT 24
Finished Apr 30 01:40:43 PM PDT 24
Peak memory 203976 kb
Host smart-71be5a04-66c0-4367-8370-fa8df5015674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180694143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3180694143
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1095510126
Short name T146
Test name
Test status
Simulation time 137975941 ps
CPU time 2.11 seconds
Started Apr 30 01:40:18 PM PDT 24
Finished Apr 30 01:40:21 PM PDT 24
Peak memory 204228 kb
Host smart-3864b31c-949d-4c4a-a13a-d987a6d8d64a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095510126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1095510126
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3562064254
Short name T145
Test name
Test status
Simulation time 66998821 ps
CPU time 0.8 seconds
Started Apr 30 01:40:25 PM PDT 24
Finished Apr 30 01:40:26 PM PDT 24
Peak memory 204000 kb
Host smart-c986db32-e185-480f-b871-1b979c918038
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562064254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3562064254
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.300919932
Short name T1411
Test name
Test status
Simulation time 64453920 ps
CPU time 0.9 seconds
Started Apr 30 01:40:25 PM PDT 24
Finished Apr 30 01:40:27 PM PDT 24
Peak memory 204016 kb
Host smart-f9817850-0051-4b3a-9353-77c8eee2efcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300919932 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.300919932
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3675418866
Short name T151
Test name
Test status
Simulation time 52789556 ps
CPU time 0.69 seconds
Started Apr 30 01:40:26 PM PDT 24
Finished Apr 30 01:40:27 PM PDT 24
Peak memory 204052 kb
Host smart-5e46572b-5f55-49ca-b664-46b3057311ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675418866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3675418866
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.4161505171
Short name T1404
Test name
Test status
Simulation time 16422026 ps
CPU time 0.66 seconds
Started Apr 30 01:40:25 PM PDT 24
Finished Apr 30 01:40:27 PM PDT 24
Peak memory 203976 kb
Host smart-3b8a0d4c-2810-4b64-826b-3cb6db457f37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161505171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.4161505171
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.869172472
Short name T1439
Test name
Test status
Simulation time 84624647 ps
CPU time 1.17 seconds
Started Apr 30 01:40:17 PM PDT 24
Finished Apr 30 01:40:18 PM PDT 24
Peak memory 204256 kb
Host smart-198f32fe-ad63-4784-b838-33fdfe714c2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869172472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.869172472
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.4129186533
Short name T1434
Test name
Test status
Simulation time 328908570 ps
CPU time 1.61 seconds
Started Apr 30 01:40:25 PM PDT 24
Finished Apr 30 01:40:27 PM PDT 24
Peak memory 204264 kb
Host smart-b816ac0f-8688-4053-bc82-d3569163fc7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129186533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.4129186533
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.1843248020
Short name T1416
Test name
Test status
Simulation time 14696739 ps
CPU time 0.64 seconds
Started Apr 30 01:40:42 PM PDT 24
Finished Apr 30 01:40:44 PM PDT 24
Peak memory 204000 kb
Host smart-d4ef093e-95e4-43a0-9b08-b2e1b529e7aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843248020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1843248020
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.3463404840
Short name T1368
Test name
Test status
Simulation time 14704654 ps
CPU time 0.66 seconds
Started Apr 30 01:40:41 PM PDT 24
Finished Apr 30 01:40:42 PM PDT 24
Peak memory 203996 kb
Host smart-6596bafe-0092-48fc-a3c3-873265757f76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463404840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3463404840
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.3478721822
Short name T1367
Test name
Test status
Simulation time 28881682 ps
CPU time 0.65 seconds
Started Apr 30 01:40:41 PM PDT 24
Finished Apr 30 01:40:42 PM PDT 24
Peak memory 203972 kb
Host smart-0f1d76f2-f621-4722-9ecc-ad137777dd77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478721822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.3478721822
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.1497399111
Short name T1441
Test name
Test status
Simulation time 47548837 ps
CPU time 0.65 seconds
Started Apr 30 01:40:46 PM PDT 24
Finished Apr 30 01:40:47 PM PDT 24
Peak memory 204004 kb
Host smart-fdb16b23-0d9b-4706-a0fa-9c3e9b4e95b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497399111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1497399111
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.1618979243
Short name T1432
Test name
Test status
Simulation time 15170192 ps
CPU time 0.69 seconds
Started Apr 30 01:40:45 PM PDT 24
Finished Apr 30 01:40:47 PM PDT 24
Peak memory 203960 kb
Host smart-d239fb23-fc77-48c7-b042-d9122b0c4572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618979243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1618979243
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.1644413612
Short name T1398
Test name
Test status
Simulation time 17307009 ps
CPU time 0.71 seconds
Started Apr 30 01:40:41 PM PDT 24
Finished Apr 30 01:40:43 PM PDT 24
Peak memory 203988 kb
Host smart-e5edce30-b1c7-4416-9901-cf322ab5a809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644413612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1644413612
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1096772165
Short name T1414
Test name
Test status
Simulation time 17185299 ps
CPU time 0.67 seconds
Started Apr 30 01:40:43 PM PDT 24
Finished Apr 30 01:40:44 PM PDT 24
Peak memory 204000 kb
Host smart-7a7395c9-83d1-432a-9531-2070f0f82751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096772165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1096772165
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.1046454435
Short name T1388
Test name
Test status
Simulation time 63805778 ps
CPU time 0.7 seconds
Started Apr 30 01:40:42 PM PDT 24
Finished Apr 30 01:40:43 PM PDT 24
Peak memory 203984 kb
Host smart-779e8d9b-8b88-41b6-ac87-eff074b88cff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046454435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1046454435
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.1690239706
Short name T1374
Test name
Test status
Simulation time 138734037 ps
CPU time 0.7 seconds
Started Apr 30 01:40:45 PM PDT 24
Finished Apr 30 01:40:46 PM PDT 24
Peak memory 203788 kb
Host smart-38a7954b-a0e5-4e36-bc8c-fad5a4319b49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690239706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1690239706
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1961866346
Short name T1452
Test name
Test status
Simulation time 15309494 ps
CPU time 0.67 seconds
Started Apr 30 01:40:44 PM PDT 24
Finished Apr 30 01:40:45 PM PDT 24
Peak memory 204016 kb
Host smart-408bf418-da20-4cba-8f44-74f50c04c5a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961866346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1961866346
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.474969290
Short name T1392
Test name
Test status
Simulation time 396539628 ps
CPU time 2.16 seconds
Started Apr 30 01:40:21 PM PDT 24
Finished Apr 30 01:40:24 PM PDT 24
Peak memory 204180 kb
Host smart-fafacf43-f3c1-4d1e-a24d-b8a2a271937e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474969290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.474969290
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3899055707
Short name T260
Test name
Test status
Simulation time 27688196 ps
CPU time 0.77 seconds
Started Apr 30 01:40:19 PM PDT 24
Finished Apr 30 01:40:21 PM PDT 24
Peak memory 203984 kb
Host smart-93322025-b0e2-487a-9856-fbac40ded21b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899055707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3899055707
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3818857838
Short name T129
Test name
Test status
Simulation time 37919294 ps
CPU time 1.1 seconds
Started Apr 30 01:40:29 PM PDT 24
Finished Apr 30 01:40:30 PM PDT 24
Peak memory 204100 kb
Host smart-9331dc40-c3cf-4572-a8d5-fffee6543f03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818857838 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3818857838
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.282162477
Short name T142
Test name
Test status
Simulation time 23519889 ps
CPU time 0.78 seconds
Started Apr 30 01:40:21 PM PDT 24
Finished Apr 30 01:40:22 PM PDT 24
Peak memory 203904 kb
Host smart-a412c801-aa08-4733-86d0-4033c3b368ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282162477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.282162477
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.4197892605
Short name T1363
Test name
Test status
Simulation time 15718441 ps
CPU time 0.69 seconds
Started Apr 30 01:40:27 PM PDT 24
Finished Apr 30 01:40:28 PM PDT 24
Peak memory 204200 kb
Host smart-ceb81d09-4650-43d2-9a86-cc7391639cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197892605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.4197892605
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2926579900
Short name T1415
Test name
Test status
Simulation time 19821527 ps
CPU time 0.91 seconds
Started Apr 30 01:40:27 PM PDT 24
Finished Apr 30 01:40:28 PM PDT 24
Peak memory 204240 kb
Host smart-9fc49bb6-c7e6-455c-8c20-2994ecaf6383
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926579900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.2926579900
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1634592483
Short name T121
Test name
Test status
Simulation time 267913135 ps
CPU time 1.69 seconds
Started Apr 30 01:40:26 PM PDT 24
Finished Apr 30 01:40:28 PM PDT 24
Peak memory 204236 kb
Host smart-3a86a415-bdc3-47fb-aada-3ba36a11ccd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634592483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.1634592483
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.4153871404
Short name T1382
Test name
Test status
Simulation time 52040183 ps
CPU time 0.66 seconds
Started Apr 30 01:40:45 PM PDT 24
Finished Apr 30 01:40:46 PM PDT 24
Peak memory 203996 kb
Host smart-0fdd6419-a901-45be-a203-199ebbf73916
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153871404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.4153871404
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.2188170491
Short name T1375
Test name
Test status
Simulation time 108492358 ps
CPU time 0.67 seconds
Started Apr 30 01:40:43 PM PDT 24
Finished Apr 30 01:40:44 PM PDT 24
Peak memory 203972 kb
Host smart-f4c973ac-1976-4c82-a15a-22e5f33a7eb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188170491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2188170491
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.1469346443
Short name T1446
Test name
Test status
Simulation time 36585506 ps
CPU time 0.69 seconds
Started Apr 30 01:40:43 PM PDT 24
Finished Apr 30 01:40:45 PM PDT 24
Peak memory 203944 kb
Host smart-0f6a4983-ed3a-4a4f-8229-26822ba4fcb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469346443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.1469346443
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.1873267163
Short name T1427
Test name
Test status
Simulation time 25305313 ps
CPU time 0.67 seconds
Started Apr 30 01:40:45 PM PDT 24
Finished Apr 30 01:40:46 PM PDT 24
Peak memory 203708 kb
Host smart-c187c4c3-a85f-489c-af7c-9f247c5cfec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873267163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1873267163
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.2028646366
Short name T1403
Test name
Test status
Simulation time 15516555 ps
CPU time 0.69 seconds
Started Apr 30 01:40:44 PM PDT 24
Finished Apr 30 01:40:46 PM PDT 24
Peak memory 204004 kb
Host smart-1aec76a7-a86d-4a29-bc0c-73254fb4277b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028646366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2028646366
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2968092091
Short name T1361
Test name
Test status
Simulation time 31271193 ps
CPU time 0.67 seconds
Started Apr 30 01:40:46 PM PDT 24
Finished Apr 30 01:40:48 PM PDT 24
Peak memory 203988 kb
Host smart-5c19e5de-9fbf-44d3-aeaf-6d78c46ed317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968092091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2968092091
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.3327585321
Short name T1372
Test name
Test status
Simulation time 15803009 ps
CPU time 0.66 seconds
Started Apr 30 01:40:42 PM PDT 24
Finished Apr 30 01:40:44 PM PDT 24
Peak memory 203980 kb
Host smart-261d3497-51ce-408b-83f8-2ee1b6ac465d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327585321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.3327585321
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.3421288579
Short name T1384
Test name
Test status
Simulation time 20546429 ps
CPU time 0.63 seconds
Started Apr 30 01:40:42 PM PDT 24
Finished Apr 30 01:40:43 PM PDT 24
Peak memory 203188 kb
Host smart-76189268-67fc-498e-9411-82bd6002d7b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421288579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3421288579
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.1617482778
Short name T1376
Test name
Test status
Simulation time 17981216 ps
CPU time 0.66 seconds
Started Apr 30 01:40:43 PM PDT 24
Finished Apr 30 01:40:45 PM PDT 24
Peak memory 203876 kb
Host smart-d38adf92-9191-4ebc-946d-4695b76744d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617482778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.1617482778
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.276235811
Short name T1370
Test name
Test status
Simulation time 42651799 ps
CPU time 0.67 seconds
Started Apr 30 01:40:44 PM PDT 24
Finished Apr 30 01:40:45 PM PDT 24
Peak memory 203212 kb
Host smart-27b58482-779f-4ceb-b6ec-b0e90dbe2ba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276235811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.276235811
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.17131535
Short name T1436
Test name
Test status
Simulation time 29699111 ps
CPU time 1.27 seconds
Started Apr 30 01:40:28 PM PDT 24
Finished Apr 30 01:40:30 PM PDT 24
Peak memory 204308 kb
Host smart-3c1362d3-d850-4d29-93ac-b3238d1a8635
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17131535 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.17131535
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.923852147
Short name T141
Test name
Test status
Simulation time 67346896 ps
CPU time 0.7 seconds
Started Apr 30 01:40:31 PM PDT 24
Finished Apr 30 01:40:32 PM PDT 24
Peak memory 204012 kb
Host smart-d3e77ff8-6379-4661-9b45-7ea4a218613f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923852147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.923852147
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.222495555
Short name T1385
Test name
Test status
Simulation time 20059493 ps
CPU time 0.69 seconds
Started Apr 30 01:40:26 PM PDT 24
Finished Apr 30 01:40:27 PM PDT 24
Peak memory 203980 kb
Host smart-38f06ac0-4f51-4b6f-9a04-27e9cd2695c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222495555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.222495555
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.435636698
Short name T1455
Test name
Test status
Simulation time 36095756 ps
CPU time 0.89 seconds
Started Apr 30 01:40:30 PM PDT 24
Finished Apr 30 01:40:32 PM PDT 24
Peak memory 204048 kb
Host smart-bf83bdec-0f79-412d-b84b-5126d67376cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435636698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_out
standing.435636698
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3667967247
Short name T1435
Test name
Test status
Simulation time 210649602 ps
CPU time 1.48 seconds
Started Apr 30 01:40:28 PM PDT 24
Finished Apr 30 01:40:30 PM PDT 24
Peak memory 204236 kb
Host smart-630c1f85-10ed-437e-83f3-ee2e5b7b0202
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667967247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3667967247
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.4151471321
Short name T134
Test name
Test status
Simulation time 260724606 ps
CPU time 1.5 seconds
Started Apr 30 01:40:26 PM PDT 24
Finished Apr 30 01:40:28 PM PDT 24
Peak memory 204260 kb
Host smart-2a9405f7-6232-4286-a57a-82879ca87066
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151471321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.4151471321
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3521389673
Short name T159
Test name
Test status
Simulation time 127554703 ps
CPU time 0.96 seconds
Started Apr 30 01:40:26 PM PDT 24
Finished Apr 30 01:40:28 PM PDT 24
Peak memory 204148 kb
Host smart-a89b83eb-c0c0-41e5-b0a3-32cb3dae52d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521389673 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3521389673
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.3549376017
Short name T1448
Test name
Test status
Simulation time 39717178 ps
CPU time 0.7 seconds
Started Apr 30 01:40:27 PM PDT 24
Finished Apr 30 01:40:29 PM PDT 24
Peak memory 204104 kb
Host smart-db91a674-20f0-4544-803b-42269e505072
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549376017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.3549376017
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1691380604
Short name T1394
Test name
Test status
Simulation time 44163863 ps
CPU time 0.65 seconds
Started Apr 30 01:40:28 PM PDT 24
Finished Apr 30 01:40:29 PM PDT 24
Peak memory 203976 kb
Host smart-9935c09e-fceb-4901-b6f6-51a932dcc32d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691380604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1691380604
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.233228985
Short name T155
Test name
Test status
Simulation time 313355193 ps
CPU time 1.16 seconds
Started Apr 30 01:40:25 PM PDT 24
Finished Apr 30 01:40:27 PM PDT 24
Peak memory 204232 kb
Host smart-4fed16ec-f046-40b9-a885-abc670aa194e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233228985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_out
standing.233228985
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2615051256
Short name T1389
Test name
Test status
Simulation time 136544178 ps
CPU time 2.16 seconds
Started Apr 30 01:40:25 PM PDT 24
Finished Apr 30 01:40:27 PM PDT 24
Peak memory 204224 kb
Host smart-f3bc13c8-d5f5-4b7d-9bb8-b49a88317efe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615051256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2615051256
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4141573760
Short name T219
Test name
Test status
Simulation time 208839775 ps
CPU time 1.28 seconds
Started Apr 30 01:40:28 PM PDT 24
Finished Apr 30 01:40:30 PM PDT 24
Peak memory 204288 kb
Host smart-65690ff9-77bd-4af9-808b-c7fd92ac242b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141573760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.4141573760
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.336630446
Short name T1395
Test name
Test status
Simulation time 85100965 ps
CPU time 1.17 seconds
Started Apr 30 01:40:26 PM PDT 24
Finished Apr 30 01:40:28 PM PDT 24
Peak memory 204332 kb
Host smart-7a6ce2a2-c0f2-4101-b101-c51ecbbeb8ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336630446 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.336630446
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.1270394260
Short name T1371
Test name
Test status
Simulation time 30722927 ps
CPU time 0.67 seconds
Started Apr 30 01:40:33 PM PDT 24
Finished Apr 30 01:40:34 PM PDT 24
Peak memory 204192 kb
Host smart-61fbcfa2-d8f4-404e-a3de-9b2c00a7a93c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270394260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1270394260
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1074814613
Short name T1429
Test name
Test status
Simulation time 61194847 ps
CPU time 0.95 seconds
Started Apr 30 01:40:27 PM PDT 24
Finished Apr 30 01:40:29 PM PDT 24
Peak memory 203992 kb
Host smart-393c81ff-d305-43c5-b325-e82aa39184da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074814613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.1074814613
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1693409131
Short name T126
Test name
Test status
Simulation time 46784814 ps
CPU time 2.15 seconds
Started Apr 30 01:40:28 PM PDT 24
Finished Apr 30 01:40:31 PM PDT 24
Peak memory 204208 kb
Host smart-82785591-83a6-4175-bfb9-a166fd7854df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693409131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.1693409131
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2947452776
Short name T131
Test name
Test status
Simulation time 81476892 ps
CPU time 1.53 seconds
Started Apr 30 01:40:23 PM PDT 24
Finished Apr 30 01:40:25 PM PDT 24
Peak memory 204224 kb
Host smart-2165847b-4434-4587-a03a-a980e1bb03a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947452776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2947452776
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3464927753
Short name T1449
Test name
Test status
Simulation time 69149860 ps
CPU time 1.11 seconds
Started Apr 30 01:40:31 PM PDT 24
Finished Apr 30 01:40:33 PM PDT 24
Peak memory 204260 kb
Host smart-62638a93-569e-4b24-ac9a-539a15eb97b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464927753 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.3464927753
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2759571835
Short name T144
Test name
Test status
Simulation time 19396373 ps
CPU time 0.81 seconds
Started Apr 30 01:40:26 PM PDT 24
Finished Apr 30 01:40:28 PM PDT 24
Peak memory 204104 kb
Host smart-4bed696d-6df3-41d1-9335-e4db1ececd29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759571835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2759571835
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1591271835
Short name T175
Test name
Test status
Simulation time 162284218 ps
CPU time 0.61 seconds
Started Apr 30 01:40:25 PM PDT 24
Finished Apr 30 01:40:26 PM PDT 24
Peak memory 204016 kb
Host smart-95c6ad1d-76ce-41a1-bb32-17366f113d2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591271835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1591271835
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1228253414
Short name T1426
Test name
Test status
Simulation time 200692511 ps
CPU time 1.16 seconds
Started Apr 30 01:40:29 PM PDT 24
Finished Apr 30 01:40:30 PM PDT 24
Peak memory 204324 kb
Host smart-282df7e7-04c1-4dd3-b254-22f45ef25251
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228253414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.1228253414
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3341211795
Short name T1431
Test name
Test status
Simulation time 73292522 ps
CPU time 1.26 seconds
Started Apr 30 01:40:28 PM PDT 24
Finished Apr 30 01:40:30 PM PDT 24
Peak memory 204244 kb
Host smart-1562c12d-d2da-4995-b405-3556048d14f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341211795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3341211795
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.261069926
Short name T138
Test name
Test status
Simulation time 92662409 ps
CPU time 1.51 seconds
Started Apr 30 01:40:35 PM PDT 24
Finished Apr 30 01:40:37 PM PDT 24
Peak memory 204260 kb
Host smart-20c88742-be37-4d59-b86c-e0de2ee4f1b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261069926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.261069926
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.4008099567
Short name T158
Test name
Test status
Simulation time 50782792 ps
CPU time 0.94 seconds
Started Apr 30 01:40:35 PM PDT 24
Finished Apr 30 01:40:37 PM PDT 24
Peak memory 204172 kb
Host smart-051a6fd3-3bc6-4064-b716-f056df46e3c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008099567 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.4008099567
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.8741766
Short name T1408
Test name
Test status
Simulation time 78683516 ps
CPU time 0.68 seconds
Started Apr 30 01:40:31 PM PDT 24
Finished Apr 30 01:40:32 PM PDT 24
Peak memory 204024 kb
Host smart-1eb8ebee-1789-4e8c-96dc-65e11eb01d3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8741766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.8741766
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.1981342929
Short name T1407
Test name
Test status
Simulation time 73771774 ps
CPU time 1.29 seconds
Started Apr 30 01:40:26 PM PDT 24
Finished Apr 30 01:40:28 PM PDT 24
Peak memory 204204 kb
Host smart-b60175b0-cd73-424b-9db5-d4cbb44e86d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981342929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.1981342929
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.962008399
Short name T133
Test name
Test status
Simulation time 220414318 ps
CPU time 1.55 seconds
Started Apr 30 01:40:26 PM PDT 24
Finished Apr 30 01:40:28 PM PDT 24
Peak memory 204296 kb
Host smart-cdca4032-e5c8-40d7-ba56-3b8a6dbb4a13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962008399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.962008399
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.656569747
Short name T990
Test name
Test status
Simulation time 20191597 ps
CPU time 0.66 seconds
Started Apr 30 01:52:30 PM PDT 24
Finished Apr 30 01:52:31 PM PDT 24
Peak memory 203900 kb
Host smart-c529d7f9-17f4-435d-93c0-18d345f9bf12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656569747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.656569747
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.2418382923
Short name T1105
Test name
Test status
Simulation time 165803319 ps
CPU time 1.77 seconds
Started Apr 30 01:52:23 PM PDT 24
Finished Apr 30 01:52:25 PM PDT 24
Peak memory 212436 kb
Host smart-ed8aded1-d0f7-47ef-bfcb-882ea22d9b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418382923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2418382923
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.852172099
Short name T495
Test name
Test status
Simulation time 416187941 ps
CPU time 6.17 seconds
Started Apr 30 01:52:17 PM PDT 24
Finished Apr 30 01:52:24 PM PDT 24
Peak memory 247540 kb
Host smart-5d027442-ab57-4a28-9ec5-74258e7d1bae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852172099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty
.852172099
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3787481899
Short name T733
Test name
Test status
Simulation time 4713177593 ps
CPU time 74.42 seconds
Started Apr 30 01:52:29 PM PDT 24
Finished Apr 30 01:53:43 PM PDT 24
Peak memory 698700 kb
Host smart-2b2a2be8-0e4a-405c-8d44-f983adb7c889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787481899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3787481899
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.3932323050
Short name T1141
Test name
Test status
Simulation time 2230435578 ps
CPU time 65.8 seconds
Started Apr 30 01:52:18 PM PDT 24
Finished Apr 30 01:53:24 PM PDT 24
Peak memory 696680 kb
Host smart-bba09b7b-bbdf-49ab-9f60-654b54fa96c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932323050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.3932323050
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.3164092669
Short name T1054
Test name
Test status
Simulation time 1094498872 ps
CPU time 1.15 seconds
Started Apr 30 01:52:17 PM PDT 24
Finished Apr 30 01:52:19 PM PDT 24
Peak memory 204116 kb
Host smart-a6eaf02b-0b5f-49a6-a10b-cb185319055a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164092669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.3164092669
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.421371345
Short name T325
Test name
Test status
Simulation time 161421021 ps
CPU time 4.14 seconds
Started Apr 30 01:52:17 PM PDT 24
Finished Apr 30 01:52:21 PM PDT 24
Peak memory 232032 kb
Host smart-81186231-0334-487b-bdf8-6ea3f7f95a33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421371345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.421371345
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.3727037203
Short name T160
Test name
Test status
Simulation time 4500535610 ps
CPU time 123.6 seconds
Started Apr 30 01:52:18 PM PDT 24
Finished Apr 30 01:54:22 PM PDT 24
Peak memory 1283812 kb
Host smart-43b2e278-14d9-49bf-afe2-ede80f64ed4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727037203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.3727037203
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.506593055
Short name T281
Test name
Test status
Simulation time 335634754 ps
CPU time 4.9 seconds
Started Apr 30 01:52:32 PM PDT 24
Finished Apr 30 01:52:37 PM PDT 24
Peak memory 204152 kb
Host smart-2a46c9f7-3971-48a8-b332-2040c7f49c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506593055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.506593055
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.3466849304
Short name T791
Test name
Test status
Simulation time 3212298655 ps
CPU time 75.54 seconds
Started Apr 30 01:52:35 PM PDT 24
Finished Apr 30 01:53:51 PM PDT 24
Peak memory 328720 kb
Host smart-cff9dd63-25a8-4cee-875b-2584f57cb6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466849304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.3466849304
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_perf.2448721355
Short name T866
Test name
Test status
Simulation time 49760797535 ps
CPU time 648.52 seconds
Started Apr 30 01:52:35 PM PDT 24
Finished Apr 30 02:03:24 PM PDT 24
Peak memory 231744 kb
Host smart-095a8a69-7d1c-4481-8e61-99fc04a24725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448721355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.2448721355
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.487430915
Short name T1239
Test name
Test status
Simulation time 1152118868 ps
CPU time 54.58 seconds
Started Apr 30 01:52:20 PM PDT 24
Finished Apr 30 01:53:15 PM PDT 24
Peak memory 284888 kb
Host smart-b6991104-228f-4fc5-93e1-f1c09daca5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487430915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.487430915
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.4028377876
Short name T1182
Test name
Test status
Simulation time 63139302469 ps
CPU time 2693.27 seconds
Started Apr 30 01:52:35 PM PDT 24
Finished Apr 30 02:37:29 PM PDT 24
Peak memory 2771288 kb
Host smart-79ab61a7-e592-4961-a3b4-1b8c023b47d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028377876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.4028377876
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.889386417
Short name T735
Test name
Test status
Simulation time 2942760045 ps
CPU time 15.17 seconds
Started Apr 30 01:52:23 PM PDT 24
Finished Apr 30 01:52:38 PM PDT 24
Peak memory 219808 kb
Host smart-db29e323-735a-4659-bcd5-17db4a19cb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889386417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.889386417
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.2757706674
Short name T937
Test name
Test status
Simulation time 713065430 ps
CPU time 3.89 seconds
Started Apr 30 01:52:40 PM PDT 24
Finished Apr 30 01:52:45 PM PDT 24
Peak memory 204180 kb
Host smart-d31737e7-4941-443f-a539-dce0c8f8839a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757706674 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.2757706674
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.4015707130
Short name T56
Test name
Test status
Simulation time 10060581448 ps
CPU time 68.3 seconds
Started Apr 30 01:52:35 PM PDT 24
Finished Apr 30 01:53:44 PM PDT 24
Peak memory 442540 kb
Host smart-12d13264-931b-4c36-a73e-4f920dc0d8e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015707130 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.4015707130
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.4249453435
Short name T927
Test name
Test status
Simulation time 10157678012 ps
CPU time 39.01 seconds
Started Apr 30 01:52:29 PM PDT 24
Finished Apr 30 01:53:08 PM PDT 24
Peak memory 395916 kb
Host smart-f94f353e-8cb3-4239-bf36-a6f1e2502a14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249453435 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.4249453435
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.2320924865
Short name T21
Test name
Test status
Simulation time 7323844152 ps
CPU time 8.72 seconds
Started Apr 30 01:52:23 PM PDT 24
Finished Apr 30 01:52:32 PM PDT 24
Peak memory 204368 kb
Host smart-c70e776c-05c8-428f-90f8-7ac56bd71c40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320924865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2320924865
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.4201946915
Short name T1249
Test name
Test status
Simulation time 1699328427 ps
CPU time 2.57 seconds
Started Apr 30 01:52:29 PM PDT 24
Finished Apr 30 01:52:32 PM PDT 24
Peak memory 204080 kb
Host smart-2d32308c-9447-4678-834b-c9a903eba392
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201946915 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.4201946915
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.455347693
Short name T775
Test name
Test status
Simulation time 1511834916 ps
CPU time 6.56 seconds
Started Apr 30 01:52:26 PM PDT 24
Finished Apr 30 01:52:34 PM PDT 24
Peak memory 212360 kb
Host smart-f1832201-6a3f-4329-9816-e7e32aa44ef5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455347693 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_intr_smoke.455347693
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.4020305744
Short name T675
Test name
Test status
Simulation time 22986051099 ps
CPU time 330.79 seconds
Started Apr 30 01:52:22 PM PDT 24
Finished Apr 30 01:57:54 PM PDT 24
Peak memory 4289140 kb
Host smart-257184dd-5432-4b32-afb9-437d16521e0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020305744 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.4020305744
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.1737182553
Short name T1315
Test name
Test status
Simulation time 1378063938 ps
CPU time 18.39 seconds
Started Apr 30 01:52:30 PM PDT 24
Finished Apr 30 01:52:49 PM PDT 24
Peak memory 204104 kb
Host smart-f2548cc9-e001-4797-8e89-2f1429f1e335
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737182553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.1737182553
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.843384776
Short name T723
Test name
Test status
Simulation time 1112249148 ps
CPU time 20.65 seconds
Started Apr 30 01:52:27 PM PDT 24
Finished Apr 30 01:52:49 PM PDT 24
Peak memory 214656 kb
Host smart-1d1e99d2-82eb-4b43-8da7-397edbb4498f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843384776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_rd.843384776
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.218061782
Short name T1079
Test name
Test status
Simulation time 55249347504 ps
CPU time 214.96 seconds
Started Apr 30 01:52:30 PM PDT 24
Finished Apr 30 01:56:06 PM PDT 24
Peak memory 2333716 kb
Host smart-1724eaa5-00f2-4580-842c-9acb80d7e691
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218061782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_wr.218061782
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.990222620
Short name T1350
Test name
Test status
Simulation time 5821458040 ps
CPU time 128.49 seconds
Started Apr 30 01:52:24 PM PDT 24
Finished Apr 30 01:54:33 PM PDT 24
Peak memory 1472620 kb
Host smart-8061c21c-688d-45c4-9b85-4761fe292ea5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990222620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_ta
rget_stretch.990222620
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.1219321738
Short name T1312
Test name
Test status
Simulation time 1121416876 ps
CPU time 6.25 seconds
Started Apr 30 01:52:25 PM PDT 24
Finished Apr 30 01:52:32 PM PDT 24
Peak memory 217872 kb
Host smart-78bf5a04-3da7-4e5f-b6a6-24f68668512e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219321738 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.1219321738
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.1573164462
Short name T745
Test name
Test status
Simulation time 17449514 ps
CPU time 0.63 seconds
Started Apr 30 01:52:32 PM PDT 24
Finished Apr 30 01:52:33 PM PDT 24
Peak memory 203864 kb
Host smart-2c06c182-44e1-4ac2-b9c5-a60fc7cc2908
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573164462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.1573164462
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.3283943222
Short name T827
Test name
Test status
Simulation time 216213790 ps
CPU time 1.19 seconds
Started Apr 30 01:52:42 PM PDT 24
Finished Apr 30 01:52:44 PM PDT 24
Peak memory 212472 kb
Host smart-b45a4b2a-0ef7-46df-8493-34dd93c80458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283943222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3283943222
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.909734265
Short name T956
Test name
Test status
Simulation time 2696628714 ps
CPU time 5.24 seconds
Started Apr 30 01:52:43 PM PDT 24
Finished Apr 30 01:52:48 PM PDT 24
Peak memory 262912 kb
Host smart-76f8c946-437b-4c02-a9c0-cda055d16f5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909734265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.909734265
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.2743261474
Short name T811
Test name
Test status
Simulation time 2750972610 ps
CPU time 53.24 seconds
Started Apr 30 01:52:38 PM PDT 24
Finished Apr 30 01:53:32 PM PDT 24
Peak memory 427904 kb
Host smart-1955cb53-485a-4395-93d4-6e67222ea2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743261474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.2743261474
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.1246917549
Short name T1227
Test name
Test status
Simulation time 6149045821 ps
CPU time 46.62 seconds
Started Apr 30 01:52:30 PM PDT 24
Finished Apr 30 01:53:17 PM PDT 24
Peak memory 569876 kb
Host smart-4eb8fef9-3e3f-43a0-aee9-6ee508a304fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246917549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.1246917549
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.2186141124
Short name T754
Test name
Test status
Simulation time 134764650 ps
CPU time 1.07 seconds
Started Apr 30 01:52:42 PM PDT 24
Finished Apr 30 01:52:43 PM PDT 24
Peak memory 204196 kb
Host smart-7f0c54c6-51b6-4d5b-81ed-3252f1e3826f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186141124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.2186141124
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.3569247075
Short name T1304
Test name
Test status
Simulation time 749176857 ps
CPU time 8.45 seconds
Started Apr 30 01:52:38 PM PDT 24
Finished Apr 30 01:52:47 PM PDT 24
Peak memory 204124 kb
Host smart-1600dd42-f92e-4e96-90e0-7a0c9dfd6834
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569247075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
3569247075
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.3112270452
Short name T341
Test name
Test status
Simulation time 16421768911 ps
CPU time 274.44 seconds
Started Apr 30 01:52:36 PM PDT 24
Finished Apr 30 01:57:11 PM PDT 24
Peak memory 1133932 kb
Host smart-0c3cc351-6700-4aae-8b9b-ce0e964be5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112270452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.3112270452
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.1478855068
Short name T660
Test name
Test status
Simulation time 728898775 ps
CPU time 6.06 seconds
Started Apr 30 01:52:39 PM PDT 24
Finished Apr 30 01:52:45 PM PDT 24
Peak memory 204196 kb
Host smart-29d6deb8-8d95-4b94-8c5c-f302f8bd5ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478855068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.1478855068
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.2423679827
Short name T1331
Test name
Test status
Simulation time 5758064104 ps
CPU time 37.72 seconds
Started Apr 30 01:52:42 PM PDT 24
Finished Apr 30 01:53:20 PM PDT 24
Peak memory 424052 kb
Host smart-4f87c1df-d9f7-4ab2-85b6-75e5097edda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423679827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.2423679827
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.1095625783
Short name T286
Test name
Test status
Simulation time 25055137 ps
CPU time 0.68 seconds
Started Apr 30 01:52:40 PM PDT 24
Finished Apr 30 01:52:41 PM PDT 24
Peak memory 203768 kb
Host smart-3febd5e4-1d08-4c25-a6ce-737d12dce09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095625783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1095625783
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.3786367132
Short name T958
Test name
Test status
Simulation time 48836388643 ps
CPU time 2038.5 seconds
Started Apr 30 01:52:41 PM PDT 24
Finished Apr 30 02:26:40 PM PDT 24
Peak memory 212448 kb
Host smart-7f062542-af6e-4eaa-8e20-2cf338b092b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786367132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.3786367132
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.2723564591
Short name T503
Test name
Test status
Simulation time 4205609993 ps
CPU time 21.75 seconds
Started Apr 30 01:52:30 PM PDT 24
Finished Apr 30 01:52:53 PM PDT 24
Peak memory 327288 kb
Host smart-d8c682d9-0474-4a5c-8ec1-dcc2a5cab2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723564591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2723564591
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.411890438
Short name T269
Test name
Test status
Simulation time 2287417826 ps
CPU time 7.46 seconds
Started Apr 30 01:52:42 PM PDT 24
Finished Apr 30 01:52:50 PM PDT 24
Peak memory 212492 kb
Host smart-bb470a96-0221-4431-994c-4098d70e61f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411890438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.411890438
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2478474250
Short name T110
Test name
Test status
Simulation time 151692038 ps
CPU time 1.06 seconds
Started Apr 30 01:52:48 PM PDT 24
Finished Apr 30 01:52:50 PM PDT 24
Peak memory 222452 kb
Host smart-ed236d40-b16e-4a0b-9dee-724a03d3ca41
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478474250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2478474250
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.265064713
Short name T636
Test name
Test status
Simulation time 615270190 ps
CPU time 3.02 seconds
Started Apr 30 01:52:32 PM PDT 24
Finished Apr 30 01:52:36 PM PDT 24
Peak memory 204172 kb
Host smart-1230d212-76e3-4de2-9a85-8ecc8ad17094
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265064713 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.265064713
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.2044053129
Short name T1110
Test name
Test status
Simulation time 10136620595 ps
CPU time 65.75 seconds
Started Apr 30 01:52:40 PM PDT 24
Finished Apr 30 01:53:46 PM PDT 24
Peak memory 442320 kb
Host smart-1005e77e-b5c0-469d-8f29-0b5111d9c944
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044053129 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.2044053129
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.4245335921
Short name T1166
Test name
Test status
Simulation time 10086221922 ps
CPU time 28.05 seconds
Started Apr 30 01:52:34 PM PDT 24
Finished Apr 30 01:53:02 PM PDT 24
Peak memory 368164 kb
Host smart-8c26669e-c083-4170-a67d-673cc1f32be8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245335921 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.4245335921
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.1813285504
Short name T288
Test name
Test status
Simulation time 1745260200 ps
CPU time 4.68 seconds
Started Apr 30 01:52:33 PM PDT 24
Finished Apr 30 01:52:39 PM PDT 24
Peak memory 204208 kb
Host smart-4d324a62-a256-44d1-92ab-46583369be7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813285504 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.1813285504
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.3835816061
Short name T1264
Test name
Test status
Simulation time 4277004007 ps
CPU time 3.57 seconds
Started Apr 30 01:52:30 PM PDT 24
Finished Apr 30 01:52:34 PM PDT 24
Peak memory 204200 kb
Host smart-7e9ca9e3-f662-4eea-a5c6-4b18f57e9a7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835816061 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.3835816061
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.4069589146
Short name T506
Test name
Test status
Simulation time 2709450313 ps
CPU time 28.34 seconds
Started Apr 30 01:52:40 PM PDT 24
Finished Apr 30 01:53:09 PM PDT 24
Peak memory 204204 kb
Host smart-daa0774e-9c38-4db5-830d-9427cb1c6a9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069589146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.4069589146
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.1367782365
Short name T765
Test name
Test status
Simulation time 1122720626 ps
CPU time 15.75 seconds
Started Apr 30 01:52:32 PM PDT 24
Finished Apr 30 01:52:48 PM PDT 24
Peak memory 218872 kb
Host smart-26533478-92c7-4dcc-97de-bab5424cfa7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367782365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.1367782365
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.1048082628
Short name T947
Test name
Test status
Simulation time 19790300233 ps
CPU time 12.53 seconds
Started Apr 30 01:52:36 PM PDT 24
Finished Apr 30 01:52:49 PM PDT 24
Peak memory 204240 kb
Host smart-2f1a4e2e-07e9-4cd6-bee3-b6b8aa755d05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048082628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.1048082628
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.1202396316
Short name T867
Test name
Test status
Simulation time 20267409644 ps
CPU time 398.96 seconds
Started Apr 30 01:52:41 PM PDT 24
Finished Apr 30 01:59:21 PM PDT 24
Peak memory 2378664 kb
Host smart-8244e9b5-16ec-4bd0-8784-e7dc6dfd0fee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202396316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.1202396316
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.1297961361
Short name T730
Test name
Test status
Simulation time 1230677362 ps
CPU time 7.18 seconds
Started Apr 30 01:52:34 PM PDT 24
Finished Apr 30 01:52:42 PM PDT 24
Peak memory 220384 kb
Host smart-5a3ca319-d64b-49ec-a5a2-cb15cf182618
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297961361 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.1297961361
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.356025220
Short name T794
Test name
Test status
Simulation time 54495429 ps
CPU time 0.61 seconds
Started Apr 30 01:53:28 PM PDT 24
Finished Apr 30 01:53:29 PM PDT 24
Peak memory 203888 kb
Host smart-ccdd0466-0c90-499e-8d6f-0154aa82a710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356025220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.356025220
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.3849872700
Short name T1085
Test name
Test status
Simulation time 125679489 ps
CPU time 1.36 seconds
Started Apr 30 01:53:28 PM PDT 24
Finished Apr 30 01:53:29 PM PDT 24
Peak memory 212500 kb
Host smart-50eeaf43-2b3b-4265-842f-0ce08bd94c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849872700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.3849872700
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.1162831984
Short name T878
Test name
Test status
Simulation time 1056382558 ps
CPU time 13.6 seconds
Started Apr 30 01:53:22 PM PDT 24
Finished Apr 30 01:53:36 PM PDT 24
Peak memory 255012 kb
Host smart-c7673afd-aa9e-4755-a498-381a52c8f7ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162831984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.1162831984
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.1615686388
Short name T422
Test name
Test status
Simulation time 3643672864 ps
CPU time 54.19 seconds
Started Apr 30 01:53:28 PM PDT 24
Finished Apr 30 01:54:23 PM PDT 24
Peak memory 638732 kb
Host smart-7a1fc597-3040-4f61-a3ac-1557588d9ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615686388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.1615686388
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.2613651855
Short name T42
Test name
Test status
Simulation time 7410099540 ps
CPU time 140.25 seconds
Started Apr 30 01:53:21 PM PDT 24
Finished Apr 30 01:55:41 PM PDT 24
Peak memory 648484 kb
Host smart-6426d3a1-a5b1-41ae-935c-5b5136313a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613651855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.2613651855
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.3318692240
Short name T681
Test name
Test status
Simulation time 477367660 ps
CPU time 0.98 seconds
Started Apr 30 01:53:21 PM PDT 24
Finished Apr 30 01:53:22 PM PDT 24
Peak memory 204048 kb
Host smart-5de9dc96-774a-4c45-a30c-4da0374495f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318692240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.3318692240
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.609853414
Short name T911
Test name
Test status
Simulation time 436659234 ps
CPU time 3.62 seconds
Started Apr 30 01:53:20 PM PDT 24
Finished Apr 30 01:53:24 PM PDT 24
Peak memory 204104 kb
Host smart-2d421e0a-3cea-4da5-9d7f-ee54c6717751
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609853414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.
609853414
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.80141278
Short name T912
Test name
Test status
Simulation time 2341442639 ps
CPU time 152.08 seconds
Started Apr 30 01:53:21 PM PDT 24
Finished Apr 30 01:55:53 PM PDT 24
Peak memory 777576 kb
Host smart-3664631b-fc57-4963-938a-5d1a14e5e477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80141278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.80141278
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.3124718747
Short name T538
Test name
Test status
Simulation time 1188918677 ps
CPU time 15.75 seconds
Started Apr 30 01:53:28 PM PDT 24
Finished Apr 30 01:53:44 PM PDT 24
Peak memory 204140 kb
Host smart-56139090-466b-4d58-a2b1-5aff679b5057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124718747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.3124718747
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.1188265222
Short name T283
Test name
Test status
Simulation time 2361393057 ps
CPU time 45.13 seconds
Started Apr 30 01:53:25 PM PDT 24
Finished Apr 30 01:54:11 PM PDT 24
Peak memory 382852 kb
Host smart-170f64ac-dfb5-4bef-a706-96367ce85dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188265222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.1188265222
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.3495178904
Short name T38
Test name
Test status
Simulation time 77461075 ps
CPU time 0.67 seconds
Started Apr 30 01:53:18 PM PDT 24
Finished Apr 30 01:53:19 PM PDT 24
Peak memory 203872 kb
Host smart-168c0121-7a5e-4047-a587-8c50e4f6c47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495178904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3495178904
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.1167124163
Short name T465
Test name
Test status
Simulation time 140735136 ps
CPU time 5.67 seconds
Started Apr 30 01:53:26 PM PDT 24
Finished Apr 30 01:53:32 PM PDT 24
Peak memory 228660 kb
Host smart-4028df25-cea6-42ea-91f7-d69a24da0097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167124163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.1167124163
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.3989595210
Short name T410
Test name
Test status
Simulation time 25411117668 ps
CPU time 45.24 seconds
Started Apr 30 01:53:20 PM PDT 24
Finished Apr 30 01:54:05 PM PDT 24
Peak memory 403520 kb
Host smart-ea76b709-f215-4a76-b321-a668c876ac19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989595210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.3989595210
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.3723491103
Short name T46
Test name
Test status
Simulation time 20965525811 ps
CPU time 1795.79 seconds
Started Apr 30 01:53:26 PM PDT 24
Finished Apr 30 02:23:23 PM PDT 24
Peak memory 4212204 kb
Host smart-1743f9ba-0303-456c-8fbb-c4dce9b9bf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723491103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.3723491103
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.3233597217
Short name T1045
Test name
Test status
Simulation time 4045217858 ps
CPU time 12.17 seconds
Started Apr 30 01:53:26 PM PDT 24
Finished Apr 30 01:53:39 PM PDT 24
Peak memory 217648 kb
Host smart-0a08391f-ec0d-44fa-b451-815a3b2aaa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233597217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.3233597217
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.4176473790
Short name T1103
Test name
Test status
Simulation time 10270111984 ps
CPU time 31.29 seconds
Started Apr 30 01:53:31 PM PDT 24
Finished Apr 30 01:54:03 PM PDT 24
Peak memory 331552 kb
Host smart-9fc7cd95-a468-4ea8-984a-e7787b7820c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176473790 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.4176473790
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.2187100643
Short name T271
Test name
Test status
Simulation time 10096084305 ps
CPU time 71.53 seconds
Started Apr 30 01:53:27 PM PDT 24
Finished Apr 30 01:54:39 PM PDT 24
Peak memory 459120 kb
Host smart-54aa67b6-8a45-4716-aadf-c9c43c0058eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187100643 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.2187100643
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.3065802193
Short name T326
Test name
Test status
Simulation time 1543046973 ps
CPU time 2.38 seconds
Started Apr 30 01:53:27 PM PDT 24
Finished Apr 30 01:53:30 PM PDT 24
Peak memory 204096 kb
Host smart-253f8b08-03e3-4d0f-83e5-ba68a0fd953e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065802193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.3065802193
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.2081075682
Short name T853
Test name
Test status
Simulation time 3202829598 ps
CPU time 4.04 seconds
Started Apr 30 01:53:27 PM PDT 24
Finished Apr 30 01:53:31 PM PDT 24
Peak memory 204644 kb
Host smart-228031c6-e2e6-40a2-996c-90de18b90fc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081075682 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.2081075682
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.842050618
Short name T267
Test name
Test status
Simulation time 10127353308 ps
CPU time 19.27 seconds
Started Apr 30 01:53:27 PM PDT 24
Finished Apr 30 01:53:47 PM PDT 24
Peak memory 614860 kb
Host smart-d9d0a65b-252b-4419-bf3b-b0645fe64087
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842050618 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.842050618
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.560607537
Short name T549
Test name
Test status
Simulation time 943798455 ps
CPU time 12.57 seconds
Started Apr 30 01:53:29 PM PDT 24
Finished Apr 30 01:53:42 PM PDT 24
Peak memory 204108 kb
Host smart-eb19d473-39c3-4e91-81f9-5d06203a3e78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560607537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_tar
get_smoke.560607537
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.570535440
Short name T895
Test name
Test status
Simulation time 284824598 ps
CPU time 4.35 seconds
Started Apr 30 01:53:25 PM PDT 24
Finished Apr 30 01:53:30 PM PDT 24
Peak memory 204156 kb
Host smart-a22f9320-db92-445c-bc02-ce8b1c6f4bd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570535440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c
_target_stress_rd.570535440
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.1408719141
Short name T963
Test name
Test status
Simulation time 28524207628 ps
CPU time 163.13 seconds
Started Apr 30 01:53:26 PM PDT 24
Finished Apr 30 01:56:10 PM PDT 24
Peak memory 2160180 kb
Host smart-11644011-63f0-413f-a447-ebb4b9361f1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408719141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.1408719141
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.1087807913
Short name T1325
Test name
Test status
Simulation time 3381683206 ps
CPU time 65.09 seconds
Started Apr 30 01:53:26 PM PDT 24
Finished Apr 30 01:54:32 PM PDT 24
Peak memory 830372 kb
Host smart-d623a3f5-c3f4-4ca0-9bf9-e3d56e8a477c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087807913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.1087807913
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.2014654717
Short name T1311
Test name
Test status
Simulation time 1105122745 ps
CPU time 5.85 seconds
Started Apr 30 01:53:27 PM PDT 24
Finished Apr 30 01:53:33 PM PDT 24
Peak memory 215404 kb
Host smart-624894d0-2f49-4cda-8e6c-cbdc5d1138f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014654717 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.2014654717
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.3612792110
Short name T10
Test name
Test status
Simulation time 129590891 ps
CPU time 0.62 seconds
Started Apr 30 01:53:38 PM PDT 24
Finished Apr 30 01:53:39 PM PDT 24
Peak memory 203736 kb
Host smart-617044e3-c846-4137-b243-958f10b88d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612792110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.3612792110
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.4245787791
Short name T833
Test name
Test status
Simulation time 202001940 ps
CPU time 1.29 seconds
Started Apr 30 01:53:36 PM PDT 24
Finished Apr 30 01:53:38 PM PDT 24
Peak memory 212412 kb
Host smart-717c58ff-ef53-4546-99f2-ce32513e476e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245787791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.4245787791
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.1375615050
Short name T691
Test name
Test status
Simulation time 344869417 ps
CPU time 18.42 seconds
Started Apr 30 01:53:29 PM PDT 24
Finished Apr 30 01:53:48 PM PDT 24
Peak memory 277432 kb
Host smart-fbfd6cbc-9182-4f00-bdea-2347e2a929ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375615050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.1375615050
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.972007714
Short name T514
Test name
Test status
Simulation time 2493972974 ps
CPU time 187.54 seconds
Started Apr 30 01:53:27 PM PDT 24
Finished Apr 30 01:56:35 PM PDT 24
Peak memory 799928 kb
Host smart-dd9b7526-2884-4e0d-b4ab-88ba3f80be19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972007714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.972007714
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.4202758111
Short name T684
Test name
Test status
Simulation time 5945719885 ps
CPU time 109.32 seconds
Started Apr 30 01:53:29 PM PDT 24
Finished Apr 30 01:55:19 PM PDT 24
Peak memory 575768 kb
Host smart-65d27c41-fcfd-455c-9e09-96dc9ddccd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202758111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.4202758111
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.345356569
Short name T640
Test name
Test status
Simulation time 272903092 ps
CPU time 0.98 seconds
Started Apr 30 01:53:25 PM PDT 24
Finished Apr 30 01:53:26 PM PDT 24
Peak memory 203992 kb
Host smart-6678f5a7-3acd-4479-b865-f01b124b7c73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345356569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fm
t.345356569
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.3005477204
Short name T278
Test name
Test status
Simulation time 439145649 ps
CPU time 4.31 seconds
Started Apr 30 01:53:27 PM PDT 24
Finished Apr 30 01:53:32 PM PDT 24
Peak memory 233048 kb
Host smart-6e710173-37cd-4edc-a25c-25fdc1882f2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005477204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.3005477204
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.922155546
Short name T458
Test name
Test status
Simulation time 3607432341 ps
CPU time 83.47 seconds
Started Apr 30 01:53:33 PM PDT 24
Finished Apr 30 01:54:57 PM PDT 24
Peak memory 349956 kb
Host smart-e937d703-b2a7-465f-9af9-e210619c0e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922155546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.922155546
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.114737835
Short name T1076
Test name
Test status
Simulation time 93608503 ps
CPU time 0.7 seconds
Started Apr 30 01:53:27 PM PDT 24
Finished Apr 30 01:53:29 PM PDT 24
Peak memory 203812 kb
Host smart-42cbba3b-c7d7-4582-ac36-57102163098f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114737835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.114737835
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.2381097210
Short name T1008
Test name
Test status
Simulation time 3738790637 ps
CPU time 4.49 seconds
Started Apr 30 01:53:32 PM PDT 24
Finished Apr 30 01:53:37 PM PDT 24
Peak memory 204304 kb
Host smart-10291e89-88f2-4130-b73c-372342cf48ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381097210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.2381097210
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.3237573797
Short name T1206
Test name
Test status
Simulation time 3127192083 ps
CPU time 15.29 seconds
Started Apr 30 01:53:26 PM PDT 24
Finished Apr 30 01:53:42 PM PDT 24
Peak memory 315504 kb
Host smart-67dda2a9-b3ec-4726-9840-011c02c3e2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237573797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.3237573797
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.1337426134
Short name T161
Test name
Test status
Simulation time 60985633707 ps
CPU time 439.01 seconds
Started Apr 30 01:53:32 PM PDT 24
Finished Apr 30 02:00:52 PM PDT 24
Peak memory 2104676 kb
Host smart-c634c921-5e85-4155-8fc2-558751bf29f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337426134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.1337426134
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.3564385384
Short name T989
Test name
Test status
Simulation time 723057138 ps
CPU time 6.02 seconds
Started Apr 30 01:53:34 PM PDT 24
Finished Apr 30 01:53:40 PM PDT 24
Peak memory 212328 kb
Host smart-1e1160df-a98e-4bab-9218-ad6ca345126d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564385384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.3564385384
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.3223322133
Short name T483
Test name
Test status
Simulation time 2881580217 ps
CPU time 3.87 seconds
Started Apr 30 01:53:35 PM PDT 24
Finished Apr 30 01:53:39 PM PDT 24
Peak memory 204212 kb
Host smart-86e24eb0-4ddc-4e09-94e8-648fa531ac2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223322133 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.3223322133
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.2007017379
Short name T1224
Test name
Test status
Simulation time 10231268418 ps
CPU time 28.6 seconds
Started Apr 30 01:53:38 PM PDT 24
Finished Apr 30 01:54:07 PM PDT 24
Peak memory 353912 kb
Host smart-877c1267-994d-4464-b3c6-7ea213621fc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007017379 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.2007017379
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.946658292
Short name T1343
Test name
Test status
Simulation time 13240612030 ps
CPU time 4.02 seconds
Started Apr 30 01:53:34 PM PDT 24
Finished Apr 30 01:53:38 PM PDT 24
Peak memory 231932 kb
Host smart-a6daac75-6800-44c8-8375-a26cd47d82a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946658292 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.i2c_target_fifo_reset_tx.946658292
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.4096011080
Short name T1082
Test name
Test status
Simulation time 340482527 ps
CPU time 2.23 seconds
Started Apr 30 01:53:33 PM PDT 24
Finished Apr 30 01:53:35 PM PDT 24
Peak memory 204208 kb
Host smart-442b912f-6a31-4cf2-81f2-69a03a195009
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096011080 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.4096011080
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.1907143246
Short name T324
Test name
Test status
Simulation time 553532192 ps
CPU time 3.37 seconds
Started Apr 30 01:53:32 PM PDT 24
Finished Apr 30 01:53:36 PM PDT 24
Peak memory 204200 kb
Host smart-225fd688-86b7-4f35-a196-7fd9d23af8b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907143246 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.1907143246
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.3667177302
Short name T1002
Test name
Test status
Simulation time 6877638599 ps
CPU time 13.53 seconds
Started Apr 30 01:53:33 PM PDT 24
Finished Apr 30 01:53:47 PM PDT 24
Peak memory 530976 kb
Host smart-40c10858-f8fa-41a4-bf20-1b3b9260ac3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667177302 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.3667177302
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.516531797
Short name T688
Test name
Test status
Simulation time 5891319212 ps
CPU time 23.42 seconds
Started Apr 30 01:53:36 PM PDT 24
Finished Apr 30 01:54:00 PM PDT 24
Peak memory 204244 kb
Host smart-c4363d3f-21e3-4dce-8d06-f12c28afa328
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516531797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_tar
get_smoke.516531797
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.1400882609
Short name T647
Test name
Test status
Simulation time 730247701 ps
CPU time 11.11 seconds
Started Apr 30 01:53:32 PM PDT 24
Finished Apr 30 01:53:44 PM PDT 24
Peak memory 211232 kb
Host smart-cd34c028-ebd8-44d5-b07d-7a324da92108
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400882609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.1400882609
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.2573547019
Short name T627
Test name
Test status
Simulation time 29157273725 ps
CPU time 157.97 seconds
Started Apr 30 01:53:32 PM PDT 24
Finished Apr 30 01:56:11 PM PDT 24
Peak memory 2302636 kb
Host smart-ae59f14f-3185-4665-b60b-61c614c376b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573547019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.2573547019
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.3094347084
Short name T337
Test name
Test status
Simulation time 31155622019 ps
CPU time 621.49 seconds
Started Apr 30 01:53:37 PM PDT 24
Finished Apr 30 02:03:59 PM PDT 24
Peak memory 3710316 kb
Host smart-f1d5d595-cc05-4166-b7c1-68bfd1f93a50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094347084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.3094347084
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.3657393396
Short name T507
Test name
Test status
Simulation time 5279984158 ps
CPU time 7.04 seconds
Started Apr 30 01:53:33 PM PDT 24
Finished Apr 30 01:53:41 PM PDT 24
Peak memory 209384 kb
Host smart-0377658b-d4ed-4e49-9a84-182efdd06ccf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657393396 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.3657393396
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.2504838551
Short name T478
Test name
Test status
Simulation time 42340351 ps
CPU time 0.6 seconds
Started Apr 30 01:53:49 PM PDT 24
Finished Apr 30 01:53:50 PM PDT 24
Peak memory 203916 kb
Host smart-3957fb88-c5b0-4326-9b34-6540b8248a83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504838551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.2504838551
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.324134737
Short name T993
Test name
Test status
Simulation time 43639023 ps
CPU time 1.1 seconds
Started Apr 30 01:53:39 PM PDT 24
Finished Apr 30 01:53:41 PM PDT 24
Peak memory 204248 kb
Host smart-9de156e8-6882-4e70-b0ec-e1f664ececa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324134737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.324134737
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3298476004
Short name T467
Test name
Test status
Simulation time 1459560165 ps
CPU time 7.41 seconds
Started Apr 30 01:53:35 PM PDT 24
Finished Apr 30 01:53:43 PM PDT 24
Peak memory 260320 kb
Host smart-448ddba0-3c8d-469a-8575-f23624eb589f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298476004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3298476004
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.1115619413
Short name T889
Test name
Test status
Simulation time 6299070598 ps
CPU time 37.9 seconds
Started Apr 30 01:53:32 PM PDT 24
Finished Apr 30 01:54:11 PM PDT 24
Peak memory 413588 kb
Host smart-cd1ff3d8-ff70-44a9-b946-a278784b45a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115619413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.1115619413
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.4287816049
Short name T1071
Test name
Test status
Simulation time 4058767333 ps
CPU time 64.17 seconds
Started Apr 30 01:53:38 PM PDT 24
Finished Apr 30 01:54:42 PM PDT 24
Peak memory 667484 kb
Host smart-9aa4ac37-123e-4de1-ab0d-7823782138f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287816049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.4287816049
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.2785559944
Short name T1037
Test name
Test status
Simulation time 283831600 ps
CPU time 4.4 seconds
Started Apr 30 01:53:34 PM PDT 24
Finished Apr 30 01:53:38 PM PDT 24
Peak memory 227064 kb
Host smart-b07fd1d5-6e7f-4a95-aea7-8f0cb4e23e75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785559944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.2785559944
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.1124414445
Short name T1262
Test name
Test status
Simulation time 10894401014 ps
CPU time 50.6 seconds
Started Apr 30 01:53:34 PM PDT 24
Finished Apr 30 01:54:26 PM PDT 24
Peak memory 741536 kb
Host smart-6b76792e-661b-4d2b-8228-43506f6371b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124414445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1124414445
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.3620667255
Short name T863
Test name
Test status
Simulation time 309512801 ps
CPU time 12.14 seconds
Started Apr 30 01:53:40 PM PDT 24
Finished Apr 30 01:53:53 PM PDT 24
Peak memory 204196 kb
Host smart-daaa2f68-5182-4894-8f1d-edf5cdef3216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620667255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.3620667255
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.2898413671
Short name T334
Test name
Test status
Simulation time 5818798156 ps
CPU time 74.09 seconds
Started Apr 30 01:53:47 PM PDT 24
Finished Apr 30 01:55:02 PM PDT 24
Peak memory 317832 kb
Host smart-fa3ab6d6-5933-404b-9281-5919a8193bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898413671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.2898413671
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.86242690
Short name T662
Test name
Test status
Simulation time 18886392 ps
CPU time 0.66 seconds
Started Apr 30 01:53:32 PM PDT 24
Finished Apr 30 01:53:33 PM PDT 24
Peak memory 203800 kb
Host smart-f408e1b0-a4f8-4edd-afa7-b2db1b27d1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86242690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.86242690
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.2459825902
Short name T1252
Test name
Test status
Simulation time 72332176622 ps
CPU time 1309.42 seconds
Started Apr 30 01:53:34 PM PDT 24
Finished Apr 30 02:15:24 PM PDT 24
Peak memory 918284 kb
Host smart-2e305a45-1ec7-4abe-9865-4e94ff1e9512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459825902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2459825902
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.4097708270
Short name T1324
Test name
Test status
Simulation time 3743865941 ps
CPU time 44.63 seconds
Started Apr 30 01:53:36 PM PDT 24
Finished Apr 30 01:54:21 PM PDT 24
Peak memory 300856 kb
Host smart-fea7d42b-33c0-4a0e-b6f5-17d2d78b8ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097708270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.4097708270
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.2072956584
Short name T174
Test name
Test status
Simulation time 15383128359 ps
CPU time 88.31 seconds
Started Apr 30 01:53:39 PM PDT 24
Finished Apr 30 01:55:08 PM PDT 24
Peak memory 620692 kb
Host smart-781510ae-a71a-454e-bbbc-33f998f892b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072956584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.2072956584
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.670086757
Short name T748
Test name
Test status
Simulation time 1891214108 ps
CPU time 9.25 seconds
Started Apr 30 01:53:47 PM PDT 24
Finished Apr 30 01:53:57 PM PDT 24
Peak memory 213436 kb
Host smart-abe9d5ec-67a5-4e4d-b2a6-a6d584c51251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670086757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.670086757
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.207016599
Short name T616
Test name
Test status
Simulation time 919585468 ps
CPU time 4.69 seconds
Started Apr 30 01:53:38 PM PDT 24
Finished Apr 30 01:53:44 PM PDT 24
Peak memory 212408 kb
Host smart-f220b3c2-b462-49e7-9292-9068c8f97c7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207016599 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.207016599
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.553983366
Short name T1260
Test name
Test status
Simulation time 10049056189 ps
CPU time 81.08 seconds
Started Apr 30 01:53:39 PM PDT 24
Finished Apr 30 01:55:00 PM PDT 24
Peak memory 563824 kb
Host smart-5867434e-3e06-45f3-ba43-4dc5dcd84414
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553983366 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.553983366
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.1007643461
Short name T667
Test name
Test status
Simulation time 380209465 ps
CPU time 2.32 seconds
Started Apr 30 01:53:49 PM PDT 24
Finished Apr 30 01:53:52 PM PDT 24
Peak memory 204196 kb
Host smart-ccae3706-f282-4a6b-9fe0-30e595cd24f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007643461 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.1007643461
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.227082732
Short name T117
Test name
Test status
Simulation time 1071642919 ps
CPU time 5.69 seconds
Started Apr 30 01:53:40 PM PDT 24
Finished Apr 30 01:53:47 PM PDT 24
Peak memory 218796 kb
Host smart-5ee123af-e9f5-409c-ad2d-d578e9e4677b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227082732 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_intr_smoke.227082732
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.1564222703
Short name T764
Test name
Test status
Simulation time 16710475230 ps
CPU time 333.4 seconds
Started Apr 30 01:53:40 PM PDT 24
Finished Apr 30 01:59:14 PM PDT 24
Peak memory 4118424 kb
Host smart-0d548641-c633-4921-980d-e58614a24368
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564222703 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.1564222703
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.1349438273
Short name T318
Test name
Test status
Simulation time 725002741 ps
CPU time 24.59 seconds
Started Apr 30 01:53:41 PM PDT 24
Finished Apr 30 01:54:06 PM PDT 24
Peak memory 204100 kb
Host smart-7c1cec2f-eb30-4d0f-828c-5a746eb191a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349438273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.1349438273
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.1460425297
Short name T925
Test name
Test status
Simulation time 742324825 ps
CPU time 33.12 seconds
Started Apr 30 01:53:40 PM PDT 24
Finished Apr 30 01:54:14 PM PDT 24
Peak memory 204188 kb
Host smart-d089a16a-791e-495b-b75c-7804fa5c5cbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460425297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.1460425297
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.3167091123
Short name T874
Test name
Test status
Simulation time 35506988147 ps
CPU time 45.54 seconds
Started Apr 30 01:53:41 PM PDT 24
Finished Apr 30 01:54:27 PM PDT 24
Peak memory 868624 kb
Host smart-51d08740-eb3b-47ee-a12d-342182c942bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167091123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.3167091123
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.17875847
Short name T879
Test name
Test status
Simulation time 30778657123 ps
CPU time 1265.57 seconds
Started Apr 30 01:53:41 PM PDT 24
Finished Apr 30 02:14:47 PM PDT 24
Peak memory 5292168 kb
Host smart-8ca7adc7-5e58-43a6-bbfb-aa2a2c387998
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17875847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_stretch.17875847
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.509477758
Short name T1020
Test name
Test status
Simulation time 1400608134 ps
CPU time 6.67 seconds
Started Apr 30 01:53:40 PM PDT 24
Finished Apr 30 01:53:48 PM PDT 24
Peak memory 212416 kb
Host smart-25a8fc09-e128-4d8f-92e5-84dc1f3c1a9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509477758 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_timeout.509477758
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.1362173404
Short name T5
Test name
Test status
Simulation time 31719255 ps
CPU time 0.63 seconds
Started Apr 30 01:53:48 PM PDT 24
Finished Apr 30 01:53:50 PM PDT 24
Peak memory 203728 kb
Host smart-0156786d-aec7-4f85-af85-91883bcc2b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362173404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.1362173404
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.3635091656
Short name T737
Test name
Test status
Simulation time 92761204 ps
CPU time 1.32 seconds
Started Apr 30 01:53:42 PM PDT 24
Finished Apr 30 01:53:44 PM PDT 24
Peak memory 212472 kb
Host smart-f5ab282e-26ad-4775-926d-bcea495f3726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635091656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.3635091656
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.4230789122
Short name T614
Test name
Test status
Simulation time 420951292 ps
CPU time 7.36 seconds
Started Apr 30 01:53:41 PM PDT 24
Finished Apr 30 01:53:49 PM PDT 24
Peak memory 294864 kb
Host smart-a7111983-da14-4ac8-adac-11f06cf41079
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230789122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.4230789122
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.482194911
Short name T698
Test name
Test status
Simulation time 1948955854 ps
CPU time 116.75 seconds
Started Apr 30 01:53:39 PM PDT 24
Finished Apr 30 01:55:36 PM PDT 24
Peak memory 566508 kb
Host smart-c128d07b-2186-468e-accd-77f2d8a0fcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482194911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.482194911
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.2221759262
Short name T574
Test name
Test status
Simulation time 7739313932 ps
CPU time 52.92 seconds
Started Apr 30 01:53:38 PM PDT 24
Finished Apr 30 01:54:32 PM PDT 24
Peak memory 591272 kb
Host smart-c59fb905-05db-49f8-a159-285073766c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221759262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.2221759262
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2364289480
Short name T795
Test name
Test status
Simulation time 369965241 ps
CPU time 0.82 seconds
Started Apr 30 01:53:39 PM PDT 24
Finished Apr 30 01:53:41 PM PDT 24
Peak memory 203948 kb
Host smart-de6fbb37-976f-459f-92a8-2f60981fc274
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364289480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2364289480
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3317201041
Short name T490
Test name
Test status
Simulation time 499363619 ps
CPU time 6.2 seconds
Started Apr 30 01:53:40 PM PDT 24
Finished Apr 30 01:53:47 PM PDT 24
Peak memory 204128 kb
Host smart-5f369b30-85c1-4be6-8ae5-09ca213916d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317201041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3317201041
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.685974995
Short name T45
Test name
Test status
Simulation time 13631393231 ps
CPU time 233.56 seconds
Started Apr 30 01:53:42 PM PDT 24
Finished Apr 30 01:57:36 PM PDT 24
Peak memory 990308 kb
Host smart-a0d5ccd6-f666-4f72-8ee8-823ec48da911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685974995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.685974995
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.283279151
Short name T906
Test name
Test status
Simulation time 600931944 ps
CPU time 7.54 seconds
Started Apr 30 01:53:47 PM PDT 24
Finished Apr 30 01:53:55 PM PDT 24
Peak memory 204128 kb
Host smart-5b2646e6-4f19-414e-8c60-d9f4ac686f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283279151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.283279151
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.1653023836
Short name T491
Test name
Test status
Simulation time 1163791439 ps
CPU time 58.68 seconds
Started Apr 30 01:53:50 PM PDT 24
Finished Apr 30 01:54:49 PM PDT 24
Peak memory 336148 kb
Host smart-1fd955d7-deb4-4cd4-bdcd-6585e7f003d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653023836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.1653023836
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.3152775933
Short name T558
Test name
Test status
Simulation time 83121081 ps
CPU time 0.65 seconds
Started Apr 30 01:53:40 PM PDT 24
Finished Apr 30 01:53:41 PM PDT 24
Peak memory 203840 kb
Host smart-783578cc-979b-4eab-91e0-85ba47dccf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152775933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.3152775933
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.1039587710
Short name T596
Test name
Test status
Simulation time 50574432947 ps
CPU time 486.77 seconds
Started Apr 30 01:53:40 PM PDT 24
Finished Apr 30 02:01:48 PM PDT 24
Peak memory 1272300 kb
Host smart-7c6d5251-2d7e-44d1-8dec-890e62461499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039587710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.1039587710
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.2005970685
Short name T1228
Test name
Test status
Simulation time 3811006346 ps
CPU time 40.69 seconds
Started Apr 30 01:53:38 PM PDT 24
Finished Apr 30 01:54:19 PM PDT 24
Peak memory 400108 kb
Host smart-a3fc7946-dd10-427a-afe0-cc5a39239fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005970685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.2005970685
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.3291918768
Short name T1269
Test name
Test status
Simulation time 98024827636 ps
CPU time 3032.89 seconds
Started Apr 30 01:53:40 PM PDT 24
Finished Apr 30 02:44:14 PM PDT 24
Peak memory 3984096 kb
Host smart-481bb25f-0267-4e2b-90b8-314a0be68b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291918768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.3291918768
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.1467184971
Short name T846
Test name
Test status
Simulation time 549243719 ps
CPU time 25.41 seconds
Started Apr 30 01:53:47 PM PDT 24
Finished Apr 30 01:54:13 PM PDT 24
Peak memory 212412 kb
Host smart-51570780-886d-4eef-97d9-5483359bece7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467184971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.1467184971
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.2372553795
Short name T1279
Test name
Test status
Simulation time 4059970015 ps
CPU time 3.97 seconds
Started Apr 30 01:53:48 PM PDT 24
Finished Apr 30 01:53:53 PM PDT 24
Peak memory 204452 kb
Host smart-372b4674-223d-46a7-8c95-dd4fc0c7202e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372553795 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.2372553795
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.2561568513
Short name T463
Test name
Test status
Simulation time 10212332951 ps
CPU time 29.08 seconds
Started Apr 30 01:53:47 PM PDT 24
Finished Apr 30 01:54:18 PM PDT 24
Peak memory 312152 kb
Host smart-7beaaf7f-3ae9-4558-a859-31c8cb563c27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561568513 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.2561568513
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.2094079848
Short name T1137
Test name
Test status
Simulation time 10131879640 ps
CPU time 83.31 seconds
Started Apr 30 01:53:47 PM PDT 24
Finished Apr 30 01:55:11 PM PDT 24
Peak memory 550316 kb
Host smart-f40b3cf5-b8c0-4c4f-a01a-bdf6c97cdb63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094079848 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.2094079848
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.1634158085
Short name T553
Test name
Test status
Simulation time 1233346927 ps
CPU time 3 seconds
Started Apr 30 01:53:51 PM PDT 24
Finished Apr 30 01:53:54 PM PDT 24
Peak memory 204200 kb
Host smart-944905fd-9404-4932-84c9-f2bf08bc35c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634158085 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.1634158085
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.3343052954
Short name T1015
Test name
Test status
Simulation time 1601259069 ps
CPU time 4.27 seconds
Started Apr 30 01:53:40 PM PDT 24
Finished Apr 30 01:53:45 PM PDT 24
Peak memory 209600 kb
Host smart-2ce0f5c4-507c-4b17-a85a-b5fa3020d3fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343052954 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.3343052954
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.2022891910
Short name T1200
Test name
Test status
Simulation time 2067846813 ps
CPU time 16.11 seconds
Started Apr 30 01:53:39 PM PDT 24
Finished Apr 30 01:53:56 PM PDT 24
Peak memory 204112 kb
Host smart-517af038-6ac5-49b6-9610-beb7ef709be6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022891910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.2022891910
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.2042534510
Short name T744
Test name
Test status
Simulation time 274714269 ps
CPU time 4.82 seconds
Started Apr 30 01:53:41 PM PDT 24
Finished Apr 30 01:53:47 PM PDT 24
Peak memory 204184 kb
Host smart-a0d4cf76-f161-429e-885a-d7e8f669d303
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042534510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.2042534510
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.3767552405
Short name T398
Test name
Test status
Simulation time 41404018183 ps
CPU time 89.01 seconds
Started Apr 30 01:53:39 PM PDT 24
Finished Apr 30 01:55:09 PM PDT 24
Peak memory 1453428 kb
Host smart-292818df-8593-4c81-b9e5-3c09e5e08a10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767552405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.3767552405
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.1757447243
Short name T1012
Test name
Test status
Simulation time 24268311907 ps
CPU time 59.02 seconds
Started Apr 30 01:53:48 PM PDT 24
Finished Apr 30 01:54:48 PM PDT 24
Peak memory 723368 kb
Host smart-8b00427f-df09-43a1-a461-31e5fd9109ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757447243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.1757447243
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_alert_test.425156038
Short name T1109
Test name
Test status
Simulation time 21536794 ps
CPU time 0.62 seconds
Started Apr 30 01:53:52 PM PDT 24
Finished Apr 30 01:53:53 PM PDT 24
Peak memory 203896 kb
Host smart-ff6ebaa1-b2d0-4a22-afa3-7f282eb0804d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425156038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.425156038
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.2138529556
Short name T446
Test name
Test status
Simulation time 111688287 ps
CPU time 1.58 seconds
Started Apr 30 01:53:45 PM PDT 24
Finished Apr 30 01:53:47 PM PDT 24
Peak memory 212460 kb
Host smart-5f10e50b-7fac-45ce-a873-ac521c09e6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138529556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.2138529556
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.70134027
Short name T1098
Test name
Test status
Simulation time 381009267 ps
CPU time 4.32 seconds
Started Apr 30 01:53:46 PM PDT 24
Finished Apr 30 01:53:50 PM PDT 24
Peak memory 232800 kb
Host smart-61f62190-b621-4f62-b56a-b2de69ae05e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70134027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empty
.70134027
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.1957890359
Short name T521
Test name
Test status
Simulation time 3719617516 ps
CPU time 56.68 seconds
Started Apr 30 01:53:46 PM PDT 24
Finished Apr 30 01:54:43 PM PDT 24
Peak memory 659224 kb
Host smart-fbc644a8-8b9f-4369-ae41-b3b6b7c588d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957890359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.1957890359
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.4180069924
Short name T984
Test name
Test status
Simulation time 1753537459 ps
CPU time 57.54 seconds
Started Apr 30 01:53:45 PM PDT 24
Finished Apr 30 01:54:43 PM PDT 24
Peak memory 622436 kb
Host smart-700f58c0-bbeb-493b-987c-7e2c9ab56c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180069924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.4180069924
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2890226374
Short name T1044
Test name
Test status
Simulation time 86004124 ps
CPU time 0.81 seconds
Started Apr 30 01:53:46 PM PDT 24
Finished Apr 30 01:53:48 PM PDT 24
Peak memory 203808 kb
Host smart-32993f79-c8cb-4329-88d7-8368fc9ba60d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890226374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2890226374
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.1880237962
Short name T972
Test name
Test status
Simulation time 1241281720 ps
CPU time 3.23 seconds
Started Apr 30 01:53:47 PM PDT 24
Finished Apr 30 01:53:51 PM PDT 24
Peak memory 204128 kb
Host smart-a49e3c4c-e8ac-449a-ad97-760fb518021e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880237962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.1880237962
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.1209491498
Short name T428
Test name
Test status
Simulation time 3052089812 ps
CPU time 73.34 seconds
Started Apr 30 01:53:48 PM PDT 24
Finished Apr 30 01:55:02 PM PDT 24
Peak memory 848288 kb
Host smart-e6a06b38-7bd3-4c77-b07d-2b0d31a6bc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209491498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.1209491498
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.465464817
Short name T860
Test name
Test status
Simulation time 1143922298 ps
CPU time 11.97 seconds
Started Apr 30 01:53:51 PM PDT 24
Finished Apr 30 01:54:03 PM PDT 24
Peak memory 204108 kb
Host smart-5c65014f-a4d7-4f9e-97f8-047e790b3ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465464817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.465464817
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.984451576
Short name T1057
Test name
Test status
Simulation time 2859028480 ps
CPU time 29.9 seconds
Started Apr 30 01:53:51 PM PDT 24
Finished Apr 30 01:54:22 PM PDT 24
Peak memory 432076 kb
Host smart-8160155c-add2-4811-be69-5b84789053ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984451576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.984451576
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.4015932825
Short name T1273
Test name
Test status
Simulation time 27039917 ps
CPU time 0.67 seconds
Started Apr 30 01:53:48 PM PDT 24
Finished Apr 30 01:53:50 PM PDT 24
Peak memory 203776 kb
Host smart-0a16b4a0-9b33-43c3-97f7-c49fa664d4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015932825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.4015932825
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.1767333944
Short name T1256
Test name
Test status
Simulation time 7505629640 ps
CPU time 79.12 seconds
Started Apr 30 01:53:50 PM PDT 24
Finished Apr 30 01:55:10 PM PDT 24
Peak memory 204248 kb
Host smart-6ff7a680-f005-4cb0-9f8e-554b07ad9ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767333944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.1767333944
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.4250770232
Short name T931
Test name
Test status
Simulation time 9416903316 ps
CPU time 68.35 seconds
Started Apr 30 01:53:45 PM PDT 24
Finished Apr 30 01:54:54 PM PDT 24
Peak memory 349172 kb
Host smart-3aeef6a7-8880-4151-a490-d72e88895258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250770232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.4250770232
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.1033902868
Short name T838
Test name
Test status
Simulation time 33290445137 ps
CPU time 297.83 seconds
Started Apr 30 01:53:48 PM PDT 24
Finished Apr 30 01:58:47 PM PDT 24
Peak memory 1130724 kb
Host smart-9ea3935f-5d5a-4208-9204-b961f53eea99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033902868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.1033902868
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.1401394350
Short name T414
Test name
Test status
Simulation time 3469836077 ps
CPU time 24.24 seconds
Started Apr 30 01:53:46 PM PDT 24
Finished Apr 30 01:54:11 PM PDT 24
Peak memory 212436 kb
Host smart-c29ee25a-d7a2-4fc7-84fa-ebdf81d70c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401394350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.1401394350
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.4147184952
Short name T313
Test name
Test status
Simulation time 912046501 ps
CPU time 3.03 seconds
Started Apr 30 01:53:54 PM PDT 24
Finished Apr 30 01:53:57 PM PDT 24
Peak memory 204200 kb
Host smart-4cf4f2d8-6820-4c07-a797-1af78093ce77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147184952 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.4147184952
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.653502069
Short name T118
Test name
Test status
Simulation time 10286511422 ps
CPU time 12.69 seconds
Started Apr 30 01:53:54 PM PDT 24
Finished Apr 30 01:54:07 PM PDT 24
Peak memory 236200 kb
Host smart-46665e35-facb-4df6-9a73-4f17433e4e4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653502069 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_acq.653502069
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.3114734668
Short name T890
Test name
Test status
Simulation time 1814558674 ps
CPU time 2.48 seconds
Started Apr 30 01:53:50 PM PDT 24
Finished Apr 30 01:53:53 PM PDT 24
Peak memory 204168 kb
Host smart-c180d9ae-6232-499a-80de-e6209ec0f60c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114734668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.3114734668
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.658114631
Short name T598
Test name
Test status
Simulation time 3871337338 ps
CPU time 4.07 seconds
Started Apr 30 01:53:47 PM PDT 24
Finished Apr 30 01:53:52 PM PDT 24
Peak memory 204288 kb
Host smart-4e467e1a-25cf-4766-a7a0-c7997aba1de9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658114631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_intr_smoke.658114631
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.2969179292
Short name T575
Test name
Test status
Simulation time 20078934426 ps
CPU time 483.64 seconds
Started Apr 30 01:53:46 PM PDT 24
Finished Apr 30 02:01:51 PM PDT 24
Peak memory 4619924 kb
Host smart-80d0f2e3-56cf-46e3-ab27-2a1c30280868
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969179292 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.2969179292
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.1922632655
Short name T1017
Test name
Test status
Simulation time 1910786595 ps
CPU time 13.51 seconds
Started Apr 30 01:53:51 PM PDT 24
Finished Apr 30 01:54:05 PM PDT 24
Peak memory 204088 kb
Host smart-f7841bda-9b6c-4cbc-9da6-30ae73f9ca0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922632655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.1922632655
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.4262512156
Short name T1223
Test name
Test status
Simulation time 11773452250 ps
CPU time 12.61 seconds
Started Apr 30 01:53:47 PM PDT 24
Finished Apr 30 01:54:01 PM PDT 24
Peak memory 218184 kb
Host smart-e6ffbb99-088a-4d70-be4d-a96d16033c8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262512156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.4262512156
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.2929385862
Short name T399
Test name
Test status
Simulation time 20025250228 ps
CPU time 11.14 seconds
Started Apr 30 01:53:46 PM PDT 24
Finished Apr 30 01:53:59 PM PDT 24
Peak memory 204212 kb
Host smart-ed869c70-6708-44a0-9447-9ded0bf09ecc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929385862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.2929385862
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.2776410829
Short name T340
Test name
Test status
Simulation time 13344060827 ps
CPU time 1550.03 seconds
Started Apr 30 01:53:46 PM PDT 24
Finished Apr 30 02:19:37 PM PDT 24
Peak memory 3123520 kb
Host smart-8baf238d-847d-4a60-b8dd-bb05b8e53129
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776410829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.2776410829
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.4094616234
Short name T477
Test name
Test status
Simulation time 1314812844 ps
CPU time 6.48 seconds
Started Apr 30 01:53:50 PM PDT 24
Finished Apr 30 01:53:57 PM PDT 24
Peak memory 218524 kb
Host smart-5720d8ed-4656-4f3f-bb9c-f7a98e8d1e3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094616234 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.4094616234
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.718573550
Short name T361
Test name
Test status
Simulation time 16935278 ps
CPU time 0.65 seconds
Started Apr 30 01:54:00 PM PDT 24
Finished Apr 30 01:54:02 PM PDT 24
Peak memory 203916 kb
Host smart-24e84228-89e5-440f-b0cc-2f4736106661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718573550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.718573550
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.3635914242
Short name T1290
Test name
Test status
Simulation time 43144372 ps
CPU time 1.07 seconds
Started Apr 30 01:53:51 PM PDT 24
Finished Apr 30 01:53:53 PM PDT 24
Peak memory 212420 kb
Host smart-d1cd1789-7413-4edb-9454-dc42c9c24256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635914242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.3635914242
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.1625248192
Short name T455
Test name
Test status
Simulation time 523208888 ps
CPU time 12.53 seconds
Started Apr 30 01:53:52 PM PDT 24
Finished Apr 30 01:54:05 PM PDT 24
Peak memory 251404 kb
Host smart-58da2645-1482-4a56-ad9a-0c25b8cddf42
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625248192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.1625248192
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.240478655
Short name T862
Test name
Test status
Simulation time 1644818403 ps
CPU time 38.9 seconds
Started Apr 30 01:53:50 PM PDT 24
Finished Apr 30 01:54:30 PM PDT 24
Peak memory 409280 kb
Host smart-bb379f2f-953b-4170-93c6-53bfb0b97eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240478655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.240478655
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.2865039792
Short name T41
Test name
Test status
Simulation time 2956116490 ps
CPU time 49.01 seconds
Started Apr 30 01:53:52 PM PDT 24
Finished Apr 30 01:54:42 PM PDT 24
Peak memory 562676 kb
Host smart-034390be-57c7-4a6e-901d-f4659553f786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865039792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.2865039792
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.1078203498
Short name T1088
Test name
Test status
Simulation time 109888725 ps
CPU time 1.05 seconds
Started Apr 30 01:53:52 PM PDT 24
Finished Apr 30 01:53:54 PM PDT 24
Peak memory 203996 kb
Host smart-2f1132fa-8c18-433f-a760-ab36d7d2c203
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078203498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.1078203498
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.569054702
Short name T858
Test name
Test status
Simulation time 278163226 ps
CPU time 3.4 seconds
Started Apr 30 01:53:53 PM PDT 24
Finished Apr 30 01:53:57 PM PDT 24
Peak memory 226668 kb
Host smart-405d2616-d7b8-465a-98ea-632aaf8c8205
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569054702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.
569054702
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.2047189203
Short name T1217
Test name
Test status
Simulation time 13121848674 ps
CPU time 64.32 seconds
Started Apr 30 01:54:00 PM PDT 24
Finished Apr 30 01:55:05 PM PDT 24
Peak memory 790196 kb
Host smart-f4648c69-444d-484f-86f1-8b1ee7286375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047189203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.2047189203
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.1027725300
Short name T634
Test name
Test status
Simulation time 1007265189 ps
CPU time 10.24 seconds
Started Apr 30 01:54:02 PM PDT 24
Finished Apr 30 01:54:13 PM PDT 24
Peak memory 204184 kb
Host smart-243259c0-eb87-4a3d-a528-9b623ad50476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027725300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1027725300
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.504287421
Short name T625
Test name
Test status
Simulation time 2941899809 ps
CPU time 29.37 seconds
Started Apr 30 01:54:02 PM PDT 24
Finished Apr 30 01:54:32 PM PDT 24
Peak memory 333852 kb
Host smart-11162ba2-36ea-4823-8d90-79a32c5d3c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504287421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.504287421
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.887272178
Short name T496
Test name
Test status
Simulation time 18675687 ps
CPU time 0.67 seconds
Started Apr 30 01:53:52 PM PDT 24
Finished Apr 30 01:53:54 PM PDT 24
Peak memory 203816 kb
Host smart-5e4fad1d-9234-4f71-85d5-6219f06bedc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887272178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.887272178
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.1743783656
Short name T973
Test name
Test status
Simulation time 4078476411 ps
CPU time 49.92 seconds
Started Apr 30 01:53:52 PM PDT 24
Finished Apr 30 01:54:42 PM PDT 24
Peak memory 312676 kb
Host smart-c9316596-6b4d-474c-95ba-9257dff1c981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743783656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1743783656
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.1484203419
Short name T646
Test name
Test status
Simulation time 1777341622 ps
CPU time 13.69 seconds
Started Apr 30 01:53:52 PM PDT 24
Finished Apr 30 01:54:06 PM PDT 24
Peak memory 220520 kb
Host smart-ef4e0c65-dd71-4125-8e40-546d3233edcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484203419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.1484203419
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.124870284
Short name T1303
Test name
Test status
Simulation time 409644141 ps
CPU time 2.15 seconds
Started Apr 30 01:53:59 PM PDT 24
Finished Apr 30 01:54:01 PM PDT 24
Peak memory 204112 kb
Host smart-adecad64-a1bf-496e-b610-c2f442d0496a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124870284 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.124870284
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.502742181
Short name T663
Test name
Test status
Simulation time 10844185744 ps
CPU time 8.09 seconds
Started Apr 30 01:53:56 PM PDT 24
Finished Apr 30 01:54:04 PM PDT 24
Peak memory 245380 kb
Host smart-cc5073f9-55d6-482e-83ab-be9e053b679e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502742181 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_acq.502742181
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.3205939424
Short name T1152
Test name
Test status
Simulation time 10379311132 ps
CPU time 12.08 seconds
Started Apr 30 01:53:56 PM PDT 24
Finished Apr 30 01:54:08 PM PDT 24
Peak memory 294260 kb
Host smart-a0aaac2f-1637-4101-916b-1318385b8ea4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205939424 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.3205939424
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.1447289085
Short name T1077
Test name
Test status
Simulation time 341492486 ps
CPU time 2.29 seconds
Started Apr 30 01:54:00 PM PDT 24
Finished Apr 30 01:54:02 PM PDT 24
Peak memory 204168 kb
Host smart-f6109154-a4bd-4155-aa67-f2e1b296ad95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447289085 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.1447289085
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.2610657460
Short name T621
Test name
Test status
Simulation time 4312245199 ps
CPU time 5.51 seconds
Started Apr 30 01:53:56 PM PDT 24
Finished Apr 30 01:54:02 PM PDT 24
Peak memory 219852 kb
Host smart-647499d9-367a-4037-be5e-f11d92dab427
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610657460 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.2610657460
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.1585400004
Short name T413
Test name
Test status
Simulation time 15318724903 ps
CPU time 313.27 seconds
Started Apr 30 01:53:56 PM PDT 24
Finished Apr 30 01:59:09 PM PDT 24
Peak memory 3695332 kb
Host smart-422d0cf4-daa3-441d-b4eb-e584695ded5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585400004 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.1585400004
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.242283477
Short name T1282
Test name
Test status
Simulation time 3240977848 ps
CPU time 15.09 seconds
Started Apr 30 01:53:53 PM PDT 24
Finished Apr 30 01:54:08 PM PDT 24
Peak memory 204200 kb
Host smart-cf2584b8-9683-4289-a7bf-30a0ab0a5ee0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242283477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_tar
get_smoke.242283477
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.861835000
Short name T996
Test name
Test status
Simulation time 728027852 ps
CPU time 5.41 seconds
Started Apr 30 01:53:59 PM PDT 24
Finished Apr 30 01:54:05 PM PDT 24
Peak memory 204140 kb
Host smart-3bd05202-dde7-451c-8378-3eb66f737176
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861835000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_rd.861835000
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.3407175733
Short name T426
Test name
Test status
Simulation time 39871965302 ps
CPU time 490.45 seconds
Started Apr 30 01:53:58 PM PDT 24
Finished Apr 30 02:02:09 PM PDT 24
Peak memory 4315616 kb
Host smart-fff41482-cf30-47bf-af76-5307199b243b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407175733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.3407175733
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.2990490722
Short name T1263
Test name
Test status
Simulation time 18106969376 ps
CPU time 1059.76 seconds
Started Apr 30 01:53:55 PM PDT 24
Finished Apr 30 02:11:36 PM PDT 24
Peak memory 2204432 kb
Host smart-df8f07cc-8f39-4769-9f99-c9996dfcb816
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990490722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.2990490722
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.3828771840
Short name T1267
Test name
Test status
Simulation time 6393027664 ps
CPU time 7.75 seconds
Started Apr 30 01:54:01 PM PDT 24
Finished Apr 30 01:54:09 PM PDT 24
Peak memory 218964 kb
Host smart-6f2aac68-e7d9-4340-917a-4bc5a432fda3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828771840 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.3828771840
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.918073034
Short name T1360
Test name
Test status
Simulation time 19659616 ps
CPU time 0.61 seconds
Started Apr 30 01:54:06 PM PDT 24
Finished Apr 30 01:54:07 PM PDT 24
Peak memory 203896 kb
Host smart-8f616d6b-2f03-42c2-b025-519e7bd62c6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918073034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.918073034
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.1677758618
Short name T577
Test name
Test status
Simulation time 649664423 ps
CPU time 1.41 seconds
Started Apr 30 01:54:00 PM PDT 24
Finished Apr 30 01:54:02 PM PDT 24
Peak memory 204192 kb
Host smart-1d6e4f2b-ee11-4e0c-a784-2552863b2ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677758618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.1677758618
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.2567954168
Short name T183
Test name
Test status
Simulation time 710598388 ps
CPU time 8.38 seconds
Started Apr 30 01:54:00 PM PDT 24
Finished Apr 30 01:54:09 PM PDT 24
Peak memory 282384 kb
Host smart-13ba7ef9-71af-4116-ac41-96e33cad2407
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567954168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.2567954168
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.4127775976
Short name T1147
Test name
Test status
Simulation time 4101151162 ps
CPU time 49.14 seconds
Started Apr 30 01:54:00 PM PDT 24
Finished Apr 30 01:54:50 PM PDT 24
Peak memory 479756 kb
Host smart-b1c6d00b-533a-44eb-95f2-c9be3ebcbe94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127775976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.4127775976
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.3427480489
Short name T199
Test name
Test status
Simulation time 7856034864 ps
CPU time 55.32 seconds
Started Apr 30 01:54:00 PM PDT 24
Finished Apr 30 01:54:56 PM PDT 24
Peak memory 663124 kb
Host smart-0529c66e-b2ad-4899-a4c2-351cfd888c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427480489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.3427480489
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.2202133660
Short name T1216
Test name
Test status
Simulation time 809730644 ps
CPU time 0.87 seconds
Started Apr 30 01:54:01 PM PDT 24
Finished Apr 30 01:54:02 PM PDT 24
Peak memory 203940 kb
Host smart-36a22e62-4e32-499d-9340-cff1c0f2c586
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202133660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.2202133660
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.2467946669
Short name T1150
Test name
Test status
Simulation time 806313601 ps
CPU time 6.14 seconds
Started Apr 30 01:54:00 PM PDT 24
Finished Apr 30 01:54:07 PM PDT 24
Peak memory 243064 kb
Host smart-ad93b2a0-6f21-4384-a1b0-23a24346196e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467946669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.2467946669
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.2890725067
Short name T44
Test name
Test status
Simulation time 23383716464 ps
CPU time 81.07 seconds
Started Apr 30 01:54:02 PM PDT 24
Finished Apr 30 01:55:23 PM PDT 24
Peak memory 901332 kb
Host smart-7caf55f5-748b-40ea-b598-ff8ddce57995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890725067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.2890725067
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.2519714194
Short name T1229
Test name
Test status
Simulation time 1387554395 ps
CPU time 4.76 seconds
Started Apr 30 01:54:07 PM PDT 24
Finished Apr 30 01:54:12 PM PDT 24
Peak memory 204152 kb
Host smart-4e71c828-9726-481a-8d51-5ed0332763be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519714194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.2519714194
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.1522193116
Short name T692
Test name
Test status
Simulation time 1511809902 ps
CPU time 76.01 seconds
Started Apr 30 01:54:08 PM PDT 24
Finished Apr 30 01:55:24 PM PDT 24
Peak memory 396660 kb
Host smart-ef335170-a529-48fd-b8c1-b712f8746a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522193116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.1522193116
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.387876742
Short name T316
Test name
Test status
Simulation time 43881215 ps
CPU time 0.64 seconds
Started Apr 30 01:54:00 PM PDT 24
Finished Apr 30 01:54:01 PM PDT 24
Peak memory 203764 kb
Host smart-b6ded0f1-4d0e-489d-8a3e-5325bb065112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387876742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.387876742
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.2270058682
Short name T766
Test name
Test status
Simulation time 1265033848 ps
CPU time 50.95 seconds
Started Apr 30 01:54:00 PM PDT 24
Finished Apr 30 01:54:52 PM PDT 24
Peak memory 204172 kb
Host smart-3f5b762b-941a-4ba6-a84b-e3b545b55e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270058682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.2270058682
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.69679655
Short name T1028
Test name
Test status
Simulation time 1563478452 ps
CPU time 27.21 seconds
Started Apr 30 01:54:01 PM PDT 24
Finished Apr 30 01:54:29 PM PDT 24
Peak memory 284516 kb
Host smart-48777cd5-7ee8-4a68-b8f4-068694d8144b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69679655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.69679655
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.578052995
Short name T253
Test name
Test status
Simulation time 70588130437 ps
CPU time 780.76 seconds
Started Apr 30 01:54:01 PM PDT 24
Finished Apr 30 02:07:02 PM PDT 24
Peak memory 2274852 kb
Host smart-3594460a-215f-4c69-90b3-4bf83010f1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578052995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.578052995
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.2398537465
Short name T653
Test name
Test status
Simulation time 2444332807 ps
CPU time 18.8 seconds
Started Apr 30 01:54:03 PM PDT 24
Finished Apr 30 01:54:22 PM PDT 24
Peak memory 212420 kb
Host smart-0648f908-4f4e-421d-922c-5ad57366ca7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398537465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.2398537465
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.2142428200
Short name T677
Test name
Test status
Simulation time 1726164938 ps
CPU time 2.64 seconds
Started Apr 30 01:54:07 PM PDT 24
Finished Apr 30 01:54:10 PM PDT 24
Peak memory 204116 kb
Host smart-3af86fd3-c795-47c0-8d29-ff7955cac477
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142428200 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.2142428200
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.2540254782
Short name T1066
Test name
Test status
Simulation time 10229971178 ps
CPU time 10.25 seconds
Started Apr 30 01:54:06 PM PDT 24
Finished Apr 30 01:54:17 PM PDT 24
Peak memory 251456 kb
Host smart-bbad8470-a40d-4c2f-9ffa-86689ea6bd0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540254782 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.2540254782
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.2572296940
Short name T431
Test name
Test status
Simulation time 10276108615 ps
CPU time 11.8 seconds
Started Apr 30 01:54:06 PM PDT 24
Finished Apr 30 01:54:18 PM PDT 24
Peak memory 295464 kb
Host smart-3b991cb0-51ef-4bc3-bfff-e68ea02ea4db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572296940 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.2572296940
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.1700122002
Short name T1219
Test name
Test status
Simulation time 423801687 ps
CPU time 2.56 seconds
Started Apr 30 01:54:08 PM PDT 24
Finished Apr 30 01:54:11 PM PDT 24
Peak memory 204156 kb
Host smart-0eaddf7c-e0cb-4cf7-9db5-7c1b80bc2d0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700122002 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.1700122002
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.609118266
Short name T276
Test name
Test status
Simulation time 6923607711 ps
CPU time 5.96 seconds
Started Apr 30 01:54:01 PM PDT 24
Finished Apr 30 01:54:07 PM PDT 24
Peak memory 212856 kb
Host smart-9be6824b-4d48-42a1-a10c-e42dfc5dfa45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609118266 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_intr_smoke.609118266
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.2562772873
Short name T437
Test name
Test status
Simulation time 9836683941 ps
CPU time 4.64 seconds
Started Apr 30 01:54:01 PM PDT 24
Finished Apr 30 01:54:07 PM PDT 24
Peak memory 204180 kb
Host smart-1a51ff93-d637-419d-8ea3-f0e3816f1763
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562772873 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.2562772873
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.2171204457
Short name T435
Test name
Test status
Simulation time 807776565 ps
CPU time 30.37 seconds
Started Apr 30 01:54:01 PM PDT 24
Finished Apr 30 01:54:32 PM PDT 24
Peak memory 204128 kb
Host smart-d4df78fb-47f2-4f2d-ae60-0eb85454dcca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171204457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.2171204457
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.647626081
Short name T1113
Test name
Test status
Simulation time 315323541 ps
CPU time 13.21 seconds
Started Apr 30 01:54:00 PM PDT 24
Finished Apr 30 01:54:13 PM PDT 24
Peak memory 204064 kb
Host smart-631cfa02-948e-42a2-b309-db31bb4fde0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647626081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_rd.647626081
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.2241651496
Short name T535
Test name
Test status
Simulation time 8393686737 ps
CPU time 17.11 seconds
Started Apr 30 01:54:02 PM PDT 24
Finished Apr 30 01:54:20 PM PDT 24
Peak memory 204216 kb
Host smart-a6a4e6ea-28a1-4915-8472-e90f5569e532
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241651496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.2241651496
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.3399266930
Short name T856
Test name
Test status
Simulation time 17325878386 ps
CPU time 616.57 seconds
Started Apr 30 01:54:02 PM PDT 24
Finished Apr 30 02:04:19 PM PDT 24
Peak memory 3481460 kb
Host smart-8453d73a-d520-4264-b3c2-fef41a0c54a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399266930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.3399266930
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.2056993085
Short name T1221
Test name
Test status
Simulation time 1293503824 ps
CPU time 6.73 seconds
Started Apr 30 01:54:07 PM PDT 24
Finished Apr 30 01:54:14 PM PDT 24
Peak memory 212392 kb
Host smart-ff118134-b8f3-41c0-a013-c9bd37fab7e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056993085 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.2056993085
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.3501901950
Short name T482
Test name
Test status
Simulation time 16927692 ps
CPU time 0.64 seconds
Started Apr 30 01:54:19 PM PDT 24
Finished Apr 30 01:54:20 PM PDT 24
Peak memory 203920 kb
Host smart-751218bd-970c-41d6-9d9b-279a37792721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501901950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.3501901950
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.2334575516
Short name T520
Test name
Test status
Simulation time 188383396 ps
CPU time 1.84 seconds
Started Apr 30 01:54:13 PM PDT 24
Finished Apr 30 01:54:16 PM PDT 24
Peak memory 212476 kb
Host smart-7575f093-3fb5-4663-863a-964bdd55663a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334575516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.2334575516
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.733892743
Short name T1220
Test name
Test status
Simulation time 1074734570 ps
CPU time 4.85 seconds
Started Apr 30 01:54:11 PM PDT 24
Finished Apr 30 01:54:17 PM PDT 24
Peak memory 250516 kb
Host smart-8e43f269-ef4e-49fc-b978-c7fffad0e7e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733892743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empt
y.733892743
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.2352125781
Short name T348
Test name
Test status
Simulation time 1402375434 ps
CPU time 41.18 seconds
Started Apr 30 01:54:12 PM PDT 24
Finished Apr 30 01:54:54 PM PDT 24
Peak memory 552628 kb
Host smart-c467e8a7-758f-4566-8fdf-355e4e66861a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352125781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.2352125781
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.2519917635
Short name T370
Test name
Test status
Simulation time 2000924681 ps
CPU time 150.03 seconds
Started Apr 30 01:54:16 PM PDT 24
Finished Apr 30 01:56:47 PM PDT 24
Peak memory 678940 kb
Host smart-c40c01ea-1cd8-4f70-8a93-57df096a1f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519917635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2519917635
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.293884898
Short name T839
Test name
Test status
Simulation time 82422333 ps
CPU time 0.81 seconds
Started Apr 30 01:54:14 PM PDT 24
Finished Apr 30 01:54:15 PM PDT 24
Peak memory 203976 kb
Host smart-13d2489a-dac4-4d4f-8361-277251a6a2ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293884898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fm
t.293884898
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.4064796695
Short name T1175
Test name
Test status
Simulation time 525699132 ps
CPU time 4.83 seconds
Started Apr 30 01:54:12 PM PDT 24
Finished Apr 30 01:54:17 PM PDT 24
Peak memory 236976 kb
Host smart-3f091bb6-a715-4057-9e0e-571648cb46be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064796695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.4064796695
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.847129924
Short name T1248
Test name
Test status
Simulation time 18324445829 ps
CPU time 167.91 seconds
Started Apr 30 01:54:12 PM PDT 24
Finished Apr 30 01:57:01 PM PDT 24
Peak memory 814548 kb
Host smart-c7f44cde-1746-4202-8c1c-c3ce6b8de26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847129924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.847129924
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1200930559
Short name T357
Test name
Test status
Simulation time 1794598268 ps
CPU time 12.55 seconds
Started Apr 30 01:54:20 PM PDT 24
Finished Apr 30 01:54:34 PM PDT 24
Peak memory 204120 kb
Host smart-e2c16cab-b9b4-4868-b56c-0e5287a90398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200930559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1200930559
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.1554939547
Short name T569
Test name
Test status
Simulation time 16961102712 ps
CPU time 34.74 seconds
Started Apr 30 01:54:20 PM PDT 24
Finished Apr 30 01:54:55 PM PDT 24
Peak memory 328764 kb
Host smart-44cfa7a2-8290-4716-9747-4cbb577fce0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554939547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.1554939547
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.3856034818
Short name T190
Test name
Test status
Simulation time 28788502 ps
CPU time 0.66 seconds
Started Apr 30 01:54:13 PM PDT 24
Finished Apr 30 01:54:14 PM PDT 24
Peak memory 203864 kb
Host smart-b2870b36-2a45-467f-bd7d-f49fc1bece7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856034818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.3856034818
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.1073047790
Short name T787
Test name
Test status
Simulation time 3919350648 ps
CPU time 39.31 seconds
Started Apr 30 01:54:12 PM PDT 24
Finished Apr 30 01:54:52 PM PDT 24
Peak memory 542552 kb
Host smart-cb07f3a8-22d2-451e-bab1-f39469b8039e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073047790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.1073047790
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.3248411386
Short name T673
Test name
Test status
Simulation time 4686874106 ps
CPU time 55.66 seconds
Started Apr 30 01:54:10 PM PDT 24
Finished Apr 30 01:55:06 PM PDT 24
Peak memory 333248 kb
Host smart-635a4957-deb7-48b2-a2b9-e76f040fff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248411386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3248411386
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.1898986151
Short name T998
Test name
Test status
Simulation time 45046668210 ps
CPU time 765.69 seconds
Started Apr 30 01:54:12 PM PDT 24
Finished Apr 30 02:06:59 PM PDT 24
Peak memory 1795392 kb
Host smart-8b5afb09-a0ba-4dde-b349-ecd39d676978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898986151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.1898986151
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.3209682211
Short name T769
Test name
Test status
Simulation time 796054063 ps
CPU time 35.05 seconds
Started Apr 30 01:54:13 PM PDT 24
Finished Apr 30 01:54:48 PM PDT 24
Peak memory 212372 kb
Host smart-4241415a-bbb0-467f-8054-8c77250fe8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209682211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.3209682211
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.2113070274
Short name T864
Test name
Test status
Simulation time 8941778622 ps
CPU time 4.97 seconds
Started Apr 30 01:54:19 PM PDT 24
Finished Apr 30 01:54:25 PM PDT 24
Peak memory 204228 kb
Host smart-e254cc23-6ab4-4b5f-b3c7-6ce87ea0e7bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113070274 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.2113070274
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.1844710374
Short name T53
Test name
Test status
Simulation time 10249719376 ps
CPU time 28.01 seconds
Started Apr 30 01:54:20 PM PDT 24
Finished Apr 30 01:54:49 PM PDT 24
Peak memory 347308 kb
Host smart-02f72b90-fe76-4bfe-abd7-02e38af307bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844710374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.1844710374
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.3036456397
Short name T785
Test name
Test status
Simulation time 10123718995 ps
CPU time 69.08 seconds
Started Apr 30 01:54:26 PM PDT 24
Finished Apr 30 01:55:35 PM PDT 24
Peak memory 465340 kb
Host smart-4c25a564-9013-4751-94bf-c0fc38c66511
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036456397 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.3036456397
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.1175775453
Short name T770
Test name
Test status
Simulation time 831447034 ps
CPU time 2.59 seconds
Started Apr 30 01:54:21 PM PDT 24
Finished Apr 30 01:54:24 PM PDT 24
Peak memory 204152 kb
Host smart-fb7e89c1-cb70-4f51-b521-54331dc87e79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175775453 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.1175775453
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.360397802
Short name T1321
Test name
Test status
Simulation time 4725670552 ps
CPU time 4.05 seconds
Started Apr 30 01:54:11 PM PDT 24
Finished Apr 30 01:54:15 PM PDT 24
Peak memory 204248 kb
Host smart-7d4864ee-bf5e-41ae-9591-ee36e773e76e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360397802 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_intr_smoke.360397802
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.3216695800
Short name T19
Test name
Test status
Simulation time 15542878588 ps
CPU time 165.59 seconds
Started Apr 30 01:54:12 PM PDT 24
Finished Apr 30 01:56:58 PM PDT 24
Peak memory 2151744 kb
Host smart-58bdf252-189d-445e-8b5e-ec0ef6379822
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216695800 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.3216695800
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.1533835888
Short name T966
Test name
Test status
Simulation time 5231711305 ps
CPU time 20.98 seconds
Started Apr 30 01:54:13 PM PDT 24
Finished Apr 30 01:54:35 PM PDT 24
Peak memory 204220 kb
Host smart-aedb36fe-571a-4914-abcb-6b5b0ae4fd03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533835888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.1533835888
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.2032062740
Short name T342
Test name
Test status
Simulation time 992817211 ps
CPU time 42.68 seconds
Started Apr 30 01:54:11 PM PDT 24
Finished Apr 30 01:54:55 PM PDT 24
Peak memory 204344 kb
Host smart-1c744fde-7be0-4dba-ae61-c82d896bc4e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032062740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.2032062740
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.3466034355
Short name T802
Test name
Test status
Simulation time 47259271351 ps
CPU time 127 seconds
Started Apr 30 01:54:13 PM PDT 24
Finished Apr 30 01:56:21 PM PDT 24
Peak memory 1725892 kb
Host smart-d4c439ff-d17e-4d14-8b5c-d9a072dd4bf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466034355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.3466034355
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.3249743002
Short name T659
Test name
Test status
Simulation time 7153961070 ps
CPU time 216.92 seconds
Started Apr 30 01:54:13 PM PDT 24
Finished Apr 30 01:57:51 PM PDT 24
Peak memory 1770252 kb
Host smart-2d501a3c-d7d6-4272-8926-bd37ca4dec33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249743002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.3249743002
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.1595867441
Short name T582
Test name
Test status
Simulation time 1274999672 ps
CPU time 6.32 seconds
Started Apr 30 01:54:13 PM PDT 24
Finished Apr 30 01:54:19 PM PDT 24
Peak memory 212376 kb
Host smart-aeb56f23-aa73-4320-bea5-55d7d2145fb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595867441 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.1595867441
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.3932258140
Short name T1148
Test name
Test status
Simulation time 29130076 ps
CPU time 0.69 seconds
Started Apr 30 01:54:26 PM PDT 24
Finished Apr 30 01:54:27 PM PDT 24
Peak memory 203888 kb
Host smart-17a9dfc2-e87a-489d-a385-ebdef1451008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932258140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3932258140
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.1232247288
Short name T501
Test name
Test status
Simulation time 865127592 ps
CPU time 1.88 seconds
Started Apr 30 01:54:19 PM PDT 24
Finished Apr 30 01:54:21 PM PDT 24
Peak memory 212476 kb
Host smart-4058d64e-dd69-4350-989a-85512a6923d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232247288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.1232247288
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2028594521
Short name T112
Test name
Test status
Simulation time 275188268 ps
CPU time 6.22 seconds
Started Apr 30 01:54:21 PM PDT 24
Finished Apr 30 01:54:27 PM PDT 24
Peak memory 258808 kb
Host smart-5d07a562-851a-4ed9-85d1-62d56bbdcd7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028594521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.2028594521
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.731871846
Short name T1345
Test name
Test status
Simulation time 2516274031 ps
CPU time 39.39 seconds
Started Apr 30 01:54:25 PM PDT 24
Finished Apr 30 01:55:05 PM PDT 24
Peak memory 546296 kb
Host smart-ae83bd1c-26c3-4505-8f43-e6f74466e605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731871846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.731871846
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.3254740741
Short name T699
Test name
Test status
Simulation time 6742603377 ps
CPU time 52.43 seconds
Started Apr 30 01:54:20 PM PDT 24
Finished Apr 30 01:55:13 PM PDT 24
Peak memory 605884 kb
Host smart-a415859a-09c7-4c2a-8c07-f4b3a0e863c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254740741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.3254740741
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.1558322225
Short name T670
Test name
Test status
Simulation time 92724822 ps
CPU time 0.91 seconds
Started Apr 30 01:54:20 PM PDT 24
Finished Apr 30 01:54:21 PM PDT 24
Peak memory 204000 kb
Host smart-d8a3655a-154d-403b-a797-b8a64e61aedd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558322225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.1558322225
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.3094805622
Short name T1146
Test name
Test status
Simulation time 92806237 ps
CPU time 2.8 seconds
Started Apr 30 01:54:20 PM PDT 24
Finished Apr 30 01:54:23 PM PDT 24
Peak memory 215480 kb
Host smart-1edb83f9-ceb4-4f55-8e38-32236835ce70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094805622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.3094805622
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.757110089
Short name T1211
Test name
Test status
Simulation time 3058873124 ps
CPU time 70.39 seconds
Started Apr 30 01:54:18 PM PDT 24
Finished Apr 30 01:55:29 PM PDT 24
Peak memory 957632 kb
Host smart-3c0e5c05-b7b2-4acd-91ae-55494f7cbf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757110089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.757110089
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.3286289507
Short name T216
Test name
Test status
Simulation time 267176176 ps
CPU time 3.65 seconds
Started Apr 30 01:54:24 PM PDT 24
Finished Apr 30 01:54:28 PM PDT 24
Peak memory 204156 kb
Host smart-c372dd19-f0c5-4fe6-8129-360030d79b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286289507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.3286289507
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.4050451724
Short name T917
Test name
Test status
Simulation time 7957211472 ps
CPU time 90.42 seconds
Started Apr 30 01:54:26 PM PDT 24
Finished Apr 30 01:55:57 PM PDT 24
Peak memory 316984 kb
Host smart-7723e4c7-4ef9-4536-b01c-b665120592db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050451724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.4050451724
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.2116608510
Short name T1316
Test name
Test status
Simulation time 40806064 ps
CPU time 0.66 seconds
Started Apr 30 01:54:18 PM PDT 24
Finished Apr 30 01:54:20 PM PDT 24
Peak memory 203828 kb
Host smart-5e98f4e2-0cbc-4f1d-bc40-4f23722097e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116608510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2116608510
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.1258453489
Short name T975
Test name
Test status
Simulation time 24919838182 ps
CPU time 1162.11 seconds
Started Apr 30 01:54:21 PM PDT 24
Finished Apr 30 02:13:43 PM PDT 24
Peak memory 322716 kb
Host smart-4f773a03-925f-4c46-8ef4-4abc21c4eb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258453489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1258453489
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.2027369418
Short name T881
Test name
Test status
Simulation time 795803330 ps
CPU time 36.36 seconds
Started Apr 30 01:54:19 PM PDT 24
Finished Apr 30 01:54:56 PM PDT 24
Peak memory 251800 kb
Host smart-4cad31a9-33da-42e4-bdf7-ffe321e5175c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027369418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2027369418
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.296340283
Short name T252
Test name
Test status
Simulation time 9216920994 ps
CPU time 683.79 seconds
Started Apr 30 01:54:20 PM PDT 24
Finished Apr 30 02:05:44 PM PDT 24
Peak memory 1514408 kb
Host smart-ba24afbd-0f03-4ce3-8719-05a9a6359bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296340283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.296340283
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.1081681808
Short name T559
Test name
Test status
Simulation time 1354928314 ps
CPU time 6.47 seconds
Started Apr 30 01:54:19 PM PDT 24
Finished Apr 30 01:54:25 PM PDT 24
Peak memory 212432 kb
Host smart-1345451c-0dba-4b15-b8bf-cdc4776cff24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081681808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.1081681808
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.3116150991
Short name T786
Test name
Test status
Simulation time 3288189000 ps
CPU time 4.36 seconds
Started Apr 30 01:54:24 PM PDT 24
Finished Apr 30 01:54:29 PM PDT 24
Peak memory 212440 kb
Host smart-0740f13a-b9c7-4472-9285-10570e38f3e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116150991 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.3116150991
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.3613697694
Short name T1352
Test name
Test status
Simulation time 10377820359 ps
CPU time 9.11 seconds
Started Apr 30 01:54:25 PM PDT 24
Finished Apr 30 01:54:35 PM PDT 24
Peak memory 258952 kb
Host smart-5c5e8a95-1c39-4593-956e-f46b2becb8d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613697694 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.3613697694
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3154877929
Short name T1174
Test name
Test status
Simulation time 10105041176 ps
CPU time 75.25 seconds
Started Apr 30 01:54:21 PM PDT 24
Finished Apr 30 01:55:37 PM PDT 24
Peak memory 544460 kb
Host smart-cd1ec4f0-b13e-43d0-9b9c-458dc8634089
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154877929 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3154877929
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.1956636429
Short name T392
Test name
Test status
Simulation time 1227892279 ps
CPU time 2.14 seconds
Started Apr 30 01:54:23 PM PDT 24
Finished Apr 30 01:54:26 PM PDT 24
Peak memory 204132 kb
Host smart-704f9b9b-c590-4927-b5f8-7a1d8dd04207
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956636429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.1956636429
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.4217689432
Short name T362
Test name
Test status
Simulation time 1168411336 ps
CPU time 5.13 seconds
Started Apr 30 01:54:26 PM PDT 24
Finished Apr 30 01:54:31 PM PDT 24
Peak memory 204176 kb
Host smart-ef52827a-0266-4545-b865-39ae7001a441
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217689432 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.4217689432
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.3580216717
Short name T759
Test name
Test status
Simulation time 18068143279 ps
CPU time 16.77 seconds
Started Apr 30 01:54:24 PM PDT 24
Finished Apr 30 01:54:41 PM PDT 24
Peak memory 423220 kb
Host smart-0ff2e78a-855d-41de-97c1-3b425330a492
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580216717 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.3580216717
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.1245279821
Short name T1126
Test name
Test status
Simulation time 642578677 ps
CPU time 10.54 seconds
Started Apr 30 01:54:22 PM PDT 24
Finished Apr 30 01:54:33 PM PDT 24
Peak memory 204148 kb
Host smart-e14652be-5892-48e4-be62-105f3794f923
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245279821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.1245279821
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.3682618243
Short name T384
Test name
Test status
Simulation time 1978248870 ps
CPU time 6.65 seconds
Started Apr 30 01:54:23 PM PDT 24
Finished Apr 30 01:54:30 PM PDT 24
Peak memory 204756 kb
Host smart-72476a6b-4be0-4e11-acf2-2baa8df5363c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682618243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.3682618243
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.3744630100
Short name T98
Test name
Test status
Simulation time 67283791149 ps
CPU time 1147.65 seconds
Started Apr 30 01:54:23 PM PDT 24
Finished Apr 30 02:13:32 PM PDT 24
Peak memory 7257564 kb
Host smart-7cd0048c-6d6d-4ddd-9411-555eef6840f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744630100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.3744630100
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.3964960453
Short name T547
Test name
Test status
Simulation time 9758274975 ps
CPU time 22.8 seconds
Started Apr 30 01:54:22 PM PDT 24
Finished Apr 30 01:54:45 PM PDT 24
Peak memory 444984 kb
Host smart-4ec05d5c-f51c-4052-a461-97a828c2b920
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964960453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.3964960453
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.1678426586
Short name T262
Test name
Test status
Simulation time 9534658898 ps
CPU time 6.41 seconds
Started Apr 30 01:54:22 PM PDT 24
Finished Apr 30 01:54:29 PM PDT 24
Peak memory 220536 kb
Host smart-06826dd3-5563-41d0-9392-ee1ed43bed05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678426586 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.1678426586
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.2872186884
Short name T407
Test name
Test status
Simulation time 154970926 ps
CPU time 1.37 seconds
Started Apr 30 01:54:28 PM PDT 24
Finished Apr 30 01:54:30 PM PDT 24
Peak memory 212448 kb
Host smart-da4b47d2-5dca-43f1-a7e0-0eeee38714df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872186884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.2872186884
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.4141148989
Short name T372
Test name
Test status
Simulation time 400341933 ps
CPU time 9.12 seconds
Started Apr 30 01:54:29 PM PDT 24
Finished Apr 30 01:54:38 PM PDT 24
Peak memory 280716 kb
Host smart-08a542a3-0b5b-44af-aba8-a98750b0f954
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141148989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.4141148989
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.2864511972
Short name T1154
Test name
Test status
Simulation time 1716526423 ps
CPU time 53.8 seconds
Started Apr 30 01:54:27 PM PDT 24
Finished Apr 30 01:55:21 PM PDT 24
Peak memory 585740 kb
Host smart-a9e1380a-b1d8-47b7-92f0-0d79b541f4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864511972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2864511972
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.166899623
Short name T60
Test name
Test status
Simulation time 9346380362 ps
CPU time 55.53 seconds
Started Apr 30 01:54:26 PM PDT 24
Finished Apr 30 01:55:22 PM PDT 24
Peak memory 665880 kb
Host smart-fd4cf3fa-e371-456c-9c08-9497937d6e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166899623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.166899623
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.3232622978
Short name T1177
Test name
Test status
Simulation time 306767593 ps
CPU time 1.14 seconds
Started Apr 30 01:54:23 PM PDT 24
Finished Apr 30 01:54:25 PM PDT 24
Peak memory 204184 kb
Host smart-64fc7c84-b2ac-47ce-bb1c-4830c53ea273
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232622978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.3232622978
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.2350092937
Short name T919
Test name
Test status
Simulation time 537877010 ps
CPU time 6.57 seconds
Started Apr 30 01:54:32 PM PDT 24
Finished Apr 30 01:54:39 PM PDT 24
Peak memory 220104 kb
Host smart-5495ef4e-455d-4a85-a8e1-6dba25e1d08f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350092937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.2350092937
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.779949012
Short name T195
Test name
Test status
Simulation time 3911702194 ps
CPU time 124.51 seconds
Started Apr 30 01:54:23 PM PDT 24
Finished Apr 30 01:56:29 PM PDT 24
Peak memory 1168028 kb
Host smart-a8df9ce3-703d-4245-9d19-461e73fc045d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779949012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.779949012
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.1305750184
Short name T914
Test name
Test status
Simulation time 820937825 ps
CPU time 9.43 seconds
Started Apr 30 01:54:28 PM PDT 24
Finished Apr 30 01:54:38 PM PDT 24
Peak memory 204228 kb
Host smart-efddf989-5974-4a19-8af7-d1e987e1d5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305750184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.1305750184
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.871208718
Short name T738
Test name
Test status
Simulation time 1520897295 ps
CPU time 27.6 seconds
Started Apr 30 01:54:28 PM PDT 24
Finished Apr 30 01:54:56 PM PDT 24
Peak memory 294140 kb
Host smart-9995bd33-e5c3-4241-861c-8634b7ed76c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871208718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.871208718
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.236554578
Short name T258
Test name
Test status
Simulation time 37150692 ps
CPU time 0.66 seconds
Started Apr 30 01:54:22 PM PDT 24
Finished Apr 30 01:54:23 PM PDT 24
Peak memory 203760 kb
Host smart-07073b33-b9cb-4a59-9984-e506c76456bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236554578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.236554578
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.1576140084
Short name T946
Test name
Test status
Simulation time 2972651577 ps
CPU time 189.64 seconds
Started Apr 30 01:54:38 PM PDT 24
Finished Apr 30 01:57:49 PM PDT 24
Peak memory 617368 kb
Host smart-6573890e-49e4-4173-a5a8-3f2265ed1860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576140084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.1576140084
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.511046653
Short name T964
Test name
Test status
Simulation time 1316715585 ps
CPU time 61.16 seconds
Started Apr 30 01:54:25 PM PDT 24
Finished Apr 30 01:55:26 PM PDT 24
Peak memory 319720 kb
Host smart-865cb6cc-63dc-4780-9c45-ba85cbecf4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511046653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.511046653
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.3544393502
Short name T166
Test name
Test status
Simulation time 10365504677 ps
CPU time 155.93 seconds
Started Apr 30 01:54:28 PM PDT 24
Finished Apr 30 01:57:04 PM PDT 24
Peak memory 1097364 kb
Host smart-8979d695-8daa-4d58-b599-ba8a86533056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544393502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.3544393502
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.1810556214
Short name T1100
Test name
Test status
Simulation time 658964783 ps
CPU time 10.85 seconds
Started Apr 30 01:54:28 PM PDT 24
Finished Apr 30 01:54:39 PM PDT 24
Peak memory 220460 kb
Host smart-96b3175b-e973-4879-ad8d-2b70ce65dd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810556214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.1810556214
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.1895930702
Short name T402
Test name
Test status
Simulation time 2325042072 ps
CPU time 2.77 seconds
Started Apr 30 01:54:29 PM PDT 24
Finished Apr 30 01:54:32 PM PDT 24
Peak memory 204264 kb
Host smart-7039c3b8-f0b5-4566-af68-f3e17771d781
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895930702 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.1895930702
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.419800664
Short name T697
Test name
Test status
Simulation time 10686947082 ps
CPU time 5.61 seconds
Started Apr 30 01:54:26 PM PDT 24
Finished Apr 30 01:54:32 PM PDT 24
Peak memory 241756 kb
Host smart-5c44fe32-7d24-4538-8787-7fbcb3e6fc96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419800664 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_acq.419800664
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.70563755
Short name T986
Test name
Test status
Simulation time 10150322978 ps
CPU time 83.98 seconds
Started Apr 30 01:54:38 PM PDT 24
Finished Apr 30 01:56:03 PM PDT 24
Peak memory 479444 kb
Host smart-0b99fb2f-c099-4574-9b47-9f32776cb3fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70563755 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 19.i2c_target_fifo_reset_tx.70563755
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.3067551135
Short name T1097
Test name
Test status
Simulation time 618350194 ps
CPU time 3.32 seconds
Started Apr 30 01:54:33 PM PDT 24
Finished Apr 30 01:54:37 PM PDT 24
Peak memory 204112 kb
Host smart-73743b38-543d-4973-abc5-3a401d026e27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067551135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.3067551135
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.2413149554
Short name T459
Test name
Test status
Simulation time 1304102810 ps
CPU time 3.55 seconds
Started Apr 30 01:54:38 PM PDT 24
Finished Apr 30 01:54:43 PM PDT 24
Peak memory 205644 kb
Host smart-162c5e64-b03a-4594-8c42-3d8138a0e3f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413149554 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.2413149554
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.795108568
Short name T655
Test name
Test status
Simulation time 22509409082 ps
CPU time 185.31 seconds
Started Apr 30 01:54:29 PM PDT 24
Finished Apr 30 01:57:35 PM PDT 24
Peak memory 1934360 kb
Host smart-b03248d8-595c-410d-b19b-5cbb6f8de242
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795108568 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.795108568
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.4223010723
Short name T1156
Test name
Test status
Simulation time 829395752 ps
CPU time 30.28 seconds
Started Apr 30 01:54:29 PM PDT 24
Finished Apr 30 01:54:59 PM PDT 24
Peak memory 204152 kb
Host smart-148671b1-50df-4c50-9495-cbac05177c77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223010723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.4223010723
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.2573874405
Short name T902
Test name
Test status
Simulation time 682550692 ps
CPU time 13.36 seconds
Started Apr 30 01:54:29 PM PDT 24
Finished Apr 30 01:54:43 PM PDT 24
Peak memory 207692 kb
Host smart-d659fb58-dccb-4a65-a132-57a6d973c969
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573874405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.2573874405
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2044177026
Short name T1309
Test name
Test status
Simulation time 10110525279 ps
CPU time 21.64 seconds
Started Apr 30 01:54:30 PM PDT 24
Finished Apr 30 01:54:52 PM PDT 24
Peak memory 204204 kb
Host smart-33472f84-e79c-4453-87f1-c84ad8e62f85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044177026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2044177026
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.3031179852
Short name T721
Test name
Test status
Simulation time 8632453618 ps
CPU time 7.66 seconds
Started Apr 30 01:54:29 PM PDT 24
Finished Apr 30 01:54:37 PM PDT 24
Peak memory 218612 kb
Host smart-5851aef9-cf34-40ee-b522-7cefb62f9b6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031179852 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.3031179852
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.688054185
Short name T1081
Test name
Test status
Simulation time 34409820 ps
CPU time 0.61 seconds
Started Apr 30 01:52:36 PM PDT 24
Finished Apr 30 01:52:37 PM PDT 24
Peak memory 203860 kb
Host smart-08e1a00b-71e8-425b-bfd1-9d87e04119ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688054185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.688054185
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.3719611826
Short name T780
Test name
Test status
Simulation time 383903845 ps
CPU time 1.37 seconds
Started Apr 30 01:52:42 PM PDT 24
Finished Apr 30 01:52:44 PM PDT 24
Peak memory 212488 kb
Host smart-e1f3497f-c2fb-4640-b470-c9ba52c52f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719611826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.3719611826
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1221396716
Short name T893
Test name
Test status
Simulation time 345285923 ps
CPU time 6.44 seconds
Started Apr 30 01:52:47 PM PDT 24
Finished Apr 30 01:52:54 PM PDT 24
Peak memory 276344 kb
Host smart-cbc99a18-bc43-4d52-845f-e8f788c45133
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221396716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1221396716
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.3996250574
Short name T83
Test name
Test status
Simulation time 8990483900 ps
CPU time 71.34 seconds
Started Apr 30 01:52:48 PM PDT 24
Finished Apr 30 01:54:00 PM PDT 24
Peak memory 740960 kb
Host smart-ac5b4372-14cd-4c2f-801f-1b4f888f0d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996250574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.3996250574
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.1319871058
Short name T1194
Test name
Test status
Simulation time 1213788494 ps
CPU time 29.93 seconds
Started Apr 30 01:52:43 PM PDT 24
Finished Apr 30 01:53:13 PM PDT 24
Peak memory 470468 kb
Host smart-31493e40-5fb7-459d-8f18-d0bcef240815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319871058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.1319871058
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.3927996252
Short name T816
Test name
Test status
Simulation time 161244645 ps
CPU time 0.83 seconds
Started Apr 30 01:52:37 PM PDT 24
Finished Apr 30 01:52:38 PM PDT 24
Peak memory 203952 kb
Host smart-e8e3647f-f92a-48d5-98f5-2f10ea8af429
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927996252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.3927996252
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.2134512766
Short name T113
Test name
Test status
Simulation time 445610681 ps
CPU time 6.43 seconds
Started Apr 30 01:52:41 PM PDT 24
Finished Apr 30 01:52:48 PM PDT 24
Peak memory 204156 kb
Host smart-5b084c5d-9501-43dd-8ea7-c4fb8c95af01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134512766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
2134512766
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.4044986647
Short name T162
Test name
Test status
Simulation time 4450120423 ps
CPU time 126.43 seconds
Started Apr 30 01:52:33 PM PDT 24
Finished Apr 30 01:54:40 PM PDT 24
Peak memory 1276476 kb
Host smart-895ed506-d227-413a-9fe2-6a48781e52b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044986647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.4044986647
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.2937261664
Short name T447
Test name
Test status
Simulation time 594141469 ps
CPU time 7.4 seconds
Started Apr 30 01:52:46 PM PDT 24
Finished Apr 30 01:52:54 PM PDT 24
Peak memory 204100 kb
Host smart-d9773a25-c71a-48b9-896f-8b0e1e3a4b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937261664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.2937261664
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.1618479648
Short name T215
Test name
Test status
Simulation time 1373602764 ps
CPU time 66.6 seconds
Started Apr 30 01:52:38 PM PDT 24
Finished Apr 30 01:53:46 PM PDT 24
Peak memory 305652 kb
Host smart-68045a07-139b-4818-8802-4bcaa7aa004c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618479648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.1618479648
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.1418177593
Short name T868
Test name
Test status
Simulation time 26842754 ps
CPU time 0.64 seconds
Started Apr 30 01:52:40 PM PDT 24
Finished Apr 30 01:52:41 PM PDT 24
Peak memory 203868 kb
Host smart-04bab906-45e8-4ecc-aa62-defeeddd178b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418177593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1418177593
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.2780217572
Short name T983
Test name
Test status
Simulation time 12307503899 ps
CPU time 126.68 seconds
Started Apr 30 01:52:37 PM PDT 24
Finished Apr 30 01:54:44 PM PDT 24
Peak memory 204208 kb
Host smart-ae4d141e-d657-49c4-b989-955b7421a5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780217572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.2780217572
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.3511710244
Short name T474
Test name
Test status
Simulation time 1575768909 ps
CPU time 34.6 seconds
Started Apr 30 01:52:31 PM PDT 24
Finished Apr 30 01:53:06 PM PDT 24
Peak memory 335480 kb
Host smart-feb85331-54e1-4b4f-ace9-337c50e220ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511710244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.3511710244
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.3706249258
Short name T168
Test name
Test status
Simulation time 8612412405 ps
CPU time 44.94 seconds
Started Apr 30 01:52:41 PM PDT 24
Finished Apr 30 01:53:26 PM PDT 24
Peak memory 349108 kb
Host smart-dbeced62-65ac-453c-8005-52943239b6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706249258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.3706249258
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.1360534581
Short name T716
Test name
Test status
Simulation time 427031685 ps
CPU time 7.53 seconds
Started Apr 30 01:52:44 PM PDT 24
Finished Apr 30 01:52:52 PM PDT 24
Peak memory 220592 kb
Host smart-72ce4a24-5e82-4a11-ab8e-86babb217b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360534581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.1360534581
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2205067031
Short name T108
Test name
Test status
Simulation time 327577886 ps
CPU time 0.93 seconds
Started Apr 30 01:52:45 PM PDT 24
Finished Apr 30 01:52:46 PM PDT 24
Peak memory 221432 kb
Host smart-6df07a8f-37d1-494c-9b1e-78dcecc173e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205067031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2205067031
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.3935734085
Short name T1195
Test name
Test status
Simulation time 3188355672 ps
CPU time 5.05 seconds
Started Apr 30 01:52:41 PM PDT 24
Finished Apr 30 01:52:46 PM PDT 24
Peak memory 214272 kb
Host smart-48960733-61b2-412f-ae11-856d7d325251
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935734085 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.3935734085
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.3962848751
Short name T359
Test name
Test status
Simulation time 10376918583 ps
CPU time 13.47 seconds
Started Apr 30 01:52:46 PM PDT 24
Finished Apr 30 01:53:00 PM PDT 24
Peak memory 240284 kb
Host smart-a81e652f-8a0e-4666-9241-cf55778cf630
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962848751 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.3962848751
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.1225970092
Short name T1359
Test name
Test status
Simulation time 10055222931 ps
CPU time 70.77 seconds
Started Apr 30 01:52:42 PM PDT 24
Finished Apr 30 01:53:53 PM PDT 24
Peak memory 489488 kb
Host smart-bc470258-db19-41ba-b948-a402f5998979
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225970092 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.1225970092
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.87982417
Short name T809
Test name
Test status
Simulation time 432551672 ps
CPU time 2.6 seconds
Started Apr 30 01:52:50 PM PDT 24
Finished Apr 30 01:52:53 PM PDT 24
Peak memory 204192 kb
Host smart-a37516b7-2457-431a-b857-705ccbab5cdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87982417 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.i2c_target_hrst.87982417
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2116604339
Short name T306
Test name
Test status
Simulation time 3135685512 ps
CPU time 4.2 seconds
Started Apr 30 01:52:46 PM PDT 24
Finished Apr 30 01:52:51 PM PDT 24
Peak memory 204272 kb
Host smart-b08e3b76-f23b-423b-a048-d88de2a0f400
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116604339 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2116604339
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.4213379701
Short name T1202
Test name
Test status
Simulation time 11317410179 ps
CPU time 12.52 seconds
Started Apr 30 01:52:52 PM PDT 24
Finished Apr 30 01:53:05 PM PDT 24
Peak memory 334688 kb
Host smart-6f44cf45-de50-4982-8739-783d57026fb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213379701 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.4213379701
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.3611278175
Short name T499
Test name
Test status
Simulation time 1148712338 ps
CPU time 46.4 seconds
Started Apr 30 01:52:51 PM PDT 24
Finished Apr 30 01:53:38 PM PDT 24
Peak memory 204184 kb
Host smart-5a28f40b-7549-4984-8d35-9373cb1c7723
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611278175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.3611278175
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1122684910
Short name T607
Test name
Test status
Simulation time 633355500 ps
CPU time 26.08 seconds
Started Apr 30 01:52:47 PM PDT 24
Finished Apr 30 01:53:14 PM PDT 24
Peak memory 204128 kb
Host smart-051906c0-63cb-47e9-882d-48734cbcfbfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122684910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1122684910
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.1421693636
Short name T1130
Test name
Test status
Simulation time 36599010861 ps
CPU time 446.82 seconds
Started Apr 30 01:52:51 PM PDT 24
Finished Apr 30 02:00:19 PM PDT 24
Peak memory 4045828 kb
Host smart-5d11ea8b-148d-4737-b13f-2da285d4a512
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421693636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.1421693636
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.3416238612
Short name T979
Test name
Test status
Simulation time 30642823462 ps
CPU time 212.87 seconds
Started Apr 30 01:52:47 PM PDT 24
Finished Apr 30 01:56:20 PM PDT 24
Peak memory 1783160 kb
Host smart-12f5e18e-c0b1-46ef-9c32-36884c2ec436
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416238612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.3416238612
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.284172159
Short name T197
Test name
Test status
Simulation time 2533674346 ps
CPU time 6.06 seconds
Started Apr 30 01:52:41 PM PDT 24
Finished Apr 30 01:52:47 PM PDT 24
Peak memory 212404 kb
Host smart-43566e43-bac1-41f7-acb4-9381ef4690c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284172159 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_timeout.284172159
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.135504431
Short name T355
Test name
Test status
Simulation time 25181175 ps
CPU time 0.62 seconds
Started Apr 30 01:54:35 PM PDT 24
Finished Apr 30 01:54:36 PM PDT 24
Peak memory 203888 kb
Host smart-6277d2b4-601f-4158-8fba-c1d25ef5c006
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135504431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.135504431
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.3755746025
Short name T718
Test name
Test status
Simulation time 1086400859 ps
CPU time 1.38 seconds
Started Apr 30 01:54:34 PM PDT 24
Finished Apr 30 01:54:36 PM PDT 24
Peak memory 212464 kb
Host smart-77ca530c-3d9d-4617-8d2d-50123ad8ab8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755746025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3755746025
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.1880029655
Short name T1050
Test name
Test status
Simulation time 1552716101 ps
CPU time 8.26 seconds
Started Apr 30 01:54:28 PM PDT 24
Finished Apr 30 01:54:37 PM PDT 24
Peak memory 296120 kb
Host smart-1ce427b6-94f1-48b0-a2a1-263ea1cba148
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880029655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.1880029655
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.400511446
Short name T365
Test name
Test status
Simulation time 7483716412 ps
CPU time 92.49 seconds
Started Apr 30 01:54:30 PM PDT 24
Finished Apr 30 01:56:02 PM PDT 24
Peak memory 507208 kb
Host smart-67855783-b928-4e26-8234-d6141e462c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400511446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.400511446
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.3782182114
Short name T604
Test name
Test status
Simulation time 3540878171 ps
CPU time 127.2 seconds
Started Apr 30 01:54:30 PM PDT 24
Finished Apr 30 01:56:38 PM PDT 24
Peak memory 618580 kb
Host smart-7cf87711-ce49-48ec-82f1-7909d86212eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782182114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3782182114
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.1792584411
Short name T713
Test name
Test status
Simulation time 480326062 ps
CPU time 1.16 seconds
Started Apr 30 01:54:38 PM PDT 24
Finished Apr 30 01:54:40 PM PDT 24
Peak memory 204136 kb
Host smart-7cbeb091-1b66-474e-bffb-2a54506e3b75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792584411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.1792584411
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.2434279600
Short name T832
Test name
Test status
Simulation time 462078002 ps
CPU time 2.84 seconds
Started Apr 30 01:54:29 PM PDT 24
Finished Apr 30 01:54:32 PM PDT 24
Peak memory 220956 kb
Host smart-32f182a9-877c-42aa-aced-21fcbeaf9e21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434279600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.2434279600
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.812844766
Short name T941
Test name
Test status
Simulation time 4157161262 ps
CPU time 103.3 seconds
Started Apr 30 01:54:27 PM PDT 24
Finished Apr 30 01:56:11 PM PDT 24
Peak memory 1197204 kb
Host smart-a7c722c7-ccfa-484e-a230-e6b3a74e4d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812844766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.812844766
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.918760698
Short name T987
Test name
Test status
Simulation time 1455714822 ps
CPU time 13.14 seconds
Started Apr 30 01:54:35 PM PDT 24
Finished Apr 30 01:54:48 PM PDT 24
Peak memory 204232 kb
Host smart-0edda49b-7324-4493-91f0-59ef3fce9bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918760698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.918760698
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.3061495326
Short name T1115
Test name
Test status
Simulation time 3056204628 ps
CPU time 21.63 seconds
Started Apr 30 01:54:35 PM PDT 24
Finished Apr 30 01:54:57 PM PDT 24
Peak memory 312932 kb
Host smart-6396e550-08a9-4309-ae88-49f70fd7ba4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061495326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3061495326
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.3970530742
Short name T470
Test name
Test status
Simulation time 17298530 ps
CPU time 0.64 seconds
Started Apr 30 01:54:28 PM PDT 24
Finished Apr 30 01:54:29 PM PDT 24
Peak memory 203860 kb
Host smart-c673a0a6-0c59-48b1-b24e-42c3832e8bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970530742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.3970530742
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.1015914558
Short name T76
Test name
Test status
Simulation time 31541048223 ps
CPU time 22.64 seconds
Started Apr 30 01:54:38 PM PDT 24
Finished Apr 30 01:55:02 PM PDT 24
Peak memory 204224 kb
Host smart-8ba2f4e1-5b46-41a3-a1a5-1ae78b2d6783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015914558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.1015914558
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.2966276234
Short name T800
Test name
Test status
Simulation time 954752734 ps
CPU time 45.29 seconds
Started Apr 30 01:54:30 PM PDT 24
Finished Apr 30 01:55:16 PM PDT 24
Peak memory 282644 kb
Host smart-e66cc27f-bebb-4959-ac1c-b222ef04dfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966276234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.2966276234
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.3209840391
Short name T169
Test name
Test status
Simulation time 3186992979 ps
CPU time 89.43 seconds
Started Apr 30 01:54:34 PM PDT 24
Finished Apr 30 01:56:04 PM PDT 24
Peak memory 568124 kb
Host smart-d5e1f0af-c8d6-49cb-92e0-8584285079d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209840391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.3209840391
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.2175404504
Short name T243
Test name
Test status
Simulation time 956301828 ps
CPU time 21.28 seconds
Started Apr 30 01:54:33 PM PDT 24
Finished Apr 30 01:54:55 PM PDT 24
Peak memory 212404 kb
Host smart-a485c531-66be-4d65-a125-59d2b6943be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175404504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.2175404504
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.2922195071
Short name T1169
Test name
Test status
Simulation time 5583887010 ps
CPU time 5.37 seconds
Started Apr 30 01:54:33 PM PDT 24
Finished Apr 30 01:54:38 PM PDT 24
Peak memory 213624 kb
Host smart-e8a0dd7b-937d-4917-a30f-e7ab339f6af6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922195071 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.2922195071
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.764277075
Short name T741
Test name
Test status
Simulation time 10378976394 ps
CPU time 17.34 seconds
Started Apr 30 01:54:33 PM PDT 24
Finished Apr 30 01:54:51 PM PDT 24
Peak memory 295708 kb
Host smart-1d48b2f1-a15b-496b-a3f4-6e01cdaf7aca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764277075 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_fifo_reset_tx.764277075
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.3355623624
Short name T479
Test name
Test status
Simulation time 473077030 ps
CPU time 2.96 seconds
Started Apr 30 01:54:34 PM PDT 24
Finished Apr 30 01:54:38 PM PDT 24
Peak memory 204144 kb
Host smart-e30a4ec4-4092-4513-b3c6-03ee700bb0d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355623624 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.3355623624
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.2401770155
Short name T629
Test name
Test status
Simulation time 10599888360 ps
CPU time 3.1 seconds
Started Apr 30 01:54:41 PM PDT 24
Finished Apr 30 01:54:45 PM PDT 24
Peak memory 204164 kb
Host smart-32efd33e-08e2-4c3f-ab6a-e0bf5c343535
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401770155 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.2401770155
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.4290228789
Short name T364
Test name
Test status
Simulation time 5641524251 ps
CPU time 4.09 seconds
Started Apr 30 01:54:39 PM PDT 24
Finished Apr 30 01:54:44 PM PDT 24
Peak memory 204452 kb
Host smart-279d25fb-5da6-438f-a689-16fae55e4906
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290228789 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.4290228789
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.532726455
Short name T1048
Test name
Test status
Simulation time 662638639 ps
CPU time 23.21 seconds
Started Apr 30 01:54:34 PM PDT 24
Finished Apr 30 01:54:57 PM PDT 24
Peak memory 204060 kb
Host smart-26980608-a90d-4b04-abf5-22d47915ebaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532726455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_tar
get_smoke.532726455
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.3903044907
Short name T1357
Test name
Test status
Simulation time 758073347 ps
CPU time 10.92 seconds
Started Apr 30 01:54:33 PM PDT 24
Finished Apr 30 01:54:45 PM PDT 24
Peak memory 215436 kb
Host smart-1c542d3c-a86c-4d3e-97d0-4c29b4d97315
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903044907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.3903044907
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.3430415303
Short name T1053
Test name
Test status
Simulation time 40263347671 ps
CPU time 39.88 seconds
Started Apr 30 01:54:34 PM PDT 24
Finished Apr 30 01:55:15 PM PDT 24
Peak memory 861832 kb
Host smart-a9bf8894-876b-47c9-8ab6-11cfc3d56b48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430415303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.3430415303
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.2484445745
Short name T1230
Test name
Test status
Simulation time 15823151345 ps
CPU time 27.16 seconds
Started Apr 30 01:54:34 PM PDT 24
Finished Apr 30 01:55:01 PM PDT 24
Peak memory 387844 kb
Host smart-fba3bd79-7e82-4f34-800f-cdbe3f5f85d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484445745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.2484445745
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.1925128910
Short name T915
Test name
Test status
Simulation time 1413507576 ps
CPU time 7.3 seconds
Started Apr 30 01:54:34 PM PDT 24
Finished Apr 30 01:54:42 PM PDT 24
Peak memory 215700 kb
Host smart-f38913e1-dd1a-44bb-b520-baedc7c8306d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925128910 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.1925128910
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_unexp_stop.100607800
Short name T18
Test name
Test status
Simulation time 5950721760 ps
CPU time 5.55 seconds
Started Apr 30 01:54:33 PM PDT 24
Finished Apr 30 01:54:39 PM PDT 24
Peak memory 204180 kb
Host smart-3073ed43-ed89-49c1-a4f7-981706fd705f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100607800 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_unexp_stop.100607800
Directory /workspace/20.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/21.i2c_alert_test.3903924525
Short name T296
Test name
Test status
Simulation time 41922160 ps
CPU time 0.62 seconds
Started Apr 30 01:54:46 PM PDT 24
Finished Apr 30 01:54:47 PM PDT 24
Peak memory 203868 kb
Host smart-11d3dea1-167f-4150-b4e1-d21e9b3740b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903924525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3903924525
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.129318679
Short name T1168
Test name
Test status
Simulation time 111331664 ps
CPU time 1.58 seconds
Started Apr 30 01:54:40 PM PDT 24
Finished Apr 30 01:54:42 PM PDT 24
Peak memory 212368 kb
Host smart-375d4ae9-842c-4a37-87f6-273de28f69c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129318679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.129318679
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.3775966427
Short name T913
Test name
Test status
Simulation time 153904927 ps
CPU time 8.09 seconds
Started Apr 30 01:54:41 PM PDT 24
Finished Apr 30 01:54:50 PM PDT 24
Peak memory 228376 kb
Host smart-553590fc-0497-479b-a2e0-6a6be52c0aab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775966427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.3775966427
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.186442378
Short name T408
Test name
Test status
Simulation time 1793027204 ps
CPU time 99.33 seconds
Started Apr 30 01:54:38 PM PDT 24
Finished Apr 30 01:56:19 PM PDT 24
Peak memory 492568 kb
Host smart-ef95c10a-9c46-471b-932a-1eb2a28b9410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186442378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.186442378
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.1893440532
Short name T385
Test name
Test status
Simulation time 2162611427 ps
CPU time 72.72 seconds
Started Apr 30 01:54:38 PM PDT 24
Finished Apr 30 01:55:51 PM PDT 24
Peak memory 721012 kb
Host smart-17babd82-3810-4c69-a148-4e51adde06fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893440532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.1893440532
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.3343513359
Short name T722
Test name
Test status
Simulation time 527094756 ps
CPU time 1.14 seconds
Started Apr 30 01:54:47 PM PDT 24
Finished Apr 30 01:54:48 PM PDT 24
Peak memory 204080 kb
Host smart-d7e85fed-8a01-434d-b27e-a82d3d37e23e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343513359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.3343513359
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.15990879
Short name T950
Test name
Test status
Simulation time 99965969 ps
CPU time 2.44 seconds
Started Apr 30 01:54:39 PM PDT 24
Finished Apr 30 01:54:42 PM PDT 24
Peak memory 204220 kb
Host smart-a4fb2360-4a2e-4bfd-b9d5-062be564f738
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15990879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.15990879
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2397120288
Short name T668
Test name
Test status
Simulation time 3426502574 ps
CPU time 92.67 seconds
Started Apr 30 01:54:40 PM PDT 24
Finished Apr 30 01:56:13 PM PDT 24
Peak memory 957180 kb
Host smart-7cb44289-96d8-4ad8-832e-485c79c4a584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397120288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2397120288
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.3143643318
Short name T825
Test name
Test status
Simulation time 2079501998 ps
CPU time 7.64 seconds
Started Apr 30 01:54:46 PM PDT 24
Finished Apr 30 01:54:53 PM PDT 24
Peak memory 204180 kb
Host smart-2768bdf1-fabc-4ac2-a4ff-d30f8a667872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143643318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.3143643318
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.2943483903
Short name T40
Test name
Test status
Simulation time 3396567807 ps
CPU time 77.24 seconds
Started Apr 30 01:54:48 PM PDT 24
Finished Apr 30 01:56:05 PM PDT 24
Peak memory 363796 kb
Host smart-77948a4c-9773-4883-b6fe-b5f23f90cafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943483903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.2943483903
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.2113747502
Short name T191
Test name
Test status
Simulation time 18134285 ps
CPU time 0.63 seconds
Started Apr 30 01:54:39 PM PDT 24
Finished Apr 30 01:54:40 PM PDT 24
Peak memory 203852 kb
Host smart-f5085958-a601-47df-af4f-f816195034b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113747502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.2113747502
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.730853302
Short name T715
Test name
Test status
Simulation time 5474248860 ps
CPU time 73.99 seconds
Started Apr 30 01:54:41 PM PDT 24
Finished Apr 30 01:55:56 PM PDT 24
Peak memory 245132 kb
Host smart-1d3c4a32-7cd5-4eab-826a-555907d4b225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730853302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.730853302
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.1494792522
Short name T1034
Test name
Test status
Simulation time 4414550309 ps
CPU time 56.21 seconds
Started Apr 30 01:54:42 PM PDT 24
Finished Apr 30 01:55:38 PM PDT 24
Peak memory 351656 kb
Host smart-81f952b6-1c97-4822-a809-2bf4eac3ade1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494792522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.1494792522
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.286349977
Short name T1155
Test name
Test status
Simulation time 2986906090 ps
CPU time 34.39 seconds
Started Apr 30 01:54:38 PM PDT 24
Finished Apr 30 01:55:13 PM PDT 24
Peak memory 212528 kb
Host smart-18369997-150f-4b76-9218-86d9e107b5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286349977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.286349977
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.3261549795
Short name T991
Test name
Test status
Simulation time 1165586594 ps
CPU time 5.18 seconds
Started Apr 30 01:54:42 PM PDT 24
Finished Apr 30 01:54:48 PM PDT 24
Peak memory 214640 kb
Host smart-e7e1854b-f614-474f-a91a-d8835c147d61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261549795 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.3261549795
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1447724885
Short name T690
Test name
Test status
Simulation time 10077627400 ps
CPU time 14.24 seconds
Started Apr 30 01:54:39 PM PDT 24
Finished Apr 30 01:54:54 PM PDT 24
Peak memory 283116 kb
Host smart-bbd48245-39e6-4b4a-a5c8-cb4aedea5e70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447724885 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.1447724885
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.1844114159
Short name T865
Test name
Test status
Simulation time 11127092969 ps
CPU time 6.01 seconds
Started Apr 30 01:54:40 PM PDT 24
Finished Apr 30 01:54:46 PM PDT 24
Peak memory 227564 kb
Host smart-1cb2d5d7-3d67-4e3b-98b8-6c4ee823ec20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844114159 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.1844114159
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.3859880645
Short name T1060
Test name
Test status
Simulation time 481563269 ps
CPU time 2.68 seconds
Started Apr 30 01:54:46 PM PDT 24
Finished Apr 30 01:54:49 PM PDT 24
Peak memory 204212 kb
Host smart-5b60e9a0-631d-4a27-98b6-cae6a0dd9268
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859880645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.3859880645
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.3654582525
Short name T1018
Test name
Test status
Simulation time 2316680788 ps
CPU time 3.39 seconds
Started Apr 30 01:54:40 PM PDT 24
Finished Apr 30 01:54:44 PM PDT 24
Peak memory 204252 kb
Host smart-6b788d59-f670-4882-9882-185963ed8801
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654582525 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.3654582525
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.2412063947
Short name T373
Test name
Test status
Simulation time 23703958082 ps
CPU time 660.42 seconds
Started Apr 30 01:54:39 PM PDT 24
Finished Apr 30 02:05:40 PM PDT 24
Peak memory 5754984 kb
Host smart-b04cebb6-93f4-49cc-bb51-d90e4597efba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412063947 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.2412063947
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.3190271465
Short name T1153
Test name
Test status
Simulation time 843480729 ps
CPU time 10.41 seconds
Started Apr 30 01:54:40 PM PDT 24
Finished Apr 30 01:54:51 PM PDT 24
Peak memory 204060 kb
Host smart-cd5f6b3f-34ec-49df-92b8-4f7ef3bd934c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190271465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.3190271465
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.4170258313
Short name T556
Test name
Test status
Simulation time 338222473 ps
CPU time 13.86 seconds
Started Apr 30 01:54:39 PM PDT 24
Finished Apr 30 01:54:54 PM PDT 24
Peak memory 204120 kb
Host smart-3dcd74e1-02dd-44e0-9a0f-909ae62a70f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170258313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.4170258313
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.2669549584
Short name T910
Test name
Test status
Simulation time 47345355753 ps
CPU time 996.31 seconds
Started Apr 30 01:54:39 PM PDT 24
Finished Apr 30 02:11:16 PM PDT 24
Peak memory 6675180 kb
Host smart-e179a551-1871-4f5e-bf4b-abc337857238
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669549584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.2669549584
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.450521161
Short name T1338
Test name
Test status
Simulation time 3751387086 ps
CPU time 32.5 seconds
Started Apr 30 01:54:41 PM PDT 24
Finished Apr 30 01:55:14 PM PDT 24
Peak memory 534896 kb
Host smart-dd50ba99-add0-45f0-a70c-9d9bbc9390fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450521161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_t
arget_stretch.450521161
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.753175631
Short name T620
Test name
Test status
Simulation time 1331180944 ps
CPU time 6.61 seconds
Started Apr 30 01:54:38 PM PDT 24
Finished Apr 30 01:54:45 PM PDT 24
Peak memory 212412 kb
Host smart-c9c689b8-5cb9-4692-a3b1-c017c0dad8da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753175631 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_timeout.753175631
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.3768053064
Short name T869
Test name
Test status
Simulation time 40697315 ps
CPU time 0.63 seconds
Started Apr 30 01:54:50 PM PDT 24
Finished Apr 30 01:54:51 PM PDT 24
Peak memory 203824 kb
Host smart-2184dbba-9f2d-41b2-bf62-f8486ae7b449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768053064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3768053064
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.800762005
Short name T1010
Test name
Test status
Simulation time 75131153 ps
CPU time 1.21 seconds
Started Apr 30 01:54:48 PM PDT 24
Finished Apr 30 01:54:49 PM PDT 24
Peak memory 212460 kb
Host smart-bfbc6a9d-2758-4db6-abde-ede54b106277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800762005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.800762005
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1027158626
Short name T593
Test name
Test status
Simulation time 1107676681 ps
CPU time 5.77 seconds
Started Apr 30 01:54:49 PM PDT 24
Finished Apr 30 01:54:55 PM PDT 24
Peak memory 256092 kb
Host smart-6a35ee2c-0638-4b8a-be50-09be8624d817
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027158626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1027158626
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.732273776
Short name T1185
Test name
Test status
Simulation time 3477284322 ps
CPU time 51.58 seconds
Started Apr 30 01:54:44 PM PDT 24
Finished Apr 30 01:55:36 PM PDT 24
Peak memory 595324 kb
Host smart-d7c48a76-b625-48b2-b773-47506f741f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732273776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.732273776
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.3061903784
Short name T1080
Test name
Test status
Simulation time 9475553207 ps
CPU time 61.03 seconds
Started Apr 30 01:54:46 PM PDT 24
Finished Apr 30 01:55:48 PM PDT 24
Peak memory 690216 kb
Host smart-17b9c283-b1d1-4388-94c8-d51f137bbb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061903784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.3061903784
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.4267314544
Short name T213
Test name
Test status
Simulation time 111867135 ps
CPU time 0.95 seconds
Started Apr 30 01:54:46 PM PDT 24
Finished Apr 30 01:54:47 PM PDT 24
Peak memory 203916 kb
Host smart-b17eff1e-e6d1-4de3-8ec8-ad8ee3d0c22a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267314544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.4267314544
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.1271984724
Short name T976
Test name
Test status
Simulation time 1107236358 ps
CPU time 2.6 seconds
Started Apr 30 01:54:46 PM PDT 24
Finished Apr 30 01:54:49 PM PDT 24
Peak memory 204136 kb
Host smart-90c3ddc5-a93d-43b5-ad7e-e2f1f6c3f817
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271984724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.1271984724
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.3408781252
Short name T248
Test name
Test status
Simulation time 16497259949 ps
CPU time 315.91 seconds
Started Apr 30 01:54:45 PM PDT 24
Finished Apr 30 02:00:01 PM PDT 24
Peak memory 1232180 kb
Host smart-696fa709-dcde-4c17-9235-60ab49c9ee0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408781252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.3408781252
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.2732174735
Short name T600
Test name
Test status
Simulation time 498310423 ps
CPU time 6.11 seconds
Started Apr 30 01:54:50 PM PDT 24
Finished Apr 30 01:54:57 PM PDT 24
Peak memory 204176 kb
Host smart-51fef7dd-96a8-418f-a523-238ae5f497ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732174735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.2732174735
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.2301494937
Short name T777
Test name
Test status
Simulation time 2782952952 ps
CPU time 22.72 seconds
Started Apr 30 01:54:49 PM PDT 24
Finished Apr 30 01:55:12 PM PDT 24
Peak memory 308088 kb
Host smart-abfd2163-5633-4855-a949-bfa15dad1dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301494937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.2301494937
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.913082623
Short name T1025
Test name
Test status
Simulation time 46676736 ps
CPU time 0.68 seconds
Started Apr 30 01:54:44 PM PDT 24
Finished Apr 30 01:54:45 PM PDT 24
Peak memory 203828 kb
Host smart-8f9f7e54-1699-484c-8cb0-6e7c99bf23ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913082623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.913082623
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.656358889
Short name T522
Test name
Test status
Simulation time 4676794780 ps
CPU time 13.42 seconds
Started Apr 30 01:54:48 PM PDT 24
Finished Apr 30 01:55:02 PM PDT 24
Peak memory 235404 kb
Host smart-8c219ce4-322e-4d48-ad9b-8e59ac7778a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656358889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.656358889
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.2475947496
Short name T897
Test name
Test status
Simulation time 9598757395 ps
CPU time 26.79 seconds
Started Apr 30 01:54:45 PM PDT 24
Finished Apr 30 01:55:12 PM PDT 24
Peak memory 295220 kb
Host smart-965381ae-3a7e-4568-8ed6-aa14f5b4859a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475947496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.2475947496
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.438438500
Short name T703
Test name
Test status
Simulation time 4511485704 ps
CPU time 194.7 seconds
Started Apr 30 01:54:48 PM PDT 24
Finished Apr 30 01:58:03 PM PDT 24
Peak memory 1128172 kb
Host smart-ec0082c0-fca7-4baa-bf65-ece7886ec31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438438500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.438438500
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.3783039118
Short name T182
Test name
Test status
Simulation time 765083515 ps
CPU time 15.24 seconds
Started Apr 30 01:54:48 PM PDT 24
Finished Apr 30 01:55:03 PM PDT 24
Peak memory 219160 kb
Host smart-9fdf8244-b673-4bce-9686-e38b20555e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783039118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.3783039118
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.412396393
Short name T350
Test name
Test status
Simulation time 3730644363 ps
CPU time 4.43 seconds
Started Apr 30 01:54:52 PM PDT 24
Finished Apr 30 01:54:57 PM PDT 24
Peak memory 204252 kb
Host smart-9693db9e-dfd0-4e1a-a570-3f02dc19688e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412396393 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.412396393
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.3967140553
Short name T758
Test name
Test status
Simulation time 10070118420 ps
CPU time 80.91 seconds
Started Apr 30 01:54:50 PM PDT 24
Finished Apr 30 01:56:12 PM PDT 24
Peak memory 572000 kb
Host smart-f7655cd5-59d6-48bb-9310-10a34d872b37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967140553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.3967140553
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.648125824
Short name T589
Test name
Test status
Simulation time 1108240348 ps
CPU time 3.14 seconds
Started Apr 30 01:54:54 PM PDT 24
Finished Apr 30 01:54:58 PM PDT 24
Peak memory 204184 kb
Host smart-676fe966-607b-4461-8be1-ff0878bfeeb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648125824 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_hrst.648125824
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.3818421164
Short name T774
Test name
Test status
Simulation time 1798519127 ps
CPU time 3.09 seconds
Started Apr 30 01:54:49 PM PDT 24
Finished Apr 30 01:54:52 PM PDT 24
Peak memory 204140 kb
Host smart-f5709840-d422-44ef-b894-b0fb8e5aaf6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818421164 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.3818421164
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.336093169
Short name T845
Test name
Test status
Simulation time 14227170195 ps
CPU time 52.48 seconds
Started Apr 30 01:54:45 PM PDT 24
Finished Apr 30 01:55:38 PM PDT 24
Peak memory 913344 kb
Host smart-6263b02a-1ccc-4f3f-b16e-35b75e5fb125
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336093169 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.336093169
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.1553626039
Short name T30
Test name
Test status
Simulation time 1394985492 ps
CPU time 21.68 seconds
Started Apr 30 01:54:46 PM PDT 24
Finished Apr 30 01:55:08 PM PDT 24
Peak memory 204208 kb
Host smart-c6cbb8e0-cc44-4ef0-8b08-a0542c24cbd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553626039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.1553626039
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.1269262573
Short name T1139
Test name
Test status
Simulation time 13366863053 ps
CPU time 25.96 seconds
Started Apr 30 01:54:49 PM PDT 24
Finished Apr 30 01:55:15 PM PDT 24
Peak memory 232660 kb
Host smart-69c6c8a5-8bb8-48a1-b5b9-632e74ec8234
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269262573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.1269262573
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.1367886530
Short name T1272
Test name
Test status
Simulation time 21032887400 ps
CPU time 20.66 seconds
Started Apr 30 01:54:45 PM PDT 24
Finished Apr 30 01:55:06 PM PDT 24
Peak memory 204176 kb
Host smart-d9930045-656d-4573-b2ca-d7f6be8a5b5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367886530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.1367886530
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.1315269705
Short name T960
Test name
Test status
Simulation time 16070094232 ps
CPU time 239.23 seconds
Started Apr 30 01:54:45 PM PDT 24
Finished Apr 30 01:58:44 PM PDT 24
Peak memory 954184 kb
Host smart-11f06916-e6b5-49e6-bb2f-d2e03bc2212d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315269705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.1315269705
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.1939861705
Short name T3
Test name
Test status
Simulation time 1645380420 ps
CPU time 7.71 seconds
Started Apr 30 01:54:47 PM PDT 24
Finished Apr 30 01:54:55 PM PDT 24
Peak memory 218800 kb
Host smart-fbdf5bcd-62a6-403e-91af-2b044c17a8d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939861705 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.1939861705
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.539584843
Short name T939
Test name
Test status
Simulation time 39958529 ps
CPU time 0.63 seconds
Started Apr 30 01:55:01 PM PDT 24
Finished Apr 30 01:55:02 PM PDT 24
Peak memory 203880 kb
Host smart-0ab56a6e-963b-4343-a752-f393afafb145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539584843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.539584843
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.2521087713
Short name T790
Test name
Test status
Simulation time 109278113 ps
CPU time 1.75 seconds
Started Apr 30 01:54:59 PM PDT 24
Finished Apr 30 01:55:02 PM PDT 24
Peak memory 212236 kb
Host smart-e8709f64-7852-4f9f-b168-15090c720b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521087713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2521087713
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.519340854
Short name T1348
Test name
Test status
Simulation time 3228849239 ps
CPU time 6.36 seconds
Started Apr 30 01:54:50 PM PDT 24
Finished Apr 30 01:54:57 PM PDT 24
Peak memory 272256 kb
Host smart-3fa8139c-8a89-48ab-b930-2c9a45fcd65b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519340854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empt
y.519340854
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.1209916405
Short name T719
Test name
Test status
Simulation time 30812424631 ps
CPU time 54.25 seconds
Started Apr 30 01:54:52 PM PDT 24
Finished Apr 30 01:55:47 PM PDT 24
Peak memory 485672 kb
Host smart-55c9e789-b770-4e87-82f0-9c7b53d3ced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209916405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1209916405
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.1152693221
Short name T1237
Test name
Test status
Simulation time 3040574946 ps
CPU time 44.64 seconds
Started Apr 30 01:54:49 PM PDT 24
Finished Apr 30 01:55:34 PM PDT 24
Peak memory 582852 kb
Host smart-b6659aec-cef7-4c30-8dce-068c906ffd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152693221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.1152693221
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3817844592
Short name T268
Test name
Test status
Simulation time 1641787751 ps
CPU time 1.06 seconds
Started Apr 30 01:54:52 PM PDT 24
Finished Apr 30 01:54:54 PM PDT 24
Peak memory 204180 kb
Host smart-3677ba6d-3fcb-4370-a3fd-3c4e115ed4d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817844592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.3817844592
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.560540381
Short name T1295
Test name
Test status
Simulation time 246995470 ps
CPU time 3.31 seconds
Started Apr 30 01:54:55 PM PDT 24
Finished Apr 30 01:54:59 PM PDT 24
Peak memory 223276 kb
Host smart-1dc60c20-9320-4594-8846-4c52b2d3e15c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560540381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.
560540381
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.1423703631
Short name T746
Test name
Test status
Simulation time 2228770939 ps
CPU time 142.41 seconds
Started Apr 30 01:54:54 PM PDT 24
Finished Apr 30 01:57:17 PM PDT 24
Peak memory 755192 kb
Host smart-e40c73ba-045d-47a7-9e59-a5af422388b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423703631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.1423703631
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.3961042588
Short name T1122
Test name
Test status
Simulation time 665375341 ps
CPU time 10.24 seconds
Started Apr 30 01:55:01 PM PDT 24
Finished Apr 30 01:55:12 PM PDT 24
Peak memory 204128 kb
Host smart-496cff49-88aa-4624-9942-1d00e5b01584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961042588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.3961042588
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.3478907103
Short name T633
Test name
Test status
Simulation time 3655204874 ps
CPU time 35.08 seconds
Started Apr 30 01:55:04 PM PDT 24
Finished Apr 30 01:55:40 PM PDT 24
Peak memory 298852 kb
Host smart-2b20ff67-f28e-42f2-96d5-0bfdb21e46f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478907103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.3478907103
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.3195155826
Short name T1131
Test name
Test status
Simulation time 15835273 ps
CPU time 0.64 seconds
Started Apr 30 01:54:51 PM PDT 24
Finished Apr 30 01:54:52 PM PDT 24
Peak memory 203824 kb
Host smart-fe1c7e47-26f4-4d70-8f15-94782d926dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195155826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.3195155826
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.3444947927
Short name T198
Test name
Test status
Simulation time 5124915196 ps
CPU time 57.01 seconds
Started Apr 30 01:54:57 PM PDT 24
Finished Apr 30 01:55:55 PM PDT 24
Peak memory 276804 kb
Host smart-8044ab21-b52f-419a-8b1e-3a491898f060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444947927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3444947927
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.1873790063
Short name T566
Test name
Test status
Simulation time 1227796017 ps
CPU time 22.61 seconds
Started Apr 30 01:54:49 PM PDT 24
Finished Apr 30 01:55:12 PM PDT 24
Peak memory 286136 kb
Host smart-27576933-6f82-44fc-b77b-31839fb88574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873790063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.1873790063
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.4130158865
Short name T843
Test name
Test status
Simulation time 7257809332 ps
CPU time 683.11 seconds
Started Apr 30 01:54:55 PM PDT 24
Finished Apr 30 02:06:19 PM PDT 24
Peak memory 1283228 kb
Host smart-a1e4eed0-742a-4277-8cce-0f9ab7a971e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130158865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.4130158865
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.2893207498
Short name T239
Test name
Test status
Simulation time 2404894259 ps
CPU time 11.88 seconds
Started Apr 30 01:54:55 PM PDT 24
Finished Apr 30 01:55:07 PM PDT 24
Peak memory 220644 kb
Host smart-e11beb64-05d8-409d-9157-e0b6c78cf643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893207498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.2893207498
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.3107006790
Short name T1326
Test name
Test status
Simulation time 1553851315 ps
CPU time 3.79 seconds
Started Apr 30 01:54:57 PM PDT 24
Finished Apr 30 01:55:01 PM PDT 24
Peak memory 204180 kb
Host smart-b2f095fa-a76d-416a-ae59-b06b30ec98b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107006790 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.3107006790
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.785854745
Short name T803
Test name
Test status
Simulation time 10048567925 ps
CPU time 71.02 seconds
Started Apr 30 01:54:58 PM PDT 24
Finished Apr 30 01:56:09 PM PDT 24
Peak memory 415628 kb
Host smart-ca08d07e-365b-4671-8b41-e6df0059ec8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785854745 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_acq.785854745
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.372165065
Short name T561
Test name
Test status
Simulation time 10304794955 ps
CPU time 14.33 seconds
Started Apr 30 01:54:55 PM PDT 24
Finished Apr 30 01:55:10 PM PDT 24
Peak memory 273468 kb
Host smart-934ca61d-7736-4b86-96b4-9a30424ab5b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372165065 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_fifo_reset_tx.372165065
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.712241743
Short name T1191
Test name
Test status
Simulation time 717426167 ps
CPU time 2.19 seconds
Started Apr 30 01:54:55 PM PDT 24
Finished Apr 30 01:54:58 PM PDT 24
Peak memory 204232 kb
Host smart-b0ec070c-1131-4da8-b31d-95c6361edc23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712241743 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.i2c_target_hrst.712241743
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.2175858724
Short name T740
Test name
Test status
Simulation time 910291012 ps
CPU time 4.09 seconds
Started Apr 30 01:54:56 PM PDT 24
Finished Apr 30 01:55:01 PM PDT 24
Peak memory 204152 kb
Host smart-abb51489-b919-4df7-bfe7-500a9714577d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175858724 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.2175858724
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.2024997005
Short name T588
Test name
Test status
Simulation time 19146040987 ps
CPU time 311.27 seconds
Started Apr 30 01:54:55 PM PDT 24
Finished Apr 30 02:00:07 PM PDT 24
Peak memory 3090536 kb
Host smart-f18637cc-34e1-4ec9-a63c-d3b0f04b40a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024997005 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.2024997005
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.1696489217
Short name T658
Test name
Test status
Simulation time 864086139 ps
CPU time 30.17 seconds
Started Apr 30 01:54:55 PM PDT 24
Finished Apr 30 01:55:26 PM PDT 24
Peak memory 204164 kb
Host smart-0976c9f0-cd95-4a50-a75b-6097b31d3346
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696489217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.1696489217
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2290069938
Short name T1178
Test name
Test status
Simulation time 10759748227 ps
CPU time 29.05 seconds
Started Apr 30 01:54:55 PM PDT 24
Finished Apr 30 01:55:24 PM PDT 24
Peak memory 225976 kb
Host smart-bd6ce314-9376-44b2-ae00-a2db323eafec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290069938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2290069938
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.2984176135
Short name T664
Test name
Test status
Simulation time 11475796556 ps
CPU time 7.25 seconds
Started Apr 30 01:54:55 PM PDT 24
Finished Apr 30 01:55:03 PM PDT 24
Peak memory 204212 kb
Host smart-4db9fb51-d043-4e8e-86d7-d2a2e88a6892
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984176135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.2984176135
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.2324028085
Short name T302
Test name
Test status
Simulation time 7819448366 ps
CPU time 390.21 seconds
Started Apr 30 01:54:58 PM PDT 24
Finished Apr 30 02:01:29 PM PDT 24
Peak memory 1291768 kb
Host smart-1e20ae7f-ce92-4131-820a-126eaef40d0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324028085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.2324028085
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.2067605391
Short name T848
Test name
Test status
Simulation time 1563419714 ps
CPU time 7.57 seconds
Started Apr 30 01:54:59 PM PDT 24
Finished Apr 30 01:55:07 PM PDT 24
Peak memory 212144 kb
Host smart-c1848373-5161-4140-9a20-5ebc10836fc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067605391 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.2067605391
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.3164613125
Short name T1284
Test name
Test status
Simulation time 35907044 ps
CPU time 0.67 seconds
Started Apr 30 01:55:08 PM PDT 24
Finished Apr 30 01:55:09 PM PDT 24
Peak memory 203920 kb
Host smart-01a0f769-9f3a-41af-b03b-47eb77d7d178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164613125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.3164613125
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.2294923411
Short name T201
Test name
Test status
Simulation time 227221605 ps
CPU time 1.26 seconds
Started Apr 30 01:55:03 PM PDT 24
Finished Apr 30 01:55:05 PM PDT 24
Peak memory 212356 kb
Host smart-9c86e7e2-902a-47ce-aba4-f233813954b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294923411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.2294923411
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3084177814
Short name T665
Test name
Test status
Simulation time 1324108933 ps
CPU time 6.54 seconds
Started Apr 30 01:55:01 PM PDT 24
Finished Apr 30 01:55:08 PM PDT 24
Peak memory 275908 kb
Host smart-4bf8ad40-7209-46cd-9c08-3306d686fbd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084177814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.3084177814
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.998736850
Short name T1199
Test name
Test status
Simulation time 2058945054 ps
CPU time 152.8 seconds
Started Apr 30 01:55:03 PM PDT 24
Finished Apr 30 01:57:36 PM PDT 24
Peak memory 662920 kb
Host smart-f7caa9ad-5db9-47af-a0fc-885523cf3772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998736850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.998736850
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.2671395672
Short name T784
Test name
Test status
Simulation time 2537676865 ps
CPU time 88.67 seconds
Started Apr 30 01:55:03 PM PDT 24
Finished Apr 30 01:56:32 PM PDT 24
Peak memory 511716 kb
Host smart-cfbf27ac-8974-4601-b47a-7faa27521a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671395672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.2671395672
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.745634117
Short name T4
Test name
Test status
Simulation time 114153941 ps
CPU time 0.95 seconds
Started Apr 30 01:55:03 PM PDT 24
Finished Apr 30 01:55:05 PM PDT 24
Peak memory 203976 kb
Host smart-efc5848f-3bc4-4020-ad88-b41c03aa352e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745634117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fm
t.745634117
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.331124175
Short name T1292
Test name
Test status
Simulation time 498663862 ps
CPU time 7.45 seconds
Started Apr 30 01:55:02 PM PDT 24
Finished Apr 30 01:55:10 PM PDT 24
Peak memory 224764 kb
Host smart-49049917-4500-49c3-942a-08da5e521685
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331124175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.
331124175
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1513103711
Short name T815
Test name
Test status
Simulation time 54933338622 ps
CPU time 134.68 seconds
Started Apr 30 01:55:01 PM PDT 24
Finished Apr 30 01:57:16 PM PDT 24
Peak memory 1245172 kb
Host smart-00c235a7-7a73-416c-9297-b15bd39ed99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513103711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1513103711
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.1769548343
Short name T1068
Test name
Test status
Simulation time 4520500374 ps
CPU time 11 seconds
Started Apr 30 01:55:06 PM PDT 24
Finished Apr 30 01:55:17 PM PDT 24
Peak memory 204164 kb
Host smart-f1027d9f-b717-4bd4-a323-24c12935e50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769548343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.1769548343
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.496240726
Short name T1310
Test name
Test status
Simulation time 1647626534 ps
CPU time 37.02 seconds
Started Apr 30 01:55:13 PM PDT 24
Finished Apr 30 01:55:50 PM PDT 24
Peak memory 415220 kb
Host smart-d2f0c1c3-f709-4a40-95a9-2371e7b5bd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496240726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.496240726
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.3308741947
Short name T638
Test name
Test status
Simulation time 27042711 ps
CPU time 0.72 seconds
Started Apr 30 01:55:02 PM PDT 24
Finished Apr 30 01:55:03 PM PDT 24
Peak memory 203840 kb
Host smart-0c6da779-82c2-4ec1-97a0-5cde58c62c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308741947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.3308741947
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.2791143316
Short name T1030
Test name
Test status
Simulation time 1157478147 ps
CPU time 53.87 seconds
Started Apr 30 01:55:01 PM PDT 24
Finished Apr 30 01:55:55 PM PDT 24
Peak memory 298176 kb
Host smart-f0466a4e-16e6-42af-8f27-645f3776921b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791143316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.2791143316
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.1865728143
Short name T442
Test name
Test status
Simulation time 13066147864 ps
CPU time 30.34 seconds
Started Apr 30 01:55:02 PM PDT 24
Finished Apr 30 01:55:33 PM PDT 24
Peak memory 213448 kb
Host smart-fd48fa6a-e95b-49a9-8180-0184f9399e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865728143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.1865728143
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.1644041179
Short name T27
Test name
Test status
Simulation time 1614990942 ps
CPU time 2.37 seconds
Started Apr 30 01:55:06 PM PDT 24
Finished Apr 30 01:55:09 PM PDT 24
Peak memory 204212 kb
Host smart-6abf38fe-251a-432f-b76c-a324c0c4e824
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644041179 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.1644041179
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.1927212918
Short name T1289
Test name
Test status
Simulation time 10054961609 ps
CPU time 61.47 seconds
Started Apr 30 01:55:08 PM PDT 24
Finished Apr 30 01:56:10 PM PDT 24
Peak memory 501832 kb
Host smart-fb80e2ad-58d9-4db5-b274-7254673eea8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927212918 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.1927212918
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.4088100863
Short name T1314
Test name
Test status
Simulation time 10643998491 ps
CPU time 6.45 seconds
Started Apr 30 01:55:07 PM PDT 24
Finished Apr 30 01:55:14 PM PDT 24
Peak memory 244696 kb
Host smart-7890ec25-f3d7-436b-8866-7f9b3bf9e9a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088100863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.4088100863
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.2187050186
Short name T981
Test name
Test status
Simulation time 454818127 ps
CPU time 2.71 seconds
Started Apr 30 01:55:11 PM PDT 24
Finished Apr 30 01:55:15 PM PDT 24
Peak memory 204196 kb
Host smart-e9c7ee79-4b6b-49e8-8ae0-9859489fb00b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187050186 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.2187050186
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.3655469694
Short name T1127
Test name
Test status
Simulation time 5353385264 ps
CPU time 6.36 seconds
Started Apr 30 01:55:03 PM PDT 24
Finished Apr 30 01:55:10 PM PDT 24
Peak memory 216268 kb
Host smart-69d980cc-8b10-44fe-92f0-ed265117425e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655469694 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.3655469694
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.210642846
Short name T1161
Test name
Test status
Simulation time 10062227095 ps
CPU time 5.28 seconds
Started Apr 30 01:55:04 PM PDT 24
Finished Apr 30 01:55:10 PM PDT 24
Peak memory 204292 kb
Host smart-c8dd421d-d67d-426d-91f1-c3e9b4b2ec0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210642846 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.210642846
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.3511819088
Short name T948
Test name
Test status
Simulation time 1391758612 ps
CPU time 27.47 seconds
Started Apr 30 01:55:03 PM PDT 24
Finished Apr 30 01:55:31 PM PDT 24
Peak memory 204140 kb
Host smart-b740b6c5-4fe4-4344-a3ac-8db301bd8ff7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511819088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.3511819088
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.4002312595
Short name T736
Test name
Test status
Simulation time 1582731907 ps
CPU time 46.44 seconds
Started Apr 30 01:55:02 PM PDT 24
Finished Apr 30 01:55:48 PM PDT 24
Peak memory 204924 kb
Host smart-8107696c-ade2-4c46-baf2-e26bff2b8e03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002312595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.4002312595
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.670585492
Short name T386
Test name
Test status
Simulation time 24270607918 ps
CPU time 77.96 seconds
Started Apr 30 01:55:04 PM PDT 24
Finished Apr 30 01:56:22 PM PDT 24
Peak memory 1107216 kb
Host smart-5be8e784-e273-421b-9ad3-41fbdb79111a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670585492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_wr.670585492
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.1537315389
Short name T1047
Test name
Test status
Simulation time 35607388125 ps
CPU time 762.19 seconds
Started Apr 30 01:55:04 PM PDT 24
Finished Apr 30 02:07:47 PM PDT 24
Peak memory 2100564 kb
Host smart-139ad423-fbe7-40df-b61e-830c7757807f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537315389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.1537315389
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.1503553821
Short name T762
Test name
Test status
Simulation time 5114606618 ps
CPU time 6.63 seconds
Started Apr 30 01:55:05 PM PDT 24
Finished Apr 30 01:55:13 PM PDT 24
Peak memory 219168 kb
Host smart-45e8bb3e-2c5c-47a3-9dd6-8578c4f81b8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503553821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.1503553821
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.3505548781
Short name T509
Test name
Test status
Simulation time 16174969 ps
CPU time 0.64 seconds
Started Apr 30 01:55:20 PM PDT 24
Finished Apr 30 01:55:21 PM PDT 24
Peak memory 203888 kb
Host smart-2cc26565-2fc3-41c2-a00f-46973d0b41b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505548781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.3505548781
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.2339522550
Short name T532
Test name
Test status
Simulation time 223446007 ps
CPU time 1.09 seconds
Started Apr 30 01:55:07 PM PDT 24
Finished Apr 30 01:55:08 PM PDT 24
Peak memory 204324 kb
Host smart-a844625e-0701-4aaf-87e6-4e8befe3d416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339522550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.2339522550
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2239446360
Short name T1064
Test name
Test status
Simulation time 2802890016 ps
CPU time 4.28 seconds
Started Apr 30 01:55:13 PM PDT 24
Finished Apr 30 01:55:18 PM PDT 24
Peak memory 244748 kb
Host smart-662dc5ce-426a-494a-8efc-8bd19d08a5fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239446360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2239446360
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.1147266464
Short name T1186
Test name
Test status
Simulation time 1531460434 ps
CPU time 105.11 seconds
Started Apr 30 01:55:15 PM PDT 24
Finished Apr 30 01:57:00 PM PDT 24
Peak memory 584400 kb
Host smart-09351d9a-6815-4822-b760-236d36a59853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147266464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.1147266464
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.2059158040
Short name T571
Test name
Test status
Simulation time 4801508918 ps
CPU time 84.02 seconds
Started Apr 30 01:55:07 PM PDT 24
Finished Apr 30 01:56:32 PM PDT 24
Peak memory 501508 kb
Host smart-572dbf2f-0951-4274-b027-6982dd6c7726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059158040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.2059158040
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.2856006527
Short name T702
Test name
Test status
Simulation time 136092732 ps
CPU time 0.85 seconds
Started Apr 30 01:55:09 PM PDT 24
Finished Apr 30 01:55:11 PM PDT 24
Peak memory 204000 kb
Host smart-61446eda-5d1e-47ac-a029-56bbc76dfeaf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856006527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.2856006527
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.2924324305
Short name T967
Test name
Test status
Simulation time 566662094 ps
CPU time 6.72 seconds
Started Apr 30 01:55:06 PM PDT 24
Finished Apr 30 01:55:13 PM PDT 24
Peak memory 204208 kb
Host smart-ae3abdee-7fc0-43c8-804b-2ba9eb7b0880
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924324305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.2924324305
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.374273805
Short name T1067
Test name
Test status
Simulation time 10537960410 ps
CPU time 121.59 seconds
Started Apr 30 01:55:07 PM PDT 24
Finished Apr 30 01:57:09 PM PDT 24
Peak memory 1359356 kb
Host smart-de89d677-ce5b-4ea8-8626-f3dfbdb009e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374273805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.374273805
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.1299169683
Short name T622
Test name
Test status
Simulation time 249604047 ps
CPU time 3.88 seconds
Started Apr 30 01:55:14 PM PDT 24
Finished Apr 30 01:55:18 PM PDT 24
Peak memory 204160 kb
Host smart-0c56e1ad-21ef-4735-a7f4-f96875a1d884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299169683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.1299169683
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.2988151711
Short name T471
Test name
Test status
Simulation time 4243494294 ps
CPU time 41.99 seconds
Started Apr 30 01:55:13 PM PDT 24
Finished Apr 30 01:55:56 PM PDT 24
Peak memory 372704 kb
Host smart-8418fd8d-06aa-4fdc-a6b4-801b6fa60ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988151711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.2988151711
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.3874982357
Short name T37
Test name
Test status
Simulation time 38439352 ps
CPU time 0.64 seconds
Started Apr 30 01:55:06 PM PDT 24
Finished Apr 30 01:55:07 PM PDT 24
Peak memory 203772 kb
Host smart-decf75fb-d03c-4766-abab-b7bce5b970b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874982357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.3874982357
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.694465510
Short name T1322
Test name
Test status
Simulation time 858610669 ps
CPU time 38.13 seconds
Started Apr 30 01:55:07 PM PDT 24
Finished Apr 30 01:55:46 PM PDT 24
Peak memory 266152 kb
Host smart-605b4f83-262e-439c-b0f1-352c248f9226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694465510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.694465510
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.2422546977
Short name T572
Test name
Test status
Simulation time 978190912 ps
CPU time 17.27 seconds
Started Apr 30 01:55:07 PM PDT 24
Finished Apr 30 01:55:24 PM PDT 24
Peak memory 322452 kb
Host smart-bc9d536f-1f1f-474a-a46d-1f2cedeb1580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422546977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.2422546977
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.1307114828
Short name T971
Test name
Test status
Simulation time 4247525524 ps
CPU time 148.02 seconds
Started Apr 30 01:55:08 PM PDT 24
Finished Apr 30 01:57:36 PM PDT 24
Peak memory 1019088 kb
Host smart-2af3808a-7d50-4451-9e56-7d701c227ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307114828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.1307114828
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.3348881268
Short name T623
Test name
Test status
Simulation time 3812219930 ps
CPU time 22.54 seconds
Started Apr 30 01:55:07 PM PDT 24
Finished Apr 30 01:55:30 PM PDT 24
Peak memory 212356 kb
Host smart-36b0879f-8f4e-4cdd-885d-ba0804f766f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348881268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.3348881268
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.1030277809
Short name T1120
Test name
Test status
Simulation time 2189901573 ps
CPU time 5.38 seconds
Started Apr 30 01:55:15 PM PDT 24
Finished Apr 30 01:55:21 PM PDT 24
Peak memory 212416 kb
Host smart-1a733639-c594-4218-aa00-29c683285671
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030277809 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.1030277809
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.2407335045
Short name T1302
Test name
Test status
Simulation time 10166613003 ps
CPU time 31.21 seconds
Started Apr 30 01:55:14 PM PDT 24
Finished Apr 30 01:55:45 PM PDT 24
Peak memory 360848 kb
Host smart-50895058-589b-4d4d-99a0-d42b455424fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407335045 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.2407335045
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.2701986389
Short name T254
Test name
Test status
Simulation time 10204670705 ps
CPU time 13.7 seconds
Started Apr 30 01:55:15 PM PDT 24
Finished Apr 30 01:55:29 PM PDT 24
Peak memory 296516 kb
Host smart-a57296b5-5816-4b74-9a9c-ba7610b97f31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701986389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.2701986389
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.338049585
Short name T22
Test name
Test status
Simulation time 822730611 ps
CPU time 2.46 seconds
Started Apr 30 01:55:15 PM PDT 24
Finished Apr 30 01:55:18 PM PDT 24
Peak memory 204196 kb
Host smart-5aacaece-f90c-465a-b7b9-e69725c59586
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338049585 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.i2c_target_hrst.338049585
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3332456584
Short name T969
Test name
Test status
Simulation time 2820488811 ps
CPU time 6.65 seconds
Started Apr 30 01:55:13 PM PDT 24
Finished Apr 30 01:55:20 PM PDT 24
Peak memory 219288 kb
Host smart-5f109138-8cb8-484c-8c3e-01c3c7f6c033
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332456584 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3332456584
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.2564271431
Short name T445
Test name
Test status
Simulation time 23063968248 ps
CPU time 171.74 seconds
Started Apr 30 01:55:13 PM PDT 24
Finished Apr 30 01:58:05 PM PDT 24
Peak memory 2488612 kb
Host smart-e204346e-b4af-4c79-85c6-be62c88f9c6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564271431 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.2564271431
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.1609842003
Short name T238
Test name
Test status
Simulation time 891475711 ps
CPU time 14.25 seconds
Started Apr 30 01:55:08 PM PDT 24
Finished Apr 30 01:55:23 PM PDT 24
Peak memory 204120 kb
Host smart-9898c839-1234-42ad-882d-eb0e29962800
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609842003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.1609842003
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.1396483717
Short name T462
Test name
Test status
Simulation time 3720057002 ps
CPU time 10.35 seconds
Started Apr 30 01:55:16 PM PDT 24
Finished Apr 30 01:55:26 PM PDT 24
Peak memory 211684 kb
Host smart-a7ff9abf-531b-44f3-85ae-cfa9821d61ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396483717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.1396483717
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.2433670269
Short name T798
Test name
Test status
Simulation time 37197357082 ps
CPU time 162.84 seconds
Started Apr 30 01:55:17 PM PDT 24
Finished Apr 30 01:58:00 PM PDT 24
Peak memory 2146976 kb
Host smart-ef774e0a-2bf7-4f17-b000-a14054d2ab49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433670269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.2433670269
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.3514989254
Short name T319
Test name
Test status
Simulation time 15590144379 ps
CPU time 653.71 seconds
Started Apr 30 01:55:16 PM PDT 24
Finished Apr 30 02:06:10 PM PDT 24
Peak memory 1842840 kb
Host smart-2ae4ee07-4b20-4034-af59-5e9914e68ed2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514989254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.3514989254
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.3909177346
Short name T294
Test name
Test status
Simulation time 4605158908 ps
CPU time 6.65 seconds
Started Apr 30 01:55:14 PM PDT 24
Finished Apr 30 01:55:21 PM PDT 24
Peak memory 212396 kb
Host smart-85e61abc-1a65-4f10-a535-1bd14076cb24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909177346 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.3909177346
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.907008200
Short name T797
Test name
Test status
Simulation time 18689594 ps
CPU time 0.61 seconds
Started Apr 30 01:55:30 PM PDT 24
Finished Apr 30 01:55:31 PM PDT 24
Peak memory 203820 kb
Host smart-164c2e3f-5213-4bba-91bf-8a9351194946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907008200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.907008200
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.1057703420
Short name T453
Test name
Test status
Simulation time 1960926197 ps
CPU time 4.69 seconds
Started Apr 30 01:55:20 PM PDT 24
Finished Apr 30 01:55:26 PM PDT 24
Peak memory 241224 kb
Host smart-ca61a968-2ca7-445f-a9ba-15fe770014db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057703420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.1057703420
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.976405891
Short name T464
Test name
Test status
Simulation time 1969548815 ps
CPU time 126.16 seconds
Started Apr 30 01:55:20 PM PDT 24
Finished Apr 30 01:57:26 PM PDT 24
Peak memory 596676 kb
Host smart-b7af806b-8b4a-4bd7-aec5-c10404b21545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976405891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.976405891
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.1231375363
Short name T434
Test name
Test status
Simulation time 11713272578 ps
CPU time 73.48 seconds
Started Apr 30 01:55:22 PM PDT 24
Finished Apr 30 01:56:36 PM PDT 24
Peak memory 673076 kb
Host smart-f6ce2657-00ab-4d0d-814c-12d99d6a4bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231375363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.1231375363
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.3902473284
Short name T210
Test name
Test status
Simulation time 159367082 ps
CPU time 0.85 seconds
Started Apr 30 01:55:19 PM PDT 24
Finished Apr 30 01:55:20 PM PDT 24
Peak memory 203940 kb
Host smart-3a78fed1-0fe7-4a7a-9b51-1394e1a95995
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902473284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.3902473284
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.2344704177
Short name T952
Test name
Test status
Simulation time 10854042159 ps
CPU time 63.67 seconds
Started Apr 30 01:55:21 PM PDT 24
Finished Apr 30 01:56:25 PM PDT 24
Peak memory 799644 kb
Host smart-bd280711-b560-48b0-998c-f77145834ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344704177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.2344704177
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.3933831340
Short name T1136
Test name
Test status
Simulation time 274758968 ps
CPU time 4.34 seconds
Started Apr 30 01:55:31 PM PDT 24
Finished Apr 30 01:55:35 PM PDT 24
Peak memory 204140 kb
Host smart-e1ebd46a-37fe-4b1c-b0d2-8293620e535b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933831340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.3933831340
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.4029186033
Short name T438
Test name
Test status
Simulation time 1373583711 ps
CPU time 66.55 seconds
Started Apr 30 01:55:28 PM PDT 24
Finished Apr 30 01:56:35 PM PDT 24
Peak memory 334028 kb
Host smart-019586d6-6d42-4993-a7bb-8573d65f3c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029186033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.4029186033
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.819712283
Short name T189
Test name
Test status
Simulation time 34847032 ps
CPU time 0.69 seconds
Started Apr 30 01:55:20 PM PDT 24
Finished Apr 30 01:55:22 PM PDT 24
Peak memory 203768 kb
Host smart-d4c6f168-0f9a-4e77-b265-80394e96a397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819712283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.819712283
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.2887577032
Short name T861
Test name
Test status
Simulation time 18490092715 ps
CPU time 1053.35 seconds
Started Apr 30 01:55:20 PM PDT 24
Finished Apr 30 02:12:54 PM PDT 24
Peak memory 1949900 kb
Host smart-1fe18d45-8e65-4fd0-aa0b-b2353fa6640e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887577032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2887577032
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.3274885435
Short name T429
Test name
Test status
Simulation time 1703102007 ps
CPU time 81.6 seconds
Started Apr 30 01:55:20 PM PDT 24
Finished Apr 30 01:56:43 PM PDT 24
Peak memory 300108 kb
Host smart-8d64507a-850a-47cf-9e0c-77c48f2be29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274885435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.3274885435
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.2978191153
Short name T397
Test name
Test status
Simulation time 24330604049 ps
CPU time 1648.19 seconds
Started Apr 30 01:55:20 PM PDT 24
Finished Apr 30 02:22:49 PM PDT 24
Peak memory 2860616 kb
Host smart-773b81b8-6789-4fa3-9cfd-4ed858c36fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978191153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.2978191153
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.3216083520
Short name T492
Test name
Test status
Simulation time 10415886788 ps
CPU time 27.76 seconds
Started Apr 30 01:55:20 PM PDT 24
Finished Apr 30 01:55:48 PM PDT 24
Peak memory 212432 kb
Host smart-a1f2b517-2001-4dc3-b52d-2745f9c06ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216083520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3216083520
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.3337254889
Short name T1271
Test name
Test status
Simulation time 3413254394 ps
CPU time 4.55 seconds
Started Apr 30 01:55:20 PM PDT 24
Finished Apr 30 01:55:25 PM PDT 24
Peak memory 212412 kb
Host smart-49cc6a45-5817-42e0-b623-ddccf1140061
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337254889 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.3337254889
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.1509572507
Short name T1337
Test name
Test status
Simulation time 10189269729 ps
CPU time 30.67 seconds
Started Apr 30 01:55:21 PM PDT 24
Finished Apr 30 01:55:52 PM PDT 24
Peak memory 321000 kb
Host smart-081d2a2b-bf9a-4b26-bb02-a1e949c3108e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509572507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.1509572507
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.3289778075
Short name T489
Test name
Test status
Simulation time 10160868997 ps
CPU time 31.5 seconds
Started Apr 30 01:55:21 PM PDT 24
Finished Apr 30 01:55:53 PM PDT 24
Peak memory 320420 kb
Host smart-73f4f495-ce3e-4877-99fe-00aec7f994e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289778075 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.3289778075
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.4110655501
Short name T1301
Test name
Test status
Simulation time 1664387306 ps
CPU time 2.63 seconds
Started Apr 30 01:55:22 PM PDT 24
Finished Apr 30 01:55:25 PM PDT 24
Peak memory 204148 kb
Host smart-0530ab63-7f53-4314-82b5-ced1b609d078
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110655501 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.4110655501
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.992369255
Short name T907
Test name
Test status
Simulation time 1205057267 ps
CPU time 3.21 seconds
Started Apr 30 01:55:21 PM PDT 24
Finished Apr 30 01:55:25 PM PDT 24
Peak memory 204172 kb
Host smart-d2b58a68-6315-4b5e-891a-29126ab4ba2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992369255 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_intr_smoke.992369255
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.1596008222
Short name T630
Test name
Test status
Simulation time 14520524052 ps
CPU time 30.61 seconds
Started Apr 30 01:55:19 PM PDT 24
Finished Apr 30 01:55:50 PM PDT 24
Peak memory 900968 kb
Host smart-5929ea73-da0e-4b44-9a97-86805fc82c5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596008222 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.1596008222
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.3405533093
Short name T391
Test name
Test status
Simulation time 1340136441 ps
CPU time 50.5 seconds
Started Apr 30 01:55:21 PM PDT 24
Finished Apr 30 01:56:12 PM PDT 24
Peak memory 204212 kb
Host smart-60183ccc-65f8-4c5b-b578-b48981e067c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405533093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.3405533093
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3830071306
Short name T885
Test name
Test status
Simulation time 916045103 ps
CPU time 14.83 seconds
Started Apr 30 01:55:19 PM PDT 24
Finished Apr 30 01:55:35 PM PDT 24
Peak memory 220832 kb
Host smart-42114bde-da8e-49d8-b88a-323f0b0e1ea0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830071306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3830071306
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.3342866721
Short name T231
Test name
Test status
Simulation time 61234236005 ps
CPU time 242.04 seconds
Started Apr 30 01:55:21 PM PDT 24
Finished Apr 30 01:59:23 PM PDT 24
Peak memory 2425960 kb
Host smart-cc328b60-d257-4767-ba68-02ec4df1abf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342866721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.3342866721
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.528759927
Short name T934
Test name
Test status
Simulation time 22878452525 ps
CPU time 530.33 seconds
Started Apr 30 01:55:20 PM PDT 24
Finished Apr 30 02:04:11 PM PDT 24
Peak memory 3276748 kb
Host smart-ed88e769-913c-418a-9191-dc5022b1b4eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528759927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_t
arget_stretch.528759927
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.2851678462
Short name T486
Test name
Test status
Simulation time 3215841631 ps
CPU time 7.53 seconds
Started Apr 30 01:55:20 PM PDT 24
Finished Apr 30 01:55:28 PM PDT 24
Peak memory 219280 kb
Host smart-7f1ea844-5939-4a2c-b20d-b9578efc998b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851678462 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.2851678462
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3891988928
Short name T1238
Test name
Test status
Simulation time 42005800 ps
CPU time 0.63 seconds
Started Apr 30 01:55:34 PM PDT 24
Finished Apr 30 01:55:35 PM PDT 24
Peak memory 203916 kb
Host smart-de336b26-3a36-4482-b59a-adb58f09c586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891988928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3891988928
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.1307122198
Short name T1132
Test name
Test status
Simulation time 154968329 ps
CPU time 2.17 seconds
Started Apr 30 01:55:27 PM PDT 24
Finished Apr 30 01:55:30 PM PDT 24
Peak memory 212400 kb
Host smart-c9f156fc-2a3c-4058-bada-d2b2f9831cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307122198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.1307122198
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.2514986915
Short name T1172
Test name
Test status
Simulation time 1137196196 ps
CPU time 14.72 seconds
Started Apr 30 01:55:32 PM PDT 24
Finished Apr 30 01:55:47 PM PDT 24
Peak memory 261520 kb
Host smart-7e3cb5b9-d789-490c-9721-3d8322c62307
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514986915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.2514986915
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.212304991
Short name T544
Test name
Test status
Simulation time 7502256265 ps
CPU time 113.55 seconds
Started Apr 30 01:55:29 PM PDT 24
Finished Apr 30 01:57:24 PM PDT 24
Peak memory 526748 kb
Host smart-1e8ef391-0f85-4ce7-b4e4-fb5b97b61595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212304991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.212304991
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.4173361908
Short name T270
Test name
Test status
Simulation time 1897646352 ps
CPU time 54.03 seconds
Started Apr 30 01:55:30 PM PDT 24
Finished Apr 30 01:56:24 PM PDT 24
Peak memory 634280 kb
Host smart-a6921056-b582-49dd-b3a9-0dff48ef09ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173361908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.4173361908
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.547937521
Short name T74
Test name
Test status
Simulation time 549189048 ps
CPU time 1.15 seconds
Started Apr 30 01:55:32 PM PDT 24
Finished Apr 30 01:55:33 PM PDT 24
Peak memory 204148 kb
Host smart-83b45791-a524-48bc-9711-ae28a0b14731
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547937521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fm
t.547937521
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.1680703826
Short name T605
Test name
Test status
Simulation time 732270323 ps
CPU time 4.62 seconds
Started Apr 30 01:55:32 PM PDT 24
Finished Apr 30 01:55:37 PM PDT 24
Peak memory 236372 kb
Host smart-5cded4b6-26e6-46b8-97c7-88990118b842
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680703826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.1680703826
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.2659548987
Short name T586
Test name
Test status
Simulation time 3702970589 ps
CPU time 109.97 seconds
Started Apr 30 01:55:34 PM PDT 24
Finished Apr 30 01:57:24 PM PDT 24
Peak memory 1095712 kb
Host smart-0bd8675b-c653-44d1-8cbb-6c7e378de503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659548987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.2659548987
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.2107177753
Short name T1251
Test name
Test status
Simulation time 1703250383 ps
CPU time 6.36 seconds
Started Apr 30 01:55:34 PM PDT 24
Finished Apr 30 01:55:41 PM PDT 24
Peak memory 204200 kb
Host smart-d0718ffe-2210-45f2-aeee-0f90cd5518a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107177753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2107177753
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.164071596
Short name T680
Test name
Test status
Simulation time 9954691765 ps
CPU time 23.8 seconds
Started Apr 30 01:55:36 PM PDT 24
Finished Apr 30 01:56:00 PM PDT 24
Peak memory 333824 kb
Host smart-690f5901-547c-4c84-956a-f19cb951681e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164071596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.164071596
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.2344808051
Short name T872
Test name
Test status
Simulation time 34979089 ps
CPU time 0.64 seconds
Started Apr 30 01:55:29 PM PDT 24
Finished Apr 30 01:55:30 PM PDT 24
Peak memory 203872 kb
Host smart-7f853065-8a55-4b16-be9f-8441cc7d73a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344808051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.2344808051
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.2636487343
Short name T1242
Test name
Test status
Simulation time 5200378624 ps
CPU time 177.2 seconds
Started Apr 30 01:55:29 PM PDT 24
Finished Apr 30 01:58:26 PM PDT 24
Peak memory 1380244 kb
Host smart-b23b4e19-437d-42e0-82e9-af76f4718d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636487343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.2636487343
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.1825535885
Short name T1003
Test name
Test status
Simulation time 996770063 ps
CPU time 42.72 seconds
Started Apr 30 01:55:28 PM PDT 24
Finished Apr 30 01:56:11 PM PDT 24
Peak memory 261192 kb
Host smart-d9d13f22-8e5d-4994-a4c6-57075e6117fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825535885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.1825535885
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.1840962143
Short name T685
Test name
Test status
Simulation time 9239699201 ps
CPU time 1149.44 seconds
Started Apr 30 01:55:27 PM PDT 24
Finished Apr 30 02:14:37 PM PDT 24
Peak memory 1705016 kb
Host smart-a6d00a35-fc7e-4c0b-9c6c-f82a815605a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840962143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.1840962143
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.933829268
Short name T8
Test name
Test status
Simulation time 1631756789 ps
CPU time 18.76 seconds
Started Apr 30 01:55:29 PM PDT 24
Finished Apr 30 01:55:48 PM PDT 24
Peak memory 212400 kb
Host smart-3558166b-303e-4ec3-8dad-8fd60ec0cf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933829268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.933829268
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.3897187357
Short name T1218
Test name
Test status
Simulation time 908318801 ps
CPU time 4.45 seconds
Started Apr 30 01:55:29 PM PDT 24
Finished Apr 30 01:55:34 PM PDT 24
Peak memory 204152 kb
Host smart-4ca9a9ba-2cd7-4a46-b1c9-0ac35c9e4517
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897187357 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.3897187357
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.2728103488
Short name T1209
Test name
Test status
Simulation time 10778720096 ps
CPU time 6.39 seconds
Started Apr 30 01:55:29 PM PDT 24
Finished Apr 30 01:55:36 PM PDT 24
Peak memory 219104 kb
Host smart-e053a958-10ea-4223-ba4f-8be13ebc30d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728103488 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.2728103488
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.2508136957
Short name T581
Test name
Test status
Simulation time 10288158256 ps
CPU time 14.72 seconds
Started Apr 30 01:55:29 PM PDT 24
Finished Apr 30 01:55:45 PM PDT 24
Peak memory 287584 kb
Host smart-10298e63-173d-48f9-aa6f-2e51599f26db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508136957 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.2508136957
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.3136300796
Short name T179
Test name
Test status
Simulation time 4866565070 ps
CPU time 2.28 seconds
Started Apr 30 01:55:32 PM PDT 24
Finished Apr 30 01:55:35 PM PDT 24
Peak memory 204140 kb
Host smart-056d0455-e556-4357-a5e5-437ed67f7fb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136300796 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.3136300796
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.1207304296
Short name T1192
Test name
Test status
Simulation time 1559008306 ps
CPU time 4.01 seconds
Started Apr 30 01:55:29 PM PDT 24
Finished Apr 30 01:55:34 PM PDT 24
Peak memory 204308 kb
Host smart-0e850e7b-ba21-42c6-8fc2-83e83ae4a2d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207304296 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.1207304296
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.3622699294
Short name T870
Test name
Test status
Simulation time 19634782625 ps
CPU time 130.21 seconds
Started Apr 30 01:55:32 PM PDT 24
Finished Apr 30 01:57:43 PM PDT 24
Peak memory 2336292 kb
Host smart-60927225-a020-483c-9976-95b57624c7a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622699294 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.3622699294
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.863572067
Short name T1235
Test name
Test status
Simulation time 810755837 ps
CPU time 27.62 seconds
Started Apr 30 01:55:28 PM PDT 24
Finished Apr 30 01:55:56 PM PDT 24
Peak memory 204176 kb
Host smart-2ad39944-b26b-4a61-ab15-2345728a0ff1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863572067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_tar
get_smoke.863572067
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_all.2858578212
Short name T230
Test name
Test status
Simulation time 78340359399 ps
CPU time 315.71 seconds
Started Apr 30 01:55:31 PM PDT 24
Finished Apr 30 02:00:47 PM PDT 24
Peak memory 3504592 kb
Host smart-2ae6a6c9-fd3a-4a9b-bbe0-3394b4ffe1fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858578212 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 27.i2c_target_stress_all.2858578212
Directory /workspace/27.i2c_target_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.550030308
Short name T793
Test name
Test status
Simulation time 7724618068 ps
CPU time 25.33 seconds
Started Apr 30 01:55:27 PM PDT 24
Finished Apr 30 01:55:53 PM PDT 24
Peak memory 234680 kb
Host smart-3a0a7fe3-58db-4e68-9b90-097fa710f06a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550030308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_rd.550030308
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.2631432555
Short name T701
Test name
Test status
Simulation time 58525280776 ps
CPU time 227.42 seconds
Started Apr 30 01:55:30 PM PDT 24
Finished Apr 30 01:59:18 PM PDT 24
Peak memory 2415352 kb
Host smart-e704bab8-471a-4582-b012-23f082411902
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631432555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.2631432555
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.2222897727
Short name T1244
Test name
Test status
Simulation time 42014732589 ps
CPU time 164.63 seconds
Started Apr 30 01:55:31 PM PDT 24
Finished Apr 30 01:58:16 PM PDT 24
Peak memory 1384364 kb
Host smart-05d0ed4a-cc67-40d0-abdb-80885b198218
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222897727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.2222897727
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.757603517
Short name T284
Test name
Test status
Simulation time 1568733180 ps
CPU time 7.06 seconds
Started Apr 30 01:55:29 PM PDT 24
Finished Apr 30 01:55:36 PM PDT 24
Peak memory 212300 kb
Host smart-fc68b0e7-1d4f-4190-b439-3db61d158e70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757603517 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_timeout.757603517
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.3607269845
Short name T880
Test name
Test status
Simulation time 21275694 ps
CPU time 0.62 seconds
Started Apr 30 01:55:34 PM PDT 24
Finished Apr 30 01:55:36 PM PDT 24
Peak memory 203904 kb
Host smart-b5ef0dae-fdcc-481a-82f5-b2e5a1d7a142
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607269845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.3607269845
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.2412525825
Short name T903
Test name
Test status
Simulation time 88081761 ps
CPU time 1.82 seconds
Started Apr 30 01:55:35 PM PDT 24
Finished Apr 30 01:55:38 PM PDT 24
Peak memory 212388 kb
Host smart-4f753794-844a-4dca-a2ee-667422977bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412525825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.2412525825
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2680910151
Short name T995
Test name
Test status
Simulation time 3678304493 ps
CPU time 5.29 seconds
Started Apr 30 01:55:35 PM PDT 24
Finished Apr 30 01:55:41 PM PDT 24
Peak memory 257804 kb
Host smart-ce447f6c-c305-4423-8a9d-500b09ca9b4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680910151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2680910151
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3406165029
Short name T1073
Test name
Test status
Simulation time 3506861921 ps
CPU time 49.59 seconds
Started Apr 30 01:55:33 PM PDT 24
Finished Apr 30 01:56:23 PM PDT 24
Peak memory 550232 kb
Host smart-dd0e0794-5ae1-45c1-b9d2-2e702fe05ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406165029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3406165029
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.3570581356
Short name T1004
Test name
Test status
Simulation time 4803195684 ps
CPU time 86.31 seconds
Started Apr 30 01:55:34 PM PDT 24
Finished Apr 30 01:57:01 PM PDT 24
Peak memory 501492 kb
Host smart-94244a2a-9757-4471-8790-29934c729d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570581356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3570581356
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.2970595387
Short name T265
Test name
Test status
Simulation time 129638550 ps
CPU time 1.15 seconds
Started Apr 30 01:55:35 PM PDT 24
Finished Apr 30 01:55:37 PM PDT 24
Peak memory 204156 kb
Host smart-eadf4911-15d3-4dc5-938e-b8ca8dea4949
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970595387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.2970595387
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.148743084
Short name T1135
Test name
Test status
Simulation time 576242180 ps
CPU time 4.36 seconds
Started Apr 30 01:55:32 PM PDT 24
Finished Apr 30 01:55:37 PM PDT 24
Peak memory 229476 kb
Host smart-c34d1ccf-5358-4310-9767-155f15dc7823
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148743084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.
148743084
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.2341817598
Short name T851
Test name
Test status
Simulation time 3090904207 ps
CPU time 85.32 seconds
Started Apr 30 01:55:42 PM PDT 24
Finished Apr 30 01:57:08 PM PDT 24
Peak memory 939824 kb
Host smart-e7d40f9a-b362-4bd5-b4e8-25fff5b92839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341817598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.2341817598
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.2087686332
Short name T1070
Test name
Test status
Simulation time 379811678 ps
CPU time 6.08 seconds
Started Apr 30 01:55:34 PM PDT 24
Finished Apr 30 01:55:41 PM PDT 24
Peak memory 204084 kb
Host smart-89cc0da5-1af4-429a-aa0d-6df60083eb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087686332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.2087686332
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.2345793136
Short name T66
Test name
Test status
Simulation time 1942417513 ps
CPU time 37.94 seconds
Started Apr 30 01:55:34 PM PDT 24
Finished Apr 30 01:56:13 PM PDT 24
Peak memory 349896 kb
Host smart-b7318962-fb9d-4886-b662-49d34b7d8d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345793136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.2345793136
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.4155454725
Short name T1016
Test name
Test status
Simulation time 79933821 ps
CPU time 0.68 seconds
Started Apr 30 01:55:35 PM PDT 24
Finished Apr 30 01:55:37 PM PDT 24
Peak memory 204040 kb
Host smart-813a3c8c-9ff4-4eb9-9fa8-b8c312d5c254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155454725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.4155454725
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.2447017997
Short name T1083
Test name
Test status
Simulation time 12229807272 ps
CPU time 461.79 seconds
Started Apr 30 01:55:34 PM PDT 24
Finished Apr 30 02:03:16 PM PDT 24
Peak memory 204288 kb
Host smart-367a52f6-f23a-4938-bf68-8f06ac3b5dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447017997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.2447017997
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1873916081
Short name T1123
Test name
Test status
Simulation time 1154865159 ps
CPU time 20.1 seconds
Started Apr 30 01:55:38 PM PDT 24
Finished Apr 30 01:55:59 PM PDT 24
Peak memory 260676 kb
Host smart-2a9e4344-68d7-4632-b68e-e59d1da36e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873916081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1873916081
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.2953819335
Short name T242
Test name
Test status
Simulation time 21959012782 ps
CPU time 460.24 seconds
Started Apr 30 01:55:36 PM PDT 24
Finished Apr 30 02:03:16 PM PDT 24
Peak memory 1783240 kb
Host smart-dadbe2ef-c933-4aa2-99f0-ac69887fa3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953819335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.2953819335
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.3047646439
Short name T1354
Test name
Test status
Simulation time 627555002 ps
CPU time 22.73 seconds
Started Apr 30 01:55:35 PM PDT 24
Finished Apr 30 01:55:58 PM PDT 24
Peak memory 212416 kb
Host smart-c0d23bd8-b90c-4af2-a089-c25de04de223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047646439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.3047646439
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.4070230631
Short name T712
Test name
Test status
Simulation time 3293182401 ps
CPU time 3.65 seconds
Started Apr 30 01:55:35 PM PDT 24
Finished Apr 30 01:55:39 PM PDT 24
Peak memory 212396 kb
Host smart-b3d816e2-93e4-4aaf-a051-0c3baf64619b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070230631 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.4070230631
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.2649060113
Short name T358
Test name
Test status
Simulation time 10090475713 ps
CPU time 15.35 seconds
Started Apr 30 01:55:34 PM PDT 24
Finished Apr 30 01:55:50 PM PDT 24
Peak memory 254344 kb
Host smart-fae77872-d097-47c3-a6d2-a508e1958897
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649060113 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.2649060113
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.2178200313
Short name T430
Test name
Test status
Simulation time 10060581051 ps
CPU time 81.28 seconds
Started Apr 30 01:55:37 PM PDT 24
Finished Apr 30 01:56:59 PM PDT 24
Peak memory 526056 kb
Host smart-48d3a17c-478b-412e-b2cc-0db24ec6a965
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178200313 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.2178200313
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.669002848
Short name T14
Test name
Test status
Simulation time 405622320 ps
CPU time 2.49 seconds
Started Apr 30 01:55:40 PM PDT 24
Finished Apr 30 01:55:43 PM PDT 24
Peak memory 204144 kb
Host smart-cf3e9c3d-af87-42d7-84aa-3d66edc388e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669002848 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.i2c_target_hrst.669002848
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.826216977
Short name T181
Test name
Test status
Simulation time 4426340075 ps
CPU time 5.38 seconds
Started Apr 30 01:55:33 PM PDT 24
Finished Apr 30 01:55:38 PM PDT 24
Peak memory 218752 kb
Host smart-90717540-36e0-4cb5-9f03-0c0d27d5e6f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826216977 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.826216977
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.1870336936
Short name T1095
Test name
Test status
Simulation time 9236539677 ps
CPU time 119.3 seconds
Started Apr 30 01:55:34 PM PDT 24
Finished Apr 30 01:57:34 PM PDT 24
Peak memory 2294320 kb
Host smart-c82d647a-6d2b-4271-9073-5ef53030e7ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870336936 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.1870336936
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1700287541
Short name T1049
Test name
Test status
Simulation time 1190237385 ps
CPU time 47.06 seconds
Started Apr 30 01:55:33 PM PDT 24
Finished Apr 30 01:56:21 PM PDT 24
Peak memory 204212 kb
Host smart-eb600845-fab2-433f-9d05-e666cc7b5b4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700287541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1700287541
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.646827074
Short name T541
Test name
Test status
Simulation time 9215622631 ps
CPU time 31.85 seconds
Started Apr 30 01:55:37 PM PDT 24
Finished Apr 30 01:56:09 PM PDT 24
Peak memory 225808 kb
Host smart-1a48ae3a-2b19-4e1e-abcc-a0d97bce4973
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646827074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c
_target_stress_rd.646827074
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.2675328174
Short name T935
Test name
Test status
Simulation time 13812888982 ps
CPU time 7.26 seconds
Started Apr 30 01:55:35 PM PDT 24
Finished Apr 30 01:55:43 PM PDT 24
Peak memory 204184 kb
Host smart-ed8e1014-784d-4740-aa85-bb661c945477
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675328174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.2675328174
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.1111315607
Short name T962
Test name
Test status
Simulation time 6080574928 ps
CPU time 166.11 seconds
Started Apr 30 01:55:37 PM PDT 24
Finished Apr 30 01:58:24 PM PDT 24
Peak memory 799264 kb
Host smart-215f95d2-59d9-4933-a118-f80cbde5c019
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111315607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.1111315607
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.3066971189
Short name T679
Test name
Test status
Simulation time 5700547277 ps
CPU time 7.01 seconds
Started Apr 30 01:55:34 PM PDT 24
Finished Apr 30 01:55:42 PM PDT 24
Peak memory 220424 kb
Host smart-030571de-519d-4c39-b73b-b9054d2ad670
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066971189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.3066971189
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_unexp_stop.80867015
Short name T221
Test name
Test status
Simulation time 6800762305 ps
CPU time 5.45 seconds
Started Apr 30 01:55:36 PM PDT 24
Finished Apr 30 01:55:42 PM PDT 24
Peak memory 219516 kb
Host smart-5876fae7-780c-4dea-9c3e-5d1351846fdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80867015 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_unexp_stop.80867015
Directory /workspace/28.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/29.i2c_alert_test.1869070385
Short name T773
Test name
Test status
Simulation time 16278719 ps
CPU time 0.67 seconds
Started Apr 30 01:55:49 PM PDT 24
Finished Apr 30 01:55:51 PM PDT 24
Peak memory 203916 kb
Host smart-389b6b27-5ea2-4ae1-aea0-acd9caaef92b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869070385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1869070385
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.1432793189
Short name T1051
Test name
Test status
Simulation time 378599471 ps
CPU time 1.1 seconds
Started Apr 30 01:55:38 PM PDT 24
Finished Apr 30 01:55:40 PM PDT 24
Peak memory 204288 kb
Host smart-4514c1c8-4b38-4ef6-bc86-d1f6d3e52ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432793189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.1432793189
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.333376108
Short name T376
Test name
Test status
Simulation time 457688815 ps
CPU time 5.71 seconds
Started Apr 30 01:55:39 PM PDT 24
Finished Apr 30 01:55:45 PM PDT 24
Peak memory 221828 kb
Host smart-ea314254-f7a0-4ea8-913e-6362f071924d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333376108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empt
y.333376108
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.404898953
Short name T298
Test name
Test status
Simulation time 4293784121 ps
CPU time 156.34 seconds
Started Apr 30 01:55:38 PM PDT 24
Finished Apr 30 01:58:15 PM PDT 24
Peak memory 716352 kb
Host smart-114a218d-8383-4c20-bf3c-fa416168b85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404898953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.404898953
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.1904612052
Short name T1356
Test name
Test status
Simulation time 1427194490 ps
CPU time 37.74 seconds
Started Apr 30 01:55:42 PM PDT 24
Finished Apr 30 01:56:20 PM PDT 24
Peak memory 521192 kb
Host smart-ffe0dacd-2a96-49fa-a9ad-d53c8d41225d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904612052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1904612052
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.621581438
Short name T615
Test name
Test status
Simulation time 287399521 ps
CPU time 0.84 seconds
Started Apr 30 01:55:38 PM PDT 24
Finished Apr 30 01:55:40 PM PDT 24
Peak memory 203904 kb
Host smart-2f483a14-ccdd-426a-a020-ec1bbfcf28e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621581438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fm
t.621581438
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.2715716682
Short name T331
Test name
Test status
Simulation time 156385593 ps
CPU time 2.84 seconds
Started Apr 30 01:55:38 PM PDT 24
Finished Apr 30 01:55:42 PM PDT 24
Peak memory 204160 kb
Host smart-ef3ae939-e854-4a28-befa-5ebb3a262e7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715716682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.2715716682
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.3048499975
Short name T1031
Test name
Test status
Simulation time 3983084301 ps
CPU time 104.67 seconds
Started Apr 30 01:55:34 PM PDT 24
Finished Apr 30 01:57:20 PM PDT 24
Peak memory 1153260 kb
Host smart-34af4e78-ec75-401f-b95f-748324527460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048499975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.3048499975
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.3568290509
Short name T307
Test name
Test status
Simulation time 311946418 ps
CPU time 4.15 seconds
Started Apr 30 01:55:48 PM PDT 24
Finished Apr 30 01:55:53 PM PDT 24
Peak memory 204228 kb
Host smart-fc036b1e-2d8f-4a23-bf81-0a0c193b944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568290509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.3568290509
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_override.506555261
Short name T817
Test name
Test status
Simulation time 51282397 ps
CPU time 0.66 seconds
Started Apr 30 01:55:34 PM PDT 24
Finished Apr 30 01:55:35 PM PDT 24
Peak memory 203828 kb
Host smart-3ef1e833-e7f6-4976-8887-116b16dbb6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506555261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.506555261
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.1932376755
Short name T921
Test name
Test status
Simulation time 27007760550 ps
CPU time 1010.54 seconds
Started Apr 30 01:55:40 PM PDT 24
Finished Apr 30 02:12:31 PM PDT 24
Peak memory 250488 kb
Host smart-e17933aa-be5e-4324-8a1e-219eed98a5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932376755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.1932376755
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.2485455515
Short name T1069
Test name
Test status
Simulation time 4535223573 ps
CPU time 48.3 seconds
Started Apr 30 01:55:33 PM PDT 24
Finished Apr 30 01:56:22 PM PDT 24
Peak memory 293776 kb
Host smart-0dcfc964-9891-4809-8710-e19938020cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485455515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.2485455515
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.2100231738
Short name T1258
Test name
Test status
Simulation time 10345621355 ps
CPU time 463.74 seconds
Started Apr 30 01:55:40 PM PDT 24
Finished Apr 30 02:03:24 PM PDT 24
Peak memory 1870080 kb
Host smart-a6f8f3a9-ee7d-4393-a8e5-b002b5805e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100231738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.2100231738
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.793697971
Short name T517
Test name
Test status
Simulation time 677766920 ps
CPU time 30.82 seconds
Started Apr 30 01:55:42 PM PDT 24
Finished Apr 30 01:56:13 PM PDT 24
Peak memory 212380 kb
Host smart-cae7510e-4aa5-4422-90ed-0acc6e0f7613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793697971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.793697971
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.2435405892
Short name T396
Test name
Test status
Simulation time 2077407837 ps
CPU time 3.06 seconds
Started Apr 30 01:55:48 PM PDT 24
Finished Apr 30 01:55:51 PM PDT 24
Peak memory 204184 kb
Host smart-e5e016d7-7d2b-4596-953b-86de35af698e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435405892 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.2435405892
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.3322583891
Short name T1176
Test name
Test status
Simulation time 10068798472 ps
CPU time 54.69 seconds
Started Apr 30 01:55:39 PM PDT 24
Finished Apr 30 01:56:34 PM PDT 24
Peak memory 345460 kb
Host smart-ccd4128d-bb00-4abd-9a6f-cf4416d9601c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322583891 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.3322583891
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3481439226
Short name T977
Test name
Test status
Simulation time 10345685599 ps
CPU time 14.26 seconds
Started Apr 30 01:55:39 PM PDT 24
Finished Apr 30 01:55:54 PM PDT 24
Peak memory 285120 kb
Host smart-46c82f41-f6f8-4a8f-beaf-17234ff11702
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481439226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3481439226
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.2668756258
Short name T116
Test name
Test status
Simulation time 1654004862 ps
CPU time 2.7 seconds
Started Apr 30 01:55:46 PM PDT 24
Finished Apr 30 01:55:50 PM PDT 24
Peak memory 204200 kb
Host smart-f4f5cf0c-aeaa-4f58-ab4e-1592ed2f69f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668756258 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.2668756258
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.1769364155
Short name T1118
Test name
Test status
Simulation time 7496977450 ps
CPU time 4.82 seconds
Started Apr 30 01:55:40 PM PDT 24
Finished Apr 30 01:55:45 PM PDT 24
Peak memory 204224 kb
Host smart-7f64541d-c492-4c94-90a2-86a5032a6ec5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769364155 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.1769364155
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.3432077944
Short name T714
Test name
Test status
Simulation time 21279397987 ps
CPU time 82.96 seconds
Started Apr 30 01:55:38 PM PDT 24
Finished Apr 30 01:57:02 PM PDT 24
Peak memory 1613532 kb
Host smart-0ce814b9-beeb-42e5-af31-b6bd6895b2fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432077944 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.3432077944
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.3739803911
Short name T750
Test name
Test status
Simulation time 6952620045 ps
CPU time 39.96 seconds
Started Apr 30 01:55:38 PM PDT 24
Finished Apr 30 01:56:19 PM PDT 24
Peak memory 204176 kb
Host smart-afbc8744-80f5-4889-992d-9674c8b3a7a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739803911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.3739803911
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.3681639110
Short name T261
Test name
Test status
Simulation time 3099545492 ps
CPU time 12.47 seconds
Started Apr 30 01:55:40 PM PDT 24
Finished Apr 30 01:55:53 PM PDT 24
Peak memory 212956 kb
Host smart-fb253e4e-8b46-4da6-ad67-345aaa9ae809
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681639110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.3681639110
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.1440858154
Short name T488
Test name
Test status
Simulation time 45614155103 ps
CPU time 116.92 seconds
Started Apr 30 01:55:37 PM PDT 24
Finished Apr 30 01:57:34 PM PDT 24
Peak memory 1678604 kb
Host smart-dff16f33-04e0-40e0-9c9c-e47d2d1fb7a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440858154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.1440858154
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.4255476177
Short name T595
Test name
Test status
Simulation time 23830932871 ps
CPU time 1306.64 seconds
Started Apr 30 01:55:38 PM PDT 24
Finished Apr 30 02:17:26 PM PDT 24
Peak memory 5683716 kb
Host smart-b49458d5-01de-4dfd-a626-9974359fd80f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255476177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.4255476177
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.3325044885
Short name T1102
Test name
Test status
Simulation time 4637362660 ps
CPU time 6.49 seconds
Started Apr 30 01:55:38 PM PDT 24
Finished Apr 30 01:55:46 PM PDT 24
Peak memory 217328 kb
Host smart-58aa15d5-036d-40d7-a885-5d6aecd6d6d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325044885 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.3325044885
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.3884777767
Short name T440
Test name
Test status
Simulation time 34804592 ps
CPU time 0.63 seconds
Started Apr 30 01:52:54 PM PDT 24
Finished Apr 30 01:52:55 PM PDT 24
Peak memory 203896 kb
Host smart-3145fd01-df21-4742-82f6-eedb3fe75d88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884777767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.3884777767
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.1557416046
Short name T279
Test name
Test status
Simulation time 50182731 ps
CPU time 1.2 seconds
Started Apr 30 01:52:43 PM PDT 24
Finished Apr 30 01:52:45 PM PDT 24
Peak memory 216008 kb
Host smart-ccca0838-7e45-4724-a337-aea5acee6a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557416046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.1557416046
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.307597113
Short name T310
Test name
Test status
Simulation time 647660164 ps
CPU time 8.72 seconds
Started Apr 30 01:52:39 PM PDT 24
Finished Apr 30 01:52:48 PM PDT 24
Peak memory 233012 kb
Host smart-f983bebd-0afd-49e4-a1cf-380d26dfb690
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307597113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty
.307597113
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3441757248
Short name T84
Test name
Test status
Simulation time 3130489528 ps
CPU time 70.27 seconds
Started Apr 30 01:52:46 PM PDT 24
Finished Apr 30 01:53:57 PM PDT 24
Peak memory 743652 kb
Host smart-63f54e0b-a062-4937-8c95-640bdb9d6927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441757248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3441757248
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.441280024
Short name T877
Test name
Test status
Simulation time 17228247339 ps
CPU time 58.93 seconds
Started Apr 30 01:52:43 PM PDT 24
Finished Apr 30 01:53:42 PM PDT 24
Peak memory 649604 kb
Host smart-35d6c5cb-0629-4411-889c-b524e9a5290a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441280024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.441280024
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.190596226
Short name T836
Test name
Test status
Simulation time 129374363 ps
CPU time 1.06 seconds
Started Apr 30 01:52:45 PM PDT 24
Finished Apr 30 01:52:46 PM PDT 24
Peak memory 204004 kb
Host smart-ab9d7a4b-5904-4815-a394-fe3d27f6c948
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190596226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt
.190596226
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.2209660921
Short name T597
Test name
Test status
Simulation time 230094756 ps
CPU time 2.55 seconds
Started Apr 30 01:52:47 PM PDT 24
Finished Apr 30 01:52:50 PM PDT 24
Peak memory 204152 kb
Host smart-30e839ff-bec5-4810-a342-c7c72da9a54e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209660921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
2209660921
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.3576591713
Short name T1104
Test name
Test status
Simulation time 3590286389 ps
CPU time 80.19 seconds
Started Apr 30 01:52:40 PM PDT 24
Finished Apr 30 01:54:01 PM PDT 24
Peak memory 1041516 kb
Host smart-28866e90-871c-4464-b1ce-728c1666034c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576591713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.3576591713
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.2271536594
Short name T820
Test name
Test status
Simulation time 364277765 ps
CPU time 15.66 seconds
Started Apr 30 01:52:48 PM PDT 24
Finished Apr 30 01:53:04 PM PDT 24
Peak memory 204168 kb
Host smart-6c9a0eef-f0a3-4a20-9c3e-46c2dab2886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271536594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.2271536594
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.3163782084
Short name T1291
Test name
Test status
Simulation time 6208511365 ps
CPU time 75.42 seconds
Started Apr 30 01:52:48 PM PDT 24
Finished Apr 30 01:54:04 PM PDT 24
Peak memory 357388 kb
Host smart-2c409545-5e0a-4db1-baab-4fef01c98783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163782084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.3163782084
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.1602293885
Short name T1336
Test name
Test status
Simulation time 63104674 ps
CPU time 0.7 seconds
Started Apr 30 01:52:39 PM PDT 24
Finished Apr 30 01:52:41 PM PDT 24
Peak memory 203760 kb
Host smart-acd7c669-54ab-4897-be54-c049a9a8f5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602293885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.1602293885
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.649342264
Short name T203
Test name
Test status
Simulation time 7484321941 ps
CPU time 255.59 seconds
Started Apr 30 01:52:47 PM PDT 24
Finished Apr 30 01:57:03 PM PDT 24
Peak memory 1310584 kb
Host smart-c2daa178-9695-452a-8153-52adfb0707f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649342264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.649342264
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.1835491705
Short name T436
Test name
Test status
Simulation time 951035042 ps
CPU time 43.54 seconds
Started Apr 30 01:52:39 PM PDT 24
Finished Apr 30 01:53:23 PM PDT 24
Peak memory 277524 kb
Host smart-e1592482-1112-4a45-a523-36010959a434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835491705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1835491705
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.1996469782
Short name T178
Test name
Test status
Simulation time 928851792 ps
CPU time 33.31 seconds
Started Apr 30 01:52:52 PM PDT 24
Finished Apr 30 01:53:25 PM PDT 24
Peak memory 212396 kb
Host smart-532380f1-a610-4a73-b610-fab021c4a2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996469782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.1996469782
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.1864947894
Short name T109
Test name
Test status
Simulation time 76686455 ps
CPU time 0.91 seconds
Started Apr 30 01:52:45 PM PDT 24
Finished Apr 30 01:52:47 PM PDT 24
Peak memory 221496 kb
Host smart-01f627e9-405b-48ed-8ca4-be7c99206d56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864947894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1864947894
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.2057892413
Short name T603
Test name
Test status
Simulation time 3188793665 ps
CPU time 3.66 seconds
Started Apr 30 01:52:47 PM PDT 24
Finished Apr 30 01:52:51 PM PDT 24
Peak memory 204128 kb
Host smart-246d8510-67d0-4c5a-a8c7-359d9b844107
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057892413 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.2057892413
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.3405742667
Short name T86
Test name
Test status
Simulation time 10217170881 ps
CPU time 15.05 seconds
Started Apr 30 01:52:51 PM PDT 24
Finished Apr 30 01:53:07 PM PDT 24
Peak memory 262588 kb
Host smart-e3fe88b3-1f1c-44e6-b603-9399e3d634b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405742667 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.3405742667
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.607578553
Short name T694
Test name
Test status
Simulation time 10068807393 ps
CPU time 15.16 seconds
Started Apr 30 01:52:48 PM PDT 24
Finished Apr 30 01:53:04 PM PDT 24
Peak memory 297168 kb
Host smart-ab3a2044-975e-43a0-aca9-326dc4434408
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607578553 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_fifo_reset_tx.607578553
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.1253884025
Short name T587
Test name
Test status
Simulation time 447064324 ps
CPU time 2.34 seconds
Started Apr 30 01:52:46 PM PDT 24
Finished Apr 30 01:52:49 PM PDT 24
Peak memory 204088 kb
Host smart-73b69925-b2e1-4d4b-9539-9b7766c83c31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253884025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.1253884025
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3417143887
Short name T1124
Test name
Test status
Simulation time 4513978306 ps
CPU time 3.48 seconds
Started Apr 30 01:52:46 PM PDT 24
Finished Apr 30 01:52:50 PM PDT 24
Peak memory 204544 kb
Host smart-1631fed5-289e-4ea9-bf10-8cda06c1f563
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417143887 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3417143887
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.1030868225
Short name T346
Test name
Test status
Simulation time 4516260203 ps
CPU time 5.49 seconds
Started Apr 30 01:52:45 PM PDT 24
Finished Apr 30 01:52:50 PM PDT 24
Peak memory 204320 kb
Host smart-07f7f90d-dc5c-4fea-a955-26a87ba73894
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030868225 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.1030868225
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.1208700051
Short name T828
Test name
Test status
Simulation time 2418423352 ps
CPU time 9.64 seconds
Started Apr 30 01:52:50 PM PDT 24
Finished Apr 30 01:53:00 PM PDT 24
Peak memory 204188 kb
Host smart-ad545393-edc3-4c64-b2c8-2b332889454a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208700051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.1208700051
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.1457947578
Short name T336
Test name
Test status
Simulation time 855480754 ps
CPU time 14.68 seconds
Started Apr 30 01:52:45 PM PDT 24
Finished Apr 30 01:53:00 PM PDT 24
Peak memory 213628 kb
Host smart-4e2aceb0-a53d-48c7-8086-bf62bd1760de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457947578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.1457947578
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.1682084862
Short name T1204
Test name
Test status
Simulation time 9642196191 ps
CPU time 18.27 seconds
Started Apr 30 01:52:52 PM PDT 24
Finished Apr 30 01:53:11 PM PDT 24
Peak memory 204168 kb
Host smart-1900e7d9-dc77-4507-b0d5-b3e61ae9f2c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682084862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.1682084862
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.3497192887
Short name T1042
Test name
Test status
Simulation time 37251687048 ps
CPU time 100.92 seconds
Started Apr 30 01:52:51 PM PDT 24
Finished Apr 30 01:54:32 PM PDT 24
Peak memory 984460 kb
Host smart-4d4dea88-5f5d-414c-83a3-eea78810f0b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497192887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.3497192887
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.1779380039
Short name T1241
Test name
Test status
Simulation time 5546371322 ps
CPU time 6.3 seconds
Started Apr 30 01:52:53 PM PDT 24
Finished Apr 30 01:53:00 PM PDT 24
Peak memory 212396 kb
Host smart-7dab1747-14b2-43cb-9698-30bb2778816f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779380039 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.1779380039
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_unexp_stop.685812717
Short name T222
Test name
Test status
Simulation time 2610136218 ps
CPU time 3.24 seconds
Started Apr 30 01:52:51 PM PDT 24
Finished Apr 30 01:52:55 PM PDT 24
Peak memory 204268 kb
Host smart-e9cc1b7c-5f98-4a1c-a190-b95f0aa12c27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685812717 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_unexp_stop.685812717
Directory /workspace/3.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/30.i2c_alert_test.2892046257
Short name T904
Test name
Test status
Simulation time 122427503 ps
CPU time 0.61 seconds
Started Apr 30 01:55:53 PM PDT 24
Finished Apr 30 01:55:54 PM PDT 24
Peak memory 203868 kb
Host smart-a65ad934-ad51-4b6b-8e8f-34b0fd7be3a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892046257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.2892046257
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.1786548587
Short name T573
Test name
Test status
Simulation time 137868738 ps
CPU time 1.27 seconds
Started Apr 30 01:55:48 PM PDT 24
Finished Apr 30 01:55:49 PM PDT 24
Peak memory 212504 kb
Host smart-1f552ba3-83c8-41db-b605-9da556209244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786548587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.1786548587
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.3665319420
Short name T886
Test name
Test status
Simulation time 657327332 ps
CPU time 8.47 seconds
Started Apr 30 01:55:46 PM PDT 24
Finished Apr 30 01:55:56 PM PDT 24
Peak memory 233368 kb
Host smart-61a7f080-569f-42c6-8c9e-74d7945d22b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665319420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.3665319420
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.3757077684
Short name T970
Test name
Test status
Simulation time 16656132459 ps
CPU time 97.2 seconds
Started Apr 30 01:55:48 PM PDT 24
Finished Apr 30 01:57:26 PM PDT 24
Peak memory 505548 kb
Host smart-00aa5504-79e5-4260-b767-0be3fcf006df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757077684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.3757077684
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.2960935858
Short name T432
Test name
Test status
Simulation time 8077577411 ps
CPU time 154.28 seconds
Started Apr 30 01:55:47 PM PDT 24
Finished Apr 30 01:58:22 PM PDT 24
Peak memory 678292 kb
Host smart-54ec530e-fccc-4537-a9e1-f00a2e90ac0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960935858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.2960935858
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.2506975006
Short name T1215
Test name
Test status
Simulation time 548292756 ps
CPU time 3.24 seconds
Started Apr 30 01:55:48 PM PDT 24
Finished Apr 30 01:55:52 PM PDT 24
Peak memory 225208 kb
Host smart-3138daea-046c-4379-9b2b-610d4ed33b4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506975006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.2506975006
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.2844259374
Short name T743
Test name
Test status
Simulation time 15990842501 ps
CPU time 53.79 seconds
Started Apr 30 01:55:49 PM PDT 24
Finished Apr 30 01:56:43 PM PDT 24
Peak memory 764592 kb
Host smart-0e1f8291-8e0e-4c6a-aec5-6411f59fef2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844259374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.2844259374
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.371357617
Short name T69
Test name
Test status
Simulation time 680452817 ps
CPU time 10.62 seconds
Started Apr 30 01:55:50 PM PDT 24
Finished Apr 30 01:56:02 PM PDT 24
Peak memory 204172 kb
Host smart-91e48f8e-b742-47cf-b3b3-599776e0da5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371357617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.371357617
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.1764118668
Short name T444
Test name
Test status
Simulation time 1474204630 ps
CPU time 30 seconds
Started Apr 30 01:55:50 PM PDT 24
Finished Apr 30 01:56:21 PM PDT 24
Peak memory 367456 kb
Host smart-5af0a8ef-5e0f-45bd-b2e0-df0960297753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764118668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.1764118668
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.3724200933
Short name T383
Test name
Test status
Simulation time 28665728 ps
CPU time 0.64 seconds
Started Apr 30 01:55:49 PM PDT 24
Finished Apr 30 01:55:50 PM PDT 24
Peak memory 203824 kb
Host smart-affd3a5e-40ba-4e5a-86aa-3f9ec8b2314f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724200933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3724200933
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.484020994
Short name T639
Test name
Test status
Simulation time 7813163269 ps
CPU time 89.03 seconds
Started Apr 30 01:55:50 PM PDT 24
Finished Apr 30 01:57:20 PM PDT 24
Peak memory 523928 kb
Host smart-3bee2c8a-6912-42e0-9e34-4e09a2f1716f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484020994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.484020994
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.594998889
Short name T99
Test name
Test status
Simulation time 11949026822 ps
CPU time 35.06 seconds
Started Apr 30 01:55:48 PM PDT 24
Finished Apr 30 01:56:24 PM PDT 24
Peak memory 402592 kb
Host smart-4db71ba7-19b0-4c44-b5cf-24c28b6687d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594998889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.594998889
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.2998050423
Short name T619
Test name
Test status
Simulation time 11113497981 ps
CPU time 581.33 seconds
Started Apr 30 01:55:46 PM PDT 24
Finished Apr 30 02:05:28 PM PDT 24
Peak memory 2088640 kb
Host smart-3e7905df-91ee-466c-af2c-27df70edc1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998050423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.2998050423
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.4129725679
Short name T1009
Test name
Test status
Simulation time 1687950049 ps
CPU time 5.03 seconds
Started Apr 30 01:55:47 PM PDT 24
Finished Apr 30 01:55:53 PM PDT 24
Peak memory 212352 kb
Host smart-62dc9850-4723-4ee7-90ad-1af3573e21b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129725679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.4129725679
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.2992723770
Short name T707
Test name
Test status
Simulation time 767878798 ps
CPU time 4.03 seconds
Started Apr 30 01:55:51 PM PDT 24
Finished Apr 30 01:55:56 PM PDT 24
Peak memory 212396 kb
Host smart-c039f260-589d-4d6e-91f3-22710ef28b56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992723770 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.2992723770
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.551292521
Short name T908
Test name
Test status
Simulation time 10057595555 ps
CPU time 29.81 seconds
Started Apr 30 01:55:52 PM PDT 24
Finished Apr 30 01:56:23 PM PDT 24
Peak memory 315520 kb
Host smart-a1ea0262-f582-41c9-b0ee-ebf3ef8fda07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551292521 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_acq.551292521
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.1381290236
Short name T1108
Test name
Test status
Simulation time 10126907772 ps
CPU time 30.02 seconds
Started Apr 30 01:55:51 PM PDT 24
Finished Apr 30 01:56:22 PM PDT 24
Peak memory 333496 kb
Host smart-185c441e-7110-448a-a8b2-cd5f8791831f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381290236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.1381290236
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.1732999285
Short name T418
Test name
Test status
Simulation time 1347787129 ps
CPU time 2.37 seconds
Started Apr 30 01:55:52 PM PDT 24
Finished Apr 30 01:55:55 PM PDT 24
Peak memory 204208 kb
Host smart-8ce32b99-739a-4255-a3d4-d87d1c08a353
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732999285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.1732999285
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.1522603406
Short name T818
Test name
Test status
Simulation time 1904365926 ps
CPU time 5.03 seconds
Started Apr 30 01:55:46 PM PDT 24
Finished Apr 30 01:55:51 PM PDT 24
Peak memory 207228 kb
Host smart-e694240e-1b90-4467-a116-b0024214ecb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522603406 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.1522603406
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.1623782365
Short name T776
Test name
Test status
Simulation time 2779063288 ps
CPU time 21.21 seconds
Started Apr 30 01:55:51 PM PDT 24
Finished Apr 30 01:56:13 PM PDT 24
Peak memory 837392 kb
Host smart-c5161e6d-c8f5-4540-8ac1-beab51901e81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623782365 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.1623782365
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.2135814430
Short name T1096
Test name
Test status
Simulation time 4407073520 ps
CPU time 43.47 seconds
Started Apr 30 01:55:48 PM PDT 24
Finished Apr 30 01:56:32 PM PDT 24
Peak memory 204120 kb
Host smart-4f57aca6-b96f-489f-a1e8-c5c006911add
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135814430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.2135814430
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.4104100717
Short name T727
Test name
Test status
Simulation time 5737365866 ps
CPU time 40.71 seconds
Started Apr 30 01:55:48 PM PDT 24
Finished Apr 30 01:56:29 PM PDT 24
Peak memory 204212 kb
Host smart-d38fe61e-eebd-4022-a883-275fbc60149c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104100717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.4104100717
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.720788304
Short name T1297
Test name
Test status
Simulation time 67906466043 ps
CPU time 108.95 seconds
Started Apr 30 01:55:47 PM PDT 24
Finished Apr 30 01:57:37 PM PDT 24
Peak memory 1347020 kb
Host smart-38c91ddf-389c-4616-9e96-8a455041f734
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720788304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_wr.720788304
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.734637307
Short name T234
Test name
Test status
Simulation time 25933681623 ps
CPU time 727.68 seconds
Started Apr 30 01:55:49 PM PDT 24
Finished Apr 30 02:07:57 PM PDT 24
Peak memory 3134772 kb
Host smart-8383ed30-8311-4daa-9ead-73f550d2907e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734637307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_t
arget_stretch.734637307
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.3624271498
Short name T389
Test name
Test status
Simulation time 5968519005 ps
CPU time 7.18 seconds
Started Apr 30 01:55:53 PM PDT 24
Finished Apr 30 01:56:01 PM PDT 24
Peak memory 220416 kb
Host smart-079489fa-4b5f-4dd0-ae9a-7f0ec7da4e62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624271498 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.3624271498
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.672669173
Short name T104
Test name
Test status
Simulation time 27489058 ps
CPU time 0.65 seconds
Started Apr 30 01:56:03 PM PDT 24
Finished Apr 30 01:56:04 PM PDT 24
Peak memory 203888 kb
Host smart-72b8f1fb-9446-4dca-8259-e7e58955275e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672669173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.672669173
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.509023653
Short name T1319
Test name
Test status
Simulation time 126025047 ps
CPU time 2.14 seconds
Started Apr 30 01:55:51 PM PDT 24
Finished Apr 30 01:55:54 PM PDT 24
Peak memory 212416 kb
Host smart-5f4dcdcc-4df2-4846-a19b-6f1c5f4fe81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509023653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.509023653
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.1952851940
Short name T821
Test name
Test status
Simulation time 188033051 ps
CPU time 2.05 seconds
Started Apr 30 01:55:51 PM PDT 24
Finished Apr 30 01:55:54 PM PDT 24
Peak memory 217328 kb
Host smart-f0502034-0ed1-4cb7-abef-01b967964ae9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952851940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.1952851940
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.1206179351
Short name T1052
Test name
Test status
Simulation time 19978545960 ps
CPU time 107.43 seconds
Started Apr 30 01:55:56 PM PDT 24
Finished Apr 30 01:57:44 PM PDT 24
Peak memory 477316 kb
Host smart-6217af5d-7513-4c1d-8cd2-859f8a8b0d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206179351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.1206179351
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.2394491435
Short name T771
Test name
Test status
Simulation time 5240283921 ps
CPU time 30.3 seconds
Started Apr 30 01:55:51 PM PDT 24
Finished Apr 30 01:56:22 PM PDT 24
Peak memory 402752 kb
Host smart-b85e8ec9-ccdd-4467-a79f-3a1bffe2a1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394491435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.2394491435
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.2380851380
Short name T379
Test name
Test status
Simulation time 602426068 ps
CPU time 0.93 seconds
Started Apr 30 01:55:56 PM PDT 24
Finished Apr 30 01:55:57 PM PDT 24
Peak memory 203908 kb
Host smart-2bb17917-32d9-434c-a3af-a7c0ff583afc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380851380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.2380851380
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.1260496958
Short name T1328
Test name
Test status
Simulation time 201362471 ps
CPU time 2.67 seconds
Started Apr 30 01:55:53 PM PDT 24
Finished Apr 30 01:55:56 PM PDT 24
Peak memory 204388 kb
Host smart-e2f144a8-9952-4464-b182-4bcbf1182585
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260496958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.1260496958
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.602523547
Short name T1087
Test name
Test status
Simulation time 43284981177 ps
CPU time 103.75 seconds
Started Apr 30 01:55:53 PM PDT 24
Finished Apr 30 01:57:37 PM PDT 24
Peak memory 1009964 kb
Host smart-1ad1b2c1-60c6-4573-92d9-6bd2eed0643a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602523547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.602523547
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.2161407640
Short name T1101
Test name
Test status
Simulation time 536990270 ps
CPU time 22.07 seconds
Started Apr 30 01:56:03 PM PDT 24
Finished Apr 30 01:56:26 PM PDT 24
Peak memory 204132 kb
Host smart-84c44ccf-602d-4708-b9ab-9e57dc49fcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161407640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2161407640
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.3053536297
Short name T884
Test name
Test status
Simulation time 1616456888 ps
CPU time 35.73 seconds
Started Apr 30 01:56:01 PM PDT 24
Finished Apr 30 01:56:37 PM PDT 24
Peak memory 405788 kb
Host smart-2f0317f8-c8e5-479d-9281-e74b832fab03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053536297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.3053536297
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.1079130855
Short name T922
Test name
Test status
Simulation time 96789881 ps
CPU time 0.63 seconds
Started Apr 30 01:55:51 PM PDT 24
Finished Apr 30 01:55:52 PM PDT 24
Peak memory 203848 kb
Host smart-4ddac88b-558d-4b1c-909b-7f9e935191b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079130855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1079130855
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.4020084211
Short name T782
Test name
Test status
Simulation time 1030092331 ps
CPU time 16.33 seconds
Started Apr 30 01:55:56 PM PDT 24
Finished Apr 30 01:56:13 PM PDT 24
Peak memory 280576 kb
Host smart-e740888c-3c6c-4960-80dc-b79cf8776d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020084211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.4020084211
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.2346145222
Short name T859
Test name
Test status
Simulation time 40406245663 ps
CPU time 503.45 seconds
Started Apr 30 01:55:53 PM PDT 24
Finished Apr 30 02:04:17 PM PDT 24
Peak memory 2406052 kb
Host smart-54af5874-1479-4eed-8f26-ae7976b45d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346145222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.2346145222
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.1638901379
Short name T1171
Test name
Test status
Simulation time 3146096800 ps
CPU time 11.9 seconds
Started Apr 30 01:55:54 PM PDT 24
Finished Apr 30 01:56:06 PM PDT 24
Peak memory 216976 kb
Host smart-61f5011c-96e3-45b8-8187-189f25b76788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638901379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1638901379
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.1936669104
Short name T562
Test name
Test status
Simulation time 2018650689 ps
CPU time 4.96 seconds
Started Apr 30 01:56:02 PM PDT 24
Finished Apr 30 01:56:07 PM PDT 24
Peak memory 212604 kb
Host smart-98b85ef8-dd63-47f7-87e5-68e2770f72c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936669104 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.1936669104
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.842507724
Short name T114
Test name
Test status
Simulation time 10104393329 ps
CPU time 73.09 seconds
Started Apr 30 01:56:03 PM PDT 24
Finished Apr 30 01:57:17 PM PDT 24
Peak memory 512504 kb
Host smart-8ab8b42e-c681-4b45-a0cb-f927e7bceb58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842507724 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_acq.842507724
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.359056927
Short name T641
Test name
Test status
Simulation time 10113936607 ps
CPU time 72.41 seconds
Started Apr 30 01:56:03 PM PDT 24
Finished Apr 30 01:57:16 PM PDT 24
Peak memory 531752 kb
Host smart-0f29088c-24f3-46bc-badf-d6222826bfda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359056927 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.i2c_target_fifo_reset_tx.359056927
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.1099579198
Short name T753
Test name
Test status
Simulation time 1915725004 ps
CPU time 2.84 seconds
Started Apr 30 01:56:01 PM PDT 24
Finished Apr 30 01:56:04 PM PDT 24
Peak memory 204152 kb
Host smart-4af99a50-25f8-48f7-bb08-370ebe6fa489
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099579198 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.1099579198
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.2951827006
Short name T237
Test name
Test status
Simulation time 5185718040 ps
CPU time 4.23 seconds
Started Apr 30 01:56:02 PM PDT 24
Finished Apr 30 01:56:07 PM PDT 24
Peak memory 207100 kb
Host smart-f5ee11d0-24fd-4f23-bef1-a7bd2f21e1cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951827006 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.2951827006
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.3429391369
Short name T957
Test name
Test status
Simulation time 22118535139 ps
CPU time 58.07 seconds
Started Apr 30 01:56:01 PM PDT 24
Finished Apr 30 01:57:00 PM PDT 24
Peak memory 1235600 kb
Host smart-bbf29056-672b-4698-abcb-185859464106
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429391369 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.3429391369
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.814404622
Short name T835
Test name
Test status
Simulation time 1047984024 ps
CPU time 7.52 seconds
Started Apr 30 01:56:00 PM PDT 24
Finished Apr 30 01:56:08 PM PDT 24
Peak memory 204064 kb
Host smart-654121ab-6c87-41c7-b7d0-8d49abb9aecc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814404622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_tar
get_smoke.814404622
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.90354562
Short name T1283
Test name
Test status
Simulation time 3739496334 ps
CPU time 33.71 seconds
Started Apr 30 01:56:00 PM PDT 24
Finished Apr 30 01:56:34 PM PDT 24
Peak memory 226592 kb
Host smart-89a6e5ac-b8c6-486b-b608-3fef2ba0527f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90354562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stress_rd.90354562
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.2559176464
Short name T1346
Test name
Test status
Simulation time 60517938985 ps
CPU time 1050.94 seconds
Started Apr 30 01:56:00 PM PDT 24
Finished Apr 30 02:13:32 PM PDT 24
Peak memory 7124480 kb
Host smart-e35cec4e-23ce-4788-a5b3-9510ef5118f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559176464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.2559176464
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.3266557987
Short name T725
Test name
Test status
Simulation time 4729642487 ps
CPU time 5.2 seconds
Started Apr 30 01:56:01 PM PDT 24
Finished Apr 30 01:56:07 PM PDT 24
Peak memory 229712 kb
Host smart-d98c2df3-9850-4698-872a-f96036d90a58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266557987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.3266557987
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.4163857177
Short name T654
Test name
Test status
Simulation time 1151694675 ps
CPU time 6.31 seconds
Started Apr 30 01:56:00 PM PDT 24
Finished Apr 30 01:56:07 PM PDT 24
Peak memory 220380 kb
Host smart-0f7ce448-a69c-4c7d-986a-e73c215bd9be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163857177 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.4163857177
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.2034241541
Short name T1180
Test name
Test status
Simulation time 44220689 ps
CPU time 0.61 seconds
Started Apr 30 01:56:11 PM PDT 24
Finished Apr 30 01:56:12 PM PDT 24
Peak memory 203856 kb
Host smart-57d5013d-d63a-44af-9b05-a06e2236a30f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034241541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.2034241541
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.1796467851
Short name T424
Test name
Test status
Simulation time 454791817 ps
CPU time 1.31 seconds
Started Apr 30 01:56:05 PM PDT 24
Finished Apr 30 01:56:07 PM PDT 24
Peak memory 212404 kb
Host smart-08279f28-8b5a-4697-b027-291f82390412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796467851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.1796467851
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.744809514
Short name T289
Test name
Test status
Simulation time 715958967 ps
CPU time 4.12 seconds
Started Apr 30 01:56:03 PM PDT 24
Finished Apr 30 01:56:08 PM PDT 24
Peak memory 235712 kb
Host smart-1675f696-f340-4bc6-9b1b-910aa5582d91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744809514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empt
y.744809514
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.518451251
Short name T826
Test name
Test status
Simulation time 1090300123 ps
CPU time 20.99 seconds
Started Apr 30 01:56:03 PM PDT 24
Finished Apr 30 01:56:25 PM PDT 24
Peak memory 220568 kb
Host smart-64d8bde3-41a8-476c-83ed-c6f256a6588e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518451251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.518451251
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.495632308
Short name T393
Test name
Test status
Simulation time 2302887659 ps
CPU time 72.84 seconds
Started Apr 30 01:56:08 PM PDT 24
Finished Apr 30 01:57:21 PM PDT 24
Peak memory 766040 kb
Host smart-fd5d8d2a-42b7-439e-93a5-44a52711463e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495632308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.495632308
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.3085150037
Short name T287
Test name
Test status
Simulation time 96048416 ps
CPU time 0.93 seconds
Started Apr 30 01:56:07 PM PDT 24
Finished Apr 30 01:56:09 PM PDT 24
Peak memory 203932 kb
Host smart-683a3645-a426-4b0e-8e3f-886bb3e675d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085150037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.3085150037
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.3726532833
Short name T451
Test name
Test status
Simulation time 180687854 ps
CPU time 8.73 seconds
Started Apr 30 01:56:04 PM PDT 24
Finished Apr 30 01:56:14 PM PDT 24
Peak memory 204180 kb
Host smart-26ea9e47-0692-41b9-98aa-8959f77db641
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726532833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.3726532833
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2679669982
Short name T247
Test name
Test status
Simulation time 6996714829 ps
CPU time 242.35 seconds
Started Apr 30 01:56:03 PM PDT 24
Finished Apr 30 02:00:06 PM PDT 24
Peak memory 980356 kb
Host smart-076da88d-0d46-4a59-97ce-aaf10c84a501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679669982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2679669982
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.408717790
Short name T1226
Test name
Test status
Simulation time 893137905 ps
CPU time 5.43 seconds
Started Apr 30 01:56:13 PM PDT 24
Finished Apr 30 01:56:19 PM PDT 24
Peak memory 204220 kb
Host smart-39aa006d-e470-40ba-8017-2e9f17355d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408717790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.408717790
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.3364498079
Short name T351
Test name
Test status
Simulation time 1160976619 ps
CPU time 54.6 seconds
Started Apr 30 01:56:11 PM PDT 24
Finished Apr 30 01:57:06 PM PDT 24
Peak memory 260664 kb
Host smart-e5d85b94-e2ad-4e81-955d-006d556bdd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364498079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.3364498079
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.1079557457
Short name T814
Test name
Test status
Simulation time 93811879 ps
CPU time 0.64 seconds
Started Apr 30 01:56:06 PM PDT 24
Finished Apr 30 01:56:07 PM PDT 24
Peak memory 203800 kb
Host smart-eb37f049-ba1b-4ea7-aec6-d75594ecfe24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079557457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.1079557457
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1017317353
Short name T205
Test name
Test status
Simulation time 5645895443 ps
CPU time 40.49 seconds
Started Apr 30 01:56:04 PM PDT 24
Finished Apr 30 01:56:45 PM PDT 24
Peak memory 212456 kb
Host smart-06d36709-7a20-46dc-9629-42d56369f694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017317353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1017317353
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.366173980
Short name T1207
Test name
Test status
Simulation time 1860502723 ps
CPU time 38.91 seconds
Started Apr 30 01:56:04 PM PDT 24
Finished Apr 30 01:56:43 PM PDT 24
Peak memory 372488 kb
Host smart-5d9f1f23-69d2-4239-867a-e67e8a092b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366173980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.366173980
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.1523214070
Short name T1138
Test name
Test status
Simulation time 19304455840 ps
CPU time 951.48 seconds
Started Apr 30 01:56:02 PM PDT 24
Finished Apr 30 02:11:54 PM PDT 24
Peak memory 2787020 kb
Host smart-be289206-3905-409c-a537-c17a38102cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523214070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.1523214070
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.4060736719
Short name T1140
Test name
Test status
Simulation time 576121970 ps
CPU time 10.66 seconds
Started Apr 30 01:56:06 PM PDT 24
Finished Apr 30 01:56:17 PM PDT 24
Peak memory 213852 kb
Host smart-5c8516d2-fbaf-4ffd-aaae-29a91ab90976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060736719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.4060736719
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.1681751565
Short name T563
Test name
Test status
Simulation time 1637245858 ps
CPU time 3.01 seconds
Started Apr 30 01:56:07 PM PDT 24
Finished Apr 30 01:56:11 PM PDT 24
Peak memory 204208 kb
Host smart-276fe50c-3007-45ff-be05-1fbaea6b1dac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681751565 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.1681751565
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.1200864765
Short name T411
Test name
Test status
Simulation time 10229517524 ps
CPU time 33.62 seconds
Started Apr 30 01:56:06 PM PDT 24
Finished Apr 30 01:56:40 PM PDT 24
Peak memory 326868 kb
Host smart-5e7cc67a-5373-4d40-b40c-5ea4417a20b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200864765 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.1200864765
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.550520360
Short name T1205
Test name
Test status
Simulation time 10091139892 ps
CPU time 74.61 seconds
Started Apr 30 01:56:08 PM PDT 24
Finished Apr 30 01:57:23 PM PDT 24
Peak memory 571200 kb
Host smart-cc410e1e-dd90-482d-abdd-823cb315ae9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550520360 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_fifo_reset_tx.550520360
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3261781588
Short name T16
Test name
Test status
Simulation time 387720129 ps
CPU time 2.42 seconds
Started Apr 30 01:56:08 PM PDT 24
Finished Apr 30 01:56:11 PM PDT 24
Peak memory 204192 kb
Host smart-0aa82451-4c29-41a6-9e64-619016cea0c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261781588 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3261781588
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.3529841039
Short name T652
Test name
Test status
Simulation time 1048130992 ps
CPU time 5.4 seconds
Started Apr 30 01:56:06 PM PDT 24
Finished Apr 30 01:56:13 PM PDT 24
Peak memory 220444 kb
Host smart-223c4edf-fa92-4bb7-bf0d-3f66c6ecf4b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529841039 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.3529841039
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.1664120857
Short name T456
Test name
Test status
Simulation time 14953491465 ps
CPU time 32.27 seconds
Started Apr 30 01:56:07 PM PDT 24
Finished Apr 30 01:56:40 PM PDT 24
Peak memory 688520 kb
Host smart-8986c879-0226-46e1-8cdf-c6318e792000
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664120857 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.1664120857
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.159884857
Short name T729
Test name
Test status
Simulation time 3745379433 ps
CPU time 32.68 seconds
Started Apr 30 01:56:07 PM PDT 24
Finished Apr 30 01:56:40 PM PDT 24
Peak memory 204236 kb
Host smart-831025c1-c8bd-47d4-928f-51ef78fe2120
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159884857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_tar
get_smoke.159884857
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.1857753845
Short name T611
Test name
Test status
Simulation time 426951791 ps
CPU time 17.82 seconds
Started Apr 30 01:56:07 PM PDT 24
Finished Apr 30 01:56:25 PM PDT 24
Peak memory 204056 kb
Host smart-7cff6184-d5d3-4033-bc63-385cc3516890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857753845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.1857753845
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.3013921737
Short name T936
Test name
Test status
Simulation time 58212272275 ps
CPU time 1838.78 seconds
Started Apr 30 01:56:02 PM PDT 24
Finished Apr 30 02:26:42 PM PDT 24
Peak memory 9876092 kb
Host smart-31f5f0ba-4b33-418e-aa19-bb9aaff6abcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013921737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.3013921737
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.891775576
Short name T1358
Test name
Test status
Simulation time 2158848960 ps
CPU time 6.16 seconds
Started Apr 30 01:56:04 PM PDT 24
Finished Apr 30 01:56:11 PM PDT 24
Peak memory 212472 kb
Host smart-ebcaa4f7-5c0d-47d1-be25-27ace8eb8123
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891775576 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_timeout.891775576
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.365947328
Short name T1005
Test name
Test status
Simulation time 17672840 ps
CPU time 0.62 seconds
Started Apr 30 01:56:15 PM PDT 24
Finished Apr 30 01:56:16 PM PDT 24
Peak memory 203888 kb
Host smart-10b2642e-2d63-42ca-a11f-c294abb78e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365947328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.365947328
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.2844577577
Short name T92
Test name
Test status
Simulation time 166683113 ps
CPU time 1.73 seconds
Started Apr 30 01:56:15 PM PDT 24
Finished Apr 30 01:56:17 PM PDT 24
Peak memory 212448 kb
Host smart-d110a49a-9f1e-4053-8567-6c0f11aeaeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844577577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.2844577577
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.444322859
Short name T1142
Test name
Test status
Simulation time 348348700 ps
CPU time 3.6 seconds
Started Apr 30 01:56:13 PM PDT 24
Finished Apr 30 01:56:17 PM PDT 24
Peak memory 236256 kb
Host smart-fbdbad0a-4fec-48a8-8e49-c3dd668d1d5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444322859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empt
y.444322859
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.741453388
Short name T929
Test name
Test status
Simulation time 4877525484 ps
CPU time 193.1 seconds
Started Apr 30 01:56:09 PM PDT 24
Finished Apr 30 01:59:23 PM PDT 24
Peak memory 800604 kb
Host smart-a403050f-d4bc-4ba8-ab62-cb6322e4c3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741453388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.741453388
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.1374153325
Short name T648
Test name
Test status
Simulation time 1260943868 ps
CPU time 79.14 seconds
Started Apr 30 01:56:12 PM PDT 24
Finished Apr 30 01:57:32 PM PDT 24
Peak memory 458616 kb
Host smart-d63f6cf2-68e6-4c8e-af6a-51edae6b8da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374153325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.1374153325
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.385993135
Short name T876
Test name
Test status
Simulation time 402965581 ps
CPU time 1.09 seconds
Started Apr 30 01:56:09 PM PDT 24
Finished Apr 30 01:56:11 PM PDT 24
Peak memory 204128 kb
Host smart-50b9b50b-774f-4faf-83b5-1b33ab615b1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385993135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fm
t.385993135
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.2550350279
Short name T974
Test name
Test status
Simulation time 133502244 ps
CPU time 6.61 seconds
Started Apr 30 01:56:13 PM PDT 24
Finished Apr 30 01:56:20 PM PDT 24
Peak memory 204144 kb
Host smart-fb37abbe-5707-4da6-bcd7-c26a088a70f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550350279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.2550350279
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.531745165
Short name T246
Test name
Test status
Simulation time 3964719432 ps
CPU time 300.15 seconds
Started Apr 30 01:56:09 PM PDT 24
Finished Apr 30 02:01:10 PM PDT 24
Peak memory 1190892 kb
Host smart-c2ea2cf3-cd22-44b5-bb20-16ec61352384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531745165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.531745165
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.861285649
Short name T834
Test name
Test status
Simulation time 859132221 ps
CPU time 17.56 seconds
Started Apr 30 01:56:15 PM PDT 24
Finished Apr 30 01:56:34 PM PDT 24
Peak memory 204076 kb
Host smart-7eb24a07-f1bc-4c3a-94fd-3a2cc5ef2ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861285649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.861285649
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1440644980
Short name T1245
Test name
Test status
Simulation time 1378058498 ps
CPU time 67.64 seconds
Started Apr 30 01:56:16 PM PDT 24
Finished Apr 30 01:57:24 PM PDT 24
Peak memory 335404 kb
Host smart-77d8edf8-05f4-4fb0-bab1-eefa7b82b7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440644980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1440644980
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.2908900868
Short name T193
Test name
Test status
Simulation time 92935539 ps
CPU time 0.64 seconds
Started Apr 30 01:56:10 PM PDT 24
Finished Apr 30 01:56:11 PM PDT 24
Peak memory 203768 kb
Host smart-326caabc-8b6f-4253-991e-c11919f7e829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908900868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.2908900868
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.210510852
Short name T339
Test name
Test status
Simulation time 2788020261 ps
CPU time 51.97 seconds
Started Apr 30 01:56:09 PM PDT 24
Finished Apr 30 01:57:02 PM PDT 24
Peak memory 609732 kb
Host smart-d4177f38-707f-4c67-bd07-6f078ff41850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210510852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.210510852
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.2751052794
Short name T1027
Test name
Test status
Simulation time 15481269475 ps
CPU time 23.86 seconds
Started Apr 30 01:56:09 PM PDT 24
Finished Apr 30 01:56:33 PM PDT 24
Peak memory 306528 kb
Host smart-d69ef377-434d-409c-b1de-fdf3661ce6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751052794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2751052794
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.2355677987
Short name T1257
Test name
Test status
Simulation time 816571101 ps
CPU time 38.45 seconds
Started Apr 30 01:56:15 PM PDT 24
Finished Apr 30 01:56:53 PM PDT 24
Peak memory 212364 kb
Host smart-0fd6870d-b90e-4bac-8116-fe6783de2d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355677987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.2355677987
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.1050302487
Short name T1116
Test name
Test status
Simulation time 9557200170 ps
CPU time 3.57 seconds
Started Apr 30 01:56:13 PM PDT 24
Finished Apr 30 01:56:17 PM PDT 24
Peak memory 204308 kb
Host smart-a05d5b55-0005-4458-ae12-d58dc2548217
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050302487 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.1050302487
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.2016953744
Short name T387
Test name
Test status
Simulation time 10130080342 ps
CPU time 73.82 seconds
Started Apr 30 01:56:16 PM PDT 24
Finished Apr 30 01:57:30 PM PDT 24
Peak memory 523028 kb
Host smart-2ea7b412-1728-456a-bd7a-964893718f4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016953744 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.2016953744
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.3494851374
Short name T300
Test name
Test status
Simulation time 10115919524 ps
CPU time 69.73 seconds
Started Apr 30 01:56:15 PM PDT 24
Finished Apr 30 01:57:25 PM PDT 24
Peak memory 468676 kb
Host smart-3e40ab88-2797-4a36-b07a-e35facef0513
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494851374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.3494851374
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.3527151720
Short name T810
Test name
Test status
Simulation time 432285833 ps
CPU time 2.44 seconds
Started Apr 30 01:56:18 PM PDT 24
Finished Apr 30 01:56:21 PM PDT 24
Peak memory 204184 kb
Host smart-1830db55-a0bf-4add-8d08-01e44c7a86d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527151720 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.3527151720
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.2357854482
Short name T257
Test name
Test status
Simulation time 979023477 ps
CPU time 4.66 seconds
Started Apr 30 01:56:16 PM PDT 24
Finished Apr 30 01:56:21 PM PDT 24
Peak memory 204208 kb
Host smart-e6676043-deb9-452d-b1a5-aaf40e44daf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357854482 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.2357854482
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.895880448
Short name T1330
Test name
Test status
Simulation time 18350546132 ps
CPU time 109.75 seconds
Started Apr 30 01:56:14 PM PDT 24
Finished Apr 30 01:58:04 PM PDT 24
Peak memory 1580860 kb
Host smart-e371f51d-2da4-4ad8-a864-3abe9d5eead7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895880448 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.895880448
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.1914101583
Short name T1078
Test name
Test status
Simulation time 799904680 ps
CPU time 12.41 seconds
Started Apr 30 01:56:17 PM PDT 24
Finished Apr 30 01:56:30 PM PDT 24
Peak memory 204176 kb
Host smart-74815121-eebd-4593-aa73-a1b79dc58018
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914101583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.1914101583
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.207611079
Short name T228
Test name
Test status
Simulation time 2898188211 ps
CPU time 31.6 seconds
Started Apr 30 01:56:14 PM PDT 24
Finished Apr 30 01:56:46 PM PDT 24
Peak memory 204172 kb
Host smart-97216471-cecb-4501-80d3-b45518358cd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207611079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_rd.207611079
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.89621531
Short name T924
Test name
Test status
Simulation time 36719804521 ps
CPU time 171.05 seconds
Started Apr 30 01:56:15 PM PDT 24
Finished Apr 30 01:59:07 PM PDT 24
Peak memory 2144400 kb
Host smart-0fcb447e-8167-48ab-afba-a5067c583005
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89621531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stress_wr.89621531
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.4082482200
Short name T789
Test name
Test status
Simulation time 6343868970 ps
CPU time 128.49 seconds
Started Apr 30 01:56:16 PM PDT 24
Finished Apr 30 01:58:25 PM PDT 24
Peak memory 693028 kb
Host smart-d8465d95-bc00-433a-967a-45ffae174101
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082482200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.4082482200
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.2017981109
Short name T301
Test name
Test status
Simulation time 5255869949 ps
CPU time 6.13 seconds
Started Apr 30 01:56:17 PM PDT 24
Finished Apr 30 01:56:23 PM PDT 24
Peak memory 208972 kb
Host smart-81e21e8b-ad34-47fa-82dd-9cadf60c84f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017981109 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.2017981109
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.2161134445
Short name T1351
Test name
Test status
Simulation time 53619413 ps
CPU time 0.6 seconds
Started Apr 30 01:56:27 PM PDT 24
Finished Apr 30 01:56:28 PM PDT 24
Peak memory 203888 kb
Host smart-77249b9f-2041-4cd9-b1ac-48d292db08df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161134445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.2161134445
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.2514530872
Short name T232
Test name
Test status
Simulation time 67676828 ps
CPU time 1.35 seconds
Started Apr 30 01:56:22 PM PDT 24
Finished Apr 30 01:56:24 PM PDT 24
Peak memory 212408 kb
Host smart-684923c2-77bb-4117-a706-ceb71d544dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514530872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.2514530872
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.3253949864
Short name T1208
Test name
Test status
Simulation time 803745767 ps
CPU time 4.62 seconds
Started Apr 30 01:56:20 PM PDT 24
Finished Apr 30 01:56:25 PM PDT 24
Peak memory 241248 kb
Host smart-3b245a7d-630a-4a3f-89d3-8de121a75893
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253949864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.3253949864
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.2050626978
Short name T717
Test name
Test status
Simulation time 1958730215 ps
CPU time 55.3 seconds
Started Apr 30 01:56:21 PM PDT 24
Finished Apr 30 01:57:17 PM PDT 24
Peak memory 611584 kb
Host smart-bc55a850-93e5-4391-937c-32d19c0d6945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050626978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.2050626978
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.3762402352
Short name T617
Test name
Test status
Simulation time 8654385375 ps
CPU time 65.21 seconds
Started Apr 30 01:56:15 PM PDT 24
Finished Apr 30 01:57:21 PM PDT 24
Peak memory 719208 kb
Host smart-fa320f2d-ae45-42fc-b1a6-7931d19fa422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762402352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3762402352
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3759630873
Short name T73
Test name
Test status
Simulation time 165033463 ps
CPU time 0.98 seconds
Started Apr 30 01:56:14 PM PDT 24
Finished Apr 30 01:56:16 PM PDT 24
Peak memory 203980 kb
Host smart-ba913438-14af-42ed-b2d1-d47a25adacf5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759630873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3759630873
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.3470243151
Short name T1329
Test name
Test status
Simulation time 528217028 ps
CPU time 7.41 seconds
Started Apr 30 01:56:20 PM PDT 24
Finished Apr 30 01:56:28 PM PDT 24
Peak memory 226240 kb
Host smart-907fd4cf-cdbc-4486-8b36-9d42b2114f28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470243151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.3470243151
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2914740102
Short name T460
Test name
Test status
Simulation time 3980534247 ps
CPU time 124.42 seconds
Started Apr 30 01:56:17 PM PDT 24
Finished Apr 30 01:58:22 PM PDT 24
Peak memory 1191880 kb
Host smart-b2644730-8fd6-4228-9135-2604eb528741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914740102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2914740102
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.952522654
Short name T1106
Test name
Test status
Simulation time 315410467 ps
CPU time 4.93 seconds
Started Apr 30 01:56:31 PM PDT 24
Finished Apr 30 01:56:37 PM PDT 24
Peak memory 204212 kb
Host smart-43415fdf-6186-4f27-882c-f7f35734a0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952522654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.952522654
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.3516685305
Short name T626
Test name
Test status
Simulation time 8177339026 ps
CPU time 27.89 seconds
Started Apr 30 01:56:29 PM PDT 24
Finished Apr 30 01:56:57 PM PDT 24
Peak memory 277280 kb
Host smart-5dab897f-0c0c-4ab8-b6a9-86d892049327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516685305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.3516685305
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.1033996711
Short name T192
Test name
Test status
Simulation time 167876710 ps
CPU time 0.7 seconds
Started Apr 30 01:56:19 PM PDT 24
Finished Apr 30 01:56:20 PM PDT 24
Peak memory 203860 kb
Host smart-010e85b5-0bf5-4c5d-8d7d-b051be52d7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033996711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1033996711
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.783966205
Short name T1099
Test name
Test status
Simulation time 4946636103 ps
CPU time 249.27 seconds
Started Apr 30 01:56:20 PM PDT 24
Finished Apr 30 02:00:30 PM PDT 24
Peak memory 773796 kb
Host smart-1e95e2b3-41fd-4982-bc9b-b89faa4f08de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783966205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.783966205
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.179919072
Short name T891
Test name
Test status
Simulation time 7318733841 ps
CPU time 32.79 seconds
Started Apr 30 01:56:19 PM PDT 24
Finished Apr 30 01:56:52 PM PDT 24
Peak memory 414688 kb
Host smart-28c520ee-66e8-4ca4-bf84-bd95f6c740d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179919072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.179919072
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.3998116581
Short name T194
Test name
Test status
Simulation time 7986561446 ps
CPU time 781.05 seconds
Started Apr 30 01:56:19 PM PDT 24
Finished Apr 30 02:09:21 PM PDT 24
Peak memory 1616512 kb
Host smart-95b56926-af97-468e-8126-f132a5574294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998116581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.3998116581
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.1694909959
Short name T1287
Test name
Test status
Simulation time 539066553 ps
CPU time 7.01 seconds
Started Apr 30 01:56:20 PM PDT 24
Finished Apr 30 01:56:27 PM PDT 24
Peak memory 216072 kb
Host smart-ad2b3c7d-5ccf-42e0-8a8c-589fdaf92c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694909959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.1694909959
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.796926744
Short name T405
Test name
Test status
Simulation time 3919021450 ps
CPU time 4.06 seconds
Started Apr 30 01:56:22 PM PDT 24
Finished Apr 30 01:56:27 PM PDT 24
Peak memory 212364 kb
Host smart-cf313059-2bd0-488e-bb53-e94a8ffffd73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796926744 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.796926744
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.260737127
Short name T360
Test name
Test status
Simulation time 10207566379 ps
CPU time 9.68 seconds
Started Apr 30 01:56:21 PM PDT 24
Finished Apr 30 01:56:31 PM PDT 24
Peak memory 244968 kb
Host smart-970b9de1-4abb-416f-b0ce-de5732e7481b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260737127 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_acq.260737127
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.1046699797
Short name T590
Test name
Test status
Simulation time 10042214677 ps
CPU time 75.55 seconds
Started Apr 30 01:56:20 PM PDT 24
Finished Apr 30 01:57:36 PM PDT 24
Peak memory 559184 kb
Host smart-364147c3-af7d-4e46-bea5-d23b6cdfa41d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046699797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.1046699797
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.4224510590
Short name T452
Test name
Test status
Simulation time 288076699 ps
CPU time 2.15 seconds
Started Apr 30 01:56:22 PM PDT 24
Finished Apr 30 01:56:24 PM PDT 24
Peak memory 204056 kb
Host smart-b7968370-8585-43f3-8ac9-48c57de0a74d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224510590 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.4224510590
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.387364820
Short name T807
Test name
Test status
Simulation time 1420796291 ps
CPU time 6.76 seconds
Started Apr 30 01:56:21 PM PDT 24
Finished Apr 30 01:56:29 PM PDT 24
Peak memory 220416 kb
Host smart-295b1616-e679-4df4-9f58-9ad0180bdd7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387364820 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_intr_smoke.387364820
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.1369881864
Short name T330
Test name
Test status
Simulation time 5705975133 ps
CPU time 3.87 seconds
Started Apr 30 01:56:20 PM PDT 24
Finished Apr 30 01:56:25 PM PDT 24
Peak memory 204172 kb
Host smart-9bd02ac5-6906-481e-b3cb-76f53c7e714a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369881864 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.1369881864
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.17457208
Short name T1188
Test name
Test status
Simulation time 5437618906 ps
CPU time 12.31 seconds
Started Apr 30 01:56:24 PM PDT 24
Finished Apr 30 01:56:37 PM PDT 24
Peak memory 204212 kb
Host smart-05bffbba-37ff-452b-999e-5f6fc5b06ce5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17457208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_targ
et_smoke.17457208
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.3472590480
Short name T292
Test name
Test status
Simulation time 15068559949 ps
CPU time 56.88 seconds
Started Apr 30 01:56:25 PM PDT 24
Finished Apr 30 01:57:22 PM PDT 24
Peak memory 207784 kb
Host smart-d031fde9-97bc-4842-9a21-a30d2c0194fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472590480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.3472590480
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.1132683109
Short name T29
Test name
Test status
Simulation time 53496379464 ps
CPU time 119.05 seconds
Started Apr 30 01:56:21 PM PDT 24
Finished Apr 30 01:58:20 PM PDT 24
Peak memory 1637532 kb
Host smart-e3a3cb27-573a-4b52-b58d-f38878d55a48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132683109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.1132683109
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.1072029796
Short name T1063
Test name
Test status
Simulation time 31364703012 ps
CPU time 436.12 seconds
Started Apr 30 01:56:23 PM PDT 24
Finished Apr 30 02:03:39 PM PDT 24
Peak memory 1376536 kb
Host smart-301fec32-61e6-4e04-a96a-2433cb0f11a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072029796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.1072029796
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.4229750464
Short name T1276
Test name
Test status
Simulation time 2537475490 ps
CPU time 6.64 seconds
Started Apr 30 01:56:20 PM PDT 24
Finished Apr 30 01:56:28 PM PDT 24
Peak memory 217808 kb
Host smart-96b8d219-a52a-4684-bb9d-89982b0e35ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229750464 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.4229750464
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2445974821
Short name T672
Test name
Test status
Simulation time 25206971 ps
CPU time 0.63 seconds
Started Apr 30 01:56:32 PM PDT 24
Finished Apr 30 01:56:34 PM PDT 24
Peak memory 203924 kb
Host smart-ff619e46-e977-4805-8e75-e53e9e853dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445974821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2445974821
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.2322903911
Short name T280
Test name
Test status
Simulation time 78773807 ps
CPU time 1.82 seconds
Started Apr 30 01:56:31 PM PDT 24
Finished Apr 30 01:56:34 PM PDT 24
Peak memory 212496 kb
Host smart-c85cee5a-2885-44f8-b820-6637a706030e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322903911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.2322903911
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.3132448462
Short name T481
Test name
Test status
Simulation time 409069851 ps
CPU time 3.87 seconds
Started Apr 30 01:56:31 PM PDT 24
Finished Apr 30 01:56:36 PM PDT 24
Peak memory 241380 kb
Host smart-a57ec155-998e-4ea0-8e3c-34a9bdd58994
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132448462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.3132448462
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.2043955118
Short name T1133
Test name
Test status
Simulation time 1381627067 ps
CPU time 30.87 seconds
Started Apr 30 01:56:33 PM PDT 24
Finished Apr 30 01:57:05 PM PDT 24
Peak memory 325016 kb
Host smart-7dfdbcc9-958d-4734-a58d-a9fb01af7236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043955118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.2043955118
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.2462395398
Short name T88
Test name
Test status
Simulation time 12376605644 ps
CPU time 89.55 seconds
Started Apr 30 01:56:32 PM PDT 24
Finished Apr 30 01:58:03 PM PDT 24
Peak memory 511216 kb
Host smart-6c68142f-3c35-4e41-97e0-b05101fcb7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462395398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2462395398
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.3973155824
Short name T1210
Test name
Test status
Simulation time 87709773 ps
CPU time 0.88 seconds
Started Apr 30 01:56:32 PM PDT 24
Finished Apr 30 01:56:34 PM PDT 24
Peak memory 203944 kb
Host smart-84bf3f9f-273a-43ea-8acc-3704486d5d13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973155824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.3973155824
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.3406440164
Short name T696
Test name
Test status
Simulation time 1795684930 ps
CPU time 10.79 seconds
Started Apr 30 01:56:28 PM PDT 24
Finished Apr 30 01:56:39 PM PDT 24
Peak memory 204172 kb
Host smart-3f3d66af-a1ff-40b4-974a-4790b17f828e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406440164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.3406440164
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.1487234336
Short name T94
Test name
Test status
Simulation time 16609447012 ps
CPU time 105.4 seconds
Started Apr 30 01:56:31 PM PDT 24
Finished Apr 30 01:58:18 PM PDT 24
Peak memory 1197888 kb
Host smart-f1c652ea-40a0-42b3-adf5-67987159d386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487234336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1487234336
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.2438740988
Short name T666
Test name
Test status
Simulation time 1131256038 ps
CPU time 4.22 seconds
Started Apr 30 01:56:33 PM PDT 24
Finished Apr 30 01:56:38 PM PDT 24
Peak memory 204136 kb
Host smart-3a9e7187-62c6-4eec-9d6c-967f52b9319b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438740988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.2438740988
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.1159457545
Short name T475
Test name
Test status
Simulation time 7737591240 ps
CPU time 58.72 seconds
Started Apr 30 01:56:33 PM PDT 24
Finished Apr 30 01:57:32 PM PDT 24
Peak memory 316512 kb
Host smart-b18869d0-fcbe-48d8-8c1b-e78b4598f2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159457545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.1159457545
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.3744190232
Short name T291
Test name
Test status
Simulation time 26961493 ps
CPU time 0.7 seconds
Started Apr 30 01:56:33 PM PDT 24
Finished Apr 30 01:56:34 PM PDT 24
Peak memory 203812 kb
Host smart-bc83b941-b6bb-44dc-aa1c-71db63c3683a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744190232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3744190232
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.553065423
Short name T1353
Test name
Test status
Simulation time 18359211077 ps
CPU time 3351.57 seconds
Started Apr 30 01:56:26 PM PDT 24
Finished Apr 30 02:52:19 PM PDT 24
Peak memory 3016560 kb
Host smart-70c0c702-8e9b-4e4c-895b-c4c9caeefbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553065423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.553065423
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.647958652
Short name T942
Test name
Test status
Simulation time 1453271310 ps
CPU time 22.85 seconds
Started Apr 30 01:56:29 PM PDT 24
Finished Apr 30 01:56:52 PM PDT 24
Peak memory 282568 kb
Host smart-5248e6d4-1226-46a3-bebf-835b4c2fe79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647958652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.647958652
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.2495267243
Short name T1058
Test name
Test status
Simulation time 51787723402 ps
CPU time 1252.31 seconds
Started Apr 30 01:56:29 PM PDT 24
Finished Apr 30 02:17:22 PM PDT 24
Peak memory 2064540 kb
Host smart-edeff037-bc3b-4a67-9ab2-aa4d1891e8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495267243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.2495267243
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.3219462934
Short name T421
Test name
Test status
Simulation time 899527314 ps
CPU time 20.68 seconds
Started Apr 30 01:56:31 PM PDT 24
Finished Apr 30 01:56:52 PM PDT 24
Peak memory 212376 kb
Host smart-e645b92b-f6fd-48ea-94d4-446827576d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219462934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.3219462934
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.463203173
Short name T661
Test name
Test status
Simulation time 3931754885 ps
CPU time 4.66 seconds
Started Apr 30 01:56:33 PM PDT 24
Finished Apr 30 01:56:39 PM PDT 24
Peak memory 212452 kb
Host smart-4411d5c2-eebb-4b2f-99a9-8167bd825933
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463203173 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.463203173
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.1160400186
Short name T545
Test name
Test status
Simulation time 11405945384 ps
CPU time 5.27 seconds
Started Apr 30 01:56:33 PM PDT 24
Finished Apr 30 01:56:40 PM PDT 24
Peak memory 236928 kb
Host smart-b6a19a23-3db7-410f-83e6-e5f47f9c1672
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160400186 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.1160400186
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.260847097
Short name T381
Test name
Test status
Simulation time 10093934911 ps
CPU time 39.77 seconds
Started Apr 30 01:56:34 PM PDT 24
Finished Apr 30 01:57:14 PM PDT 24
Peak memory 429332 kb
Host smart-063f3465-8b5b-47ea-91d0-5d79c8aebc7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260847097 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.260847097
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.2325317103
Short name T24
Test name
Test status
Simulation time 827635505 ps
CPU time 2.51 seconds
Started Apr 30 01:56:34 PM PDT 24
Finished Apr 30 01:56:37 PM PDT 24
Peak memory 204120 kb
Host smart-b034cc81-8d28-48c2-8210-bbaf3d84d2b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325317103 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.2325317103
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.145011274
Short name T412
Test name
Test status
Simulation time 977933074 ps
CPU time 5.38 seconds
Started Apr 30 01:56:27 PM PDT 24
Finished Apr 30 01:56:33 PM PDT 24
Peak memory 212332 kb
Host smart-eae44fa9-d6bc-44f9-bb34-1a7ea1f36e1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145011274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_intr_smoke.145011274
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.451289348
Short name T1286
Test name
Test status
Simulation time 9415484639 ps
CPU time 36.67 seconds
Started Apr 30 01:56:26 PM PDT 24
Finished Apr 30 01:57:03 PM PDT 24
Peak memory 722336 kb
Host smart-57e35cbc-a57c-4190-8f77-77a7efc7617f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451289348 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.451289348
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.3867182160
Short name T101
Test name
Test status
Simulation time 6955453815 ps
CPU time 14.83 seconds
Started Apr 30 01:56:26 PM PDT 24
Finished Apr 30 01:56:41 PM PDT 24
Peak memory 204216 kb
Host smart-84b50a2e-aeb2-42cd-867d-de93a41743f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867182160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.3867182160
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.3243327283
Short name T932
Test name
Test status
Simulation time 7994932217 ps
CPU time 70.89 seconds
Started Apr 30 01:56:31 PM PDT 24
Finished Apr 30 01:57:43 PM PDT 24
Peak memory 208464 kb
Host smart-343b4022-ccda-410e-8c1f-7c18695836a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243327283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.3243327283
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.399645021
Short name T1274
Test name
Test status
Simulation time 19835332980 ps
CPU time 9.98 seconds
Started Apr 30 01:56:26 PM PDT 24
Finished Apr 30 01:56:37 PM PDT 24
Peak memory 204164 kb
Host smart-8e2e64b8-4504-4c29-8595-e5fccf9d938f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399645021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_wr.399645021
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2878595880
Short name T796
Test name
Test status
Simulation time 30536294215 ps
CPU time 656.37 seconds
Started Apr 30 01:56:31 PM PDT 24
Finished Apr 30 02:07:28 PM PDT 24
Peak memory 3593592 kb
Host smart-80e58957-b910-4c6c-bc4d-94b9fd59bf35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878595880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2878595880
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.2610095185
Short name T792
Test name
Test status
Simulation time 6542934184 ps
CPU time 7.37 seconds
Started Apr 30 01:56:32 PM PDT 24
Finished Apr 30 01:56:41 PM PDT 24
Peak memory 212516 kb
Host smart-ac09466e-0341-4d19-81d5-5b415f306649
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610095185 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.2610095185
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_unexp_stop.1309127359
Short name T17
Test name
Test status
Simulation time 4327913500 ps
CPU time 6.15 seconds
Started Apr 30 01:56:33 PM PDT 24
Finished Apr 30 01:56:40 PM PDT 24
Peak memory 204216 kb
Host smart-e33e681d-c54f-49c2-b590-69cc752e1057
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309127359 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.i2c_target_unexp_stop.1309127359
Directory /workspace/35.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2065045927
Short name T277
Test name
Test status
Simulation time 39241098 ps
CPU time 0.59 seconds
Started Apr 30 01:56:46 PM PDT 24
Finished Apr 30 01:56:47 PM PDT 24
Peak memory 203888 kb
Host smart-c38eae6b-d976-4510-96de-8be54a8541ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065045927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2065045927
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.2932295345
Short name T401
Test name
Test status
Simulation time 402023263 ps
CPU time 1.21 seconds
Started Apr 30 01:56:34 PM PDT 24
Finished Apr 30 01:56:36 PM PDT 24
Peak memory 212464 kb
Host smart-84cb74e4-414c-4293-91e2-cadfe57b3963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932295345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.2932295345
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.3351885620
Short name T406
Test name
Test status
Simulation time 3830338970 ps
CPU time 19.39 seconds
Started Apr 30 01:56:34 PM PDT 24
Finished Apr 30 01:56:54 PM PDT 24
Peak memory 283048 kb
Host smart-325748a4-940c-49e6-be0f-083314ed6d3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351885620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.3351885620
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.1554568428
Short name T543
Test name
Test status
Simulation time 1726919521 ps
CPU time 50.85 seconds
Started Apr 30 01:56:33 PM PDT 24
Finished Apr 30 01:57:25 PM PDT 24
Peak memory 401376 kb
Host smart-0b9e796e-7a6b-459b-837f-04749f344e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554568428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.1554568428
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.3407595913
Short name T1144
Test name
Test status
Simulation time 1712330713 ps
CPU time 55.72 seconds
Started Apr 30 01:56:34 PM PDT 24
Finished Apr 30 01:57:30 PM PDT 24
Peak memory 600816 kb
Host smart-5bce44ad-2d46-4d27-b3d6-74e00aafdb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407595913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.3407595913
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.936939959
Short name T1089
Test name
Test status
Simulation time 158387470 ps
CPU time 0.97 seconds
Started Apr 30 01:56:35 PM PDT 24
Finished Apr 30 01:56:37 PM PDT 24
Peak memory 203944 kb
Host smart-57e0781b-a2dc-4f10-8da5-eb4a095af153
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936939959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fm
t.936939959
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.2358857774
Short name T1151
Test name
Test status
Simulation time 327334890 ps
CPU time 3.58 seconds
Started Apr 30 01:56:32 PM PDT 24
Finished Apr 30 01:56:36 PM PDT 24
Peak memory 204128 kb
Host smart-88b2a24f-4f7e-4729-a38f-d47d7d2d44a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358857774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.2358857774
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.1174984509
Short name T164
Test name
Test status
Simulation time 9626628629 ps
CPU time 126.17 seconds
Started Apr 30 01:56:31 PM PDT 24
Finished Apr 30 01:58:39 PM PDT 24
Peak memory 1355644 kb
Host smart-81745f65-e05e-439c-b458-d09543a50f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174984509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.1174984509
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.3868276693
Short name T196
Test name
Test status
Simulation time 284543171 ps
CPU time 4.67 seconds
Started Apr 30 01:56:45 PM PDT 24
Finished Apr 30 01:56:51 PM PDT 24
Peak memory 204100 kb
Host smart-f4eb3620-ed0d-42e5-9a01-b3c277a977b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868276693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.3868276693
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.358236328
Short name T1022
Test name
Test status
Simulation time 2447378545 ps
CPU time 21.23 seconds
Started Apr 30 01:56:40 PM PDT 24
Finished Apr 30 01:57:01 PM PDT 24
Peak memory 306920 kb
Host smart-b3f9f24c-42b1-4b5a-a6c2-429c2b395fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358236328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.358236328
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.2018678256
Short name T1268
Test name
Test status
Simulation time 27844120 ps
CPU time 0.68 seconds
Started Apr 30 01:56:35 PM PDT 24
Finished Apr 30 01:56:36 PM PDT 24
Peak memory 203808 kb
Host smart-903e9cbe-7f5a-43e2-ac85-dcd0a977b0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018678256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.2018678256
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.1203239646
Short name T1341
Test name
Test status
Simulation time 6243461708 ps
CPU time 67.81 seconds
Started Apr 30 01:56:32 PM PDT 24
Finished Apr 30 01:57:41 PM PDT 24
Peak memory 252856 kb
Host smart-fcde1e5d-320f-4448-b9aa-86c4c1258117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203239646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.1203239646
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.358770491
Short name T857
Test name
Test status
Simulation time 3622799504 ps
CPU time 36.37 seconds
Started Apr 30 01:56:33 PM PDT 24
Finished Apr 30 01:57:10 PM PDT 24
Peak memory 351156 kb
Host smart-9dd98926-b0c4-4569-9980-6399b0c84464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358770491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.358770491
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.2046592318
Short name T245
Test name
Test status
Simulation time 61435995662 ps
CPU time 2760.95 seconds
Started Apr 30 01:56:34 PM PDT 24
Finished Apr 30 02:42:36 PM PDT 24
Peak memory 2571868 kb
Host smart-68fb4f80-1be6-44a8-a0d6-20f795f45de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046592318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.2046592318
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.4136767908
Short name T951
Test name
Test status
Simulation time 1547816230 ps
CPU time 18.24 seconds
Started Apr 30 01:56:34 PM PDT 24
Finished Apr 30 01:56:53 PM PDT 24
Peak memory 212400 kb
Host smart-846503f2-72db-4f9f-b47f-8cc6f5b75dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136767908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.4136767908
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.4093180208
Short name T938
Test name
Test status
Simulation time 709568283 ps
CPU time 3.73 seconds
Started Apr 30 01:56:39 PM PDT 24
Finished Apr 30 01:56:43 PM PDT 24
Peak memory 204180 kb
Host smart-999d3627-5a08-459f-bcdc-f084efabed0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093180208 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.4093180208
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.3240117226
Short name T1281
Test name
Test status
Simulation time 10244330387 ps
CPU time 14.66 seconds
Started Apr 30 01:56:40 PM PDT 24
Finished Apr 30 01:56:55 PM PDT 24
Peak memory 253684 kb
Host smart-9a2c0904-27ac-4c8b-99d2-61f4b593b7fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240117226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.3240117226
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.549758353
Short name T837
Test name
Test status
Simulation time 10075183239 ps
CPU time 78.69 seconds
Started Apr 30 01:56:39 PM PDT 24
Finished Apr 30 01:57:58 PM PDT 24
Peak memory 557984 kb
Host smart-f9c23ae3-1d6c-4a40-9c9d-0bd075bbcf9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549758353 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_fifo_reset_tx.549758353
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.2804650729
Short name T23
Test name
Test status
Simulation time 544109867 ps
CPU time 2.82 seconds
Started Apr 30 01:56:40 PM PDT 24
Finished Apr 30 01:56:43 PM PDT 24
Peak memory 204088 kb
Host smart-46e4b9eb-5168-42f7-804f-3e326bb89c98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804650729 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.2804650729
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2724855032
Short name T1107
Test name
Test status
Simulation time 763813094 ps
CPU time 4.14 seconds
Started Apr 30 01:56:34 PM PDT 24
Finished Apr 30 01:56:39 PM PDT 24
Peak memory 204132 kb
Host smart-f48ec4b5-93c2-47ef-aedd-4729a6a9abf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724855032 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2724855032
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.3339917537
Short name T813
Test name
Test status
Simulation time 7571111716 ps
CPU time 15.56 seconds
Started Apr 30 01:56:41 PM PDT 24
Finished Apr 30 01:56:57 PM PDT 24
Peak memory 275176 kb
Host smart-31766300-cf19-4242-a9b1-6de5db537d0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339917537 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.3339917537
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.1942289645
Short name T829
Test name
Test status
Simulation time 2121880748 ps
CPU time 15.14 seconds
Started Apr 30 01:56:38 PM PDT 24
Finished Apr 30 01:56:53 PM PDT 24
Peak memory 204112 kb
Host smart-8676e52b-b312-4320-bc65-514c77da1e8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942289645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.1942289645
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.854037139
Short name T882
Test name
Test status
Simulation time 1517670999 ps
CPU time 28.23 seconds
Started Apr 30 01:56:33 PM PDT 24
Finished Apr 30 01:57:03 PM PDT 24
Peak memory 223020 kb
Host smart-249a5eac-425d-4141-bc2f-e8bcdf2b9784
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854037139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_rd.854037139
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.405321096
Short name T999
Test name
Test status
Simulation time 12171877689 ps
CPU time 26.79 seconds
Started Apr 30 01:56:34 PM PDT 24
Finished Apr 30 01:57:02 PM PDT 24
Peak memory 204192 kb
Host smart-72f0dd2f-fb78-4a4e-a7f4-42ec603aff1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405321096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_wr.405321096
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.2433374334
Short name T643
Test name
Test status
Simulation time 5942559603 ps
CPU time 466.66 seconds
Started Apr 30 01:56:34 PM PDT 24
Finished Apr 30 02:04:21 PM PDT 24
Peak memory 1592236 kb
Host smart-c44b3a16-4331-4beb-aec5-3ff220a2f802
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433374334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.2433374334
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.745034490
Short name T568
Test name
Test status
Simulation time 1385579803 ps
CPU time 7.52 seconds
Started Apr 30 01:56:41 PM PDT 24
Finished Apr 30 01:56:49 PM PDT 24
Peak memory 215688 kb
Host smart-c4735dc8-fb0d-4661-bae8-186cf2f130ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745034490 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_timeout.745034490
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_unexp_stop.3808680203
Short name T711
Test name
Test status
Simulation time 6474673856 ps
CPU time 4.98 seconds
Started Apr 30 01:56:40 PM PDT 24
Finished Apr 30 01:56:45 PM PDT 24
Peak memory 206660 kb
Host smart-435ca4cb-e312-47d8-a551-297821d1cb78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808680203 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.i2c_target_unexp_stop.3808680203
Directory /workspace/36.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2701151273
Short name T523
Test name
Test status
Simulation time 17323028 ps
CPU time 0.62 seconds
Started Apr 30 01:56:48 PM PDT 24
Finished Apr 30 01:56:49 PM PDT 24
Peak memory 203876 kb
Host smart-11123d3b-785a-4cc1-8955-508e15a070fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701151273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2701151273
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.3101061461
Short name T530
Test name
Test status
Simulation time 917333586 ps
CPU time 1.65 seconds
Started Apr 30 01:56:51 PM PDT 24
Finished Apr 30 01:56:54 PM PDT 24
Peak memory 212384 kb
Host smart-96f4c22c-286c-437b-a2e5-0560cfcc64e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101061461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.3101061461
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.2790870354
Short name T624
Test name
Test status
Simulation time 475354966 ps
CPU time 2.96 seconds
Started Apr 30 01:56:51 PM PDT 24
Finished Apr 30 01:56:54 PM PDT 24
Peak memory 229696 kb
Host smart-d7e1f1ea-cc9f-4487-a2d9-526a4d13237a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790870354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.2790870354
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.2819117988
Short name T317
Test name
Test status
Simulation time 2231617637 ps
CPU time 59.7 seconds
Started Apr 30 01:56:45 PM PDT 24
Finished Apr 30 01:57:45 PM PDT 24
Peak memory 640328 kb
Host smart-da1c0c7b-a371-41c8-90cf-1cc3991be14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819117988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.2819117988
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.1145709102
Short name T93
Test name
Test status
Simulation time 4445046179 ps
CPU time 158.16 seconds
Started Apr 30 01:56:45 PM PDT 24
Finished Apr 30 01:59:23 PM PDT 24
Peak memory 745436 kb
Host smart-6eb2bade-2b05-4420-846f-f9b59dfc16f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145709102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.1145709102
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.62664611
Short name T537
Test name
Test status
Simulation time 241837601 ps
CPU time 0.99 seconds
Started Apr 30 01:56:46 PM PDT 24
Finished Apr 30 01:56:48 PM PDT 24
Peak memory 204088 kb
Host smart-f5b775e5-6ba6-40d1-af11-f01d6e204e07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62664611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fmt
.62664611
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.757123779
Short name T594
Test name
Test status
Simulation time 594235229 ps
CPU time 7.22 seconds
Started Apr 30 01:56:47 PM PDT 24
Finished Apr 30 01:56:55 PM PDT 24
Peak memory 204128 kb
Host smart-e80d4d35-8dea-474e-aa4f-361912ecc64f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757123779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.
757123779
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1037865218
Short name T852
Test name
Test status
Simulation time 3310480384 ps
CPU time 232.47 seconds
Started Apr 30 01:56:48 PM PDT 24
Finished Apr 30 02:00:40 PM PDT 24
Peak memory 986476 kb
Host smart-94989472-5431-400c-a801-a801b230648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037865218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1037865218
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.989345618
Short name T527
Test name
Test status
Simulation time 1342313678 ps
CPU time 3.71 seconds
Started Apr 30 01:56:48 PM PDT 24
Finished Apr 30 01:56:52 PM PDT 24
Peak memory 204144 kb
Host smart-ebf91a07-c499-42a3-af7d-1891b80cb112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989345618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.989345618
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.2587605237
Short name T67
Test name
Test status
Simulation time 2217634362 ps
CPU time 17.64 seconds
Started Apr 30 01:56:47 PM PDT 24
Finished Apr 30 01:57:05 PM PDT 24
Peak memory 294144 kb
Host smart-619a5c85-194a-477b-9c8c-0852da9d2f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587605237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.2587605237
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.1847853291
Short name T1157
Test name
Test status
Simulation time 111898029 ps
CPU time 0.63 seconds
Started Apr 30 01:56:49 PM PDT 24
Finished Apr 30 01:56:50 PM PDT 24
Peak memory 203796 kb
Host smart-7f1373fc-792e-463f-8172-8cf5b629e3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847853291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.1847853291
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.1571367031
Short name T1007
Test name
Test status
Simulation time 30068989989 ps
CPU time 80.05 seconds
Started Apr 30 01:56:47 PM PDT 24
Finished Apr 30 01:58:08 PM PDT 24
Peak memory 331320 kb
Host smart-0c88e381-4cab-4a8b-88f9-fba37a34e0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571367031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.1571367031
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.1409019019
Short name T637
Test name
Test status
Simulation time 6549243321 ps
CPU time 27.58 seconds
Started Apr 30 01:56:50 PM PDT 24
Finished Apr 30 01:57:18 PM PDT 24
Peak memory 326192 kb
Host smart-be5755ac-d709-4a75-9b77-320fcd93958b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409019019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.1409019019
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.111424703
Short name T170
Test name
Test status
Simulation time 41177148718 ps
CPU time 326.95 seconds
Started Apr 30 01:56:51 PM PDT 24
Finished Apr 30 02:02:19 PM PDT 24
Peak memory 1975856 kb
Host smart-8dc71aa8-0134-493d-99f6-ba92eede62eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111424703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.111424703
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.188336620
Short name T1065
Test name
Test status
Simulation time 423558608 ps
CPU time 6.34 seconds
Started Apr 30 01:56:47 PM PDT 24
Finished Apr 30 01:56:54 PM PDT 24
Peak memory 213944 kb
Host smart-f6dfb22d-f8b9-44d0-97d9-87e75d6dca8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188336620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.188336620
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.3936795602
Short name T676
Test name
Test status
Simulation time 3666089665 ps
CPU time 4.51 seconds
Started Apr 30 01:56:49 PM PDT 24
Finished Apr 30 01:56:54 PM PDT 24
Peak memory 212656 kb
Host smart-c9ac55da-530b-4682-be11-736f0afe6b96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936795602 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.3936795602
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.859912717
Short name T542
Test name
Test status
Simulation time 10066044940 ps
CPU time 73.6 seconds
Started Apr 30 01:56:45 PM PDT 24
Finished Apr 30 01:57:59 PM PDT 24
Peak memory 451592 kb
Host smart-5f1f4dff-db2c-4c93-9aee-eb8d84d2ed68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859912717 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_acq.859912717
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.1617406272
Short name T689
Test name
Test status
Simulation time 10105281597 ps
CPU time 57.43 seconds
Started Apr 30 01:56:46 PM PDT 24
Finished Apr 30 01:57:43 PM PDT 24
Peak memory 518840 kb
Host smart-b21d6692-aa80-4e7e-b1f6-5c6dcb280dbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617406272 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.1617406272
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.701063496
Short name T524
Test name
Test status
Simulation time 432106617 ps
CPU time 2.74 seconds
Started Apr 30 01:56:46 PM PDT 24
Finished Apr 30 01:56:50 PM PDT 24
Peak memory 204092 kb
Host smart-66c66809-286f-4c29-8b96-cb275fe92cdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701063496 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.i2c_target_hrst.701063496
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.3976548874
Short name T1001
Test name
Test status
Simulation time 2146840326 ps
CPU time 5.9 seconds
Started Apr 30 01:56:47 PM PDT 24
Finished Apr 30 01:56:53 PM PDT 24
Peak memory 211904 kb
Host smart-7e04b8e7-3602-446e-9093-3be0343a434a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976548874 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.3976548874
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.968131302
Short name T982
Test name
Test status
Simulation time 4134954991 ps
CPU time 9.09 seconds
Started Apr 30 01:56:47 PM PDT 24
Finished Apr 30 01:56:56 PM PDT 24
Peak memory 204196 kb
Host smart-0f824c57-8439-46c7-a874-9bf08ed915da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968131302 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.968131302
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.2967409686
Short name T1265
Test name
Test status
Simulation time 782558637 ps
CPU time 11.05 seconds
Started Apr 30 01:56:47 PM PDT 24
Finished Apr 30 01:56:58 PM PDT 24
Peak memory 204076 kb
Host smart-c33aae49-8f20-49a1-a00f-8ef9376435de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967409686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.2967409686
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.433839047
Short name T529
Test name
Test status
Simulation time 3029273651 ps
CPU time 18.65 seconds
Started Apr 30 01:56:47 PM PDT 24
Finished Apr 30 01:57:06 PM PDT 24
Peak memory 204116 kb
Host smart-cbaa7fcd-700f-4ef5-b7b9-01b0151e8fb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433839047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_rd.433839047
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.2289625866
Short name T1308
Test name
Test status
Simulation time 29267700123 ps
CPU time 192.91 seconds
Started Apr 30 01:56:47 PM PDT 24
Finished Apr 30 02:00:01 PM PDT 24
Peak memory 2343492 kb
Host smart-9d972943-5449-45a1-9b48-4304d1c0ec14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289625866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.2289625866
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.4133040396
Short name T706
Test name
Test status
Simulation time 28982794044 ps
CPU time 746.87 seconds
Started Apr 30 01:56:46 PM PDT 24
Finished Apr 30 02:09:14 PM PDT 24
Peak memory 3913748 kb
Host smart-c5449487-816e-4f60-9c2b-1cc2d7972789
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133040396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.4133040396
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.964323837
Short name T1335
Test name
Test status
Simulation time 3337162612 ps
CPU time 8.09 seconds
Started Apr 30 01:56:47 PM PDT 24
Finished Apr 30 01:56:55 PM PDT 24
Peak memory 219040 kb
Host smart-2275b43a-e2c4-48e3-9deb-78a5c0b0434c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964323837 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_timeout.964323837
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.185584685
Short name T91
Test name
Test status
Simulation time 37195202 ps
CPU time 0.62 seconds
Started Apr 30 01:56:59 PM PDT 24
Finished Apr 30 01:57:00 PM PDT 24
Peak memory 203864 kb
Host smart-f63edfc4-8898-4090-8843-b4593b0e40ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185584685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.185584685
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.4085899922
Short name T649
Test name
Test status
Simulation time 182478047 ps
CPU time 1.47 seconds
Started Apr 30 01:56:51 PM PDT 24
Finished Apr 30 01:56:53 PM PDT 24
Peak memory 212524 kb
Host smart-236d991d-adc4-4e10-b2a0-f615e712c021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085899922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.4085899922
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.3567853397
Short name T1158
Test name
Test status
Simulation time 1395539186 ps
CPU time 6.47 seconds
Started Apr 30 01:56:49 PM PDT 24
Finished Apr 30 01:56:56 PM PDT 24
Peak memory 281944 kb
Host smart-49c30be4-3458-4ff6-bc67-4b8753294ca8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567853397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.3567853397
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.649368501
Short name T329
Test name
Test status
Simulation time 14555146523 ps
CPU time 58.03 seconds
Started Apr 30 01:56:59 PM PDT 24
Finished Apr 30 01:57:57 PM PDT 24
Peak memory 602060 kb
Host smart-4f740add-57fd-4e67-aa70-094951c1627f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649368501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.649368501
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.125810370
Short name T1222
Test name
Test status
Simulation time 12424039111 ps
CPU time 66.95 seconds
Started Apr 30 01:56:45 PM PDT 24
Finished Apr 30 01:57:53 PM PDT 24
Peak memory 670580 kb
Host smart-68c260b6-9db3-47ab-a22d-1a0172ab0a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125810370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.125810370
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.2172432280
Short name T752
Test name
Test status
Simulation time 92988158 ps
CPU time 0.88 seconds
Started Apr 30 01:56:45 PM PDT 24
Finished Apr 30 01:56:46 PM PDT 24
Peak memory 203964 kb
Host smart-59c6b59e-b3d5-4f3d-bac1-4ca88af18400
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172432280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.2172432280
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.2116184428
Short name T1074
Test name
Test status
Simulation time 497712559 ps
CPU time 3.25 seconds
Started Apr 30 01:56:52 PM PDT 24
Finished Apr 30 01:56:56 PM PDT 24
Peak memory 221692 kb
Host smart-10553376-aa6f-4b19-83b1-7b2c30c34b5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116184428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.2116184428
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.2239962790
Short name T1342
Test name
Test status
Simulation time 13798986561 ps
CPU time 256.46 seconds
Started Apr 30 01:56:48 PM PDT 24
Finished Apr 30 02:01:05 PM PDT 24
Peak memory 1064020 kb
Host smart-680f8d06-0377-4bd8-b18b-2037a53c23f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239962790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.2239962790
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.879408231
Short name T994
Test name
Test status
Simulation time 5752435747 ps
CPU time 21.66 seconds
Started Apr 30 01:56:58 PM PDT 24
Finished Apr 30 01:57:21 PM PDT 24
Peak memory 204168 kb
Host smart-930634f2-bc4f-46e5-8287-b769dc8b4c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879408231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.879408231
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.4292152846
Short name T1062
Test name
Test status
Simulation time 1309900107 ps
CPU time 24.59 seconds
Started Apr 30 01:56:58 PM PDT 24
Finished Apr 30 01:57:23 PM PDT 24
Peak memory 289256 kb
Host smart-278b72f5-993f-435c-9f60-0b02fc87121a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292152846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.4292152846
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.3857146123
Short name T187
Test name
Test status
Simulation time 184450289 ps
CPU time 0.69 seconds
Started Apr 30 01:56:45 PM PDT 24
Finished Apr 30 01:56:47 PM PDT 24
Peak memory 203872 kb
Host smart-ecdd7475-4b76-4a04-80c6-e2e260a6f4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857146123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3857146123
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.359105593
Short name T830
Test name
Test status
Simulation time 17837577098 ps
CPU time 680.49 seconds
Started Apr 30 01:56:53 PM PDT 24
Finished Apr 30 02:08:14 PM PDT 24
Peak memory 204224 kb
Host smart-4b3cab0c-c7ee-46f1-935c-16fc83040434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359105593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.359105593
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.1662981329
Short name T822
Test name
Test status
Simulation time 4134362035 ps
CPU time 29.67 seconds
Started Apr 30 01:56:46 PM PDT 24
Finished Apr 30 01:57:16 PM PDT 24
Peak memory 326232 kb
Host smart-af634eaa-b803-491a-8604-935960cac768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662981329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1662981329
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.228153306
Short name T472
Test name
Test status
Simulation time 2708968432 ps
CPU time 10.22 seconds
Started Apr 30 01:56:51 PM PDT 24
Finished Apr 30 01:57:02 PM PDT 24
Peak memory 214888 kb
Host smart-e844f66a-21ea-4551-9a36-83477398b08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228153306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.228153306
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.1334810778
Short name T1255
Test name
Test status
Simulation time 9672518986 ps
CPU time 4.43 seconds
Started Apr 30 01:56:49 PM PDT 24
Finished Apr 30 01:56:54 PM PDT 24
Peak memory 212476 kb
Host smart-71014412-229b-4864-95b1-dd1711d6d518
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334810778 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.1334810778
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.3686872950
Short name T274
Test name
Test status
Simulation time 10082733582 ps
CPU time 64.18 seconds
Started Apr 30 01:56:51 PM PDT 24
Finished Apr 30 01:57:55 PM PDT 24
Peak memory 487572 kb
Host smart-54eccafb-e6b7-4d46-9758-ebb0a15551b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686872950 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.3686872950
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.2919672792
Short name T275
Test name
Test status
Simulation time 12317063094 ps
CPU time 4.39 seconds
Started Apr 30 01:56:50 PM PDT 24
Finished Apr 30 01:56:55 PM PDT 24
Peak memory 232804 kb
Host smart-6ec3cdd2-92cd-4d5a-9d49-4013434f99b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919672792 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.2919672792
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.3081560986
Short name T448
Test name
Test status
Simulation time 283663073 ps
CPU time 1.97 seconds
Started Apr 30 01:56:50 PM PDT 24
Finished Apr 30 01:56:53 PM PDT 24
Peak memory 204148 kb
Host smart-d858d692-d6a5-4960-a96b-491627d85391
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081560986 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.3081560986
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.1956847173
Short name T457
Test name
Test status
Simulation time 832807813 ps
CPU time 4.45 seconds
Started Apr 30 01:56:51 PM PDT 24
Finished Apr 30 01:56:56 PM PDT 24
Peak memory 204148 kb
Host smart-52fc5c1c-37f5-43e3-a731-258d65fa686e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956847173 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.1956847173
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.2210394893
Short name T1349
Test name
Test status
Simulation time 14871783596 ps
CPU time 33.9 seconds
Started Apr 30 01:56:51 PM PDT 24
Finished Apr 30 01:57:26 PM PDT 24
Peak memory 864364 kb
Host smart-a4705448-a352-48da-8f33-ade9c59ad7b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210394893 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.2210394893
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.1918010826
Short name T1072
Test name
Test status
Simulation time 1444008034 ps
CPU time 24.52 seconds
Started Apr 30 01:56:52 PM PDT 24
Finished Apr 30 01:57:17 PM PDT 24
Peak memory 204172 kb
Host smart-8bcc83b3-1035-424f-9784-57f00dc44b74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918010826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.1918010826
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.4092199138
Short name T404
Test name
Test status
Simulation time 2961402113 ps
CPU time 29.97 seconds
Started Apr 30 01:56:50 PM PDT 24
Finished Apr 30 01:57:21 PM PDT 24
Peak memory 204236 kb
Host smart-06a8ac50-2394-4bc8-a589-ff57f20a8a57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092199138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.4092199138
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.2797880895
Short name T928
Test name
Test status
Simulation time 49968340595 ps
CPU time 130.32 seconds
Started Apr 30 01:56:51 PM PDT 24
Finished Apr 30 01:59:02 PM PDT 24
Peak memory 1742032 kb
Host smart-58d51beb-227d-4c51-ab15-7eb656abf4cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797880895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.2797880895
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.243640314
Short name T926
Test name
Test status
Simulation time 30284830823 ps
CPU time 1920.27 seconds
Started Apr 30 01:56:51 PM PDT 24
Finished Apr 30 02:28:52 PM PDT 24
Peak memory 7415904 kb
Host smart-c5d64718-5ea1-45a2-a988-329add2e3c41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243640314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_t
arget_stretch.243640314
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.1573508543
Short name T255
Test name
Test status
Simulation time 20078144226 ps
CPU time 7.57 seconds
Started Apr 30 01:56:53 PM PDT 24
Finished Apr 30 01:57:01 PM PDT 24
Peak memory 217236 kb
Host smart-da9ceadb-7c31-4c48-8908-5be81de29ec7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573508543 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.1573508543
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1563724253
Short name T96
Test name
Test status
Simulation time 15077033 ps
CPU time 0.61 seconds
Started Apr 30 01:57:03 PM PDT 24
Finished Apr 30 01:57:04 PM PDT 24
Peak memory 203832 kb
Host smart-b57ce0f3-8e86-487a-85d3-a7d073b0a7ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563724253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1563724253
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.1660024479
Short name T415
Test name
Test status
Simulation time 243227101 ps
CPU time 1.75 seconds
Started Apr 30 01:56:58 PM PDT 24
Finished Apr 30 01:57:00 PM PDT 24
Peak memory 212712 kb
Host smart-3298bfdc-e234-4160-b254-5c52aa904f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660024479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.1660024479
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.188068673
Short name T380
Test name
Test status
Simulation time 1615477272 ps
CPU time 7.57 seconds
Started Apr 30 01:56:56 PM PDT 24
Finished Apr 30 01:57:04 PM PDT 24
Peak memory 292980 kb
Host smart-c01fe6f2-d72f-4cd6-8bbd-80b68d1d6a40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188068673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empt
y.188068673
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.253393134
Short name T1250
Test name
Test status
Simulation time 1691419604 ps
CPU time 49.36 seconds
Started Apr 30 01:56:56 PM PDT 24
Finished Apr 30 01:57:46 PM PDT 24
Peak memory 616644 kb
Host smart-6d5eb845-1ce6-4298-8ade-5acb89f0eb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253393134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.253393134
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.1679226572
Short name T1165
Test name
Test status
Simulation time 1766127730 ps
CPU time 46.31 seconds
Started Apr 30 01:57:00 PM PDT 24
Finished Apr 30 01:57:47 PM PDT 24
Peak memory 576212 kb
Host smart-acede5f0-54f9-4ccd-8727-7e2abde7532e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679226572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.1679226572
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3553296011
Short name T583
Test name
Test status
Simulation time 245067992 ps
CPU time 0.82 seconds
Started Apr 30 01:57:00 PM PDT 24
Finished Apr 30 01:57:02 PM PDT 24
Peak memory 203928 kb
Host smart-ef87ca31-1581-4b82-8875-aa87d28b8fd2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553296011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3553296011
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.3017885308
Short name T366
Test name
Test status
Simulation time 185894498 ps
CPU time 4.96 seconds
Started Apr 30 01:56:58 PM PDT 24
Finished Apr 30 01:57:03 PM PDT 24
Peak memory 235720 kb
Host smart-e67feb9b-0808-4bb3-b609-1e9b0007a220
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017885308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.3017885308
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.1836044132
Short name T163
Test name
Test status
Simulation time 2303630962 ps
CPU time 50.2 seconds
Started Apr 30 01:56:58 PM PDT 24
Finished Apr 30 01:57:48 PM PDT 24
Peak memory 714972 kb
Host smart-11054153-1ec8-4eac-a5b9-cba722484f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836044132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1836044132
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.2826400765
Short name T1285
Test name
Test status
Simulation time 488648229 ps
CPU time 17.57 seconds
Started Apr 30 01:57:02 PM PDT 24
Finished Apr 30 01:57:20 PM PDT 24
Peak memory 204140 kb
Host smart-6a62769d-c178-469f-b73e-f6bcc980c919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826400765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.2826400765
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.1837548874
Short name T1128
Test name
Test status
Simulation time 5987648009 ps
CPU time 29.85 seconds
Started Apr 30 01:57:03 PM PDT 24
Finished Apr 30 01:57:34 PM PDT 24
Peak memory 329316 kb
Host smart-6c64cb28-ed74-44ac-94b8-3b6d82557cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837548874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.1837548874
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.2340350133
Short name T186
Test name
Test status
Simulation time 75121651 ps
CPU time 0.65 seconds
Started Apr 30 01:56:59 PM PDT 24
Finished Apr 30 01:57:00 PM PDT 24
Peak memory 203840 kb
Host smart-cc402237-2cf8-48b8-a6f7-543d299abea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340350133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.2340350133
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2961408689
Short name T519
Test name
Test status
Simulation time 12570387236 ps
CPU time 476.72 seconds
Started Apr 30 01:57:02 PM PDT 24
Finished Apr 30 02:04:59 PM PDT 24
Peak memory 2063444 kb
Host smart-01400f9c-c482-4e92-91a8-235123e183ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961408689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2961408689
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.4224625723
Short name T949
Test name
Test status
Simulation time 1041663578 ps
CPU time 17.28 seconds
Started Apr 30 01:56:58 PM PDT 24
Finished Apr 30 01:57:16 PM PDT 24
Peak memory 310924 kb
Host smart-7da11ac4-cde4-4bb5-abb4-6a7b19f3c848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224625723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.4224625723
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.638011775
Short name T171
Test name
Test status
Simulation time 33882802259 ps
CPU time 271.75 seconds
Started Apr 30 01:56:58 PM PDT 24
Finished Apr 30 02:01:31 PM PDT 24
Peak memory 1500952 kb
Host smart-b43f690e-23fc-4aff-ae06-d214b11a8d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638011775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.638011775
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.3002769545
Short name T1170
Test name
Test status
Simulation time 781369860 ps
CPU time 31.48 seconds
Started Apr 30 01:56:57 PM PDT 24
Finished Apr 30 01:57:29 PM PDT 24
Peak memory 212372 kb
Host smart-2913a2cb-3ea9-4ff7-962f-3f9954a74a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002769545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.3002769545
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.1319047927
Short name T887
Test name
Test status
Simulation time 1707831912 ps
CPU time 4.32 seconds
Started Apr 30 01:57:03 PM PDT 24
Finished Apr 30 01:57:08 PM PDT 24
Peak memory 212616 kb
Host smart-ad9217df-e9d4-4c61-ad23-c30c44931aa1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319047927 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1319047927
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.3946464113
Short name T945
Test name
Test status
Simulation time 10067858321 ps
CPU time 28.09 seconds
Started Apr 30 01:57:01 PM PDT 24
Finished Apr 30 01:57:30 PM PDT 24
Peak memory 338992 kb
Host smart-3d6b9c1c-630e-4bb3-8c8f-c6d87eb6d8ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946464113 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.3946464113
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.2829174247
Short name T1275
Test name
Test status
Simulation time 10130048376 ps
CPU time 20.43 seconds
Started Apr 30 01:56:59 PM PDT 24
Finished Apr 30 01:57:20 PM PDT 24
Peak memory 294736 kb
Host smart-6b848688-840b-48e4-837d-39d1dacbb8c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829174247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.2829174247
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.334028225
Short name T505
Test name
Test status
Simulation time 358550606 ps
CPU time 2.26 seconds
Started Apr 30 01:57:03 PM PDT 24
Finished Apr 30 01:57:06 PM PDT 24
Peak memory 204232 kb
Host smart-45aa9ed8-2dcb-48d3-a811-5654fc7ccc51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334028225 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.i2c_target_hrst.334028225
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.3774126583
Short name T812
Test name
Test status
Simulation time 2293818456 ps
CPU time 4.5 seconds
Started Apr 30 01:56:56 PM PDT 24
Finished Apr 30 01:57:01 PM PDT 24
Peak memory 212440 kb
Host smart-2c47ea6d-4d98-4ebb-99e1-eb19b1213324
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774126583 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.3774126583
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.1571981091
Short name T97
Test name
Test status
Simulation time 41527075577 ps
CPU time 20.93 seconds
Started Apr 30 01:56:57 PM PDT 24
Finished Apr 30 01:57:19 PM PDT 24
Peak memory 524604 kb
Host smart-b09ec8a2-d912-41f5-9d0c-82415bb5696c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571981091 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.1571981091
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.432363372
Short name T642
Test name
Test status
Simulation time 2605454260 ps
CPU time 21.33 seconds
Started Apr 30 01:56:57 PM PDT 24
Finished Apr 30 01:57:19 PM PDT 24
Peak memory 204212 kb
Host smart-b73c63a8-45f8-4571-99b3-979c892ed72f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432363372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_tar
get_smoke.432363372
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.282310762
Short name T961
Test name
Test status
Simulation time 1132974883 ps
CPU time 20.14 seconds
Started Apr 30 01:57:00 PM PDT 24
Finished Apr 30 01:57:21 PM PDT 24
Peak memory 214080 kb
Host smart-03a97377-d5e3-4a2d-9236-a8477e84969e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282310762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_rd.282310762
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.3864403882
Short name T1225
Test name
Test status
Simulation time 35338578665 ps
CPU time 50.87 seconds
Started Apr 30 01:56:57 PM PDT 24
Finished Apr 30 01:57:49 PM PDT 24
Peak memory 1031960 kb
Host smart-79722e6d-ec12-4493-9f7e-7fde64df799b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864403882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.3864403882
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.610004311
Short name T425
Test name
Test status
Simulation time 33754186829 ps
CPU time 3177.8 seconds
Started Apr 30 01:56:59 PM PDT 24
Finished Apr 30 02:49:58 PM PDT 24
Peak memory 7989940 kb
Host smart-22f00cc8-47b1-4da7-bb5f-5e3267aef3b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610004311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_t
arget_stretch.610004311
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.2557799470
Short name T1014
Test name
Test status
Simulation time 1469406278 ps
CPU time 6.79 seconds
Started Apr 30 01:56:58 PM PDT 24
Finished Apr 30 01:57:05 PM PDT 24
Peak memory 217476 kb
Host smart-53a3145d-1165-4034-b7e9-47ec5fb6bc24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557799470 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.2557799470
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_unexp_stop.847857866
Short name T757
Test name
Test status
Simulation time 2309359244 ps
CPU time 6.52 seconds
Started Apr 30 01:56:58 PM PDT 24
Finished Apr 30 01:57:05 PM PDT 24
Peak memory 217932 kb
Host smart-f658e78d-6737-44d3-8f1a-38180d73f15b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847857866 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_unexp_stop.847857866
Directory /workspace/39.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/4.i2c_alert_test.1068240747
Short name T965
Test name
Test status
Simulation time 17025937 ps
CPU time 0.63 seconds
Started Apr 30 01:53:03 PM PDT 24
Finished Apr 30 01:53:04 PM PDT 24
Peak memory 203952 kb
Host smart-4d5b54df-e930-433a-8150-3d570c1429fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068240747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.1068240747
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.68548727
Short name T871
Test name
Test status
Simulation time 405791108 ps
CPU time 1.55 seconds
Started Apr 30 01:52:48 PM PDT 24
Finished Apr 30 01:52:50 PM PDT 24
Peak memory 212500 kb
Host smart-6d81c59e-5789-4f7c-9810-fd869a5e9388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68548727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.68548727
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.627118612
Short name T1024
Test name
Test status
Simulation time 657804994 ps
CPU time 3.23 seconds
Started Apr 30 01:52:46 PM PDT 24
Finished Apr 30 01:52:50 PM PDT 24
Peak memory 231792 kb
Host smart-082fc199-7631-491b-8c35-7d2a32d35de8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627118612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty
.627118612
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.2431066468
Short name T43
Test name
Test status
Simulation time 5492789272 ps
CPU time 130.71 seconds
Started Apr 30 01:52:44 PM PDT 24
Finished Apr 30 01:54:55 PM PDT 24
Peak memory 630328 kb
Host smart-85cf3b02-710d-4895-9f5e-0d51beb5e03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431066468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.2431066468
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.1805417972
Short name T1187
Test name
Test status
Simulation time 5192129865 ps
CPU time 85.31 seconds
Started Apr 30 01:52:50 PM PDT 24
Finished Apr 30 01:54:16 PM PDT 24
Peak memory 515236 kb
Host smart-139e60ff-4e75-4050-b667-a5d620537bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805417972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.1805417972
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.1990300895
Short name T371
Test name
Test status
Simulation time 418539708 ps
CPU time 0.89 seconds
Started Apr 30 01:52:46 PM PDT 24
Finished Apr 30 01:52:48 PM PDT 24
Peak memory 203944 kb
Host smart-a44f8083-7e14-4aee-8f43-88533880ea66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990300895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.1990300895
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.3225051087
Short name T1259
Test name
Test status
Simulation time 374073431 ps
CPU time 2.84 seconds
Started Apr 30 01:52:47 PM PDT 24
Finished Apr 30 01:52:51 PM PDT 24
Peak memory 204012 kb
Host smart-ffbc8214-f094-465c-9054-5b73f25a7b84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225051087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
3225051087
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.3995554729
Short name T1270
Test name
Test status
Simulation time 2892508201 ps
CPU time 205.61 seconds
Started Apr 30 01:52:51 PM PDT 24
Finished Apr 30 01:56:17 PM PDT 24
Peak memory 905796 kb
Host smart-518cedd1-9087-484c-8121-76c28f48a535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995554729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.3995554729
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.1916539697
Short name T352
Test name
Test status
Simulation time 429940284 ps
CPU time 6.7 seconds
Started Apr 30 01:52:55 PM PDT 24
Finished Apr 30 01:53:02 PM PDT 24
Peak memory 204196 kb
Host smart-5341652c-8d49-4d22-89e0-3c5cbe499212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916539697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.1916539697
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.1666142046
Short name T954
Test name
Test status
Simulation time 4876334515 ps
CPU time 56.38 seconds
Started Apr 30 01:52:59 PM PDT 24
Finished Apr 30 01:53:56 PM PDT 24
Peak memory 301632 kb
Host smart-0065c2c5-01ab-458b-ab6b-941f4c433eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666142046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.1666142046
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.1350699857
Short name T36
Test name
Test status
Simulation time 54739895 ps
CPU time 0.69 seconds
Started Apr 30 01:52:53 PM PDT 24
Finished Apr 30 01:52:54 PM PDT 24
Peak memory 203892 kb
Host smart-2147a0f8-137b-4e1b-a341-d689793ed5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350699857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.1350699857
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.343300066
Short name T806
Test name
Test status
Simulation time 49279936332 ps
CPU time 153.11 seconds
Started Apr 30 01:52:50 PM PDT 24
Finished Apr 30 01:55:24 PM PDT 24
Peak memory 204236 kb
Host smart-5b7bb678-912a-4d2b-a98c-02636a8d808a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343300066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.343300066
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1079943335
Short name T1019
Test name
Test status
Simulation time 6930628673 ps
CPU time 37.28 seconds
Started Apr 30 01:52:52 PM PDT 24
Finished Apr 30 01:53:29 PM PDT 24
Peak memory 401880 kb
Host smart-9871d3a3-e759-4eb9-99fb-5a2de66b800b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079943335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1079943335
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.1484359277
Short name T299
Test name
Test status
Simulation time 353482215 ps
CPU time 5.68 seconds
Started Apr 30 01:52:50 PM PDT 24
Finished Apr 30 01:53:01 PM PDT 24
Peak memory 212340 kb
Host smart-acdc7668-6195-465a-83b7-ebdf13354062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484359277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.1484359277
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.1908774790
Short name T111
Test name
Test status
Simulation time 127467236 ps
CPU time 0.91 seconds
Started Apr 30 01:52:52 PM PDT 24
Finished Apr 30 01:52:53 PM PDT 24
Peak memory 222440 kb
Host smart-3774b401-34af-40de-a83a-2f40db6388da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908774790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.1908774790
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.3905222697
Short name T709
Test name
Test status
Simulation time 843111956 ps
CPU time 4.03 seconds
Started Apr 30 01:52:54 PM PDT 24
Finished Apr 30 01:52:59 PM PDT 24
Peak memory 203988 kb
Host smart-d7ed0b59-4e7d-4e1f-bcff-42812be62c7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905222697 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.3905222697
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.854380630
Short name T844
Test name
Test status
Simulation time 10074716517 ps
CPU time 23.01 seconds
Started Apr 30 01:52:53 PM PDT 24
Finished Apr 30 01:53:17 PM PDT 24
Peak memory 295812 kb
Host smart-db238222-5f54-4e2c-917c-4b10a1f17543
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854380630 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_acq.854380630
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.2897841413
Short name T1125
Test name
Test status
Simulation time 10073442009 ps
CPU time 75.28 seconds
Started Apr 30 01:52:50 PM PDT 24
Finished Apr 30 01:54:06 PM PDT 24
Peak memory 555064 kb
Host smart-08f79813-964e-4bc4-8331-8c7451183b22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897841413 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.2897841413
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.3851216018
Short name T1197
Test name
Test status
Simulation time 445403513 ps
CPU time 2.82 seconds
Started Apr 30 01:52:53 PM PDT 24
Finished Apr 30 01:52:57 PM PDT 24
Peak memory 204120 kb
Host smart-34db3c43-e4b9-4511-b9e5-9e6fad2e6730
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851216018 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.3851216018
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.2687605861
Short name T819
Test name
Test status
Simulation time 2177082289 ps
CPU time 5.59 seconds
Started Apr 30 01:52:45 PM PDT 24
Finished Apr 30 01:52:51 PM PDT 24
Peak memory 204888 kb
Host smart-afd3a92e-77fd-48c2-b7f1-881d6b95f21d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687605861 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.2687605861
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.1962253696
Short name T176
Test name
Test status
Simulation time 4303119933 ps
CPU time 15.6 seconds
Started Apr 30 01:52:47 PM PDT 24
Finished Apr 30 01:53:03 PM PDT 24
Peak memory 664064 kb
Host smart-fbe07cd2-71f7-47fa-b692-ed4f57f7ccf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962253696 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.1962253696
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.1250943865
Short name T923
Test name
Test status
Simulation time 4518519541 ps
CPU time 23.1 seconds
Started Apr 30 01:52:49 PM PDT 24
Finished Apr 30 01:53:12 PM PDT 24
Peak memory 204232 kb
Host smart-f0aa617b-4f48-4f36-a9e0-e7d296f2daef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250943865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.1250943865
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.1856381167
Short name T808
Test name
Test status
Simulation time 654977542 ps
CPU time 8.81 seconds
Started Apr 30 01:52:48 PM PDT 24
Finished Apr 30 01:52:58 PM PDT 24
Peak memory 208620 kb
Host smart-b6150bef-2c96-49f6-aeb6-b4607460f1fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856381167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.1856381167
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.4036057980
Short name T567
Test name
Test status
Simulation time 43501270966 ps
CPU time 801.85 seconds
Started Apr 30 01:52:47 PM PDT 24
Finished Apr 30 02:06:10 PM PDT 24
Peak memory 5803004 kb
Host smart-f096b5c3-558d-481f-97cd-33b2cd5fa024
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036057980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.4036057980
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.1890113644
Short name T536
Test name
Test status
Simulation time 26681593452 ps
CPU time 300.77 seconds
Started Apr 30 01:52:47 PM PDT 24
Finished Apr 30 01:57:48 PM PDT 24
Peak memory 2381576 kb
Host smart-9530fc30-4312-40aa-adf1-6022e17b97eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890113644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.1890113644
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1790425609
Short name T305
Test name
Test status
Simulation time 1629189379 ps
CPU time 6.51 seconds
Started Apr 30 01:52:56 PM PDT 24
Finished Apr 30 01:53:03 PM PDT 24
Peak memory 212616 kb
Host smart-59bb6ca4-bb03-405f-b285-7194de14196a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790425609 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1790425609
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1520816178
Short name T557
Test name
Test status
Simulation time 20195599 ps
CPU time 0.61 seconds
Started Apr 30 01:57:16 PM PDT 24
Finished Apr 30 01:57:17 PM PDT 24
Peak memory 203844 kb
Host smart-0ef0fad7-2852-4873-8f32-11fa682ef52c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520816178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1520816178
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.4136660325
Short name T449
Test name
Test status
Simulation time 97360200 ps
CPU time 1.8 seconds
Started Apr 30 01:57:07 PM PDT 24
Finished Apr 30 01:57:09 PM PDT 24
Peak memory 212476 kb
Host smart-e58f7a7a-30a4-4b63-891f-f6b3b14ad639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136660325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.4136660325
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.4257850726
Short name T347
Test name
Test status
Simulation time 547770367 ps
CPU time 13.38 seconds
Started Apr 30 01:57:04 PM PDT 24
Finished Apr 30 01:57:17 PM PDT 24
Peak memory 254892 kb
Host smart-3fecf9b1-2a4c-4b02-8ed6-5de7ca26b68f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257850726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.4257850726
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.2164187922
Short name T338
Test name
Test status
Simulation time 1998815403 ps
CPU time 63.44 seconds
Started Apr 30 01:57:06 PM PDT 24
Finished Apr 30 01:58:10 PM PDT 24
Peak memory 686376 kb
Host smart-888a1c90-09f3-4ea0-a046-54c1fe799b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164187922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.2164187922
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.1129806408
Short name T403
Test name
Test status
Simulation time 7115783535 ps
CPU time 61.09 seconds
Started Apr 30 01:57:05 PM PDT 24
Finished Apr 30 01:58:07 PM PDT 24
Peak memory 628340 kb
Host smart-397a4f13-515e-45a9-ad93-0edc39ad0999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129806408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1129806408
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3371251978
Short name T1193
Test name
Test status
Simulation time 122858256 ps
CPU time 0.99 seconds
Started Apr 30 01:57:02 PM PDT 24
Finished Apr 30 01:57:04 PM PDT 24
Peak memory 203960 kb
Host smart-054c74c8-2155-4d33-bedb-ffa528ae1f25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371251978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.3371251978
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.3219372906
Short name T39
Test name
Test status
Simulation time 116949786 ps
CPU time 6.74 seconds
Started Apr 30 01:57:04 PM PDT 24
Finished Apr 30 01:57:11 PM PDT 24
Peak memory 222664 kb
Host smart-94e08dfc-a58d-4bdf-b375-f8d52cba923b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219372906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.3219372906
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.1983096684
Short name T1011
Test name
Test status
Simulation time 15348524782 ps
CPU time 275.59 seconds
Started Apr 30 01:57:03 PM PDT 24
Finished Apr 30 02:01:40 PM PDT 24
Peak memory 1054532 kb
Host smart-5e2753d4-7b1a-4f5d-a2d8-4027d9be3da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983096684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.1983096684
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.2194153914
Short name T779
Test name
Test status
Simulation time 2582891396 ps
CPU time 6.56 seconds
Started Apr 30 01:57:15 PM PDT 24
Finished Apr 30 01:57:22 PM PDT 24
Peak memory 204228 kb
Host smart-52f2277c-a612-4352-bb6d-a0cd06ca787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194153914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.2194153914
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.1897219613
Short name T1196
Test name
Test status
Simulation time 1250221065 ps
CPU time 55.91 seconds
Started Apr 30 01:57:12 PM PDT 24
Finished Apr 30 01:58:08 PM PDT 24
Peak memory 283568 kb
Host smart-8dd5e429-e7ae-4b72-bcde-3f21a52d8c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897219613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.1897219613
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.1008980400
Short name T1084
Test name
Test status
Simulation time 82600318 ps
CPU time 0.67 seconds
Started Apr 30 01:57:03 PM PDT 24
Finished Apr 30 01:57:04 PM PDT 24
Peak memory 203840 kb
Host smart-04eafed5-9e6d-47ad-ba34-855f42a0eb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008980400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.1008980400
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.396902754
Short name T420
Test name
Test status
Simulation time 2755059445 ps
CPU time 17.44 seconds
Started Apr 30 01:57:01 PM PDT 24
Finished Apr 30 01:57:19 PM PDT 24
Peak memory 214908 kb
Host smart-7bf5dcda-c1ba-48c0-a73b-fd5da2208f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396902754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.396902754
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.1284426300
Short name T985
Test name
Test status
Simulation time 3204487036 ps
CPU time 28.45 seconds
Started Apr 30 01:57:04 PM PDT 24
Finished Apr 30 01:57:33 PM PDT 24
Peak memory 359636 kb
Host smart-4994277c-bea0-400a-8255-4f8d9906bb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284426300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.1284426300
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.3234568308
Short name T249
Test name
Test status
Simulation time 25799598676 ps
CPU time 1373.45 seconds
Started Apr 30 01:57:06 PM PDT 24
Finished Apr 30 02:20:00 PM PDT 24
Peak memory 2380276 kb
Host smart-d129286e-4f0f-4b78-a048-8e5e5e873466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234568308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.3234568308
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.2443512423
Short name T546
Test name
Test status
Simulation time 472265002 ps
CPU time 20.96 seconds
Started Apr 30 01:57:03 PM PDT 24
Finished Apr 30 01:57:25 PM PDT 24
Peak memory 212400 kb
Host smart-789142d9-0f2b-4616-99fb-bb053145281e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443512423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.2443512423
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.704941749
Short name T854
Test name
Test status
Simulation time 755193752 ps
CPU time 2.2 seconds
Started Apr 30 01:57:13 PM PDT 24
Finished Apr 30 01:57:15 PM PDT 24
Peak memory 204216 kb
Host smart-96e24aeb-c01e-4f51-b9bc-7038be059dca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704941749 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.704941749
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.2021791490
Short name T1307
Test name
Test status
Simulation time 10604468845 ps
CPU time 13.74 seconds
Started Apr 30 01:57:17 PM PDT 24
Finished Apr 30 01:57:31 PM PDT 24
Peak memory 284252 kb
Host smart-a06a2960-294a-46ef-869d-bc15348b566a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021791490 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.2021791490
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.3958972659
Short name T1094
Test name
Test status
Simulation time 949695427 ps
CPU time 2.84 seconds
Started Apr 30 01:57:12 PM PDT 24
Finished Apr 30 01:57:15 PM PDT 24
Peak memory 204148 kb
Host smart-6599beb5-5d68-4aae-8a40-1c038b71d32f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958972659 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.3958972659
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.9386257
Short name T469
Test name
Test status
Simulation time 3234685197 ps
CPU time 4.24 seconds
Started Apr 30 01:57:16 PM PDT 24
Finished Apr 30 01:57:20 PM PDT 24
Peak memory 204168 kb
Host smart-ae886dc1-2124-4b40-a944-d4b04dc2cd4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9386257 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.i2c_target_intr_smoke.9386257
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.2179104067
Short name T390
Test name
Test status
Simulation time 21621991058 ps
CPU time 50.26 seconds
Started Apr 30 01:57:13 PM PDT 24
Finished Apr 30 01:58:04 PM PDT 24
Peak memory 1089504 kb
Host smart-5628edfa-2235-4931-8dbd-78acb8bc2243
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179104067 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.2179104067
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.443490703
Short name T487
Test name
Test status
Simulation time 1308111052 ps
CPU time 49.03 seconds
Started Apr 30 01:57:02 PM PDT 24
Finished Apr 30 01:57:52 PM PDT 24
Peak memory 204192 kb
Host smart-b332f786-89e1-4aec-89f5-340e77bbaa25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443490703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.443490703
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.3104753051
Short name T526
Test name
Test status
Simulation time 5297166361 ps
CPU time 29.89 seconds
Started Apr 30 01:57:13 PM PDT 24
Finished Apr 30 01:57:43 PM PDT 24
Peak memory 260212 kb
Host smart-210b7007-e42d-485f-9f79-ba14456ef45a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104753051 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_target_stress_all.3104753051
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.3552327005
Short name T32
Test name
Test status
Simulation time 1604873235 ps
CPU time 6.14 seconds
Started Apr 30 01:57:12 PM PDT 24
Finished Apr 30 01:57:19 PM PDT 24
Peak memory 204168 kb
Host smart-40c69904-54da-4b37-9a27-fa92ce487559
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552327005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.3552327005
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.3322212269
Short name T327
Test name
Test status
Simulation time 38939051796 ps
CPU time 76.3 seconds
Started Apr 30 01:57:03 PM PDT 24
Finished Apr 30 01:58:20 PM PDT 24
Peak memory 1226004 kb
Host smart-7079aa04-fc83-46f9-b5df-b1686a5e816a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322212269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.3322212269
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.3307591650
Short name T400
Test name
Test status
Simulation time 16000981741 ps
CPU time 120.53 seconds
Started Apr 30 01:57:14 PM PDT 24
Finished Apr 30 01:59:15 PM PDT 24
Peak memory 989000 kb
Host smart-ca6d8e79-c919-4f9e-bfc3-1ec0d38db1ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307591650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.3307591650
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.1561621076
Short name T823
Test name
Test status
Simulation time 20898587045 ps
CPU time 6.46 seconds
Started Apr 30 01:57:13 PM PDT 24
Finished Apr 30 01:57:20 PM PDT 24
Peak memory 212412 kb
Host smart-26764126-6f84-451f-9d41-738ac7bc5b94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561621076 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.1561621076
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.3442736521
Short name T1236
Test name
Test status
Simulation time 39442285 ps
CPU time 0.61 seconds
Started Apr 30 01:57:18 PM PDT 24
Finished Apr 30 01:57:20 PM PDT 24
Peak memory 203924 kb
Host smart-f2cd4e4b-fe84-4693-9d2c-e6934d4af56e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442736521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3442736521
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.1213145047
Short name T223
Test name
Test status
Simulation time 251823177 ps
CPU time 1.4 seconds
Started Apr 30 01:57:15 PM PDT 24
Finished Apr 30 01:57:17 PM PDT 24
Peak memory 212496 kb
Host smart-1a486dd0-5f8c-4659-8fe1-630e1f6596e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213145047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.1213145047
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.1389719202
Short name T1334
Test name
Test status
Simulation time 334823730 ps
CPU time 16.36 seconds
Started Apr 30 01:57:24 PM PDT 24
Finished Apr 30 01:57:41 PM PDT 24
Peak memory 259784 kb
Host smart-31fedc70-bf3e-4080-ac4d-d382710ef607
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389719202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.1389719202
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.2539800322
Short name T700
Test name
Test status
Simulation time 6645156607 ps
CPU time 186.98 seconds
Started Apr 30 01:57:18 PM PDT 24
Finished Apr 30 02:00:26 PM PDT 24
Peak memory 782424 kb
Host smart-724d5f75-d07f-4c00-89cf-e610027c5cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539800322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2539800322
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.1154678145
Short name T297
Test name
Test status
Simulation time 1385010248 ps
CPU time 92.67 seconds
Started Apr 30 01:57:14 PM PDT 24
Finished Apr 30 01:58:47 PM PDT 24
Peak memory 513788 kb
Host smart-c7957adf-4b52-4498-9ff0-0cc1a5b67a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154678145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1154678145
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.3039491964
Short name T612
Test name
Test status
Simulation time 643554640 ps
CPU time 1.12 seconds
Started Apr 30 01:57:16 PM PDT 24
Finished Apr 30 01:57:18 PM PDT 24
Peak memory 204120 kb
Host smart-6b0a116f-a4a1-4e4c-9d58-8fe322fa8139
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039491964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.3039491964
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.1713110105
Short name T1277
Test name
Test status
Simulation time 140636911 ps
CPU time 3.26 seconds
Started Apr 30 01:57:26 PM PDT 24
Finished Apr 30 01:57:29 PM PDT 24
Peak memory 224108 kb
Host smart-c26f554f-9f0b-46d2-8c0b-6f877f819f51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713110105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.1713110105
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.1855025030
Short name T1086
Test name
Test status
Simulation time 35999665157 ps
CPU time 234.04 seconds
Started Apr 30 01:57:16 PM PDT 24
Finished Apr 30 02:01:10 PM PDT 24
Peak memory 1009284 kb
Host smart-29925625-806e-4f29-b35c-1bf67d32b992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855025030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1855025030
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.124060167
Short name T226
Test name
Test status
Simulation time 546341216 ps
CPU time 2.53 seconds
Started Apr 30 01:57:20 PM PDT 24
Finished Apr 30 01:57:23 PM PDT 24
Peak memory 204108 kb
Host smart-c1d306a2-0e87-47b7-af78-59a1ca63859f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124060167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.124060167
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.2222823977
Short name T484
Test name
Test status
Simulation time 1530575307 ps
CPU time 22.64 seconds
Started Apr 30 01:57:20 PM PDT 24
Finished Apr 30 01:57:43 PM PDT 24
Peak memory 319688 kb
Host smart-82e2345b-90d7-4779-bddc-ad4b01a9f692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222823977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.2222823977
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.2782888271
Short name T1201
Test name
Test status
Simulation time 29850315 ps
CPU time 0.71 seconds
Started Apr 30 01:57:19 PM PDT 24
Finished Apr 30 01:57:20 PM PDT 24
Peak memory 203852 kb
Host smart-3cda056c-1a06-4630-8e81-ff22c76d799b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782888271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.2782888271
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.3461124860
Short name T1117
Test name
Test status
Simulation time 71607354744 ps
CPU time 687.33 seconds
Started Apr 30 01:57:19 PM PDT 24
Finished Apr 30 02:08:47 PM PDT 24
Peak memory 212516 kb
Host smart-e7b74a43-d48b-4999-9976-384ce30a9c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461124860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.3461124860
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.3659253563
Short name T1300
Test name
Test status
Simulation time 3360991343 ps
CPU time 39.08 seconds
Started Apr 30 01:57:26 PM PDT 24
Finished Apr 30 01:58:05 PM PDT 24
Peak memory 295180 kb
Host smart-e641609b-9162-4cd4-94bd-e54bd7172fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659253563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.3659253563
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.3654377628
Short name T1075
Test name
Test status
Simulation time 783482376 ps
CPU time 18.14 seconds
Started Apr 30 01:57:14 PM PDT 24
Finished Apr 30 01:57:33 PM PDT 24
Peak memory 212348 kb
Host smart-f57b1014-7ecc-43d3-acfa-58f66bcab7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654377628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3654377628
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.4211876832
Short name T1038
Test name
Test status
Simulation time 603496526 ps
CPU time 3.08 seconds
Started Apr 30 01:57:24 PM PDT 24
Finished Apr 30 01:57:27 PM PDT 24
Peak memory 212304 kb
Host smart-14a3f6ca-33f9-49fe-8d75-a9c425fd1c07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211876832 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.4211876832
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.550314841
Short name T1183
Test name
Test status
Simulation time 10150241712 ps
CPU time 12.27 seconds
Started Apr 30 01:57:25 PM PDT 24
Finished Apr 30 01:57:37 PM PDT 24
Peak memory 256968 kb
Host smart-39d9984c-d7ca-40a0-ab52-7d429dedaa1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550314841 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.550314841
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.185570708
Short name T33
Test name
Test status
Simulation time 10125744003 ps
CPU time 40.55 seconds
Started Apr 30 01:57:18 PM PDT 24
Finished Apr 30 01:57:59 PM PDT 24
Peak memory 407836 kb
Host smart-27ef1910-877e-4579-a2db-976908c88ce7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185570708 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_fifo_reset_tx.185570708
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.1261184862
Short name T309
Test name
Test status
Simulation time 1786594363 ps
CPU time 2.52 seconds
Started Apr 30 01:57:14 PM PDT 24
Finished Apr 30 01:57:17 PM PDT 24
Peak memory 204176 kb
Host smart-85dcbc04-3ad6-473e-8e9c-8ff545132bdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261184862 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.1261184862
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.2849047592
Short name T635
Test name
Test status
Simulation time 8612073533 ps
CPU time 3.9 seconds
Started Apr 30 01:57:18 PM PDT 24
Finished Apr 30 01:57:22 PM PDT 24
Peak memory 204232 kb
Host smart-a0707c65-1240-47fb-8c3a-f776de27e2c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849047592 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.2849047592
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.712505204
Short name T1213
Test name
Test status
Simulation time 16202502047 ps
CPU time 29.99 seconds
Started Apr 30 01:57:18 PM PDT 24
Finished Apr 30 01:57:48 PM PDT 24
Peak memory 596440 kb
Host smart-4881c1d5-dce3-4c94-bd6d-4c88465ce6c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712505204 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.712505204
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.1452818568
Short name T304
Test name
Test status
Simulation time 1938578273 ps
CPU time 39.41 seconds
Started Apr 30 01:57:16 PM PDT 24
Finished Apr 30 01:57:56 PM PDT 24
Peak memory 204124 kb
Host smart-09edbafd-caf7-47b8-a2b1-382e1bd486fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452818568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.1452818568
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.3911832464
Short name T502
Test name
Test status
Simulation time 2583171239 ps
CPU time 13.52 seconds
Started Apr 30 01:57:15 PM PDT 24
Finished Apr 30 01:57:29 PM PDT 24
Peak memory 207208 kb
Host smart-c5037fae-b735-4386-905b-e64003ac51b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911832464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.3911832464
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.1486305720
Short name T1162
Test name
Test status
Simulation time 58642687516 ps
CPU time 253.33 seconds
Started Apr 30 01:57:26 PM PDT 24
Finished Apr 30 02:01:40 PM PDT 24
Peak memory 2411260 kb
Host smart-1a487e88-fd66-418d-b533-b756f581da1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486305720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.1486305720
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.2275252821
Short name T918
Test name
Test status
Simulation time 24957088679 ps
CPU time 453.16 seconds
Started Apr 30 01:57:19 PM PDT 24
Finished Apr 30 02:04:53 PM PDT 24
Peak memory 2565412 kb
Host smart-061fe1bf-79b9-4e9b-8c67-ece08959d569
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275252821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.2275252821
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.2795664892
Short name T1313
Test name
Test status
Simulation time 1471442894 ps
CPU time 6.86 seconds
Started Apr 30 01:57:19 PM PDT 24
Finished Apr 30 01:57:26 PM PDT 24
Peak memory 212396 kb
Host smart-ffd61ed0-9834-4e64-92be-9689dd82cb6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795664892 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.2795664892
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.3869713960
Short name T628
Test name
Test status
Simulation time 104032592 ps
CPU time 0.62 seconds
Started Apr 30 01:57:34 PM PDT 24
Finished Apr 30 01:57:35 PM PDT 24
Peak memory 203872 kb
Host smart-2073826c-fefb-4074-aaa9-0630b32f215c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869713960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3869713960
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.959546441
Short name T35
Test name
Test status
Simulation time 417885901 ps
CPU time 1.41 seconds
Started Apr 30 01:57:27 PM PDT 24
Finished Apr 30 01:57:29 PM PDT 24
Peak memory 220608 kb
Host smart-a6f873e4-fd91-48fa-9f53-6f745bf0857f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959546441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.959546441
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.1110964078
Short name T1143
Test name
Test status
Simulation time 1746133394 ps
CPU time 7.11 seconds
Started Apr 30 01:57:21 PM PDT 24
Finished Apr 30 01:57:28 PM PDT 24
Peak memory 271068 kb
Host smart-a8985be9-d1b5-4f1e-bac9-8d640727827f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110964078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.1110964078
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3823856052
Short name T1039
Test name
Test status
Simulation time 4237756845 ps
CPU time 151.96 seconds
Started Apr 30 01:57:21 PM PDT 24
Finished Apr 30 01:59:54 PM PDT 24
Peak memory 694704 kb
Host smart-09654f89-a2d9-472b-a45f-a4ac62a93f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823856052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3823856052
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.4094394158
Short name T508
Test name
Test status
Simulation time 4016347473 ps
CPU time 68.69 seconds
Started Apr 30 01:57:22 PM PDT 24
Finished Apr 30 01:58:31 PM PDT 24
Peak memory 640480 kb
Host smart-22e8a2e8-3bb9-4bee-a314-6090ddfaf244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094394158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.4094394158
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.1909313114
Short name T344
Test name
Test status
Simulation time 288325865 ps
CPU time 0.81 seconds
Started Apr 30 01:57:22 PM PDT 24
Finished Apr 30 01:57:23 PM PDT 24
Peak memory 203876 kb
Host smart-7588b17a-99e6-4254-b2fc-852b7ea5a040
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909313114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.1909313114
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.2594894918
Short name T62
Test name
Test status
Simulation time 1112078640 ps
CPU time 4.81 seconds
Started Apr 30 01:57:21 PM PDT 24
Finished Apr 30 01:57:26 PM PDT 24
Peak memory 231380 kb
Host smart-4ca1f06d-d52a-473a-8fc0-cd102d26ebf0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594894918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.2594894918
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.2666556123
Short name T167
Test name
Test status
Simulation time 4853972295 ps
CPU time 64.54 seconds
Started Apr 30 01:57:19 PM PDT 24
Finished Apr 30 01:58:24 PM PDT 24
Peak memory 781620 kb
Host smart-efbbffb7-9c2c-4870-980c-76eb8321fd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666556123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.2666556123
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.525244273
Short name T645
Test name
Test status
Simulation time 1812494327 ps
CPU time 7.24 seconds
Started Apr 30 01:57:33 PM PDT 24
Finished Apr 30 01:57:41 PM PDT 24
Peak memory 204132 kb
Host smart-7e5c2e53-7f0a-42de-b239-240c438a7833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525244273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.525244273
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.2310536204
Short name T552
Test name
Test status
Simulation time 4243025224 ps
CPU time 22.45 seconds
Started Apr 30 01:57:32 PM PDT 24
Finished Apr 30 01:57:56 PM PDT 24
Peak memory 318056 kb
Host smart-4a142182-496f-4043-ab69-d8fc4e32a81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310536204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.2310536204
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.488972622
Short name T1240
Test name
Test status
Simulation time 117275605 ps
CPU time 0.62 seconds
Started Apr 30 01:57:22 PM PDT 24
Finished Apr 30 01:57:23 PM PDT 24
Peak memory 203808 kb
Host smart-1fa75732-39d9-4455-bc1b-5a6cec9548e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488972622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.488972622
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.3690991771
Short name T293
Test name
Test status
Simulation time 1238979309 ps
CPU time 23.15 seconds
Started Apr 30 01:57:23 PM PDT 24
Finished Apr 30 01:57:46 PM PDT 24
Peak memory 264880 kb
Host smart-599cc58b-ef96-48cb-ba77-4eb6b8782398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690991771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.3690991771
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.807962505
Short name T172
Test name
Test status
Simulation time 17296658968 ps
CPU time 717.12 seconds
Started Apr 30 01:57:28 PM PDT 24
Finished Apr 30 02:09:26 PM PDT 24
Peak memory 2319756 kb
Host smart-ac79facc-f151-4ca0-99af-2e3d25a23985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807962505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.807962505
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.793867902
Short name T1189
Test name
Test status
Simulation time 1621309301 ps
CPU time 19.17 seconds
Started Apr 30 01:57:21 PM PDT 24
Finished Apr 30 01:57:41 PM PDT 24
Peak memory 212412 kb
Host smart-628d0409-6101-4f45-9288-130ca1927473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793867902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.793867902
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.875313477
Short name T933
Test name
Test status
Simulation time 1426399373 ps
CPU time 2.16 seconds
Started Apr 30 01:57:27 PM PDT 24
Finished Apr 30 01:57:30 PM PDT 24
Peak memory 204128 kb
Host smart-013f972d-359b-4c93-9cd5-70d698eb84bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875313477 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.875313477
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1611128832
Short name T1090
Test name
Test status
Simulation time 10179572207 ps
CPU time 13.62 seconds
Started Apr 30 01:57:27 PM PDT 24
Finished Apr 30 01:57:41 PM PDT 24
Peak memory 253988 kb
Host smart-849d05d7-09ed-45f1-b606-8e3ee273a72b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611128832 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1611128832
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.3398791319
Short name T943
Test name
Test status
Simulation time 10393701451 ps
CPU time 9.61 seconds
Started Apr 30 01:57:28 PM PDT 24
Finished Apr 30 01:57:38 PM PDT 24
Peak memory 264532 kb
Host smart-7efe9027-9aba-4d25-aba5-cce937e12422
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398791319 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.3398791319
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.3963429037
Short name T896
Test name
Test status
Simulation time 1265063245 ps
CPU time 2.09 seconds
Started Apr 30 01:57:27 PM PDT 24
Finished Apr 30 01:57:30 PM PDT 24
Peak memory 204204 kb
Host smart-01a01b5c-7374-45a1-866b-2f5a73174fbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963429037 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.3963429037
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.1322204289
Short name T511
Test name
Test status
Simulation time 2301846390 ps
CPU time 3.25 seconds
Started Apr 30 01:57:29 PM PDT 24
Finished Apr 30 01:57:32 PM PDT 24
Peak memory 204316 kb
Host smart-3ccb7367-c6d7-47f4-8b49-8d1b9b3f9bc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322204289 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.1322204289
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.2016717467
Short name T644
Test name
Test status
Simulation time 16166112657 ps
CPU time 34.36 seconds
Started Apr 30 01:57:28 PM PDT 24
Finished Apr 30 01:58:03 PM PDT 24
Peak memory 661328 kb
Host smart-e1bcd809-4852-4670-b0d7-8e9da0f62e95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016717467 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.2016717467
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.1339154199
Short name T534
Test name
Test status
Simulation time 1022358683 ps
CPU time 10.6 seconds
Started Apr 30 01:57:27 PM PDT 24
Finished Apr 30 01:57:38 PM PDT 24
Peak memory 204156 kb
Host smart-3c0d94f5-e282-4af6-af7f-d192f5507f3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339154199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.1339154199
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.4172779832
Short name T898
Test name
Test status
Simulation time 1405450302 ps
CPU time 5.36 seconds
Started Apr 30 01:57:27 PM PDT 24
Finished Apr 30 01:57:33 PM PDT 24
Peak memory 204112 kb
Host smart-9626d313-8468-476d-bc11-d6079177d594
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172779832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.4172779832
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.3494760466
Short name T531
Test name
Test status
Simulation time 48113338218 ps
CPU time 1100.18 seconds
Started Apr 30 01:57:26 PM PDT 24
Finished Apr 30 02:15:47 PM PDT 24
Peak memory 7032168 kb
Host smart-14b75e7a-94b4-4e06-beb4-6dda0b4f64e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494760466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.3494760466
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.2657791207
Short name T1296
Test name
Test status
Simulation time 7369682346 ps
CPU time 22.43 seconds
Started Apr 30 01:57:28 PM PDT 24
Finished Apr 30 01:57:51 PM PDT 24
Peak memory 556888 kb
Host smart-0ce84d68-c3c1-4151-8f50-dc5379aa2898
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657791207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.2657791207
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.282537736
Short name T12
Test name
Test status
Simulation time 5133015277 ps
CPU time 6.71 seconds
Started Apr 30 01:57:26 PM PDT 24
Finished Apr 30 01:57:33 PM PDT 24
Peak memory 217556 kb
Host smart-274e0eec-23e2-4372-ac20-65f9ce352e50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282537736 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_timeout.282537736
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.936877696
Short name T328
Test name
Test status
Simulation time 89698322 ps
CPU time 0.67 seconds
Started Apr 30 01:57:39 PM PDT 24
Finished Apr 30 01:57:41 PM PDT 24
Peak memory 203836 kb
Host smart-1ff050eb-af01-4d7c-8805-350cb0c9849f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936877696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.936877696
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.283909045
Short name T295
Test name
Test status
Simulation time 92005767 ps
CPU time 1.65 seconds
Started Apr 30 01:57:33 PM PDT 24
Finished Apr 30 01:57:35 PM PDT 24
Peak memory 212484 kb
Host smart-6341dc2e-24b5-4809-a741-ad45e2481b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283909045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.283909045
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.1865138283
Short name T395
Test name
Test status
Simulation time 337996484 ps
CPU time 17.23 seconds
Started Apr 30 01:57:31 PM PDT 24
Finished Apr 30 01:57:49 PM PDT 24
Peak memory 277036 kb
Host smart-e4f9f775-7046-4474-a04f-166a73fa76c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865138283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.1865138283
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.4133476132
Short name T767
Test name
Test status
Simulation time 6722189852 ps
CPU time 43.93 seconds
Started Apr 30 01:57:34 PM PDT 24
Finished Apr 30 01:58:19 PM PDT 24
Peak memory 502388 kb
Host smart-fb3405fc-4623-4b4b-aecb-9dea0291d216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133476132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.4133476132
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.1597747218
Short name T1280
Test name
Test status
Simulation time 2386351458 ps
CPU time 73.85 seconds
Started Apr 30 01:57:33 PM PDT 24
Finished Apr 30 01:58:47 PM PDT 24
Peak memory 796664 kb
Host smart-edd10e66-f8c4-4b07-9297-8fa9f1f777e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597747218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.1597747218
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.287652837
Short name T211
Test name
Test status
Simulation time 273096646 ps
CPU time 1.04 seconds
Started Apr 30 01:57:35 PM PDT 24
Finished Apr 30 01:57:36 PM PDT 24
Peak memory 203992 kb
Host smart-e6c3c33f-9dd4-4743-8a2f-d4f396645dbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287652837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.287652837
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.779285397
Short name T1344
Test name
Test status
Simulation time 230101823 ps
CPU time 3.2 seconds
Started Apr 30 01:57:33 PM PDT 24
Finished Apr 30 01:57:37 PM PDT 24
Peak memory 222492 kb
Host smart-a5b63d03-a3c2-44fe-b66f-b3f716b25183
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779285397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.
779285397
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.1153641603
Short name T518
Test name
Test status
Simulation time 2792650824 ps
CPU time 75.69 seconds
Started Apr 30 01:57:32 PM PDT 24
Finished Apr 30 01:58:49 PM PDT 24
Peak memory 898668 kb
Host smart-87cbc1ab-9f6f-4aae-9d5a-215f2f970a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153641603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.1153641603
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.2852145532
Short name T494
Test name
Test status
Simulation time 1248751859 ps
CPU time 7.34 seconds
Started Apr 30 01:57:43 PM PDT 24
Finished Apr 30 01:57:51 PM PDT 24
Peak memory 203776 kb
Host smart-7c79e90a-b396-4a81-974f-a43571e3faec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852145532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.2852145532
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.790257691
Short name T601
Test name
Test status
Simulation time 3408785981 ps
CPU time 24.82 seconds
Started Apr 30 01:57:40 PM PDT 24
Finished Apr 30 01:58:05 PM PDT 24
Peak memory 299512 kb
Host smart-916f56a9-378a-4ac1-b17d-a8dbcb9f0949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790257691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.790257691
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.1117419240
Short name T1253
Test name
Test status
Simulation time 49572001 ps
CPU time 0.63 seconds
Started Apr 30 01:57:34 PM PDT 24
Finished Apr 30 01:57:35 PM PDT 24
Peak memory 203816 kb
Host smart-c5844b97-5e45-4c48-ade1-f8494ed9cd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117419240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1117419240
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.528017638
Short name T704
Test name
Test status
Simulation time 7723049915 ps
CPU time 37.84 seconds
Started Apr 30 01:57:37 PM PDT 24
Finished Apr 30 01:58:15 PM PDT 24
Peak memory 220288 kb
Host smart-cf844b1c-8175-4b18-a6f4-e9dbbb6eb51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528017638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.528017638
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.2785287552
Short name T940
Test name
Test status
Simulation time 1364892803 ps
CPU time 67.61 seconds
Started Apr 30 01:57:34 PM PDT 24
Finished Apr 30 01:58:42 PM PDT 24
Peak memory 350656 kb
Host smart-2bd28fc8-07ba-423e-b330-157ccadded23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785287552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.2785287552
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.3936129018
Short name T955
Test name
Test status
Simulation time 1158202541 ps
CPU time 9.62 seconds
Started Apr 30 01:57:34 PM PDT 24
Finished Apr 30 01:57:44 PM PDT 24
Peak memory 212364 kb
Host smart-d73b8bc4-fe57-4436-b13f-45ad19d1dd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936129018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.3936129018
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.1131144336
Short name T580
Test name
Test status
Simulation time 3448400168 ps
CPU time 3.7 seconds
Started Apr 30 01:57:36 PM PDT 24
Finished Apr 30 01:57:40 PM PDT 24
Peak memory 204264 kb
Host smart-9891e1f1-855c-4abe-bc35-f7f57291050a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131144336 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.1131144336
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.1938333335
Short name T374
Test name
Test status
Simulation time 10123352052 ps
CPU time 13.96 seconds
Started Apr 30 01:57:35 PM PDT 24
Finished Apr 30 01:57:49 PM PDT 24
Peak memory 261800 kb
Host smart-aa9def4a-dfc6-42cc-9ecc-5e0ce3074e24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938333335 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.1938333335
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3207087886
Short name T1029
Test name
Test status
Simulation time 10046413463 ps
CPU time 71.36 seconds
Started Apr 30 01:57:32 PM PDT 24
Finished Apr 30 01:58:44 PM PDT 24
Peak memory 573228 kb
Host smart-4829b2b8-0db9-49df-97ff-b8b8e49145cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207087886 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.3207087886
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.3408063801
Short name T579
Test name
Test status
Simulation time 982877025 ps
CPU time 2.89 seconds
Started Apr 30 01:57:36 PM PDT 24
Finished Apr 30 01:57:39 PM PDT 24
Peak memory 204184 kb
Host smart-750f4a73-70be-4289-b320-7de0cd64c3ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408063801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.3408063801
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3562952571
Short name T781
Test name
Test status
Simulation time 813523043 ps
CPU time 4.09 seconds
Started Apr 30 01:57:33 PM PDT 24
Finished Apr 30 01:57:38 PM PDT 24
Peak memory 204208 kb
Host smart-a372561b-95b8-47e8-b8ba-92fdfde348e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562952571 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3562952571
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.1260051227
Short name T409
Test name
Test status
Simulation time 6581716245 ps
CPU time 11.01 seconds
Started Apr 30 01:57:31 PM PDT 24
Finished Apr 30 01:57:43 PM PDT 24
Peak memory 511396 kb
Host smart-e66b30c9-4315-4edb-94c6-7e72f5faed90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260051227 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.1260051227
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3139829404
Short name T540
Test name
Test status
Simulation time 1397964531 ps
CPU time 10.79 seconds
Started Apr 30 01:57:37 PM PDT 24
Finished Apr 30 01:57:48 PM PDT 24
Peak memory 204036 kb
Host smart-8c11ec5a-2ae1-4a89-9f6e-fd09254d0ab1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139829404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3139829404
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.3559545762
Short name T498
Test name
Test status
Simulation time 844792871 ps
CPU time 36.51 seconds
Started Apr 30 01:57:33 PM PDT 24
Finished Apr 30 01:58:10 PM PDT 24
Peak memory 204128 kb
Host smart-6cd3150a-840a-4406-847f-c4335eb3865c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559545762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.3559545762
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.511736623
Short name T783
Test name
Test status
Simulation time 23341854779 ps
CPU time 44.4 seconds
Started Apr 30 01:57:33 PM PDT 24
Finished Apr 30 01:58:18 PM PDT 24
Peak memory 725964 kb
Host smart-92ff1cbe-6160-4141-93e1-0d0b05d39792
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511736623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_wr.511736623
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.565523698
Short name T632
Test name
Test status
Simulation time 34343307421 ps
CPU time 2744 seconds
Started Apr 30 01:57:33 PM PDT 24
Finished Apr 30 02:43:18 PM PDT 24
Peak memory 7651492 kb
Host smart-fae852a2-ed40-4d4c-b66b-a4e8a363c87b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565523698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_t
arget_stretch.565523698
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.3425503311
Short name T11
Test name
Test status
Simulation time 5754176427 ps
CPU time 6.99 seconds
Started Apr 30 01:57:35 PM PDT 24
Finished Apr 30 01:57:43 PM PDT 24
Peak memory 212444 kb
Host smart-d25ea38c-2381-4d04-8ac9-785ffa6b5869
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425503311 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.3425503311
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.1097129917
Short name T103
Test name
Test status
Simulation time 48836527 ps
CPU time 0.62 seconds
Started Apr 30 01:57:46 PM PDT 24
Finished Apr 30 01:57:47 PM PDT 24
Peak memory 203836 kb
Host smart-b3a7fe0f-4c22-40d4-9d59-6c4b3239b2b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097129917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.1097129917
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.1889467550
Short name T724
Test name
Test status
Simulation time 697970436 ps
CPU time 1.79 seconds
Started Apr 30 01:57:41 PM PDT 24
Finished Apr 30 01:57:43 PM PDT 24
Peak memory 212408 kb
Host smart-0bc4cae6-5dbc-4556-80d0-44a48c3d4f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889467550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.1889467550
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.2584253176
Short name T988
Test name
Test status
Simulation time 218528336 ps
CPU time 4.4 seconds
Started Apr 30 01:57:40 PM PDT 24
Finished Apr 30 01:57:45 PM PDT 24
Peak memory 247820 kb
Host smart-42b37933-8410-4092-9346-4a879917f331
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584253176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.2584253176
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2963237867
Short name T89
Test name
Test status
Simulation time 8183011687 ps
CPU time 56.9 seconds
Started Apr 30 01:57:40 PM PDT 24
Finished Apr 30 01:58:38 PM PDT 24
Peak memory 598812 kb
Host smart-37d5d3af-bbd0-4092-80ce-bbfc190d057a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963237867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2963237867
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.2867417717
Short name T686
Test name
Test status
Simulation time 1291188575 ps
CPU time 77.13 seconds
Started Apr 30 01:57:40 PM PDT 24
Finished Apr 30 01:58:58 PM PDT 24
Peak memory 435912 kb
Host smart-a58d6383-631f-480a-8812-b84a6bb58d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867417717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2867417717
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.2015186355
Short name T953
Test name
Test status
Simulation time 1341396714 ps
CPU time 1.03 seconds
Started Apr 30 01:57:39 PM PDT 24
Finished Apr 30 01:57:40 PM PDT 24
Peak memory 204096 kb
Host smart-13a096d2-24d2-41eb-8063-083a4645a5b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015186355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.2015186355
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.3220737770
Short name T208
Test name
Test status
Simulation time 129900551 ps
CPU time 7.51 seconds
Started Apr 30 01:57:39 PM PDT 24
Finished Apr 30 01:57:47 PM PDT 24
Peak memory 225580 kb
Host smart-54353789-1254-4d55-82cd-6d205f6b96ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220737770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.3220737770
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.1413877598
Short name T321
Test name
Test status
Simulation time 2354556033 ps
CPU time 54.41 seconds
Started Apr 30 01:57:41 PM PDT 24
Finished Apr 30 01:58:36 PM PDT 24
Peak memory 714100 kb
Host smart-1fd30933-def4-475d-8a38-a8b52e820e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413877598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.1413877598
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.1008446911
Short name T308
Test name
Test status
Simulation time 927187817 ps
CPU time 9.79 seconds
Started Apr 30 01:57:46 PM PDT 24
Finished Apr 30 01:57:57 PM PDT 24
Peak memory 204116 kb
Host smart-03e778dc-7c67-4a62-9bee-4428209bf80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008446911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.1008446911
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.812427455
Short name T377
Test name
Test status
Simulation time 7425670944 ps
CPU time 57.88 seconds
Started Apr 30 01:57:45 PM PDT 24
Finished Apr 30 01:58:43 PM PDT 24
Peak memory 381384 kb
Host smart-024f348d-740c-4887-9539-10bb461a9ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812427455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.812427455
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.782510628
Short name T224
Test name
Test status
Simulation time 38875793 ps
CPU time 0.66 seconds
Started Apr 30 01:57:39 PM PDT 24
Finished Apr 30 01:57:40 PM PDT 24
Peak memory 203872 kb
Host smart-ab0bcc33-b36f-4f6e-aeb4-f6f069281231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782510628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.782510628
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.2815206390
Short name T1355
Test name
Test status
Simulation time 2731453689 ps
CPU time 28.19 seconds
Started Apr 30 01:57:41 PM PDT 24
Finished Apr 30 01:58:10 PM PDT 24
Peak memory 204472 kb
Host smart-6b988420-0587-47c4-8ffe-df3b75497ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815206390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2815206390
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.1582362337
Short name T944
Test name
Test status
Simulation time 8674674075 ps
CPU time 66.22 seconds
Started Apr 30 01:57:39 PM PDT 24
Finished Apr 30 01:58:46 PM PDT 24
Peak memory 304096 kb
Host smart-b761f6e6-7d53-4bae-941b-2f0be9984ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582362337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.1582362337
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.2835461464
Short name T682
Test name
Test status
Simulation time 35743102613 ps
CPU time 489.86 seconds
Started Apr 30 01:57:42 PM PDT 24
Finished Apr 30 02:05:52 PM PDT 24
Peak memory 2284888 kb
Host smart-f1fc42a6-d5b9-49df-a4e5-a1ecc3520214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835461464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.2835461464
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.208125950
Short name T1167
Test name
Test status
Simulation time 3328535958 ps
CPU time 10.32 seconds
Started Apr 30 01:57:38 PM PDT 24
Finished Apr 30 01:57:48 PM PDT 24
Peak memory 220480 kb
Host smart-32a7c553-59f9-4d88-bce7-4caeefb39b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208125950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.208125950
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.1950094590
Short name T1243
Test name
Test status
Simulation time 668478210 ps
CPU time 3.77 seconds
Started Apr 30 01:57:42 PM PDT 24
Finished Apr 30 01:57:46 PM PDT 24
Peak memory 212072 kb
Host smart-420083a5-49b3-4ae2-a9fa-57ad5b567178
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950094590 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.1950094590
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.3314479633
Short name T85
Test name
Test status
Simulation time 10450802998 ps
CPU time 8.57 seconds
Started Apr 30 01:57:42 PM PDT 24
Finished Apr 30 01:57:50 PM PDT 24
Peak memory 261092 kb
Host smart-2d924e0f-ce8e-476f-aa21-8b92a7617eab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314479633 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.3314479633
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1606969122
Short name T1293
Test name
Test status
Simulation time 10403359708 ps
CPU time 15.83 seconds
Started Apr 30 01:57:43 PM PDT 24
Finished Apr 30 01:57:59 PM PDT 24
Peak memory 297800 kb
Host smart-1963e434-357b-4fe1-bb3b-b54c6ff76d8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606969122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1606969122
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.1093501145
Short name T1121
Test name
Test status
Simulation time 1235544048 ps
CPU time 2.14 seconds
Started Apr 30 01:57:43 PM PDT 24
Finished Apr 30 01:57:45 PM PDT 24
Peak memory 204156 kb
Host smart-a652b21b-934e-4548-b4da-909f5c4cf451
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093501145 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.1093501145
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.70062728
Short name T1173
Test name
Test status
Simulation time 955144769 ps
CPU time 5.46 seconds
Started Apr 30 01:57:44 PM PDT 24
Finished Apr 30 01:57:50 PM PDT 24
Peak memory 217596 kb
Host smart-c4f4fff9-46c8-4e3c-99f5-e2069b22a11c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70062728 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_intr_smoke.70062728
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.1350038446
Short name T565
Test name
Test status
Simulation time 11576288715 ps
CPU time 75.83 seconds
Started Apr 30 01:57:43 PM PDT 24
Finished Apr 30 01:58:59 PM PDT 24
Peak memory 1320212 kb
Host smart-2fd634f6-7b71-468d-8014-196a1ad3a041
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350038446 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.1350038446
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.338610293
Short name T1111
Test name
Test status
Simulation time 4096832042 ps
CPU time 14.98 seconds
Started Apr 30 01:57:44 PM PDT 24
Finished Apr 30 01:57:59 PM PDT 24
Peak memory 204160 kb
Host smart-40abdf81-fd22-4fce-8143-e81999db3284
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338610293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_tar
get_smoke.338610293
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.1958171990
Short name T1023
Test name
Test status
Simulation time 553562260 ps
CPU time 8.47 seconds
Started Apr 30 01:57:39 PM PDT 24
Finished Apr 30 01:57:48 PM PDT 24
Peak memory 206220 kb
Host smart-dbee1965-7b0f-4b58-a147-82d77af9d4a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958171990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.1958171990
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.604576679
Short name T847
Test name
Test status
Simulation time 27335874867 ps
CPU time 131.29 seconds
Started Apr 30 01:57:43 PM PDT 24
Finished Apr 30 01:59:55 PM PDT 24
Peak memory 1806724 kb
Host smart-c9f7e7b9-6a3c-4da4-9b11-001ca1ff5450
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604576679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_wr.604576679
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.988780897
Short name T266
Test name
Test status
Simulation time 25862153685 ps
CPU time 1828.29 seconds
Started Apr 30 01:57:40 PM PDT 24
Finished Apr 30 02:28:09 PM PDT 24
Peak memory 5895332 kb
Host smart-b79de5f2-68a4-4726-8497-0b8179f5e8ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988780897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_t
arget_stretch.988780897
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.849958623
Short name T353
Test name
Test status
Simulation time 5075916587 ps
CPU time 6.55 seconds
Started Apr 30 01:57:41 PM PDT 24
Finished Apr 30 01:57:48 PM PDT 24
Peak memory 212392 kb
Host smart-76627cb3-059d-448c-9d84-ce595ace8e22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849958623 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_timeout.849958623
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_unexp_stop.593356638
Short name T28
Test name
Test status
Simulation time 1767032074 ps
CPU time 5.51 seconds
Started Apr 30 01:57:40 PM PDT 24
Finished Apr 30 01:57:46 PM PDT 24
Peak memory 214380 kb
Host smart-cbf47086-59a4-4076-b759-68695f7f12c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593356638 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_unexp_stop.593356638
Directory /workspace/44.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/45.i2c_alert_test.89235379
Short name T356
Test name
Test status
Simulation time 57131739 ps
CPU time 0.65 seconds
Started Apr 30 01:57:54 PM PDT 24
Finished Apr 30 01:57:55 PM PDT 24
Peak memory 203924 kb
Host smart-8694f22f-6a75-47c6-9cb1-cb1aecf190d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89235379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.89235379
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.3585758172
Short name T369
Test name
Test status
Simulation time 191015111 ps
CPU time 1.5 seconds
Started Apr 30 01:57:45 PM PDT 24
Finished Apr 30 01:57:47 PM PDT 24
Peak memory 212492 kb
Host smart-fc336cb8-d178-49d9-99ad-c6c9d46234e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585758172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3585758172
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.1174315416
Short name T613
Test name
Test status
Simulation time 593597400 ps
CPU time 7.34 seconds
Started Apr 30 01:57:44 PM PDT 24
Finished Apr 30 01:57:52 PM PDT 24
Peak memory 272672 kb
Host smart-db70f0ed-2444-4998-901a-ae02734529f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174315416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.1174315416
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.1791247441
Short name T916
Test name
Test status
Simulation time 1669370611 ps
CPU time 40.78 seconds
Started Apr 30 01:57:45 PM PDT 24
Finished Apr 30 01:58:26 PM PDT 24
Peak memory 305904 kb
Host smart-45ba78e2-42d9-4a94-8a17-510b0536416d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791247441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.1791247441
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.426435945
Short name T1041
Test name
Test status
Simulation time 2167237974 ps
CPU time 54.39 seconds
Started Apr 30 01:57:46 PM PDT 24
Finished Apr 30 01:58:41 PM PDT 24
Peak memory 602392 kb
Host smart-515043d4-9aaa-4afa-a09b-8300723e5a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426435945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.426435945
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.3909201044
Short name T450
Test name
Test status
Simulation time 510885617 ps
CPU time 1.08 seconds
Started Apr 30 01:57:45 PM PDT 24
Finished Apr 30 01:57:46 PM PDT 24
Peak memory 204180 kb
Host smart-d4907522-817a-4285-bb57-20c3a659e611
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909201044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.3909201044
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.1966050258
Short name T720
Test name
Test status
Simulation time 518944838 ps
CPU time 7.88 seconds
Started Apr 30 01:57:45 PM PDT 24
Finished Apr 30 01:57:53 PM PDT 24
Peak memory 225388 kb
Host smart-f99e572f-a87d-4d3a-8695-f5e531c921ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966050258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.1966050258
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.3823646865
Short name T102
Test name
Test status
Simulation time 3743260513 ps
CPU time 99.79 seconds
Started Apr 30 01:57:45 PM PDT 24
Finished Apr 30 01:59:25 PM PDT 24
Peak memory 1133488 kb
Host smart-881c26ed-9095-48bb-bc9e-93c841669679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823646865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.3823646865
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.44626896
Short name T70
Test name
Test status
Simulation time 838304294 ps
CPU time 5.3 seconds
Started Apr 30 01:57:56 PM PDT 24
Finished Apr 30 01:58:01 PM PDT 24
Peak memory 204216 kb
Host smart-1ad97e4b-e886-4443-8d59-9fcbe2d62d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44626896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.44626896
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.293558153
Short name T202
Test name
Test status
Simulation time 18545392041 ps
CPU time 34.98 seconds
Started Apr 30 01:57:53 PM PDT 24
Finished Apr 30 01:58:28 PM PDT 24
Peak memory 301636 kb
Host smart-a4f7d743-29ff-4c95-aeeb-99ab6af6c3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293558153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.293558153
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.1007505349
Short name T528
Test name
Test status
Simulation time 78375442 ps
CPU time 0.68 seconds
Started Apr 30 01:57:45 PM PDT 24
Finished Apr 30 01:57:46 PM PDT 24
Peak memory 203760 kb
Host smart-4246d85b-8386-4c71-bbe0-f8a350d71e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007505349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.1007505349
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.3300433408
Short name T71
Test name
Test status
Simulation time 7164917197 ps
CPU time 22.48 seconds
Started Apr 30 01:57:45 PM PDT 24
Finished Apr 30 01:58:08 PM PDT 24
Peak memory 220448 kb
Host smart-02ec41cf-4f63-4a76-acdf-4c716f2d12f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300433408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.3300433408
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.1358207845
Short name T263
Test name
Test status
Simulation time 1355063934 ps
CPU time 20.9 seconds
Started Apr 30 01:57:46 PM PDT 24
Finished Apr 30 01:58:07 PM PDT 24
Peak memory 310592 kb
Host smart-e71cc88b-a3ec-4397-a0cf-0147ea263521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358207845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.1358207845
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.1708486870
Short name T214
Test name
Test status
Simulation time 21431543550 ps
CPU time 440.13 seconds
Started Apr 30 01:57:46 PM PDT 24
Finished Apr 30 02:05:06 PM PDT 24
Peak memory 1930300 kb
Host smart-5f550edc-f699-4cce-b7ea-98312d05e65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708486870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.1708486870
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.2540588207
Short name T1046
Test name
Test status
Simulation time 1063921141 ps
CPU time 14.58 seconds
Started Apr 30 01:57:46 PM PDT 24
Finished Apr 30 01:58:01 PM PDT 24
Peak memory 229600 kb
Host smart-e5a60964-5f26-4711-aa5c-34c99c4f601a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540588207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.2540588207
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.1691375928
Short name T731
Test name
Test status
Simulation time 1248447919 ps
CPU time 3.67 seconds
Started Apr 30 01:57:57 PM PDT 24
Finished Apr 30 01:58:01 PM PDT 24
Peak memory 203692 kb
Host smart-4cfe86e6-864c-4dd8-84bd-1ae689eb7b75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691375928 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.1691375928
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.3370808
Short name T1159
Test name
Test status
Simulation time 10085179126 ps
CPU time 28.06 seconds
Started Apr 30 01:57:53 PM PDT 24
Finished Apr 30 01:58:22 PM PDT 24
Peak memory 328668 kb
Host smart-0f5e1474-bbd4-4e6d-9eb2-aaa88df2fe2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370808 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.i2c_target_fifo_reset_tx.3370808
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.1609536608
Short name T378
Test name
Test status
Simulation time 1150469347 ps
CPU time 5.89 seconds
Started Apr 30 01:57:54 PM PDT 24
Finished Apr 30 01:58:01 PM PDT 24
Peak memory 212436 kb
Host smart-49563cab-2549-44c3-adf9-edc8e5ec2d50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609536608 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.1609536608
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.3701721992
Short name T576
Test name
Test status
Simulation time 11271115180 ps
CPU time 26.02 seconds
Started Apr 30 01:57:51 PM PDT 24
Finished Apr 30 01:58:18 PM PDT 24
Peak memory 597144 kb
Host smart-579c13e1-967b-4d93-9826-db19b9655be3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701721992 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.3701721992
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.1821883627
Short name T618
Test name
Test status
Simulation time 580484435 ps
CPU time 20.22 seconds
Started Apr 30 01:57:47 PM PDT 24
Finished Apr 30 01:58:08 PM PDT 24
Peak memory 204136 kb
Host smart-6ec1461f-d5a0-4eb5-8f3b-8ea3099d3c0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821883627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.1821883627
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.3961034388
Short name T801
Test name
Test status
Simulation time 2972780650 ps
CPU time 27.18 seconds
Started Apr 30 01:57:52 PM PDT 24
Finished Apr 30 01:58:19 PM PDT 24
Peak memory 218792 kb
Host smart-10b75e1d-f3cd-4fa8-b471-d09afd2a94a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961034388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.3961034388
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.3718743344
Short name T747
Test name
Test status
Simulation time 16563319242 ps
CPU time 30.7 seconds
Started Apr 30 01:57:45 PM PDT 24
Finished Apr 30 01:58:16 PM PDT 24
Peak memory 204216 kb
Host smart-db9218a7-caf8-4e56-91b5-389c12385dfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718743344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.3718743344
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.3953483044
Short name T1247
Test name
Test status
Simulation time 2787829586 ps
CPU time 7.33 seconds
Started Apr 30 01:57:53 PM PDT 24
Finished Apr 30 01:58:00 PM PDT 24
Peak memory 217068 kb
Host smart-52c10d02-d286-4e9f-b43f-b2ea095ff60c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953483044 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.3953483044
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.2598260549
Short name T512
Test name
Test status
Simulation time 66684478 ps
CPU time 0.62 seconds
Started Apr 30 01:57:58 PM PDT 24
Finished Apr 30 01:57:59 PM PDT 24
Peak memory 203896 kb
Host smart-cefffcaf-8dee-44cd-8ce6-660dfc220cdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598260549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.2598260549
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.299334393
Short name T909
Test name
Test status
Simulation time 187625189 ps
CPU time 1.58 seconds
Started Apr 30 01:58:01 PM PDT 24
Finished Apr 30 01:58:03 PM PDT 24
Peak memory 212384 kb
Host smart-0524ebd6-2e8a-4212-a878-4d5876165a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299334393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.299334393
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.4281311475
Short name T578
Test name
Test status
Simulation time 642442117 ps
CPU time 7.01 seconds
Started Apr 30 01:57:59 PM PDT 24
Finished Apr 30 01:58:07 PM PDT 24
Peak memory 270408 kb
Host smart-a50cbe67-0bc7-42d9-b099-6018d7084a52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281311475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.4281311475
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.243098761
Short name T1112
Test name
Test status
Simulation time 2503027515 ps
CPU time 154.46 seconds
Started Apr 30 01:58:00 PM PDT 24
Finished Apr 30 02:00:35 PM PDT 24
Peak memory 632576 kb
Host smart-0984d49a-ee97-4f23-a836-3db7fffe98d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243098761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.243098761
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.2431298813
Short name T739
Test name
Test status
Simulation time 7111561047 ps
CPU time 48.66 seconds
Started Apr 30 01:57:58 PM PDT 24
Finished Apr 30 01:58:48 PM PDT 24
Peak memory 600508 kb
Host smart-f12c7c5c-b110-45a0-b54d-a672b0e71f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431298813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2431298813
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.632198383
Short name T978
Test name
Test status
Simulation time 653006331 ps
CPU time 1.08 seconds
Started Apr 30 01:57:59 PM PDT 24
Finished Apr 30 01:58:00 PM PDT 24
Peak memory 204164 kb
Host smart-2c81c455-6cbe-4965-8b13-2cf7ad5b4fa5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632198383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fm
t.632198383
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.566130444
Short name T920
Test name
Test status
Simulation time 799543557 ps
CPU time 5.09 seconds
Started Apr 30 01:57:57 PM PDT 24
Finished Apr 30 01:58:02 PM PDT 24
Peak memory 242604 kb
Host smart-ad428ffd-ac60-403b-926e-26ad871b0a7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566130444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.
566130444
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.4137215251
Short name T761
Test name
Test status
Simulation time 3289576301 ps
CPU time 98.68 seconds
Started Apr 30 01:57:59 PM PDT 24
Finished Apr 30 01:59:39 PM PDT 24
Peak memory 1022120 kb
Host smart-50e38237-22fd-46aa-a694-49788e5866b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137215251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.4137215251
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.2989716861
Short name T968
Test name
Test status
Simulation time 437443442 ps
CPU time 3.18 seconds
Started Apr 30 01:57:59 PM PDT 24
Finished Apr 30 01:58:03 PM PDT 24
Peak memory 204132 kb
Host smart-de427b2e-300e-4345-9014-20ec98eb3ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989716861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.2989716861
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.583941468
Short name T1059
Test name
Test status
Simulation time 6478937762 ps
CPU time 34.35 seconds
Started Apr 30 01:57:57 PM PDT 24
Finished Apr 30 01:58:32 PM PDT 24
Peak memory 415444 kb
Host smart-5bdc2ac5-673d-4af5-aa46-4d9012d3f4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583941468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.583941468
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.3737487295
Short name T683
Test name
Test status
Simulation time 28730285 ps
CPU time 0.69 seconds
Started Apr 30 01:57:52 PM PDT 24
Finished Apr 30 01:57:53 PM PDT 24
Peak memory 203872 kb
Host smart-c236584c-4c69-47f9-96da-e93550765ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737487295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.3737487295
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.1589237146
Short name T726
Test name
Test status
Simulation time 7070120282 ps
CPU time 75.34 seconds
Started Apr 30 01:58:01 PM PDT 24
Finished Apr 30 01:59:17 PM PDT 24
Peak memory 204244 kb
Host smart-878e912e-babe-4089-a55c-77f0b916b9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589237146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.1589237146
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.1864278402
Short name T1129
Test name
Test status
Simulation time 5964136062 ps
CPU time 24.98 seconds
Started Apr 30 01:57:51 PM PDT 24
Finished Apr 30 01:58:17 PM PDT 24
Peak memory 348408 kb
Host smart-f7c80caf-baf8-4c14-8e9c-0ab7e0e25adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864278402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.1864278402
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.2708695758
Short name T285
Test name
Test status
Simulation time 1323275807 ps
CPU time 15.27 seconds
Started Apr 30 01:57:56 PM PDT 24
Finished Apr 30 01:58:12 PM PDT 24
Peak memory 212364 kb
Host smart-acb4306d-74fd-4117-92dc-7cd932ec783d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708695758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2708695758
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.2347057641
Short name T177
Test name
Test status
Simulation time 1660824473 ps
CPU time 3.96 seconds
Started Apr 30 01:57:59 PM PDT 24
Finished Apr 30 01:58:04 PM PDT 24
Peak memory 204148 kb
Host smart-a686f1d1-c34c-4574-a2ad-a0f5eccc29f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347057641 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.2347057641
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.125667983
Short name T695
Test name
Test status
Simulation time 11219381260 ps
CPU time 6.41 seconds
Started Apr 30 01:58:00 PM PDT 24
Finished Apr 30 01:58:07 PM PDT 24
Peak memory 224292 kb
Host smart-920af7ab-0860-441b-b7e0-e2b132228044
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125667983 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_acq.125667983
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.795866459
Short name T282
Test name
Test status
Simulation time 10283034082 ps
CPU time 13.56 seconds
Started Apr 30 01:58:01 PM PDT 24
Finished Apr 30 01:58:15 PM PDT 24
Peak memory 296000 kb
Host smart-09b2c004-eb81-4bc9-91e8-d8dc3283d2c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795866459 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_tx.795866459
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.3358241057
Short name T1320
Test name
Test status
Simulation time 687853176 ps
CPU time 2.29 seconds
Started Apr 30 01:57:59 PM PDT 24
Finished Apr 30 01:58:02 PM PDT 24
Peak memory 204168 kb
Host smart-f532938e-665d-4270-99f9-f078b4fd4ff0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358241057 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.3358241057
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.3260227348
Short name T31
Test name
Test status
Simulation time 1034945062 ps
CPU time 3.22 seconds
Started Apr 30 01:57:57 PM PDT 24
Finished Apr 30 01:58:01 PM PDT 24
Peak memory 204116 kb
Host smart-a447b576-deac-4f3d-848d-daa7dacdbd9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260227348 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.3260227348
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.1523866763
Short name T1036
Test name
Test status
Simulation time 41597642720 ps
CPU time 22.95 seconds
Started Apr 30 01:57:58 PM PDT 24
Finished Apr 30 01:58:21 PM PDT 24
Peak memory 553736 kb
Host smart-ab476a0f-7e2c-4428-a6a9-651a1f24de11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523866763 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.1523866763
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.3869029106
Short name T332
Test name
Test status
Simulation time 787132669 ps
CPU time 10.21 seconds
Started Apr 30 01:57:59 PM PDT 24
Finished Apr 30 01:58:09 PM PDT 24
Peak memory 204180 kb
Host smart-61d313c4-b157-46e3-a0e1-da8d89df7c9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869029106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.3869029106
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.1004684500
Short name T1317
Test name
Test status
Simulation time 250089126 ps
CPU time 3.75 seconds
Started Apr 30 01:57:58 PM PDT 24
Finished Apr 30 01:58:02 PM PDT 24
Peak memory 204152 kb
Host smart-b931c810-e173-47cd-959d-9cc08c1b5600
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004684500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.1004684500
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.1931762644
Short name T1033
Test name
Test status
Simulation time 10312049579 ps
CPU time 19.52 seconds
Started Apr 30 01:58:00 PM PDT 24
Finished Apr 30 01:58:20 PM PDT 24
Peak memory 204184 kb
Host smart-91352d04-57c9-47d3-a56a-5697c5617831
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931762644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.1931762644
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.955500118
Short name T1339
Test name
Test status
Simulation time 26060535723 ps
CPU time 145.7 seconds
Started Apr 30 01:57:59 PM PDT 24
Finished Apr 30 02:00:25 PM PDT 24
Peak memory 1493916 kb
Host smart-822a568d-1db0-4e2f-acc1-6a004563a86c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955500118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_t
arget_stretch.955500118
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.436373447
Short name T345
Test name
Test status
Simulation time 1303273040 ps
CPU time 6.78 seconds
Started Apr 30 01:57:59 PM PDT 24
Finished Apr 30 01:58:06 PM PDT 24
Peak memory 218532 kb
Host smart-c7573d6e-373a-473b-85de-da75677c2ccc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436373447 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_timeout.436373447
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.704645779
Short name T570
Test name
Test status
Simulation time 122319145 ps
CPU time 0.6 seconds
Started Apr 30 01:58:05 PM PDT 24
Finished Apr 30 01:58:06 PM PDT 24
Peak memory 203880 kb
Host smart-997d6f16-9d75-442f-9d55-651f1fc1f580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704645779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.704645779
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.1972009589
Short name T728
Test name
Test status
Simulation time 118274442 ps
CPU time 1.23 seconds
Started Apr 30 01:58:05 PM PDT 24
Finished Apr 30 01:58:07 PM PDT 24
Peak memory 212392 kb
Host smart-080af2f2-08fe-4d21-86f2-ccfda9048d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972009589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.1972009589
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.4261822796
Short name T894
Test name
Test status
Simulation time 2093735495 ps
CPU time 30.37 seconds
Started Apr 30 01:57:59 PM PDT 24
Finished Apr 30 01:58:30 PM PDT 24
Peak memory 311944 kb
Host smart-6dbc6ebe-0557-4a9b-a21c-a52e63802a5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261822796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.4261822796
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1099943299
Short name T539
Test name
Test status
Simulation time 1930857497 ps
CPU time 41.39 seconds
Started Apr 30 01:58:01 PM PDT 24
Finished Apr 30 01:58:43 PM PDT 24
Peak memory 343524 kb
Host smart-f6d06982-7454-46a1-86d7-4fe6d21a94be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099943299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1099943299
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.821990291
Short name T875
Test name
Test status
Simulation time 1873889047 ps
CPU time 60.3 seconds
Started Apr 30 01:57:58 PM PDT 24
Finished Apr 30 01:58:59 PM PDT 24
Peak memory 608428 kb
Host smart-68cdceb6-a41b-4afc-b6d5-c24cc0101bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821990291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.821990291
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1090886418
Short name T473
Test name
Test status
Simulation time 399771688 ps
CPU time 0.94 seconds
Started Apr 30 01:57:59 PM PDT 24
Finished Apr 30 01:58:01 PM PDT 24
Peak memory 203952 kb
Host smart-b758632e-5462-4373-b07f-66d2f07d71e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090886418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.1090886418
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1021031627
Short name T433
Test name
Test status
Simulation time 251550706 ps
CPU time 7.19 seconds
Started Apr 30 01:57:59 PM PDT 24
Finished Apr 30 01:58:07 PM PDT 24
Peak memory 204140 kb
Host smart-d1ac2637-9c3e-465e-97a7-1ea1609dbd24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021031627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.1021031627
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.4113662963
Short name T608
Test name
Test status
Simulation time 4464439857 ps
CPU time 60.91 seconds
Started Apr 30 01:58:01 PM PDT 24
Finished Apr 30 01:59:02 PM PDT 24
Peak memory 760032 kb
Host smart-f38f3c68-9288-41b8-b9dd-1cb7e41f0663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113662963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.4113662963
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.1921248858
Short name T1055
Test name
Test status
Simulation time 448543778 ps
CPU time 5.51 seconds
Started Apr 30 01:58:04 PM PDT 24
Finished Apr 30 01:58:10 PM PDT 24
Peak memory 204180 kb
Host smart-46d29e66-6c1f-4bb4-b029-7c38b75179dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921248858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.1921248858
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.461497684
Short name T439
Test name
Test status
Simulation time 1176984838 ps
CPU time 53.22 seconds
Started Apr 30 01:58:04 PM PDT 24
Finished Apr 30 01:58:57 PM PDT 24
Peak memory 284608 kb
Host smart-405bcb7f-d7a1-4b23-af12-409d2865172b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461497684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.461497684
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.4017444543
Short name T1323
Test name
Test status
Simulation time 46766061 ps
CPU time 0.7 seconds
Started Apr 30 01:58:00 PM PDT 24
Finished Apr 30 01:58:01 PM PDT 24
Peak memory 203764 kb
Host smart-884e5203-0455-4448-b677-473d84dbb58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017444543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.4017444543
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.1228916664
Short name T1190
Test name
Test status
Simulation time 1429327929 ps
CPU time 15.38 seconds
Started Apr 30 01:57:59 PM PDT 24
Finished Apr 30 01:58:15 PM PDT 24
Peak memory 212344 kb
Host smart-3be961f1-67d3-430b-aef6-a5ee8abc2b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228916664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.1228916664
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.4093596211
Short name T95
Test name
Test status
Simulation time 1385128739 ps
CPU time 21.96 seconds
Started Apr 30 01:57:58 PM PDT 24
Finished Apr 30 01:58:20 PM PDT 24
Peak memory 349340 kb
Host smart-18a94518-28be-44d0-a059-449aaa2a1f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093596211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.4093596211
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.2455902004
Short name T751
Test name
Test status
Simulation time 79390467163 ps
CPU time 670.29 seconds
Started Apr 30 01:58:07 PM PDT 24
Finished Apr 30 02:09:18 PM PDT 24
Peak memory 2899492 kb
Host smart-f6698acc-6207-4f4c-937b-d37b00a8688b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455902004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.2455902004
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.3663978851
Short name T7
Test name
Test status
Simulation time 2727490337 ps
CPU time 30.91 seconds
Started Apr 30 01:58:08 PM PDT 24
Finished Apr 30 01:58:40 PM PDT 24
Peak memory 212424 kb
Host smart-127fe81a-4d58-45b5-931e-89a4677da99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663978851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.3663978851
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.3187993759
Short name T1298
Test name
Test status
Simulation time 4725973246 ps
CPU time 3.59 seconds
Started Apr 30 01:58:07 PM PDT 24
Finished Apr 30 01:58:11 PM PDT 24
Peak memory 204168 kb
Host smart-17767906-feca-418c-acbd-fb01fe9aecc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187993759 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.3187993759
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.714808150
Short name T233
Test name
Test status
Simulation time 10077622692 ps
CPU time 18.86 seconds
Started Apr 30 01:58:08 PM PDT 24
Finished Apr 30 01:58:27 PM PDT 24
Peak memory 262428 kb
Host smart-6202ef23-1583-4577-b912-f08ff17e886b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714808150 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_acq.714808150
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.3010792308
Short name T54
Test name
Test status
Simulation time 10051850464 ps
CPU time 28.49 seconds
Started Apr 30 01:58:06 PM PDT 24
Finished Apr 30 01:58:35 PM PDT 24
Peak memory 372240 kb
Host smart-0f08d297-3708-4b6e-97dd-799ef35437dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010792308 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.3010792308
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.528190068
Short name T732
Test name
Test status
Simulation time 503218596 ps
CPU time 2.66 seconds
Started Apr 30 01:58:07 PM PDT 24
Finished Apr 30 01:58:10 PM PDT 24
Peak memory 204208 kb
Host smart-27da6ea0-a45c-4205-a001-5eed8295095f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528190068 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.i2c_target_hrst.528190068
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2070958484
Short name T900
Test name
Test status
Simulation time 1619104853 ps
CPU time 7.97 seconds
Started Apr 30 01:58:10 PM PDT 24
Finished Apr 30 01:58:19 PM PDT 24
Peak memory 220424 kb
Host smart-ec1b1476-7d2b-4278-9d3f-c229c58d2efb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070958484 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2070958484
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.1871500687
Short name T873
Test name
Test status
Simulation time 21458979000 ps
CPU time 151.12 seconds
Started Apr 30 01:58:05 PM PDT 24
Finished Apr 30 02:00:36 PM PDT 24
Peak memory 2481004 kb
Host smart-4797f4ac-4d9a-443c-a8ab-08cb55c66ed2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871500687 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.1871500687
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.409818556
Short name T693
Test name
Test status
Simulation time 1506358691 ps
CPU time 57.76 seconds
Started Apr 30 01:58:07 PM PDT 24
Finished Apr 30 01:59:05 PM PDT 24
Peak memory 204184 kb
Host smart-b17d3a9b-7f38-4ae1-8f0e-36342d01eb0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409818556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_tar
get_smoke.409818556
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.4203248934
Short name T476
Test name
Test status
Simulation time 1093350701 ps
CPU time 16.5 seconds
Started Apr 30 01:58:06 PM PDT 24
Finished Apr 30 01:58:23 PM PDT 24
Peak memory 215108 kb
Host smart-332b5199-80a0-4a92-8ac1-7f369e36b137
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203248934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.4203248934
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.1802500924
Short name T20
Test name
Test status
Simulation time 37470371107 ps
CPU time 485.96 seconds
Started Apr 30 01:58:10 PM PDT 24
Finished Apr 30 02:06:17 PM PDT 24
Peak memory 4285592 kb
Host smart-a4fe6e40-e6a3-4419-ba2f-81c4103872c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802500924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.1802500924
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.3159224560
Short name T710
Test name
Test status
Simulation time 29698036941 ps
CPU time 800.91 seconds
Started Apr 30 01:58:08 PM PDT 24
Finished Apr 30 02:11:29 PM PDT 24
Peak memory 3457704 kb
Host smart-c69806d1-fcfd-4143-9784-141afe83e99e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159224560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.3159224560
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1762810490
Short name T349
Test name
Test status
Simulation time 4330366446 ps
CPU time 6.15 seconds
Started Apr 30 01:58:06 PM PDT 24
Finished Apr 30 01:58:13 PM PDT 24
Peak memory 212516 kb
Host smart-e920f2e0-6a09-4720-8000-b664332e1972
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762810490 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1762810490
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.2115339776
Short name T734
Test name
Test status
Simulation time 74092536 ps
CPU time 0.58 seconds
Started Apr 30 01:58:18 PM PDT 24
Finished Apr 30 01:58:19 PM PDT 24
Peak memory 203792 kb
Host smart-02bb0fb8-753e-40b4-a7e5-a6fec02365b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115339776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2115339776
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.382212326
Short name T980
Test name
Test status
Simulation time 95054207 ps
CPU time 1.32 seconds
Started Apr 30 01:58:11 PM PDT 24
Finished Apr 30 01:58:13 PM PDT 24
Peak memory 212416 kb
Host smart-50820b2f-5913-46dd-9c1d-e7c40e10ed4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382212326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.382212326
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.2461233837
Short name T461
Test name
Test status
Simulation time 1495605796 ps
CPU time 7.11 seconds
Started Apr 30 01:58:14 PM PDT 24
Finished Apr 30 01:58:22 PM PDT 24
Peak memory 285648 kb
Host smart-b571b0d5-8ccc-4eb9-a287-82f5e5ee908c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461233837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.2461233837
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.1167521041
Short name T51
Test name
Test status
Simulation time 2459094874 ps
CPU time 150.35 seconds
Started Apr 30 01:58:13 PM PDT 24
Finished Apr 30 02:00:43 PM PDT 24
Peak memory 522392 kb
Host smart-bf154b73-a23f-445b-ba98-8bb20b7dc6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167521041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.1167521041
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.1301675766
Short name T849
Test name
Test status
Simulation time 30808831473 ps
CPU time 134.82 seconds
Started Apr 30 01:58:13 PM PDT 24
Finished Apr 30 02:00:28 PM PDT 24
Peak memory 637884 kb
Host smart-c46825a3-2f4a-431c-a3ea-66cb0c692590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301675766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.1301675766
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.3243122896
Short name T394
Test name
Test status
Simulation time 850497349 ps
CPU time 0.86 seconds
Started Apr 30 01:58:11 PM PDT 24
Finished Apr 30 01:58:13 PM PDT 24
Peak memory 204004 kb
Host smart-1ba88efb-a1cd-48f9-9591-3e4541a97343
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243122896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.3243122896
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.71826048
Short name T382
Test name
Test status
Simulation time 635466012 ps
CPU time 4.17 seconds
Started Apr 30 01:58:13 PM PDT 24
Finished Apr 30 01:58:18 PM PDT 24
Peak memory 204160 kb
Host smart-29d3694f-34e1-4174-8c1a-1b9d9444411a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71826048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.71826048
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.4247263698
Short name T443
Test name
Test status
Simulation time 17620808536 ps
CPU time 258.86 seconds
Started Apr 30 01:58:14 PM PDT 24
Finished Apr 30 02:02:34 PM PDT 24
Peak memory 1050220 kb
Host smart-9779a966-c8c4-4eea-a7e2-eb44b70b58ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247263698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.4247263698
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.825593786
Short name T343
Test name
Test status
Simulation time 340125677 ps
CPU time 4.42 seconds
Started Apr 30 01:58:18 PM PDT 24
Finished Apr 30 01:58:23 PM PDT 24
Peak memory 204184 kb
Host smart-cef7330c-0554-487b-9c90-c173b3c561ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825593786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.825593786
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.3938929580
Short name T220
Test name
Test status
Simulation time 1004147807 ps
CPU time 48.49 seconds
Started Apr 30 01:58:17 PM PDT 24
Finished Apr 30 01:59:06 PM PDT 24
Peak memory 317868 kb
Host smart-1a194942-8b0c-4a81-ac3d-03e7a67c4638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938929580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.3938929580
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.2280537984
Short name T1145
Test name
Test status
Simulation time 38377130 ps
CPU time 0.65 seconds
Started Apr 30 01:58:11 PM PDT 24
Finished Apr 30 01:58:12 PM PDT 24
Peak memory 203776 kb
Host smart-a5d7d42d-8fbc-4c10-aef5-5a781e462494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280537984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.2280537984
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.3918186888
Short name T388
Test name
Test status
Simulation time 12684537687 ps
CPU time 156.87 seconds
Started Apr 30 01:58:10 PM PDT 24
Finished Apr 30 02:00:48 PM PDT 24
Peak memory 965600 kb
Host smart-008eff97-36e0-4291-970d-dabe4b5f0cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918186888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.3918186888
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.1338231219
Short name T1203
Test name
Test status
Simulation time 919115512 ps
CPU time 46.38 seconds
Started Apr 30 01:58:05 PM PDT 24
Finished Apr 30 01:58:52 PM PDT 24
Peak memory 337764 kb
Host smart-4e87ced9-2e9c-4104-a60b-3e32e2f45113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338231219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.1338231219
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.1055671623
Short name T250
Test name
Test status
Simulation time 10966067622 ps
CPU time 603.96 seconds
Started Apr 30 01:58:13 PM PDT 24
Finished Apr 30 02:08:17 PM PDT 24
Peak memory 1701272 kb
Host smart-98a795d4-c4b6-4083-988b-cd070c9bee23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055671623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.1055671623
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.1914825638
Short name T1043
Test name
Test status
Simulation time 518546577 ps
CPU time 8.09 seconds
Started Apr 30 01:58:13 PM PDT 24
Finished Apr 30 01:58:22 PM PDT 24
Peak memory 219252 kb
Host smart-96cb706c-7c23-47d1-99e0-cf656acd5de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914825638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.1914825638
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.2599866092
Short name T1233
Test name
Test status
Simulation time 2900326279 ps
CPU time 3.9 seconds
Started Apr 30 01:58:17 PM PDT 24
Finished Apr 30 01:58:21 PM PDT 24
Peak memory 212412 kb
Host smart-e5487c76-87af-4a83-9e33-7f21cb320433
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599866092 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.2599866092
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.1086913530
Short name T674
Test name
Test status
Simulation time 10349982309 ps
CPU time 12.65 seconds
Started Apr 30 01:58:12 PM PDT 24
Finished Apr 30 01:58:25 PM PDT 24
Peak memory 247248 kb
Host smart-593fe6d2-dc47-4568-8d15-4884844e8cce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086913530 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.1086913530
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.2386687443
Short name T416
Test name
Test status
Simulation time 10439054020 ps
CPU time 7.27 seconds
Started Apr 30 01:58:12 PM PDT 24
Finished Apr 30 01:58:20 PM PDT 24
Peak memory 234956 kb
Host smart-e00f27c0-6673-4afe-9f26-bf080dd07a63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386687443 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.2386687443
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.1112798461
Short name T609
Test name
Test status
Simulation time 838066674 ps
CPU time 2.59 seconds
Started Apr 30 01:58:12 PM PDT 24
Finished Apr 30 01:58:15 PM PDT 24
Peak memory 204208 kb
Host smart-4f71dcae-50af-4d05-b3c7-924830afd12b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112798461 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.1112798461
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.2602847918
Short name T1091
Test name
Test status
Simulation time 1576390294 ps
CPU time 7.37 seconds
Started Apr 30 01:58:11 PM PDT 24
Finished Apr 30 01:58:19 PM PDT 24
Peak memory 220400 kb
Host smart-1471a7be-0f55-4bb3-90da-e8d6d605c016
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602847918 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.2602847918
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.1568619109
Short name T1093
Test name
Test status
Simulation time 8523386582 ps
CPU time 24.2 seconds
Started Apr 30 01:58:12 PM PDT 24
Finished Apr 30 01:58:37 PM PDT 24
Peak memory 467652 kb
Host smart-428884c4-17a4-49cc-ac4f-d73967f684df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568619109 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.1568619109
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.1463153320
Short name T591
Test name
Test status
Simulation time 2023197373 ps
CPU time 15.17 seconds
Started Apr 30 01:58:12 PM PDT 24
Finished Apr 30 01:58:27 PM PDT 24
Peak memory 204136 kb
Host smart-3468692e-2edc-4252-af94-2067966d0cd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463153320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.1463153320
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.2326291892
Short name T1347
Test name
Test status
Simulation time 2208301560 ps
CPU time 23.41 seconds
Started Apr 30 01:58:12 PM PDT 24
Finished Apr 30 01:58:35 PM PDT 24
Peak memory 204228 kb
Host smart-6d9255f1-5263-4d80-b513-5445f5a363f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326291892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.2326291892
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.1966962278
Short name T824
Test name
Test status
Simulation time 61003956491 ps
CPU time 426.2 seconds
Started Apr 30 01:58:14 PM PDT 24
Finished Apr 30 02:05:21 PM PDT 24
Peak memory 3749164 kb
Host smart-f256f96a-13b7-4908-93d7-60e52d93107c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966962278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.1966962278
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.1809688246
Short name T564
Test name
Test status
Simulation time 8431177447 ps
CPU time 92.78 seconds
Started Apr 30 01:58:13 PM PDT 24
Finished Apr 30 01:59:47 PM PDT 24
Peak memory 1143208 kb
Host smart-ace59528-881f-4452-8a0e-627c9f73cf8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809688246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.1809688246
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.3349377661
Short name T560
Test name
Test status
Simulation time 4730325107 ps
CPU time 6.04 seconds
Started Apr 30 01:58:14 PM PDT 24
Finished Apr 30 01:58:21 PM PDT 24
Peak memory 212380 kb
Host smart-8cfffb9e-57d5-4731-8f72-7c1386e59e34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349377661 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.3349377661
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.4256420095
Short name T180
Test name
Test status
Simulation time 17271787 ps
CPU time 0.61 seconds
Started Apr 30 01:58:24 PM PDT 24
Finished Apr 30 01:58:25 PM PDT 24
Peak memory 203952 kb
Host smart-ecb332fb-c7b9-4880-9d9f-7481853a11b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256420095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.4256420095
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.2320540688
Short name T671
Test name
Test status
Simulation time 400116378 ps
CPU time 1.54 seconds
Started Apr 30 01:58:20 PM PDT 24
Finished Apr 30 01:58:22 PM PDT 24
Peak memory 212448 kb
Host smart-f705c59d-5987-42b6-af88-a3c024e6e3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320540688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.2320540688
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.3321986880
Short name T322
Test name
Test status
Simulation time 700577923 ps
CPU time 12.74 seconds
Started Apr 30 01:58:18 PM PDT 24
Finished Apr 30 01:58:31 PM PDT 24
Peak memory 254212 kb
Host smart-f2cdf75a-3935-49d7-a902-56de4504bcb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321986880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.3321986880
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.4129121249
Short name T333
Test name
Test status
Simulation time 4053543734 ps
CPU time 149.98 seconds
Started Apr 30 01:58:19 PM PDT 24
Finished Apr 30 02:00:49 PM PDT 24
Peak memory 671424 kb
Host smart-75adfd65-9c29-4c71-8bde-c0b6134e973f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129121249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.4129121249
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.3579674632
Short name T840
Test name
Test status
Simulation time 1465349506 ps
CPU time 45.98 seconds
Started Apr 30 01:58:18 PM PDT 24
Finished Apr 30 01:59:04 PM PDT 24
Peak memory 567644 kb
Host smart-b431629b-6bb1-4d58-99d0-8f2f2097d34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579674632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.3579674632
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.3135137802
Short name T497
Test name
Test status
Simulation time 352591655 ps
CPU time 0.85 seconds
Started Apr 30 01:58:19 PM PDT 24
Finished Apr 30 01:58:20 PM PDT 24
Peak memory 203912 kb
Host smart-4037d733-7d19-4d28-be5a-4e5a52d94b29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135137802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.3135137802
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.3044598181
Short name T1306
Test name
Test status
Simulation time 140061057 ps
CPU time 3.98 seconds
Started Apr 30 01:58:17 PM PDT 24
Finished Apr 30 01:58:22 PM PDT 24
Peak memory 225216 kb
Host smart-5b1b2923-6c4d-46e8-b3f2-f3ff16d7215c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044598181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.3044598181
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.2771702364
Short name T1333
Test name
Test status
Simulation time 4533929047 ps
CPU time 126 seconds
Started Apr 30 01:58:18 PM PDT 24
Finished Apr 30 02:00:25 PM PDT 24
Peak memory 1273052 kb
Host smart-fdc12a97-a494-416f-83f2-831403d7f14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771702364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.2771702364
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.2299185697
Short name T855
Test name
Test status
Simulation time 504604114 ps
CPU time 11.14 seconds
Started Apr 30 01:58:24 PM PDT 24
Finished Apr 30 01:58:36 PM PDT 24
Peak memory 204228 kb
Host smart-9a60f362-db99-4f9d-a195-202a7fa78b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299185697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.2299185697
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.1190337544
Short name T510
Test name
Test status
Simulation time 12197284725 ps
CPU time 21.11 seconds
Started Apr 30 01:58:23 PM PDT 24
Finished Apr 30 01:58:44 PM PDT 24
Peak memory 295852 kb
Host smart-11259269-af98-4c95-9b98-9dfd46ba4cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190337544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.1190337544
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.3224742743
Short name T188
Test name
Test status
Simulation time 42253603 ps
CPU time 0.61 seconds
Started Apr 30 01:58:18 PM PDT 24
Finished Apr 30 01:58:19 PM PDT 24
Peak memory 203860 kb
Host smart-02468a9d-815c-4204-8879-7d2d11d31e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224742743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.3224742743
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.313259181
Short name T1332
Test name
Test status
Simulation time 6891598118 ps
CPU time 33.3 seconds
Started Apr 30 01:58:19 PM PDT 24
Finished Apr 30 01:58:53 PM PDT 24
Peak memory 486580 kb
Host smart-8f258f2c-e0ee-42ac-b079-944c6c8a9b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313259181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.313259181
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.2392045859
Short name T631
Test name
Test status
Simulation time 1440269540 ps
CPU time 34.74 seconds
Started Apr 30 01:58:17 PM PDT 24
Finished Apr 30 01:58:53 PM PDT 24
Peak memory 405452 kb
Host smart-abaf7de2-9b79-412d-8ed1-57685d794a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392045859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.2392045859
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.1599861405
Short name T1056
Test name
Test status
Simulation time 5951269764 ps
CPU time 74.55 seconds
Started Apr 30 01:58:17 PM PDT 24
Finished Apr 30 01:59:32 PM PDT 24
Peak memory 584428 kb
Host smart-13069fb4-7eb0-4b8f-838a-a607b359dcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599861405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.1599861405
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.71754337
Short name T323
Test name
Test status
Simulation time 1535534634 ps
CPU time 7.02 seconds
Started Apr 30 01:58:18 PM PDT 24
Finished Apr 30 01:58:25 PM PDT 24
Peak memory 220424 kb
Host smart-e6871d46-2381-43ed-9bbd-31a3075ca9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71754337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.71754337
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.3112268846
Short name T1214
Test name
Test status
Simulation time 2086249021 ps
CPU time 2.86 seconds
Started Apr 30 01:58:23 PM PDT 24
Finished Apr 30 01:58:27 PM PDT 24
Peak memory 204212 kb
Host smart-4e8634f6-f024-4b1f-8a20-049310c57116
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112268846 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.3112268846
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.1867429716
Short name T206
Test name
Test status
Simulation time 10317575377 ps
CPU time 12.08 seconds
Started Apr 30 01:58:21 PM PDT 24
Finished Apr 30 01:58:33 PM PDT 24
Peak memory 260924 kb
Host smart-a5663ad8-2c81-4291-9281-d8d05a2cfcc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867429716 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.1867429716
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.2947180197
Short name T1092
Test name
Test status
Simulation time 10338966852 ps
CPU time 13.44 seconds
Started Apr 30 01:58:18 PM PDT 24
Finished Apr 30 01:58:32 PM PDT 24
Peak memory 263872 kb
Host smart-132f0f76-4090-4c10-8483-0adbdfd07e0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947180197 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.2947180197
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.711787833
Short name T419
Test name
Test status
Simulation time 1714577350 ps
CPU time 4.4 seconds
Started Apr 30 01:58:17 PM PDT 24
Finished Apr 30 01:58:22 PM PDT 24
Peak memory 204156 kb
Host smart-7aa20254-d196-479e-8e5c-8f35644fa64e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711787833 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_intr_smoke.711787833
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.601785382
Short name T533
Test name
Test status
Simulation time 3399728743 ps
CPU time 8.13 seconds
Started Apr 30 01:58:20 PM PDT 24
Finished Apr 30 01:58:29 PM PDT 24
Peak memory 204116 kb
Host smart-d3d1fc2b-56b2-4dbc-a491-72462e2c0b43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601785382 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.601785382
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.4015965624
Short name T375
Test name
Test status
Simulation time 830752085 ps
CPU time 26.06 seconds
Started Apr 30 01:58:23 PM PDT 24
Finished Apr 30 01:58:50 PM PDT 24
Peak memory 204120 kb
Host smart-05e52e28-78e3-4034-b0f6-0500e6144fa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015965624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.4015965624
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.1175922150
Short name T441
Test name
Test status
Simulation time 1534238014 ps
CPU time 11.62 seconds
Started Apr 30 01:58:19 PM PDT 24
Finished Apr 30 01:58:31 PM PDT 24
Peak memory 216012 kb
Host smart-3fb84a12-3d37-424b-b9ce-d01747655404
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175922150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.1175922150
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.2461782878
Short name T1234
Test name
Test status
Simulation time 25611726400 ps
CPU time 36.73 seconds
Started Apr 30 01:58:17 PM PDT 24
Finished Apr 30 01:58:54 PM PDT 24
Peak memory 750148 kb
Host smart-27de58d6-8408-4f92-a8dc-5fb78e4cfefc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461782878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.2461782878
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.3420192410
Short name T500
Test name
Test status
Simulation time 13308855412 ps
CPU time 701.82 seconds
Started Apr 30 01:58:23 PM PDT 24
Finished Apr 30 02:10:06 PM PDT 24
Peak memory 3183072 kb
Host smart-ce7774e0-5383-465c-9223-cf8c9193d307
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420192410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.3420192410
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.3441795202
Short name T1163
Test name
Test status
Simulation time 5126442493 ps
CPU time 6.39 seconds
Started Apr 30 01:58:17 PM PDT 24
Finished Apr 30 01:58:24 PM PDT 24
Peak memory 212440 kb
Host smart-47d4f8ab-cb0a-4452-84ec-35945f8b1f2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441795202 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.3441795202
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.3597648886
Short name T888
Test name
Test status
Simulation time 173077283 ps
CPU time 0.62 seconds
Started Apr 30 01:52:55 PM PDT 24
Finished Apr 30 01:52:56 PM PDT 24
Peak memory 203888 kb
Host smart-a661a5d6-10ea-4dfc-9393-53fc4828967e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597648886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3597648886
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3146941066
Short name T335
Test name
Test status
Simulation time 60615730 ps
CPU time 1.41 seconds
Started Apr 30 01:53:03 PM PDT 24
Finished Apr 30 01:53:05 PM PDT 24
Peak memory 212536 kb
Host smart-c62dfe59-277a-4306-8dc4-81c5bd4a3efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146941066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3146941066
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.2157995521
Short name T273
Test name
Test status
Simulation time 6711239799 ps
CPU time 8.19 seconds
Started Apr 30 01:52:54 PM PDT 24
Finished Apr 30 01:53:03 PM PDT 24
Peak memory 280420 kb
Host smart-4433ce2f-7aa2-4847-ab80-87223251c27b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157995521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.2157995521
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.3284657719
Short name T892
Test name
Test status
Simulation time 1611886721 ps
CPU time 50.78 seconds
Started Apr 30 01:52:57 PM PDT 24
Finished Apr 30 01:53:48 PM PDT 24
Peak memory 564820 kb
Host smart-548e9a05-a7fb-42b9-8c36-2d243a8bfacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284657719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.3284657719
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.389034583
Short name T1026
Test name
Test status
Simulation time 4317432431 ps
CPU time 63.58 seconds
Started Apr 30 01:52:55 PM PDT 24
Finished Apr 30 01:53:59 PM PDT 24
Peak memory 718920 kb
Host smart-cf34435b-1d5b-492e-bb7e-acfd85ed8ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389034583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.389034583
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.1534326494
Short name T427
Test name
Test status
Simulation time 111775703 ps
CPU time 1.03 seconds
Started Apr 30 01:52:55 PM PDT 24
Finished Apr 30 01:52:56 PM PDT 24
Peak memory 204156 kb
Host smart-3db7a3d8-9c1f-4e07-8ab9-b435ce7071a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534326494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.1534326494
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.4146065085
Short name T513
Test name
Test status
Simulation time 259775511 ps
CPU time 3.88 seconds
Started Apr 30 01:52:58 PM PDT 24
Finished Apr 30 01:53:02 PM PDT 24
Peak memory 225208 kb
Host smart-55004af6-ef63-4590-9116-2d6054c1b1c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146065085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
4146065085
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.3578161528
Short name T905
Test name
Test status
Simulation time 35903100201 ps
CPU time 234.57 seconds
Started Apr 30 01:52:53 PM PDT 24
Finished Apr 30 01:56:48 PM PDT 24
Peak memory 1007680 kb
Host smart-46257332-9b98-4f57-b206-12a50f27c8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578161528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3578161528
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.2843221401
Short name T1000
Test name
Test status
Simulation time 401836865 ps
CPU time 4.85 seconds
Started Apr 30 01:52:56 PM PDT 24
Finished Apr 30 01:53:01 PM PDT 24
Peak memory 204040 kb
Host smart-3efd250f-7d85-4c77-ab6b-1a7a0a896cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843221401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.2843221401
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.3261080947
Short name T755
Test name
Test status
Simulation time 5188149926 ps
CPU time 25.38 seconds
Started Apr 30 01:52:53 PM PDT 24
Finished Apr 30 01:53:19 PM PDT 24
Peak memory 293864 kb
Host smart-121ce52b-6833-4624-b70d-54261ba2460a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261080947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.3261080947
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.843764147
Short name T1232
Test name
Test status
Simulation time 45755272 ps
CPU time 0.64 seconds
Started Apr 30 01:52:52 PM PDT 24
Finished Apr 30 01:52:53 PM PDT 24
Peak memory 203852 kb
Host smart-3d490a1a-e841-4e3b-830c-3ba3a0f7994c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843764147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.843764147
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.1826181141
Short name T485
Test name
Test status
Simulation time 4953610162 ps
CPU time 69.68 seconds
Started Apr 30 01:52:56 PM PDT 24
Finished Apr 30 01:54:06 PM PDT 24
Peak memory 221348 kb
Host smart-771eb107-89e2-44db-a7a9-b7fb4189b88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826181141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.1826181141
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.1503493214
Short name T850
Test name
Test status
Simulation time 7791176156 ps
CPU time 41.5 seconds
Started Apr 30 01:52:53 PM PDT 24
Finished Apr 30 01:53:35 PM PDT 24
Peak memory 352048 kb
Host smart-52f9db88-eb57-4ed1-b29c-7f2702f55339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503493214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.1503493214
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.1051981488
Short name T1246
Test name
Test status
Simulation time 698572735 ps
CPU time 12.19 seconds
Started Apr 30 01:52:56 PM PDT 24
Finished Apr 30 01:53:08 PM PDT 24
Peak memory 228528 kb
Host smart-dcf5256a-4b0c-4d82-a4f8-f29efa4b80d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051981488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.1051981488
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.1701861226
Short name T788
Test name
Test status
Simulation time 4091612954 ps
CPU time 4.69 seconds
Started Apr 30 01:53:01 PM PDT 24
Finished Apr 30 01:53:06 PM PDT 24
Peak memory 205392 kb
Host smart-b421f8fb-07e9-4369-a257-2ea9f897efca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701861226 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.1701861226
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.3904679998
Short name T468
Test name
Test status
Simulation time 10309253581 ps
CPU time 10.99 seconds
Started Apr 30 01:53:03 PM PDT 24
Finished Apr 30 01:53:14 PM PDT 24
Peak memory 247968 kb
Host smart-01fdea78-fe9f-44ca-8684-a81926a22fe0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904679998 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.3904679998
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.3537021342
Short name T669
Test name
Test status
Simulation time 11944130837 ps
CPU time 5.61 seconds
Started Apr 30 01:52:53 PM PDT 24
Finished Apr 30 01:52:59 PM PDT 24
Peak memory 257032 kb
Host smart-06f80605-85b3-4f5e-93f5-cc1e7f77c0d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537021342 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.3537021342
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.466180008
Short name T1340
Test name
Test status
Simulation time 6348466951 ps
CPU time 2.2 seconds
Started Apr 30 01:52:53 PM PDT 24
Finished Apr 30 01:52:55 PM PDT 24
Peak memory 204272 kb
Host smart-40749491-9c1b-4737-9219-1492234a2a1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466180008 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.i2c_target_hrst.466180008
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.2568173421
Short name T1040
Test name
Test status
Simulation time 11540281643 ps
CPU time 4.8 seconds
Started Apr 30 01:53:01 PM PDT 24
Finished Apr 30 01:53:06 PM PDT 24
Peak memory 204308 kb
Host smart-6afe56d8-f7de-425f-b91c-36147527d0ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568173421 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.2568173421
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.736542453
Short name T1261
Test name
Test status
Simulation time 21932266972 ps
CPU time 23.82 seconds
Started Apr 30 01:52:58 PM PDT 24
Finished Apr 30 01:53:22 PM PDT 24
Peak memory 485964 kb
Host smart-69d581f3-d1da-4e92-8531-dd33dfcada12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736542453 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.736542453
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.2379231123
Short name T1149
Test name
Test status
Simulation time 3999454470 ps
CPU time 13.39 seconds
Started Apr 30 01:52:54 PM PDT 24
Finished Apr 30 01:53:08 PM PDT 24
Peak memory 204192 kb
Host smart-5cba0c15-f4c6-46de-b1c1-f90c1da4a8e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379231123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.2379231123
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.3322439524
Short name T1179
Test name
Test status
Simulation time 273387075 ps
CPU time 9.45 seconds
Started Apr 30 01:53:01 PM PDT 24
Finished Apr 30 01:53:11 PM PDT 24
Peak memory 204116 kb
Host smart-6e593837-1b6a-4043-89f0-d25745a015be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322439524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.3322439524
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.2701226013
Short name T554
Test name
Test status
Simulation time 37710959079 ps
CPU time 618.28 seconds
Started Apr 30 01:52:49 PM PDT 24
Finished Apr 30 02:03:08 PM PDT 24
Peak memory 4539300 kb
Host smart-543bd47b-b33f-4755-8797-b2b5aed6b562
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701226013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.2701226013
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.4194539656
Short name T687
Test name
Test status
Simulation time 10197831533 ps
CPU time 26.01 seconds
Started Apr 30 01:53:07 PM PDT 24
Finished Apr 30 01:53:33 PM PDT 24
Peak memory 265708 kb
Host smart-d4d4c4bd-d0a8-467e-8adc-8160e982d6b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194539656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.4194539656
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.176295048
Short name T548
Test name
Test status
Simulation time 5246079581 ps
CPU time 6.16 seconds
Started Apr 30 01:52:54 PM PDT 24
Finished Apr 30 01:53:01 PM PDT 24
Peak memory 212544 kb
Host smart-4d260b55-354e-49c4-a649-5875777c343e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176295048 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_timeout.176295048
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.1290650812
Short name T1294
Test name
Test status
Simulation time 15510370 ps
CPU time 0.65 seconds
Started Apr 30 01:53:01 PM PDT 24
Finished Apr 30 01:53:03 PM PDT 24
Peak memory 203864 kb
Host smart-883ae47f-e798-4f88-8414-e0cfd294cacd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290650812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.1290650812
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1492473056
Short name T200
Test name
Test status
Simulation time 185490971 ps
CPU time 1.09 seconds
Started Apr 30 01:52:59 PM PDT 24
Finished Apr 30 01:53:01 PM PDT 24
Peak memory 212416 kb
Host smart-c832ce28-1e86-4e1a-bd32-1760f502e893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492473056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1492473056
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.1059655021
Short name T997
Test name
Test status
Simulation time 428718418 ps
CPU time 4.56 seconds
Started Apr 30 01:52:57 PM PDT 24
Finished Apr 30 01:53:02 PM PDT 24
Peak memory 232800 kb
Host smart-3ee03046-28b8-46f5-827d-bc73b6c1ef17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059655021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.1059655021
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.2411926243
Short name T651
Test name
Test status
Simulation time 7416040399 ps
CPU time 113.18 seconds
Started Apr 30 01:52:53 PM PDT 24
Finished Apr 30 01:54:47 PM PDT 24
Peak memory 517976 kb
Host smart-e3dc09e0-0759-4c47-b8c6-ff3817d1a15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411926243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2411926243
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.2555051446
Short name T515
Test name
Test status
Simulation time 1714784902 ps
CPU time 54.49 seconds
Started Apr 30 01:52:57 PM PDT 24
Finished Apr 30 01:53:52 PM PDT 24
Peak memory 596372 kb
Host smart-cb7dbe5d-db55-4974-8a51-b5a9e6ec24fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555051446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.2555051446
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.3395526282
Short name T584
Test name
Test status
Simulation time 83068146 ps
CPU time 0.84 seconds
Started Apr 30 01:52:55 PM PDT 24
Finished Apr 30 01:52:56 PM PDT 24
Peak memory 203972 kb
Host smart-b33f47be-126c-47ed-91c5-4ba2dbcfbddb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395526282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.3395526282
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.2312048970
Short name T303
Test name
Test status
Simulation time 1425001810 ps
CPU time 5.09 seconds
Started Apr 30 01:52:59 PM PDT 24
Finished Apr 30 01:53:04 PM PDT 24
Peak memory 235292 kb
Host smart-442fa8ef-2862-4765-bf68-f0780ae10d81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312048970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
2312048970
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.4229845571
Short name T241
Test name
Test status
Simulation time 6406699024 ps
CPU time 88.62 seconds
Started Apr 30 01:52:56 PM PDT 24
Finished Apr 30 01:54:25 PM PDT 24
Peak memory 917228 kb
Host smart-673450ed-2bc5-42dc-9baa-52fba1506097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229845571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.4229845571
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.208471832
Short name T1061
Test name
Test status
Simulation time 2524158347 ps
CPU time 7.09 seconds
Started Apr 30 01:53:06 PM PDT 24
Finished Apr 30 01:53:14 PM PDT 24
Peak memory 204248 kb
Host smart-443e72ff-9dfe-4305-a357-99695d8e700b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208471832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.208471832
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.249975691
Short name T901
Test name
Test status
Simulation time 6507689986 ps
CPU time 37.88 seconds
Started Apr 30 01:53:01 PM PDT 24
Finished Apr 30 01:53:39 PM PDT 24
Peak memory 414476 kb
Host smart-8c77fec4-6b33-42c3-8435-71e0f220dc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249975691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.249975691
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.2939959748
Short name T550
Test name
Test status
Simulation time 35137417 ps
CPU time 0.66 seconds
Started Apr 30 01:52:59 PM PDT 24
Finished Apr 30 01:53:01 PM PDT 24
Peak memory 203844 kb
Host smart-4eabfca9-4212-41c2-b490-74c681f21684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939959748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.2939959748
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.2568116725
Short name T75
Test name
Test status
Simulation time 5745107553 ps
CPU time 81.1 seconds
Started Apr 30 01:52:58 PM PDT 24
Finished Apr 30 01:54:20 PM PDT 24
Peak memory 263920 kb
Host smart-e35bd2b7-ae81-464b-96f6-e675833e4451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568116725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.2568116725
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1113777704
Short name T363
Test name
Test status
Simulation time 11698689713 ps
CPU time 86.88 seconds
Started Apr 30 01:52:59 PM PDT 24
Finished Apr 30 01:54:26 PM PDT 24
Peak memory 359992 kb
Host smart-53ed831d-8dbd-4eb9-be59-f328d8716e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113777704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1113777704
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.4159519730
Short name T1160
Test name
Test status
Simulation time 181898246963 ps
CPU time 1477.43 seconds
Started Apr 30 01:53:06 PM PDT 24
Finished Apr 30 02:17:44 PM PDT 24
Peak memory 2537492 kb
Host smart-ef5031ff-f4b3-42ef-87c5-068df9f31b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159519730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.4159519730
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.1954380969
Short name T61
Test name
Test status
Simulation time 1090499058 ps
CPU time 8.17 seconds
Started Apr 30 01:52:53 PM PDT 24
Finished Apr 30 01:53:02 PM PDT 24
Peak memory 213348 kb
Host smart-66c52cd0-a498-4938-953e-74ba2f7aff25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954380969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1954380969
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.1686758095
Short name T1318
Test name
Test status
Simulation time 4217020772 ps
CPU time 4.73 seconds
Started Apr 30 01:53:11 PM PDT 24
Finished Apr 30 01:53:16 PM PDT 24
Peak memory 212416 kb
Host smart-2df35e0c-6a51-4f2b-ad12-d8949ead7282
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686758095 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.1686758095
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.1551657041
Short name T417
Test name
Test status
Simulation time 10169722731 ps
CPU time 34.06 seconds
Started Apr 30 01:53:05 PM PDT 24
Finished Apr 30 01:53:40 PM PDT 24
Peak memory 351228 kb
Host smart-e008052e-90a5-4efb-a4ee-419f0ad1e71f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551657041 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.1551657041
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.30034544
Short name T592
Test name
Test status
Simulation time 10208301553 ps
CPU time 16.08 seconds
Started Apr 30 01:53:05 PM PDT 24
Finished Apr 30 01:53:22 PM PDT 24
Peak memory 280024 kb
Host smart-5b946bab-6e31-4da0-807a-7963b738d2c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30034544 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_fifo_reset_tx.30034544
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.1298546358
Short name T555
Test name
Test status
Simulation time 362587692 ps
CPU time 2.27 seconds
Started Apr 30 01:53:08 PM PDT 24
Finished Apr 30 01:53:11 PM PDT 24
Peak memory 204152 kb
Host smart-8c7e3975-49a9-4d14-9868-b0eb74fef388
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298546358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.1298546358
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3400254189
Short name T272
Test name
Test status
Simulation time 1737226784 ps
CPU time 4.6 seconds
Started Apr 30 01:53:00 PM PDT 24
Finished Apr 30 01:53:05 PM PDT 24
Peak memory 207280 kb
Host smart-15ef057f-fbb9-4ab9-a5ac-80d82b723a90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400254189 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3400254189
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.3702274869
Short name T930
Test name
Test status
Simulation time 10239964349 ps
CPU time 149.97 seconds
Started Apr 30 01:53:08 PM PDT 24
Finished Apr 30 01:55:39 PM PDT 24
Peak memory 2553656 kb
Host smart-78fcfdf3-3a69-42ce-b732-b80142db0342
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702274869 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.3702274869
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.1423582855
Short name T354
Test name
Test status
Simulation time 2503766685 ps
CPU time 9.27 seconds
Started Apr 30 01:53:00 PM PDT 24
Finished Apr 30 01:53:10 PM PDT 24
Peak memory 204208 kb
Host smart-2c8dff5a-09e6-463c-86da-29c534e23aa2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423582855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.1423582855
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.3457861950
Short name T1278
Test name
Test status
Simulation time 4301613609 ps
CPU time 14.69 seconds
Started Apr 30 01:53:02 PM PDT 24
Finished Apr 30 01:53:17 PM PDT 24
Peak memory 216216 kb
Host smart-709fa888-5967-4c43-9ae3-667fb6b17a31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457861950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.3457861950
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.147319709
Short name T454
Test name
Test status
Simulation time 23563191030 ps
CPU time 66.6 seconds
Started Apr 30 01:53:00 PM PDT 24
Finished Apr 30 01:54:07 PM PDT 24
Peak memory 1007884 kb
Host smart-5a2525c3-6501-440b-b2ba-0cf0a1fe9dca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147319709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_
target_stress_wr.147319709
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.279931604
Short name T650
Test name
Test status
Simulation time 5088370081 ps
CPU time 23.44 seconds
Started Apr 30 01:53:00 PM PDT 24
Finished Apr 30 01:53:25 PM PDT 24
Peak memory 435528 kb
Host smart-7d1c398f-0a59-4077-90e2-b705e936d54e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279931604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_ta
rget_stretch.279931604
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.3462524774
Short name T899
Test name
Test status
Simulation time 1292390969 ps
CPU time 6.36 seconds
Started Apr 30 01:53:07 PM PDT 24
Finished Apr 30 01:53:14 PM PDT 24
Peak memory 212372 kb
Host smart-df1fd4e4-0336-452e-9fa6-fc4d76099b19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462524774 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.3462524774
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.367090803
Short name T551
Test name
Test status
Simulation time 16227668 ps
CPU time 0.64 seconds
Started Apr 30 01:53:00 PM PDT 24
Finished Apr 30 01:53:02 PM PDT 24
Peak memory 203868 kb
Host smart-e58ca8be-1f94-43b2-bbde-3d66cc4f9ac1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367090803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.367090803
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.595966845
Short name T778
Test name
Test status
Simulation time 92887304 ps
CPU time 1.52 seconds
Started Apr 30 01:52:58 PM PDT 24
Finished Apr 30 01:53:00 PM PDT 24
Peak memory 220692 kb
Host smart-2b8a98cf-9968-415f-8f7b-146093f52e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595966845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.595966845
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.3887667278
Short name T368
Test name
Test status
Simulation time 346737221 ps
CPU time 8.06 seconds
Started Apr 30 01:53:02 PM PDT 24
Finished Apr 30 01:53:11 PM PDT 24
Peak memory 275948 kb
Host smart-c0da8079-abf5-45e4-931a-4a13d1b7e980
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887667278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.3887667278
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.4057680803
Short name T1013
Test name
Test status
Simulation time 6941698039 ps
CPU time 50.89 seconds
Started Apr 30 01:53:00 PM PDT 24
Finished Apr 30 01:53:52 PM PDT 24
Peak memory 534300 kb
Host smart-5c64652f-3c74-4791-8774-ecd9165ffc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057680803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.4057680803
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.1827514719
Short name T466
Test name
Test status
Simulation time 2058181338 ps
CPU time 67.19 seconds
Started Apr 30 01:53:02 PM PDT 24
Finished Apr 30 01:54:10 PM PDT 24
Peak memory 659908 kb
Host smart-6a9d4d14-cf6c-4017-aab5-a7846928c49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827514719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.1827514719
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.128486043
Short name T742
Test name
Test status
Simulation time 236402593 ps
CPU time 1.13 seconds
Started Apr 30 01:52:58 PM PDT 24
Finished Apr 30 01:52:59 PM PDT 24
Peak memory 204124 kb
Host smart-8384a8c4-79ab-4085-a3bc-ab018ba46510
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128486043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt
.128486043
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.465244843
Short name T1327
Test name
Test status
Simulation time 415852579 ps
CPU time 5.96 seconds
Started Apr 30 01:53:00 PM PDT 24
Finished Apr 30 01:53:06 PM PDT 24
Peak memory 219236 kb
Host smart-27235d71-99ef-4445-b33c-b1486d3e3abe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465244843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.465244843
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.1430220223
Short name T165
Test name
Test status
Simulation time 77622361366 ps
CPU time 119.63 seconds
Started Apr 30 01:52:59 PM PDT 24
Finished Apr 30 01:54:59 PM PDT 24
Peak memory 1300668 kb
Host smart-28028804-9bf6-4ba3-b5fd-5e06784f9871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430220223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.1430220223
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.1897784378
Short name T1134
Test name
Test status
Simulation time 245011356 ps
CPU time 3.38 seconds
Started Apr 30 01:53:00 PM PDT 24
Finished Apr 30 01:53:04 PM PDT 24
Peak memory 204068 kb
Host smart-b1604eed-ec6f-4a6b-b4f7-4ce0feeecc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897784378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.1897784378
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.362636456
Short name T64
Test name
Test status
Simulation time 6740602440 ps
CPU time 75.06 seconds
Started Apr 30 01:53:06 PM PDT 24
Finished Apr 30 01:54:22 PM PDT 24
Peak memory 316824 kb
Host smart-4a232e9c-0dde-400d-b23c-a78d992a1ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362636456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.362636456
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.4069625971
Short name T504
Test name
Test status
Simulation time 28231153 ps
CPU time 0.71 seconds
Started Apr 30 01:53:00 PM PDT 24
Finished Apr 30 01:53:02 PM PDT 24
Peak memory 203804 kb
Host smart-2d00f471-7d41-47e3-8a41-e2ec8d646bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069625971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.4069625971
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.245899927
Short name T78
Test name
Test status
Simulation time 263269629 ps
CPU time 2.26 seconds
Started Apr 30 01:53:01 PM PDT 24
Finished Apr 30 01:53:04 PM PDT 24
Peak memory 228736 kb
Host smart-dc0bbd4b-553f-45e1-b5e2-ad2c8b90ba76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245899927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.245899927
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.4147544845
Short name T805
Test name
Test status
Simulation time 1098474075 ps
CPU time 53.43 seconds
Started Apr 30 01:53:05 PM PDT 24
Finished Apr 30 01:53:59 PM PDT 24
Peak memory 326200 kb
Host smart-4d7ef91b-c996-458f-adc1-b25027b10204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147544845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.4147544845
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.594440226
Short name T656
Test name
Test status
Simulation time 1368105070 ps
CPU time 16.27 seconds
Started Apr 30 01:53:07 PM PDT 24
Finished Apr 30 01:53:24 PM PDT 24
Peak memory 212428 kb
Host smart-ebec01ee-2bba-4217-98cc-758f7de97ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594440226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.594440226
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.3665528568
Short name T1231
Test name
Test status
Simulation time 1519284343 ps
CPU time 3.69 seconds
Started Apr 30 01:53:12 PM PDT 24
Finished Apr 30 01:53:16 PM PDT 24
Peak memory 204136 kb
Host smart-cd57f586-82b0-499b-88c8-977c2d4a145f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665528568 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3665528568
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.3304732281
Short name T57
Test name
Test status
Simulation time 10053170072 ps
CPU time 77.06 seconds
Started Apr 30 01:53:06 PM PDT 24
Finished Apr 30 01:54:24 PM PDT 24
Peak memory 437428 kb
Host smart-ef26167b-0ada-4c10-b4ac-14a82a6a89b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304732281 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.3304732281
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.162433942
Short name T1021
Test name
Test status
Simulation time 10334607849 ps
CPU time 13.01 seconds
Started Apr 30 01:53:11 PM PDT 24
Finished Apr 30 01:53:25 PM PDT 24
Peak memory 285880 kb
Host smart-fdf4dca0-2c5c-4b99-a05d-fb743bd8d46a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162433942 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.i2c_target_fifo_reset_tx.162433942
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.42116328
Short name T763
Test name
Test status
Simulation time 945476165 ps
CPU time 2.62 seconds
Started Apr 30 01:53:01 PM PDT 24
Finished Apr 30 01:53:05 PM PDT 24
Peak memory 204148 kb
Host smart-d8c7b858-ab5d-4f5e-a23e-a62d8b1a9e7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42116328 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.i2c_target_hrst.42116328
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1889818621
Short name T493
Test name
Test status
Simulation time 1546253131 ps
CPU time 6.72 seconds
Started Apr 30 01:53:10 PM PDT 24
Finished Apr 30 01:53:17 PM PDT 24
Peak memory 204120 kb
Host smart-ff06fc4d-38fe-449d-b9ce-aadb52cf488d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889818621 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1889818621
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.173214493
Short name T883
Test name
Test status
Simulation time 18401959619 ps
CPU time 6.78 seconds
Started Apr 30 01:53:02 PM PDT 24
Finished Apr 30 01:53:10 PM PDT 24
Peak memory 204236 kb
Host smart-dbaffe34-ce74-48b2-ad09-150ea780e4a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173214493 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.173214493
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.557726554
Short name T768
Test name
Test status
Simulation time 2720195034 ps
CPU time 10.96 seconds
Started Apr 30 01:53:00 PM PDT 24
Finished Apr 30 01:53:12 PM PDT 24
Peak memory 204136 kb
Host smart-9ccafcf0-9584-4eb8-bfe8-0631e1cfce33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557726554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_targ
et_smoke.557726554
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.4026927753
Short name T1119
Test name
Test status
Simulation time 1025599169 ps
CPU time 4.38 seconds
Started Apr 30 01:53:02 PM PDT 24
Finished Apr 30 01:53:07 PM PDT 24
Peak memory 204140 kb
Host smart-8fb01f05-b5a2-49ac-86e1-16603862e18a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026927753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.4026927753
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.2533738916
Short name T1035
Test name
Test status
Simulation time 34685048533 ps
CPU time 45.99 seconds
Started Apr 30 01:53:00 PM PDT 24
Finished Apr 30 01:53:46 PM PDT 24
Peak memory 940964 kb
Host smart-9027e34a-d285-46ff-aad6-06b13cb6054d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533738916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.2533738916
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.2333562352
Short name T1288
Test name
Test status
Simulation time 985887251 ps
CPU time 5.75 seconds
Started Apr 30 01:53:00 PM PDT 24
Finished Apr 30 01:53:07 PM PDT 24
Peak memory 212412 kb
Host smart-8dc6bc8d-25f7-4b7c-9523-04fa5b7ce372
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333562352 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.2333562352
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.1702919562
Short name T602
Test name
Test status
Simulation time 20334083 ps
CPU time 0.62 seconds
Started Apr 30 01:53:12 PM PDT 24
Finished Apr 30 01:53:13 PM PDT 24
Peak memory 203920 kb
Host smart-fe01c4e3-9e34-453d-b338-c1daee7d5d2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702919562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.1702919562
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.2964822716
Short name T311
Test name
Test status
Simulation time 111612803 ps
CPU time 1.81 seconds
Started Apr 30 01:53:05 PM PDT 24
Finished Apr 30 01:53:08 PM PDT 24
Peak memory 212396 kb
Host smart-e33c2084-d8e7-458c-92ed-226be31815f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964822716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.2964822716
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.714984274
Short name T992
Test name
Test status
Simulation time 524566311 ps
CPU time 2.96 seconds
Started Apr 30 01:53:02 PM PDT 24
Finished Apr 30 01:53:05 PM PDT 24
Peak memory 230692 kb
Host smart-6f895571-e6e3-4894-aa95-3d5dbd4d906f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714984274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty
.714984274
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.1378307187
Short name T606
Test name
Test status
Simulation time 7583855035 ps
CPU time 62.59 seconds
Started Apr 30 01:52:59 PM PDT 24
Finished Apr 30 01:54:02 PM PDT 24
Peak memory 678012 kb
Host smart-3093840d-ee09-45e6-855f-2ebbf1f814b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378307187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.1378307187
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.1740574692
Short name T1181
Test name
Test status
Simulation time 2329841003 ps
CPU time 164.19 seconds
Started Apr 30 01:53:09 PM PDT 24
Finished Apr 30 01:55:54 PM PDT 24
Peak memory 721860 kb
Host smart-e6fe4869-a2b7-4dae-8d32-305ed2ebd90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740574692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.1740574692
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.1881612453
Short name T209
Test name
Test status
Simulation time 165093726 ps
CPU time 0.94 seconds
Started Apr 30 01:53:02 PM PDT 24
Finished Apr 30 01:53:04 PM PDT 24
Peak memory 203960 kb
Host smart-4482a664-2ccd-47a7-ace9-dee227ba049e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881612453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.1881612453
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.302744956
Short name T367
Test name
Test status
Simulation time 1236909289 ps
CPU time 5.15 seconds
Started Apr 30 01:53:05 PM PDT 24
Finished Apr 30 01:53:11 PM PDT 24
Peak memory 241660 kb
Host smart-da21c465-0c26-4d18-92d7-1ca3f9ae3ce9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302744956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.302744956
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.475053130
Short name T804
Test name
Test status
Simulation time 3022803741 ps
CPU time 200.63 seconds
Started Apr 30 01:53:00 PM PDT 24
Finished Apr 30 01:56:22 PM PDT 24
Peak memory 918540 kb
Host smart-d6221465-8ddb-4aac-88af-b6d82bacbfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475053130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.475053130
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.2176876476
Short name T1212
Test name
Test status
Simulation time 562957599 ps
CPU time 7.55 seconds
Started Apr 30 01:53:08 PM PDT 24
Finished Apr 30 01:53:16 PM PDT 24
Peak memory 204172 kb
Host smart-954f5495-ba91-486f-a847-cde82107687b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176876476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2176876476
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.1741137576
Short name T1006
Test name
Test status
Simulation time 6408939951 ps
CPU time 75.37 seconds
Started Apr 30 01:53:11 PM PDT 24
Finished Apr 30 01:54:27 PM PDT 24
Peak memory 366576 kb
Host smart-2364979f-ccbc-458f-b50a-6c1cb1e78fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741137576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.1741137576
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.3838900220
Short name T1305
Test name
Test status
Simulation time 86971724 ps
CPU time 0.74 seconds
Started Apr 30 01:53:10 PM PDT 24
Finished Apr 30 01:53:11 PM PDT 24
Peak memory 203784 kb
Host smart-3d8cd065-6cf9-4740-8f68-bc7808056b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838900220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.3838900220
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.2909569344
Short name T77
Test name
Test status
Simulation time 924325411 ps
CPU time 4.74 seconds
Started Apr 30 01:53:07 PM PDT 24
Finished Apr 30 01:53:12 PM PDT 24
Peak memory 232392 kb
Host smart-482577c8-e6f7-4fd3-8660-dd7056ae530d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909569344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.2909569344
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.2977489014
Short name T842
Test name
Test status
Simulation time 2770542360 ps
CPU time 69.12 seconds
Started Apr 30 01:53:07 PM PDT 24
Finished Apr 30 01:54:17 PM PDT 24
Peak memory 375772 kb
Host smart-bef0102b-9ef1-4c98-b188-d8fd1d4e4d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977489014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.2977489014
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.939369293
Short name T204
Test name
Test status
Simulation time 54000659215 ps
CPU time 302.63 seconds
Started Apr 30 01:53:05 PM PDT 24
Finished Apr 30 01:58:09 PM PDT 24
Peak memory 1650572 kb
Host smart-94dffa46-80e4-47ad-8f00-3b77f6f434b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939369293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.939369293
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.3717013920
Short name T480
Test name
Test status
Simulation time 1585774575 ps
CPU time 6.23 seconds
Started Apr 30 01:53:05 PM PDT 24
Finished Apr 30 01:53:11 PM PDT 24
Peak memory 220568 kb
Host smart-006b63e4-cc93-49c8-9965-94274297fae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717013920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.3717013920
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.3818897004
Short name T756
Test name
Test status
Simulation time 880014717 ps
CPU time 3.91 seconds
Started Apr 30 01:53:12 PM PDT 24
Finished Apr 30 01:53:16 PM PDT 24
Peak memory 212408 kb
Host smart-e0a135ae-7b1c-4f7a-9ef8-22375e76ef89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818897004 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3818897004
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3628011650
Short name T58
Test name
Test status
Simulation time 10252832738 ps
CPU time 13.36 seconds
Started Apr 30 01:53:11 PM PDT 24
Finished Apr 30 01:53:25 PM PDT 24
Peak memory 256948 kb
Host smart-dad7bb09-03fc-4015-8072-66f9ad161e43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628011650 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.3628011650
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2267641298
Short name T1114
Test name
Test status
Simulation time 10149038163 ps
CPU time 34.65 seconds
Started Apr 30 01:53:10 PM PDT 24
Finished Apr 30 01:53:45 PM PDT 24
Peak memory 383304 kb
Host smart-7165a37e-dc3b-47b1-a421-e54deb0cce06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267641298 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2267641298
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.1048006095
Short name T235
Test name
Test status
Simulation time 853942737 ps
CPU time 2.84 seconds
Started Apr 30 01:53:08 PM PDT 24
Finished Apr 30 01:53:11 PM PDT 24
Peak memory 204172 kb
Host smart-527ce7fb-64a5-4a53-816a-90f227eb883b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048006095 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.1048006095
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.786272062
Short name T1164
Test name
Test status
Simulation time 8118140491 ps
CPU time 2.95 seconds
Started Apr 30 01:53:07 PM PDT 24
Finished Apr 30 01:53:10 PM PDT 24
Peak memory 204220 kb
Host smart-bb4e7df7-d18e-4b37-8e67-9c4c18950a8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786272062 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_intr_smoke.786272062
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.2186034131
Short name T264
Test name
Test status
Simulation time 4313455019 ps
CPU time 3.81 seconds
Started Apr 30 01:53:06 PM PDT 24
Finished Apr 30 01:53:10 PM PDT 24
Peak memory 204228 kb
Host smart-498b65dc-bf7f-40a1-8e67-9e857437075c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186034131 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.2186034131
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.1759153576
Short name T1032
Test name
Test status
Simulation time 10327977572 ps
CPU time 52.79 seconds
Started Apr 30 01:53:06 PM PDT 24
Finished Apr 30 01:53:59 PM PDT 24
Peak memory 204208 kb
Host smart-0766e4e8-9f8d-452c-b2d3-61ea658aedd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759153576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.1759153576
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.3216590132
Short name T678
Test name
Test status
Simulation time 1497801087 ps
CPU time 31.95 seconds
Started Apr 30 01:53:10 PM PDT 24
Finished Apr 30 01:53:43 PM PDT 24
Peak memory 204088 kb
Host smart-bf2b2a10-3b0d-4750-99d1-e3b9345b8f65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216590132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.3216590132
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.3522018981
Short name T312
Test name
Test status
Simulation time 32688321098 ps
CPU time 48.95 seconds
Started Apr 30 01:53:06 PM PDT 24
Finished Apr 30 01:53:56 PM PDT 24
Peak memory 962388 kb
Host smart-03f27159-73ea-4ae7-92f9-86c8ed52eaf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522018981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.3522018981
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.2608893741
Short name T1184
Test name
Test status
Simulation time 33674067306 ps
CPU time 245.55 seconds
Started Apr 30 01:53:11 PM PDT 24
Finished Apr 30 01:57:18 PM PDT 24
Peak memory 936588 kb
Host smart-ee31db4a-2aaa-4ea9-9dc1-2e09e83616e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608893741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.2608893741
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.11276516
Short name T1299
Test name
Test status
Simulation time 5283941262 ps
CPU time 7.04 seconds
Started Apr 30 01:53:06 PM PDT 24
Finished Apr 30 01:53:14 PM PDT 24
Peak memory 218016 kb
Host smart-bf36e5bd-9ad5-4883-8db2-eae48e9293bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11276516 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_timeout.11276516
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.4019322804
Short name T525
Test name
Test status
Simulation time 23273837 ps
CPU time 0.6 seconds
Started Apr 30 01:53:20 PM PDT 24
Finished Apr 30 01:53:21 PM PDT 24
Peak memory 203888 kb
Host smart-1e040722-a31a-4e7e-b570-63f4999d6bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019322804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.4019322804
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1867595937
Short name T841
Test name
Test status
Simulation time 121366003 ps
CPU time 1.73 seconds
Started Apr 30 01:53:13 PM PDT 24
Finished Apr 30 01:53:16 PM PDT 24
Peak memory 212448 kb
Host smart-234eaf7d-2ea9-4c02-a2e2-188dacf8bbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867595937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1867595937
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.2789186583
Short name T760
Test name
Test status
Simulation time 388973625 ps
CPU time 20.44 seconds
Started Apr 30 01:53:15 PM PDT 24
Finished Apr 30 01:53:36 PM PDT 24
Peak memory 282344 kb
Host smart-883b7efa-56b3-41c6-8113-31d2240c96f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789186583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.2789186583
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.4022416386
Short name T50
Test name
Test status
Simulation time 2521496479 ps
CPU time 102.78 seconds
Started Apr 30 01:53:14 PM PDT 24
Finished Apr 30 01:54:58 PM PDT 24
Peak memory 830056 kb
Host smart-f238a8ef-7e98-4e6a-b843-75b74131c5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022416386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.4022416386
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.1019218259
Short name T585
Test name
Test status
Simulation time 2296502021 ps
CPU time 63.17 seconds
Started Apr 30 01:53:15 PM PDT 24
Finished Apr 30 01:54:19 PM PDT 24
Peak memory 683524 kb
Host smart-055c1405-bb5e-4d97-b6d5-c44bc30bd565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019218259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1019218259
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.1785820926
Short name T314
Test name
Test status
Simulation time 1550355266 ps
CPU time 1.04 seconds
Started Apr 30 01:53:15 PM PDT 24
Finished Apr 30 01:53:17 PM PDT 24
Peak memory 204076 kb
Host smart-285575df-acb6-4e95-bfb7-31c7c8368103
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785820926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.1785820926
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.215574312
Short name T90
Test name
Test status
Simulation time 684832769 ps
CPU time 4.52 seconds
Started Apr 30 01:53:13 PM PDT 24
Finished Apr 30 01:53:18 PM PDT 24
Peak memory 236088 kb
Host smart-9d225dc7-6a35-47b7-a2be-77809c70bece
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215574312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.215574312
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.3258240499
Short name T423
Test name
Test status
Simulation time 4609925984 ps
CPU time 128.87 seconds
Started Apr 30 01:53:14 PM PDT 24
Finished Apr 30 01:55:23 PM PDT 24
Peak memory 1163588 kb
Host smart-e48db966-5e58-47ee-8866-b4d10681a714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258240499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.3258240499
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.2031343772
Short name T516
Test name
Test status
Simulation time 314689782 ps
CPU time 6.63 seconds
Started Apr 30 01:53:20 PM PDT 24
Finished Apr 30 01:53:28 PM PDT 24
Peak memory 204056 kb
Host smart-0501c5ff-71d0-4ce3-ae9c-93a62f62ccbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031343772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.2031343772
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.3176085394
Short name T657
Test name
Test status
Simulation time 1505076949 ps
CPU time 28.27 seconds
Started Apr 30 01:53:19 PM PDT 24
Finished Apr 30 01:53:48 PM PDT 24
Peak memory 333440 kb
Host smart-f0d8328e-2a6a-4720-8618-e5bd96624808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176085394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.3176085394
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.2211525767
Short name T185
Test name
Test status
Simulation time 251142796 ps
CPU time 0.65 seconds
Started Apr 30 01:53:14 PM PDT 24
Finished Apr 30 01:53:15 PM PDT 24
Peak memory 203868 kb
Host smart-360bbc63-48ca-48ed-aa8d-f96622835d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211525767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2211525767
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.3976068812
Short name T799
Test name
Test status
Simulation time 6993585442 ps
CPU time 91.23 seconds
Started Apr 30 01:53:14 PM PDT 24
Finished Apr 30 01:54:45 PM PDT 24
Peak memory 364892 kb
Host smart-93a0b1d7-f0fe-4dad-ad90-2a6ed81803d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976068812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.3976068812
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.4224174484
Short name T708
Test name
Test status
Simulation time 1579424765 ps
CPU time 35.02 seconds
Started Apr 30 01:53:13 PM PDT 24
Finished Apr 30 01:53:48 PM PDT 24
Peak memory 413288 kb
Host smart-f1fc755b-e935-4184-9edb-1714504e7c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224174484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.4224174484
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.4092765913
Short name T173
Test name
Test status
Simulation time 53892318297 ps
CPU time 311.07 seconds
Started Apr 30 01:53:17 PM PDT 24
Finished Apr 30 01:58:28 PM PDT 24
Peak memory 1993860 kb
Host smart-f1f215ca-aae6-4d89-8a5f-d0b5b74f0968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092765913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.4092765913
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.2544808466
Short name T959
Test name
Test status
Simulation time 722903429 ps
CPU time 13.02 seconds
Started Apr 30 01:53:14 PM PDT 24
Finished Apr 30 01:53:27 PM PDT 24
Peak memory 220540 kb
Host smart-5819e426-ed92-48d6-9136-1235ed9f8ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544808466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.2544808466
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.642965415
Short name T25
Test name
Test status
Simulation time 1153152874 ps
CPU time 5.22 seconds
Started Apr 30 01:53:22 PM PDT 24
Finished Apr 30 01:53:27 PM PDT 24
Peak memory 212348 kb
Host smart-1286951f-5b3f-43e4-8c3f-de84a00c4dbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642965415 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.642965415
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.1647854168
Short name T705
Test name
Test status
Simulation time 10189645489 ps
CPU time 12.24 seconds
Started Apr 30 01:53:20 PM PDT 24
Finished Apr 30 01:53:33 PM PDT 24
Peak memory 249376 kb
Host smart-71ce368d-0592-41a2-bc31-bb48e316f7c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647854168 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.1647854168
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.1772359276
Short name T1198
Test name
Test status
Simulation time 10106708474 ps
CPU time 31.34 seconds
Started Apr 30 01:53:22 PM PDT 24
Finished Apr 30 01:53:53 PM PDT 24
Peak memory 349216 kb
Host smart-aa37174c-354d-4ed8-9c16-a55cf00184f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772359276 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.1772359276
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.1641644033
Short name T1254
Test name
Test status
Simulation time 1715221655 ps
CPU time 2.06 seconds
Started Apr 30 01:53:18 PM PDT 24
Finished Apr 30 01:53:20 PM PDT 24
Peak memory 204168 kb
Host smart-732ad096-d214-484f-838b-9cd5d7f3fe2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641644033 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.1641644033
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.3484621567
Short name T749
Test name
Test status
Simulation time 764859447 ps
CPU time 4.77 seconds
Started Apr 30 01:53:23 PM PDT 24
Finished Apr 30 01:53:28 PM PDT 24
Peak memory 206168 kb
Host smart-37ace226-0e7b-493d-b69a-4670c7d522df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484621567 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.3484621567
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.2052500629
Short name T13
Test name
Test status
Simulation time 22873324799 ps
CPU time 539.36 seconds
Started Apr 30 01:53:19 PM PDT 24
Finished Apr 30 02:02:19 PM PDT 24
Peak memory 5509164 kb
Host smart-bb73b9f3-4998-4934-bc9e-1b6a39c3fed1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052500629 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.2052500629
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.3967190357
Short name T100
Test name
Test status
Simulation time 2091261668 ps
CPU time 16.08 seconds
Started Apr 30 01:53:19 PM PDT 24
Finished Apr 30 01:53:35 PM PDT 24
Peak memory 204140 kb
Host smart-e2e26324-d074-4d6b-a54a-52522c1ea556
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967190357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.3967190357
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.4222743322
Short name T256
Test name
Test status
Simulation time 1426138456 ps
CPU time 14.98 seconds
Started Apr 30 01:53:24 PM PDT 24
Finished Apr 30 01:53:40 PM PDT 24
Peak memory 204156 kb
Host smart-4e7ff4c9-5888-4e58-b99c-a96f5d1d5386
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222743322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.4222743322
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.677520455
Short name T610
Test name
Test status
Simulation time 10754419813 ps
CPU time 19.29 seconds
Started Apr 30 01:53:19 PM PDT 24
Finished Apr 30 01:53:39 PM PDT 24
Peak memory 204132 kb
Host smart-0eb4a5ee-3767-4102-8d23-071c88eafbf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677520455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_wr.677520455
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.2629069147
Short name T831
Test name
Test status
Simulation time 26202946998 ps
CPU time 1768.88 seconds
Started Apr 30 01:53:21 PM PDT 24
Finished Apr 30 02:22:51 PM PDT 24
Peak memory 3077008 kb
Host smart-eb1ac8f5-e4cc-452f-ab48-62a0e23b2c70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629069147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.2629069147
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.3532541392
Short name T1266
Test name
Test status
Simulation time 1251114939 ps
CPU time 5.93 seconds
Started Apr 30 01:53:22 PM PDT 24
Finished Apr 30 01:53:28 PM PDT 24
Peak memory 210016 kb
Host smart-c8028f37-4a06-4cd0-9fcf-1737a8d30501
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532541392 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.3532541392
Directory /workspace/9.i2c_target_timeout/latest
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