Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	727919	1			T1	7		T2	89		T3	12
all_values[1]	727919	1			T1	7		T2	89		T3	12
all_values[2]	727919	1			T1	7		T2	89		T3	12
all_values[3]	727919	1			T1	7		T2	89		T3	12
all_values[4]	727919	1			T1	7		T2	89		T3	12
all_values[5]	727919	1			T1	7		T2	89		T3	12
all_values[6]	727919	1			T1	7		T2	89		T3	12
all_values[7]	727919	1			T1	7		T2	89		T3	12
all_values[8]	727919	1			T1	7		T2	89		T3	12
all_values[9]	727919	1			T1	7		T2	89		T3	12
all_values[10]	727919	1			T1	7		T2	89		T3	12
all_values[11]	727919	1			T1	7		T2	89		T3	12
all_values[12]	727919	1			T1	7		T2	89		T3	12
all_values[13]	727919	1			T1	7		T2	89		T3	12
all_values[14]	727919	1			T1	7		T2	89		T3	12

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7894426

1

T1

105

T2

1144

T3

180

auto[1]

3024359

1

T2

191

T4

4

T5

145

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9405822

1

T1

105

T2

1335

T3

180

auto[1]

1512963

1

T94

50415

T95

104746

T96

67270

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12] , all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	77497	1			T1	7		T2	16		T3	12
all_values[0]	auto[0]	auto[1]	11525	1			T94	608		T95	217		T96	1159
all_values[0]	auto[1]	auto[0]	545470	1			T2	73		T4	2		T5	60
all_values[0]	auto[1]	auto[1]	93427	1			T94	3269		T95	7265		T96	3327
all_values[1]	auto[0]	auto[0]	620221	1			T1	7		T2	89		T3	12
all_values[1]	auto[0]	auto[1]	106977	1			T94	3870		T95	7420		T96	4481
all_values[1]	auto[1]	auto[0]	308	1			T5	3		T47	3		T48	2
all_values[1]	auto[1]	auto[1]	413	1			T94	9		T95	62		T96	5
all_values[2]	auto[0]	auto[0]	619664	1			T1	7		T2	89		T3	12
all_values[2]	auto[0]	auto[1]	108069	1			T94	3876		T95	7478		T96	4480
all_values[2]	auto[1]	auto[1]	186	1			T94	1		T95	4		T96	2
all_values[3]	auto[0]	auto[0]	619693	1			T1	7		T2	89		T3	12
all_values[3]	auto[0]	auto[1]	108008	1			T94	3878		T95	7475		T96	4481
all_values[3]	auto[1]	auto[1]	218	1			T94	1		T95	7		T96	4
all_values[4]	auto[0]	auto[0]	627751	1			T1	7		T2	88		T3	12
all_values[4]	auto[0]	auto[1]	99970	1			T94	3877		T95	4		T96	4481
all_values[4]	auto[1]	auto[0]	23	1			T2	1		T5	1		T217	1
all_values[4]	auto[1]	auto[1]	175	1			T94	1		T95	1		T96	2
all_values[5]	auto[0]	auto[0]	632121	1			T1	7		T2	89		T3	12
all_values[5]	auto[0]	auto[1]	95589	1			T94	3879		T95	7482		T96	4484
all_values[5]	auto[1]	auto[1]	209	1			T126	2		T87	7		T185	4
all_values[6]	auto[0]	auto[0]	180933	1			T1	7		T2	87		T3	12
all_values[6]	auto[0]	auto[1]	13146	1			T94	467		T95	2812		T96	1098
all_values[6]	auto[1]	auto[0]	465254	1			T2	2		T5	1		T6	4418
all_values[6]	auto[1]	auto[1]	68586	1			T94	3411		T95	4669		T96	3387
all_values[7]	auto[0]	auto[0]	602170	1			T1	7		T2	75		T3	12
all_values[7]	auto[0]	auto[1]	92342	1			T94	3674		T95	6949		T96	4284
all_values[7]	auto[1]	auto[0]	30088	1			T2	14		T5	4		T6	270
all_values[7]	auto[1]	auto[1]	3319	1			T94	204		T95	532		T96	202
all_values[8]	auto[0]	auto[0]	157721	1			T1	7		T2	81		T3	12
all_values[8]	auto[0]	auto[1]	12461	1			T94	26		T95	1709		T96	1106
all_values[8]	auto[1]	auto[0]	461971	1			T2	8		T5	10		T6	4409
all_values[8]	auto[1]	auto[1]	95766	1			T94	3853		T95	5773		T96	3378
all_values[9]	auto[0]	auto[0]	180049	1			T1	7		T2	83		T3	12
all_values[9]	auto[0]	auto[1]	14207	1			T94	322		T95	1915		T96	1165
all_values[9]	auto[1]	auto[0]	439628	1			T2	6		T5	6		T6	4306
all_values[9]	auto[1]	auto[1]	94035	1			T94	3557		T95	5565		T96	3321
all_values[10]	auto[0]	auto[0]	650688	1			T1	7		T2	89		T3	12
all_values[10]	auto[0]	auto[1]	77062	1			T95	7478		T96	4481		T126	3265
all_values[10]	auto[1]	auto[1]	169	1			T95	3		T96	3		T126	2
all_values[11]	auto[0]	auto[0]	2970	1			T1	7		T2	2		T3	12
all_values[11]	auto[0]	auto[1]	404	1			T94	4		T95	22		T181	11
all_values[11]	auto[1]	auto[0]	617336	1			T2	87		T4	2		T5	60
all_values[11]	auto[1]	auto[1]	107209	1			T94	3873		T95	7459		T96	4486
all_values[12]	auto[0]	auto[0]	622954	1			T1	7		T2	89		T3	12
all_values[12]	auto[0]	auto[1]	104799	1			T94	3876		T95	7479		T96	4482
all_values[12]	auto[1]	auto[1]	166	1			T94	2		T95	3		T96	4
all_values[13]	auto[0]	auto[0]	627666	1			T1	7		T2	89		T3	12
all_values[13]	auto[0]	auto[1]	100047	1			T94	3875		T95	7479		T96	4479
all_values[13]	auto[1]	auto[1]	206	1			T94	2		T95	3		T96	2
all_values[14]	auto[0]	auto[0]	623646	1			T1	7		T2	89		T3	12
all_values[14]	auto[0]	auto[1]	104076	1			T95	7476		T96	4483		T181	12434
all_values[14]	auto[1]	auto[1]	197	1			T95	5		T96	3		T181	3