Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	727919	1			T1	7		T2	89		T3	12
all_pins[1]	727919	1			T1	7		T2	89		T3	12
all_pins[2]	727919	1			T1	7		T2	89		T3	12
all_pins[3]	727919	1			T1	7		T2	89		T3	12
all_pins[4]	727919	1			T1	7		T2	89		T3	12
all_pins[5]	727919	1			T1	7		T2	89		T3	12
all_pins[6]	727919	1			T1	7		T2	89		T3	12
all_pins[7]	727919	1			T1	7		T2	89		T3	12
all_pins[8]	727919	1			T1	7		T2	89		T3	12
all_pins[9]	727919	1			T1	7		T2	89		T3	12
all_pins[10]	727919	1			T1	7		T2	89		T3	12
all_pins[11]	727919	1			T1	7		T2	89		T3	12
all_pins[12]	727919	1			T1	7		T2	89		T3	12
all_pins[13]	727919	1			T1	7		T2	89		T3	12
all_pins[14]	727919	1			T1	7		T2	89		T3	12

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	7898793	1			T1	105		T2	1328		T3	180
values[0x1]	3019992	1			T2	7		T4	4		T5	10
transitions[0x0=>0x1]	2446860	1			T2	7		T4	4		T5	10
transitions[0x1=>0x0]	2445826	1			T2	7		T4	3		T5	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	92069	1			T1	7		T2	89		T3	12
all_pins[0]	values[0x1]	635850	1			T4	2		T6	4232		T7	696
all_pins[0]	transitions[0x0=>0x1]	635190	1			T4	2		T6	4232		T7	696
all_pins[0]	transitions[0x1=>0x0]	63	1			T5	3		T94	1		T95	1
all_pins[1]	values[0x0]	727196	1			T1	7		T2	89		T3	12
all_pins[1]	values[0x1]	723	1			T5	3		T47	4		T48	2
all_pins[1]	transitions[0x0=>0x1]	703	1			T5	3		T47	4		T48	2
all_pins[1]	transitions[0x1=>0x0]	69	1			T95	2		T96	1		T126	1
all_pins[2]	values[0x0]	727830	1			T1	7		T2	89		T3	12
all_pins[2]	values[0x1]	89	1			T95	3		T96	1		T126	1
all_pins[2]	transitions[0x0=>0x1]	68	1			T95	2		T96	1		T126	1
all_pins[2]	transitions[0x1=>0x0]	95	1			T94	1		T95	4		T96	1
all_pins[3]	values[0x0]	727803	1			T1	7		T2	89		T3	12
all_pins[3]	values[0x1]	116	1			T94	1		T95	5		T96	1
all_pins[3]	transitions[0x0=>0x1]	90	1			T94	1		T95	5		T96	1
all_pins[3]	transitions[0x1=>0x0]	87	1			T2	1		T5	1		T94	1
all_pins[4]	values[0x0]	727806	1			T1	7		T2	88		T3	12
all_pins[4]	values[0x1]	113	1			T2	1		T5	1		T94	1
all_pins[4]	transitions[0x0=>0x1]	91	1			T2	1		T5	1		T94	1
all_pins[4]	transitions[0x1=>0x0]	85	1			T87	2		T185	2		T248	3
all_pins[5]	values[0x0]	727812	1			T1	7		T2	89		T3	12
all_pins[5]	values[0x1]	107	1			T87	2		T185	2		T248	3
all_pins[5]	transitions[0x0=>0x1]	79	1			T87	2		T248	2		T249	1
all_pins[5]	transitions[0x1=>0x0]	533524	1			T6	4418		T60	1		T47	11
all_pins[6]	values[0x0]	194367	1			T1	7		T2	89		T3	12
all_pins[6]	values[0x1]	533552	1			T6	4418		T60	1		T47	11
all_pins[6]	transitions[0x0=>0x1]	514567	1			T6	4106		T47	7		T50	1
all_pins[6]	transitions[0x1=>0x0]	17648	1			T7	320		T47	123		T78	1
all_pins[7]	values[0x0]	691286	1			T1	7		T2	89		T3	12
all_pins[7]	values[0x1]	36633	1			T6	312		T7	320		T60	1
all_pins[7]	transitions[0x0=>0x1]	14825	1			T7	260		T47	105		T79	32
all_pins[7]	transitions[0x1=>0x0]	535796	1			T6	4098		T7	71		T10	1
all_pins[8]	values[0x0]	170315	1			T1	7		T2	89		T3	12
all_pins[8]	values[0x1]	557604	1			T6	4410		T7	131		T10	1
all_pins[8]	transitions[0x0=>0x1]	26204	1			T6	104		T7	130		T47	41
all_pins[8]	transitions[0x1=>0x0]	2191	1			T2	6		T5	6		T7	2
all_pins[9]	values[0x0]	194328	1			T1	7		T2	83		T3	12
all_pins[9]	values[0x1]	533591	1			T2	6		T5	6		T6	4306
all_pins[9]	transitions[0x0=>0x1]	533568	1			T2	6		T5	6		T6	4306
all_pins[9]	transitions[0x1=>0x0]	62	1			T95	3		T96	2		T126	1
all_pins[10]	values[0x0]	727834	1			T1	7		T2	89		T3	12
all_pins[10]	values[0x1]	85	1			T95	3		T96	2		T126	1
all_pins[10]	transitions[0x0=>0x1]	47	1			T95	2		T96	1		T87	1
all_pins[10]	transitions[0x1=>0x0]	721197	1			T4	2		T6	4422		T7	1317
all_pins[11]	values[0x0]	6684	1			T1	7		T2	89		T3	12
all_pins[11]	values[0x1]	721235	1			T4	2		T6	4422		T7	1317
all_pins[11]	transitions[0x0=>0x1]	721215	1			T4	2		T6	4422		T7	1317
all_pins[11]	transitions[0x1=>0x0]	54	1			T95	1		T96	1		T181	1
all_pins[12]	values[0x0]	727845	1			T1	7		T2	89		T3	12
all_pins[12]	values[0x1]	74	1			T95	1		T96	1		T181	1
all_pins[12]	transitions[0x0=>0x1]	58	1			T96	1		T181	1		T185	1
all_pins[12]	transitions[0x1=>0x0]	104	1			T94	2		T95	2		T181	2
all_pins[13]	values[0x0]	727799	1			T1	7		T2	89		T3	12
all_pins[13]	values[0x1]	120	1			T94	2		T95	3		T181	2
all_pins[13]	transitions[0x0=>0x1]	88	1			T94	2		T95	2		T87	5
all_pins[13]	transitions[0x1=>0x0]	68	1			T95	1		T96	1		T87	2
all_pins[14]	values[0x0]	727819	1			T1	7		T2	89		T3	12
all_pins[14]	values[0x1]	100	1			T95	2		T96	1		T181	2
all_pins[14]	transitions[0x0=>0x1]	67	1			T95	1		T181	1		T87	2
all_pins[14]	transitions[0x1=>0x0]	634783	1			T4	1		T6	4231		T7	695