Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	426	1			T94	4		T95	8		T96	7
all_values[1]	426	1			T94	4		T95	8		T96	7
all_values[2]	426	1			T94	4		T95	8		T96	7
all_values[3]	426	1			T94	4		T95	8		T96	7
all_values[4]	426	1			T94	4		T95	8		T96	7
all_values[5]	426	1			T94	4		T95	8		T96	7
all_values[6]	426	1			T94	4		T95	8		T96	7
all_values[7]	426	1			T94	4		T95	8		T96	7
all_values[8]	426	1			T94	4		T95	8		T96	7
all_values[9]	426	1			T94	4		T95	8		T96	7
all_values[10]	426	1			T94	4		T95	8		T96	7
all_values[11]	426	1			T94	4		T95	8		T96	7
all_values[12]	426	1			T94	4		T95	8		T96	7
all_values[13]	426	1			T94	4		T95	8		T96	7
all_values[14]	426	1			T94	4		T95	8		T96	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3323

1

T94

37

T95

56

T96

53

auto[1]

3067

1

T94

23

T95

64

T96

52

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1096

1

T94

20

T95

12

T96

20

auto[1]

5294

1

T94

40

T95

108

T96

85

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3832

1

T94

41

T95

79

T96

55

auto[1]

2558

1

T94

19

T95

41

T96

50

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	51	1			T94	1		T87	2		T185	2
all_values[0]	auto[0]	auto[0]	auto[1]	85	1			T95	2		T96	1		T87	3
all_values[0]	auto[0]	auto[1]	auto[0]	32	1			T94	1		T126	4		T87	3
all_values[0]	auto[0]	auto[1]	auto[1]	94	1			T94	1		T95	3		T96	2
all_values[0]	auto[1]	auto[0]	auto[1]	85	1			T95	1		T96	1		T87	1
all_values[0]	auto[1]	auto[1]	auto[1]	79	1			T94	1		T95	2		T96	3
all_values[1]	auto[0]	auto[0]	auto[0]	37	1			T87	2		T185	4		T250	4
all_values[1]	auto[0]	auto[0]	auto[1]	105	1			T94	1		T95	1		T96	2
all_values[1]	auto[0]	auto[1]	auto[0]	33	1			T87	2		T248	3		T65	1
all_values[1]	auto[0]	auto[1]	auto[1]	84	1			T94	1		T95	3		T181	2
all_values[1]	auto[1]	auto[0]	auto[1]	97	1			T94	1		T95	3		T126	2
all_values[1]	auto[1]	auto[1]	auto[1]	70	1			T94	1		T95	1		T96	5
all_values[2]	auto[0]	auto[0]	auto[0]	29	1			T94	2		T96	2		T248	2
all_values[2]	auto[0]	auto[0]	auto[1]	87	1			T94	1		T95	2		T181	3
all_values[2]	auto[0]	auto[1]	auto[0]	21	1			T96	2		T251	1		T252	3
all_values[2]	auto[0]	auto[1]	auto[1]	103	1			T95	2		T96	1		T126	1
all_values[2]	auto[1]	auto[0]	auto[1]	101	1			T94	1		T95	1		T96	2
all_values[2]	auto[1]	auto[1]	auto[1]	85	1			T95	3		T181	1		T126	2
all_values[3]	auto[0]	auto[0]	auto[0]	49	1			T185	1		T251	2		T253	1
all_values[3]	auto[0]	auto[0]	auto[1]	93	1			T94	3		T95	1		T96	1
all_values[3]	auto[0]	auto[1]	auto[0]	25	1			T96	1		T181	1		T126	2
all_values[3]	auto[0]	auto[1]	auto[1]	91	1			T95	4		T96	1		T87	3
all_values[3]	auto[1]	auto[0]	auto[1]	89	1			T94	1		T95	2		T96	1
all_values[3]	auto[1]	auto[1]	auto[1]	79	1			T95	1		T96	3		T87	2
all_values[4]	auto[0]	auto[0]	auto[0]	31	1			T94	1		T96	2		T87	2
all_values[4]	auto[0]	auto[0]	auto[1]	90	1			T95	2		T96	1		T181	1
all_values[4]	auto[0]	auto[1]	auto[0]	30	1			T95	5		T96	1		T185	3
all_values[4]	auto[0]	auto[1]	auto[1]	100	1			T94	2		T96	1		T181	1
all_values[4]	auto[1]	auto[0]	auto[1]	95	1			T96	2		T181	1		T126	1
all_values[4]	auto[1]	auto[1]	auto[1]	80	1			T94	1		T95	1		T181	1
all_values[5]	auto[0]	auto[0]	auto[0]	37	1			T96	1		T181	1		T249	2
all_values[5]	auto[0]	auto[0]	auto[1]	102	1			T94	2		T95	5		T96	1
all_values[5]	auto[0]	auto[1]	auto[0]	32	1			T96	1		T181	3		T65	1
all_values[5]	auto[0]	auto[1]	auto[1]	88	1			T95	2		T96	2		T126	1
all_values[5]	auto[1]	auto[0]	auto[1]	88	1			T94	1		T95	1		T96	1
all_values[5]	auto[1]	auto[1]	auto[1]	79	1			T94	1		T96	1		T126	1
all_values[6]	auto[0]	auto[0]	auto[0]	50	1			T94	1		T95	1		T96	1
all_values[6]	auto[0]	auto[0]	auto[1]	87	1			T94	2		T95	3		T96	1
all_values[6]	auto[0]	auto[1]	auto[0]	43	1			T181	1		T126	3		T249	1
all_values[6]	auto[0]	auto[1]	auto[1]	88	1			T95	2		T96	2		T181	1
all_values[6]	auto[1]	auto[0]	auto[1]	77	1			T95	1		T87	3		T185	1
all_values[6]	auto[1]	auto[1]	auto[1]	81	1			T94	1		T95	1		T96	3
all_values[7]	auto[0]	auto[0]	auto[0]	30	1			T94	1		T254	1		T255	4
all_values[7]	auto[0]	auto[0]	auto[1]	98	1			T94	2		T95	3		T96	2
all_values[7]	auto[0]	auto[1]	auto[0]	35	1			T95	1		T248	1		T249	3
all_values[7]	auto[0]	auto[1]	auto[1]	100	1			T95	1		T96	1		T181	2
all_values[7]	auto[1]	auto[0]	auto[1]	82	1			T95	3		T96	1		T87	3
all_values[7]	auto[1]	auto[1]	auto[1]	81	1			T94	1		T96	3		T181	2
all_values[8]	auto[0]	auto[0]	auto[0]	47	1			T87	1		T65	1		T250	1
all_values[8]	auto[0]	auto[0]	auto[1]	82	1			T95	4		T96	3		T181	1
all_values[8]	auto[0]	auto[1]	auto[0]	28	1			T96	2		T126	1		T256	1
all_values[8]	auto[0]	auto[1]	auto[1]	106	1			T94	1		T95	2		T181	2
all_values[8]	auto[1]	auto[0]	auto[1]	95	1			T94	2		T95	1		T96	1
all_values[8]	auto[1]	auto[1]	auto[1]	68	1			T94	1		T95	1		T96	1
all_values[9]	auto[0]	auto[0]	auto[0]	39	1			T95	1		T185	1		T249	2
all_values[9]	auto[0]	auto[0]	auto[1]	91	1			T94	2		T95	2		T96	2
all_values[9]	auto[0]	auto[1]	auto[0]	24	1			T95	1		T87	1		T249	2
all_values[9]	auto[0]	auto[1]	auto[1]	95	1			T95	3		T181	1		T87	4
all_values[9]	auto[1]	auto[0]	auto[1]	95	1			T94	1		T96	3		T126	1
all_values[9]	auto[1]	auto[1]	auto[1]	82	1			T94	1		T95	1		T96	2
all_values[10]	auto[0]	auto[0]	auto[0]	51	1			T94	3		T96	1		T181	3
all_values[10]	auto[0]	auto[0]	auto[1]	78	1			T126	1		T87	1		T248	1
all_values[10]	auto[0]	auto[1]	auto[0]	41	1			T94	1		T95	1		T96	1
all_values[10]	auto[0]	auto[1]	auto[1]	87	1			T95	4		T96	2		T87	3
all_values[10]	auto[1]	auto[0]	auto[1]	90	1			T96	1		T126	1		T87	1
all_values[10]	auto[1]	auto[1]	auto[1]	79	1			T95	3		T96	2		T126	1
all_values[11]	auto[0]	auto[0]	auto[0]	41	1			T94	2		T95	1		T185	4
all_values[11]	auto[0]	auto[0]	auto[1]	81	1			T95	2		T96	1		T87	5
all_values[11]	auto[0]	auto[1]	auto[0]	24	1			T181	2		T248	1		T249	2
all_values[11]	auto[0]	auto[1]	auto[1]	98	1			T94	1		T95	1		T96	1
all_values[11]	auto[1]	auto[0]	auto[1]	98	1			T95	2		T96	4		T126	1
all_values[11]	auto[1]	auto[1]	auto[1]	84	1			T94	1		T95	2		T96	1
all_values[12]	auto[0]	auto[0]	auto[0]	48	1			T94	1		T126	1		T185	1
all_values[12]	auto[0]	auto[0]	auto[1]	87	1			T94	1		T95	5		T96	2
all_values[12]	auto[0]	auto[1]	auto[0]	29	1			T126	3		T87	2		T248	1
all_values[12]	auto[0]	auto[1]	auto[1]	96	1			T96	1		T87	2		T185	1
all_values[12]	auto[1]	auto[0]	auto[1]	89	1			T94	2		T95	2		T96	3
all_values[12]	auto[1]	auto[1]	auto[1]	77	1			T95	1		T96	1		T181	1
all_values[13]	auto[0]	auto[0]	auto[0]	56	1			T94	1		T96	4		T87	4
all_values[13]	auto[0]	auto[0]	auto[1]	64	1			T96	1		T249	2		T65	2
all_values[13]	auto[0]	auto[1]	auto[0]	24	1			T94	1		T96	1		T181	1
all_values[13]	auto[0]	auto[1]	auto[1]	107	1			T94	1		T95	5		T181	2
all_values[13]	auto[1]	auto[0]	auto[1]	92	1			T96	1		T181	1		T126	1
all_values[13]	auto[1]	auto[1]	auto[1]	83	1			T94	1		T95	3		T126	1
all_values[14]	auto[0]	auto[0]	auto[0]	41	1			T94	1		T65	1		T250	1
all_values[14]	auto[0]	auto[0]	auto[1]	88	1			T95	1		T96	2		T87	2
all_values[14]	auto[0]	auto[1]	auto[0]	38	1			T94	3		T95	1		T181	1
all_values[14]	auto[0]	auto[1]	auto[1]	81	1			T95	2		T96	1		T181	1
all_values[14]	auto[1]	auto[0]	auto[1]	95	1			T95	3		T96	1		T181	1
all_values[14]	auto[1]	auto[1]	auto[1]	83	1			T95	1		T96	3		T181	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal