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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.50 97.12 91.38 97.66 83.58 94.37 98.67 91.70


Total test records in report: 1472
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T1310 /workspace/coverage/default/39.i2c_host_fifo_reset_rx.260011250 May 07 12:58:07 PM PDT 24 May 07 12:58:20 PM PDT 24 875960837 ps
T1311 /workspace/coverage/default/16.i2c_host_error_intr.2662664031 May 07 12:54:39 PM PDT 24 May 07 12:54:42 PM PDT 24 91253794 ps
T1312 /workspace/coverage/default/35.i2c_host_smoke.1096421171 May 07 12:57:20 PM PDT 24 May 07 12:57:44 PM PDT 24 1022913166 ps
T1313 /workspace/coverage/default/33.i2c_target_stretch.4128975965 May 07 12:57:14 PM PDT 24 May 07 12:58:44 PM PDT 24 3774398430 ps
T1314 /workspace/coverage/default/46.i2c_host_error_intr.2280002414 May 07 12:58:57 PM PDT 24 May 07 12:59:00 PM PDT 24 80413449 ps
T1315 /workspace/coverage/default/46.i2c_host_smoke.765131959 May 07 12:58:56 PM PDT 24 May 07 12:59:18 PM PDT 24 7520734159 ps
T1316 /workspace/coverage/default/21.i2c_target_intr_stress_wr.1736564047 May 07 12:55:29 PM PDT 24 May 07 01:01:27 PM PDT 24 17389992498 ps
T1317 /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.2757061972 May 07 12:58:03 PM PDT 24 May 07 12:58:05 PM PDT 24 92286210 ps
T1318 /workspace/coverage/default/15.i2c_host_fifo_reset_rx.2145240695 May 07 12:54:31 PM PDT 24 May 07 12:54:43 PM PDT 24 180330273 ps
T1319 /workspace/coverage/default/44.i2c_target_fifo_reset_tx.2175807429 May 07 12:58:43 PM PDT 24 May 07 12:58:58 PM PDT 24 10267603066 ps
T1320 /workspace/coverage/default/7.i2c_target_smoke.484209488 May 07 12:53:17 PM PDT 24 May 07 12:53:31 PM PDT 24 1080546946 ps
T1321 /workspace/coverage/default/30.i2c_host_fifo_overflow.20898538 May 07 12:56:49 PM PDT 24 May 07 12:58:30 PM PDT 24 5971547002 ps
T1322 /workspace/coverage/default/39.i2c_target_fifo_reset_tx.1646683577 May 07 12:58:01 PM PDT 24 May 07 12:59:18 PM PDT 24 10108006205 ps
T1323 /workspace/coverage/default/12.i2c_target_stress_wr.2798479369 May 07 12:54:08 PM PDT 24 May 07 12:54:20 PM PDT 24 19641352051 ps
T1324 /workspace/coverage/default/1.i2c_target_hrst.2071998884 May 07 12:52:10 PM PDT 24 May 07 12:52:15 PM PDT 24 2115074923 ps
T1325 /workspace/coverage/default/27.i2c_target_intr_smoke.638378452 May 07 12:56:24 PM PDT 24 May 07 12:56:30 PM PDT 24 4038834159 ps
T1326 /workspace/coverage/default/34.i2c_host_fifo_watermark.2604906227 May 07 12:57:14 PM PDT 24 May 07 12:58:51 PM PDT 24 16368102657 ps
T1327 /workspace/coverage/default/8.i2c_host_fifo_overflow.2758139385 May 07 12:53:16 PM PDT 24 May 07 12:54:25 PM PDT 24 2070133049 ps
T1328 /workspace/coverage/default/28.i2c_host_fifo_watermark.1662847362 May 07 12:56:21 PM PDT 24 May 07 01:00:45 PM PDT 24 16776804917 ps
T1329 /workspace/coverage/default/19.i2c_host_mode_toggle.2277473409 May 07 12:55:16 PM PDT 24 May 07 12:56:10 PM PDT 24 2293651338 ps
T1330 /workspace/coverage/default/29.i2c_host_fifo_full.548333501 May 07 12:56:40 PM PDT 24 May 07 12:57:20 PM PDT 24 2205160605 ps
T1331 /workspace/coverage/default/23.i2c_host_error_intr.2021803195 May 07 12:55:40 PM PDT 24 May 07 12:55:43 PM PDT 24 92945516 ps
T1332 /workspace/coverage/default/42.i2c_target_stretch.3841541120 May 07 12:58:19 PM PDT 24 May 07 01:14:26 PM PDT 24 37895396103 ps
T1333 /workspace/coverage/default/39.i2c_host_mode_toggle.2329668312 May 07 12:58:07 PM PDT 24 May 07 12:59:21 PM PDT 24 4464250177 ps
T1334 /workspace/coverage/default/28.i2c_target_stress_rd.2560350404 May 07 12:56:25 PM PDT 24 May 07 12:56:35 PM PDT 24 10771870749 ps
T240 /workspace/coverage/default/24.i2c_host_stretch_timeout.3467275805 May 07 12:55:57 PM PDT 24 May 07 12:56:17 PM PDT 24 7839499929 ps
T1335 /workspace/coverage/default/15.i2c_target_stress_wr.522909324 May 07 12:54:31 PM PDT 24 May 07 01:15:35 PM PDT 24 52695865778 ps
T1336 /workspace/coverage/default/48.i2c_target_intr_stress_wr.2593618688 May 07 12:59:07 PM PDT 24 May 07 01:00:00 PM PDT 24 18913617118 ps
T1337 /workspace/coverage/default/34.i2c_target_stretch.3689125924 May 07 12:57:23 PM PDT 24 May 07 01:04:06 PM PDT 24 21120955961 ps
T1338 /workspace/coverage/default/3.i2c_target_intr_smoke.1689926084 May 07 12:52:31 PM PDT 24 May 07 12:52:37 PM PDT 24 4305711178 ps
T1339 /workspace/coverage/default/0.i2c_target_intr_stress_wr.2558874197 May 07 12:51:48 PM PDT 24 May 07 12:54:27 PM PDT 24 10141736691 ps
T1340 /workspace/coverage/default/8.i2c_host_stress_all.2657284160 May 07 12:53:23 PM PDT 24 May 07 01:11:27 PM PDT 24 35323097069 ps
T1341 /workspace/coverage/default/11.i2c_target_fifo_reset_tx.2523726770 May 07 12:53:59 PM PDT 24 May 07 12:54:09 PM PDT 24 10588150492 ps
T1342 /workspace/coverage/default/27.i2c_target_fifo_reset_acq.23781956 May 07 12:56:25 PM PDT 24 May 07 12:56:56 PM PDT 24 10214462356 ps
T1343 /workspace/coverage/default/4.i2c_target_stretch.3973608951 May 07 12:52:44 PM PDT 24 May 07 01:09:02 PM PDT 24 16831761543 ps
T1344 /workspace/coverage/default/44.i2c_target_stress_rd.2391764999 May 07 12:58:53 PM PDT 24 May 07 12:59:21 PM PDT 24 14931325628 ps
T1345 /workspace/coverage/default/39.i2c_target_timeout.3831306107 May 07 12:58:03 PM PDT 24 May 07 12:58:10 PM PDT 24 4660679959 ps
T1346 /workspace/coverage/default/1.i2c_host_error_intr.2418055276 May 07 12:52:01 PM PDT 24 May 07 12:52:03 PM PDT 24 100703828 ps
T1347 /workspace/coverage/default/12.i2c_host_smoke.314066996 May 07 12:54:03 PM PDT 24 May 07 12:54:38 PM PDT 24 3196872996 ps
T1348 /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.590161265 May 07 12:53:10 PM PDT 24 May 07 12:53:12 PM PDT 24 91621114 ps
T1349 /workspace/coverage/default/47.i2c_target_intr_stress_wr.897894678 May 07 12:59:06 PM PDT 24 May 07 12:59:15 PM PDT 24 10182975122 ps
T1350 /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.2265933615 May 07 12:51:40 PM PDT 24 May 07 12:51:42 PM PDT 24 616309866 ps
T1351 /workspace/coverage/default/45.i2c_host_stretch_timeout.2617884316 May 07 12:58:54 PM PDT 24 May 07 12:59:20 PM PDT 24 1128225588 ps
T1352 /workspace/coverage/default/46.i2c_target_intr_smoke.350992068 May 07 12:58:56 PM PDT 24 May 07 12:59:04 PM PDT 24 1617232656 ps
T1353 /workspace/coverage/default/36.i2c_host_fifo_reset_rx.367268930 May 07 12:57:33 PM PDT 24 May 07 12:57:38 PM PDT 24 500580406 ps
T1354 /workspace/coverage/default/36.i2c_host_smoke.4153722305 May 07 12:57:33 PM PDT 24 May 07 12:57:55 PM PDT 24 994141048 ps
T1355 /workspace/coverage/default/8.i2c_target_hrst.2995841611 May 07 12:53:29 PM PDT 24 May 07 12:53:33 PM PDT 24 1476859816 ps
T1356 /workspace/coverage/default/26.i2c_target_hrst.198432897 May 07 12:56:12 PM PDT 24 May 07 12:56:18 PM PDT 24 284121055 ps
T1357 /workspace/coverage/default/14.i2c_host_fifo_reset_rx.2776449086 May 07 12:54:18 PM PDT 24 May 07 12:54:22 PM PDT 24 198070978 ps
T1358 /workspace/coverage/default/8.i2c_alert_test.2271709434 May 07 12:53:28 PM PDT 24 May 07 12:53:31 PM PDT 24 25071149 ps
T1359 /workspace/coverage/default/17.i2c_target_timeout.837969225 May 07 12:54:52 PM PDT 24 May 07 12:55:01 PM PDT 24 1541794005 ps
T1360 /workspace/coverage/default/35.i2c_host_may_nack.1462519236 May 07 12:57:33 PM PDT 24 May 07 12:57:39 PM PDT 24 1107157351 ps
T1361 /workspace/coverage/default/32.i2c_target_intr_stress_wr.2256389176 May 07 12:57:00 PM PDT 24 May 07 01:01:30 PM PDT 24 19428644316 ps
T1362 /workspace/coverage/default/48.i2c_target_stretch.3055886369 May 07 12:59:08 PM PDT 24 May 07 01:34:31 PM PDT 24 15009048951 ps
T1363 /workspace/coverage/default/20.i2c_host_fifo_reset_rx.274837802 May 07 12:55:18 PM PDT 24 May 07 12:55:23 PM PDT 24 514144108 ps
T1364 /workspace/coverage/default/48.i2c_target_stress_wr.998599138 May 07 12:59:06 PM PDT 24 May 07 12:59:45 PM PDT 24 24187412763 ps
T1365 /workspace/coverage/default/32.i2c_target_stress_wr.2768166180 May 07 12:56:59 PM PDT 24 May 07 01:32:47 PM PDT 24 61985606942 ps
T122 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2404514620 May 07 12:40:27 PM PDT 24 May 07 12:40:30 PM PDT 24 35956113 ps
T91 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.255719624 May 07 12:40:17 PM PDT 24 May 07 12:40:22 PM PDT 24 173228557 ps
T1366 /workspace/coverage/cover_reg_top/10.i2c_intr_test.1421907254 May 07 12:40:42 PM PDT 24 May 07 12:40:44 PM PDT 24 30561122 ps
T194 /workspace/coverage/cover_reg_top/34.i2c_intr_test.1314534574 May 07 12:40:44 PM PDT 24 May 07 12:40:47 PM PDT 24 38922578 ps
T123 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2471596804 May 07 12:40:34 PM PDT 24 May 07 12:40:36 PM PDT 24 203826009 ps
T92 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3456333535 May 07 12:40:40 PM PDT 24 May 07 12:40:42 PM PDT 24 23296496 ps
T93 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3733722382 May 07 12:40:32 PM PDT 24 May 07 12:40:39 PM PDT 24 421752107 ps
T255 /workspace/coverage/cover_reg_top/24.i2c_intr_test.4183566284 May 07 12:40:37 PM PDT 24 May 07 12:40:39 PM PDT 24 67009524 ps
T160 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3581284391 May 07 12:40:40 PM PDT 24 May 07 12:40:43 PM PDT 24 59946285 ps
T161 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1162242167 May 07 12:40:26 PM PDT 24 May 07 12:40:28 PM PDT 24 24652771 ps
T1367 /workspace/coverage/cover_reg_top/37.i2c_intr_test.1962539017 May 07 12:40:41 PM PDT 24 May 07 12:40:44 PM PDT 24 42066753 ps
T1368 /workspace/coverage/cover_reg_top/49.i2c_intr_test.3917639215 May 07 12:40:53 PM PDT 24 May 07 12:40:55 PM PDT 24 192116039 ps
T134 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1372627937 May 07 12:40:40 PM PDT 24 May 07 12:40:43 PM PDT 24 82522064 ps
T1369 /workspace/coverage/cover_reg_top/38.i2c_intr_test.1906890304 May 07 12:40:46 PM PDT 24 May 07 12:40:50 PM PDT 24 45515352 ps
T195 /workspace/coverage/cover_reg_top/0.i2c_intr_test.1125522311 May 07 12:40:12 PM PDT 24 May 07 12:40:15 PM PDT 24 21191596 ps
T1370 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.404115483 May 07 12:40:13 PM PDT 24 May 07 12:40:17 PM PDT 24 48356368 ps
T174 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2773508150 May 07 12:40:37 PM PDT 24 May 07 12:40:40 PM PDT 24 76547255 ps
T135 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2283469199 May 07 12:40:41 PM PDT 24 May 07 12:40:46 PM PDT 24 563477649 ps
T175 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1019698433 May 07 12:40:37 PM PDT 24 May 07 12:40:40 PM PDT 24 61553609 ps
T162 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2798546736 May 07 12:40:48 PM PDT 24 May 07 12:40:52 PM PDT 24 93244575 ps
T176 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3680455649 May 07 12:40:46 PM PDT 24 May 07 12:40:50 PM PDT 24 83121298 ps
T1371 /workspace/coverage/cover_reg_top/43.i2c_intr_test.1110767629 May 07 12:40:41 PM PDT 24 May 07 12:40:44 PM PDT 24 19927489 ps
T158 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.30473660 May 07 12:40:26 PM PDT 24 May 07 12:40:28 PM PDT 24 101239243 ps
T159 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.711703517 May 07 12:40:36 PM PDT 24 May 07 12:40:38 PM PDT 24 58745789 ps
T136 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2160473732 May 07 12:40:15 PM PDT 24 May 07 12:40:20 PM PDT 24 79185462 ps
T177 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.434243396 May 07 12:40:17 PM PDT 24 May 07 12:40:21 PM PDT 24 256857450 ps
T1372 /workspace/coverage/cover_reg_top/42.i2c_intr_test.2251194487 May 07 12:40:43 PM PDT 24 May 07 12:40:46 PM PDT 24 20348810 ps
T1373 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1577958642 May 07 12:40:12 PM PDT 24 May 07 12:40:15 PM PDT 24 38950386 ps
T178 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2915968159 May 07 12:40:13 PM PDT 24 May 07 12:40:17 PM PDT 24 143823375 ps
T179 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1947860387 May 07 12:40:43 PM PDT 24 May 07 12:40:46 PM PDT 24 30014658 ps
T1374 /workspace/coverage/cover_reg_top/44.i2c_intr_test.2002937487 May 07 12:40:55 PM PDT 24 May 07 12:40:57 PM PDT 24 25796638 ps
T180 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.214774655 May 07 12:40:48 PM PDT 24 May 07 12:40:52 PM PDT 24 34485571 ps
T182 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2992644157 May 07 12:40:10 PM PDT 24 May 07 12:40:13 PM PDT 24 70163205 ps
T1375 /workspace/coverage/cover_reg_top/32.i2c_intr_test.2968434693 May 07 12:40:43 PM PDT 24 May 07 12:40:46 PM PDT 24 17110714 ps
T163 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1978658196 May 07 12:40:30 PM PDT 24 May 07 12:40:32 PM PDT 24 27811942 ps
T137 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2721206545 May 07 12:40:11 PM PDT 24 May 07 12:40:15 PM PDT 24 1354430613 ps
T140 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3008679237 May 07 12:40:48 PM PDT 24 May 07 12:40:57 PM PDT 24 32536655 ps
T141 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2152347245 May 07 12:40:42 PM PDT 24 May 07 12:40:46 PM PDT 24 101270284 ps
T1376 /workspace/coverage/cover_reg_top/25.i2c_intr_test.932403462 May 07 12:40:42 PM PDT 24 May 07 12:40:44 PM PDT 24 18115140 ps
T164 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1434106623 May 07 12:40:47 PM PDT 24 May 07 12:40:51 PM PDT 24 57806994 ps
T1377 /workspace/coverage/cover_reg_top/30.i2c_intr_test.609537998 May 07 12:40:39 PM PDT 24 May 07 12:40:41 PM PDT 24 41815154 ps
T1378 /workspace/coverage/cover_reg_top/27.i2c_intr_test.3827988238 May 07 12:40:39 PM PDT 24 May 07 12:40:40 PM PDT 24 20500786 ps
T142 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1342513620 May 07 12:40:15 PM PDT 24 May 07 12:40:19 PM PDT 24 101489963 ps
T150 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1125260583 May 07 12:40:22 PM PDT 24 May 07 12:40:26 PM PDT 24 52883469 ps
T1379 /workspace/coverage/cover_reg_top/45.i2c_intr_test.252447607 May 07 12:40:47 PM PDT 24 May 07 12:40:51 PM PDT 24 31073238 ps
T1380 /workspace/coverage/cover_reg_top/35.i2c_intr_test.1304775395 May 07 12:40:54 PM PDT 24 May 07 12:40:57 PM PDT 24 57530514 ps
T148 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.605581825 May 07 12:40:20 PM PDT 24 May 07 12:40:26 PM PDT 24 549578382 ps
T1381 /workspace/coverage/cover_reg_top/48.i2c_intr_test.3578147050 May 07 12:40:44 PM PDT 24 May 07 12:40:48 PM PDT 24 41970591 ps
T1382 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3901162384 May 07 12:40:20 PM PDT 24 May 07 12:40:24 PM PDT 24 34502650 ps
T165 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1201025272 May 07 12:40:19 PM PDT 24 May 07 12:40:25 PM PDT 24 1291085482 ps
T1383 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1044444939 May 07 12:40:15 PM PDT 24 May 07 12:40:19 PM PDT 24 133585323 ps
T1384 /workspace/coverage/cover_reg_top/9.i2c_intr_test.3251974045 May 07 12:40:16 PM PDT 24 May 07 12:40:20 PM PDT 24 23460920 ps
T1385 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3561796797 May 07 12:40:44 PM PDT 24 May 07 12:40:48 PM PDT 24 47036411 ps
T138 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3061873224 May 07 12:40:21 PM PDT 24 May 07 12:40:25 PM PDT 24 24770545 ps
T1386 /workspace/coverage/cover_reg_top/16.i2c_intr_test.916029009 May 07 12:40:44 PM PDT 24 May 07 12:40:48 PM PDT 24 18538416 ps
T147 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3697052857 May 07 12:40:40 PM PDT 24 May 07 12:40:44 PM PDT 24 84404533 ps
T1387 /workspace/coverage/cover_reg_top/41.i2c_intr_test.3791682767 May 07 12:40:40 PM PDT 24 May 07 12:40:42 PM PDT 24 24829318 ps
T153 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1860537065 May 07 12:40:37 PM PDT 24 May 07 12:40:39 PM PDT 24 81584797 ps
T143 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1949637956 May 07 12:40:41 PM PDT 24 May 07 12:40:45 PM PDT 24 311075392 ps
T152 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.697234673 May 07 12:40:37 PM PDT 24 May 07 12:40:40 PM PDT 24 219163804 ps
T1388 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.27765527 May 07 12:40:18 PM PDT 24 May 07 12:40:22 PM PDT 24 112655656 ps
T139 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.438955125 May 07 12:40:24 PM PDT 24 May 07 12:40:28 PM PDT 24 126949694 ps
T1389 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3797694173 May 07 12:40:59 PM PDT 24 May 07 12:41:02 PM PDT 24 123294958 ps
T218 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.73484644 May 07 12:40:29 PM PDT 24 May 07 12:40:31 PM PDT 24 84464285 ps
T1390 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1817520184 May 07 12:40:22 PM PDT 24 May 07 12:40:25 PM PDT 24 83917643 ps
T146 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.4050407060 May 07 12:40:43 PM PDT 24 May 07 12:40:47 PM PDT 24 83081165 ps
T1391 /workspace/coverage/cover_reg_top/26.i2c_intr_test.1722919524 May 07 12:40:43 PM PDT 24 May 07 12:40:46 PM PDT 24 18461174 ps
T166 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3347019076 May 07 12:40:47 PM PDT 24 May 07 12:40:51 PM PDT 24 21713299 ps
T1392 /workspace/coverage/cover_reg_top/21.i2c_intr_test.1238037335 May 07 12:40:42 PM PDT 24 May 07 12:40:45 PM PDT 24 22378657 ps
T167 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3067497685 May 07 12:40:34 PM PDT 24 May 07 12:40:35 PM PDT 24 27177532 ps
T1393 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1552778685 May 07 12:40:33 PM PDT 24 May 07 12:40:36 PM PDT 24 288250899 ps
T1394 /workspace/coverage/cover_reg_top/20.i2c_intr_test.2313920287 May 07 12:40:40 PM PDT 24 May 07 12:40:42 PM PDT 24 16857506 ps
T1395 /workspace/coverage/cover_reg_top/1.i2c_intr_test.1624862678 May 07 12:40:20 PM PDT 24 May 07 12:40:24 PM PDT 24 34458276 ps
T1396 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.854921796 May 07 12:40:42 PM PDT 24 May 07 12:40:46 PM PDT 24 22247385 ps
T1397 /workspace/coverage/cover_reg_top/11.i2c_intr_test.1995072134 May 07 12:40:33 PM PDT 24 May 07 12:40:35 PM PDT 24 24569879 ps
T1398 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.568582486 May 07 12:40:43 PM PDT 24 May 07 12:40:48 PM PDT 24 156975520 ps
T1399 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3629482135 May 07 12:40:38 PM PDT 24 May 07 12:40:40 PM PDT 24 28501868 ps
T1400 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1812463377 May 07 12:40:35 PM PDT 24 May 07 12:40:38 PM PDT 24 31930038 ps
T1401 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3831507770 May 07 12:40:44 PM PDT 24 May 07 12:40:49 PM PDT 24 171838195 ps
T1402 /workspace/coverage/cover_reg_top/22.i2c_intr_test.2057088571 May 07 12:40:59 PM PDT 24 May 07 12:41:01 PM PDT 24 50711565 ps
T1403 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2017022077 May 07 12:40:29 PM PDT 24 May 07 12:40:30 PM PDT 24 73423356 ps
T1404 /workspace/coverage/cover_reg_top/4.i2c_intr_test.353172534 May 07 12:40:26 PM PDT 24 May 07 12:40:28 PM PDT 24 76247236 ps
T1405 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1538027745 May 07 12:40:33 PM PDT 24 May 07 12:40:35 PM PDT 24 171885355 ps
T1406 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.4096156362 May 07 12:40:15 PM PDT 24 May 07 12:40:19 PM PDT 24 43913597 ps
T1407 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.370929109 May 07 12:40:49 PM PDT 24 May 07 12:40:54 PM PDT 24 448918825 ps
T1408 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1547644353 May 07 12:40:22 PM PDT 24 May 07 12:40:25 PM PDT 24 893082548 ps
T168 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.207691345 May 07 12:40:36 PM PDT 24 May 07 12:40:38 PM PDT 24 18359900 ps
T169 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.105374820 May 07 12:40:45 PM PDT 24 May 07 12:40:49 PM PDT 24 19658734 ps
T1409 /workspace/coverage/cover_reg_top/15.i2c_intr_test.2380871362 May 07 12:40:43 PM PDT 24 May 07 12:40:47 PM PDT 24 26962883 ps
T1410 /workspace/coverage/cover_reg_top/47.i2c_intr_test.760246526 May 07 12:40:42 PM PDT 24 May 07 12:40:46 PM PDT 24 18686410 ps
T1411 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3662421931 May 07 12:40:19 PM PDT 24 May 07 12:40:23 PM PDT 24 40427487 ps
T1412 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2991632026 May 07 12:40:28 PM PDT 24 May 07 12:40:31 PM PDT 24 154427061 ps
T1413 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1529275983 May 07 12:40:33 PM PDT 24 May 07 12:40:36 PM PDT 24 29971739 ps
T1414 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.791507442 May 07 12:40:38 PM PDT 24 May 07 12:40:40 PM PDT 24 50871337 ps
T1415 /workspace/coverage/cover_reg_top/3.i2c_intr_test.2835609328 May 07 12:40:37 PM PDT 24 May 07 12:40:39 PM PDT 24 34157246 ps
T170 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.912356843 May 07 12:40:14 PM PDT 24 May 07 12:40:18 PM PDT 24 62412400 ps
T1416 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1809371886 May 07 12:40:43 PM PDT 24 May 07 12:40:47 PM PDT 24 64293167 ps
T1417 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1627344644 May 07 12:40:38 PM PDT 24 May 07 12:40:40 PM PDT 24 32465510 ps
T1418 /workspace/coverage/cover_reg_top/5.i2c_intr_test.3234599074 May 07 12:40:30 PM PDT 24 May 07 12:40:32 PM PDT 24 27189213 ps
T1419 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1613496828 May 07 12:40:37 PM PDT 24 May 07 12:40:40 PM PDT 24 58640227 ps
T1420 /workspace/coverage/cover_reg_top/2.i2c_intr_test.1450730157 May 07 12:40:24 PM PDT 24 May 07 12:40:26 PM PDT 24 16807280 ps
T1421 /workspace/coverage/cover_reg_top/29.i2c_intr_test.3589572467 May 07 12:40:51 PM PDT 24 May 07 12:40:54 PM PDT 24 53940244 ps
T1422 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2097043769 May 07 12:40:38 PM PDT 24 May 07 12:40:41 PM PDT 24 71358355 ps
T173 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1245502235 May 07 12:40:12 PM PDT 24 May 07 12:40:18 PM PDT 24 273776554 ps
T1423 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1472888730 May 07 12:40:46 PM PDT 24 May 07 12:40:51 PM PDT 24 33491181 ps
T144 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1698558693 May 07 12:40:39 PM PDT 24 May 07 12:40:43 PM PDT 24 86102232 ps
T149 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.701252861 May 07 12:40:43 PM PDT 24 May 07 12:40:47 PM PDT 24 176712992 ps
T1424 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3904763016 May 07 12:40:36 PM PDT 24 May 07 12:40:38 PM PDT 24 46841607 ps
T1425 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3471960895 May 07 12:40:24 PM PDT 24 May 07 12:40:28 PM PDT 24 82388904 ps
T1426 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2471399295 May 07 12:40:39 PM PDT 24 May 07 12:40:41 PM PDT 24 110601361 ps
T154 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3698451208 May 07 12:40:42 PM PDT 24 May 07 12:40:46 PM PDT 24 446370116 ps
T1427 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.629916394 May 07 12:40:41 PM PDT 24 May 07 12:40:43 PM PDT 24 218015231 ps
T1428 /workspace/coverage/cover_reg_top/18.i2c_intr_test.3848557933 May 07 12:40:42 PM PDT 24 May 07 12:40:44 PM PDT 24 21157184 ps
T1429 /workspace/coverage/cover_reg_top/12.i2c_intr_test.4065847193 May 07 12:40:17 PM PDT 24 May 07 12:40:21 PM PDT 24 65248892 ps
T1430 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3263604119 May 07 12:40:50 PM PDT 24 May 07 12:40:55 PM PDT 24 216017067 ps
T171 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3455958518 May 07 12:40:13 PM PDT 24 May 07 12:40:18 PM PDT 24 371013753 ps
T145 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3634854659 May 07 12:40:36 PM PDT 24 May 07 12:40:38 PM PDT 24 126885650 ps
T1431 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1295126665 May 07 12:40:43 PM PDT 24 May 07 12:40:47 PM PDT 24 780100471 ps
T1432 /workspace/coverage/cover_reg_top/46.i2c_intr_test.1566397991 May 07 12:40:40 PM PDT 24 May 07 12:40:42 PM PDT 24 15947299 ps
T1433 /workspace/coverage/cover_reg_top/17.i2c_intr_test.1744855948 May 07 12:40:41 PM PDT 24 May 07 12:40:43 PM PDT 24 14576128 ps
T1434 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3687691019 May 07 12:40:30 PM PDT 24 May 07 12:40:32 PM PDT 24 62768332 ps
T1435 /workspace/coverage/cover_reg_top/39.i2c_intr_test.3426477810 May 07 12:40:32 PM PDT 24 May 07 12:40:34 PM PDT 24 29077414 ps
T1436 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2939185649 May 07 12:40:41 PM PDT 24 May 07 12:40:44 PM PDT 24 19770878 ps
T172 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3199770354 May 07 12:40:36 PM PDT 24 May 07 12:40:38 PM PDT 24 27454774 ps
T1437 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3154507184 May 07 12:40:25 PM PDT 24 May 07 12:40:28 PM PDT 24 393280572 ps
T1438 /workspace/coverage/cover_reg_top/7.i2c_intr_test.3111457542 May 07 12:40:16 PM PDT 24 May 07 12:40:19 PM PDT 24 29951047 ps
T1439 /workspace/coverage/cover_reg_top/31.i2c_intr_test.2413783226 May 07 12:40:48 PM PDT 24 May 07 12:40:51 PM PDT 24 22977495 ps
T1440 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2098892281 May 07 12:40:36 PM PDT 24 May 07 12:40:38 PM PDT 24 65672807 ps
T1441 /workspace/coverage/cover_reg_top/13.i2c_intr_test.2928626107 May 07 12:40:43 PM PDT 24 May 07 12:40:46 PM PDT 24 19847208 ps
T1442 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3247262058 May 07 12:40:40 PM PDT 24 May 07 12:40:43 PM PDT 24 100907305 ps
T1443 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1950192479 May 07 12:40:39 PM PDT 24 May 07 12:40:42 PM PDT 24 57881358 ps
T1444 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.295502224 May 07 12:40:10 PM PDT 24 May 07 12:40:15 PM PDT 24 73271743 ps
T1445 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3277233786 May 07 12:40:46 PM PDT 24 May 07 12:40:50 PM PDT 24 54844444 ps
T1446 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.170533512 May 07 12:40:10 PM PDT 24 May 07 12:40:12 PM PDT 24 24139927 ps
T1447 /workspace/coverage/cover_reg_top/33.i2c_intr_test.675028073 May 07 12:40:45 PM PDT 24 May 07 12:40:50 PM PDT 24 56803300 ps
T151 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3432502678 May 07 12:40:14 PM PDT 24 May 07 12:40:18 PM PDT 24 910520156 ps
T1448 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.336454865 May 07 12:40:31 PM PDT 24 May 07 12:40:34 PM PDT 24 252564272 ps
T1449 /workspace/coverage/cover_reg_top/23.i2c_intr_test.3491532608 May 07 12:40:41 PM PDT 24 May 07 12:40:43 PM PDT 24 17379961 ps
T1450 /workspace/coverage/cover_reg_top/28.i2c_intr_test.79719795 May 07 12:40:42 PM PDT 24 May 07 12:40:45 PM PDT 24 20732746 ps
T1451 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2169816776 May 07 12:40:22 PM PDT 24 May 07 12:40:25 PM PDT 24 190625033 ps
T1452 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.874589750 May 07 12:40:26 PM PDT 24 May 07 12:40:28 PM PDT 24 117470131 ps
T1453 /workspace/coverage/cover_reg_top/19.i2c_intr_test.4135109604 May 07 12:40:31 PM PDT 24 May 07 12:40:32 PM PDT 24 24896042 ps
T1454 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2137398666 May 07 12:40:41 PM PDT 24 May 07 12:40:44 PM PDT 24 39447800 ps
T1455 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2363248934 May 07 12:40:34 PM PDT 24 May 07 12:40:37 PM PDT 24 605184666 ps
T219 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2264119363 May 07 12:40:31 PM PDT 24 May 07 12:40:34 PM PDT 24 155905498 ps
T1456 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2425402813 May 07 12:40:21 PM PDT 24 May 07 12:40:25 PM PDT 24 126178278 ps
T155 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4006998179 May 07 12:40:42 PM PDT 24 May 07 12:40:46 PM PDT 24 75724382 ps
T1457 /workspace/coverage/cover_reg_top/40.i2c_intr_test.2968291184 May 07 12:40:47 PM PDT 24 May 07 12:40:51 PM PDT 24 59825875 ps
T220 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2083483819 May 07 12:40:40 PM PDT 24 May 07 12:40:44 PM PDT 24 333987725 ps
T156 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3457909674 May 07 12:40:45 PM PDT 24 May 07 12:40:50 PM PDT 24 314955406 ps
T1458 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3817716127 May 07 12:40:15 PM PDT 24 May 07 12:40:23 PM PDT 24 5968066891 ps
T1459 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1757075336 May 07 12:40:17 PM PDT 24 May 07 12:40:26 PM PDT 24 760325878 ps
T1460 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.270832739 May 07 12:40:47 PM PDT 24 May 07 12:40:51 PM PDT 24 49907451 ps
T1461 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3537285364 May 07 12:40:34 PM PDT 24 May 07 12:40:36 PM PDT 24 21791006 ps
T1462 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.719661940 May 07 12:40:44 PM PDT 24 May 07 12:40:47 PM PDT 24 54565975 ps
T1463 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2682216877 May 07 12:40:43 PM PDT 24 May 07 12:40:47 PM PDT 24 34982545 ps
T1464 /workspace/coverage/cover_reg_top/6.i2c_intr_test.2120106958 May 07 12:40:36 PM PDT 24 May 07 12:40:38 PM PDT 24 127918988 ps
T1465 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2597252807 May 07 12:40:37 PM PDT 24 May 07 12:40:39 PM PDT 24 75081568 ps
T1466 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3119318237 May 07 12:40:42 PM PDT 24 May 07 12:40:46 PM PDT 24 85179898 ps
T1467 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1314007651 May 07 12:40:25 PM PDT 24 May 07 12:40:34 PM PDT 24 1038520221 ps
T1468 /workspace/coverage/cover_reg_top/36.i2c_intr_test.2185940723 May 07 12:40:38 PM PDT 24 May 07 12:40:40 PM PDT 24 37402978 ps
T1469 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2258415675 May 07 12:40:19 PM PDT 24 May 07 12:40:23 PM PDT 24 15866798 ps
T1470 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2428036317 May 07 12:40:10 PM PDT 24 May 07 12:40:13 PM PDT 24 61441917 ps
T1471 /workspace/coverage/cover_reg_top/8.i2c_intr_test.2549660240 May 07 12:40:32 PM PDT 24 May 07 12:40:34 PM PDT 24 17479675 ps
T1472 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1562926715 May 07 12:40:41 PM PDT 24 May 07 12:40:43 PM PDT 24 120269207 ps

Test location /workspace/coverage/default/21.i2c_host_perf.3985514739
Short name T7
Test name
Test status
Simulation time 12904354482 ps
CPU time 229.53 seconds
Started May 07 12:55:26 PM PDT 24
Finished May 07 12:59:17 PM PDT 24
Peak memory 1470984 kb
Host smart-3ef60ca2-7fcf-4eca-8830-1cbe3d8a74ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985514739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.3985514739
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.1324395948
Short name T8
Test name
Test status
Simulation time 2056072652 ps
CPU time 5.79 seconds
Started May 07 12:56:29 PM PDT 24
Finished May 07 12:56:36 PM PDT 24
Peak memory 218784 kb
Host smart-2cc411eb-af2a-4419-89ab-c1baf64497a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324395948 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.1324395948
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.2428806514
Short name T22
Test name
Test status
Simulation time 3756763756 ps
CPU time 9.9 seconds
Started May 07 12:51:40 PM PDT 24
Finished May 07 12:51:51 PM PDT 24
Peak memory 212312 kb
Host smart-3bc306e0-91d3-4641-8f1c-8d555f44dde4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428806514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2428806514
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.2560652725
Short name T95
Test name
Test status
Simulation time 27798194287 ps
CPU time 634.92 seconds
Started May 07 12:52:44 PM PDT 24
Finished May 07 01:03:20 PM PDT 24
Peak memory 1581312 kb
Host smart-b99902b1-5d16-43aa-8af3-d85b7a0da77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560652725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.2560652725
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.4211296355
Short name T43
Test name
Test status
Simulation time 43088700347 ps
CPU time 2800.99 seconds
Started May 07 12:58:02 PM PDT 24
Finished May 07 01:44:45 PM PDT 24
Peak memory 5363112 kb
Host smart-63010147-795a-4c4c-92ba-0de2b9698b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211296355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.4211296355
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2283469199
Short name T135
Test name
Test status
Simulation time 563477649 ps
CPU time 2.28 seconds
Started May 07 12:40:41 PM PDT 24
Finished May 07 12:40:46 PM PDT 24
Peak memory 203932 kb
Host smart-1a72d2e2-c138-40e7-8a9c-71d91f0265d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283469199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2283469199
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.1520443641
Short name T5
Test name
Test status
Simulation time 1676771050 ps
CPU time 6.57 seconds
Started May 07 12:58:50 PM PDT 24
Finished May 07 12:58:58 PM PDT 24
Peak memory 203892 kb
Host smart-8f745521-df48-4521-84f4-6823534d8af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520443641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.1520443641
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_override.4109175257
Short name T52
Test name
Test status
Simulation time 107096807 ps
CPU time 0.67 seconds
Started May 07 12:53:48 PM PDT 24
Finished May 07 12:53:50 PM PDT 24
Peak memory 203748 kb
Host smart-af4878c1-3014-493f-a66a-d3343f8effb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109175257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.4109175257
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.437985504
Short name T250
Test name
Test status
Simulation time 48481050249 ps
CPU time 1016.47 seconds
Started May 07 12:57:21 PM PDT 24
Finished May 07 01:14:18 PM PDT 24
Peak memory 1553024 kb
Host smart-e259f7c1-967c-4afa-bcf6-9140ebc38ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437985504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.437985504
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.989657690
Short name T73
Test name
Test status
Simulation time 10121642728 ps
CPU time 63.6 seconds
Started May 07 12:58:20 PM PDT 24
Finished May 07 12:59:25 PM PDT 24
Peak memory 428732 kb
Host smart-cfae12d1-f1d7-4fde-84db-8a97e50aea28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989657690 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_fifo_reset_tx.989657690
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3749975345
Short name T34
Test name
Test status
Simulation time 15586908630 ps
CPU time 156.51 seconds
Started May 07 12:52:31 PM PDT 24
Finished May 07 12:55:09 PM PDT 24
Peak memory 2114080 kb
Host smart-4d41ebba-9cbb-4b13-936d-bc525058502c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749975345 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3749975345
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2471596804
Short name T123
Test name
Test status
Simulation time 203826009 ps
CPU time 1.48 seconds
Started May 07 12:40:34 PM PDT 24
Finished May 07 12:40:36 PM PDT 24
Peak memory 203924 kb
Host smart-d5393c24-28cd-49f3-a75c-b4985853cc44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471596804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2471596804
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1092679677
Short name T125
Test name
Test status
Simulation time 65257535 ps
CPU time 0.96 seconds
Started May 07 12:51:54 PM PDT 24
Finished May 07 12:51:56 PM PDT 24
Peak memory 222388 kb
Host smart-5fb6c1cb-3708-46dd-991e-22a82b79e8f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092679677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1092679677
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/29.i2c_target_unexp_stop.992434575
Short name T16
Test name
Test status
Simulation time 4327906399 ps
CPU time 8.26 seconds
Started May 07 12:56:41 PM PDT 24
Finished May 07 12:56:52 PM PDT 24
Peak memory 203984 kb
Host smart-1306f894-7337-4eea-99db-18e49c2f5c14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992434575 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_unexp_stop.992434575
Directory /workspace/29.i2c_target_unexp_stop/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1162242167
Short name T161
Test name
Test status
Simulation time 24652771 ps
CPU time 0.68 seconds
Started May 07 12:40:26 PM PDT 24
Finished May 07 12:40:28 PM PDT 24
Peak memory 203732 kb
Host smart-19caca09-e61a-4001-9456-e0698cda5121
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162242167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.1162242167
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.4022499846
Short name T50
Test name
Test status
Simulation time 143031442 ps
CPU time 1.17 seconds
Started May 07 12:58:56 PM PDT 24
Finished May 07 12:58:58 PM PDT 24
Peak memory 203812 kb
Host smart-eaf49dd5-2dbe-471a-89ca-1bf823e4d895
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022499846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.4022499846
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.1640104502
Short name T38
Test name
Test status
Simulation time 1224642288 ps
CPU time 6.83 seconds
Started May 07 12:53:47 PM PDT 24
Finished May 07 12:53:55 PM PDT 24
Peak memory 212060 kb
Host smart-dcbdc38a-40de-4773-bf29-e4468d3a03a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640104502 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.1640104502
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.3803861718
Short name T96
Test name
Test status
Simulation time 66113456919 ps
CPU time 402.31 seconds
Started May 07 12:55:28 PM PDT 24
Finished May 07 01:02:11 PM PDT 24
Peak memory 2139376 kb
Host smart-0d5d6e5f-c639-44d0-82e7-79038be4f7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803861718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.3803861718
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.4183787645
Short name T294
Test name
Test status
Simulation time 802012858 ps
CPU time 3.71 seconds
Started May 07 12:51:49 PM PDT 24
Finished May 07 12:51:54 PM PDT 24
Peak memory 203968 kb
Host smart-d8de4ab4-930e-4ece-94df-1deb8c4070b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183787645 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.4183787645
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.2707202914
Short name T13
Test name
Test status
Simulation time 430620548 ps
CPU time 2.6 seconds
Started May 07 12:54:20 PM PDT 24
Finished May 07 12:54:23 PM PDT 24
Peak memory 203904 kb
Host smart-11a36c18-2ecf-46c2-9079-145023f970eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707202914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.2707202914
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.3259115295
Short name T221
Test name
Test status
Simulation time 3309554464 ps
CPU time 78.81 seconds
Started May 07 12:56:09 PM PDT 24
Finished May 07 12:57:33 PM PDT 24
Peak memory 296968 kb
Host smart-4759235e-369a-425a-a814-ddd0eed3dea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259115295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.3259115295
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_alert_test.1190120106
Short name T119
Test name
Test status
Simulation time 43296528 ps
CPU time 0.6 seconds
Started May 07 12:52:10 PM PDT 24
Finished May 07 12:52:12 PM PDT 24
Peak memory 203804 kb
Host smart-c5d55dac-760f-4ad0-811f-2ab82ce014ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190120106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.1190120106
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.2663882578
Short name T185
Test name
Test status
Simulation time 168255193829 ps
CPU time 420.97 seconds
Started May 07 12:54:06 PM PDT 24
Finished May 07 01:01:08 PM PDT 24
Peak memory 1593272 kb
Host smart-6fc51b1b-f3fe-457b-954e-66fceb2588eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663882578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.2663882578
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.4158901523
Short name T132
Test name
Test status
Simulation time 134805096 ps
CPU time 3.51 seconds
Started May 07 12:56:09 PM PDT 24
Finished May 07 12:56:18 PM PDT 24
Peak memory 225444 kb
Host smart-937aa153-aa9b-4017-8f58-456596d70cb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158901523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.4158901523
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.2605072185
Short name T65
Test name
Test status
Simulation time 7910592549 ps
CPU time 313.93 seconds
Started May 07 12:56:03 PM PDT 24
Finished May 07 01:01:23 PM PDT 24
Peak memory 1113208 kb
Host smart-acd5e0d6-bbf8-4664-98c0-6222513dee26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605072185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.2605072185
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2721206545
Short name T137
Test name
Test status
Simulation time 1354430613 ps
CPU time 2.28 seconds
Started May 07 12:40:11 PM PDT 24
Finished May 07 12:40:15 PM PDT 24
Peak memory 203936 kb
Host smart-1a2a6ead-2b3f-44f7-a2d9-2fc7e29cf707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721206545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.2721206545
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.3199770354
Short name T172
Test name
Test status
Simulation time 27454774 ps
CPU time 0.81 seconds
Started May 07 12:40:36 PM PDT 24
Finished May 07 12:40:38 PM PDT 24
Peak memory 203804 kb
Host smart-ce4668be-e803-46b5-bfce-bf57c374256a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199770354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.3199770354
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.1202780793
Short name T254
Test name
Test status
Simulation time 59419400633 ps
CPU time 1692.35 seconds
Started May 07 12:57:45 PM PDT 24
Finished May 07 01:25:59 PM PDT 24
Peak memory 1334224 kb
Host smart-83b02d3a-627d-43d9-91e2-302a5120a2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202780793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.1202780793
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.2274418988
Short name T223
Test name
Test status
Simulation time 39114978546 ps
CPU time 3311.8 seconds
Started May 07 12:59:08 PM PDT 24
Finished May 07 01:54:22 PM PDT 24
Peak memory 3058040 kb
Host smart-48d67bc7-b5d4-483b-a560-82644869dd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274418988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.2274418988
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.3253459322
Short name T88
Test name
Test status
Simulation time 8373618597 ps
CPU time 513.96 seconds
Started May 07 12:56:58 PM PDT 24
Finished May 07 01:05:33 PM PDT 24
Peak memory 789644 kb
Host smart-e781f9ef-24cd-4032-9516-29df28cf81ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253459322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.3253459322
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3797694173
Short name T1389
Test name
Test status
Simulation time 123294958 ps
CPU time 1.15 seconds
Started May 07 12:40:59 PM PDT 24
Finished May 07 12:41:02 PM PDT 24
Peak memory 203924 kb
Host smart-a230082c-95d3-497d-859a-a8baf76e383f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797694173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3797694173
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.856486154
Short name T70
Test name
Test status
Simulation time 10147301015 ps
CPU time 13.22 seconds
Started May 07 12:59:18 PM PDT 24
Finished May 07 12:59:33 PM PDT 24
Peak memory 268660 kb
Host smart-9e4734c0-b4a4-454c-b519-67421f902dee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856486154 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_acq.856486154
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.1883496060
Short name T259
Test name
Test status
Simulation time 5549035073 ps
CPU time 6.83 seconds
Started May 07 12:55:38 PM PDT 24
Finished May 07 12:55:47 PM PDT 24
Peak memory 220240 kb
Host smart-e26b6509-346c-4b4c-858f-d0d1c4ae2963
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883496060 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.1883496060
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1868062615
Short name T213
Test name
Test status
Simulation time 10103776873 ps
CPU time 21.72 seconds
Started May 07 12:58:30 PM PDT 24
Finished May 07 12:58:54 PM PDT 24
Peak memory 290512 kb
Host smart-e09fb3ed-4b96-4f09-a434-384b79fcee2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868062615 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1868062615
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.1878190931
Short name T216
Test name
Test status
Simulation time 520216421 ps
CPU time 1.12 seconds
Started May 07 12:58:54 PM PDT 24
Finished May 07 12:58:57 PM PDT 24
Peak memory 203884 kb
Host smart-9c72f865-f44f-466e-8435-ae84fac29549
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878190931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.1878190931
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.1699042488
Short name T66
Test name
Test status
Simulation time 4828273214 ps
CPU time 38.17 seconds
Started May 07 12:59:16 PM PDT 24
Finished May 07 12:59:56 PM PDT 24
Peak memory 502468 kb
Host smart-2370fa4c-334d-4ce5-9793-2f5b75481cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699042488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.1699042488
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.3329583836
Short name T1162
Test name
Test status
Simulation time 8809358298 ps
CPU time 59.82 seconds
Started May 07 12:55:05 PM PDT 24
Finished May 07 12:56:06 PM PDT 24
Peak memory 297144 kb
Host smart-b5dee350-9507-4144-817e-749346a7015e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329583836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.3329583836
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.1949637956
Short name T143
Test name
Test status
Simulation time 311075392 ps
CPU time 2.01 seconds
Started May 07 12:40:41 PM PDT 24
Finished May 07 12:40:45 PM PDT 24
Peak memory 203952 kb
Host smart-5c392f18-7ed4-4c35-9b1e-d69eea124577
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949637956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1949637956
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.605581825
Short name T148
Test name
Test status
Simulation time 549578382 ps
CPU time 2.28 seconds
Started May 07 12:40:20 PM PDT 24
Finished May 07 12:40:26 PM PDT 24
Peak memory 203940 kb
Host smart-d594f16b-3fa2-4be1-85b4-9433fd3ecdca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605581825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.605581825
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.1615786969
Short name T226
Test name
Test status
Simulation time 33269353420 ps
CPU time 753.82 seconds
Started May 07 12:51:47 PM PDT 24
Finished May 07 01:04:22 PM PDT 24
Peak memory 3606260 kb
Host smart-90a9188e-1669-41c1-b5a0-38b42ac8f998
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615786969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.1615786969
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.1941507506
Short name T443
Test name
Test status
Simulation time 10160973094 ps
CPU time 45.43 seconds
Started May 07 12:52:06 PM PDT 24
Finished May 07 12:52:53 PM PDT 24
Peak memory 404376 kb
Host smart-0e66e75f-dfe7-4a1d-86bc-4ca36ea37366
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941507506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.1941507506
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1707928261
Short name T1208
Test name
Test status
Simulation time 5139782694 ps
CPU time 17.55 seconds
Started May 07 12:51:58 PM PDT 24
Finished May 07 12:52:17 PM PDT 24
Peak memory 203932 kb
Host smart-ba627fe0-61f1-4d5d-8d8c-c1186ba0527b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707928261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1707928261
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.776509998
Short name T247
Test name
Test status
Simulation time 2207638622 ps
CPU time 10.28 seconds
Started May 07 12:55:24 PM PDT 24
Finished May 07 12:55:35 PM PDT 24
Peak memory 212240 kb
Host smart-f6850d33-3b6f-488c-ab56-48344306f2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776509998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.776509998
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.3467275805
Short name T240
Test name
Test status
Simulation time 7839499929 ps
CPU time 15.01 seconds
Started May 07 12:55:57 PM PDT 24
Finished May 07 12:56:17 PM PDT 24
Peak memory 218384 kb
Host smart-293fef61-42ad-4e16-bd5b-4c75d7a0763d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467275805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3467275805
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_host_override.3279244242
Short name T451
Test name
Test status
Simulation time 41898997 ps
CPU time 0.65 seconds
Started May 07 12:51:51 PM PDT 24
Finished May 07 12:51:53 PM PDT 24
Peak memory 203708 kb
Host smart-3f4242b8-5594-467b-a0b4-03f99d66cbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279244242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.3279244242
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.2791339372
Short name T46
Test name
Test status
Simulation time 1698196454 ps
CPU time 29.78 seconds
Started May 07 12:52:27 PM PDT 24
Finished May 07 12:52:59 PM PDT 24
Peak memory 375600 kb
Host smart-e48d8218-551d-4b9a-b483-421539998871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791339372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.2791339372
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.404115483
Short name T1370
Test name
Test status
Simulation time 48356368 ps
CPU time 2.01 seconds
Started May 07 12:40:13 PM PDT 24
Finished May 07 12:40:17 PM PDT 24
Peak memory 203912 kb
Host smart-359af428-721e-4a20-aa92-55140720f2b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404115483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.404115483
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3817716127
Short name T1458
Test name
Test status
Simulation time 5968066891 ps
CPU time 5.8 seconds
Started May 07 12:40:15 PM PDT 24
Finished May 07 12:40:23 PM PDT 24
Peak memory 203972 kb
Host smart-7fb43bb9-6aaf-4dc9-aaab-6b5bfb7b8122
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817716127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.3817716127
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2428036317
Short name T1470
Test name
Test status
Simulation time 61441917 ps
CPU time 0.71 seconds
Started May 07 12:40:10 PM PDT 24
Finished May 07 12:40:13 PM PDT 24
Peak memory 203744 kb
Host smart-df7e38df-1e17-4b56-ae50-01210295706f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428036317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2428036317
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1812463377
Short name T1400
Test name
Test status
Simulation time 31930038 ps
CPU time 1.34 seconds
Started May 07 12:40:35 PM PDT 24
Finished May 07 12:40:38 PM PDT 24
Peak memory 204016 kb
Host smart-3bb4b703-cbb2-40a7-b76a-0674abbe6efa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812463377 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1812463377
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3901162384
Short name T1382
Test name
Test status
Simulation time 34502650 ps
CPU time 0.7 seconds
Started May 07 12:40:20 PM PDT 24
Finished May 07 12:40:24 PM PDT 24
Peak memory 203732 kb
Host smart-3c993952-5ac1-43f4-a824-029c655d2836
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901162384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.3901162384
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.1125522311
Short name T195
Test name
Test status
Simulation time 21191596 ps
CPU time 0.68 seconds
Started May 07 12:40:12 PM PDT 24
Finished May 07 12:40:15 PM PDT 24
Peak memory 203668 kb
Host smart-eaff4b17-b85e-40b3-a05e-f392c1fae620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125522311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1125522311
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.4096156362
Short name T1406
Test name
Test status
Simulation time 43913597 ps
CPU time 0.97 seconds
Started May 07 12:40:15 PM PDT 24
Finished May 07 12:40:19 PM PDT 24
Peak memory 203824 kb
Host smart-a376049a-a8e4-45c6-9f6b-4e1a22958afa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096156362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.4096156362
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1342513620
Short name T142
Test name
Test status
Simulation time 101489963 ps
CPU time 1.38 seconds
Started May 07 12:40:15 PM PDT 24
Finished May 07 12:40:19 PM PDT 24
Peak memory 203916 kb
Host smart-d40e70bb-ab15-4bf5-87e5-0157a14911d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342513620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1342513620
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2992644157
Short name T182
Test name
Test status
Simulation time 70163205 ps
CPU time 1.34 seconds
Started May 07 12:40:10 PM PDT 24
Finished May 07 12:40:13 PM PDT 24
Peak memory 203916 kb
Host smart-376f969c-8d40-47a1-b552-63d8c4859ac7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992644157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2992644157
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.295502224
Short name T1444
Test name
Test status
Simulation time 73271743 ps
CPU time 2.8 seconds
Started May 07 12:40:10 PM PDT 24
Finished May 07 12:40:15 PM PDT 24
Peak memory 203872 kb
Host smart-2198ece5-c3cc-4b72-9c5b-29ea5e459f2c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295502224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.295502224
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.30473660
Short name T158
Test name
Test status
Simulation time 101239243 ps
CPU time 0.93 seconds
Started May 07 12:40:26 PM PDT 24
Finished May 07 12:40:28 PM PDT 24
Peak memory 203844 kb
Host smart-5d4cf7f8-f729-4f75-8338-284ce4af806c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30473660 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.30473660
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.1624862678
Short name T1395
Test name
Test status
Simulation time 34458276 ps
CPU time 0.66 seconds
Started May 07 12:40:20 PM PDT 24
Finished May 07 12:40:24 PM PDT 24
Peak memory 203684 kb
Host smart-d6f5eddd-30a0-4ee7-98ef-05ad4d5f520b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624862678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1624862678
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.27765527
Short name T1388
Test name
Test status
Simulation time 112655656 ps
CPU time 0.89 seconds
Started May 07 12:40:18 PM PDT 24
Finished May 07 12:40:22 PM PDT 24
Peak memory 203772 kb
Host smart-575f9064-259e-44d0-8a2c-cfbe2b7d65d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27765527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_outs
tanding.27765527
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2363248934
Short name T1455
Test name
Test status
Simulation time 605184666 ps
CPU time 1.39 seconds
Started May 07 12:40:34 PM PDT 24
Finished May 07 12:40:37 PM PDT 24
Peak memory 203996 kb
Host smart-7fa3411e-afe2-405a-a389-9d20d5558c23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363248934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2363248934
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.73484644
Short name T218
Test name
Test status
Simulation time 84464285 ps
CPU time 1.47 seconds
Started May 07 12:40:29 PM PDT 24
Finished May 07 12:40:31 PM PDT 24
Peak memory 203944 kb
Host smart-bae5a992-d8d2-47f5-8ac6-1a8b504a175d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73484644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.73484644
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2137398666
Short name T1454
Test name
Test status
Simulation time 39447800 ps
CPU time 1.01 seconds
Started May 07 12:40:41 PM PDT 24
Finished May 07 12:40:44 PM PDT 24
Peak memory 203860 kb
Host smart-74f29c86-1e2f-410b-94b3-d11c3b861d2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137398666 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.2137398666
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2017022077
Short name T1403
Test name
Test status
Simulation time 73423356 ps
CPU time 0.66 seconds
Started May 07 12:40:29 PM PDT 24
Finished May 07 12:40:30 PM PDT 24
Peak memory 203768 kb
Host smart-cdea9a92-80dd-468a-993c-92a3546ee0ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017022077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.2017022077
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.1421907254
Short name T1366
Test name
Test status
Simulation time 30561122 ps
CPU time 0.62 seconds
Started May 07 12:40:42 PM PDT 24
Finished May 07 12:40:44 PM PDT 24
Peak memory 203700 kb
Host smart-e93b5587-6b6b-42f0-80fb-e81b630f3810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421907254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1421907254
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1817520184
Short name T1390
Test name
Test status
Simulation time 83917643 ps
CPU time 0.95 seconds
Started May 07 12:40:22 PM PDT 24
Finished May 07 12:40:25 PM PDT 24
Peak memory 203780 kb
Host smart-0c98aa73-d58f-46c7-8cbd-298a9f4854ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817520184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.1817520184
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.568582486
Short name T1398
Test name
Test status
Simulation time 156975520 ps
CPU time 2.66 seconds
Started May 07 12:40:43 PM PDT 24
Finished May 07 12:40:48 PM PDT 24
Peak memory 203876 kb
Host smart-02f03bdf-5479-4525-b6b9-8978d633386d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568582486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.568582486
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1372627937
Short name T134
Test name
Test status
Simulation time 82522064 ps
CPU time 1.52 seconds
Started May 07 12:40:40 PM PDT 24
Finished May 07 12:40:43 PM PDT 24
Peak memory 203916 kb
Host smart-76c56ab7-1a9e-4d2d-81cd-f4f51aed86b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372627937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1372627937
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3662421931
Short name T1411
Test name
Test status
Simulation time 40427487 ps
CPU time 0.81 seconds
Started May 07 12:40:19 PM PDT 24
Finished May 07 12:40:23 PM PDT 24
Peak memory 203820 kb
Host smart-33741b78-5d7d-4f79-b442-4a1a93592288
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662421931 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3662421931
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1044444939
Short name T1383
Test name
Test status
Simulation time 133585323 ps
CPU time 0.69 seconds
Started May 07 12:40:15 PM PDT 24
Finished May 07 12:40:19 PM PDT 24
Peak memory 203736 kb
Host smart-4c63242a-8384-42df-93a0-dc1556f0df30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044444939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1044444939
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.1995072134
Short name T1397
Test name
Test status
Simulation time 24569879 ps
CPU time 0.66 seconds
Started May 07 12:40:33 PM PDT 24
Finished May 07 12:40:35 PM PDT 24
Peak memory 203672 kb
Host smart-1de1ba16-8754-4a77-ae47-2e004a1cfe37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995072134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1995072134
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1562926715
Short name T1472
Test name
Test status
Simulation time 120269207 ps
CPU time 0.92 seconds
Started May 07 12:40:41 PM PDT 24
Finished May 07 12:40:43 PM PDT 24
Peak memory 203780 kb
Host smart-e1200c8c-4dbf-461f-80d0-9fac0c093b86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562926715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.1562926715
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.438955125
Short name T139
Test name
Test status
Simulation time 126949694 ps
CPU time 2.57 seconds
Started May 07 12:40:24 PM PDT 24
Finished May 07 12:40:28 PM PDT 24
Peak memory 203956 kb
Host smart-255774b7-c257-4774-b5ad-d9bd6b9d98da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438955125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.438955125
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.4050407060
Short name T146
Test name
Test status
Simulation time 83081165 ps
CPU time 1.46 seconds
Started May 07 12:40:43 PM PDT 24
Finished May 07 12:40:47 PM PDT 24
Peak memory 203780 kb
Host smart-b0fc324b-facf-4151-9cba-1b0f1f740c9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050407060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.4050407060
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.270832739
Short name T1460
Test name
Test status
Simulation time 49907451 ps
CPU time 0.81 seconds
Started May 07 12:40:47 PM PDT 24
Finished May 07 12:40:51 PM PDT 24
Peak memory 203804 kb
Host smart-ff587555-cd67-4e4b-b3ca-648870f41c7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270832739 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.270832739
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.2939185649
Short name T1436
Test name
Test status
Simulation time 19770878 ps
CPU time 0.72 seconds
Started May 07 12:40:41 PM PDT 24
Finished May 07 12:40:44 PM PDT 24
Peak memory 203768 kb
Host smart-376cfbf5-8d24-41bb-a352-00f54cc8c249
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939185649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.2939185649
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.4065847193
Short name T1429
Test name
Test status
Simulation time 65248892 ps
CPU time 0.67 seconds
Started May 07 12:40:17 PM PDT 24
Finished May 07 12:40:21 PM PDT 24
Peak memory 203596 kb
Host smart-bd2db7ed-ee2b-4df3-92e1-dfb6cf6c4f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065847193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.4065847193
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.629916394
Short name T1427
Test name
Test status
Simulation time 218015231 ps
CPU time 1.09 seconds
Started May 07 12:40:41 PM PDT 24
Finished May 07 12:40:43 PM PDT 24
Peak memory 203904 kb
Host smart-26bc9596-ac08-4bc8-834f-53329642aab6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629916394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_ou
tstanding.629916394
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2160473732
Short name T136
Test name
Test status
Simulation time 79185462 ps
CPU time 1.75 seconds
Started May 07 12:40:15 PM PDT 24
Finished May 07 12:40:20 PM PDT 24
Peak memory 203872 kb
Host smart-9cf1b671-57b6-4a47-80cb-6c6084fd2402
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160473732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2160473732
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.2264119363
Short name T219
Test name
Test status
Simulation time 155905498 ps
CPU time 1.42 seconds
Started May 07 12:40:31 PM PDT 24
Finished May 07 12:40:34 PM PDT 24
Peak memory 203956 kb
Host smart-ca9a4c75-ce32-4015-a8ff-aef9a077aaf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264119363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.2264119363
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2152347245
Short name T141
Test name
Test status
Simulation time 101270284 ps
CPU time 0.92 seconds
Started May 07 12:40:42 PM PDT 24
Finished May 07 12:40:46 PM PDT 24
Peak memory 203704 kb
Host smart-6a0dabea-ec40-4de2-b03e-7e4898b5a5e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152347245 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2152347245
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1434106623
Short name T164
Test name
Test status
Simulation time 57806994 ps
CPU time 0.72 seconds
Started May 07 12:40:47 PM PDT 24
Finished May 07 12:40:51 PM PDT 24
Peak memory 203696 kb
Host smart-44309d5d-945a-4475-a6ce-886955e5721f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434106623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1434106623
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.2928626107
Short name T1441
Test name
Test status
Simulation time 19847208 ps
CPU time 0.66 seconds
Started May 07 12:40:43 PM PDT 24
Finished May 07 12:40:46 PM PDT 24
Peak memory 203680 kb
Host smart-51263780-2daa-4d3a-96bc-ea18bb0f867c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928626107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2928626107
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2471399295
Short name T1426
Test name
Test status
Simulation time 110601361 ps
CPU time 0.89 seconds
Started May 07 12:40:39 PM PDT 24
Finished May 07 12:40:41 PM PDT 24
Peak memory 203636 kb
Host smart-94b7c1f2-a967-4c67-bad8-81a7200cc373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471399295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.2471399295
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1860537065
Short name T153
Test name
Test status
Simulation time 81584797 ps
CPU time 1.11 seconds
Started May 07 12:40:37 PM PDT 24
Finished May 07 12:40:39 PM PDT 24
Peak memory 203832 kb
Host smart-3442e436-229a-45cf-bb95-77e4c21bea83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860537065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1860537065
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1125260583
Short name T150
Test name
Test status
Simulation time 52883469 ps
CPU time 1.4 seconds
Started May 07 12:40:22 PM PDT 24
Finished May 07 12:40:26 PM PDT 24
Peak memory 203948 kb
Host smart-80fb240f-c73b-43cd-89fe-5ab953222a69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125260583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.1125260583
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3061873224
Short name T138
Test name
Test status
Simulation time 24770545 ps
CPU time 0.98 seconds
Started May 07 12:40:21 PM PDT 24
Finished May 07 12:40:25 PM PDT 24
Peak memory 203832 kb
Host smart-f4ba8b6e-8466-403f-95c1-dee17017e5ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061873224 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3061873224
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1978658196
Short name T163
Test name
Test status
Simulation time 27811942 ps
CPU time 0.77 seconds
Started May 07 12:40:30 PM PDT 24
Finished May 07 12:40:32 PM PDT 24
Peak memory 203748 kb
Host smart-0c1b8323-2b1e-4edb-8112-b3982e275f54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978658196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1978658196
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3629482135
Short name T1399
Test name
Test status
Simulation time 28501868 ps
CPU time 0.65 seconds
Started May 07 12:40:38 PM PDT 24
Finished May 07 12:40:40 PM PDT 24
Peak memory 203696 kb
Host smart-20d66b38-7adc-4deb-80ac-cc74d815cb7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629482135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3629482135
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1627344644
Short name T1417
Test name
Test status
Simulation time 32465510 ps
CPU time 0.91 seconds
Started May 07 12:40:38 PM PDT 24
Finished May 07 12:40:40 PM PDT 24
Peak memory 203748 kb
Host smart-6d0818c8-a8c6-4676-a41d-7d23503ff393
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627344644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.1627344644
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3247262058
Short name T1442
Test name
Test status
Simulation time 100907305 ps
CPU time 1.49 seconds
Started May 07 12:40:40 PM PDT 24
Finished May 07 12:40:43 PM PDT 24
Peak memory 204004 kb
Host smart-deebd395-c64e-4ea1-a379-3513da681294
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247262058 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3247262058
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2798546736
Short name T162
Test name
Test status
Simulation time 93244575 ps
CPU time 0.79 seconds
Started May 07 12:40:48 PM PDT 24
Finished May 07 12:40:52 PM PDT 24
Peak memory 203768 kb
Host smart-85f8e868-b533-41b6-a322-0148e18ae66d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798546736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2798546736
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.2380871362
Short name T1409
Test name
Test status
Simulation time 26962883 ps
CPU time 0.68 seconds
Started May 07 12:40:43 PM PDT 24
Finished May 07 12:40:47 PM PDT 24
Peak memory 203752 kb
Host smart-e5b8fb7e-32af-4197-8a94-7b450e9681bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380871362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.2380871362
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.214774655
Short name T180
Test name
Test status
Simulation time 34485571 ps
CPU time 0.86 seconds
Started May 07 12:40:48 PM PDT 24
Finished May 07 12:40:52 PM PDT 24
Peak memory 203780 kb
Host smart-75a74110-6db9-4fef-81c4-847c8128e3ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214774655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_ou
tstanding.214774655
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1613496828
Short name T1419
Test name
Test status
Simulation time 58640227 ps
CPU time 1.49 seconds
Started May 07 12:40:37 PM PDT 24
Finished May 07 12:40:40 PM PDT 24
Peak memory 203972 kb
Host smart-8b00dc9c-e9d4-4606-b5ea-e998ec42156d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613496828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.1613496828
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2083483819
Short name T220
Test name
Test status
Simulation time 333987725 ps
CPU time 2.14 seconds
Started May 07 12:40:40 PM PDT 24
Finished May 07 12:40:44 PM PDT 24
Peak memory 203952 kb
Host smart-a9c41dae-158c-444a-9db3-260c16726b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083483819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2083483819
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.711703517
Short name T159
Test name
Test status
Simulation time 58745789 ps
CPU time 0.8 seconds
Started May 07 12:40:36 PM PDT 24
Finished May 07 12:40:38 PM PDT 24
Peak memory 203856 kb
Host smart-ee1e10dc-39ed-4100-8811-5e1023daac8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711703517 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.711703517
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1947860387
Short name T179
Test name
Test status
Simulation time 30014658 ps
CPU time 0.76 seconds
Started May 07 12:40:43 PM PDT 24
Finished May 07 12:40:46 PM PDT 24
Peak memory 203776 kb
Host smart-e123fce1-115b-45c2-814a-d3f9707470a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947860387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1947860387
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.916029009
Short name T1386
Test name
Test status
Simulation time 18538416 ps
CPU time 0.64 seconds
Started May 07 12:40:44 PM PDT 24
Finished May 07 12:40:48 PM PDT 24
Peak memory 203696 kb
Host smart-0ccf3c37-5922-4c3a-be52-6358b9bfb8df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916029009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.916029009
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.854921796
Short name T1396
Test name
Test status
Simulation time 22247385 ps
CPU time 0.86 seconds
Started May 07 12:40:42 PM PDT 24
Finished May 07 12:40:46 PM PDT 24
Peak memory 203764 kb
Host smart-5b8174e1-21c5-4679-bb45-4a407ffec18a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854921796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_ou
tstanding.854921796
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.3831507770
Short name T1401
Test name
Test status
Simulation time 171838195 ps
CPU time 2.2 seconds
Started May 07 12:40:44 PM PDT 24
Finished May 07 12:40:49 PM PDT 24
Peak memory 204024 kb
Host smart-25cc1daa-2c07-45dd-b822-5f7e6708c682
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831507770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.3831507770
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3456333535
Short name T92
Test name
Test status
Simulation time 23296496 ps
CPU time 0.76 seconds
Started May 07 12:40:40 PM PDT 24
Finished May 07 12:40:42 PM PDT 24
Peak memory 203860 kb
Host smart-4d7e4fa2-585d-4311-821e-552bf77cc780
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456333535 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3456333535
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3347019076
Short name T166
Test name
Test status
Simulation time 21713299 ps
CPU time 0.71 seconds
Started May 07 12:40:47 PM PDT 24
Finished May 07 12:40:51 PM PDT 24
Peak memory 203784 kb
Host smart-a1b8b71e-7765-4fd0-97e3-623b141b3878
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347019076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3347019076
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.1744855948
Short name T1433
Test name
Test status
Simulation time 14576128 ps
CPU time 0.7 seconds
Started May 07 12:40:41 PM PDT 24
Finished May 07 12:40:43 PM PDT 24
Peak memory 203668 kb
Host smart-21e071a4-59d1-4dc8-86b2-d1a7a7cec17b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744855948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1744855948
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1809371886
Short name T1416
Test name
Test status
Simulation time 64293167 ps
CPU time 0.79 seconds
Started May 07 12:40:43 PM PDT 24
Finished May 07 12:40:47 PM PDT 24
Peak memory 203756 kb
Host smart-52105af2-2835-4552-b2e6-844ac89db2df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809371886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.1809371886
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.3698451208
Short name T154
Test name
Test status
Simulation time 446370116 ps
CPU time 2.25 seconds
Started May 07 12:40:42 PM PDT 24
Finished May 07 12:40:46 PM PDT 24
Peak memory 203924 kb
Host smart-70c5cfec-16ea-4c34-8053-f2ce14a938de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698451208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3698451208
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3008679237
Short name T140
Test name
Test status
Simulation time 32536655 ps
CPU time 1.44 seconds
Started May 07 12:40:48 PM PDT 24
Finished May 07 12:40:57 PM PDT 24
Peak memory 213272 kb
Host smart-599d2174-f619-4d7d-ae41-a27eabfa8dc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008679237 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3008679237
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3119318237
Short name T1466
Test name
Test status
Simulation time 85179898 ps
CPU time 0.71 seconds
Started May 07 12:40:42 PM PDT 24
Finished May 07 12:40:46 PM PDT 24
Peak memory 203852 kb
Host smart-565d14fb-d49b-454e-bed8-ed0ca2b557c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119318237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3119318237
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.3848557933
Short name T1428
Test name
Test status
Simulation time 21157184 ps
CPU time 0.67 seconds
Started May 07 12:40:42 PM PDT 24
Finished May 07 12:40:44 PM PDT 24
Peak memory 203704 kb
Host smart-bb6bc442-0244-40f6-bf19-2caf09be5801
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848557933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3848557933
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2773508150
Short name T174
Test name
Test status
Simulation time 76547255 ps
CPU time 0.9 seconds
Started May 07 12:40:37 PM PDT 24
Finished May 07 12:40:40 PM PDT 24
Peak memory 203760 kb
Host smart-4b255fda-b5ba-4b60-9483-765c7b1ad74c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773508150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2773508150
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3697052857
Short name T147
Test name
Test status
Simulation time 84404533 ps
CPU time 1.66 seconds
Started May 07 12:40:40 PM PDT 24
Finished May 07 12:40:44 PM PDT 24
Peak memory 203952 kb
Host smart-156302e4-afbf-44d6-8697-6aa1f7f4278f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697052857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3697052857
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.3457909674
Short name T156
Test name
Test status
Simulation time 314955406 ps
CPU time 2.35 seconds
Started May 07 12:40:45 PM PDT 24
Finished May 07 12:40:50 PM PDT 24
Peak memory 203876 kb
Host smart-af1c48ac-d4a5-4319-b2fc-9a17ae5dc562
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457909674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.3457909674
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3277233786
Short name T1445
Test name
Test status
Simulation time 54844444 ps
CPU time 1.48 seconds
Started May 07 12:40:46 PM PDT 24
Finished May 07 12:40:50 PM PDT 24
Peak memory 203920 kb
Host smart-fbe399a1-d0f4-4003-b582-9e9898098cd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277233786 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3277233786
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.719661940
Short name T1462
Test name
Test status
Simulation time 54565975 ps
CPU time 0.73 seconds
Started May 07 12:40:44 PM PDT 24
Finished May 07 12:40:47 PM PDT 24
Peak memory 203664 kb
Host smart-8b5a90ad-4be6-4f19-ba54-4052b9629415
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719661940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.719661940
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.4135109604
Short name T1453
Test name
Test status
Simulation time 24896042 ps
CPU time 0.67 seconds
Started May 07 12:40:31 PM PDT 24
Finished May 07 12:40:32 PM PDT 24
Peak memory 203664 kb
Host smart-83b16704-ac4d-4f5c-a14c-bdb302aa9af7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135109604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.4135109604
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2682216877
Short name T1463
Test name
Test status
Simulation time 34982545 ps
CPU time 0.86 seconds
Started May 07 12:40:43 PM PDT 24
Finished May 07 12:40:47 PM PDT 24
Peak memory 203752 kb
Host smart-5713cfb1-dd88-48f7-9e4f-e4fca842ed4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682216877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.2682216877
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.370929109
Short name T1407
Test name
Test status
Simulation time 448918825 ps
CPU time 1.34 seconds
Started May 07 12:40:49 PM PDT 24
Finished May 07 12:40:54 PM PDT 24
Peak memory 203936 kb
Host smart-64f84d18-94c6-4c7a-9e57-6b74410ad61c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370929109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.370929109
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.701252861
Short name T149
Test name
Test status
Simulation time 176712992 ps
CPU time 1.38 seconds
Started May 07 12:40:43 PM PDT 24
Finished May 07 12:40:47 PM PDT 24
Peak memory 203932 kb
Host smart-45297d8b-0cf6-40a0-8845-e6ef4284bf3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701252861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.701252861
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3455958518
Short name T171
Test name
Test status
Simulation time 371013753 ps
CPU time 1.97 seconds
Started May 07 12:40:13 PM PDT 24
Finished May 07 12:40:18 PM PDT 24
Peak memory 203880 kb
Host smart-b435d928-3781-4323-86cc-ca4c41257cf8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455958518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3455958518
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1245502235
Short name T173
Test name
Test status
Simulation time 273776554 ps
CPU time 3.35 seconds
Started May 07 12:40:12 PM PDT 24
Finished May 07 12:40:18 PM PDT 24
Peak memory 203904 kb
Host smart-c6fa144d-9e5f-46a6-8d56-0d83d76c5a6e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245502235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.1245502235
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.1577958642
Short name T1373
Test name
Test status
Simulation time 38950386 ps
CPU time 0.76 seconds
Started May 07 12:40:12 PM PDT 24
Finished May 07 12:40:15 PM PDT 24
Peak memory 203744 kb
Host smart-38c7f2be-471b-4d60-85b4-6224ed51b5ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577958642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.1577958642
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2597252807
Short name T1465
Test name
Test status
Simulation time 75081568 ps
CPU time 0.84 seconds
Started May 07 12:40:37 PM PDT 24
Finished May 07 12:40:39 PM PDT 24
Peak memory 203812 kb
Host smart-0ffecf64-7a86-41e6-b7fe-f1d0ecfbf78c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597252807 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.2597252807
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.170533512
Short name T1446
Test name
Test status
Simulation time 24139927 ps
CPU time 0.77 seconds
Started May 07 12:40:10 PM PDT 24
Finished May 07 12:40:12 PM PDT 24
Peak memory 203772 kb
Host smart-69aaa624-9aab-46c9-bc8f-f6840b4c3c8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170533512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.170533512
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.1450730157
Short name T1420
Test name
Test status
Simulation time 16807280 ps
CPU time 0.67 seconds
Started May 07 12:40:24 PM PDT 24
Finished May 07 12:40:26 PM PDT 24
Peak memory 203684 kb
Host smart-29c8347d-ca32-4bdc-b820-b4c1600fc38e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450730157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.1450730157
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2915968159
Short name T178
Test name
Test status
Simulation time 143823375 ps
CPU time 0.81 seconds
Started May 07 12:40:13 PM PDT 24
Finished May 07 12:40:17 PM PDT 24
Peak memory 203716 kb
Host smart-0c0779b3-ecca-4d2e-b47e-de7f54b35762
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915968159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.2915968159
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1547644353
Short name T1408
Test name
Test status
Simulation time 893082548 ps
CPU time 1.29 seconds
Started May 07 12:40:22 PM PDT 24
Finished May 07 12:40:25 PM PDT 24
Peak memory 203964 kb
Host smart-dc8a614e-fab7-48e1-816f-cdacd46e170c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547644353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1547644353
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.3432502678
Short name T151
Test name
Test status
Simulation time 910520156 ps
CPU time 1.47 seconds
Started May 07 12:40:14 PM PDT 24
Finished May 07 12:40:18 PM PDT 24
Peak memory 203876 kb
Host smart-f1da9d2e-ec8a-44f3-9b2a-d01fd4ef76a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432502678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3432502678
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.2313920287
Short name T1394
Test name
Test status
Simulation time 16857506 ps
CPU time 0.64 seconds
Started May 07 12:40:40 PM PDT 24
Finished May 07 12:40:42 PM PDT 24
Peak memory 203704 kb
Host smart-dbf5a6e6-fcc3-4389-99f4-4284d5cd67d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313920287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2313920287
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.1238037335
Short name T1392
Test name
Test status
Simulation time 22378657 ps
CPU time 0.69 seconds
Started May 07 12:40:42 PM PDT 24
Finished May 07 12:40:45 PM PDT 24
Peak memory 203732 kb
Host smart-bb6cf46f-5a2d-424e-b276-aec2e5e0f9ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238037335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1238037335
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.2057088571
Short name T1402
Test name
Test status
Simulation time 50711565 ps
CPU time 0.69 seconds
Started May 07 12:40:59 PM PDT 24
Finished May 07 12:41:01 PM PDT 24
Peak memory 203900 kb
Host smart-51095200-39ed-4b37-bba0-f85e49771597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057088571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.2057088571
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.3491532608
Short name T1449
Test name
Test status
Simulation time 17379961 ps
CPU time 0.68 seconds
Started May 07 12:40:41 PM PDT 24
Finished May 07 12:40:43 PM PDT 24
Peak memory 202928 kb
Host smart-0e0f9020-63d1-4a49-896a-788e6c44473a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491532608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3491532608
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.4183566284
Short name T255
Test name
Test status
Simulation time 67009524 ps
CPU time 0.7 seconds
Started May 07 12:40:37 PM PDT 24
Finished May 07 12:40:39 PM PDT 24
Peak memory 203692 kb
Host smart-35e7849a-56cc-4efd-bfb0-35566a7ff461
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183566284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.4183566284
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.932403462
Short name T1376
Test name
Test status
Simulation time 18115140 ps
CPU time 0.67 seconds
Started May 07 12:40:42 PM PDT 24
Finished May 07 12:40:44 PM PDT 24
Peak memory 203704 kb
Host smart-ce4836d7-070b-4e44-9aaa-36965f7b4065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932403462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.932403462
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.1722919524
Short name T1391
Test name
Test status
Simulation time 18461174 ps
CPU time 0.7 seconds
Started May 07 12:40:43 PM PDT 24
Finished May 07 12:40:46 PM PDT 24
Peak memory 203672 kb
Host smart-a3bec817-e3af-4652-aadb-5a12c358e3bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722919524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1722919524
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.3827988238
Short name T1378
Test name
Test status
Simulation time 20500786 ps
CPU time 0.67 seconds
Started May 07 12:40:39 PM PDT 24
Finished May 07 12:40:40 PM PDT 24
Peak memory 203708 kb
Host smart-2bf9c487-7c46-4738-a29c-53d71706ac46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827988238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.3827988238
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.79719795
Short name T1450
Test name
Test status
Simulation time 20732746 ps
CPU time 0.68 seconds
Started May 07 12:40:42 PM PDT 24
Finished May 07 12:40:45 PM PDT 24
Peak memory 203676 kb
Host smart-8c0716c0-4358-4018-8ed5-95062f71eaed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79719795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.79719795
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.3589572467
Short name T1421
Test name
Test status
Simulation time 53940244 ps
CPU time 0.66 seconds
Started May 07 12:40:51 PM PDT 24
Finished May 07 12:40:54 PM PDT 24
Peak memory 203900 kb
Host smart-f4013abe-4cd2-4bc0-ae61-3ecd3cd2cf57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589572467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3589572467
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1201025272
Short name T165
Test name
Test status
Simulation time 1291085482 ps
CPU time 2.05 seconds
Started May 07 12:40:19 PM PDT 24
Finished May 07 12:40:25 PM PDT 24
Peak memory 203900 kb
Host smart-9a04a739-93a0-4cab-82a5-79494dfd762f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201025272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1201025272
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3733722382
Short name T93
Test name
Test status
Simulation time 421752107 ps
CPU time 5.56 seconds
Started May 07 12:40:32 PM PDT 24
Finished May 07 12:40:39 PM PDT 24
Peak memory 203848 kb
Host smart-0af8a68f-42d5-4fbe-be4d-a99e304c2fde
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733722382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3733722382
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.912356843
Short name T170
Test name
Test status
Simulation time 62412400 ps
CPU time 0.76 seconds
Started May 07 12:40:14 PM PDT 24
Finished May 07 12:40:18 PM PDT 24
Peak memory 203744 kb
Host smart-a371d70a-a74f-4b6f-886e-21d9395a61c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912356843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.912356843
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3687691019
Short name T1434
Test name
Test status
Simulation time 62768332 ps
CPU time 0.95 seconds
Started May 07 12:40:30 PM PDT 24
Finished May 07 12:40:32 PM PDT 24
Peak memory 203868 kb
Host smart-30051b6f-940a-47fb-aa89-38323bec8e73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687691019 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3687691019
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3067497685
Short name T167
Test name
Test status
Simulation time 27177532 ps
CPU time 0.77 seconds
Started May 07 12:40:34 PM PDT 24
Finished May 07 12:40:35 PM PDT 24
Peak memory 203736 kb
Host smart-23e0c7f1-32e9-4adc-a87c-164c3fb8323d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067497685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3067497685
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.2835609328
Short name T1415
Test name
Test status
Simulation time 34157246 ps
CPU time 0.65 seconds
Started May 07 12:40:37 PM PDT 24
Finished May 07 12:40:39 PM PDT 24
Peak memory 203656 kb
Host smart-00a4d7c9-ed96-4b90-89c7-6198e645e06b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835609328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.2835609328
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1529275983
Short name T1413
Test name
Test status
Simulation time 29971739 ps
CPU time 1.09 seconds
Started May 07 12:40:33 PM PDT 24
Finished May 07 12:40:36 PM PDT 24
Peak memory 203900 kb
Host smart-5d713f02-a993-469b-bbff-1e35601df0bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529275983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.1529275983
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2991632026
Short name T1412
Test name
Test status
Simulation time 154427061 ps
CPU time 2.28 seconds
Started May 07 12:40:28 PM PDT 24
Finished May 07 12:40:31 PM PDT 24
Peak memory 204000 kb
Host smart-15f963b4-899c-40eb-ae5b-098d04c5c588
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991632026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2991632026
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3471960895
Short name T1425
Test name
Test status
Simulation time 82388904 ps
CPU time 1.41 seconds
Started May 07 12:40:24 PM PDT 24
Finished May 07 12:40:28 PM PDT 24
Peak memory 203884 kb
Host smart-0c08f505-cdfd-4723-b224-25db1c8e88db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471960895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3471960895
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.609537998
Short name T1377
Test name
Test status
Simulation time 41815154 ps
CPU time 0.68 seconds
Started May 07 12:40:39 PM PDT 24
Finished May 07 12:40:41 PM PDT 24
Peak memory 203712 kb
Host smart-ca44e10a-a903-48b6-86b3-867413057d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609537998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.609537998
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2413783226
Short name T1439
Test name
Test status
Simulation time 22977495 ps
CPU time 0.64 seconds
Started May 07 12:40:48 PM PDT 24
Finished May 07 12:40:51 PM PDT 24
Peak memory 203676 kb
Host smart-9004fed2-f4f7-439c-843c-b242a9780854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413783226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2413783226
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.2968434693
Short name T1375
Test name
Test status
Simulation time 17110714 ps
CPU time 0.66 seconds
Started May 07 12:40:43 PM PDT 24
Finished May 07 12:40:46 PM PDT 24
Peak memory 203704 kb
Host smart-e81189fa-97fc-40ca-b1e1-99c2edf33923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968434693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2968434693
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.675028073
Short name T1447
Test name
Test status
Simulation time 56803300 ps
CPU time 0.69 seconds
Started May 07 12:40:45 PM PDT 24
Finished May 07 12:40:50 PM PDT 24
Peak memory 203700 kb
Host smart-75cb6bb4-85f1-4692-90a5-7176d5df8e45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675028073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.675028073
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.1314534574
Short name T194
Test name
Test status
Simulation time 38922578 ps
CPU time 0.66 seconds
Started May 07 12:40:44 PM PDT 24
Finished May 07 12:40:47 PM PDT 24
Peak memory 203704 kb
Host smart-a323b1c1-0ac2-4156-a6a3-b4bfd36a35cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314534574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1314534574
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.1304775395
Short name T1380
Test name
Test status
Simulation time 57530514 ps
CPU time 0.68 seconds
Started May 07 12:40:54 PM PDT 24
Finished May 07 12:40:57 PM PDT 24
Peak memory 203684 kb
Host smart-34e2c1da-8b5e-4ab6-ae35-35cbc670bbed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304775395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1304775395
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.2185940723
Short name T1468
Test name
Test status
Simulation time 37402978 ps
CPU time 0.63 seconds
Started May 07 12:40:38 PM PDT 24
Finished May 07 12:40:40 PM PDT 24
Peak memory 203708 kb
Host smart-264cab1e-cb3f-4e51-a8df-31986fed039c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185940723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.2185940723
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.1962539017
Short name T1367
Test name
Test status
Simulation time 42066753 ps
CPU time 0.7 seconds
Started May 07 12:40:41 PM PDT 24
Finished May 07 12:40:44 PM PDT 24
Peak memory 203696 kb
Host smart-47eea04d-defe-4894-92cb-dda12745b3e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962539017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1962539017
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.1906890304
Short name T1369
Test name
Test status
Simulation time 45515352 ps
CPU time 0.64 seconds
Started May 07 12:40:46 PM PDT 24
Finished May 07 12:40:50 PM PDT 24
Peak memory 203124 kb
Host smart-aedfced5-a6a7-41aa-8c4e-8879048151f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906890304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1906890304
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.3426477810
Short name T1435
Test name
Test status
Simulation time 29077414 ps
CPU time 0.71 seconds
Started May 07 12:40:32 PM PDT 24
Finished May 07 12:40:34 PM PDT 24
Peak memory 203552 kb
Host smart-e8878b34-69b3-4fd4-89f3-3de5e166a072
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426477810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3426477810
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1314007651
Short name T1467
Test name
Test status
Simulation time 1038520221 ps
CPU time 2.03 seconds
Started May 07 12:40:25 PM PDT 24
Finished May 07 12:40:34 PM PDT 24
Peak memory 203876 kb
Host smart-6c98a9e0-9f3d-414d-a822-10492798ddb2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314007651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1314007651
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1757075336
Short name T1459
Test name
Test status
Simulation time 760325878 ps
CPU time 5.08 seconds
Started May 07 12:40:17 PM PDT 24
Finished May 07 12:40:26 PM PDT 24
Peak memory 203916 kb
Host smart-a8baf6ca-353f-468c-8e8a-41cf73e8e2fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757075336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1757075336
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.105374820
Short name T169
Test name
Test status
Simulation time 19658734 ps
CPU time 0.64 seconds
Started May 07 12:40:45 PM PDT 24
Finished May 07 12:40:49 PM PDT 24
Peak memory 203692 kb
Host smart-b4613910-9290-456a-bc79-56036e12cb78
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105374820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.105374820
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2098892281
Short name T1440
Test name
Test status
Simulation time 65672807 ps
CPU time 0.82 seconds
Started May 07 12:40:36 PM PDT 24
Finished May 07 12:40:38 PM PDT 24
Peak memory 203804 kb
Host smart-e1091614-9bcb-416d-b06d-93963a0e2f1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098892281 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.2098892281
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2258415675
Short name T1469
Test name
Test status
Simulation time 15866798 ps
CPU time 0.7 seconds
Started May 07 12:40:19 PM PDT 24
Finished May 07 12:40:23 PM PDT 24
Peak memory 203748 kb
Host smart-7aac02a9-d88f-424f-99dd-9b0c46d5e935
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258415675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2258415675
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.353172534
Short name T1404
Test name
Test status
Simulation time 76247236 ps
CPU time 0.65 seconds
Started May 07 12:40:26 PM PDT 24
Finished May 07 12:40:28 PM PDT 24
Peak memory 203688 kb
Host smart-fd1dacb8-1c3a-401b-9a18-4185c6a68dc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353172534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.353172534
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1538027745
Short name T1405
Test name
Test status
Simulation time 171885355 ps
CPU time 1.18 seconds
Started May 07 12:40:33 PM PDT 24
Finished May 07 12:40:35 PM PDT 24
Peak memory 203824 kb
Host smart-fc40a940-55f7-4d0f-a0a9-cb693bf856d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538027745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.1538027745
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1472888730
Short name T1423
Test name
Test status
Simulation time 33491181 ps
CPU time 1.67 seconds
Started May 07 12:40:46 PM PDT 24
Finished May 07 12:40:51 PM PDT 24
Peak memory 203968 kb
Host smart-2c8c788f-6f01-43c8-a0f8-d4b7591a64e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472888730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.1472888730
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1552778685
Short name T1393
Test name
Test status
Simulation time 288250899 ps
CPU time 2.32 seconds
Started May 07 12:40:33 PM PDT 24
Finished May 07 12:40:36 PM PDT 24
Peak memory 203896 kb
Host smart-b60b9d58-490b-414b-a4ca-e438e2c9db62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552778685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.1552778685
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.2968291184
Short name T1457
Test name
Test status
Simulation time 59825875 ps
CPU time 0.65 seconds
Started May 07 12:40:47 PM PDT 24
Finished May 07 12:40:51 PM PDT 24
Peak memory 203712 kb
Host smart-7a413fe2-7aae-453d-a8b7-d496c57a356d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968291184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2968291184
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.3791682767
Short name T1387
Test name
Test status
Simulation time 24829318 ps
CPU time 0.67 seconds
Started May 07 12:40:40 PM PDT 24
Finished May 07 12:40:42 PM PDT 24
Peak memory 203720 kb
Host smart-9f722b37-6dfa-4808-b711-d0a5598b65f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791682767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3791682767
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.2251194487
Short name T1372
Test name
Test status
Simulation time 20348810 ps
CPU time 0.68 seconds
Started May 07 12:40:43 PM PDT 24
Finished May 07 12:40:46 PM PDT 24
Peak memory 203672 kb
Host smart-4c348f75-df16-4b4e-add9-9462618210dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251194487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2251194487
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.1110767629
Short name T1371
Test name
Test status
Simulation time 19927489 ps
CPU time 0.67 seconds
Started May 07 12:40:41 PM PDT 24
Finished May 07 12:40:44 PM PDT 24
Peak memory 203668 kb
Host smart-4f9a5284-98c5-4860-896d-d42f295197d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110767629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1110767629
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.2002937487
Short name T1374
Test name
Test status
Simulation time 25796638 ps
CPU time 0.67 seconds
Started May 07 12:40:55 PM PDT 24
Finished May 07 12:40:57 PM PDT 24
Peak memory 203704 kb
Host smart-20aa3c36-336c-44c3-a674-d249eae9302b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002937487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2002937487
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.252447607
Short name T1379
Test name
Test status
Simulation time 31073238 ps
CPU time 0.76 seconds
Started May 07 12:40:47 PM PDT 24
Finished May 07 12:40:51 PM PDT 24
Peak memory 203716 kb
Host smart-57848d14-a36b-4659-9d83-45771699fecf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252447607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.252447607
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.1566397991
Short name T1432
Test name
Test status
Simulation time 15947299 ps
CPU time 0.63 seconds
Started May 07 12:40:40 PM PDT 24
Finished May 07 12:40:42 PM PDT 24
Peak memory 203684 kb
Host smart-02b85a20-5aab-4340-b20e-233325711480
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566397991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1566397991
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.760246526
Short name T1410
Test name
Test status
Simulation time 18686410 ps
CPU time 0.66 seconds
Started May 07 12:40:42 PM PDT 24
Finished May 07 12:40:46 PM PDT 24
Peak memory 203676 kb
Host smart-93cbf097-1617-4392-9332-ffa6e6be32c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760246526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.760246526
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.3578147050
Short name T1381
Test name
Test status
Simulation time 41970591 ps
CPU time 0.66 seconds
Started May 07 12:40:44 PM PDT 24
Finished May 07 12:40:48 PM PDT 24
Peak memory 203720 kb
Host smart-5f79e8a4-dbd9-42ad-a9a9-72e5a9746a7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578147050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3578147050
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.3917639215
Short name T1368
Test name
Test status
Simulation time 192116039 ps
CPU time 0.7 seconds
Started May 07 12:40:53 PM PDT 24
Finished May 07 12:40:55 PM PDT 24
Peak memory 203716 kb
Host smart-df2c4543-ee97-42ec-89a5-ffd991b9731b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917639215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.3917639215
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2169816776
Short name T1451
Test name
Test status
Simulation time 190625033 ps
CPU time 1.24 seconds
Started May 07 12:40:22 PM PDT 24
Finished May 07 12:40:25 PM PDT 24
Peak memory 212252 kb
Host smart-90be3706-34aa-46bf-b957-7c83048e0dde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169816776 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2169816776
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.791507442
Short name T1414
Test name
Test status
Simulation time 50871337 ps
CPU time 0.78 seconds
Started May 07 12:40:38 PM PDT 24
Finished May 07 12:40:40 PM PDT 24
Peak memory 203752 kb
Host smart-c95020ac-8440-4018-b0a1-7227aa09cf7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791507442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.791507442
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.3234599074
Short name T1418
Test name
Test status
Simulation time 27189213 ps
CPU time 0.68 seconds
Started May 07 12:40:30 PM PDT 24
Finished May 07 12:40:32 PM PDT 24
Peak memory 203772 kb
Host smart-b728286a-31b3-4323-8fab-2bc34a37d658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234599074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3234599074
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2097043769
Short name T1422
Test name
Test status
Simulation time 71358355 ps
CPU time 0.85 seconds
Started May 07 12:40:38 PM PDT 24
Finished May 07 12:40:41 PM PDT 24
Peak memory 203780 kb
Host smart-76f02281-2d50-4bab-8710-e29dfa1d4a71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097043769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.2097043769
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2404514620
Short name T122
Test name
Test status
Simulation time 35956113 ps
CPU time 1.53 seconds
Started May 07 12:40:27 PM PDT 24
Finished May 07 12:40:30 PM PDT 24
Peak memory 203956 kb
Host smart-4d65af19-c67c-4e3e-868d-c310022441d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404514620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2404514620
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3904763016
Short name T1424
Test name
Test status
Simulation time 46841607 ps
CPU time 1.44 seconds
Started May 07 12:40:36 PM PDT 24
Finished May 07 12:40:38 PM PDT 24
Peak memory 203868 kb
Host smart-d4da7c52-4940-493e-8d55-6c4c94bada68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904763016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3904763016
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.874589750
Short name T1452
Test name
Test status
Simulation time 117470131 ps
CPU time 0.97 seconds
Started May 07 12:40:26 PM PDT 24
Finished May 07 12:40:28 PM PDT 24
Peak memory 203908 kb
Host smart-3f797988-83d4-4c71-a5ca-97b8c28b9460
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874589750 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.874589750
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.207691345
Short name T168
Test name
Test status
Simulation time 18359900 ps
CPU time 0.74 seconds
Started May 07 12:40:36 PM PDT 24
Finished May 07 12:40:38 PM PDT 24
Peak memory 203824 kb
Host smart-f5f56b57-25f1-403d-8da5-3557dbd2718d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207691345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.207691345
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.2120106958
Short name T1464
Test name
Test status
Simulation time 127918988 ps
CPU time 0.63 seconds
Started May 07 12:40:36 PM PDT 24
Finished May 07 12:40:38 PM PDT 24
Peak memory 203712 kb
Host smart-7eed26b9-3a92-41e6-a1d9-d5108cb49ce5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120106958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2120106958
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1019698433
Short name T175
Test name
Test status
Simulation time 61553609 ps
CPU time 1.2 seconds
Started May 07 12:40:37 PM PDT 24
Finished May 07 12:40:40 PM PDT 24
Peak memory 203904 kb
Host smart-095b5fcc-19b9-43e8-9d6a-e0dad59967ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019698433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.1019698433
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.336454865
Short name T1448
Test name
Test status
Simulation time 252564272 ps
CPU time 1.63 seconds
Started May 07 12:40:31 PM PDT 24
Finished May 07 12:40:34 PM PDT 24
Peak memory 203996 kb
Host smart-5bca6f37-1a11-483e-9bd2-8ced6e6f772d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336454865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.336454865
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4006998179
Short name T155
Test name
Test status
Simulation time 75724382 ps
CPU time 1.52 seconds
Started May 07 12:40:42 PM PDT 24
Finished May 07 12:40:46 PM PDT 24
Peak memory 203896 kb
Host smart-a00b80c0-9849-4277-8cd1-b171d84f84a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006998179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.4006998179
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3154507184
Short name T1437
Test name
Test status
Simulation time 393280572 ps
CPU time 0.95 seconds
Started May 07 12:40:25 PM PDT 24
Finished May 07 12:40:28 PM PDT 24
Peak memory 203776 kb
Host smart-b0ef99c7-148e-4a48-8226-dacfc94b3578
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154507184 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.3154507184
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3680455649
Short name T176
Test name
Test status
Simulation time 83121298 ps
CPU time 0.73 seconds
Started May 07 12:40:46 PM PDT 24
Finished May 07 12:40:50 PM PDT 24
Peak memory 203768 kb
Host smart-6aae6947-f9d4-4210-9acf-21915851c1d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680455649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3680455649
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.3111457542
Short name T1438
Test name
Test status
Simulation time 29951047 ps
CPU time 0.65 seconds
Started May 07 12:40:16 PM PDT 24
Finished May 07 12:40:19 PM PDT 24
Peak memory 203704 kb
Host smart-6b2e9afc-75c0-4e9d-828f-b95b4287a018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111457542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.3111457542
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.434243396
Short name T177
Test name
Test status
Simulation time 256857450 ps
CPU time 1.13 seconds
Started May 07 12:40:17 PM PDT 24
Finished May 07 12:40:21 PM PDT 24
Peak memory 203916 kb
Host smart-67d0f5a6-db8d-437c-b604-35a19f4408b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434243396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_out
standing.434243396
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.1295126665
Short name T1431
Test name
Test status
Simulation time 780100471 ps
CPU time 2.2 seconds
Started May 07 12:40:43 PM PDT 24
Finished May 07 12:40:47 PM PDT 24
Peak memory 203960 kb
Host smart-8b8597f4-8d11-4b96-908e-b8375079884b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295126665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.1295126665
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1698558693
Short name T144
Test name
Test status
Simulation time 86102232 ps
CPU time 1.52 seconds
Started May 07 12:40:39 PM PDT 24
Finished May 07 12:40:43 PM PDT 24
Peak memory 203896 kb
Host smart-ac7123ba-1cfa-48aa-9119-19b61b259261
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698558693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.1698558693
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1950192479
Short name T1443
Test name
Test status
Simulation time 57881358 ps
CPU time 0.92 seconds
Started May 07 12:40:39 PM PDT 24
Finished May 07 12:40:42 PM PDT 24
Peak memory 203832 kb
Host smart-5deca50a-000d-46e4-ad24-0f56d1bda6d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950192479 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1950192479
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3581284391
Short name T160
Test name
Test status
Simulation time 59946285 ps
CPU time 0.69 seconds
Started May 07 12:40:40 PM PDT 24
Finished May 07 12:40:43 PM PDT 24
Peak memory 203804 kb
Host smart-eacb6cdb-39f5-4d66-80f4-013325b82da3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581284391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.3581284391
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.2549660240
Short name T1471
Test name
Test status
Simulation time 17479675 ps
CPU time 0.68 seconds
Started May 07 12:40:32 PM PDT 24
Finished May 07 12:40:34 PM PDT 24
Peak memory 203708 kb
Host smart-35a594c2-4c9a-4edc-99ee-d73c058f2309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549660240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.2549660240
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3537285364
Short name T1461
Test name
Test status
Simulation time 21791006 ps
CPU time 0.84 seconds
Started May 07 12:40:34 PM PDT 24
Finished May 07 12:40:36 PM PDT 24
Peak memory 203744 kb
Host smart-9286f958-c33b-400e-ae64-1bf0cc764dd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537285364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.3537285364
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3263604119
Short name T1430
Test name
Test status
Simulation time 216017067 ps
CPU time 2.38 seconds
Started May 07 12:40:50 PM PDT 24
Finished May 07 12:40:55 PM PDT 24
Peak memory 203940 kb
Host smart-ddf6a4de-c22d-4e0c-ac11-98c09a9e92e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263604119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3263604119
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3634854659
Short name T145
Test name
Test status
Simulation time 126885650 ps
CPU time 1.59 seconds
Started May 07 12:40:36 PM PDT 24
Finished May 07 12:40:38 PM PDT 24
Peak memory 203932 kb
Host smart-aa7d2273-17e7-4865-a786-e4e3c0893e28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634854659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.3634854659
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2425402813
Short name T1456
Test name
Test status
Simulation time 126178278 ps
CPU time 1.01 seconds
Started May 07 12:40:21 PM PDT 24
Finished May 07 12:40:25 PM PDT 24
Peak memory 203864 kb
Host smart-a80443c5-b818-4aa1-945e-03e8d4095ad8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425402813 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2425402813
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3561796797
Short name T1385
Test name
Test status
Simulation time 47036411 ps
CPU time 0.82 seconds
Started May 07 12:40:44 PM PDT 24
Finished May 07 12:40:48 PM PDT 24
Peak memory 203760 kb
Host smart-54010346-27d4-4809-82d9-4fead734022f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561796797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.3561796797
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.3251974045
Short name T1384
Test name
Test status
Simulation time 23460920 ps
CPU time 0.66 seconds
Started May 07 12:40:16 PM PDT 24
Finished May 07 12:40:20 PM PDT 24
Peak memory 203656 kb
Host smart-e1833ce6-0297-449e-aa0b-211d5a417e8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251974045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.3251974045
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.255719624
Short name T91
Test name
Test status
Simulation time 173228557 ps
CPU time 1.16 seconds
Started May 07 12:40:17 PM PDT 24
Finished May 07 12:40:22 PM PDT 24
Peak memory 203844 kb
Host smart-aaa89502-c57a-4d90-9ead-ad465ce7484c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255719624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_out
standing.255719624
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.697234673
Short name T152
Test name
Test status
Simulation time 219163804 ps
CPU time 2.33 seconds
Started May 07 12:40:37 PM PDT 24
Finished May 07 12:40:40 PM PDT 24
Peak memory 203860 kb
Host smart-9452ac5b-6247-4088-8e47-37024ebba181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697234673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.697234673
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_alert_test.2102992137
Short name T1154
Test name
Test status
Simulation time 18531917 ps
CPU time 0.61 seconds
Started May 07 12:51:52 PM PDT 24
Finished May 07 12:51:54 PM PDT 24
Peak memory 203752 kb
Host smart-ad18b823-5fbf-4e7f-b661-54809377303d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102992137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.2102992137
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.1079297750
Short name T816
Test name
Test status
Simulation time 253601552 ps
CPU time 1.25 seconds
Started May 07 12:51:42 PM PDT 24
Finished May 07 12:51:44 PM PDT 24
Peak memory 212132 kb
Host smart-39667963-fe99-415d-992a-b985efc44fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079297750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.1079297750
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.3780537961
Short name T1141
Test name
Test status
Simulation time 258740962 ps
CPU time 5.82 seconds
Started May 07 12:51:40 PM PDT 24
Finished May 07 12:51:46 PM PDT 24
Peak memory 254592 kb
Host smart-6a0d5f95-53c9-4a46-8233-8c96ff6f0d6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780537961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.3780537961
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3428720524
Short name T63
Test name
Test status
Simulation time 5674779171 ps
CPU time 52.42 seconds
Started May 07 12:51:41 PM PDT 24
Finished May 07 12:52:34 PM PDT 24
Peak memory 521304 kb
Host smart-d5e73dd2-8175-4ec0-910b-e37cb0c3f53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428720524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3428720524
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.3032692174
Short name T315
Test name
Test status
Simulation time 3030231763 ps
CPU time 75.42 seconds
Started May 07 12:51:41 PM PDT 24
Finished May 07 12:52:57 PM PDT 24
Peak memory 459268 kb
Host smart-3c8c31bc-c43f-40f5-b061-928bbe5a7d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032692174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.3032692174
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.2265933615
Short name T1350
Test name
Test status
Simulation time 616309866 ps
CPU time 0.81 seconds
Started May 07 12:51:40 PM PDT 24
Finished May 07 12:51:42 PM PDT 24
Peak memory 203592 kb
Host smart-e9496ae8-7256-4888-8379-fc934939bd45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265933615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.2265933615
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.1269775851
Short name T674
Test name
Test status
Simulation time 2021220894 ps
CPU time 3.73 seconds
Started May 07 12:51:41 PM PDT 24
Finished May 07 12:51:46 PM PDT 24
Peak memory 203872 kb
Host smart-ad3c271f-9436-4cee-96fb-9052232370aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269775851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
1269775851
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.2950117054
Short name T1170
Test name
Test status
Simulation time 8223380699 ps
CPU time 90.94 seconds
Started May 07 12:51:40 PM PDT 24
Finished May 07 12:53:12 PM PDT 24
Peak memory 1004488 kb
Host smart-ee7ae1bf-3740-4ef3-8d00-64ce5a7da9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950117054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.2950117054
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.1465554239
Short name T521
Test name
Test status
Simulation time 520315085 ps
CPU time 4.68 seconds
Started May 07 12:51:53 PM PDT 24
Finished May 07 12:51:58 PM PDT 24
Peak memory 203764 kb
Host smart-fa85b86f-403d-4a7f-8bd2-3ec7e8f8414c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465554239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.1465554239
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.2550112742
Short name T41
Test name
Test status
Simulation time 1285667982 ps
CPU time 18.82 seconds
Started May 07 12:51:52 PM PDT 24
Finished May 07 12:52:11 PM PDT 24
Peak memory 293092 kb
Host smart-8fa0eed4-e4b6-4e26-b7ec-629e8cc9e796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550112742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.2550112742
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.4286415869
Short name T951
Test name
Test status
Simulation time 71816104 ps
CPU time 0.63 seconds
Started May 07 12:51:41 PM PDT 24
Finished May 07 12:51:43 PM PDT 24
Peak memory 203692 kb
Host smart-b649c71f-f88e-4e74-8abb-63ac6563a2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286415869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.4286415869
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.1455940099
Short name T893
Test name
Test status
Simulation time 2960855159 ps
CPU time 64.74 seconds
Started May 07 12:51:40 PM PDT 24
Finished May 07 12:52:46 PM PDT 24
Peak memory 253496 kb
Host smart-8877b0f3-933b-406c-98b8-69364d1c1a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455940099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.1455940099
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.243480853
Short name T718
Test name
Test status
Simulation time 6194386950 ps
CPU time 80.6 seconds
Started May 07 12:51:34 PM PDT 24
Finished May 07 12:52:55 PM PDT 24
Peak memory 341568 kb
Host smart-44fc7cfb-f1f6-4752-82fe-b8b1479d1830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243480853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.243480853
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.378986546
Short name T1086
Test name
Test status
Simulation time 19163108838 ps
CPU time 1519.11 seconds
Started May 07 12:51:41 PM PDT 24
Finished May 07 01:17:02 PM PDT 24
Peak memory 3941096 kb
Host smart-c4c2aade-4968-4df9-97bd-b672e2b5cbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378986546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.378986546
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.2777113753
Short name T239
Test name
Test status
Simulation time 682465310 ps
CPU time 12.75 seconds
Started May 07 12:51:40 PM PDT 24
Finished May 07 12:51:54 PM PDT 24
Peak memory 220304 kb
Host smart-d8151f37-ceda-4ba5-96c3-d343df5c20a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777113753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.2777113753
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.3965579568
Short name T701
Test name
Test status
Simulation time 10280502206 ps
CPU time 6.88 seconds
Started May 07 12:51:47 PM PDT 24
Finished May 07 12:51:55 PM PDT 24
Peak memory 232396 kb
Host smart-c5e197ca-dcea-4538-895d-700e664ffaf6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965579568 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.3965579568
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.203906113
Short name T1063
Test name
Test status
Simulation time 10306070068 ps
CPU time 6.14 seconds
Started May 07 12:51:48 PM PDT 24
Finished May 07 12:51:55 PM PDT 24
Peak memory 244376 kb
Host smart-46cbdb3a-4ce8-40dc-a1df-1f16b8c7a547
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203906113 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_fifo_reset_tx.203906113
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.2316128850
Short name T764
Test name
Test status
Simulation time 464181677 ps
CPU time 2.71 seconds
Started May 07 12:51:52 PM PDT 24
Finished May 07 12:51:56 PM PDT 24
Peak memory 203884 kb
Host smart-297538aa-9a4c-4ae6-ab19-f485019c2edd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316128850 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.2316128850
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.734521528
Short name T581
Test name
Test status
Simulation time 5742725888 ps
CPU time 8.08 seconds
Started May 07 12:51:46 PM PDT 24
Finished May 07 12:51:55 PM PDT 24
Peak memory 218876 kb
Host smart-e13a034b-350f-4330-9ea7-898fabe9b3e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734521528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_intr_smoke.734521528
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.2558874197
Short name T1339
Test name
Test status
Simulation time 10141736691 ps
CPU time 158.67 seconds
Started May 07 12:51:48 PM PDT 24
Finished May 07 12:54:27 PM PDT 24
Peak memory 2607400 kb
Host smart-12231f9d-38f9-4152-9a53-9c6078828817
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558874197 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.2558874197
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.2523097727
Short name T273
Test name
Test status
Simulation time 3920746564 ps
CPU time 32.57 seconds
Started May 07 12:51:40 PM PDT 24
Finished May 07 12:52:13 PM PDT 24
Peak memory 203844 kb
Host smart-553e614f-3047-4dfa-be3b-d8a3022b55f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523097727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.2523097727
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.1895632417
Short name T312
Test name
Test status
Simulation time 972811207 ps
CPU time 14.93 seconds
Started May 07 12:51:42 PM PDT 24
Finished May 07 12:51:58 PM PDT 24
Peak memory 223864 kb
Host smart-91e455ef-e36a-4a1a-90c4-af7f86fc9c47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895632417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.1895632417
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.1070669946
Short name T690
Test name
Test status
Simulation time 51490680305 ps
CPU time 64.79 seconds
Started May 07 12:51:42 PM PDT 24
Finished May 07 12:52:47 PM PDT 24
Peak memory 1100964 kb
Host smart-f1da5165-44ac-482f-9885-78dd28252442
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070669946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.1070669946
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.1944105410
Short name T359
Test name
Test status
Simulation time 5822497507 ps
CPU time 7.57 seconds
Started May 07 12:51:47 PM PDT 24
Finished May 07 12:51:55 PM PDT 24
Peak memory 220236 kb
Host smart-25561eb0-6c53-4547-8f34-5f7c0ed9e7d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944105410 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.1944105410
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.2418055276
Short name T1346
Test name
Test status
Simulation time 100703828 ps
CPU time 1.43 seconds
Started May 07 12:52:01 PM PDT 24
Finished May 07 12:52:03 PM PDT 24
Peak memory 212148 kb
Host smart-0d1d227c-e952-4439-aad2-a73450a7fd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418055276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.2418055276
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.802379798
Short name T350
Test name
Test status
Simulation time 653746064 ps
CPU time 4.07 seconds
Started May 07 12:52:01 PM PDT 24
Finished May 07 12:52:06 PM PDT 24
Peak memory 235024 kb
Host smart-cb981a17-25a8-4198-b2be-a9beaf2692ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802379798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.802379798
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.270078609
Short name T952
Test name
Test status
Simulation time 3909240220 ps
CPU time 124.95 seconds
Started May 07 12:52:00 PM PDT 24
Finished May 07 12:54:06 PM PDT 24
Peak memory 595124 kb
Host smart-551617ce-d910-4072-814f-583a7979d2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270078609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.270078609
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.1664708397
Short name T675
Test name
Test status
Simulation time 1662729786 ps
CPU time 119.3 seconds
Started May 07 12:51:59 PM PDT 24
Finished May 07 12:53:59 PM PDT 24
Peak memory 616828 kb
Host smart-4992ed41-d2d8-42ea-82a3-9dc500e6ebe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664708397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.1664708397
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.3762857723
Short name T614
Test name
Test status
Simulation time 118823312 ps
CPU time 0.99 seconds
Started May 07 12:51:58 PM PDT 24
Finished May 07 12:52:00 PM PDT 24
Peak memory 203760 kb
Host smart-cfd58a59-348e-4c0c-87b4-fe89da54bd08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762857723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.3762857723
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.4254280644
Short name T769
Test name
Test status
Simulation time 664891550 ps
CPU time 10.16 seconds
Started May 07 12:52:00 PM PDT 24
Finished May 07 12:52:11 PM PDT 24
Peak memory 235996 kb
Host smart-430610bb-1515-49c1-9eef-f1941a0a0a9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254280644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
4254280644
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.3612561728
Short name T931
Test name
Test status
Simulation time 23889477367 ps
CPU time 64.55 seconds
Started May 07 12:51:53 PM PDT 24
Finished May 07 12:52:59 PM PDT 24
Peak memory 846528 kb
Host smart-eed6929f-b412-44f3-ac4e-83b18f1b2556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612561728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.3612561728
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.3940091536
Short name T1099
Test name
Test status
Simulation time 642131240 ps
CPU time 7.91 seconds
Started May 07 12:52:11 PM PDT 24
Finished May 07 12:52:21 PM PDT 24
Peak memory 203928 kb
Host smart-a8e90ad4-49e6-4f94-b66f-d6742f7770c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940091536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.3940091536
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.1887200658
Short name T925
Test name
Test status
Simulation time 3071541905 ps
CPU time 25.33 seconds
Started May 07 12:52:10 PM PDT 24
Finished May 07 12:52:37 PM PDT 24
Peak memory 347300 kb
Host smart-f12ca0d2-e8fb-4d3c-b705-d4f3f6c27ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887200658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.1887200658
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_perf.3944251431
Short name T980
Test name
Test status
Simulation time 3240136643 ps
CPU time 9.71 seconds
Started May 07 12:52:01 PM PDT 24
Finished May 07 12:52:12 PM PDT 24
Peak memory 212232 kb
Host smart-27583253-f532-449d-b174-8230b9d79e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944251431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.3944251431
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.2576888009
Short name T1216
Test name
Test status
Simulation time 10761468447 ps
CPU time 12.95 seconds
Started May 07 12:51:51 PM PDT 24
Finished May 07 12:52:05 PM PDT 24
Peak memory 260448 kb
Host smart-d2ba6a9b-7bf3-4309-82fb-876bd10f8b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576888009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2576888009
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.2485161456
Short name T248
Test name
Test status
Simulation time 58700458857 ps
CPU time 1678.43 seconds
Started May 07 12:51:59 PM PDT 24
Finished May 07 01:19:58 PM PDT 24
Peak memory 1744932 kb
Host smart-309f57d3-18fb-4ea4-a531-032e8177f404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485161456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.2485161456
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.963767350
Short name T817
Test name
Test status
Simulation time 5826743401 ps
CPU time 22.44 seconds
Started May 07 12:51:59 PM PDT 24
Finished May 07 12:52:22 PM PDT 24
Peak memory 212196 kb
Host smart-f3271a74-1d91-48ac-9889-e30b021880cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963767350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.963767350
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.728268067
Short name T127
Test name
Test status
Simulation time 158661136 ps
CPU time 0.84 seconds
Started May 07 12:52:11 PM PDT 24
Finished May 07 12:52:14 PM PDT 24
Peak memory 221388 kb
Host smart-f64911f6-c2d3-4781-91e8-b60e0f39d157
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728268067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.728268067
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.2556646009
Short name T956
Test name
Test status
Simulation time 8970788794 ps
CPU time 5.2 seconds
Started May 07 12:52:05 PM PDT 24
Finished May 07 12:52:11 PM PDT 24
Peak memory 212400 kb
Host smart-01603fdd-0f84-4d53-bcb7-b28155c44beb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556646009 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.2556646009
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.3879389853
Short name T748
Test name
Test status
Simulation time 10563438436 ps
CPU time 8.93 seconds
Started May 07 12:52:05 PM PDT 24
Finished May 07 12:52:15 PM PDT 24
Peak memory 262712 kb
Host smart-56cfc2f9-6cf4-4491-82b2-14ab8a1e42fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879389853 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.3879389853
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.1067954737
Short name T23
Test name
Test status
Simulation time 5453341247 ps
CPU time 11.75 seconds
Started May 07 12:52:01 PM PDT 24
Finished May 07 12:52:14 PM PDT 24
Peak memory 212348 kb
Host smart-33a94766-3372-4e1c-9c42-a5b2a6d904d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067954737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.1067954737
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.2071998884
Short name T1324
Test name
Test status
Simulation time 2115074923 ps
CPU time 3.47 seconds
Started May 07 12:52:10 PM PDT 24
Finished May 07 12:52:15 PM PDT 24
Peak memory 203992 kb
Host smart-15078e66-478c-4b2a-9b39-d579a3ff5a08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071998884 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.2071998884
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.3907648400
Short name T841
Test name
Test status
Simulation time 2620410344 ps
CPU time 7.32 seconds
Started May 07 12:52:06 PM PDT 24
Finished May 07 12:52:15 PM PDT 24
Peak memory 220228 kb
Host smart-6a5f5c53-f1d5-4f43-b6f3-1580c9161b6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907648400 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.3907648400
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.771815428
Short name T991
Test name
Test status
Simulation time 8618121094 ps
CPU time 16.61 seconds
Started May 07 12:52:08 PM PDT 24
Finished May 07 12:52:25 PM PDT 24
Peak memory 615328 kb
Host smart-38fdcc99-294b-475a-bf95-24df54578a84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771815428 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.771815428
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.629169909
Short name T973
Test name
Test status
Simulation time 1271513981 ps
CPU time 12.68 seconds
Started May 07 12:52:06 PM PDT 24
Finished May 07 12:52:19 PM PDT 24
Peak memory 207244 kb
Host smart-c71f49c9-363f-46f4-a87b-621e172a632b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629169909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_rd.629169909
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.2255865729
Short name T694
Test name
Test status
Simulation time 44766889340 ps
CPU time 111.89 seconds
Started May 07 12:52:07 PM PDT 24
Finished May 07 12:54:00 PM PDT 24
Peak memory 1440012 kb
Host smart-9e644130-f43b-4b16-8088-44231aea3f1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255865729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.2255865729
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.951817749
Short name T439
Test name
Test status
Simulation time 20299593614 ps
CPU time 1261.43 seconds
Started May 07 12:52:07 PM PDT 24
Finished May 07 01:13:10 PM PDT 24
Peak memory 4787964 kb
Host smart-d57cb252-c5ac-414b-ab46-ffc3328a8a87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951817749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_ta
rget_stretch.951817749
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.1885488678
Short name T1009
Test name
Test status
Simulation time 5274317391 ps
CPU time 7.4 seconds
Started May 07 12:52:06 PM PDT 24
Finished May 07 12:52:14 PM PDT 24
Peak memory 212200 kb
Host smart-4422d89a-46e6-4f89-a6e0-3de2d9fd0ca5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885488678 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.1885488678
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.899388199
Short name T1168
Test name
Test status
Simulation time 38972288 ps
CPU time 0.6 seconds
Started May 07 12:53:51 PM PDT 24
Finished May 07 12:53:53 PM PDT 24
Peak memory 203800 kb
Host smart-0b01dd6c-ff22-40ed-9c95-70ba439fb69f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899388199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.899388199
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.3492557622
Short name T1185
Test name
Test status
Simulation time 331488216 ps
CPU time 1.57 seconds
Started May 07 12:53:40 PM PDT 24
Finished May 07 12:53:42 PM PDT 24
Peak memory 212180 kb
Host smart-29d90ebc-0b09-47bf-bf7d-c3a62422014d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492557622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.3492557622
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.250888947
Short name T426
Test name
Test status
Simulation time 434350032 ps
CPU time 23 seconds
Started May 07 12:53:42 PM PDT 24
Finished May 07 12:54:07 PM PDT 24
Peak memory 275248 kb
Host smart-d373a828-47a4-4047-b49d-fdfcb4169e3a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250888947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empt
y.250888947
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.1171274275
Short name T98
Test name
Test status
Simulation time 14685562505 ps
CPU time 59.48 seconds
Started May 07 12:53:41 PM PDT 24
Finished May 07 12:54:42 PM PDT 24
Peak memory 642592 kb
Host smart-270e3cea-f51b-4106-8f65-102488674539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171274275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.1171274275
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.1853540298
Short name T445
Test name
Test status
Simulation time 2232191030 ps
CPU time 71.95 seconds
Started May 07 12:53:40 PM PDT 24
Finished May 07 12:54:54 PM PDT 24
Peak memory 756952 kb
Host smart-69a45a16-1a77-46ad-a3e5-77034aa8ac21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853540298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1853540298
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.834267201
Short name T591
Test name
Test status
Simulation time 62206206 ps
CPU time 0.82 seconds
Started May 07 12:53:42 PM PDT 24
Finished May 07 12:53:44 PM PDT 24
Peak memory 203780 kb
Host smart-bb915277-7e7f-495c-b2f7-887b387ee882
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834267201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fm
t.834267201
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1677557528
Short name T510
Test name
Test status
Simulation time 691212629 ps
CPU time 8.83 seconds
Started May 07 12:53:39 PM PDT 24
Finished May 07 12:53:49 PM PDT 24
Peak memory 203912 kb
Host smart-464914b6-2fc4-4655-badf-8751093cf2ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677557528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1677557528
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.3613501913
Short name T1303
Test name
Test status
Simulation time 63344157137 ps
CPU time 156.84 seconds
Started May 07 12:53:40 PM PDT 24
Finished May 07 12:56:18 PM PDT 24
Peak memory 1306864 kb
Host smart-8f48fe69-0514-47fc-9751-6e3d00f64479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613501913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.3613501913
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.566300828
Short name T719
Test name
Test status
Simulation time 567786384 ps
CPU time 19.41 seconds
Started May 07 12:53:47 PM PDT 24
Finished May 07 12:54:07 PM PDT 24
Peak memory 203888 kb
Host smart-18d7d9c6-1edc-4065-8962-74f8a401ff19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566300828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.566300828
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.3086378142
Short name T520
Test name
Test status
Simulation time 2929860896 ps
CPU time 33.66 seconds
Started May 07 12:53:53 PM PDT 24
Finished May 07 12:54:27 PM PDT 24
Peak memory 413140 kb
Host smart-d97599a8-a441-4765-b961-2b4c99df12c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086378142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.3086378142
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.2022185226
Short name T1006
Test name
Test status
Simulation time 372896897 ps
CPU time 0.66 seconds
Started May 07 12:53:41 PM PDT 24
Finished May 07 12:53:43 PM PDT 24
Peak memory 203776 kb
Host smart-9dea6f2d-9cba-43c8-85f0-4cb6e51d77ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022185226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.2022185226
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.1590799545
Short name T629
Test name
Test status
Simulation time 8266801951 ps
CPU time 89.41 seconds
Started May 07 12:53:41 PM PDT 24
Finished May 07 12:55:12 PM PDT 24
Peak memory 212304 kb
Host smart-7733e753-71bf-40cd-bee9-20202c902d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590799545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.1590799545
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.2568775860
Short name T1240
Test name
Test status
Simulation time 7901386366 ps
CPU time 26.01 seconds
Started May 07 12:53:41 PM PDT 24
Finished May 07 12:54:09 PM PDT 24
Peak memory 277588 kb
Host smart-9495fb10-c9a8-42df-93e3-3589844dbcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568775860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.2568775860
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.103586420
Short name T87
Test name
Test status
Simulation time 26170555650 ps
CPU time 1093.48 seconds
Started May 07 12:53:41 PM PDT 24
Finished May 07 01:11:56 PM PDT 24
Peak memory 1711460 kb
Host smart-0e5d8b73-8eb6-4f41-bde9-01005dc6dbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103586420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.103586420
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.809398478
Short name T827
Test name
Test status
Simulation time 1739604146 ps
CPU time 8.82 seconds
Started May 07 12:53:42 PM PDT 24
Finished May 07 12:53:52 PM PDT 24
Peak memory 219920 kb
Host smart-7b726f1e-cfb7-439d-ace9-6cdf2c50b5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809398478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.809398478
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.2870825533
Short name T1031
Test name
Test status
Simulation time 12721547422 ps
CPU time 4.98 seconds
Started May 07 12:53:52 PM PDT 24
Finished May 07 12:53:58 PM PDT 24
Peak memory 212192 kb
Host smart-1e8fcb43-0071-4b2e-af34-90b14345bbe2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870825533 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.2870825533
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.2331808704
Short name T504
Test name
Test status
Simulation time 10123411271 ps
CPU time 32.96 seconds
Started May 07 12:53:46 PM PDT 24
Finished May 07 12:54:20 PM PDT 24
Peak memory 367236 kb
Host smart-306cb502-deb7-47e0-a83d-7abf577342c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331808704 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.2331808704
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.2456206951
Short name T867
Test name
Test status
Simulation time 10075193300 ps
CPU time 79.1 seconds
Started May 07 12:53:50 PM PDT 24
Finished May 07 12:55:11 PM PDT 24
Peak memory 502120 kb
Host smart-f8b9ee60-4263-49a9-a856-a5fb770dbad3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456206951 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.2456206951
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.3046433714
Short name T1210
Test name
Test status
Simulation time 416871998 ps
CPU time 2.83 seconds
Started May 07 12:53:46 PM PDT 24
Finished May 07 12:53:50 PM PDT 24
Peak memory 203832 kb
Host smart-b4912f25-b133-491d-9346-21e240edc820
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046433714 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.3046433714
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.138042745
Short name T548
Test name
Test status
Simulation time 4025854334 ps
CPU time 4.97 seconds
Started May 07 12:53:49 PM PDT 24
Finished May 07 12:53:55 PM PDT 24
Peak memory 204616 kb
Host smart-482c9ab5-8041-4ee4-bee2-7b949646cc40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138042745 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_intr_smoke.138042745
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.3144170499
Short name T269
Test name
Test status
Simulation time 13778737071 ps
CPU time 258.06 seconds
Started May 07 12:53:49 PM PDT 24
Finished May 07 12:58:08 PM PDT 24
Peak memory 3333256 kb
Host smart-966e002b-20e3-44aa-980b-86ce255724cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144170499 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.3144170499
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.3673188296
Short name T1118
Test name
Test status
Simulation time 954910982 ps
CPU time 21.29 seconds
Started May 07 12:53:40 PM PDT 24
Finished May 07 12:54:03 PM PDT 24
Peak memory 203892 kb
Host smart-e28ec303-69c3-43b5-842c-87c90456c6a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673188296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.3673188296
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.3720920188
Short name T705
Test name
Test status
Simulation time 1096530339 ps
CPU time 15.84 seconds
Started May 07 12:53:50 PM PDT 24
Finished May 07 12:54:07 PM PDT 24
Peak memory 224388 kb
Host smart-4f8ae8ac-27e1-4c42-aec0-ef60d3f94b7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720920188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.3720920188
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.1895434053
Short name T353
Test name
Test status
Simulation time 56551829722 ps
CPU time 625.83 seconds
Started May 07 12:53:47 PM PDT 24
Finished May 07 01:04:14 PM PDT 24
Peak memory 4839976 kb
Host smart-87bc55b4-7f0d-4dbe-a518-12fb1e970b46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895434053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.1895434053
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.2510514298
Short name T847
Test name
Test status
Simulation time 10809704705 ps
CPU time 202.01 seconds
Started May 07 12:53:46 PM PDT 24
Finished May 07 12:57:09 PM PDT 24
Peak memory 950268 kb
Host smart-10db8e77-feb3-48fe-a203-caddf6609f74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510514298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.2510514298
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_alert_test.1562446501
Short name T1171
Test name
Test status
Simulation time 27575079 ps
CPU time 0.65 seconds
Started May 07 12:54:00 PM PDT 24
Finished May 07 12:54:02 PM PDT 24
Peak memory 203860 kb
Host smart-a671f40f-809e-4884-8dfb-34ba18b5d433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562446501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.1562446501
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.1603669679
Short name T944
Test name
Test status
Simulation time 96597197 ps
CPU time 1.49 seconds
Started May 07 12:53:52 PM PDT 24
Finished May 07 12:53:55 PM PDT 24
Peak memory 212108 kb
Host smart-63790f00-2a9f-46f7-83fa-25423bf79fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603669679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.1603669679
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.706933653
Short name T1046
Test name
Test status
Simulation time 320683185 ps
CPU time 7.31 seconds
Started May 07 12:53:53 PM PDT 24
Finished May 07 12:54:02 PM PDT 24
Peak memory 267408 kb
Host smart-19961d6f-895f-4e29-aa61-b82a8f518a7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706933653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empt
y.706933653
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.890584595
Short name T243
Test name
Test status
Simulation time 27624936260 ps
CPU time 63.22 seconds
Started May 07 12:53:55 PM PDT 24
Finished May 07 12:54:59 PM PDT 24
Peak memory 623832 kb
Host smart-a278b554-aaa2-44df-a39f-34dfc1a5381a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890584595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.890584595
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.3755165235
Short name T575
Test name
Test status
Simulation time 8984140379 ps
CPU time 156.09 seconds
Started May 07 12:53:50 PM PDT 24
Finished May 07 12:56:28 PM PDT 24
Peak memory 669732 kb
Host smart-9ccc14e0-2e4b-480d-9006-4d0b3547b89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755165235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.3755165235
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.436159945
Short name T1128
Test name
Test status
Simulation time 124361990 ps
CPU time 1.07 seconds
Started May 07 12:53:46 PM PDT 24
Finished May 07 12:53:48 PM PDT 24
Peak memory 203864 kb
Host smart-d4631dce-0614-435b-8a30-66b9be6f8089
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436159945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fm
t.436159945
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.2758964000
Short name T1207
Test name
Test status
Simulation time 699582026 ps
CPU time 6.6 seconds
Started May 07 12:53:52 PM PDT 24
Finished May 07 12:54:00 PM PDT 24
Peak memory 203840 kb
Host smart-aa0f99ac-1407-451d-a1d9-8c7661de3ca6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758964000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.2758964000
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.1334762737
Short name T117
Test name
Test status
Simulation time 14797968724 ps
CPU time 264.56 seconds
Started May 07 12:53:51 PM PDT 24
Finished May 07 12:58:17 PM PDT 24
Peak memory 1087028 kb
Host smart-3ad504f1-64b0-4d99-9125-bb902d52d648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334762737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.1334762737
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.139024526
Short name T317
Test name
Test status
Simulation time 1436978469 ps
CPU time 6.14 seconds
Started May 07 12:54:01 PM PDT 24
Finished May 07 12:54:09 PM PDT 24
Peak memory 203884 kb
Host smart-6bf7450c-d274-489e-86bb-a8d2b26a4b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139024526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.139024526
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.66506882
Short name T1137
Test name
Test status
Simulation time 1297555373 ps
CPU time 62.01 seconds
Started May 07 12:54:00 PM PDT 24
Finished May 07 12:55:03 PM PDT 24
Peak memory 381140 kb
Host smart-8b5326b6-a129-4dfd-beba-42958edffd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66506882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.66506882
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_perf.835967869
Short name T104
Test name
Test status
Simulation time 27248166028 ps
CPU time 607.39 seconds
Started May 07 12:53:54 PM PDT 24
Finished May 07 01:04:02 PM PDT 24
Peak memory 1038252 kb
Host smart-ee3b5679-31be-4fdd-9102-44e75a449465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835967869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.835967869
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.3972075482
Short name T861
Test name
Test status
Simulation time 3583288021 ps
CPU time 23.75 seconds
Started May 07 12:53:47 PM PDT 24
Finished May 07 12:54:12 PM PDT 24
Peak memory 307860 kb
Host smart-e86d6c15-5ce9-4ab1-92e2-84b4ece232c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972075482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.3972075482
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.2315843009
Short name T71
Test name
Test status
Simulation time 22995348165 ps
CPU time 269.29 seconds
Started May 07 12:53:54 PM PDT 24
Finished May 07 12:58:24 PM PDT 24
Peak memory 1023016 kb
Host smart-16e28937-5ef2-4e1d-b93e-13f0585512e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315843009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.2315843009
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.245972091
Short name T918
Test name
Test status
Simulation time 357032167 ps
CPU time 7.27 seconds
Started May 07 12:53:54 PM PDT 24
Finished May 07 12:54:02 PM PDT 24
Peak memory 212092 kb
Host smart-5e4c152b-802c-4522-b938-54dfdd25c055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245972091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.245972091
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.4157762351
Short name T474
Test name
Test status
Simulation time 2848259144 ps
CPU time 3.35 seconds
Started May 07 12:54:01 PM PDT 24
Finished May 07 12:54:06 PM PDT 24
Peak memory 203992 kb
Host smart-b6b6b75c-2dd2-43de-9475-fcb21a4ae778
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157762351 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.4157762351
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.2068573732
Short name T1050
Test name
Test status
Simulation time 10048844701 ps
CPU time 79.67 seconds
Started May 07 12:54:01 PM PDT 24
Finished May 07 12:55:22 PM PDT 24
Peak memory 448204 kb
Host smart-b51c3298-973f-4bb6-9042-3997a6c22daf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068573732 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.2068573732
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.2523726770
Short name T1341
Test name
Test status
Simulation time 10588150492 ps
CPU time 8.25 seconds
Started May 07 12:53:59 PM PDT 24
Finished May 07 12:54:09 PM PDT 24
Peak memory 238160 kb
Host smart-2837d1a7-e6cd-45f6-855f-842780c9a8ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523726770 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.2523726770
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.697741702
Short name T1252
Test name
Test status
Simulation time 4190858638 ps
CPU time 2.11 seconds
Started May 07 12:54:00 PM PDT 24
Finished May 07 12:54:03 PM PDT 24
Peak memory 204004 kb
Host smart-15113a0b-7673-4a85-8d50-f04a330b45cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697741702 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 11.i2c_target_hrst.697741702
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.2331746063
Short name T1103
Test name
Test status
Simulation time 7134375019 ps
CPU time 6.46 seconds
Started May 07 12:53:53 PM PDT 24
Finished May 07 12:54:00 PM PDT 24
Peak memory 220144 kb
Host smart-36acb52f-67f4-43f0-89d2-c020e51d85e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331746063 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.2331746063
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.682532118
Short name T623
Test name
Test status
Simulation time 8029838477 ps
CPU time 20.18 seconds
Started May 07 12:53:54 PM PDT 24
Finished May 07 12:54:16 PM PDT 24
Peak memory 377404 kb
Host smart-cf054f20-5b95-472d-9ff9-002f095a0c31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682532118 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.682532118
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.3027921059
Short name T381
Test name
Test status
Simulation time 837939431 ps
CPU time 11.12 seconds
Started May 07 12:53:52 PM PDT 24
Finished May 07 12:54:04 PM PDT 24
Peak memory 203884 kb
Host smart-cc78e2ea-6417-437d-a3bb-61dda3acd9e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027921059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.3027921059
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.3491655413
Short name T766
Test name
Test status
Simulation time 1190223433 ps
CPU time 52.37 seconds
Started May 07 12:53:54 PM PDT 24
Finished May 07 12:54:48 PM PDT 24
Peak memory 204112 kb
Host smart-2fc407d6-9caf-4621-854a-192e47addd3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491655413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.3491655413
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.905622940
Short name T512
Test name
Test status
Simulation time 45687436981 ps
CPU time 24.46 seconds
Started May 07 12:53:53 PM PDT 24
Finished May 07 12:54:19 PM PDT 24
Peak memory 550684 kb
Host smart-1c376bb9-22c8-44cd-bcf1-e1210602b7be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905622940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_wr.905622940
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.568105846
Short name T1222
Test name
Test status
Simulation time 7208543049 ps
CPU time 7.36 seconds
Started May 07 12:53:53 PM PDT 24
Finished May 07 12:54:02 PM PDT 24
Peak memory 211336 kb
Host smart-79c0b01b-18a8-483a-8b0f-043d4bb3978b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568105846 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_timeout.568105846
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.504372407
Short name T982
Test name
Test status
Simulation time 17139330 ps
CPU time 0.63 seconds
Started May 07 12:54:19 PM PDT 24
Finished May 07 12:54:21 PM PDT 24
Peak memory 203800 kb
Host smart-d351595f-a243-4286-a37b-9ac98713d5c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504372407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.504372407
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.364593502
Short name T455
Test name
Test status
Simulation time 139715956 ps
CPU time 1.38 seconds
Started May 07 12:54:08 PM PDT 24
Finished May 07 12:54:10 PM PDT 24
Peak memory 214808 kb
Host smart-eb89f945-5ea8-464d-8f12-ada0f3ed6521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364593502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.364593502
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.424154046
Short name T399
Test name
Test status
Simulation time 274041524 ps
CPU time 4.48 seconds
Started May 07 12:54:06 PM PDT 24
Finished May 07 12:54:12 PM PDT 24
Peak memory 239188 kb
Host smart-1b87f043-47f5-43a3-a265-70f252349ae2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424154046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empt
y.424154046
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.2927145950
Short name T398
Test name
Test status
Simulation time 2230152992 ps
CPU time 67.69 seconds
Started May 07 12:54:08 PM PDT 24
Finished May 07 12:55:16 PM PDT 24
Peak memory 364088 kb
Host smart-4dd0c463-d60c-43b9-a780-e0f24c3c4053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927145950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.2927145950
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.2331509829
Short name T277
Test name
Test status
Simulation time 6004390659 ps
CPU time 109.89 seconds
Started May 07 12:54:02 PM PDT 24
Finished May 07 12:55:53 PM PDT 24
Peak memory 578888 kb
Host smart-285fb475-c234-4b24-aea7-68f10bef9d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331509829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.2331509829
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.67901207
Short name T1045
Test name
Test status
Simulation time 204237052 ps
CPU time 0.97 seconds
Started May 07 12:53:59 PM PDT 24
Finished May 07 12:54:01 PM PDT 24
Peak memory 203756 kb
Host smart-82051d7e-5744-4513-8857-796e0ab0b925
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67901207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fmt
.67901207
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.3111412829
Short name T1299
Test name
Test status
Simulation time 170932502 ps
CPU time 4.4 seconds
Started May 07 12:54:05 PM PDT 24
Finished May 07 12:54:10 PM PDT 24
Peak memory 231764 kb
Host smart-1932ee77-25e8-44bc-ba6c-32f6b7106d11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111412829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.3111412829
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.313647941
Short name T1160
Test name
Test status
Simulation time 13415715112 ps
CPU time 91.59 seconds
Started May 07 12:54:01 PM PDT 24
Finished May 07 12:55:34 PM PDT 24
Peak memory 1004328 kb
Host smart-64cc0a57-46f3-4fd0-abaa-1d5f9c675fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313647941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.313647941
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.2261543097
Short name T1004
Test name
Test status
Simulation time 1970682420 ps
CPU time 15.11 seconds
Started May 07 12:54:05 PM PDT 24
Finished May 07 12:54:21 PM PDT 24
Peak memory 203920 kb
Host smart-d5436844-9c8e-40b1-8fd8-3e9ec280276f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261543097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.2261543097
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.3666915547
Short name T525
Test name
Test status
Simulation time 3997789419 ps
CPU time 39.94 seconds
Started May 07 12:54:08 PM PDT 24
Finished May 07 12:54:49 PM PDT 24
Peak memory 357108 kb
Host smart-913ee5ba-9b78-4760-b199-f4cfd6c8cd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666915547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.3666915547
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.3289082633
Short name T202
Test name
Test status
Simulation time 18507970 ps
CPU time 0.67 seconds
Started May 07 12:54:01 PM PDT 24
Finished May 07 12:54:03 PM PDT 24
Peak memory 203644 kb
Host smart-dc08e67a-9d3a-480c-afaf-942e2102887d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289082633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.3289082633
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.2817497421
Short name T453
Test name
Test status
Simulation time 27241836062 ps
CPU time 668.36 seconds
Started May 07 12:54:05 PM PDT 24
Finished May 07 01:05:14 PM PDT 24
Peak memory 402472 kb
Host smart-57a4ad9e-2c71-4ad4-a6a2-ecc4ec191d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817497421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2817497421
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.314066996
Short name T1347
Test name
Test status
Simulation time 3196872996 ps
CPU time 34.17 seconds
Started May 07 12:54:03 PM PDT 24
Finished May 07 12:54:38 PM PDT 24
Peak memory 414648 kb
Host smart-d031a54a-e269-4259-b182-ba70c036ecf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314066996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.314066996
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.546190601
Short name T1184
Test name
Test status
Simulation time 596044523 ps
CPU time 9.58 seconds
Started May 07 12:54:07 PM PDT 24
Finished May 07 12:54:18 PM PDT 24
Peak memory 218236 kb
Host smart-be32e1ee-36b5-4063-984f-fa2f0bfa0d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546190601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.546190601
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.1724674862
Short name T796
Test name
Test status
Simulation time 551027049 ps
CPU time 3.52 seconds
Started May 07 12:54:07 PM PDT 24
Finished May 07 12:54:11 PM PDT 24
Peak memory 203876 kb
Host smart-00bd5578-3c2b-4f86-b439-edbc78e68251
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724674862 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.1724674862
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.2023065288
Short name T838
Test name
Test status
Simulation time 10301406528 ps
CPU time 15.33 seconds
Started May 07 12:54:07 PM PDT 24
Finished May 07 12:54:23 PM PDT 24
Peak memory 257452 kb
Host smart-3e726da2-6f03-4e59-8d55-bcfe3b07a67b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023065288 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.2023065288
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.282650980
Short name T700
Test name
Test status
Simulation time 10154567457 ps
CPU time 19.28 seconds
Started May 07 12:54:07 PM PDT 24
Finished May 07 12:54:27 PM PDT 24
Peak memory 294580 kb
Host smart-ee3b30f5-9a29-46b6-97bb-64c05a910400
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282650980 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.282650980
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.3489987127
Short name T1287
Test name
Test status
Simulation time 975589327 ps
CPU time 2.53 seconds
Started May 07 12:54:09 PM PDT 24
Finished May 07 12:54:12 PM PDT 24
Peak memory 203912 kb
Host smart-ea0c3801-380a-4c57-b7e6-22a282d9ab95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489987127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.3489987127
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.3933276229
Short name T729
Test name
Test status
Simulation time 3149331622 ps
CPU time 4.97 seconds
Started May 07 12:54:06 PM PDT 24
Finished May 07 12:54:12 PM PDT 24
Peak memory 207656 kb
Host smart-6850267d-0801-4074-8165-b666597d23d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933276229 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.3933276229
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.3132097669
Short name T365
Test name
Test status
Simulation time 24297771022 ps
CPU time 604.83 seconds
Started May 07 12:54:06 PM PDT 24
Finished May 07 01:04:12 PM PDT 24
Peak memory 6026364 kb
Host smart-bc213309-2b76-40fc-a97d-312ac36f5a91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132097669 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.3132097669
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.2330186329
Short name T1055
Test name
Test status
Simulation time 3044379649 ps
CPU time 32.52 seconds
Started May 07 12:54:08 PM PDT 24
Finished May 07 12:54:41 PM PDT 24
Peak memory 203944 kb
Host smart-254c4a7a-386e-40d4-b7a0-4f51add2e014
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330186329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.2330186329
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.2478830974
Short name T36
Test name
Test status
Simulation time 1219026577 ps
CPU time 54.19 seconds
Started May 07 12:54:05 PM PDT 24
Finished May 07 12:55:00 PM PDT 24
Peak memory 204992 kb
Host smart-05ac3eb8-f1f3-4d87-a9ab-5a644080b1f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478830974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.2478830974
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.2798479369
Short name T1323
Test name
Test status
Simulation time 19641352051 ps
CPU time 11.27 seconds
Started May 07 12:54:08 PM PDT 24
Finished May 07 12:54:20 PM PDT 24
Peak memory 203968 kb
Host smart-fad0d932-f544-4e64-96e0-7783112061a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798479369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.2798479369
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.3476963345
Short name T275
Test name
Test status
Simulation time 21187536143 ps
CPU time 1132.71 seconds
Started May 07 12:54:08 PM PDT 24
Finished May 07 01:13:01 PM PDT 24
Peak memory 2427460 kb
Host smart-fc04dc75-3fc4-4b9f-98a4-882a7001204b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476963345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.3476963345
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.2168869465
Short name T301
Test name
Test status
Simulation time 5222389805 ps
CPU time 6.99 seconds
Started May 07 12:54:07 PM PDT 24
Finished May 07 12:54:15 PM PDT 24
Peak memory 219392 kb
Host smart-313b64b3-fa6d-4ee9-991c-001ea15a6732
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168869465 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.2168869465
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.65479716
Short name T949
Test name
Test status
Simulation time 16427709 ps
CPU time 0.63 seconds
Started May 07 12:54:18 PM PDT 24
Finished May 07 12:54:20 PM PDT 24
Peak memory 203784 kb
Host smart-81951af9-615b-4c02-b494-adffd96714a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65479716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.65479716
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.2703559230
Short name T685
Test name
Test status
Simulation time 652845849 ps
CPU time 1.52 seconds
Started May 07 12:54:11 PM PDT 24
Finished May 07 12:54:14 PM PDT 24
Peak memory 212188 kb
Host smart-ee934948-2bf2-43ed-b282-e9fb20e3d6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703559230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.2703559230
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.240093012
Short name T360
Test name
Test status
Simulation time 305449487 ps
CPU time 5.57 seconds
Started May 07 12:54:11 PM PDT 24
Finished May 07 12:54:17 PM PDT 24
Peak memory 257756 kb
Host smart-b73f3663-79d6-4bbd-acc5-95a9caab8be8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240093012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empt
y.240093012
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.2200351032
Short name T103
Test name
Test status
Simulation time 3178539871 ps
CPU time 50.52 seconds
Started May 07 12:54:18 PM PDT 24
Finished May 07 12:55:10 PM PDT 24
Peak memory 524116 kb
Host smart-195dd940-32ff-404d-8543-52d5dcbb38ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200351032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.2200351032
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.2652581365
Short name T1151
Test name
Test status
Simulation time 1308673916 ps
CPU time 36.2 seconds
Started May 07 12:54:12 PM PDT 24
Finished May 07 12:54:49 PM PDT 24
Peak memory 515884 kb
Host smart-76451c2e-3565-42a0-9fad-591517db2382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652581365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.2652581365
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.182352125
Short name T215
Test name
Test status
Simulation time 387003567 ps
CPU time 1.14 seconds
Started May 07 12:54:15 PM PDT 24
Finished May 07 12:54:17 PM PDT 24
Peak memory 203912 kb
Host smart-84317b80-723d-4492-9029-1e4ba05c4f50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182352125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_fm
t.182352125
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3890764510
Short name T1110
Test name
Test status
Simulation time 116436428 ps
CPU time 2.8 seconds
Started May 07 12:54:19 PM PDT 24
Finished May 07 12:54:23 PM PDT 24
Peak memory 203896 kb
Host smart-b0dcf821-2a46-4bec-9e7b-43004085b461
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890764510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3890764510
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.3938158877
Short name T1142
Test name
Test status
Simulation time 5885539933 ps
CPU time 109.41 seconds
Started May 07 12:54:13 PM PDT 24
Finished May 07 12:56:03 PM PDT 24
Peak memory 1244720 kb
Host smart-be3a0648-019b-4eb3-a035-7282f04322d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938158877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.3938158877
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.2332755898
Short name T1127
Test name
Test status
Simulation time 374562832 ps
CPU time 15.35 seconds
Started May 07 12:54:18 PM PDT 24
Finished May 07 12:54:35 PM PDT 24
Peak memory 203932 kb
Host smart-e9a80881-6128-4ac8-983a-b07d0f561f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332755898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.2332755898
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.2983321176
Short name T110
Test name
Test status
Simulation time 4235341311 ps
CPU time 27.5 seconds
Started May 07 12:54:21 PM PDT 24
Finished May 07 12:54:49 PM PDT 24
Peak memory 342196 kb
Host smart-9c640f3d-7a69-43e6-a824-51e72d20f55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983321176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.2983321176
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.1447027203
Short name T205
Test name
Test status
Simulation time 28144143 ps
CPU time 0.64 seconds
Started May 07 12:54:11 PM PDT 24
Finished May 07 12:54:12 PM PDT 24
Peak memory 203716 kb
Host smart-f3b67945-3d31-41eb-863d-35735ff773d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447027203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1447027203
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.118919112
Short name T1253
Test name
Test status
Simulation time 7361192590 ps
CPU time 101.7 seconds
Started May 07 12:54:18 PM PDT 24
Finished May 07 12:56:01 PM PDT 24
Peak memory 809540 kb
Host smart-4f0ad83b-7cd2-4d9a-a2f9-6df6cac99dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118919112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.118919112
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.593052711
Short name T369
Test name
Test status
Simulation time 2880540055 ps
CPU time 78.49 seconds
Started May 07 12:54:14 PM PDT 24
Finished May 07 12:55:34 PM PDT 24
Peak memory 382172 kb
Host smart-ce65dc6c-b9b1-4b63-bc32-48277ecc64b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593052711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.593052711
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.4078006640
Short name T94
Test name
Test status
Simulation time 40989125591 ps
CPU time 399.87 seconds
Started May 07 12:54:12 PM PDT 24
Finished May 07 01:00:53 PM PDT 24
Peak memory 1800412 kb
Host smart-30dfe84b-5cfa-4c39-8bf0-ebbee6b5ef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078006640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.4078006640
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.696546898
Short name T774
Test name
Test status
Simulation time 3418261356 ps
CPU time 13.22 seconds
Started May 07 12:54:14 PM PDT 24
Finished May 07 12:54:28 PM PDT 24
Peak memory 228708 kb
Host smart-d39b7302-8856-4fbf-b284-e6c060943df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696546898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.696546898
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.2472265721
Short name T683
Test name
Test status
Simulation time 441391247 ps
CPU time 2.67 seconds
Started May 07 12:54:13 PM PDT 24
Finished May 07 12:54:17 PM PDT 24
Peak memory 203920 kb
Host smart-bcf1d352-d896-4cc5-9407-49a8c13e6759
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472265721 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.2472265721
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.902002022
Short name T408
Test name
Test status
Simulation time 10091701407 ps
CPU time 76.8 seconds
Started May 07 12:54:12 PM PDT 24
Finished May 07 12:55:30 PM PDT 24
Peak memory 404160 kb
Host smart-fe5c4829-092f-4a7b-b03e-65d7bb512fcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902002022 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_acq.902002022
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.1670812797
Short name T1275
Test name
Test status
Simulation time 10295186037 ps
CPU time 16.82 seconds
Started May 07 12:54:11 PM PDT 24
Finished May 07 12:54:28 PM PDT 24
Peak memory 286272 kb
Host smart-81cc6c4f-3dd5-48c2-ab54-bce27e3a43e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670812797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.1670812797
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.2232007338
Short name T1041
Test name
Test status
Simulation time 1017434383 ps
CPU time 2.98 seconds
Started May 07 12:54:13 PM PDT 24
Finished May 07 12:54:17 PM PDT 24
Peak memory 203756 kb
Host smart-05bf1fca-0b5a-48c1-b1ce-0a5ec1db9c02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232007338 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.2232007338
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.2285649966
Short name T1017
Test name
Test status
Simulation time 10134400889 ps
CPU time 43.32 seconds
Started May 07 12:54:11 PM PDT 24
Finished May 07 12:54:55 PM PDT 24
Peak memory 848100 kb
Host smart-c74d88f1-3553-4a8f-9596-8412c0071285
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285649966 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.2285649966
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.2852291458
Short name T372
Test name
Test status
Simulation time 2461954158 ps
CPU time 50.52 seconds
Started May 07 12:54:15 PM PDT 24
Finished May 07 12:55:06 PM PDT 24
Peak memory 203904 kb
Host smart-4b6bdb7e-c852-42bf-b15b-0b3935bbc92c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852291458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.2852291458
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.4074115045
Short name T133
Test name
Test status
Simulation time 1302752550 ps
CPU time 21.77 seconds
Started May 07 12:54:18 PM PDT 24
Finished May 07 12:54:41 PM PDT 24
Peak memory 224204 kb
Host smart-0205b581-81d1-4d11-a222-dbd495a525dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074115045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.4074115045
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.1974112228
Short name T450
Test name
Test status
Simulation time 27164529357 ps
CPU time 143.99 seconds
Started May 07 12:54:13 PM PDT 24
Finished May 07 12:56:38 PM PDT 24
Peak memory 1902588 kb
Host smart-997c68de-e7d3-4af9-a6db-8f2bcf9e2ba1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974112228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.1974112228
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.910400889
Short name T555
Test name
Test status
Simulation time 2901419984 ps
CPU time 7.51 seconds
Started May 07 12:54:11 PM PDT 24
Finished May 07 12:54:19 PM PDT 24
Peak memory 217312 kb
Host smart-5317dee8-b23f-466e-9038-9290e6fcfa35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910400889 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_timeout.910400889
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_unexp_stop.1038715051
Short name T4
Test name
Test status
Simulation time 1432371710 ps
CPU time 4.36 seconds
Started May 07 12:54:12 PM PDT 24
Finished May 07 12:54:17 PM PDT 24
Peak memory 204288 kb
Host smart-c6c74480-bd55-445b-b986-b76228173409
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038715051 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.i2c_target_unexp_stop.1038715051
Directory /workspace/13.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/14.i2c_alert_test.2213284379
Short name T385
Test name
Test status
Simulation time 14915388 ps
CPU time 0.63 seconds
Started May 07 12:54:24 PM PDT 24
Finished May 07 12:54:26 PM PDT 24
Peak memory 203768 kb
Host smart-fdd06109-4fe0-4054-81e8-7a91106e2a1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213284379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.2213284379
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.3310994096
Short name T568
Test name
Test status
Simulation time 56431481 ps
CPU time 1.13 seconds
Started May 07 12:54:20 PM PDT 24
Finished May 07 12:54:22 PM PDT 24
Peak memory 212188 kb
Host smart-ae40fada-2e87-4fa8-8f4f-6ddaf5cd8529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310994096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.3310994096
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.595606103
Short name T636
Test name
Test status
Simulation time 1400018094 ps
CPU time 20.02 seconds
Started May 07 12:54:18 PM PDT 24
Finished May 07 12:54:40 PM PDT 24
Peak memory 282536 kb
Host smart-3dde7e82-36cc-4298-bbf9-1134657466f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595606103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empt
y.595606103
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.336846773
Short name T798
Test name
Test status
Simulation time 1675400037 ps
CPU time 108.12 seconds
Started May 07 12:54:20 PM PDT 24
Finished May 07 12:56:09 PM PDT 24
Peak memory 514112 kb
Host smart-fa6ecae5-c3ef-4a01-a4a3-7e423471a519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336846773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.336846773
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.3001425165
Short name T321
Test name
Test status
Simulation time 7188226007 ps
CPU time 39.73 seconds
Started May 07 12:54:18 PM PDT 24
Finished May 07 12:54:58 PM PDT 24
Peak memory 441540 kb
Host smart-e86820ae-35ff-40ba-a37b-a9415ac616a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001425165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3001425165
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2889886646
Short name T1026
Test name
Test status
Simulation time 2281642784 ps
CPU time 1.13 seconds
Started May 07 12:54:19 PM PDT 24
Finished May 07 12:54:21 PM PDT 24
Peak memory 203900 kb
Host smart-e813d9ca-1252-4fd4-a0c8-4fc0b9685e03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889886646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2889886646
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.2776449086
Short name T1357
Test name
Test status
Simulation time 198070978 ps
CPU time 2.43 seconds
Started May 07 12:54:18 PM PDT 24
Finished May 07 12:54:22 PM PDT 24
Peak memory 203964 kb
Host smart-a1ee1e56-1681-41d8-bed6-99f21b5310e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776449086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.2776449086
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.2627171762
Short name T583
Test name
Test status
Simulation time 2198565081 ps
CPU time 136.83 seconds
Started May 07 12:54:19 PM PDT 24
Finished May 07 12:56:37 PM PDT 24
Peak memory 695596 kb
Host smart-216e9515-41f2-4568-b3bc-5f1025dfffae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627171762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.2627171762
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.1036986056
Short name T494
Test name
Test status
Simulation time 425789023 ps
CPU time 4.41 seconds
Started May 07 12:54:27 PM PDT 24
Finished May 07 12:54:33 PM PDT 24
Peak memory 203864 kb
Host smart-d705dbe9-5056-4e5a-a3e4-a24658d8ed73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036986056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.1036986056
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.4135997701
Short name T1076
Test name
Test status
Simulation time 2057626302 ps
CPU time 22.9 seconds
Started May 07 12:54:24 PM PDT 24
Finished May 07 12:54:48 PM PDT 24
Peak memory 347768 kb
Host smart-7757fc07-073b-44ab-9f12-91433330f67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135997701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.4135997701
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.2389734006
Short name T642
Test name
Test status
Simulation time 44465405 ps
CPU time 0.68 seconds
Started May 07 12:54:19 PM PDT 24
Finished May 07 12:54:21 PM PDT 24
Peak memory 203440 kb
Host smart-70f52610-ddc0-4baf-8d05-84ef6e204031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389734006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.2389734006
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.2570947497
Short name T1116
Test name
Test status
Simulation time 49370569501 ps
CPU time 623.61 seconds
Started May 07 12:54:19 PM PDT 24
Finished May 07 01:04:44 PM PDT 24
Peak memory 908152 kb
Host smart-9cb857f4-10e8-4fa6-a9fa-66cc365d77b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570947497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.2570947497
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.2415181819
Short name T1013
Test name
Test status
Simulation time 2425750668 ps
CPU time 13.37 seconds
Started May 07 12:54:18 PM PDT 24
Finished May 07 12:54:32 PM PDT 24
Peak memory 295300 kb
Host smart-d7645b02-f3bc-41f5-9dd3-f7794f4d660e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415181819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.2415181819
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.3811749816
Short name T895
Test name
Test status
Simulation time 44912610371 ps
CPU time 1702.52 seconds
Started May 07 12:54:22 PM PDT 24
Finished May 07 01:22:46 PM PDT 24
Peak memory 2506004 kb
Host smart-4d37275f-6c49-4f74-af78-82b57a3aca1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811749816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.3811749816
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.2054722561
Short name T314
Test name
Test status
Simulation time 338185656 ps
CPU time 5.44 seconds
Started May 07 12:54:22 PM PDT 24
Finished May 07 12:54:28 PM PDT 24
Peak memory 220260 kb
Host smart-badad888-8ecc-44bf-b764-739ccd8099ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054722561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.2054722561
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.2252595513
Short name T750
Test name
Test status
Simulation time 2098010437 ps
CPU time 3.6 seconds
Started May 07 12:54:24 PM PDT 24
Finished May 07 12:54:28 PM PDT 24
Peak memory 203896 kb
Host smart-1b3646fb-3856-4624-8cb1-44a9dba717d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252595513 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.2252595513
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2659870043
Short name T257
Test name
Test status
Simulation time 10549995618 ps
CPU time 6.12 seconds
Started May 07 12:54:24 PM PDT 24
Finished May 07 12:54:31 PM PDT 24
Peak memory 224772 kb
Host smart-75473ff6-d33a-4208-96d5-045fd77648aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659870043 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2659870043
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.569883958
Short name T74
Test name
Test status
Simulation time 10275137021 ps
CPU time 11.55 seconds
Started May 07 12:54:24 PM PDT 24
Finished May 07 12:54:36 PM PDT 24
Peak memory 271948 kb
Host smart-54a0a0dc-5d1c-40f3-989e-aea283ffe72e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569883958 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_fifo_reset_tx.569883958
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.90909634
Short name T446
Test name
Test status
Simulation time 913995184 ps
CPU time 2.75 seconds
Started May 07 12:54:24 PM PDT 24
Finished May 07 12:54:28 PM PDT 24
Peak memory 203928 kb
Host smart-d13cc211-8e3c-407c-8f66-dffd4e9c0fa3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90909634 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.i2c_target_hrst.90909634
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.926212327
Short name T1282
Test name
Test status
Simulation time 5612722050 ps
CPU time 3.93 seconds
Started May 07 12:54:24 PM PDT 24
Finished May 07 12:54:29 PM PDT 24
Peak memory 203972 kb
Host smart-b69fa5fd-3ed4-468e-b9a3-9e1e8224990a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926212327 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_intr_smoke.926212327
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.3122302729
Short name T972
Test name
Test status
Simulation time 29234571621 ps
CPU time 789.74 seconds
Started May 07 12:54:25 PM PDT 24
Finished May 07 01:07:36 PM PDT 24
Peak memory 6938392 kb
Host smart-80c9c8c4-3d4b-40bb-a6a5-b639679a350c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122302729 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.3122302729
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.748764394
Short name T296
Test name
Test status
Simulation time 14728035755 ps
CPU time 60.41 seconds
Started May 07 12:54:20 PM PDT 24
Finished May 07 12:55:21 PM PDT 24
Peak memory 203872 kb
Host smart-f071932e-dcde-4168-ab9a-f5ed6c218e71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748764394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_tar
get_smoke.748764394
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.709864600
Short name T544
Test name
Test status
Simulation time 1732092169 ps
CPU time 29.51 seconds
Started May 07 12:54:21 PM PDT 24
Finished May 07 12:54:51 PM PDT 24
Peak memory 224468 kb
Host smart-4e3e54b3-a4fd-47ef-9106-54399439a421
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709864600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_rd.709864600
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.634690575
Short name T998
Test name
Test status
Simulation time 7263409165 ps
CPU time 13.77 seconds
Started May 07 12:54:18 PM PDT 24
Finished May 07 12:54:33 PM PDT 24
Peak memory 203880 kb
Host smart-4d1620cc-4b70-429c-a7af-10494d6d114f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634690575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_wr.634690575
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.2207495800
Short name T229
Test name
Test status
Simulation time 31683903693 ps
CPU time 658.95 seconds
Started May 07 12:54:23 PM PDT 24
Finished May 07 01:05:22 PM PDT 24
Peak memory 1864204 kb
Host smart-6a591dd4-7cca-44a4-b9c3-1dec767316cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207495800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.2207495800
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.2401372825
Short name T786
Test name
Test status
Simulation time 5383281773 ps
CPU time 7.31 seconds
Started May 07 12:54:24 PM PDT 24
Finished May 07 12:54:32 PM PDT 24
Peak memory 213484 kb
Host smart-b9907c42-0cd9-4790-a896-3bd3fc44dc4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401372825 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.2401372825
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_unexp_stop.27504519
Short name T1018
Test name
Test status
Simulation time 2927405988 ps
CPU time 4.49 seconds
Started May 07 12:54:26 PM PDT 24
Finished May 07 12:54:31 PM PDT 24
Peak memory 204044 kb
Host smart-17ea33e8-f270-437e-b311-e43b3c44d7ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27504519 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_unexp_stop.27504519
Directory /workspace/14.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/15.i2c_alert_test.1447316898
Short name T923
Test name
Test status
Simulation time 52399102 ps
CPU time 0.63 seconds
Started May 07 12:54:40 PM PDT 24
Finished May 07 12:54:43 PM PDT 24
Peak memory 203804 kb
Host smart-3d81782f-40cc-450d-b501-c325eb7378a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447316898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.1447316898
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.4199958554
Short name T639
Test name
Test status
Simulation time 161470879 ps
CPU time 1.27 seconds
Started May 07 12:54:30 PM PDT 24
Finished May 07 12:54:33 PM PDT 24
Peak memory 212184 kb
Host smart-e86498c6-f493-4719-85ab-c4178c4ea93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199958554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.4199958554
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.3642160837
Short name T856
Test name
Test status
Simulation time 896623063 ps
CPU time 11.1 seconds
Started May 07 12:54:36 PM PDT 24
Finished May 07 12:54:48 PM PDT 24
Peak memory 246264 kb
Host smart-a04e4af5-6803-45f4-9db7-13bde1c77403
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642160837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.3642160837
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.1865213398
Short name T60
Test name
Test status
Simulation time 6529367347 ps
CPU time 90.53 seconds
Started May 07 12:54:31 PM PDT 24
Finished May 07 12:56:03 PM PDT 24
Peak memory 505148 kb
Host smart-89e16aa4-744b-49a4-9cf4-148c5309c809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865213398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.1865213398
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.1757855976
Short name T58
Test name
Test status
Simulation time 26536353958 ps
CPU time 138.22 seconds
Started May 07 12:54:33 PM PDT 24
Finished May 07 12:56:52 PM PDT 24
Peak memory 666076 kb
Host smart-6fb72ce0-6628-4868-8beb-8bf0f9ca2258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757855976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.1757855976
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.86099163
Short name T1268
Test name
Test status
Simulation time 219558879 ps
CPU time 1.04 seconds
Started May 07 12:54:32 PM PDT 24
Finished May 07 12:54:34 PM PDT 24
Peak memory 203792 kb
Host smart-3bf3d6b5-10c2-4d24-836a-b9c40146a3d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86099163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fmt
.86099163
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.2145240695
Short name T1318
Test name
Test status
Simulation time 180330273 ps
CPU time 10.48 seconds
Started May 07 12:54:31 PM PDT 24
Finished May 07 12:54:43 PM PDT 24
Peak memory 238100 kb
Host smart-a3f2b902-c76a-4784-82e7-91823150668a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145240695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.2145240695
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.116546294
Short name T792
Test name
Test status
Simulation time 2612667226 ps
CPU time 64.73 seconds
Started May 07 12:54:33 PM PDT 24
Finished May 07 12:55:39 PM PDT 24
Peak memory 763016 kb
Host smart-0159094c-c1e8-4fef-93bc-35235c93d3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116546294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.116546294
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.2663283839
Short name T39
Test name
Test status
Simulation time 1590325803 ps
CPU time 5.27 seconds
Started May 07 12:54:40 PM PDT 24
Finished May 07 12:54:46 PM PDT 24
Peak memory 203856 kb
Host smart-bea5d192-b74e-40c7-8356-ccf9b2cd8b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663283839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.2663283839
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.3823624202
Short name T932
Test name
Test status
Simulation time 1622546483 ps
CPU time 77.94 seconds
Started May 07 12:54:45 PM PDT 24
Finished May 07 12:56:05 PM PDT 24
Peak memory 361716 kb
Host smart-27f414c7-fe54-419b-b3d7-62128e5489de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823624202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.3823624202
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.1154771783
Short name T1059
Test name
Test status
Simulation time 81769564 ps
CPU time 0.68 seconds
Started May 07 12:54:30 PM PDT 24
Finished May 07 12:54:32 PM PDT 24
Peak memory 203608 kb
Host smart-d6cbd992-352d-401b-9433-6f222f2a355a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154771783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1154771783
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.261414972
Short name T452
Test name
Test status
Simulation time 6513151337 ps
CPU time 89.97 seconds
Started May 07 12:54:33 PM PDT 24
Finished May 07 12:56:04 PM PDT 24
Peak memory 212172 kb
Host smart-7b6759c3-ef5c-4219-b298-65845ca5c8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261414972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.261414972
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.438228460
Short name T706
Test name
Test status
Simulation time 918860182 ps
CPU time 38.79 seconds
Started May 07 12:54:31 PM PDT 24
Finished May 07 12:55:11 PM PDT 24
Peak memory 281436 kb
Host smart-74642ce3-02ff-495a-9ca9-6485bd782305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438228460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.438228460
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.428458003
Short name T251
Test name
Test status
Simulation time 9621045003 ps
CPU time 1320.7 seconds
Started May 07 12:54:32 PM PDT 24
Finished May 07 01:16:34 PM PDT 24
Peak memory 2249492 kb
Host smart-f6625760-4840-4900-ac65-1938de402092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428458003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.428458003
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.2509435586
Short name T1206
Test name
Test status
Simulation time 783653179 ps
CPU time 16.71 seconds
Started May 07 12:54:36 PM PDT 24
Finished May 07 12:54:53 PM PDT 24
Peak memory 228296 kb
Host smart-7f984b05-037a-4a31-8184-fe3db563c904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509435586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.2509435586
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.507274579
Short name T1186
Test name
Test status
Simulation time 812703679 ps
CPU time 4.1 seconds
Started May 07 12:54:39 PM PDT 24
Finished May 07 12:54:45 PM PDT 24
Peak memory 212040 kb
Host smart-e5add191-6d9f-4c9d-a242-2daf2cc51a68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507274579 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.507274579
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.305646754
Short name T1254
Test name
Test status
Simulation time 10084505033 ps
CPU time 71.74 seconds
Started May 07 12:54:32 PM PDT 24
Finished May 07 12:55:45 PM PDT 24
Peak memory 428104 kb
Host smart-cbcfe5f7-63b6-431c-b6c6-b4eedbd9cee2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305646754 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_acq.305646754
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.3778485288
Short name T1242
Test name
Test status
Simulation time 10281645571 ps
CPU time 14.96 seconds
Started May 07 12:54:31 PM PDT 24
Finished May 07 12:54:47 PM PDT 24
Peak memory 261828 kb
Host smart-3f23fb4a-555b-4379-b994-d38505a113fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778485288 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.3778485288
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.246577041
Short name T234
Test name
Test status
Simulation time 379760971 ps
CPU time 2.65 seconds
Started May 07 12:54:40 PM PDT 24
Finished May 07 12:54:45 PM PDT 24
Peak memory 203924 kb
Host smart-2139027b-3619-42b6-bff5-ac717eee614c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246577041 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.i2c_target_hrst.246577041
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.2618964064
Short name T313
Test name
Test status
Simulation time 5511017546 ps
CPU time 6.56 seconds
Started May 07 12:54:32 PM PDT 24
Finished May 07 12:54:40 PM PDT 24
Peak memory 220208 kb
Host smart-5ee79bf2-ae02-4c03-a80c-0673d4373b04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618964064 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.2618964064
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.3295355584
Short name T659
Test name
Test status
Simulation time 12535014178 ps
CPU time 218.9 seconds
Started May 07 12:54:32 PM PDT 24
Finished May 07 12:58:12 PM PDT 24
Peak memory 3043684 kb
Host smart-42373f89-94f5-47a3-b3bc-b2cd88253003
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295355584 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.3295355584
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.4092874923
Short name T323
Test name
Test status
Simulation time 1603997584 ps
CPU time 31.24 seconds
Started May 07 12:54:31 PM PDT 24
Finished May 07 12:55:03 PM PDT 24
Peak memory 203888 kb
Host smart-59d0a1de-6108-4388-bbda-4118c8b605e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092874923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.4092874923
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.2839960161
Short name T225
Test name
Test status
Simulation time 1966454019 ps
CPU time 36.91 seconds
Started May 07 12:54:34 PM PDT 24
Finished May 07 12:55:12 PM PDT 24
Peak memory 225132 kb
Host smart-148d4e00-3027-4a7e-b408-1d1718e27ab9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839960161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.2839960161
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.522909324
Short name T1335
Test name
Test status
Simulation time 52695865778 ps
CPU time 1262.3 seconds
Started May 07 12:54:31 PM PDT 24
Finished May 07 01:15:35 PM PDT 24
Peak memory 8330504 kb
Host smart-4565e6fa-c6d4-4b18-9b21-e634e8f0d939
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522909324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_wr.522909324
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.10352828
Short name T295
Test name
Test status
Simulation time 11433999275 ps
CPU time 61.16 seconds
Started May 07 12:54:30 PM PDT 24
Finished May 07 12:55:33 PM PDT 24
Peak memory 796504 kb
Host smart-00df45b0-75d0-4908-8ed2-d314b097cd95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10352828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_stretch.10352828
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.800773366
Short name T383
Test name
Test status
Simulation time 1396511595 ps
CPU time 7.55 seconds
Started May 07 12:54:36 PM PDT 24
Finished May 07 12:54:44 PM PDT 24
Peak memory 212068 kb
Host smart-031b0c11-5bcc-4d36-9d90-e69d6f156233
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800773366 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_timeout.800773366
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.2859223021
Short name T322
Test name
Test status
Simulation time 135367701 ps
CPU time 0.67 seconds
Started May 07 12:54:48 PM PDT 24
Finished May 07 12:54:50 PM PDT 24
Peak memory 203664 kb
Host smart-db16b462-53cb-45be-bf8f-78b68618b2cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859223021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.2859223021
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.2662664031
Short name T1311
Test name
Test status
Simulation time 91253794 ps
CPU time 1.3 seconds
Started May 07 12:54:39 PM PDT 24
Finished May 07 12:54:42 PM PDT 24
Peak memory 212192 kb
Host smart-033a1fcd-62f8-44af-8ea0-d448b14f7a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662664031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.2662664031
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.1444897991
Short name T1040
Test name
Test status
Simulation time 609401751 ps
CPU time 5.63 seconds
Started May 07 12:54:43 PM PDT 24
Finished May 07 12:54:49 PM PDT 24
Peak memory 244836 kb
Host smart-54e1253e-d68c-46c9-bb31-db59bed381ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444897991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.1444897991
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2258972841
Short name T788
Test name
Test status
Simulation time 1569265236 ps
CPU time 54.17 seconds
Started May 07 12:54:40 PM PDT 24
Finished May 07 12:55:35 PM PDT 24
Peak memory 587684 kb
Host smart-83f8e5e7-e806-4155-9c38-8ecff2179023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258972841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2258972841
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.2203523016
Short name T1020
Test name
Test status
Simulation time 1490059564 ps
CPU time 47.69 seconds
Started May 07 12:54:39 PM PDT 24
Finished May 07 12:55:28 PM PDT 24
Peak memory 522460 kb
Host smart-7ee1b2cd-a31b-4258-8108-6ae073bd72e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203523016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.2203523016
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.1390163731
Short name T464
Test name
Test status
Simulation time 392119486 ps
CPU time 0.97 seconds
Started May 07 12:54:38 PM PDT 24
Finished May 07 12:54:39 PM PDT 24
Peak memory 203748 kb
Host smart-bf0cbdea-4db8-4de9-b5e6-76022a145cc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390163731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.1390163731
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.282582330
Short name T605
Test name
Test status
Simulation time 555158838 ps
CPU time 7.76 seconds
Started May 07 12:54:39 PM PDT 24
Finished May 07 12:54:47 PM PDT 24
Peak memory 227792 kb
Host smart-ff56fadb-cb6a-4eba-a905-9649cbc51596
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282582330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.
282582330
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.2822315559
Short name T264
Test name
Test status
Simulation time 4383184570 ps
CPU time 145.01 seconds
Started May 07 12:54:39 PM PDT 24
Finished May 07 12:57:06 PM PDT 24
Peak memory 736352 kb
Host smart-f5fc8148-33ff-44dd-9c6f-8a4cb463594a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822315559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.2822315559
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.2942446735
Short name T577
Test name
Test status
Simulation time 1618468260 ps
CPU time 5.45 seconds
Started May 07 12:54:46 PM PDT 24
Finished May 07 12:54:53 PM PDT 24
Peak memory 203912 kb
Host smart-6531e124-ec14-4d4d-80f8-9a8ac328e2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942446735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.2942446735
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.3754030914
Short name T673
Test name
Test status
Simulation time 6972907538 ps
CPU time 76.66 seconds
Started May 07 12:54:45 PM PDT 24
Finished May 07 12:56:03 PM PDT 24
Peak memory 325440 kb
Host smart-4f197167-606a-4485-9022-bed9a6fa6853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754030914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.3754030914
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.2592461547
Short name T207
Test name
Test status
Simulation time 54778682 ps
CPU time 0.68 seconds
Started May 07 12:54:40 PM PDT 24
Finished May 07 12:54:42 PM PDT 24
Peak memory 203692 kb
Host smart-bb5ff694-2de7-465a-aff5-1396e45beae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592461547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.2592461547
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.3541515025
Short name T309
Test name
Test status
Simulation time 26605494111 ps
CPU time 1224.9 seconds
Started May 07 12:54:40 PM PDT 24
Finished May 07 01:15:06 PM PDT 24
Peak memory 345296 kb
Host smart-d07fe8e3-5fa9-4833-902e-ebf6bc6ee9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541515025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.3541515025
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.2677900209
Short name T652
Test name
Test status
Simulation time 1078918223 ps
CPU time 49.45 seconds
Started May 07 12:54:38 PM PDT 24
Finished May 07 12:55:28 PM PDT 24
Peak memory 281388 kb
Host smart-4e833721-bb72-462d-90c5-bb4b22ba896b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677900209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.2677900209
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.258863746
Short name T256
Test name
Test status
Simulation time 30069976498 ps
CPU time 447.85 seconds
Started May 07 12:54:39 PM PDT 24
Finished May 07 01:02:09 PM PDT 24
Peak memory 853072 kb
Host smart-41a48fbe-ff33-4884-910e-33529f8734cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258863746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.258863746
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.486954730
Short name T1111
Test name
Test status
Simulation time 724065227 ps
CPU time 33.06 seconds
Started May 07 12:54:39 PM PDT 24
Finished May 07 12:55:14 PM PDT 24
Peak memory 212144 kb
Host smart-5d98267e-f91e-48de-8d15-31d815ece01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486954730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.486954730
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.2722352983
Short name T1082
Test name
Test status
Simulation time 441374873 ps
CPU time 2.99 seconds
Started May 07 12:54:47 PM PDT 24
Finished May 07 12:54:51 PM PDT 24
Peak memory 203844 kb
Host smart-f0602ba3-f1d0-40da-8e44-7f3c8fbe8900
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722352983 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.2722352983
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.3001900449
Short name T818
Test name
Test status
Simulation time 10091888337 ps
CPU time 69.71 seconds
Started May 07 12:54:47 PM PDT 24
Finished May 07 12:55:58 PM PDT 24
Peak memory 429264 kb
Host smart-656d0137-59f0-4c71-abc0-9e74219367ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001900449 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.3001900449
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.1123484346
Short name T431
Test name
Test status
Simulation time 10195912400 ps
CPU time 13.15 seconds
Started May 07 12:54:48 PM PDT 24
Finished May 07 12:55:02 PM PDT 24
Peak memory 282700 kb
Host smart-51f3b014-5515-4093-9ebe-b30de2627950
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123484346 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.1123484346
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.1395584315
Short name T927
Test name
Test status
Simulation time 825741629 ps
CPU time 2.56 seconds
Started May 07 12:54:45 PM PDT 24
Finished May 07 12:54:49 PM PDT 24
Peak memory 203908 kb
Host smart-0400f745-21fc-4bfe-92da-f0f180ff620a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395584315 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.1395584315
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.1036658055
Short name T976
Test name
Test status
Simulation time 1912540267 ps
CPU time 4.62 seconds
Started May 07 12:54:40 PM PDT 24
Finished May 07 12:54:46 PM PDT 24
Peak memory 203940 kb
Host smart-96866858-caa3-41a3-8350-f844473bea50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036658055 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.1036658055
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.2289598933
Short name T111
Test name
Test status
Simulation time 4886495227 ps
CPU time 4.92 seconds
Started May 07 12:54:41 PM PDT 24
Finished May 07 12:54:47 PM PDT 24
Peak memory 203988 kb
Host smart-af46fc00-28d7-415d-b3c7-6257d3c2cfec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289598933 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.2289598933
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.1689786209
Short name T500
Test name
Test status
Simulation time 956738751 ps
CPU time 39.85 seconds
Started May 07 12:54:38 PM PDT 24
Finished May 07 12:55:18 PM PDT 24
Peak memory 203868 kb
Host smart-31d43a08-1121-4239-8167-20f324948cc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689786209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.1689786209
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.91021795
Short name T877
Test name
Test status
Simulation time 1795833847 ps
CPU time 14.52 seconds
Started May 07 12:54:39 PM PDT 24
Finished May 07 12:54:55 PM PDT 24
Peak memory 212688 kb
Host smart-671b2b10-a69c-40ab-8a4e-7df586db3c5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91021795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stress_rd.91021795
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.2980564589
Short name T1057
Test name
Test status
Simulation time 26813420921 ps
CPU time 5.71 seconds
Started May 07 12:54:38 PM PDT 24
Finished May 07 12:54:45 PM PDT 24
Peak memory 203920 kb
Host smart-2e73b73c-93d8-4b25-b7b8-8e3f99e8a107
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980564589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.2980564589
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.873020146
Short name T232
Test name
Test status
Simulation time 18626560326 ps
CPU time 295.28 seconds
Started May 07 12:54:39 PM PDT 24
Finished May 07 12:59:36 PM PDT 24
Peak memory 2206944 kb
Host smart-cb0f1210-5006-4bf1-98c5-6e4f06f76eb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873020146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_t
arget_stretch.873020146
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.3183450072
Short name T197
Test name
Test status
Simulation time 1332816882 ps
CPU time 7.68 seconds
Started May 07 12:54:40 PM PDT 24
Finished May 07 12:54:48 PM PDT 24
Peak memory 220120 kb
Host smart-081432ff-895c-46b5-a1eb-421de9f65f13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183450072 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.3183450072
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_unexp_stop.260056056
Short name T402
Test name
Test status
Simulation time 10295468712 ps
CPU time 6.06 seconds
Started May 07 12:54:45 PM PDT 24
Finished May 07 12:54:53 PM PDT 24
Peak memory 204520 kb
Host smart-f6851f2a-8fa6-4cbf-8704-bea16184dddb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260056056 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_unexp_stop.260056056
Directory /workspace/16.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/17.i2c_alert_test.1473740045
Short name T1081
Test name
Test status
Simulation time 70468630 ps
CPU time 0.6 seconds
Started May 07 12:54:51 PM PDT 24
Finished May 07 12:54:53 PM PDT 24
Peak memory 203796 kb
Host smart-f54245ee-4253-4e5c-98a1-ea8c303d97ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473740045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.1473740045
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.3395115113
Short name T637
Test name
Test status
Simulation time 75553654 ps
CPU time 1.3 seconds
Started May 07 12:54:52 PM PDT 24
Finished May 07 12:54:55 PM PDT 24
Peak memory 212180 kb
Host smart-be11da07-b69e-486a-b3ff-cf4c83b28669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395115113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3395115113
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.3579346566
Short name T348
Test name
Test status
Simulation time 229371278 ps
CPU time 11.82 seconds
Started May 07 12:54:46 PM PDT 24
Finished May 07 12:55:00 PM PDT 24
Peak memory 246872 kb
Host smart-fd42db75-7aa9-4d02-a82c-b62f68621b9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579346566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.3579346566
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.3746673174
Short name T892
Test name
Test status
Simulation time 1434517801 ps
CPU time 31.84 seconds
Started May 07 12:54:51 PM PDT 24
Finished May 07 12:55:24 PM PDT 24
Peak memory 212152 kb
Host smart-21e2d44a-8b07-4cb0-9fdc-c5426d335136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746673174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3746673174
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.2821748336
Short name T971
Test name
Test status
Simulation time 7247822042 ps
CPU time 128.07 seconds
Started May 07 12:54:45 PM PDT 24
Finished May 07 12:56:55 PM PDT 24
Peak memory 654572 kb
Host smart-05b88324-bb20-4e69-9cf6-5cccf9ce0362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821748336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2821748336
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.657749360
Short name T441
Test name
Test status
Simulation time 330350589 ps
CPU time 1.2 seconds
Started May 07 12:54:47 PM PDT 24
Finished May 07 12:54:50 PM PDT 24
Peak memory 203816 kb
Host smart-eb696550-373a-4ec2-9cf8-f58a8bd1465e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657749360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fm
t.657749360
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.1471774782
Short name T830
Test name
Test status
Simulation time 639756615 ps
CPU time 4.47 seconds
Started May 07 12:54:48 PM PDT 24
Finished May 07 12:54:54 PM PDT 24
Peak memory 203760 kb
Host smart-eb784164-85b8-413e-b4ff-dce9aa016550
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471774782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.1471774782
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.2851063752
Short name T941
Test name
Test status
Simulation time 14357504587 ps
CPU time 108.36 seconds
Started May 07 12:54:45 PM PDT 24
Finished May 07 12:56:35 PM PDT 24
Peak memory 1099012 kb
Host smart-fca1e90b-9506-470a-a858-0c3b9518e8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851063752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2851063752
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.345555566
Short name T604
Test name
Test status
Simulation time 398340399 ps
CPU time 5.3 seconds
Started May 07 12:54:51 PM PDT 24
Finished May 07 12:54:57 PM PDT 24
Peak memory 203888 kb
Host smart-59a77184-e438-48c7-bee8-aa99608f2914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345555566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.345555566
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.3341922438
Short name T681
Test name
Test status
Simulation time 5229101483 ps
CPU time 64.91 seconds
Started May 07 12:55:02 PM PDT 24
Finished May 07 12:56:08 PM PDT 24
Peak memory 370724 kb
Host smart-f1ea3f9c-4d08-428b-9904-f00ce07f4439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341922438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.3341922438
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.4245976810
Short name T894
Test name
Test status
Simulation time 26296558 ps
CPU time 0.68 seconds
Started May 07 12:54:47 PM PDT 24
Finished May 07 12:54:49 PM PDT 24
Peak memory 203708 kb
Host smart-db79e991-2595-4250-b5ff-965bfa6f2032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245976810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.4245976810
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.415871269
Short name T815
Test name
Test status
Simulation time 49789109996 ps
CPU time 618.1 seconds
Started May 07 12:54:49 PM PDT 24
Finished May 07 01:05:09 PM PDT 24
Peak memory 204000 kb
Host smart-07d470d0-9b77-4358-a757-5f89a61d03a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415871269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.415871269
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.1939744776
Short name T1289
Test name
Test status
Simulation time 18304029391 ps
CPU time 27.18 seconds
Started May 07 12:54:46 PM PDT 24
Finished May 07 12:55:15 PM PDT 24
Peak memory 305860 kb
Host smart-a16dd4ce-42d4-4130-9431-f91407022238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939744776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.1939744776
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.3993945830
Short name T384
Test name
Test status
Simulation time 8060786814 ps
CPU time 436.84 seconds
Started May 07 12:54:52 PM PDT 24
Finished May 07 01:02:10 PM PDT 24
Peak memory 1644672 kb
Host smart-51cffa0d-46c3-4369-97fd-d0acd4457127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993945830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.3993945830
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.1316830888
Short name T366
Test name
Test status
Simulation time 2924061740 ps
CPU time 34.69 seconds
Started May 07 12:54:50 PM PDT 24
Finished May 07 12:55:26 PM PDT 24
Peak memory 213360 kb
Host smart-4f2e31f4-e509-4c4c-81a6-dfff3be47df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316830888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.1316830888
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.3749704475
Short name T417
Test name
Test status
Simulation time 1833218411 ps
CPU time 4.49 seconds
Started May 07 12:55:02 PM PDT 24
Finished May 07 12:55:08 PM PDT 24
Peak memory 212100 kb
Host smart-d422d112-1787-4306-8638-82a81fff322c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749704475 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.3749704475
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.2231694262
Short name T697
Test name
Test status
Simulation time 10257017723 ps
CPU time 24.68 seconds
Started May 07 12:55:02 PM PDT 24
Finished May 07 12:55:28 PM PDT 24
Peak memory 302216 kb
Host smart-6d09c1fc-6bf5-4b7c-a818-774b3039fee3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231694262 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.2231694262
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.2009789536
Short name T410
Test name
Test status
Simulation time 10256999970 ps
CPU time 13.52 seconds
Started May 07 12:54:50 PM PDT 24
Finished May 07 12:55:05 PM PDT 24
Peak memory 254800 kb
Host smart-174ebaec-43ba-4ab0-99ae-ad476f9b76ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009789536 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.2009789536
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.1591586933
Short name T930
Test name
Test status
Simulation time 369479020 ps
CPU time 2.44 seconds
Started May 07 12:54:50 PM PDT 24
Finished May 07 12:54:54 PM PDT 24
Peak memory 203864 kb
Host smart-7bc46941-1033-41b1-acbe-a0ca42cd9ff2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591586933 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.1591586933
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.3231138059
Short name T1140
Test name
Test status
Simulation time 1315016420 ps
CPU time 7.24 seconds
Started May 07 12:54:50 PM PDT 24
Finished May 07 12:54:59 PM PDT 24
Peak memory 212124 kb
Host smart-af8a385f-8051-4042-9d05-21d4275a9980
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231138059 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.3231138059
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.3628614069
Short name T530
Test name
Test status
Simulation time 7816108267 ps
CPU time 9.77 seconds
Started May 07 12:54:50 PM PDT 24
Finished May 07 12:55:01 PM PDT 24
Peak memory 203992 kb
Host smart-3df48b78-7981-4b90-b3d5-f03a0ce0b8f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628614069 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.3628614069
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.2059362560
Short name T790
Test name
Test status
Simulation time 782851529 ps
CPU time 24.31 seconds
Started May 07 12:54:53 PM PDT 24
Finished May 07 12:55:18 PM PDT 24
Peak memory 203744 kb
Host smart-b3bae975-076c-46aa-b283-5bf9d97d9906
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059362560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.2059362560
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.398857620
Short name T37
Test name
Test status
Simulation time 3913839012 ps
CPU time 64.71 seconds
Started May 07 12:55:02 PM PDT 24
Finished May 07 12:56:07 PM PDT 24
Peak memory 207848 kb
Host smart-294f1587-5f52-49df-af8e-a30afd4554b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398857620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_rd.398857620
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.84969465
Short name T647
Test name
Test status
Simulation time 47748415585 ps
CPU time 8.92 seconds
Started May 07 12:55:02 PM PDT 24
Finished May 07 12:55:12 PM PDT 24
Peak memory 231252 kb
Host smart-9efdf265-176e-43a7-b4e2-21cacc86c06a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84969465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stress_wr.84969465
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.3805169582
Short name T423
Test name
Test status
Simulation time 27651025107 ps
CPU time 1454.03 seconds
Started May 07 12:55:03 PM PDT 24
Finished May 07 01:19:18 PM PDT 24
Peak memory 3168040 kb
Host smart-716b3c5f-7133-4c1f-b61c-ea0a1a8eb9f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805169582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.3805169582
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.837969225
Short name T1359
Test name
Test status
Simulation time 1541794005 ps
CPU time 7.25 seconds
Started May 07 12:54:52 PM PDT 24
Finished May 07 12:55:01 PM PDT 24
Peak memory 203792 kb
Host smart-df7043d9-7bb3-4f6b-8996-81c56d734353
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837969225 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_timeout.837969225
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.4212661747
Short name T833
Test name
Test status
Simulation time 38653648 ps
CPU time 0.61 seconds
Started May 07 12:55:06 PM PDT 24
Finished May 07 12:55:07 PM PDT 24
Peak memory 203784 kb
Host smart-a7ada8bb-f6ba-454e-afa8-b1a67c197df9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212661747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.4212661747
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.3273308507
Short name T435
Test name
Test status
Simulation time 654527393 ps
CPU time 1.72 seconds
Started May 07 12:54:57 PM PDT 24
Finished May 07 12:55:00 PM PDT 24
Peak memory 212228 kb
Host smart-d70ef883-b8d6-40e0-8b5c-b5e576f4c76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273308507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.3273308507
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.3637610038
Short name T201
Test name
Test status
Simulation time 515791184 ps
CPU time 27.73 seconds
Started May 07 12:54:58 PM PDT 24
Finished May 07 12:55:27 PM PDT 24
Peak memory 315600 kb
Host smart-203ba11a-43c2-4dbd-9696-101de06658d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637610038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.3637610038
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.2085989584
Short name T904
Test name
Test status
Simulation time 3730505918 ps
CPU time 51.69 seconds
Started May 07 12:54:59 PM PDT 24
Finished May 07 12:55:52 PM PDT 24
Peak memory 581436 kb
Host smart-97a8effc-6a00-48b8-914d-5edfe8310f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085989584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.2085989584
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.117608718
Short name T1085
Test name
Test status
Simulation time 1766522877 ps
CPU time 117.17 seconds
Started May 07 12:55:01 PM PDT 24
Finished May 07 12:56:59 PM PDT 24
Peak memory 593552 kb
Host smart-db329b10-6e97-47c5-b7c4-bc66b3718bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117608718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.117608718
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.4219308491
Short name T535
Test name
Test status
Simulation time 206028713 ps
CPU time 0.86 seconds
Started May 07 12:54:58 PM PDT 24
Finished May 07 12:54:59 PM PDT 24
Peak memory 203772 kb
Host smart-bb1bfc5e-e4fb-416a-af11-6dd886c9a260
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219308491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.4219308491
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.369022356
Short name T421
Test name
Test status
Simulation time 183948769 ps
CPU time 2.67 seconds
Started May 07 12:54:59 PM PDT 24
Finished May 07 12:55:03 PM PDT 24
Peak memory 203904 kb
Host smart-cad24815-a182-4219-b8d4-688c4c3dd0ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369022356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.
369022356
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.3808194462
Short name T1211
Test name
Test status
Simulation time 15454653420 ps
CPU time 92.51 seconds
Started May 07 12:54:57 PM PDT 24
Finished May 07 12:56:31 PM PDT 24
Peak memory 1128672 kb
Host smart-85f19b2d-06b2-47ea-a7d0-e59d38e46cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808194462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.3808194462
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.1153413332
Short name T884
Test name
Test status
Simulation time 433534831 ps
CPU time 5.83 seconds
Started May 07 12:55:05 PM PDT 24
Finished May 07 12:55:12 PM PDT 24
Peak memory 203936 kb
Host smart-e2349d12-7518-4845-948d-befa52aa36e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153413332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.1153413332
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_override.1107528758
Short name T610
Test name
Test status
Simulation time 309790248 ps
CPU time 0.68 seconds
Started May 07 12:54:53 PM PDT 24
Finished May 07 12:54:54 PM PDT 24
Peak memory 203584 kb
Host smart-e6bcba1f-217b-4854-99e5-50c25eca2157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107528758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.1107528758
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.3141039305
Short name T358
Test name
Test status
Simulation time 27340210567 ps
CPU time 652.78 seconds
Started May 07 12:54:57 PM PDT 24
Finished May 07 01:05:51 PM PDT 24
Peak memory 2685956 kb
Host smart-84308576-1959-4886-a9a5-774f65264959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141039305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.3141039305
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.2970590140
Short name T490
Test name
Test status
Simulation time 4167095464 ps
CPU time 21.36 seconds
Started May 07 12:55:03 PM PDT 24
Finished May 07 12:55:25 PM PDT 24
Peak memory 281072 kb
Host smart-210acff2-cce7-4694-9e5e-b866b265dc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970590140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2970590140
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.1804235721
Short name T252
Test name
Test status
Simulation time 56437639792 ps
CPU time 1354.42 seconds
Started May 07 12:55:00 PM PDT 24
Finished May 07 01:17:35 PM PDT 24
Peak memory 1536712 kb
Host smart-b593d115-d22a-4ab8-b666-cc9c5a9749ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804235721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.1804235721
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.189660490
Short name T458
Test name
Test status
Simulation time 1029584107 ps
CPU time 8.9 seconds
Started May 07 12:54:57 PM PDT 24
Finished May 07 12:55:07 PM PDT 24
Peak memory 220244 kb
Host smart-194c8a87-7885-49ea-a568-b54e2e72a675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189660490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.189660490
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.2377826779
Short name T995
Test name
Test status
Simulation time 1878152025 ps
CPU time 2.6 seconds
Started May 07 12:54:58 PM PDT 24
Finished May 07 12:55:03 PM PDT 24
Peak memory 203952 kb
Host smart-a79b0867-2837-4dc3-ba67-2744955ae9fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377826779 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.2377826779
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.28043391
Short name T791
Test name
Test status
Simulation time 10079626916 ps
CPU time 31.17 seconds
Started May 07 12:54:58 PM PDT 24
Finished May 07 12:55:30 PM PDT 24
Peak memory 334872 kb
Host smart-7ed522a5-ebdc-4060-af32-7beaa1c9f8f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28043391 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_fifo_reset_acq.28043391
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.1193354767
Short name T100
Test name
Test status
Simulation time 10077773156 ps
CPU time 30.34 seconds
Started May 07 12:54:59 PM PDT 24
Finished May 07 12:55:31 PM PDT 24
Peak memory 406396 kb
Host smart-bf3cf463-036d-4fdb-a0e3-33a4ad0c2d2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193354767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.1193354767
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.824441317
Short name T533
Test name
Test status
Simulation time 386546885 ps
CPU time 2.51 seconds
Started May 07 12:55:06 PM PDT 24
Finished May 07 12:55:10 PM PDT 24
Peak memory 203904 kb
Host smart-c05f1c88-eeed-41fe-b8e7-9484e47c9eb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824441317 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 18.i2c_target_hrst.824441317
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.3872398642
Short name T1002
Test name
Test status
Simulation time 1403904066 ps
CPU time 4.24 seconds
Started May 07 12:54:58 PM PDT 24
Finished May 07 12:55:03 PM PDT 24
Peak memory 203952 kb
Host smart-62d3396c-3e96-4bba-b0d9-fae4a3dd0c70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872398642 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.3872398642
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.67231252
Short name T752
Test name
Test status
Simulation time 9476138582 ps
CPU time 21.33 seconds
Started May 07 12:55:01 PM PDT 24
Finished May 07 12:55:24 PM PDT 24
Peak memory 664580 kb
Host smart-a3cfde91-b4a5-44f1-b535-f04878c254f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67231252 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.67231252
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.3591183513
Short name T1189
Test name
Test status
Simulation time 2208419125 ps
CPU time 9.63 seconds
Started May 07 12:54:59 PM PDT 24
Finished May 07 12:55:10 PM PDT 24
Peak memory 203980 kb
Host smart-edd2c67d-2197-4825-a4b1-272c82021e00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591183513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.3591183513
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.401857260
Short name T492
Test name
Test status
Simulation time 1232315571 ps
CPU time 22.56 seconds
Started May 07 12:54:57 PM PDT 24
Finished May 07 12:55:20 PM PDT 24
Peak memory 222176 kb
Host smart-c298a5af-4bed-48b0-9e49-0aca44cecf27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401857260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_rd.401857260
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.70586814
Short name T793
Test name
Test status
Simulation time 34263619684 ps
CPU time 100.08 seconds
Started May 07 12:54:59 PM PDT 24
Finished May 07 12:56:40 PM PDT 24
Peak memory 1572604 kb
Host smart-51e84d1c-f376-442a-b168-f58b84bc7d97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70586814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stress_wr.70586814
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.3209584074
Short name T299
Test name
Test status
Simulation time 34827092831 ps
CPU time 232.71 seconds
Started May 07 12:54:58 PM PDT 24
Finished May 07 12:58:52 PM PDT 24
Peak memory 856720 kb
Host smart-ca3536d2-7e5e-469e-9b37-722f54090b44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209584074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.3209584074
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.1771018548
Short name T664
Test name
Test status
Simulation time 1313924192 ps
CPU time 7.77 seconds
Started May 07 12:55:00 PM PDT 24
Finished May 07 12:55:08 PM PDT 24
Peak memory 211032 kb
Host smart-a748912d-f563-450b-ad84-23f3713fa175
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771018548 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.1771018548
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2019088587
Short name T1279
Test name
Test status
Simulation time 33712126 ps
CPU time 0.61 seconds
Started May 07 12:55:17 PM PDT 24
Finished May 07 12:55:19 PM PDT 24
Peak memory 203792 kb
Host smart-aa7d2094-a544-42e4-a904-8201db53b5c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019088587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2019088587
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.2868265265
Short name T560
Test name
Test status
Simulation time 499184039 ps
CPU time 1.61 seconds
Started May 07 12:55:05 PM PDT 24
Finished May 07 12:55:07 PM PDT 24
Peak memory 212188 kb
Host smart-6496b659-4eb2-487e-9691-a0512c6b1af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868265265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.2868265265
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.2148731387
Short name T1075
Test name
Test status
Simulation time 287835021 ps
CPU time 6.62 seconds
Started May 07 12:55:06 PM PDT 24
Finished May 07 12:55:14 PM PDT 24
Peak memory 260008 kb
Host smart-26f994b2-bd84-47b6-9c08-30c9a735cc7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148731387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.2148731387
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.242880563
Short name T829
Test name
Test status
Simulation time 2948269475 ps
CPU time 96.68 seconds
Started May 07 12:55:07 PM PDT 24
Finished May 07 12:56:44 PM PDT 24
Peak memory 431428 kb
Host smart-bfd06c93-5299-464e-92fc-a39222e9d95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242880563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.242880563
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.3068560655
Short name T628
Test name
Test status
Simulation time 3338630132 ps
CPU time 55.14 seconds
Started May 07 12:55:05 PM PDT 24
Finished May 07 12:56:01 PM PDT 24
Peak memory 603456 kb
Host smart-e9deb134-854b-4504-8cb3-9029a8888af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068560655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.3068560655
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.4215774330
Short name T480
Test name
Test status
Simulation time 119917931 ps
CPU time 1.17 seconds
Started May 07 12:55:07 PM PDT 24
Finished May 07 12:55:09 PM PDT 24
Peak memory 203848 kb
Host smart-212ff5aa-f182-4c8e-83d5-ffcb3ebddb26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215774330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.4215774330
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.916954014
Short name T413
Test name
Test status
Simulation time 176334983 ps
CPU time 3.86 seconds
Started May 07 12:55:08 PM PDT 24
Finished May 07 12:55:13 PM PDT 24
Peak memory 203868 kb
Host smart-ead46f71-4813-4973-af9e-b609280912cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916954014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.
916954014
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.2365366778
Short name T751
Test name
Test status
Simulation time 14349980166 ps
CPU time 172.25 seconds
Started May 07 12:55:06 PM PDT 24
Finished May 07 12:57:59 PM PDT 24
Peak memory 822552 kb
Host smart-a8cb6f1e-68e3-40ae-b1f2-0991520d4657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365366778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.2365366778
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.666181840
Short name T1037
Test name
Test status
Simulation time 335030830 ps
CPU time 4.32 seconds
Started May 07 12:55:14 PM PDT 24
Finished May 07 12:55:20 PM PDT 24
Peak memory 203848 kb
Host smart-cd8cf067-247e-4886-a121-f51c6c4ca964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666181840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.666181840
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.2277473409
Short name T1329
Test name
Test status
Simulation time 2293651338 ps
CPU time 52.04 seconds
Started May 07 12:55:16 PM PDT 24
Finished May 07 12:56:10 PM PDT 24
Peak memory 462828 kb
Host smart-cce3bef9-b1fa-43ba-bd8d-c3f0e18647a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277473409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.2277473409
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.3797026700
Short name T819
Test name
Test status
Simulation time 90110783 ps
CPU time 0.67 seconds
Started May 07 12:55:06 PM PDT 24
Finished May 07 12:55:08 PM PDT 24
Peak memory 203716 kb
Host smart-4e54be3b-b7ca-4587-a829-2fc3a1744a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797026700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.3797026700
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.1764999757
Short name T783
Test name
Test status
Simulation time 12695807228 ps
CPU time 123.65 seconds
Started May 07 12:55:05 PM PDT 24
Finished May 07 12:57:09 PM PDT 24
Peak memory 212036 kb
Host smart-81f789cf-ec80-4f8b-b2b5-a895dae3cd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764999757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.1764999757
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.3306415145
Short name T502
Test name
Test status
Simulation time 3812769644 ps
CPU time 15.2 seconds
Started May 07 12:55:05 PM PDT 24
Finished May 07 12:55:21 PM PDT 24
Peak memory 268400 kb
Host smart-6b084450-25ea-42b2-8a52-03b7902225ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306415145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.3306415145
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.95109324
Short name T1225
Test name
Test status
Simulation time 5119431779 ps
CPU time 149.19 seconds
Started May 07 12:55:13 PM PDT 24
Finished May 07 12:57:44 PM PDT 24
Peak memory 1166484 kb
Host smart-043b227f-a272-4fc6-9cb5-0d30476c4528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95109324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.95109324
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.4079169375
Short name T1102
Test name
Test status
Simulation time 1890955644 ps
CPU time 8.45 seconds
Started May 07 12:55:09 PM PDT 24
Finished May 07 12:55:18 PM PDT 24
Peak memory 220192 kb
Host smart-501fc370-c458-4541-84f1-0cba8fed9f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079169375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.4079169375
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.740982165
Short name T539
Test name
Test status
Simulation time 1003433483 ps
CPU time 4.98 seconds
Started May 07 12:55:15 PM PDT 24
Finished May 07 12:55:21 PM PDT 24
Peak memory 204056 kb
Host smart-3ecbf19b-14fb-4ce9-b40c-efbfe6d9afcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740982165 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.740982165
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.3077373375
Short name T564
Test name
Test status
Simulation time 10140156526 ps
CPU time 12.55 seconds
Started May 07 12:55:15 PM PDT 24
Finished May 07 12:55:29 PM PDT 24
Peak memory 256684 kb
Host smart-c1bbb104-ed6b-45b7-8870-8257dff13048
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077373375 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.3077373375
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.3484186840
Short name T552
Test name
Test status
Simulation time 10043869170 ps
CPU time 69.03 seconds
Started May 07 12:55:12 PM PDT 24
Finished May 07 12:56:22 PM PDT 24
Peak memory 469052 kb
Host smart-669c3dad-66f4-410f-a656-83ba34871a16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484186840 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.3484186840
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.2832204493
Short name T556
Test name
Test status
Simulation time 383202706 ps
CPU time 2.64 seconds
Started May 07 12:55:13 PM PDT 24
Finished May 07 12:55:17 PM PDT 24
Peak memory 203868 kb
Host smart-37573006-4075-4951-9bf1-543c78d23a03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832204493 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.2832204493
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.1267489493
Short name T650
Test name
Test status
Simulation time 1048043189 ps
CPU time 5.44 seconds
Started May 07 12:55:11 PM PDT 24
Finished May 07 12:55:17 PM PDT 24
Peak memory 203904 kb
Host smart-dcaac14b-1507-4be2-b9fe-d98d2e3cc4c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267489493 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.1267489493
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.1342892129
Short name T984
Test name
Test status
Simulation time 7355459661 ps
CPU time 16.35 seconds
Started May 07 12:55:17 PM PDT 24
Finished May 07 12:55:35 PM PDT 24
Peak memory 264840 kb
Host smart-b3440487-504c-43d2-8edb-f7e5fd797830
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342892129 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.1342892129
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.693683728
Short name T1284
Test name
Test status
Simulation time 2994286501 ps
CPU time 10.96 seconds
Started May 07 12:55:15 PM PDT 24
Finished May 07 12:55:27 PM PDT 24
Peak memory 203984 kb
Host smart-40db67c7-ad17-4aad-9c55-4daad69b7f2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693683728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_tar
get_smoke.693683728
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.348587629
Short name T349
Test name
Test status
Simulation time 808536221 ps
CPU time 15.06 seconds
Started May 07 12:55:11 PM PDT 24
Finished May 07 12:55:27 PM PDT 24
Peak memory 209772 kb
Host smart-4b4741dd-65b8-4516-9771-522ae41904b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348587629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c
_target_stress_rd.348587629
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.3059997644
Short name T428
Test name
Test status
Simulation time 31565700567 ps
CPU time 261.5 seconds
Started May 07 12:55:16 PM PDT 24
Finished May 07 12:59:40 PM PDT 24
Peak memory 2986056 kb
Host smart-0e7526fb-bf4d-481f-92c9-7197efc38be5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059997644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.3059997644
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.3559714564
Short name T831
Test name
Test status
Simulation time 30574343923 ps
CPU time 2346.34 seconds
Started May 07 12:55:16 PM PDT 24
Finished May 07 01:34:24 PM PDT 24
Peak memory 7029628 kb
Host smart-a9fda0a6-e518-43ab-a4e2-69d0a1596a50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559714564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.3559714564
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.363698702
Short name T424
Test name
Test status
Simulation time 1243074891 ps
CPU time 7.11 seconds
Started May 07 12:55:10 PM PDT 24
Finished May 07 12:55:18 PM PDT 24
Peak memory 220108 kb
Host smart-cdbe8219-4916-4a54-8312-cde44b396329
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363698702 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_timeout.363698702
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.1298154883
Short name T1272
Test name
Test status
Simulation time 17916534 ps
CPU time 0.65 seconds
Started May 07 12:52:27 PM PDT 24
Finished May 07 12:52:29 PM PDT 24
Peak memory 203772 kb
Host smart-938f2f31-83ec-4c50-a892-39d3bc66ad7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298154883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.1298154883
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1835248913
Short name T1080
Test name
Test status
Simulation time 215089982 ps
CPU time 1.36 seconds
Started May 07 12:52:17 PM PDT 24
Finished May 07 12:52:19 PM PDT 24
Peak memory 212232 kb
Host smart-4d84b8bf-7fb9-40cf-a192-e0f3554e3da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835248913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1835248913
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.690296294
Short name T1036
Test name
Test status
Simulation time 445079543 ps
CPU time 7.92 seconds
Started May 07 12:52:11 PM PDT 24
Finished May 07 12:52:21 PM PDT 24
Peak memory 274736 kb
Host smart-9f2f1ca6-ce0f-4d58-859a-5cf2c6e68235
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690296294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty
.690296294
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.1287276616
Short name T844
Test name
Test status
Simulation time 10164627442 ps
CPU time 186.81 seconds
Started May 07 12:52:18 PM PDT 24
Finished May 07 12:55:26 PM PDT 24
Peak memory 784196 kb
Host smart-eaf87bbc-44d5-4723-8f09-e2a2b2cc819d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287276616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.1287276616
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.2572883606
Short name T686
Test name
Test status
Simulation time 10488408068 ps
CPU time 76.33 seconds
Started May 07 12:52:10 PM PDT 24
Finished May 07 12:53:28 PM PDT 24
Peak memory 696268 kb
Host smart-ddb034d8-eeb8-4558-98ef-66052a0fb3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572883606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.2572883606
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.3432025393
Short name T562
Test name
Test status
Simulation time 604209801 ps
CPU time 1.18 seconds
Started May 07 12:52:12 PM PDT 24
Finished May 07 12:52:15 PM PDT 24
Peak memory 203892 kb
Host smart-b3de7d7f-01ad-401a-963f-257afd3e6901
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432025393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.3432025393
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3064876259
Short name T934
Test name
Test status
Simulation time 317954039 ps
CPU time 3.46 seconds
Started May 07 12:52:20 PM PDT 24
Finished May 07 12:52:24 PM PDT 24
Peak memory 203876 kb
Host smart-d58a5910-d022-4179-99bf-d05ad16b841d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064876259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3064876259
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.535400868
Short name T541
Test name
Test status
Simulation time 6261709758 ps
CPU time 286.56 seconds
Started May 07 12:52:12 PM PDT 24
Finished May 07 12:57:00 PM PDT 24
Peak memory 1137340 kb
Host smart-86d3fc97-4ae2-4507-8e6e-78967d59fac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535400868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.535400868
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.209417591
Short name T688
Test name
Test status
Simulation time 1005716666 ps
CPU time 3.67 seconds
Started May 07 12:52:24 PM PDT 24
Finished May 07 12:52:29 PM PDT 24
Peak memory 203844 kb
Host smart-32faf108-9468-4ed3-bfff-8e571c1c8dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209417591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.209417591
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_override.288027964
Short name T731
Test name
Test status
Simulation time 15194313 ps
CPU time 0.66 seconds
Started May 07 12:52:11 PM PDT 24
Finished May 07 12:52:13 PM PDT 24
Peak memory 203744 kb
Host smart-f5e6b946-4f18-492c-8b54-08adae4794e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288027964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.288027964
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.3639591694
Short name T1230
Test name
Test status
Simulation time 52210476609 ps
CPU time 505.64 seconds
Started May 07 12:52:20 PM PDT 24
Finished May 07 01:00:47 PM PDT 24
Peak memory 204000 kb
Host smart-d8c522a5-8319-4dd9-8633-739d40bab910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639591694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.3639591694
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.660299631
Short name T724
Test name
Test status
Simulation time 4245098788 ps
CPU time 24.7 seconds
Started May 07 12:52:13 PM PDT 24
Finished May 07 12:52:39 PM PDT 24
Peak memory 277268 kb
Host smart-39aa1196-5920-4cc9-a01a-951ad2a59ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660299631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.660299631
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.710533218
Short name T211
Test name
Test status
Simulation time 97407565055 ps
CPU time 3167.24 seconds
Started May 07 12:52:18 PM PDT 24
Finished May 07 01:45:07 PM PDT 24
Peak memory 3328840 kb
Host smart-d1f7a071-e8a2-43e3-b405-f05c66f45f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710533218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.710533218
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.3892646255
Short name T274
Test name
Test status
Simulation time 488214958 ps
CPU time 7.91 seconds
Started May 07 12:52:22 PM PDT 24
Finished May 07 12:52:31 PM PDT 24
Peak memory 220124 kb
Host smart-1563f772-76d2-4da4-9ff6-4ce850d80238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892646255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3892646255
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.3440053295
Short name T128
Test name
Test status
Simulation time 86581201 ps
CPU time 0.94 seconds
Started May 07 12:52:26 PM PDT 24
Finished May 07 12:52:29 PM PDT 24
Peak memory 222180 kb
Host smart-2e32860b-6237-45c1-8e35-dfe3e79d1fa8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440053295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.3440053295
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.3512174652
Short name T30
Test name
Test status
Simulation time 9363653932 ps
CPU time 3.76 seconds
Started May 07 12:52:27 PM PDT 24
Finished May 07 12:52:33 PM PDT 24
Peak memory 203972 kb
Host smart-12214e5e-0494-4c4b-ae48-d1484fb6df95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512174652 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.3512174652
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.3437821393
Short name T499
Test name
Test status
Simulation time 10878785336 ps
CPU time 6.36 seconds
Started May 07 12:52:19 PM PDT 24
Finished May 07 12:52:26 PM PDT 24
Peak memory 224900 kb
Host smart-3916fca7-b608-446f-9957-ef529dc1bda5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437821393 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.3437821393
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.524900681
Short name T565
Test name
Test status
Simulation time 10328291055 ps
CPU time 12.47 seconds
Started May 07 12:52:20 PM PDT 24
Finished May 07 12:52:33 PM PDT 24
Peak memory 270876 kb
Host smart-81d37cd4-4e99-4825-a77d-75508c102cfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524900681 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_fifo_reset_tx.524900681
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.302912112
Short name T1263
Test name
Test status
Simulation time 397143111 ps
CPU time 2.85 seconds
Started May 07 12:52:24 PM PDT 24
Finished May 07 12:52:28 PM PDT 24
Peak memory 203752 kb
Host smart-91714cfe-59c4-44dc-9b15-046c2b5aac18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302912112 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.i2c_target_hrst.302912112
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.1652415379
Short name T886
Test name
Test status
Simulation time 5772132517 ps
CPU time 6.8 seconds
Started May 07 12:52:19 PM PDT 24
Finished May 07 12:52:27 PM PDT 24
Peak memory 212188 kb
Host smart-0006c01a-2ac5-4321-996f-56f1e157a7b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652415379 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.1652415379
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.2517131552
Short name T1015
Test name
Test status
Simulation time 7788821989 ps
CPU time 17.07 seconds
Started May 07 12:52:20 PM PDT 24
Finished May 07 12:52:38 PM PDT 24
Peak memory 280484 kb
Host smart-c2ac8e99-da3e-4a01-9236-a21a13bb2a19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517131552 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.2517131552
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.282938943
Short name T644
Test name
Test status
Simulation time 735442199 ps
CPU time 11 seconds
Started May 07 12:52:18 PM PDT 24
Finished May 07 12:52:30 PM PDT 24
Peak memory 203876 kb
Host smart-ae7a6f83-f102-4420-b2b4-74968d9ac7c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282938943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_targ
et_smoke.282938943
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.599120497
Short name T290
Test name
Test status
Simulation time 4793504805 ps
CPU time 20.6 seconds
Started May 07 12:52:21 PM PDT 24
Finished May 07 12:52:43 PM PDT 24
Peak memory 221436 kb
Host smart-3bf9da7f-27d5-4e65-89bd-3fe4461fcbec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599120497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_rd.599120497
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.2294981209
Short name T437
Test name
Test status
Simulation time 16549419466 ps
CPU time 27.54 seconds
Started May 07 12:52:18 PM PDT 24
Finished May 07 12:52:46 PM PDT 24
Peak memory 203996 kb
Host smart-eed5a335-3c01-4520-a900-cb45882a784d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294981209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.2294981209
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.532835695
Short name T746
Test name
Test status
Simulation time 6843665661 ps
CPU time 85.58 seconds
Started May 07 12:52:21 PM PDT 24
Finished May 07 12:53:48 PM PDT 24
Peak memory 519228 kb
Host smart-19a37343-f73d-4f44-a81f-cf103c3ae2b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532835695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_ta
rget_stretch.532835695
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.197095244
Short name T1033
Test name
Test status
Simulation time 4864186479 ps
CPU time 6.86 seconds
Started May 07 12:52:23 PM PDT 24
Finished May 07 12:52:32 PM PDT 24
Peak memory 212208 kb
Host smart-7921802c-66d3-4f5d-a883-71198a19f4ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197095244 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_timeout.197095244
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1962469204
Short name T1049
Test name
Test status
Simulation time 16321097 ps
CPU time 0.63 seconds
Started May 07 12:55:24 PM PDT 24
Finished May 07 12:55:26 PM PDT 24
Peak memory 203788 kb
Host smart-6ebdcc8a-bb65-4e03-8d3c-a85d53c8affa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962469204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1962469204
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.3765835927
Short name T1177
Test name
Test status
Simulation time 165270782 ps
CPU time 1.8 seconds
Started May 07 12:55:16 PM PDT 24
Finished May 07 12:55:20 PM PDT 24
Peak memory 212192 kb
Host smart-184752ef-120c-49da-8380-55e651e9a427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765835927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3765835927
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.2408634781
Short name T1119
Test name
Test status
Simulation time 1224109237 ps
CPU time 7.23 seconds
Started May 07 12:55:21 PM PDT 24
Finished May 07 12:55:29 PM PDT 24
Peak memory 247720 kb
Host smart-fee3c66d-e300-4245-85ad-c44d33d2a7b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408634781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.2408634781
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.4218861329
Short name T403
Test name
Test status
Simulation time 1766738241 ps
CPU time 120.81 seconds
Started May 07 12:55:17 PM PDT 24
Finished May 07 12:57:20 PM PDT 24
Peak memory 590764 kb
Host smart-d2e9fca1-8459-47e4-9e24-a4d30b33a16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218861329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.4218861329
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.4230902976
Short name T632
Test name
Test status
Simulation time 2219696783 ps
CPU time 72.39 seconds
Started May 07 12:55:18 PM PDT 24
Finished May 07 12:56:32 PM PDT 24
Peak memory 753668 kb
Host smart-8d090704-7f6c-4dc7-8946-40910bb1b921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230902976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.4230902976
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.2689728301
Short name T85
Test name
Test status
Simulation time 103909028 ps
CPU time 0.84 seconds
Started May 07 12:55:17 PM PDT 24
Finished May 07 12:55:20 PM PDT 24
Peak memory 203768 kb
Host smart-3f92ba3e-b57a-41af-a098-aa1db57bb095
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689728301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.2689728301
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.274837802
Short name T1363
Test name
Test status
Simulation time 514144108 ps
CPU time 3.95 seconds
Started May 07 12:55:18 PM PDT 24
Finished May 07 12:55:23 PM PDT 24
Peak memory 225728 kb
Host smart-0ef76c2d-e6ed-4c13-982b-2ec52502186e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274837802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.
274837802
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.1450001786
Short name T666
Test name
Test status
Simulation time 3664086903 ps
CPU time 104.66 seconds
Started May 07 12:55:19 PM PDT 24
Finished May 07 12:57:05 PM PDT 24
Peak memory 1022900 kb
Host smart-8a32e3b2-6b72-46a3-a552-0f47cb326b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450001786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.1450001786
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.1360075261
Short name T217
Test name
Test status
Simulation time 472125251 ps
CPU time 7.12 seconds
Started May 07 12:55:25 PM PDT 24
Finished May 07 12:55:33 PM PDT 24
Peak memory 203948 kb
Host smart-ce94381c-1e27-4a66-96cb-3ec5ed46a3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360075261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.1360075261
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.3031386366
Short name T83
Test name
Test status
Simulation time 1454867698 ps
CPU time 49.95 seconds
Started May 07 12:55:23 PM PDT 24
Finished May 07 12:56:14 PM PDT 24
Peak memory 343744 kb
Host smart-e68fe198-32cd-4cb1-9ed5-4c2c14eb0641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031386366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3031386366
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.2470808265
Short name T1215
Test name
Test status
Simulation time 94359394 ps
CPU time 0.64 seconds
Started May 07 12:55:15 PM PDT 24
Finished May 07 12:55:16 PM PDT 24
Peak memory 203692 kb
Host smart-2a927d32-2342-4988-88db-dd893d017fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470808265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.2470808265
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.37588948
Short name T1158
Test name
Test status
Simulation time 26420246928 ps
CPU time 74.96 seconds
Started May 07 12:55:19 PM PDT 24
Finished May 07 12:56:35 PM PDT 24
Peak memory 204028 kb
Host smart-0c1339bb-95d4-49ec-b74f-cc612076ad12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37588948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.37588948
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.3983480616
Short name T611
Test name
Test status
Simulation time 2888330533 ps
CPU time 36.37 seconds
Started May 07 12:55:13 PM PDT 24
Finished May 07 12:55:51 PM PDT 24
Peak memory 411448 kb
Host smart-546ff0ad-3a88-487b-95bf-d796a2d28be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983480616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.3983480616
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.2352421288
Short name T503
Test name
Test status
Simulation time 7010903597 ps
CPU time 350.66 seconds
Started May 07 12:55:20 PM PDT 24
Finished May 07 01:01:12 PM PDT 24
Peak memory 1596536 kb
Host smart-c70e6386-d4e0-4ec2-a650-48dc7f2398f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352421288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.2352421288
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.1703812146
Short name T859
Test name
Test status
Simulation time 1307763453 ps
CPU time 10.5 seconds
Started May 07 12:55:17 PM PDT 24
Finished May 07 12:55:29 PM PDT 24
Peak memory 214880 kb
Host smart-a60e3c58-8f85-4943-8a1b-cdceaf08714e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703812146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.1703812146
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.3508819960
Short name T588
Test name
Test status
Simulation time 10552490764 ps
CPU time 5.95 seconds
Started May 07 12:55:26 PM PDT 24
Finished May 07 12:55:33 PM PDT 24
Peak memory 212156 kb
Host smart-cf94acd9-8836-414b-b9df-ffa0bb8f9d4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508819960 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3508819960
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.260805817
Short name T118
Test name
Test status
Simulation time 10209249240 ps
CPU time 29.41 seconds
Started May 07 12:55:22 PM PDT 24
Finished May 07 12:55:53 PM PDT 24
Peak memory 335688 kb
Host smart-702305b2-86c3-44d1-8577-b5472b193ca0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260805817 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_acq.260805817
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.1561630552
Short name T740
Test name
Test status
Simulation time 10244595965 ps
CPU time 14.94 seconds
Started May 07 12:55:24 PM PDT 24
Finished May 07 12:55:40 PM PDT 24
Peak memory 304620 kb
Host smart-e2229c17-c77a-46ea-bb70-b05afa097cb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561630552 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.1561630552
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.1089526742
Short name T368
Test name
Test status
Simulation time 2635736628 ps
CPU time 2.78 seconds
Started May 07 12:55:24 PM PDT 24
Finished May 07 12:55:28 PM PDT 24
Peak memory 204016 kb
Host smart-f290ce22-0e49-4810-a142-c99b82c33b96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089526742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.1089526742
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.2886838465
Short name T1190
Test name
Test status
Simulation time 752074078 ps
CPU time 4.16 seconds
Started May 07 12:55:19 PM PDT 24
Finished May 07 12:55:25 PM PDT 24
Peak memory 203948 kb
Host smart-343c61bc-e19f-4823-aed0-ce7f2fa41948
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886838465 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.2886838465
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.1208538105
Short name T703
Test name
Test status
Simulation time 15835555177 ps
CPU time 91.8 seconds
Started May 07 12:55:24 PM PDT 24
Finished May 07 12:56:58 PM PDT 24
Peak memory 1874100 kb
Host smart-382d67fc-dc17-4052-aa32-83157dee9add
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208538105 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.1208538105
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.4207201468
Short name T1108
Test name
Test status
Simulation time 2040224341 ps
CPU time 14.55 seconds
Started May 07 12:55:19 PM PDT 24
Finished May 07 12:55:35 PM PDT 24
Peak memory 203904 kb
Host smart-7279a2cb-35c4-40c0-ad96-92c33e4126d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207201468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.4207201468
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.3334419099
Short name T1008
Test name
Test status
Simulation time 671261024 ps
CPU time 11.32 seconds
Started May 07 12:55:19 PM PDT 24
Finished May 07 12:55:32 PM PDT 24
Peak memory 207420 kb
Host smart-6fbf331e-c9d9-408f-bc3c-5817de78f600
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334419099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.3334419099
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.665771183
Short name T768
Test name
Test status
Simulation time 47012190516 ps
CPU time 175.24 seconds
Started May 07 12:55:20 PM PDT 24
Finished May 07 12:58:17 PM PDT 24
Peak memory 2179972 kb
Host smart-d631cce0-5243-49f1-a32e-390a16b6ff10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665771183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_wr.665771183
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.1624660915
Short name T874
Test name
Test status
Simulation time 28355179021 ps
CPU time 664.51 seconds
Started May 07 12:55:20 PM PDT 24
Finished May 07 01:06:26 PM PDT 24
Peak memory 3350248 kb
Host smart-b1efaead-6756-43d2-8288-cf23b33fde8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624660915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.1624660915
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.563544191
Short name T682
Test name
Test status
Simulation time 2492692549 ps
CPU time 7.15 seconds
Started May 07 12:55:22 PM PDT 24
Finished May 07 12:55:30 PM PDT 24
Peak memory 215332 kb
Host smart-65604573-1f4d-46f7-b644-0b248050e48d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563544191 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.563544191
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.3006431138
Short name T881
Test name
Test status
Simulation time 105407587 ps
CPU time 0.61 seconds
Started May 07 12:55:30 PM PDT 24
Finished May 07 12:55:32 PM PDT 24
Peak memory 203792 kb
Host smart-c1ce9e3d-bfa9-4028-bf78-3ca932189da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006431138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3006431138
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.2280507446
Short name T570
Test name
Test status
Simulation time 234874383 ps
CPU time 1.76 seconds
Started May 07 12:55:24 PM PDT 24
Finished May 07 12:55:27 PM PDT 24
Peak memory 212228 kb
Host smart-6d8f2a22-631e-4b03-82b2-2c3fdad40ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280507446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2280507446
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2979944687
Short name T722
Test name
Test status
Simulation time 1105524808 ps
CPU time 13.26 seconds
Started May 07 12:55:22 PM PDT 24
Finished May 07 12:55:36 PM PDT 24
Peak memory 256468 kb
Host smart-0914e65e-83e2-4a66-b071-a92f9c2c5828
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979944687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2979944687
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.124936365
Short name T244
Test name
Test status
Simulation time 15839102474 ps
CPU time 57.2 seconds
Started May 07 12:55:26 PM PDT 24
Finished May 07 12:56:24 PM PDT 24
Peak memory 543440 kb
Host smart-adb5bfc8-8da1-4d7c-9334-5632ab0d9372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124936365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.124936365
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.936727765
Short name T288
Test name
Test status
Simulation time 45135170551 ps
CPU time 82.08 seconds
Started May 07 12:55:23 PM PDT 24
Finished May 07 12:56:46 PM PDT 24
Peak memory 766044 kb
Host smart-679efc75-16a0-4eb3-86ee-4e3782d84282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936727765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.936727765
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.803756210
Short name T1011
Test name
Test status
Simulation time 394040978 ps
CPU time 0.81 seconds
Started May 07 12:55:24 PM PDT 24
Finished May 07 12:55:26 PM PDT 24
Peak memory 203796 kb
Host smart-3b4be46e-33b8-49e4-a089-60ef36ddedc9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803756210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fm
t.803756210
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.490732155
Short name T1067
Test name
Test status
Simulation time 701421635 ps
CPU time 5.37 seconds
Started May 07 12:55:22 PM PDT 24
Finished May 07 12:55:28 PM PDT 24
Peak memory 238532 kb
Host smart-6594aab4-27df-4386-9fbd-500249c0c0cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490732155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.
490732155
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.1869364924
Short name T186
Test name
Test status
Simulation time 3748410122 ps
CPU time 93.96 seconds
Started May 07 12:55:24 PM PDT 24
Finished May 07 12:56:59 PM PDT 24
Peak memory 1022880 kb
Host smart-04f1b3e3-b640-49b5-bece-90ac83f5069b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869364924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.1869364924
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.3207725027
Short name T438
Test name
Test status
Simulation time 258162614 ps
CPU time 10.85 seconds
Started May 07 12:55:31 PM PDT 24
Finished May 07 12:55:43 PM PDT 24
Peak memory 203892 kb
Host smart-2c31846c-b663-4339-9b5f-c30b4a4f2969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207725027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.3207725027
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.2453739955
Short name T1105
Test name
Test status
Simulation time 2204665512 ps
CPU time 25.42 seconds
Started May 07 12:55:28 PM PDT 24
Finished May 07 12:55:55 PM PDT 24
Peak memory 317312 kb
Host smart-3851a3c9-8bea-4c7e-8e27-61e2f2e34ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453739955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.2453739955
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.2451871845
Short name T698
Test name
Test status
Simulation time 44384470 ps
CPU time 0.66 seconds
Started May 07 12:55:24 PM PDT 24
Finished May 07 12:55:26 PM PDT 24
Peak memory 203692 kb
Host smart-6910e7a7-55cf-4a48-b276-c37a1d902ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451871845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.2451871845
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.695986625
Short name T268
Test name
Test status
Simulation time 4405805116 ps
CPU time 63.37 seconds
Started May 07 12:55:25 PM PDT 24
Finished May 07 12:56:29 PM PDT 24
Peak memory 301484 kb
Host smart-824a8b72-8b28-4a87-a4b7-7e809543e5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695986625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.695986625
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.3893182290
Short name T776
Test name
Test status
Simulation time 732241054 ps
CPU time 2.32 seconds
Started May 07 12:55:31 PM PDT 24
Finished May 07 12:55:34 PM PDT 24
Peak memory 203828 kb
Host smart-8e402d33-b28f-467b-b03a-e67382676ff7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893182290 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.3893182290
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.862524658
Short name T621
Test name
Test status
Simulation time 10200355976 ps
CPU time 26.47 seconds
Started May 07 12:55:29 PM PDT 24
Finished May 07 12:55:56 PM PDT 24
Peak memory 355616 kb
Host smart-9f6df7af-ada0-46e4-b36b-34be50a7c9dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862524658 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_acq.862524658
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.2935665599
Short name T868
Test name
Test status
Simulation time 10093058815 ps
CPU time 36.96 seconds
Started May 07 12:55:32 PM PDT 24
Finished May 07 12:56:10 PM PDT 24
Peak memory 361636 kb
Host smart-e1f1fd89-65e0-4947-9b8c-abdeb3bc03dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935665599 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.2935665599
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.1326559098
Short name T1113
Test name
Test status
Simulation time 462862607 ps
CPU time 2.75 seconds
Started May 07 12:55:32 PM PDT 24
Finished May 07 12:55:36 PM PDT 24
Peak memory 203920 kb
Host smart-38d86977-bc4c-45ba-88e2-913a0ebc6c40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326559098 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.1326559098
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.3710243243
Short name T606
Test name
Test status
Simulation time 8166516107 ps
CPU time 5.98 seconds
Started May 07 12:55:28 PM PDT 24
Finished May 07 12:55:35 PM PDT 24
Peak memory 217308 kb
Host smart-63280775-0276-42db-a732-20d74b29eb03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710243243 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.3710243243
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.1736564047
Short name T1316
Test name
Test status
Simulation time 17389992498 ps
CPU time 356.07 seconds
Started May 07 12:55:29 PM PDT 24
Finished May 07 01:01:27 PM PDT 24
Peak memory 4081128 kb
Host smart-324ad26a-b25e-4c1f-a5e4-02375f1b645c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736564047 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.1736564047
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.1499487263
Short name T1135
Test name
Test status
Simulation time 631251182 ps
CPU time 8.51 seconds
Started May 07 12:55:30 PM PDT 24
Finished May 07 12:55:40 PM PDT 24
Peak memory 203848 kb
Host smart-2cbb4e77-3816-4012-80e6-bb0558bfc32d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499487263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.1499487263
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.841673151
Short name T1001
Test name
Test status
Simulation time 685016311 ps
CPU time 10.13 seconds
Started May 07 12:55:33 PM PDT 24
Finished May 07 12:55:44 PM PDT 24
Peak memory 203904 kb
Host smart-239a816d-2930-4ea8-8cb8-66e61c35d2f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841673151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_rd.841673151
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.3152733343
Short name T33
Test name
Test status
Simulation time 38530046870 ps
CPU time 203.37 seconds
Started May 07 12:55:30 PM PDT 24
Finished May 07 12:58:55 PM PDT 24
Peak memory 2476244 kb
Host smart-1dcdb256-88d3-43ee-ae86-355ae4f5f884
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152733343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.3152733343
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.1069043157
Short name T1136
Test name
Test status
Simulation time 23976289669 ps
CPU time 282.07 seconds
Started May 07 12:55:30 PM PDT 24
Finished May 07 01:00:14 PM PDT 24
Peak memory 2169056 kb
Host smart-db1bc4f6-35f8-4f79-b5fa-a3f41f9aa6b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069043157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.1069043157
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.4253426984
Short name T1197
Test name
Test status
Simulation time 1345993277 ps
CPU time 7.42 seconds
Started May 07 12:55:34 PM PDT 24
Finished May 07 12:55:43 PM PDT 24
Peak memory 220240 kb
Host smart-c87fc881-9d54-4327-821e-b0749abf9662
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253426984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.4253426984
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.309598751
Short name T518
Test name
Test status
Simulation time 16880072 ps
CPU time 0.67 seconds
Started May 07 12:55:47 PM PDT 24
Finished May 07 12:55:52 PM PDT 24
Peak memory 203780 kb
Host smart-57c9a03a-a1b7-4815-aa01-49b739ce45db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309598751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.309598751
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.1567110824
Short name T429
Test name
Test status
Simulation time 1384654778 ps
CPU time 1.91 seconds
Started May 07 12:55:36 PM PDT 24
Finished May 07 12:55:40 PM PDT 24
Peak memory 216044 kb
Host smart-220d7b03-6359-4aaa-955c-f6113ebfdd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567110824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.1567110824
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.3447073742
Short name T395
Test name
Test status
Simulation time 436611113 ps
CPU time 7.81 seconds
Started May 07 12:55:36 PM PDT 24
Finished May 07 12:55:45 PM PDT 24
Peak memory 296660 kb
Host smart-6becd312-7cd3-45fd-a902-3923382d8b49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447073742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.3447073742
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.2867411567
Short name T380
Test name
Test status
Simulation time 7317001734 ps
CPU time 70.36 seconds
Started May 07 12:55:36 PM PDT 24
Finished May 07 12:56:47 PM PDT 24
Peak memory 658788 kb
Host smart-784419f1-e533-470a-bd6d-dd6949b6c243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867411567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2867411567
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.253602679
Short name T687
Test name
Test status
Simulation time 4483278667 ps
CPU time 68.7 seconds
Started May 07 12:55:29 PM PDT 24
Finished May 07 12:56:40 PM PDT 24
Peak memory 425168 kb
Host smart-0ddd7153-10e4-4764-9317-d80df96ea3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253602679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.253602679
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.626155954
Short name T929
Test name
Test status
Simulation time 98270943 ps
CPU time 0.9 seconds
Started May 07 12:55:29 PM PDT 24
Finished May 07 12:55:31 PM PDT 24
Peak memory 203728 kb
Host smart-e7796d31-3a37-4bf1-a9ac-0a3e8941de1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626155954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fm
t.626155954
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.2892435976
Short name T339
Test name
Test status
Simulation time 196323583 ps
CPU time 9.46 seconds
Started May 07 12:55:34 PM PDT 24
Finished May 07 12:55:45 PM PDT 24
Peak memory 203948 kb
Host smart-6f6303e5-a5c0-4a8f-95d9-512089e360be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892435976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.2892435976
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.80106644
Short name T1293
Test name
Test status
Simulation time 13383778588 ps
CPU time 249.86 seconds
Started May 07 12:55:31 PM PDT 24
Finished May 07 12:59:42 PM PDT 24
Peak memory 1038188 kb
Host smart-3f0266e4-93e6-4780-bda3-e0bb77de5155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80106644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.80106644
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.3670808627
Short name T950
Test name
Test status
Simulation time 696561391 ps
CPU time 5.84 seconds
Started May 07 12:55:40 PM PDT 24
Finished May 07 12:55:48 PM PDT 24
Peak memory 203880 kb
Host smart-9c6b9252-a078-4132-b8fd-1294f0b971e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670808627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.3670808627
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.3575971555
Short name T872
Test name
Test status
Simulation time 17023332431 ps
CPU time 22.8 seconds
Started May 07 12:55:42 PM PDT 24
Finished May 07 12:56:07 PM PDT 24
Peak memory 292964 kb
Host smart-0e41749d-0108-4ce6-b93c-3a43e14335da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575971555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.3575971555
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.3784511230
Short name T56
Test name
Test status
Simulation time 27238668 ps
CPU time 0.64 seconds
Started May 07 12:55:30 PM PDT 24
Finished May 07 12:55:32 PM PDT 24
Peak memory 203732 kb
Host smart-f0b81752-a5a5-4f20-89c4-2af2479eefb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784511230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.3784511230
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.2721442225
Short name T779
Test name
Test status
Simulation time 501109075 ps
CPU time 1.79 seconds
Started May 07 12:55:37 PM PDT 24
Finished May 07 12:55:41 PM PDT 24
Peak memory 204004 kb
Host smart-884c0836-5fea-4cfa-a54c-adc914dc0215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721442225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.2721442225
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.2428231378
Short name T832
Test name
Test status
Simulation time 780734836 ps
CPU time 35.93 seconds
Started May 07 12:55:30 PM PDT 24
Finished May 07 12:56:08 PM PDT 24
Peak memory 281208 kb
Host smart-acdb783f-c5b7-4ace-a570-54f827b547f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428231378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.2428231378
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.2649404792
Short name T297
Test name
Test status
Simulation time 1777698070 ps
CPU time 7.86 seconds
Started May 07 12:55:37 PM PDT 24
Finished May 07 12:55:47 PM PDT 24
Peak memory 214792 kb
Host smart-2cc20dc7-c602-4c3b-b548-5639ec4723c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649404792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.2649404792
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.2766617919
Short name T310
Test name
Test status
Simulation time 5537124226 ps
CPU time 5.96 seconds
Started May 07 12:55:38 PM PDT 24
Finished May 07 12:55:46 PM PDT 24
Peak memory 213808 kb
Host smart-0f8b9dd9-e4f0-4617-9f0f-64fa9a68c74a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766617919 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.2766617919
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.3006320086
Short name T406
Test name
Test status
Simulation time 10089072748 ps
CPU time 63.86 seconds
Started May 07 12:55:34 PM PDT 24
Finished May 07 12:56:39 PM PDT 24
Peak memory 416916 kb
Host smart-92cb9c80-2770-48d2-8334-0707945c3724
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006320086 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.3006320086
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.1629459397
Short name T116
Test name
Test status
Simulation time 11003909366 ps
CPU time 9.33 seconds
Started May 07 12:55:35 PM PDT 24
Finished May 07 12:55:45 PM PDT 24
Peak memory 252648 kb
Host smart-5a1d0d08-85a8-4fc5-bf87-7e9806c7e9e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629459397 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.1629459397
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.1024002952
Short name T922
Test name
Test status
Simulation time 378300085 ps
CPU time 2.45 seconds
Started May 07 12:55:42 PM PDT 24
Finished May 07 12:55:46 PM PDT 24
Peak memory 203892 kb
Host smart-e541dacd-8609-4ac8-88a3-70e892d43feb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024002952 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.1024002952
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.3973122880
Short name T747
Test name
Test status
Simulation time 761903502 ps
CPU time 3.91 seconds
Started May 07 12:55:35 PM PDT 24
Finished May 07 12:55:40 PM PDT 24
Peak memory 203884 kb
Host smart-1a55e318-8a8a-480a-858b-d92422174a32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973122880 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.3973122880
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.896455332
Short name T341
Test name
Test status
Simulation time 11415114105 ps
CPU time 63.96 seconds
Started May 07 12:55:36 PM PDT 24
Finished May 07 12:56:42 PM PDT 24
Peak memory 1506488 kb
Host smart-048e8437-846c-4556-8a07-8e59fb0c1484
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896455332 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.896455332
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.3293843531
Short name T534
Test name
Test status
Simulation time 1155971918 ps
CPU time 14.76 seconds
Started May 07 12:55:36 PM PDT 24
Finished May 07 12:55:53 PM PDT 24
Peak memory 203836 kb
Host smart-b1de2710-2012-49a2-994d-0f4a880f8758
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293843531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.3293843531
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.240992550
Short name T228
Test name
Test status
Simulation time 1044407020 ps
CPU time 5.83 seconds
Started May 07 12:55:38 PM PDT 24
Finished May 07 12:55:46 PM PDT 24
Peak memory 203916 kb
Host smart-bddede0d-4690-44c4-97bd-1e0903adc04d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240992550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_rd.240992550
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.2443565353
Short name T319
Test name
Test status
Simulation time 34405175802 ps
CPU time 32.44 seconds
Started May 07 12:55:37 PM PDT 24
Finished May 07 12:56:11 PM PDT 24
Peak memory 689972 kb
Host smart-903742c4-cfe0-425f-a421-927aa520b646
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443565353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.2443565353
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.914743638
Short name T1106
Test name
Test status
Simulation time 7213636373 ps
CPU time 109.17 seconds
Started May 07 12:55:36 PM PDT 24
Finished May 07 12:57:27 PM PDT 24
Peak memory 1319468 kb
Host smart-2782d364-53a5-4302-8649-3acf10949d0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914743638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_t
arget_stretch.914743638
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_alert_test.4249030858
Short name T805
Test name
Test status
Simulation time 17613411 ps
CPU time 0.65 seconds
Started May 07 12:55:48 PM PDT 24
Finished May 07 12:55:54 PM PDT 24
Peak memory 203812 kb
Host smart-47b621bb-5255-4ace-aee8-6290635c7368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249030858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.4249030858
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.2021803195
Short name T1331
Test name
Test status
Simulation time 92945516 ps
CPU time 1.84 seconds
Started May 07 12:55:40 PM PDT 24
Finished May 07 12:55:43 PM PDT 24
Peak memory 212180 kb
Host smart-288a89f9-c8f3-498c-a522-bbcac8f49d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021803195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2021803195
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.2644468775
Short name T374
Test name
Test status
Simulation time 207592406 ps
CPU time 8.01 seconds
Started May 07 12:55:39 PM PDT 24
Finished May 07 12:55:49 PM PDT 24
Peak memory 231592 kb
Host smart-15a6d857-b484-4082-b6f6-7769284fff16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644468775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.2644468775
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.731463165
Short name T899
Test name
Test status
Simulation time 1230018854 ps
CPU time 34.23 seconds
Started May 07 12:55:44 PM PDT 24
Finished May 07 12:56:21 PM PDT 24
Peak memory 482304 kb
Host smart-8dff8dac-1b7a-462d-beda-b02abe956477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731463165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.731463165
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.3454762510
Short name T945
Test name
Test status
Simulation time 2151179557 ps
CPU time 164.77 seconds
Started May 07 12:55:41 PM PDT 24
Finished May 07 12:58:28 PM PDT 24
Peak memory 715016 kb
Host smart-9a0a3c80-78aa-4e7f-b0e6-7849f79169ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454762510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.3454762510
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.790903571
Short name T1053
Test name
Test status
Simulation time 201337812 ps
CPU time 1.03 seconds
Started May 07 12:55:40 PM PDT 24
Finished May 07 12:55:43 PM PDT 24
Peak memory 203748 kb
Host smart-493689bb-71ed-4177-a3eb-e128ab2e33c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790903571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fm
t.790903571
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.2057219044
Short name T602
Test name
Test status
Simulation time 510294534 ps
CPU time 3.75 seconds
Started May 07 12:55:47 PM PDT 24
Finished May 07 12:55:54 PM PDT 24
Peak memory 223644 kb
Host smart-ee944ffe-42e6-476b-83d5-4f19864cb60f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057219044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.2057219044
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.880298770
Short name T1161
Test name
Test status
Simulation time 18695828230 ps
CPU time 120.68 seconds
Started May 07 12:55:39 PM PDT 24
Finished May 07 12:57:42 PM PDT 24
Peak memory 1322492 kb
Host smart-fecc98a6-f46c-403e-bd77-7f692ecbab3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880298770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.880298770
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.1676281896
Short name T714
Test name
Test status
Simulation time 579793815 ps
CPU time 9.38 seconds
Started May 07 12:55:49 PM PDT 24
Finished May 07 12:56:04 PM PDT 24
Peak memory 203956 kb
Host smart-e87e7535-db64-4484-9b7a-c75a925b9bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676281896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.1676281896
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.3022338583
Short name T978
Test name
Test status
Simulation time 1250178583 ps
CPU time 18.43 seconds
Started May 07 12:55:49 PM PDT 24
Finished May 07 12:56:12 PM PDT 24
Peak memory 301276 kb
Host smart-5d86b167-ccfc-43ec-9060-34e6768cd59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022338583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.3022338583
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.1269647982
Short name T208
Test name
Test status
Simulation time 253800048 ps
CPU time 0.64 seconds
Started May 07 12:55:42 PM PDT 24
Finished May 07 12:55:45 PM PDT 24
Peak memory 203732 kb
Host smart-250760c8-e8ac-4fd6-ad8d-6507814be26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269647982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1269647982
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.2434244509
Short name T755
Test name
Test status
Simulation time 30647504384 ps
CPU time 83.02 seconds
Started May 07 12:55:43 PM PDT 24
Finished May 07 12:57:08 PM PDT 24
Peak memory 235984 kb
Host smart-b502a282-d078-4c1e-a654-fd907e5b9ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434244509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.2434244509
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.2091213252
Short name T757
Test name
Test status
Simulation time 1415350704 ps
CPU time 20.89 seconds
Started May 07 12:55:43 PM PDT 24
Finished May 07 12:56:07 PM PDT 24
Peak memory 284820 kb
Host smart-4129eacd-9936-4b7c-a875-44f5ae0bf5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091213252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.2091213252
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.891057782
Short name T253
Test name
Test status
Simulation time 91969664525 ps
CPU time 967.53 seconds
Started May 07 12:55:40 PM PDT 24
Finished May 07 01:11:50 PM PDT 24
Peak memory 1858700 kb
Host smart-21b3de16-174d-44f9-9dc7-0546e0cb5af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891057782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.891057782
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.4207677339
Short name T1205
Test name
Test status
Simulation time 704788016 ps
CPU time 8.6 seconds
Started May 07 12:55:41 PM PDT 24
Finished May 07 12:55:51 PM PDT 24
Peak memory 219576 kb
Host smart-57f10a48-8cb4-4952-883d-2ca29dfc0b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207677339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.4207677339
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1144047610
Short name T1174
Test name
Test status
Simulation time 733730590 ps
CPU time 3.78 seconds
Started May 07 12:55:49 PM PDT 24
Finished May 07 12:55:58 PM PDT 24
Peak memory 203944 kb
Host smart-a8169ec8-b825-4b3a-a125-df04a2a94870
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144047610 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1144047610
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.688192004
Short name T356
Test name
Test status
Simulation time 10162392137 ps
CPU time 6.93 seconds
Started May 07 12:55:42 PM PDT 24
Finished May 07 12:55:52 PM PDT 24
Peak memory 225500 kb
Host smart-ec57bb96-129b-45d1-9dee-fa80f3c77dd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688192004 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_acq.688192004
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.2335505725
Short name T627
Test name
Test status
Simulation time 10147615654 ps
CPU time 13.82 seconds
Started May 07 12:55:51 PM PDT 24
Finished May 07 12:56:10 PM PDT 24
Peak memory 262876 kb
Host smart-117c548d-2e91-4e25-8de1-87458c152c0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335505725 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.2335505725
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.1729989938
Short name T549
Test name
Test status
Simulation time 794325876 ps
CPU time 2.47 seconds
Started May 07 12:55:49 PM PDT 24
Finished May 07 12:55:57 PM PDT 24
Peak memory 203904 kb
Host smart-cc362fb7-213e-499a-abdc-d2b1e5ee71fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729989938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.1729989938
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.3958132370
Short name T710
Test name
Test status
Simulation time 841212532 ps
CPU time 5.08 seconds
Started May 07 12:55:42 PM PDT 24
Finished May 07 12:55:49 PM PDT 24
Peak memory 208148 kb
Host smart-a0cec3f2-55bd-494e-93fd-d66e2460f143
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958132370 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.3958132370
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.155514168
Short name T20
Test name
Test status
Simulation time 10320353835 ps
CPU time 9.23 seconds
Started May 07 12:55:42 PM PDT 24
Finished May 07 12:55:54 PM PDT 24
Peak memory 257492 kb
Host smart-4ff67521-373e-4b82-b768-f1c95b1c109b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155514168 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.155514168
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2045604527
Short name T808
Test name
Test status
Simulation time 2344567120 ps
CPU time 16.81 seconds
Started May 07 12:55:42 PM PDT 24
Finished May 07 12:56:01 PM PDT 24
Peak memory 203968 kb
Host smart-2f0ec7c6-2502-446f-8453-4d039de9522e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045604527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2045604527
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.3590468268
Short name T709
Test name
Test status
Simulation time 4901895804 ps
CPU time 17.97 seconds
Started May 07 12:55:41 PM PDT 24
Finished May 07 12:56:01 PM PDT 24
Peak memory 224152 kb
Host smart-7322602f-043e-4b69-9c70-f64a1e44c0ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590468268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.3590468268
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.923472933
Short name T473
Test name
Test status
Simulation time 38104806163 ps
CPU time 70.29 seconds
Started May 07 12:55:47 PM PDT 24
Finished May 07 12:57:01 PM PDT 24
Peak memory 1157080 kb
Host smart-a92d7e4a-8545-4d93-ac36-83a688b2a41c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923472933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c
_target_stress_wr.923472933
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.1404298549
Short name T108
Test name
Test status
Simulation time 16027426324 ps
CPU time 133.49 seconds
Started May 07 12:55:40 PM PDT 24
Finished May 07 12:57:55 PM PDT 24
Peak memory 1326820 kb
Host smart-5439a73a-c727-4ce3-90cd-2229b3b88f55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404298549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.1404298549
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.2288681817
Short name T286
Test name
Test status
Simulation time 18124286479 ps
CPU time 7.55 seconds
Started May 07 12:55:41 PM PDT 24
Finished May 07 12:55:50 PM PDT 24
Peak memory 218364 kb
Host smart-7af0b1af-cf88-4dad-9c00-f9dbc0be9334
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288681817 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.2288681817
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.1416522607
Short name T1267
Test name
Test status
Simulation time 31917203 ps
CPU time 0.61 seconds
Started May 07 12:56:03 PM PDT 24
Finished May 07 12:56:10 PM PDT 24
Peak memory 203788 kb
Host smart-80d913a6-28de-4adf-91e5-b018e5cf5bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416522607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.1416522607
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.3655007226
Short name T693
Test name
Test status
Simulation time 66363228 ps
CPU time 1.28 seconds
Started May 07 12:55:58 PM PDT 24
Finished May 07 12:56:05 PM PDT 24
Peak memory 212380 kb
Host smart-f9db8243-a3e5-4ef7-b0d3-e13bcaf537cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655007226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.3655007226
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3504835411
Short name T1094
Test name
Test status
Simulation time 318077338 ps
CPU time 5.59 seconds
Started May 07 12:55:49 PM PDT 24
Finished May 07 12:56:00 PM PDT 24
Peak memory 269820 kb
Host smart-16801081-3cf2-4669-ab69-eaaabcf1a83a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504835411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.3504835411
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2222531872
Short name T387
Test name
Test status
Simulation time 1785574935 ps
CPU time 126.65 seconds
Started May 07 12:55:56 PM PDT 24
Finished May 07 12:58:08 PM PDT 24
Peak memory 553656 kb
Host smart-86fc0aec-325f-4cd2-b8e9-16796469e8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222531872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2222531872
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.322290674
Short name T566
Test name
Test status
Simulation time 1603590104 ps
CPU time 51.01 seconds
Started May 07 12:55:48 PM PDT 24
Finished May 07 12:56:44 PM PDT 24
Peak memory 587592 kb
Host smart-688d5e36-f832-4d46-9e9e-d353bc901792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322290674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.322290674
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.2787868245
Short name T1156
Test name
Test status
Simulation time 326542559 ps
CPU time 1.13 seconds
Started May 07 12:55:52 PM PDT 24
Finished May 07 12:55:59 PM PDT 24
Peak memory 203868 kb
Host smart-d3884afd-d96a-4ee5-9aea-8260e4425d01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787868245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.2787868245
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.1210961530
Short name T753
Test name
Test status
Simulation time 141950778 ps
CPU time 7.79 seconds
Started May 07 12:55:46 PM PDT 24
Finished May 07 12:55:58 PM PDT 24
Peak memory 227380 kb
Host smart-cc5d8d59-aa30-44d8-bed5-558dda5b6b57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210961530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.1210961530
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.2238194217
Short name T812
Test name
Test status
Simulation time 18631528573 ps
CPU time 151.59 seconds
Started May 07 12:55:52 PM PDT 24
Finished May 07 12:58:29 PM PDT 24
Peak memory 1316036 kb
Host smart-8e2be996-d7c5-4a44-9b78-141b492457a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238194217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.2238194217
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.3704314795
Short name T493
Test name
Test status
Simulation time 241259410 ps
CPU time 10.25 seconds
Started May 07 12:56:02 PM PDT 24
Finished May 07 12:56:19 PM PDT 24
Peak memory 203828 kb
Host smart-10585485-acae-4f66-8a02-305010258b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704314795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.3704314795
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.938185791
Short name T49
Test name
Test status
Simulation time 8536517701 ps
CPU time 108.55 seconds
Started May 07 12:55:58 PM PDT 24
Finished May 07 12:57:52 PM PDT 24
Peak memory 378624 kb
Host smart-dfb86451-5d19-41d0-81fd-54f621f9ea5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938185791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.938185791
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.2039403541
Short name T361
Test name
Test status
Simulation time 93193380 ps
CPU time 0.67 seconds
Started May 07 12:55:49 PM PDT 24
Finished May 07 12:55:55 PM PDT 24
Peak memory 203724 kb
Host smart-15d8d01a-4dae-4bf6-8ca1-fc7b8ac21164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039403541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.2039403541
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.2652814316
Short name T293
Test name
Test status
Simulation time 7506022109 ps
CPU time 106.69 seconds
Started May 07 12:55:56 PM PDT 24
Finished May 07 12:57:48 PM PDT 24
Peak memory 228716 kb
Host smart-10ec9d35-eab1-427d-be4e-b5b8a2654998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652814316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.2652814316
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.3200423387
Short name T961
Test name
Test status
Simulation time 4107187489 ps
CPU time 14.87 seconds
Started May 07 12:55:47 PM PDT 24
Finished May 07 12:56:06 PM PDT 24
Peak memory 260608 kb
Host smart-037eed9b-c6b0-491c-a81b-6f67b3bd95dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200423387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.3200423387
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.3355775543
Short name T105
Test name
Test status
Simulation time 21851511676 ps
CPU time 428.96 seconds
Started May 07 12:55:55 PM PDT 24
Finished May 07 01:03:09 PM PDT 24
Peak memory 1867876 kb
Host smart-18d8750f-defd-43fb-a2a1-3541f4a07352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355775543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.3355775543
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.1145381168
Short name T898
Test name
Test status
Simulation time 805453450 ps
CPU time 4.11 seconds
Started May 07 12:55:59 PM PDT 24
Finished May 07 12:56:09 PM PDT 24
Peak memory 203792 kb
Host smart-d73814ee-f5ef-4668-9d86-33051d5c3e44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145381168 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.1145381168
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.1491805027
Short name T442
Test name
Test status
Simulation time 10091160813 ps
CPU time 72.53 seconds
Started May 07 12:55:55 PM PDT 24
Finished May 07 12:57:13 PM PDT 24
Peak memory 480840 kb
Host smart-8b5c6cd4-ee95-4c39-b2b5-32cfd3701f55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491805027 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.1491805027
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.208548992
Short name T536
Test name
Test status
Simulation time 10111608866 ps
CPU time 8.38 seconds
Started May 07 12:55:55 PM PDT 24
Finished May 07 12:56:09 PM PDT 24
Peak memory 242340 kb
Host smart-85187012-1814-4264-844e-13eef3ca84ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208548992 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_fifo_reset_tx.208548992
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.433219667
Short name T917
Test name
Test status
Simulation time 1216736985 ps
CPU time 2.15 seconds
Started May 07 12:55:56 PM PDT 24
Finished May 07 12:56:04 PM PDT 24
Peak memory 203832 kb
Host smart-02e70c75-52d7-470b-8843-0db350ecb359
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433219667 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.i2c_target_hrst.433219667
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.4232486137
Short name T974
Test name
Test status
Simulation time 1103130611 ps
CPU time 3.72 seconds
Started May 07 12:55:53 PM PDT 24
Finished May 07 12:56:03 PM PDT 24
Peak memory 203932 kb
Host smart-34484f86-7ea9-4ab0-8edb-493693333baf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232486137 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.4232486137
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.4180973950
Short name T869
Test name
Test status
Simulation time 7968151341 ps
CPU time 3.51 seconds
Started May 07 12:55:56 PM PDT 24
Finished May 07 12:56:05 PM PDT 24
Peak memory 203988 kb
Host smart-e1402a4f-30f2-4b18-b322-3507a33b4ffd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180973950 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.4180973950
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.2985929147
Short name T114
Test name
Test status
Simulation time 3866957581 ps
CPU time 16.37 seconds
Started May 07 12:55:59 PM PDT 24
Finished May 07 12:56:22 PM PDT 24
Peak memory 203892 kb
Host smart-faf139c2-6faf-4a2c-b671-f7a75dc3fe0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985929147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.2985929147
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.2073351736
Short name T284
Test name
Test status
Simulation time 687079379 ps
CPU time 12.62 seconds
Started May 07 12:55:56 PM PDT 24
Finished May 07 12:56:14 PM PDT 24
Peak memory 208696 kb
Host smart-dbecd08b-9982-47a7-acae-f061947d61a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073351736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.2073351736
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.294302370
Short name T911
Test name
Test status
Simulation time 41749255867 ps
CPU time 557.69 seconds
Started May 07 12:55:54 PM PDT 24
Finished May 07 01:05:17 PM PDT 24
Peak memory 4687604 kb
Host smart-ca8a0758-1d9e-47e5-a8f5-67765b36d92a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294302370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_wr.294302370
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.3798373718
Short name T994
Test name
Test status
Simulation time 27180255641 ps
CPU time 213.39 seconds
Started May 07 12:55:53 PM PDT 24
Finished May 07 12:59:32 PM PDT 24
Peak memory 1480860 kb
Host smart-be4f42ae-f7cf-45dd-812d-5a2cb7f10f18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798373718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.3798373718
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.1648867063
Short name T522
Test name
Test status
Simulation time 1477882938 ps
CPU time 8.02 seconds
Started May 07 12:55:54 PM PDT 24
Finished May 07 12:56:08 PM PDT 24
Peak memory 218412 kb
Host smart-abdab6e8-d4ca-425b-bd39-347c26fe7b9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648867063 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.1648867063
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.3598719131
Short name T378
Test name
Test status
Simulation time 48601809 ps
CPU time 0.6 seconds
Started May 07 12:56:11 PM PDT 24
Finished May 07 12:56:16 PM PDT 24
Peak memory 203740 kb
Host smart-3ca3d3d2-0706-421d-9255-c173be4aa9a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598719131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.3598719131
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.3855866522
Short name T3
Test name
Test status
Simulation time 111989981 ps
CPU time 2.07 seconds
Started May 07 12:56:03 PM PDT 24
Finished May 07 12:56:11 PM PDT 24
Peak memory 212184 kb
Host smart-aec296c2-3d62-45ba-a026-9e43e557495e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855866522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3855866522
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.1923724007
Short name T265
Test name
Test status
Simulation time 471061438 ps
CPU time 7.06 seconds
Started May 07 12:56:03 PM PDT 24
Finished May 07 12:56:16 PM PDT 24
Peak memory 284592 kb
Host smart-295efdb9-9757-445b-9fa3-09cebe25a1ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923724007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.1923724007
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.2238002631
Short name T1226
Test name
Test status
Simulation time 11785924559 ps
CPU time 53.5 seconds
Started May 07 12:56:04 PM PDT 24
Finished May 07 12:57:04 PM PDT 24
Peak memory 430496 kb
Host smart-b1ea9e13-747a-4e43-a6a2-bc63887a8373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238002631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.2238002631
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.154737784
Short name T905
Test name
Test status
Simulation time 2113740337 ps
CPU time 75.12 seconds
Started May 07 12:56:03 PM PDT 24
Finished May 07 12:57:25 PM PDT 24
Peak memory 693684 kb
Host smart-2740e281-06d2-4b87-9c33-b7f51783fe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154737784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.154737784
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.3974937454
Short name T550
Test name
Test status
Simulation time 94900204 ps
CPU time 0.93 seconds
Started May 07 12:56:02 PM PDT 24
Finished May 07 12:56:09 PM PDT 24
Peak memory 203780 kb
Host smart-8e4f8476-27ec-4dc5-98bb-edcc66478ca3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974937454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.3974937454
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.1948885035
Short name T598
Test name
Test status
Simulation time 695846887 ps
CPU time 4.51 seconds
Started May 07 12:56:04 PM PDT 24
Finished May 07 12:56:15 PM PDT 24
Peak memory 237400 kb
Host smart-8fb00129-d8c4-4697-9303-eb8a856fd954
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948885035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.1948885035
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.2558779099
Short name T759
Test name
Test status
Simulation time 2850505870 ps
CPU time 179.08 seconds
Started May 07 12:56:03 PM PDT 24
Finished May 07 12:59:08 PM PDT 24
Peak memory 840776 kb
Host smart-bc930ba8-f342-4d27-a572-54b21ea576b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558779099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.2558779099
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.4260233074
Short name T279
Test name
Test status
Simulation time 1896283011 ps
CPU time 6.21 seconds
Started May 07 12:56:16 PM PDT 24
Finished May 07 12:56:24 PM PDT 24
Peak memory 203800 kb
Host smart-f11bf87a-b84f-49ef-85c8-0f1a156831c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260233074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.4260233074
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_override.330095896
Short name T702
Test name
Test status
Simulation time 47408623 ps
CPU time 0.63 seconds
Started May 07 12:56:03 PM PDT 24
Finished May 07 12:56:10 PM PDT 24
Peak memory 203672 kb
Host smart-0e3bbea6-8039-4305-8ecb-f2a9d12bf6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330095896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.330095896
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.3992024633
Short name T726
Test name
Test status
Simulation time 2812116197 ps
CPU time 39.28 seconds
Started May 07 12:56:02 PM PDT 24
Finished May 07 12:56:48 PM PDT 24
Peak memory 225796 kb
Host smart-7e9b398a-aced-448d-9853-a562257f2125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992024633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.3992024633
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.78292809
Short name T316
Test name
Test status
Simulation time 1902421209 ps
CPU time 92.54 seconds
Started May 07 12:56:02 PM PDT 24
Finished May 07 12:57:42 PM PDT 24
Peak memory 344784 kb
Host smart-88e80256-217c-4cdd-86e5-fdf836287067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78292809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.78292809
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.4271968277
Short name T993
Test name
Test status
Simulation time 443599479 ps
CPU time 9.2 seconds
Started May 07 12:56:02 PM PDT 24
Finished May 07 12:56:18 PM PDT 24
Peak memory 212148 kb
Host smart-fd5b90ce-0954-4b3e-b802-c868fc30be4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271968277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.4271968277
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.3288034721
Short name T31
Test name
Test status
Simulation time 461176200 ps
CPU time 2.91 seconds
Started May 07 12:56:03 PM PDT 24
Finished May 07 12:56:12 PM PDT 24
Peak memory 203924 kb
Host smart-f85318dc-c290-41e1-98d3-6bdc380a9947
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288034721 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.3288034721
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.298409574
Short name T787
Test name
Test status
Simulation time 10034205493 ps
CPU time 75.71 seconds
Started May 07 12:56:03 PM PDT 24
Finished May 07 12:57:26 PM PDT 24
Peak memory 416872 kb
Host smart-d9eb0ace-bf89-41a9-8a63-802762781c32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298409574 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_acq.298409574
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.2592715671
Short name T35
Test name
Test status
Simulation time 10139276934 ps
CPU time 34.46 seconds
Started May 07 12:56:02 PM PDT 24
Finished May 07 12:56:43 PM PDT 24
Peak memory 402912 kb
Host smart-edc2da32-556f-43bb-99b4-8b4e3f319249
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592715671 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.2592715671
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.432456856
Short name T227
Test name
Test status
Simulation time 1460675663 ps
CPU time 2.66 seconds
Started May 07 12:56:03 PM PDT 24
Finished May 07 12:56:12 PM PDT 24
Peak memory 203980 kb
Host smart-9b516bb4-6793-4da0-949b-fe887d14698c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432456856 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.i2c_target_hrst.432456856
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3610465265
Short name T594
Test name
Test status
Simulation time 2791796751 ps
CPU time 4.54 seconds
Started May 07 12:56:04 PM PDT 24
Finished May 07 12:56:15 PM PDT 24
Peak memory 203976 kb
Host smart-cbdec911-efb7-4da7-b93d-2eb19d1086d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610465265 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3610465265
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.414596568
Short name T391
Test name
Test status
Simulation time 20773932551 ps
CPU time 45.39 seconds
Started May 07 12:56:02 PM PDT 24
Finished May 07 12:56:54 PM PDT 24
Peak memory 795312 kb
Host smart-4d9279f0-322c-4c7b-b577-1481d636927d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414596568 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.414596568
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.2592555669
Short name T770
Test name
Test status
Simulation time 2314312861 ps
CPU time 16.68 seconds
Started May 07 12:56:03 PM PDT 24
Finished May 07 12:56:26 PM PDT 24
Peak memory 203940 kb
Host smart-c8f9a4fb-7e07-4b08-9c0f-2345ba1736d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592555669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.2592555669
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.2178380914
Short name T416
Test name
Test status
Simulation time 656200186 ps
CPU time 26.48 seconds
Started May 07 12:56:01 PM PDT 24
Finished May 07 12:56:34 PM PDT 24
Peak memory 203852 kb
Host smart-fc775b5c-033b-4ea7-b83f-14a144f4300b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178380914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.2178380914
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.1113382865
Short name T1134
Test name
Test status
Simulation time 24505309457 ps
CPU time 16.64 seconds
Started May 07 12:56:03 PM PDT 24
Finished May 07 12:56:26 PM PDT 24
Peak memory 381252 kb
Host smart-f01ee6c8-d6a6-4f39-8f33-37ae38f63423
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113382865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.1113382865
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.4187671765
Short name T708
Test name
Test status
Simulation time 16047310901 ps
CPU time 87.85 seconds
Started May 07 12:56:03 PM PDT 24
Finished May 07 12:57:38 PM PDT 24
Peak memory 1049788 kb
Host smart-7f4e8258-0818-4a02-90d4-182a1618226e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187671765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.4187671765
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.2695528022
Short name T1191
Test name
Test status
Simulation time 13469385682 ps
CPU time 7.84 seconds
Started May 07 12:56:02 PM PDT 24
Finished May 07 12:56:16 PM PDT 24
Peak memory 220208 kb
Host smart-bf2444c8-4a40-415d-b44f-6eec6653cd85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695528022 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.2695528022
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.289572844
Short name T789
Test name
Test status
Simulation time 51776972 ps
CPU time 0.63 seconds
Started May 07 12:56:14 PM PDT 24
Finished May 07 12:56:18 PM PDT 24
Peak memory 203796 kb
Host smart-7de7827f-080c-49eb-86d8-b647db979058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289572844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.289572844
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.616384855
Short name T1239
Test name
Test status
Simulation time 312036729 ps
CPU time 1.4 seconds
Started May 07 12:56:12 PM PDT 24
Finished May 07 12:56:18 PM PDT 24
Peak memory 212132 kb
Host smart-02ef4855-fab0-4068-9905-e67f4a768d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616384855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.616384855
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.3803249780
Short name T624
Test name
Test status
Simulation time 869922858 ps
CPU time 3.41 seconds
Started May 07 12:56:19 PM PDT 24
Finished May 07 12:56:24 PM PDT 24
Peak memory 228540 kb
Host smart-ac344a0d-5084-4c6e-b174-eeeea9049152
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803249780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.3803249780
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.1593873512
Short name T1304
Test name
Test status
Simulation time 1120135642 ps
CPU time 29.19 seconds
Started May 07 12:56:08 PM PDT 24
Finished May 07 12:56:43 PM PDT 24
Peak memory 467572 kb
Host smart-c1acba74-76c4-44ea-abf2-8f8d5a5ddf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593873512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.1593873512
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.3727286013
Short name T887
Test name
Test status
Simulation time 1196577618 ps
CPU time 79.91 seconds
Started May 07 12:56:09 PM PDT 24
Finished May 07 12:57:34 PM PDT 24
Peak memory 495348 kb
Host smart-0792ab25-d801-46ae-b96c-279af1b37e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727286013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.3727286013
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.2458962630
Short name T1229
Test name
Test status
Simulation time 99040985 ps
CPU time 1.01 seconds
Started May 07 12:56:08 PM PDT 24
Finished May 07 12:56:15 PM PDT 24
Peak memory 203724 kb
Host smart-96bf16b5-3682-43e7-b676-3a3f3c760ab8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458962630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.2458962630
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.3115031556
Short name T655
Test name
Test status
Simulation time 3217747287 ps
CPU time 215.09 seconds
Started May 07 12:56:09 PM PDT 24
Finished May 07 12:59:50 PM PDT 24
Peak memory 970996 kb
Host smart-ebd2efbe-cf04-4f82-9047-8a72a80caf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115031556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.3115031556
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.933866072
Short name T298
Test name
Test status
Simulation time 877672120 ps
CPU time 6.97 seconds
Started May 07 12:56:16 PM PDT 24
Finished May 07 12:56:25 PM PDT 24
Peak memory 203964 kb
Host smart-59aa072e-88f9-44ac-b519-80fb59d0741c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933866072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.933866072
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.1289865788
Short name T1035
Test name
Test status
Simulation time 6859630145 ps
CPU time 66.05 seconds
Started May 07 12:56:15 PM PDT 24
Finished May 07 12:57:24 PM PDT 24
Peak memory 364884 kb
Host smart-088a1a2c-8945-45cd-b296-e7e1927231b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289865788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.1289865788
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.155428103
Short name T206
Test name
Test status
Simulation time 31729928 ps
CPU time 0.67 seconds
Started May 07 12:56:09 PM PDT 24
Finished May 07 12:56:15 PM PDT 24
Peak memory 203692 kb
Host smart-4bf75038-e95e-4251-8149-f36f1cb6654c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155428103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.155428103
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.969039351
Short name T903
Test name
Test status
Simulation time 3144788961 ps
CPU time 26.63 seconds
Started May 07 12:56:10 PM PDT 24
Finished May 07 12:56:41 PM PDT 24
Peak memory 204012 kb
Host smart-d661d5cf-8a88-431c-82b7-86b41cb54bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969039351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.969039351
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.579240081
Short name T1146
Test name
Test status
Simulation time 10058120700 ps
CPU time 78.76 seconds
Started May 07 12:56:11 PM PDT 24
Finished May 07 12:57:34 PM PDT 24
Peak memory 346504 kb
Host smart-f0716eaf-bf9e-4cf9-9ad5-625e33804475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579240081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.579240081
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.2357292564
Short name T126
Test name
Test status
Simulation time 16954970448 ps
CPU time 203.64 seconds
Started May 07 12:56:09 PM PDT 24
Finished May 07 12:59:38 PM PDT 24
Peak memory 912828 kb
Host smart-5510bf32-6e79-469e-a8d7-1e81a6142c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357292564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.2357292564
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.3019042913
Short name T513
Test name
Test status
Simulation time 3028377529 ps
CPU time 16.31 seconds
Started May 07 12:56:14 PM PDT 24
Finished May 07 12:56:33 PM PDT 24
Peak memory 228320 kb
Host smart-8c000cb4-d213-48ca-b418-8cf99f72e2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019042913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3019042913
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.387951065
Short name T613
Test name
Test status
Simulation time 4401672455 ps
CPU time 5.92 seconds
Started May 07 12:56:08 PM PDT 24
Finished May 07 12:56:19 PM PDT 24
Peak memory 210024 kb
Host smart-f26e56fa-cefc-4347-a454-52e27a768bcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387951065 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.387951065
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.3083893301
Short name T1073
Test name
Test status
Simulation time 10069246190 ps
CPU time 30.14 seconds
Started May 07 12:56:21 PM PDT 24
Finished May 07 12:56:53 PM PDT 24
Peak memory 347096 kb
Host smart-d395e43b-c200-48f8-947e-60eee38025a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083893301 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.3083893301
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.342776200
Short name T411
Test name
Test status
Simulation time 10190531157 ps
CPU time 35.27 seconds
Started May 07 12:56:11 PM PDT 24
Finished May 07 12:56:51 PM PDT 24
Peak memory 345396 kb
Host smart-de9dfeae-8880-4a29-ab28-1029546c891f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342776200 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_fifo_reset_tx.342776200
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.198432897
Short name T1356
Test name
Test status
Simulation time 284121055 ps
CPU time 2.01 seconds
Started May 07 12:56:12 PM PDT 24
Finished May 07 12:56:18 PM PDT 24
Peak memory 203816 kb
Host smart-afe71f7c-cbae-4f08-a7e8-23b726272105
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198432897 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.i2c_target_hrst.198432897
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.1531128683
Short name T1121
Test name
Test status
Simulation time 711920365 ps
CPU time 4.17 seconds
Started May 07 12:56:12 PM PDT 24
Finished May 07 12:56:20 PM PDT 24
Peak memory 203900 kb
Host smart-ac9d10b3-533a-4c49-a22a-abc3d93ed037
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531128683 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.1531128683
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.299024812
Short name T1101
Test name
Test status
Simulation time 12059944245 ps
CPU time 7.8 seconds
Started May 07 12:56:09 PM PDT 24
Finished May 07 12:56:22 PM PDT 24
Peak memory 225564 kb
Host smart-1d45604f-cdb6-4f31-a667-14a8270ed233
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299024812 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.299024812
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.2983892000
Short name T233
Test name
Test status
Simulation time 2578374153 ps
CPU time 25.93 seconds
Started May 07 12:56:09 PM PDT 24
Finished May 07 12:56:40 PM PDT 24
Peak memory 203900 kb
Host smart-1533cd26-84e0-409d-bd0e-b980998645cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983892000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.2983892000
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3999558129
Short name T427
Test name
Test status
Simulation time 316983249 ps
CPU time 5 seconds
Started May 07 12:56:10 PM PDT 24
Finished May 07 12:56:19 PM PDT 24
Peak memory 203940 kb
Host smart-98edb297-897e-41e0-b8d6-a7259c51e52c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999558129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3999558129
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.2380342983
Short name T595
Test name
Test status
Simulation time 20795451124 ps
CPU time 45.29 seconds
Started May 07 12:56:14 PM PDT 24
Finished May 07 12:57:02 PM PDT 24
Peak memory 300096 kb
Host smart-f2788ef6-160d-4978-bd14-5387c8809b9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380342983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.2380342983
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.3616681560
Short name T777
Test name
Test status
Simulation time 4742491779 ps
CPU time 7.12 seconds
Started May 07 12:56:10 PM PDT 24
Finished May 07 12:56:22 PM PDT 24
Peak memory 220196 kb
Host smart-6560081d-ef5f-4e39-a38f-c8d40e8dfc39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616681560 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.3616681560
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3682480099
Short name T897
Test name
Test status
Simulation time 18147677 ps
CPU time 0.63 seconds
Started May 07 12:56:25 PM PDT 24
Finished May 07 12:56:27 PM PDT 24
Peak memory 203804 kb
Host smart-ea8feb5d-9e70-40b3-80f3-eaf35a194e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682480099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3682480099
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.1058382772
Short name T678
Test name
Test status
Simulation time 158263745 ps
CPU time 1.72 seconds
Started May 07 12:56:15 PM PDT 24
Finished May 07 12:56:20 PM PDT 24
Peak memory 212188 kb
Host smart-45b07f2d-fca4-4a53-9adc-cd45150dbf7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058382772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.1058382772
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.1304649709
Short name T484
Test name
Test status
Simulation time 152343721 ps
CPU time 3.02 seconds
Started May 07 12:56:21 PM PDT 24
Finished May 07 12:56:26 PM PDT 24
Peak memory 229400 kb
Host smart-fdc1075c-254e-4255-a25f-56152d0b6cd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304649709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.1304649709
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.3349376004
Short name T519
Test name
Test status
Simulation time 2135246075 ps
CPU time 69.93 seconds
Started May 07 12:56:14 PM PDT 24
Finished May 07 12:57:27 PM PDT 24
Peak memory 622464 kb
Host smart-949877f5-9b47-4274-b91e-e1c1549effc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349376004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3349376004
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.733806629
Short name T459
Test name
Test status
Simulation time 8966788892 ps
CPU time 94.8 seconds
Started May 07 12:56:21 PM PDT 24
Finished May 07 12:57:57 PM PDT 24
Peak memory 514600 kb
Host smart-12c073c8-d00f-4955-879d-c76c47459373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733806629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.733806629
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.1061792751
Short name T716
Test name
Test status
Simulation time 387045639 ps
CPU time 1.13 seconds
Started May 07 12:56:14 PM PDT 24
Finished May 07 12:56:19 PM PDT 24
Peak memory 203940 kb
Host smart-ddcc68c2-6a82-47b1-952b-3d4e9b1f01d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061792751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.1061792751
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.3185532653
Short name T465
Test name
Test status
Simulation time 453991566 ps
CPU time 3.12 seconds
Started May 07 12:56:23 PM PDT 24
Finished May 07 12:56:27 PM PDT 24
Peak memory 203900 kb
Host smart-ac8e0233-2159-492b-853d-b1a3be0e6e32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185532653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.3185532653
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.1573032188
Short name T61
Test name
Test status
Simulation time 16205315400 ps
CPU time 124.48 seconds
Started May 07 12:56:17 PM PDT 24
Finished May 07 12:58:24 PM PDT 24
Peak memory 1170516 kb
Host smart-aa1f0c66-e40e-49ec-920f-57f76c164f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573032188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.1573032188
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.830560744
Short name T224
Test name
Test status
Simulation time 1626708613 ps
CPU time 14.48 seconds
Started May 07 12:56:24 PM PDT 24
Finished May 07 12:56:40 PM PDT 24
Peak memory 203964 kb
Host smart-4ed5b777-3241-479d-90ac-a060794b2ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830560744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.830560744
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.4061573792
Short name T501
Test name
Test status
Simulation time 6399550181 ps
CPU time 27.9 seconds
Started May 07 12:56:26 PM PDT 24
Finished May 07 12:56:55 PM PDT 24
Peak memory 277952 kb
Host smart-4edefff9-92c3-4990-ac5c-0358f956627b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061573792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.4061573792
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.1428779784
Short name T1100
Test name
Test status
Simulation time 27602331 ps
CPU time 0.65 seconds
Started May 07 12:56:14 PM PDT 24
Finished May 07 12:56:18 PM PDT 24
Peak memory 203748 kb
Host smart-a22e223a-0f5a-492b-a781-0a74b8140aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428779784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.1428779784
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.3989903533
Short name T45
Test name
Test status
Simulation time 26934277585 ps
CPU time 566.49 seconds
Started May 07 12:56:23 PM PDT 24
Finished May 07 01:05:51 PM PDT 24
Peak memory 1444024 kb
Host smart-9cedef6d-aa06-4a41-9a12-75da6ad0c0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989903533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.3989903533
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.437909008
Short name T743
Test name
Test status
Simulation time 1058646227 ps
CPU time 53.9 seconds
Started May 07 12:56:15 PM PDT 24
Finished May 07 12:57:12 PM PDT 24
Peak memory 309756 kb
Host smart-eb17cf5e-b983-4899-9e74-1d0181a8b3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437909008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.437909008
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.2444237286
Short name T181
Test name
Test status
Simulation time 13350178699 ps
CPU time 564.66 seconds
Started May 07 12:56:14 PM PDT 24
Finished May 07 01:05:42 PM PDT 24
Peak memory 1319452 kb
Host smart-0332f9f0-4a92-4d1b-996f-328e71da559e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444237286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.2444237286
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3828779227
Short name T907
Test name
Test status
Simulation time 400748377 ps
CPU time 7.04 seconds
Started May 07 12:56:15 PM PDT 24
Finished May 07 12:56:25 PM PDT 24
Peak memory 212104 kb
Host smart-b2b0bebe-28d4-46f4-ae26-3e155b9e63dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828779227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3828779227
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.1141130986
Short name T472
Test name
Test status
Simulation time 631128717 ps
CPU time 3.35 seconds
Started May 07 12:56:25 PM PDT 24
Finished May 07 12:56:29 PM PDT 24
Peak memory 203896 kb
Host smart-692c2e38-da49-442e-91b9-3f31fb134686
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141130986 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.1141130986
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.23781956
Short name T1342
Test name
Test status
Simulation time 10214462356 ps
CPU time 29.61 seconds
Started May 07 12:56:25 PM PDT 24
Finished May 07 12:56:56 PM PDT 24
Peak memory 315160 kb
Host smart-f72ef746-0895-4cb9-bf0a-b391cd1ae187
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23781956 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_fifo_reset_acq.23781956
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.365789350
Short name T582
Test name
Test status
Simulation time 10160840367 ps
CPU time 34.41 seconds
Started May 07 12:56:21 PM PDT 24
Finished May 07 12:56:56 PM PDT 24
Peak memory 385392 kb
Host smart-256c873f-a9f1-4e1c-ab69-010eac419c0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365789350 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_fifo_reset_tx.365789350
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.2107370776
Short name T29
Test name
Test status
Simulation time 1215397299 ps
CPU time 2.55 seconds
Started May 07 12:56:26 PM PDT 24
Finished May 07 12:56:30 PM PDT 24
Peak memory 203908 kb
Host smart-8ee4ce47-5add-4753-a2c0-3730ce57e8b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107370776 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.2107370776
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.638378452
Short name T1325
Test name
Test status
Simulation time 4038834159 ps
CPU time 5.23 seconds
Started May 07 12:56:24 PM PDT 24
Finished May 07 12:56:30 PM PDT 24
Peak memory 207948 kb
Host smart-ef9399dc-689e-4223-b9c0-48c5e5619a4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638378452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_intr_smoke.638378452
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.2201472535
Short name T12
Test name
Test status
Simulation time 22203198780 ps
CPU time 12.3 seconds
Started May 07 12:56:21 PM PDT 24
Finished May 07 12:56:35 PM PDT 24
Peak memory 409564 kb
Host smart-f71d2a39-b055-4b66-87bb-b28b4333dc83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201472535 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.2201472535
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.3614155844
Short name T1165
Test name
Test status
Simulation time 1864562655 ps
CPU time 13.52 seconds
Started May 07 12:56:15 PM PDT 24
Finished May 07 12:56:31 PM PDT 24
Peak memory 203836 kb
Host smart-57559a04-6d15-4be7-8e1a-113f6b519367
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614155844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.3614155844
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.1730345881
Short name T858
Test name
Test status
Simulation time 2496663970 ps
CPU time 51.63 seconds
Started May 07 12:56:19 PM PDT 24
Finished May 07 12:57:12 PM PDT 24
Peak memory 204436 kb
Host smart-075a9fd3-50de-4672-9434-8475c65295de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730345881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.1730345881
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.695024756
Short name T1245
Test name
Test status
Simulation time 28841393129 ps
CPU time 29.17 seconds
Started May 07 12:56:14 PM PDT 24
Finished May 07 12:56:46 PM PDT 24
Peak memory 638156 kb
Host smart-fbbad8ea-61cf-4929-b1ce-59b1cd690af9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695024756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_wr.695024756
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.2029440849
Short name T616
Test name
Test status
Simulation time 17590901759 ps
CPU time 906.06 seconds
Started May 07 12:56:21 PM PDT 24
Finished May 07 01:11:29 PM PDT 24
Peak memory 2222612 kb
Host smart-fc1dd397-9e3b-4a2a-8446-3b2a52216ec8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029440849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.2029440849
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.2556463970
Short name T237
Test name
Test status
Simulation time 13439556108 ps
CPU time 6.98 seconds
Started May 07 12:56:24 PM PDT 24
Finished May 07 12:56:32 PM PDT 24
Peak memory 212192 kb
Host smart-cbe8bd53-288c-48df-9813-85b99e5c34a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556463970 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.2556463970
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_unexp_stop.4251600153
Short name T17
Test name
Test status
Simulation time 2542160528 ps
CPU time 4.39 seconds
Started May 07 12:56:24 PM PDT 24
Finished May 07 12:56:30 PM PDT 24
Peak memory 203968 kb
Host smart-f73fb6b7-988b-4b12-aa8a-5a847742054f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251600153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.i2c_target_unexp_stop.4251600153
Directory /workspace/27.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/28.i2c_alert_test.3425698394
Short name T574
Test name
Test status
Simulation time 184122698 ps
CPU time 0.62 seconds
Started May 07 12:56:34 PM PDT 24
Finished May 07 12:56:35 PM PDT 24
Peak memory 203816 kb
Host smart-513be01a-94f1-4154-8804-2467c04675d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425698394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.3425698394
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.4228462355
Short name T1302
Test name
Test status
Simulation time 201703969 ps
CPU time 1.33 seconds
Started May 07 12:56:26 PM PDT 24
Finished May 07 12:56:29 PM PDT 24
Peak memory 212224 kb
Host smart-0d85e68c-4692-477c-93e6-8dd6671b546f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228462355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.4228462355
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.52453148
Short name T485
Test name
Test status
Simulation time 273691360 ps
CPU time 14.24 seconds
Started May 07 12:56:21 PM PDT 24
Finished May 07 12:56:37 PM PDT 24
Peak memory 261668 kb
Host smart-46505865-d9e1-4dc2-b6d6-ea62537eac92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52453148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empty
.52453148
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3879283696
Short name T1114
Test name
Test status
Simulation time 8669113162 ps
CPU time 160.66 seconds
Started May 07 12:56:30 PM PDT 24
Finished May 07 12:59:12 PM PDT 24
Peak memory 745452 kb
Host smart-a177b245-e773-460d-b650-0bba6130bec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879283696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3879283696
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.1886152884
Short name T57
Test name
Test status
Simulation time 2065994637 ps
CPU time 60.17 seconds
Started May 07 12:56:26 PM PDT 24
Finished May 07 12:57:27 PM PDT 24
Peak memory 699832 kb
Host smart-d16e8a86-62c7-4230-9c25-c231e9970286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886152884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.1886152884
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.1042683599
Short name T415
Test name
Test status
Simulation time 375460363 ps
CPU time 0.96 seconds
Started May 07 12:56:24 PM PDT 24
Finished May 07 12:56:26 PM PDT 24
Peak memory 203776 kb
Host smart-35587188-2970-4794-b21c-654385ad3cbb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042683599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.1042683599
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.4284783112
Short name T1157
Test name
Test status
Simulation time 567418427 ps
CPU time 7.22 seconds
Started May 07 12:56:26 PM PDT 24
Finished May 07 12:56:34 PM PDT 24
Peak memory 223752 kb
Host smart-e4508c9a-bbea-426e-a52f-9d3da0bb3bd6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284783112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.4284783112
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.1662847362
Short name T1328
Test name
Test status
Simulation time 16776804917 ps
CPU time 262.1 seconds
Started May 07 12:56:21 PM PDT 24
Finished May 07 01:00:45 PM PDT 24
Peak memory 1097812 kb
Host smart-5b48ebca-d3be-450f-a20a-ea0aa246a1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662847362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.1662847362
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.2064029871
Short name T1223
Test name
Test status
Simulation time 222289138 ps
CPU time 3.76 seconds
Started May 07 12:56:36 PM PDT 24
Finished May 07 12:56:41 PM PDT 24
Peak memory 203796 kb
Host smart-8e22ff0d-2ec5-42d2-9a98-eb4d8e6432fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064029871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.2064029871
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.481715863
Short name T882
Test name
Test status
Simulation time 5678114482 ps
CPU time 21.22 seconds
Started May 07 12:56:34 PM PDT 24
Finished May 07 12:56:56 PM PDT 24
Peak memory 325468 kb
Host smart-9e24e129-42f1-4e23-b48e-8c8ebb776462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481715863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.481715863
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.3606427940
Short name T663
Test name
Test status
Simulation time 30829969 ps
CPU time 0.69 seconds
Started May 07 12:56:21 PM PDT 24
Finished May 07 12:56:23 PM PDT 24
Peak memory 203732 kb
Host smart-2de72941-892d-4987-b0c8-0079365433c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606427940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.3606427940
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.1663831628
Short name T749
Test name
Test status
Simulation time 7062411256 ps
CPU time 9.75 seconds
Started May 07 12:56:27 PM PDT 24
Finished May 07 12:56:38 PM PDT 24
Peak memory 203924 kb
Host smart-275ec5b9-0665-4b16-bd51-be87d5a96fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663831628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.1663831628
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1778273998
Short name T855
Test name
Test status
Simulation time 1730903001 ps
CPU time 26.2 seconds
Started May 07 12:56:22 PM PDT 24
Finished May 07 12:56:50 PM PDT 24
Peak memory 294520 kb
Host smart-2daebf8e-c280-4668-87f5-01324c1826d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778273998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1778273998
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.2742565218
Short name T64
Test name
Test status
Simulation time 25843708659 ps
CPU time 1323.47 seconds
Started May 07 12:56:28 PM PDT 24
Finished May 07 01:18:32 PM PDT 24
Peak memory 2447708 kb
Host smart-a5f0baed-b23b-488a-8419-cc68d0fc2882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742565218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.2742565218
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.1701320701
Short name T363
Test name
Test status
Simulation time 1190843248 ps
CPU time 9.69 seconds
Started May 07 12:56:30 PM PDT 24
Finished May 07 12:56:41 PM PDT 24
Peak memory 212152 kb
Host smart-71d6683e-1bd6-4852-a0b6-ba3369e5136c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701320701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.1701320701
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.1089178911
Short name T744
Test name
Test status
Simulation time 4559423007 ps
CPU time 4.13 seconds
Started May 07 12:56:36 PM PDT 24
Finished May 07 12:56:42 PM PDT 24
Peak memory 212164 kb
Host smart-859ee6e6-0a91-4128-8ce3-24141da5adff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089178911 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.1089178911
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.2491509398
Short name T1294
Test name
Test status
Simulation time 10426369075 ps
CPU time 13.63 seconds
Started May 07 12:56:27 PM PDT 24
Finished May 07 12:56:41 PM PDT 24
Peak memory 264348 kb
Host smart-71858603-243d-418c-8e9d-6949a6a5c7f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491509398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.2491509398
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.345213359
Short name T985
Test name
Test status
Simulation time 10156081962 ps
CPU time 17.72 seconds
Started May 07 12:56:33 PM PDT 24
Finished May 07 12:56:52 PM PDT 24
Peak memory 296176 kb
Host smart-32bc75a2-1829-42db-ba79-9752ff7b68a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345213359 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_fifo_reset_tx.345213359
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.3106700376
Short name T24
Test name
Test status
Simulation time 557591876 ps
CPU time 3.17 seconds
Started May 07 12:56:36 PM PDT 24
Finished May 07 12:56:41 PM PDT 24
Peak memory 203888 kb
Host smart-e3820a03-6b8b-4d20-91a2-469951884cf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106700376 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.3106700376
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.4031049356
Short name T975
Test name
Test status
Simulation time 10353344516 ps
CPU time 21.85 seconds
Started May 07 12:56:26 PM PDT 24
Finished May 07 12:56:49 PM PDT 24
Peak memory 542080 kb
Host smart-ad6f96ef-adbc-4a67-8d18-516ad5052345
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031049356 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.4031049356
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.3870093104
Short name T462
Test name
Test status
Simulation time 3485804891 ps
CPU time 13.77 seconds
Started May 07 12:56:30 PM PDT 24
Finished May 07 12:56:44 PM PDT 24
Peak memory 203948 kb
Host smart-a4551849-3ed0-4520-b32a-926360da85e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870093104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.3870093104
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.2560350404
Short name T1334
Test name
Test status
Simulation time 10771870749 ps
CPU time 8.27 seconds
Started May 07 12:56:25 PM PDT 24
Finished May 07 12:56:35 PM PDT 24
Peak memory 209532 kb
Host smart-a4219ebe-c8f7-4700-b7af-33b473d002fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560350404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.2560350404
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.1404357011
Short name T1065
Test name
Test status
Simulation time 50469653592 ps
CPU time 28.49 seconds
Started May 07 12:56:27 PM PDT 24
Finished May 07 12:56:57 PM PDT 24
Peak memory 564324 kb
Host smart-a7688d45-a05c-4d28-9df1-f1844c39c474
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404357011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.1404357011
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.1720553277
Short name T742
Test name
Test status
Simulation time 13893589632 ps
CPU time 66.37 seconds
Started May 07 12:56:29 PM PDT 24
Finished May 07 12:57:36 PM PDT 24
Peak memory 766568 kb
Host smart-d27631aa-4d6e-4827-a0a1-59ac99c666d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720553277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.1720553277
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.3398989840
Short name T1194
Test name
Test status
Simulation time 16679576459 ps
CPU time 6.46 seconds
Started May 07 12:56:28 PM PDT 24
Finished May 07 12:56:35 PM PDT 24
Peak memory 220280 kb
Host smart-decd8333-5fc0-4e22-bb5d-1608a3957dcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398989840 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.3398989840
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.2758552915
Short name T634
Test name
Test status
Simulation time 176029673 ps
CPU time 0.64 seconds
Started May 07 12:56:48 PM PDT 24
Finished May 07 12:56:51 PM PDT 24
Peak memory 203756 kb
Host smart-eb734db7-d1d8-4261-8738-c6795f2e302e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758552915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.2758552915
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.2105803280
Short name T896
Test name
Test status
Simulation time 173229132 ps
CPU time 1.4 seconds
Started May 07 12:56:40 PM PDT 24
Finished May 07 12:56:44 PM PDT 24
Peak memory 212268 kb
Host smart-79987b23-e06a-425c-a23d-ef59e6dad038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105803280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.2105803280
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.2867913118
Short name T1143
Test name
Test status
Simulation time 676277112 ps
CPU time 14.93 seconds
Started May 07 12:56:41 PM PDT 24
Finished May 07 12:56:58 PM PDT 24
Peak memory 263368 kb
Host smart-ddde5a62-7dae-44fc-959e-8c4d88a11814
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867913118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.2867913118
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.548333501
Short name T1330
Test name
Test status
Simulation time 2205160605 ps
CPU time 37.71 seconds
Started May 07 12:56:40 PM PDT 24
Finished May 07 12:57:20 PM PDT 24
Peak memory 455884 kb
Host smart-676efe47-9433-4e92-b85f-e7abe53946a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548333501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.548333501
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.2047771218
Short name T199
Test name
Test status
Simulation time 1914613449 ps
CPU time 49.81 seconds
Started May 07 12:56:35 PM PDT 24
Finished May 07 12:57:26 PM PDT 24
Peak memory 598796 kb
Host smart-86325a3a-4a1d-445b-a2b1-c24b5db01074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047771218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.2047771218
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1716026152
Short name T653
Test name
Test status
Simulation time 168863904 ps
CPU time 0.79 seconds
Started May 07 12:56:39 PM PDT 24
Finished May 07 12:56:42 PM PDT 24
Peak memory 203756 kb
Host smart-80e22bdd-1482-4883-8c3b-849bcbbd3863
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716026152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1716026152
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.3210532333
Short name T214
Test name
Test status
Simulation time 254438991 ps
CPU time 3.17 seconds
Started May 07 12:56:41 PM PDT 24
Finished May 07 12:56:46 PM PDT 24
Peak memory 222420 kb
Host smart-559b818e-b2b5-4b3a-8edf-5b6d9e4dfd9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210532333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.3210532333
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.1658472549
Short name T730
Test name
Test status
Simulation time 19942781001 ps
CPU time 132.82 seconds
Started May 07 12:56:33 PM PDT 24
Finished May 07 12:58:46 PM PDT 24
Peak memory 1221600 kb
Host smart-a5cfb90f-49a6-479f-99bf-11d9337a7f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658472549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1658472549
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.4152536627
Short name T773
Test name
Test status
Simulation time 419289377 ps
CPU time 6.92 seconds
Started May 07 12:56:46 PM PDT 24
Finished May 07 12:56:54 PM PDT 24
Peak memory 203880 kb
Host smart-b663ffd1-1f19-43bd-b47e-58e66d9b7d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152536627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.4152536627
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.1867238827
Short name T1117
Test name
Test status
Simulation time 2411136304 ps
CPU time 48.49 seconds
Started May 07 12:56:47 PM PDT 24
Finished May 07 12:57:36 PM PDT 24
Peak memory 481316 kb
Host smart-fbefe5d5-43a3-433d-a566-587b0cba2875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867238827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.1867238827
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.3692990218
Short name T511
Test name
Test status
Simulation time 31835928 ps
CPU time 0.64 seconds
Started May 07 12:56:32 PM PDT 24
Finished May 07 12:56:33 PM PDT 24
Peak memory 203724 kb
Host smart-723e3621-a757-4d02-8483-c3767e183943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692990218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3692990218
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.1206121976
Short name T635
Test name
Test status
Simulation time 13044306964 ps
CPU time 56.02 seconds
Started May 07 12:56:40 PM PDT 24
Finished May 07 12:57:38 PM PDT 24
Peak memory 574848 kb
Host smart-f45b5c21-d4cf-4a0e-8a62-78b1616d635a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206121976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.1206121976
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.768248148
Short name T1088
Test name
Test status
Simulation time 6029219167 ps
CPU time 23.86 seconds
Started May 07 12:56:34 PM PDT 24
Finished May 07 12:57:00 PM PDT 24
Peak memory 333660 kb
Host smart-32ec1d65-3948-4bfa-8a6a-2ce4aaab8e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768248148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.768248148
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.271891881
Short name T733
Test name
Test status
Simulation time 7277331369 ps
CPU time 544.05 seconds
Started May 07 12:56:42 PM PDT 24
Finished May 07 01:05:48 PM PDT 24
Peak memory 993072 kb
Host smart-915e2a01-0d91-4275-b861-75af3cdcf11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271891881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.271891881
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.4128405107
Short name T1000
Test name
Test status
Simulation time 387133790 ps
CPU time 7.17 seconds
Started May 07 12:56:42 PM PDT 24
Finished May 07 12:56:51 PM PDT 24
Peak memory 212056 kb
Host smart-3092c0e2-ea19-4324-a6ed-ef411662f511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128405107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.4128405107
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.288732036
Short name T1244
Test name
Test status
Simulation time 3541204234 ps
CPU time 5.26 seconds
Started May 07 12:56:42 PM PDT 24
Finished May 07 12:56:49 PM PDT 24
Peak memory 219836 kb
Host smart-4afbbd7a-01d7-4360-9dfc-6b06a5086788
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288732036 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.288732036
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.1465208620
Short name T1056
Test name
Test status
Simulation time 10357379785 ps
CPU time 10.43 seconds
Started May 07 12:56:41 PM PDT 24
Finished May 07 12:56:54 PM PDT 24
Peak memory 243600 kb
Host smart-84aa1101-01c0-473d-a18c-5052388ce9fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465208620 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.1465208620
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.50195479
Short name T920
Test name
Test status
Simulation time 10183979729 ps
CPU time 13.93 seconds
Started May 07 12:56:39 PM PDT 24
Finished May 07 12:56:55 PM PDT 24
Peak memory 266728 kb
Host smart-421850c0-ec6c-420d-a973-5bfd16d6762b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50195479 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_fifo_reset_tx.50195479
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.91122033
Short name T1209
Test name
Test status
Simulation time 1649977451 ps
CPU time 2.9 seconds
Started May 07 12:56:41 PM PDT 24
Finished May 07 12:56:47 PM PDT 24
Peak memory 203868 kb
Host smart-0f7cc630-a41e-42e0-b41b-a438c143574c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91122033 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 29.i2c_target_hrst.91122033
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.2694001047
Short name T1246
Test name
Test status
Simulation time 5015872387 ps
CPU time 6.72 seconds
Started May 07 12:56:43 PM PDT 24
Finished May 07 12:56:52 PM PDT 24
Peak memory 220148 kb
Host smart-b6189815-3034-45f9-8e32-a433a3fb77d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694001047 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.2694001047
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.303218481
Short name T430
Test name
Test status
Simulation time 14968076449 ps
CPU time 31.36 seconds
Started May 07 12:56:39 PM PDT 24
Finished May 07 12:57:13 PM PDT 24
Peak memory 596996 kb
Host smart-6f0b251e-533a-4bcf-8e4e-0aeb0aa11132
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303218481 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.303218481
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.1240705689
Short name T489
Test name
Test status
Simulation time 1085423027 ps
CPU time 13 seconds
Started May 07 12:56:39 PM PDT 24
Finished May 07 12:56:54 PM PDT 24
Peak memory 203868 kb
Host smart-bd6bcdfc-0777-4434-98a5-d71ab7373151
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240705689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.1240705689
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.2718814805
Short name T1139
Test name
Test status
Simulation time 2746076693 ps
CPU time 24.69 seconds
Started May 07 12:56:41 PM PDT 24
Finished May 07 12:57:08 PM PDT 24
Peak memory 229364 kb
Host smart-73a9547f-fb57-41f4-8abf-97960062f766
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718814805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.2718814805
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.3103740937
Short name T633
Test name
Test status
Simulation time 46490965213 ps
CPU time 330.81 seconds
Started May 07 12:56:40 PM PDT 24
Finished May 07 01:02:13 PM PDT 24
Peak memory 3392440 kb
Host smart-532a0c22-fb0a-4957-b3f5-029ec0e157fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103740937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.3103740937
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.545250951
Short name T1203
Test name
Test status
Simulation time 6655562798 ps
CPU time 31.09 seconds
Started May 07 12:56:39 PM PDT 24
Finished May 07 12:57:13 PM PDT 24
Peak memory 531620 kb
Host smart-71757e54-588c-4a7d-b5eb-f716cf4680fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545250951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_t
arget_stretch.545250951
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.155982816
Short name T880
Test name
Test status
Simulation time 8037410743 ps
CPU time 7.64 seconds
Started May 07 12:56:41 PM PDT 24
Finished May 07 12:56:51 PM PDT 24
Peak memory 220276 kb
Host smart-18c1e383-ef42-4928-a343-a0ef3cb60449
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155982816 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_timeout.155982816
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.3550481790
Short name T1038
Test name
Test status
Simulation time 30488719 ps
CPU time 0.62 seconds
Started May 07 12:52:40 PM PDT 24
Finished May 07 12:52:42 PM PDT 24
Peak memory 203828 kb
Host smart-5d66d299-d6df-4cef-a106-d74bbce50e00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550481790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.3550481790
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.1493285649
Short name T80
Test name
Test status
Simulation time 103001364 ps
CPU time 1.27 seconds
Started May 07 12:52:33 PM PDT 24
Finished May 07 12:52:35 PM PDT 24
Peak memory 212152 kb
Host smart-58041a92-c8b5-493b-b5f1-f3805acccdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493285649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.1493285649
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.668804617
Short name T814
Test name
Test status
Simulation time 146125071 ps
CPU time 6.5 seconds
Started May 07 12:52:31 PM PDT 24
Finished May 07 12:52:38 PM PDT 24
Peak memory 222408 kb
Host smart-9109eb52-9204-492a-9913-92cd04e1f39e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668804617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty
.668804617
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.1860033999
Short name T547
Test name
Test status
Simulation time 2393344553 ps
CPU time 86.19 seconds
Started May 07 12:52:32 PM PDT 24
Finished May 07 12:53:59 PM PDT 24
Peak memory 774164 kb
Host smart-ffe6c4e5-8707-4994-832d-8f84af7bcda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860033999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.1860033999
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.817247984
Short name T1227
Test name
Test status
Simulation time 4646149507 ps
CPU time 34.73 seconds
Started May 07 12:52:24 PM PDT 24
Finished May 07 12:53:00 PM PDT 24
Peak memory 455196 kb
Host smart-3fd66cf2-cdc4-4217-b627-38bdca9cde27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817247984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.817247984
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.1722639112
Short name T728
Test name
Test status
Simulation time 99796858 ps
CPU time 0.95 seconds
Started May 07 12:52:27 PM PDT 24
Finished May 07 12:52:30 PM PDT 24
Peak memory 203724 kb
Host smart-6e5cb0db-3552-4ceb-841f-79dc5148e362
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722639112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.1722639112
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.11221518
Short name T10
Test name
Test status
Simulation time 583639936 ps
CPU time 3.3 seconds
Started May 07 12:52:32 PM PDT 24
Finished May 07 12:52:37 PM PDT 24
Peak memory 203896 kb
Host smart-b23ad12c-d36f-4737-881f-9279af936c1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11221518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.11221518
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.2365464983
Short name T936
Test name
Test status
Simulation time 4596634033 ps
CPU time 61.24 seconds
Started May 07 12:52:27 PM PDT 24
Finished May 07 12:53:30 PM PDT 24
Peak memory 764792 kb
Host smart-182735bc-13fb-4462-a1e0-86785b6c2a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365464983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.2365464983
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.929803637
Short name T879
Test name
Test status
Simulation time 293851754 ps
CPU time 11.62 seconds
Started May 07 12:52:37 PM PDT 24
Finished May 07 12:52:50 PM PDT 24
Peak memory 203924 kb
Host smart-713fd182-e673-432a-a2b3-27d5708102c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929803637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.929803637
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.2361362890
Short name T1221
Test name
Test status
Simulation time 6492557380 ps
CPU time 84.51 seconds
Started May 07 12:52:40 PM PDT 24
Finished May 07 12:54:05 PM PDT 24
Peak memory 430692 kb
Host smart-bb0ba965-daad-456f-b0fc-7dc8f1b2b689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361362890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.2361362890
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.3019122511
Short name T910
Test name
Test status
Simulation time 27947148 ps
CPU time 0.71 seconds
Started May 07 12:52:27 PM PDT 24
Finished May 07 12:52:30 PM PDT 24
Peak memory 203596 kb
Host smart-6e4dc4da-f6fe-4a63-b87b-1f43c6e77979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019122511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3019122511
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.1116966946
Short name T990
Test name
Test status
Simulation time 2896000268 ps
CPU time 58.01 seconds
Started May 07 12:52:30 PM PDT 24
Finished May 07 12:53:30 PM PDT 24
Peak memory 204196 kb
Host smart-bb844578-e79a-4664-a507-d9dd8993381d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116966946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.1116966946
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.3344195301
Short name T571
Test name
Test status
Simulation time 14006229703 ps
CPU time 24.04 seconds
Started May 07 12:52:25 PM PDT 24
Finished May 07 12:52:50 PM PDT 24
Peak memory 347736 kb
Host smart-4e1240a2-86bf-48ea-8ecf-a269418f0cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344195301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.3344195301
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.3856484875
Short name T1044
Test name
Test status
Simulation time 78654295395 ps
CPU time 1137.11 seconds
Started May 07 12:52:33 PM PDT 24
Finished May 07 01:11:31 PM PDT 24
Peak memory 2966072 kb
Host smart-bda42077-10bd-4920-990c-68ead99519bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856484875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.3856484875
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.1318043347
Short name T382
Test name
Test status
Simulation time 683929108 ps
CPU time 12.31 seconds
Started May 07 12:52:32 PM PDT 24
Finished May 07 12:52:46 PM PDT 24
Peak memory 228404 kb
Host smart-ea9e8336-8868-4edd-8f3a-be04e32f4ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318043347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.1318043347
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.1957953154
Short name T129
Test name
Test status
Simulation time 51239493 ps
CPU time 0.84 seconds
Started May 07 12:52:39 PM PDT 24
Finished May 07 12:52:41 PM PDT 24
Peak memory 221420 kb
Host smart-da23488e-a974-4f68-b72c-bd7231ea8ab3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957953154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1957953154
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.3345837366
Short name T803
Test name
Test status
Simulation time 2940313017 ps
CPU time 4.19 seconds
Started May 07 12:52:30 PM PDT 24
Finished May 07 12:52:36 PM PDT 24
Peak memory 212192 kb
Host smart-8f829aaf-3005-4c02-a35d-4ffd6e5ab5d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345837366 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.3345837366
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.827117063
Short name T488
Test name
Test status
Simulation time 11150376504 ps
CPU time 5.68 seconds
Started May 07 12:52:30 PM PDT 24
Finished May 07 12:52:37 PM PDT 24
Peak memory 223520 kb
Host smart-8914f31a-ea1e-4512-840c-1c7146f2bd04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827117063 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_acq.827117063
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.1887461567
Short name T661
Test name
Test status
Simulation time 10756132843 ps
CPU time 8.55 seconds
Started May 07 12:52:33 PM PDT 24
Finished May 07 12:52:43 PM PDT 24
Peak memory 229992 kb
Host smart-08b1f617-4d4d-4605-a4a5-c88b7f2df378
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887461567 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.1887461567
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.1907297990
Short name T1126
Test name
Test status
Simulation time 1325822254 ps
CPU time 2.54 seconds
Started May 07 12:52:34 PM PDT 24
Finished May 07 12:52:37 PM PDT 24
Peak memory 203948 kb
Host smart-f2a50b29-8d06-4856-b444-779bf98c1564
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907297990 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.1907297990
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.1689926084
Short name T1338
Test name
Test status
Simulation time 4305711178 ps
CPU time 5.04 seconds
Started May 07 12:52:31 PM PDT 24
Finished May 07 12:52:37 PM PDT 24
Peak memory 204008 kb
Host smart-3df020e9-ce14-4547-b883-a067b92b861b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689926084 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.1689926084
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.3694255975
Short name T340
Test name
Test status
Simulation time 1602849302 ps
CPU time 24.53 seconds
Started May 07 12:52:32 PM PDT 24
Finished May 07 12:52:57 PM PDT 24
Peak memory 203936 kb
Host smart-16a51c85-c7a0-45d9-8017-0d3d0832241a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694255975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.3694255975
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.3309468816
Short name T1109
Test name
Test status
Simulation time 244222250 ps
CPU time 4.89 seconds
Started May 07 12:52:33 PM PDT 24
Finished May 07 12:52:39 PM PDT 24
Peak memory 203912 kb
Host smart-242b8560-511d-4988-9c8c-fd81af734027
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309468816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.3309468816
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.2238223855
Short name T1145
Test name
Test status
Simulation time 31481216809 ps
CPU time 21.39 seconds
Started May 07 12:52:32 PM PDT 24
Finished May 07 12:52:55 PM PDT 24
Peak memory 512308 kb
Host smart-fad29413-b064-457d-a455-9d67aa5f3b45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238223855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.2238223855
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.2568604234
Short name T362
Test name
Test status
Simulation time 11833854476 ps
CPU time 420.74 seconds
Started May 07 12:52:33 PM PDT 24
Finished May 07 12:59:35 PM PDT 24
Peak memory 2913380 kb
Host smart-4c9fc8e8-f9db-4bf7-a897-e60ea23e3603
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568604234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.2568604234
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.1266971820
Short name T1124
Test name
Test status
Simulation time 5112512453 ps
CPU time 7.28 seconds
Started May 07 12:52:33 PM PDT 24
Finished May 07 12:52:42 PM PDT 24
Peak memory 219848 kb
Host smart-94ba3cba-7a84-4b95-9d9e-744bc1115087
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266971820 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.1266971820
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.4271978485
Short name T456
Test name
Test status
Simulation time 17310947 ps
CPU time 0.63 seconds
Started May 07 12:56:52 PM PDT 24
Finished May 07 12:56:54 PM PDT 24
Peak memory 203808 kb
Host smart-813c7a44-08ec-420f-85f2-233471f9999a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271978485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.4271978485
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.4185093128
Short name T699
Test name
Test status
Simulation time 349390435 ps
CPU time 1.23 seconds
Started May 07 12:56:52 PM PDT 24
Finished May 07 12:56:54 PM PDT 24
Peak memory 212184 kb
Host smart-9b9e0da0-1c90-4a02-88b8-b0915a7dd0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185093128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.4185093128
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1330241964
Short name T1305
Test name
Test status
Simulation time 1143815196 ps
CPU time 6.77 seconds
Started May 07 12:56:46 PM PDT 24
Finished May 07 12:56:54 PM PDT 24
Peak memory 253492 kb
Host smart-97d8d89d-303d-4a91-a00e-940c08b28c8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330241964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1330241964
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.4129275326
Short name T281
Test name
Test status
Simulation time 2202848673 ps
CPU time 162.02 seconds
Started May 07 12:56:48 PM PDT 24
Finished May 07 12:59:31 PM PDT 24
Peak memory 730104 kb
Host smart-d0d47d6b-36da-47cc-926e-dd9aaa58fe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129275326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.4129275326
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.20898538
Short name T1321
Test name
Test status
Simulation time 5971547002 ps
CPU time 99.67 seconds
Started May 07 12:56:49 PM PDT 24
Finished May 07 12:58:30 PM PDT 24
Peak memory 553888 kb
Host smart-d056609c-4461-4cc5-a401-527ba47046ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20898538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.20898538
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.3328988892
Short name T454
Test name
Test status
Simulation time 304499133 ps
CPU time 0.86 seconds
Started May 07 12:56:47 PM PDT 24
Finished May 07 12:56:50 PM PDT 24
Peak memory 203772 kb
Host smart-8c269c1b-d774-4986-b844-2c9b1d25c0ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328988892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.3328988892
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.1138174405
Short name T889
Test name
Test status
Simulation time 791262721 ps
CPU time 5.21 seconds
Started May 07 12:56:47 PM PDT 24
Finished May 07 12:56:54 PM PDT 24
Peak memory 238028 kb
Host smart-957c3e07-3e78-4976-90bf-a283a7d53dae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138174405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.1138174405
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.4150052791
Short name T824
Test name
Test status
Simulation time 12120720342 ps
CPU time 145.37 seconds
Started May 07 12:56:47 PM PDT 24
Finished May 07 12:59:14 PM PDT 24
Peak memory 1262244 kb
Host smart-69a19372-6802-4c46-b58d-e64aa5c9cf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150052791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.4150052791
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.1099055350
Short name T1163
Test name
Test status
Simulation time 486713772 ps
CPU time 7.8 seconds
Started May 07 12:56:54 PM PDT 24
Finished May 07 12:57:03 PM PDT 24
Peak memory 203856 kb
Host smart-5fdc33c5-8363-456c-a3c2-087d9765379b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099055350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.1099055350
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.3287758249
Short name T40
Test name
Test status
Simulation time 1662990994 ps
CPU time 80.43 seconds
Started May 07 12:56:54 PM PDT 24
Finished May 07 12:58:16 PM PDT 24
Peak memory 320252 kb
Host smart-7c37b790-2c5f-4977-8fe6-1ebef9682e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287758249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.3287758249
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.284374248
Short name T203
Test name
Test status
Simulation time 27336547 ps
CPU time 0.68 seconds
Started May 07 12:56:50 PM PDT 24
Finished May 07 12:56:51 PM PDT 24
Peak memory 203592 kb
Host smart-6fbb2c75-8f2f-4725-8c75-3708c8310001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284374248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.284374248
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.563829424
Short name T335
Test name
Test status
Simulation time 1660160363 ps
CPU time 5.7 seconds
Started May 07 12:56:49 PM PDT 24
Finished May 07 12:56:56 PM PDT 24
Peak memory 204000 kb
Host smart-ee7491e9-c93f-417a-bf35-d6164de61d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563829424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.563829424
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.898278588
Short name T597
Test name
Test status
Simulation time 1841428258 ps
CPU time 49.27 seconds
Started May 07 12:56:48 PM PDT 24
Finished May 07 12:57:38 PM PDT 24
Peak memory 334840 kb
Host smart-f54300c6-d7c9-4b7d-b8b1-120b66d8002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898278588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.898278588
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.1544650234
Short name T948
Test name
Test status
Simulation time 105915744925 ps
CPU time 1155.18 seconds
Started May 07 12:56:50 PM PDT 24
Finished May 07 01:16:07 PM PDT 24
Peak memory 2905516 kb
Host smart-a65bd680-eae5-4c76-877b-e36536caeb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544650234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.1544650234
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.3847445251
Short name T962
Test name
Test status
Simulation time 2472050528 ps
CPU time 9.89 seconds
Started May 07 12:56:48 PM PDT 24
Finished May 07 12:57:00 PM PDT 24
Peak memory 218692 kb
Host smart-15e7a4d7-e737-4793-8c9d-314826ff773f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847445251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.3847445251
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.829428989
Short name T1061
Test name
Test status
Simulation time 753653814 ps
CPU time 3.92 seconds
Started May 07 12:56:46 PM PDT 24
Finished May 07 12:56:51 PM PDT 24
Peak memory 203868 kb
Host smart-5fec31bd-d571-4e80-b77b-daa2938b4cee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829428989 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.829428989
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.2225682096
Short name T101
Test name
Test status
Simulation time 10136628230 ps
CPU time 14.22 seconds
Started May 07 12:56:47 PM PDT 24
Finished May 07 12:57:02 PM PDT 24
Peak memory 266592 kb
Host smart-dc770409-d32e-41f2-943f-3b8400721d2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225682096 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.2225682096
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2763087895
Short name T388
Test name
Test status
Simulation time 10065738556 ps
CPU time 80.06 seconds
Started May 07 12:56:48 PM PDT 24
Finished May 07 12:58:10 PM PDT 24
Peak memory 494012 kb
Host smart-df32741c-3582-4255-b792-2441b2e2fbb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763087895 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2763087895
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.3268842428
Short name T261
Test name
Test status
Simulation time 587484403 ps
CPU time 2.34 seconds
Started May 07 12:56:51 PM PDT 24
Finished May 07 12:56:54 PM PDT 24
Peak memory 203904 kb
Host smart-7d2a2e82-6a84-40a0-879d-3a064fa19fca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268842428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.3268842428
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.2502671738
Short name T1115
Test name
Test status
Simulation time 783814795 ps
CPU time 4.64 seconds
Started May 07 12:56:47 PM PDT 24
Finished May 07 12:56:53 PM PDT 24
Peak memory 204132 kb
Host smart-86e1e30c-c5de-4105-b228-cfcc7a7f1130
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502671738 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.2502671738
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.3502668867
Short name T670
Test name
Test status
Simulation time 15772454798 ps
CPU time 106.59 seconds
Started May 07 12:56:48 PM PDT 24
Finished May 07 12:58:37 PM PDT 24
Peak memory 1955832 kb
Host smart-0f5c4086-c690-4d73-bcb1-b46fb40a876e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502668867 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.3502668867
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.721985922
Short name T59
Test name
Test status
Simulation time 1085310471 ps
CPU time 42.39 seconds
Started May 07 12:56:50 PM PDT 24
Finished May 07 12:57:34 PM PDT 24
Peak memory 203928 kb
Host smart-b6c3ddbf-9400-496e-9201-b60f719e1af5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721985922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_tar
get_smoke.721985922
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.812290478
Short name T966
Test name
Test status
Simulation time 2874482469 ps
CPU time 23.19 seconds
Started May 07 12:56:47 PM PDT 24
Finished May 07 12:57:12 PM PDT 24
Peak memory 227820 kb
Host smart-e7a14ef3-f19e-4655-a822-0b3e300a609d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812290478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_rd.812290478
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.3122135801
Short name T1192
Test name
Test status
Simulation time 9506334536 ps
CPU time 18.89 seconds
Started May 07 12:56:46 PM PDT 24
Finished May 07 12:57:06 PM PDT 24
Peak memory 203980 kb
Host smart-d7c73b9f-d5d7-4901-aa64-b67e97f69de7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122135801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.3122135801
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.1341849510
Short name T781
Test name
Test status
Simulation time 3755217683 ps
CPU time 90.34 seconds
Started May 07 12:56:48 PM PDT 24
Finished May 07 12:58:20 PM PDT 24
Peak memory 1022520 kb
Host smart-f52fd9db-cbd0-439e-9d9c-a62fb36659ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341849510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.1341849510
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.2353668021
Short name T707
Test name
Test status
Simulation time 2936422686 ps
CPU time 6.14 seconds
Started May 07 12:56:48 PM PDT 24
Finished May 07 12:56:56 PM PDT 24
Peak memory 210044 kb
Host smart-6b62340c-1881-41ca-8c93-b1eb90233d0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353668021 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.2353668021
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.1022255954
Short name T1249
Test name
Test status
Simulation time 82630519 ps
CPU time 0.7 seconds
Started May 07 12:57:01 PM PDT 24
Finished May 07 12:57:03 PM PDT 24
Peak memory 203664 kb
Host smart-4fcc6918-8ef6-427a-980a-460eea878952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022255954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.1022255954
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.3091838779
Short name T198
Test name
Test status
Simulation time 126798219 ps
CPU time 1.94 seconds
Started May 07 12:56:54 PM PDT 24
Finished May 07 12:56:57 PM PDT 24
Peak memory 212196 kb
Host smart-f98bb945-51a0-43a7-942d-3f63b454f84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091838779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3091838779
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2142646634
Short name T589
Test name
Test status
Simulation time 796177836 ps
CPU time 7.39 seconds
Started May 07 12:56:52 PM PDT 24
Finished May 07 12:57:01 PM PDT 24
Peak memory 282228 kb
Host smart-0962d662-9ea9-4828-879a-aa8358c3fcf8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142646634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.2142646634
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.3545856204
Short name T704
Test name
Test status
Simulation time 4497819281 ps
CPU time 35.91 seconds
Started May 07 12:56:51 PM PDT 24
Finished May 07 12:57:28 PM PDT 24
Peak memory 484712 kb
Host smart-69285d51-268a-4f6f-a35f-c02336945ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545856204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.3545856204
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.2586685291
Short name T457
Test name
Test status
Simulation time 8091858046 ps
CPU time 60.6 seconds
Started May 07 12:56:56 PM PDT 24
Finished May 07 12:57:58 PM PDT 24
Peak memory 689012 kb
Host smart-0b9608d1-cc06-4090-82fc-4344ef964539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586685291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.2586685291
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.2623982243
Short name T1198
Test name
Test status
Simulation time 597081635 ps
CPU time 1.17 seconds
Started May 07 12:56:53 PM PDT 24
Finished May 07 12:56:56 PM PDT 24
Peak memory 203872 kb
Host smart-5dcd0349-d6a9-4fb4-8dd6-f35cd89bf6c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623982243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.2623982243
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.2126045067
Short name T1241
Test name
Test status
Simulation time 209594068 ps
CPU time 9.06 seconds
Started May 07 12:56:54 PM PDT 24
Finished May 07 12:57:05 PM PDT 24
Peak memory 232112 kb
Host smart-9a63f955-1ea1-4feb-928b-ff0832406283
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126045067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.2126045067
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3213892306
Short name T1247
Test name
Test status
Simulation time 15374494492 ps
CPU time 132.05 seconds
Started May 07 12:56:52 PM PDT 24
Finished May 07 12:59:05 PM PDT 24
Peak memory 1189724 kb
Host smart-edc39582-6e52-4f31-9288-309f5cadeda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213892306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3213892306
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.3745398208
Short name T1219
Test name
Test status
Simulation time 639802799 ps
CPU time 7.69 seconds
Started May 07 12:57:01 PM PDT 24
Finished May 07 12:57:09 PM PDT 24
Peak memory 203984 kb
Host smart-1700447f-a0af-4e86-83c4-4ef3e497c745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745398208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.3745398208
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.624004078
Short name T745
Test name
Test status
Simulation time 3143010686 ps
CPU time 32.58 seconds
Started May 07 12:56:59 PM PDT 24
Finished May 07 12:57:32 PM PDT 24
Peak memory 357880 kb
Host smart-e32436cd-15e6-4934-8288-ee87cbbcd08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624004078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.624004078
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.2223560260
Short name T992
Test name
Test status
Simulation time 44142212 ps
CPU time 0.63 seconds
Started May 07 12:56:53 PM PDT 24
Finished May 07 12:56:54 PM PDT 24
Peak memory 203708 kb
Host smart-4c303f40-1438-48d6-becb-3b82afc09ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223560260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2223560260
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.1961873537
Short name T836
Test name
Test status
Simulation time 4579837978 ps
CPU time 23.65 seconds
Started May 07 12:56:54 PM PDT 24
Finished May 07 12:57:19 PM PDT 24
Peak memory 308968 kb
Host smart-ccb5a1de-02f6-4553-9877-cb46d1113383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961873537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.1961873537
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.126880412
Short name T449
Test name
Test status
Simulation time 6927032278 ps
CPU time 46.9 seconds
Started May 07 12:56:53 PM PDT 24
Finished May 07 12:57:42 PM PDT 24
Peak memory 297464 kb
Host smart-af32aa29-188f-4200-af3f-0f0ad8ef4f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126880412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.126880412
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.2671802761
Short name T1132
Test name
Test status
Simulation time 11362982462 ps
CPU time 635.45 seconds
Started May 07 12:56:55 PM PDT 24
Finished May 07 01:07:32 PM PDT 24
Peak memory 1989376 kb
Host smart-7ab84469-dc67-4b8f-8d18-d179c335fdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671802761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.2671802761
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.4171082754
Short name T397
Test name
Test status
Simulation time 524259587 ps
CPU time 4.8 seconds
Started May 07 12:56:56 PM PDT 24
Finished May 07 12:57:02 PM PDT 24
Peak memory 212096 kb
Host smart-90ad8c9c-3c40-4001-90a2-f7ccc7698a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171082754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.4171082754
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.6972711
Short name T1130
Test name
Test status
Simulation time 796615773 ps
CPU time 3.93 seconds
Started May 07 12:56:53 PM PDT 24
Finished May 07 12:56:58 PM PDT 24
Peak memory 212152 kb
Host smart-02c072f7-0fcb-417a-8820-f6f0ffac4982
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6972711 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_bad_addr.6972711
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.249761411
Short name T260
Test name
Test status
Simulation time 10065315761 ps
CPU time 36.94 seconds
Started May 07 12:56:55 PM PDT 24
Finished May 07 12:57:34 PM PDT 24
Peak memory 334488 kb
Host smart-635179de-20ab-4087-92b4-fb49ff69e004
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249761411 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_acq.249761411
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.3172206968
Short name T1138
Test name
Test status
Simulation time 10336484621 ps
CPU time 14.04 seconds
Started May 07 12:56:56 PM PDT 24
Finished May 07 12:57:12 PM PDT 24
Peak memory 256948 kb
Host smart-95aedcd3-e074-4497-8ac6-4959a70b1989
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172206968 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.3172206968
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.2739857483
Short name T1234
Test name
Test status
Simulation time 6779070268 ps
CPU time 2.58 seconds
Started May 07 12:56:54 PM PDT 24
Finished May 07 12:56:58 PM PDT 24
Peak memory 203992 kb
Host smart-69e8c844-32fe-4752-9357-47d8ab20dae5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739857483 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.2739857483
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.1064115905
Short name T235
Test name
Test status
Simulation time 1118799408 ps
CPU time 6.22 seconds
Started May 07 12:56:55 PM PDT 24
Finished May 07 12:57:03 PM PDT 24
Peak memory 218048 kb
Host smart-cec74dcb-37d8-4294-81e5-ec9e17b7a4fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064115905 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.1064115905
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.1362358633
Short name T231
Test name
Test status
Simulation time 25942504587 ps
CPU time 13.26 seconds
Started May 07 12:56:55 PM PDT 24
Finished May 07 12:57:10 PM PDT 24
Peak memory 420728 kb
Host smart-6dfab009-f5a1-4024-8d7d-8c3338125fbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362358633 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.1362358633
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.1637021081
Short name T580
Test name
Test status
Simulation time 1259438009 ps
CPU time 13.9 seconds
Started May 07 12:56:56 PM PDT 24
Finished May 07 12:57:11 PM PDT 24
Peak memory 203956 kb
Host smart-f49ca4d8-1ca5-499a-917e-00085e738c6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637021081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.1637021081
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.2931493007
Short name T1297
Test name
Test status
Simulation time 2793090051 ps
CPU time 5.66 seconds
Started May 07 12:56:55 PM PDT 24
Finished May 07 12:57:02 PM PDT 24
Peak memory 203940 kb
Host smart-08186f8b-c0e9-4f42-9f20-f9fb4743d413
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931493007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.2931493007
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.426307471
Short name T741
Test name
Test status
Simulation time 48789573661 ps
CPU time 138.32 seconds
Started May 07 12:56:55 PM PDT 24
Finished May 07 12:59:15 PM PDT 24
Peak memory 1791036 kb
Host smart-620f1ca4-33ba-408d-9224-1bf762ac02ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426307471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c
_target_stress_wr.426307471
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.299003962
Short name T921
Test name
Test status
Simulation time 17999433432 ps
CPU time 31.82 seconds
Started May 07 12:56:56 PM PDT 24
Finished May 07 12:57:29 PM PDT 24
Peak memory 473996 kb
Host smart-fe6bc91c-91f6-4fad-9b76-e7f1a6d84432
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299003962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_t
arget_stretch.299003962
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.1155662073
Short name T130
Test name
Test status
Simulation time 6141708338 ps
CPU time 8.1 seconds
Started May 07 12:56:53 PM PDT 24
Finished May 07 12:57:03 PM PDT 24
Peak memory 220244 kb
Host smart-d9a8c3d3-be12-4d23-9864-74dd315b2d3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155662073 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.1155662073
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.1747905137
Short name T756
Test name
Test status
Simulation time 43236549 ps
CPU time 0.65 seconds
Started May 07 12:57:11 PM PDT 24
Finished May 07 12:57:13 PM PDT 24
Peak memory 203804 kb
Host smart-5ae10c49-9794-4f0c-9398-cac773f5d957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747905137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.1747905137
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.2531916101
Short name T355
Test name
Test status
Simulation time 295593024 ps
CPU time 1.37 seconds
Started May 07 12:56:59 PM PDT 24
Finished May 07 12:57:01 PM PDT 24
Peak memory 212224 kb
Host smart-7ae96cec-589a-4247-8919-9401487e91ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531916101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.2531916101
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.1657571183
Short name T436
Test name
Test status
Simulation time 3088736668 ps
CPU time 11.35 seconds
Started May 07 12:57:01 PM PDT 24
Finished May 07 12:57:13 PM PDT 24
Peak memory 245828 kb
Host smart-278c1edd-c8d5-4ea5-8fec-b12c178dc77f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657571183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.1657571183
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.2754040082
Short name T866
Test name
Test status
Simulation time 6170701156 ps
CPU time 88.11 seconds
Started May 07 12:56:58 PM PDT 24
Finished May 07 12:58:27 PM PDT 24
Peak memory 430388 kb
Host smart-8af68bb2-a184-457f-b35f-b1493b7afe72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754040082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2754040082
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.3845123355
Short name T999
Test name
Test status
Simulation time 8360472913 ps
CPU time 61.5 seconds
Started May 07 12:56:57 PM PDT 24
Finished May 07 12:58:00 PM PDT 24
Peak memory 695520 kb
Host smart-9e84451b-61ae-4aed-99cb-a8633072b466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845123355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.3845123355
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.1532659438
Short name T508
Test name
Test status
Simulation time 267585768 ps
CPU time 1.14 seconds
Started May 07 12:57:00 PM PDT 24
Finished May 07 12:57:02 PM PDT 24
Peak memory 203876 kb
Host smart-0fdd50ab-7762-4ba9-91be-7b2d0992eb75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532659438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.1532659438
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.3451593166
Short name T270
Test name
Test status
Simulation time 1199477116 ps
CPU time 6.96 seconds
Started May 07 12:56:58 PM PDT 24
Finished May 07 12:57:06 PM PDT 24
Peak memory 223420 kb
Host smart-f739aa25-2736-4f65-a34e-ca30c22d4521
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451593166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.3451593166
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.1320457296
Short name T1248
Test name
Test status
Simulation time 12522960028 ps
CPU time 76.32 seconds
Started May 07 12:56:58 PM PDT 24
Finished May 07 12:58:16 PM PDT 24
Peak memory 829108 kb
Host smart-3a721586-b2c2-40c9-8fec-a2bd10e368a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320457296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.1320457296
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.1426092266
Short name T671
Test name
Test status
Simulation time 311061672 ps
CPU time 5.42 seconds
Started May 07 12:57:08 PM PDT 24
Finished May 07 12:57:15 PM PDT 24
Peak memory 203940 kb
Host smart-8e5ff097-ba38-4071-9854-7b9efd303b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426092266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.1426092266
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.1982277844
Short name T1066
Test name
Test status
Simulation time 1725690670 ps
CPU time 30.05 seconds
Started May 07 12:57:11 PM PDT 24
Finished May 07 12:57:42 PM PDT 24
Peak memory 362780 kb
Host smart-c189f3db-d012-42c1-addf-042b05fec1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982277844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.1982277844
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.385299901
Short name T1083
Test name
Test status
Simulation time 70952521 ps
CPU time 0.73 seconds
Started May 07 12:57:02 PM PDT 24
Finished May 07 12:57:03 PM PDT 24
Peak memory 203608 kb
Host smart-bf144eb5-0e4a-4345-b0e9-0fe19db9785d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385299901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.385299901
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.587894872
Short name T90
Test name
Test status
Simulation time 5349316472 ps
CPU time 51.28 seconds
Started May 07 12:56:59 PM PDT 24
Finished May 07 12:57:52 PM PDT 24
Peak memory 215824 kb
Host smart-03f8eb93-3f3f-4fda-bc00-7bcf5c025d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587894872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.587894872
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.3431630712
Short name T763
Test name
Test status
Simulation time 5362959287 ps
CPU time 24.12 seconds
Started May 07 12:57:01 PM PDT 24
Finished May 07 12:57:26 PM PDT 24
Peak memory 322712 kb
Host smart-20b64da5-c7af-4439-bedd-1e53da5c61ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431630712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.3431630712
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.3551563642
Short name T935
Test name
Test status
Simulation time 2622107153 ps
CPU time 11.4 seconds
Started May 07 12:56:59 PM PDT 24
Finished May 07 12:57:11 PM PDT 24
Peak memory 213644 kb
Host smart-31dfce06-abeb-49d6-804d-1946f6cc3168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551563642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.3551563642
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.1338531232
Short name T1235
Test name
Test status
Simulation time 1023372667 ps
CPU time 5.13 seconds
Started May 07 12:57:09 PM PDT 24
Finished May 07 12:57:15 PM PDT 24
Peak memory 212040 kb
Host smart-7ef51ddf-ec39-4305-bb3f-60a795c0ab23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338531232 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.1338531232
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.1339594851
Short name T1195
Test name
Test status
Simulation time 10262686144 ps
CPU time 16.63 seconds
Started May 07 12:57:00 PM PDT 24
Finished May 07 12:57:18 PM PDT 24
Peak memory 252492 kb
Host smart-6dee9190-597e-4786-b1d8-897226568929
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339594851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.1339594851
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.2221789747
Short name T902
Test name
Test status
Simulation time 10181798403 ps
CPU time 13.84 seconds
Started May 07 12:57:09 PM PDT 24
Finished May 07 12:57:23 PM PDT 24
Peak memory 264500 kb
Host smart-201b9a44-2650-48d6-a1fb-ca519cfd0418
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221789747 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.2221789747
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.3048812141
Short name T538
Test name
Test status
Simulation time 444441540 ps
CPU time 2.69 seconds
Started May 07 12:57:06 PM PDT 24
Finished May 07 12:57:10 PM PDT 24
Peak memory 203876 kb
Host smart-6227ad9a-d283-4984-9cbc-f7bb7bc01f8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048812141 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.3048812141
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.593990183
Short name T890
Test name
Test status
Simulation time 12159884738 ps
CPU time 3.68 seconds
Started May 07 12:56:57 PM PDT 24
Finished May 07 12:57:02 PM PDT 24
Peak memory 205860 kb
Host smart-47055940-3077-495f-9130-08ba70f3ff61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593990183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_intr_smoke.593990183
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.2256389176
Short name T1361
Test name
Test status
Simulation time 19428644316 ps
CPU time 269.58 seconds
Started May 07 12:57:00 PM PDT 24
Finished May 07 01:01:30 PM PDT 24
Peak memory 3704024 kb
Host smart-9bf78134-2917-4306-a37e-9b837c24f2aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256389176 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.2256389176
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3296550919
Short name T609
Test name
Test status
Simulation time 1010195839 ps
CPU time 14.6 seconds
Started May 07 12:57:00 PM PDT 24
Finished May 07 12:57:15 PM PDT 24
Peak memory 203808 kb
Host smart-a2d49892-dad4-4b5e-96c3-c691758904c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296550919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3296550919
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.894824959
Short name T527
Test name
Test status
Simulation time 4831537137 ps
CPU time 49.42 seconds
Started May 07 12:57:00 PM PDT 24
Finished May 07 12:57:51 PM PDT 24
Peak memory 203876 kb
Host smart-de6e9308-5a53-4835-904d-e24e301e443a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894824959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c
_target_stress_rd.894824959
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.2768166180
Short name T1365
Test name
Test status
Simulation time 61985606942 ps
CPU time 2146.19 seconds
Started May 07 12:56:59 PM PDT 24
Finished May 07 01:32:47 PM PDT 24
Peak memory 10204252 kb
Host smart-43347e97-5718-4376-8a9a-916311cec64c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768166180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.2768166180
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.2717700771
Short name T1074
Test name
Test status
Simulation time 32775170787 ps
CPU time 203.4 seconds
Started May 07 12:56:58 PM PDT 24
Finished May 07 01:00:23 PM PDT 24
Peak memory 1913988 kb
Host smart-5f4f9774-19dd-43b7-8477-83e5f9caabc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717700771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.2717700771
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.2511239983
Short name T1091
Test name
Test status
Simulation time 1259024563 ps
CPU time 6.89 seconds
Started May 07 12:57:01 PM PDT 24
Finished May 07 12:57:08 PM PDT 24
Peak memory 203916 kb
Host smart-a19963ae-b576-4af7-b066-0c5a147f8c42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511239983 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.2511239983
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_unexp_stop.1151412544
Short name T1039
Test name
Test status
Simulation time 6474607098 ps
CPU time 6.87 seconds
Started May 07 12:56:59 PM PDT 24
Finished May 07 12:57:07 PM PDT 24
Peak memory 214596 kb
Host smart-e28ca691-d108-4981-a4d2-63d59ba8a1ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151412544 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.i2c_target_unexp_stop.1151412544
Directory /workspace/32.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/33.i2c_alert_test.1050545911
Short name T959
Test name
Test status
Simulation time 28774217 ps
CPU time 0.66 seconds
Started May 07 12:57:15 PM PDT 24
Finished May 07 12:57:17 PM PDT 24
Peak memory 203636 kb
Host smart-0c35c549-1b02-4f52-a45f-bf06c2e14c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050545911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.1050545911
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.1698522610
Short name T1
Test name
Test status
Simulation time 54512009 ps
CPU time 1.15 seconds
Started May 07 12:57:18 PM PDT 24
Finished May 07 12:57:20 PM PDT 24
Peak memory 212088 kb
Host smart-13e1edff-3b5f-4b40-837b-e352469e922a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698522610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.1698522610
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.3055266981
Short name T272
Test name
Test status
Simulation time 386841899 ps
CPU time 21.12 seconds
Started May 07 12:57:07 PM PDT 24
Finished May 07 12:57:29 PM PDT 24
Peak memory 288516 kb
Host smart-2fac3efe-cc12-4ef7-9ce5-63cdc2a79fa6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055266981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.3055266981
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.810477225
Short name T780
Test name
Test status
Simulation time 9236352311 ps
CPU time 32.33 seconds
Started May 07 12:57:09 PM PDT 24
Finished May 07 12:57:42 PM PDT 24
Peak memory 254820 kb
Host smart-06920c32-1410-4402-b0aa-8cb9f34edd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810477225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.810477225
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.3444826069
Short name T200
Test name
Test status
Simulation time 7304595517 ps
CPU time 79.13 seconds
Started May 07 12:57:07 PM PDT 24
Finished May 07 12:58:27 PM PDT 24
Peak memory 785432 kb
Host smart-79bad6b7-de2b-4cfa-967c-d14f557f2bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444826069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.3444826069
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.1638274607
Short name T379
Test name
Test status
Simulation time 1354726237 ps
CPU time 0.84 seconds
Started May 07 12:57:08 PM PDT 24
Finished May 07 12:57:09 PM PDT 24
Peak memory 203812 kb
Host smart-d0b3b081-3808-4ba2-99fe-313cd5474823
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638274607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.1638274607
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.301840069
Short name T287
Test name
Test status
Simulation time 308215716 ps
CPU time 4.56 seconds
Started May 07 12:57:08 PM PDT 24
Finished May 07 12:57:14 PM PDT 24
Peak memory 229712 kb
Host smart-60deeea5-59c3-4d83-80ef-5d1125fda68f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301840069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.
301840069
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.3645843864
Short name T444
Test name
Test status
Simulation time 8461808450 ps
CPU time 176.49 seconds
Started May 07 12:57:08 PM PDT 24
Finished May 07 01:00:05 PM PDT 24
Peak memory 834340 kb
Host smart-02004d4c-2c8e-45f3-a609-c633f42f848f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645843864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.3645843864
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.1023743302
Short name T862
Test name
Test status
Simulation time 468376486 ps
CPU time 3.25 seconds
Started May 07 12:57:15 PM PDT 24
Finished May 07 12:57:19 PM PDT 24
Peak memory 203772 kb
Host smart-f4c35f5b-868d-4b82-ae7e-b80a9a2f5a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023743302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.1023743302
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.2308970276
Short name T422
Test name
Test status
Simulation time 5955875956 ps
CPU time 30.48 seconds
Started May 07 12:57:13 PM PDT 24
Finished May 07 12:57:44 PM PDT 24
Peak memory 354968 kb
Host smart-efc55f23-a3a0-4017-bdfd-b1748c0aaa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308970276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.2308970276
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.1039264235
Short name T55
Test name
Test status
Simulation time 30047554 ps
CPU time 0.7 seconds
Started May 07 12:57:08 PM PDT 24
Finished May 07 12:57:10 PM PDT 24
Peak memory 203740 kb
Host smart-fc94dde5-46a6-41d1-86fd-38d3992cd11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039264235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.1039264235
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.1725785151
Short name T1228
Test name
Test status
Simulation time 3405006014 ps
CPU time 12.71 seconds
Started May 07 12:57:09 PM PDT 24
Finished May 07 12:57:22 PM PDT 24
Peak memory 236688 kb
Host smart-0a648fb0-a764-4df0-b942-fc4e82dd91a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725785151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.1725785151
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.1107442957
Short name T107
Test name
Test status
Simulation time 1152582414 ps
CPU time 22.49 seconds
Started May 07 12:57:09 PM PDT 24
Finished May 07 12:57:33 PM PDT 24
Peak memory 293164 kb
Host smart-bd1734b7-76fd-4783-8eab-987b83a884f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107442957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.1107442957
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.3783558821
Short name T242
Test name
Test status
Simulation time 38077111003 ps
CPU time 504.39 seconds
Started May 07 12:57:13 PM PDT 24
Finished May 07 01:05:38 PM PDT 24
Peak memory 2104080 kb
Host smart-815ddc24-9f49-460d-bef2-b0486b5e0f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783558821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.3783558821
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.803286723
Short name T529
Test name
Test status
Simulation time 874985818 ps
CPU time 17.46 seconds
Started May 07 12:57:08 PM PDT 24
Finished May 07 12:57:27 PM PDT 24
Peak memory 220304 kb
Host smart-46e77a7d-97cc-4c6f-b03e-830c193df1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803286723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.803286723
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3137776273
Short name T913
Test name
Test status
Simulation time 3066082069 ps
CPU time 3.6 seconds
Started May 07 12:57:20 PM PDT 24
Finished May 07 12:57:24 PM PDT 24
Peak memory 203948 kb
Host smart-13e54733-f9d2-4b35-a4bd-01ffbc2f397b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137776273 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3137776273
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.2058622071
Short name T1019
Test name
Test status
Simulation time 10058822101 ps
CPU time 73.1 seconds
Started May 07 12:57:14 PM PDT 24
Finished May 07 12:58:29 PM PDT 24
Peak memory 490588 kb
Host smart-4e3684f0-3ecd-42ce-82cb-dd8b21d4a35f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058622071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.2058622071
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.2156055712
Short name T393
Test name
Test status
Simulation time 10366949137 ps
CPU time 17.8 seconds
Started May 07 12:57:14 PM PDT 24
Finished May 07 12:57:33 PM PDT 24
Peak memory 279564 kb
Host smart-21159f95-9800-49b4-bd32-eb184ceb06c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156055712 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.2156055712
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.2438940914
Short name T27
Test name
Test status
Simulation time 501625034 ps
CPU time 2.95 seconds
Started May 07 12:57:20 PM PDT 24
Finished May 07 12:57:23 PM PDT 24
Peak memory 203872 kb
Host smart-6239886e-c5a9-44c2-82f3-fc59e13980da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438940914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.2438940914
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.4179883934
Short name T871
Test name
Test status
Simulation time 6475171285 ps
CPU time 5.45 seconds
Started May 07 12:57:16 PM PDT 24
Finished May 07 12:57:22 PM PDT 24
Peak memory 211940 kb
Host smart-b8ff85bb-94a2-4260-806d-e323b8ec545e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179883934 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.4179883934
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.192688517
Short name T1300
Test name
Test status
Simulation time 8744584106 ps
CPU time 37.97 seconds
Started May 07 12:57:13 PM PDT 24
Finished May 07 12:57:53 PM PDT 24
Peak memory 1136312 kb
Host smart-effe1d20-236f-4739-8555-d7cb3b2ba6be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192688517 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.192688517
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.1296056910
Short name T878
Test name
Test status
Simulation time 1567364412 ps
CPU time 20.05 seconds
Started May 07 12:57:12 PM PDT 24
Finished May 07 12:57:33 PM PDT 24
Peak memory 203848 kb
Host smart-32d36ff3-b99e-4fad-9be1-577cb2866e83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296056910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.1296056910
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.1508092878
Short name T1155
Test name
Test status
Simulation time 884408674 ps
CPU time 7.39 seconds
Started May 07 12:57:17 PM PDT 24
Finished May 07 12:57:25 PM PDT 24
Peak memory 203960 kb
Host smart-2c6b1629-97c3-4be9-afbc-bd1ab3deccb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508092878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.1508092878
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.2928874023
Short name T1292
Test name
Test status
Simulation time 29383191979 ps
CPU time 28.35 seconds
Started May 07 12:57:13 PM PDT 24
Finished May 07 12:57:42 PM PDT 24
Peak memory 624576 kb
Host smart-697510f2-0e69-41f6-a193-f4dcd1a82406
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928874023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.2928874023
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.4128975965
Short name T1313
Test name
Test status
Simulation time 3774398430 ps
CPU time 88.99 seconds
Started May 07 12:57:14 PM PDT 24
Finished May 07 12:58:44 PM PDT 24
Peak memory 550612 kb
Host smart-62b8eb8e-5371-4bb2-9287-5cfb6e885444
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128975965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.4128975965
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.2132337271
Short name T506
Test name
Test status
Simulation time 4413971660 ps
CPU time 7.61 seconds
Started May 07 12:57:15 PM PDT 24
Finished May 07 12:57:24 PM PDT 24
Peak memory 220188 kb
Host smart-34ea5267-e561-434f-89af-bd7df846e9e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132337271 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.2132337271
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.3950675461
Short name T567
Test name
Test status
Simulation time 162445672 ps
CPU time 0.6 seconds
Started May 07 12:57:24 PM PDT 24
Finished May 07 12:57:26 PM PDT 24
Peak memory 203592 kb
Host smart-9cd0f255-0a1c-4eaf-9852-e1c97c169649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950675461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.3950675461
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3271853505
Short name T113
Test name
Test status
Simulation time 279186883 ps
CPU time 1.11 seconds
Started May 07 12:57:20 PM PDT 24
Finished May 07 12:57:22 PM PDT 24
Peak memory 203940 kb
Host smart-7d76d8b8-9adf-47d0-8bdc-745b670d19de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271853505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3271853505
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.3496345772
Short name T327
Test name
Test status
Simulation time 4084128814 ps
CPU time 24.78 seconds
Started May 07 12:57:19 PM PDT 24
Finished May 07 12:57:44 PM PDT 24
Peak memory 293364 kb
Host smart-7d7fafbc-bf5d-4289-b7ac-9b654d519dc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496345772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.3496345772
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.1026815905
Short name T1025
Test name
Test status
Simulation time 3961549289 ps
CPU time 77.63 seconds
Started May 07 12:57:14 PM PDT 24
Finished May 07 12:58:33 PM PDT 24
Peak memory 641200 kb
Host smart-3d05ffd3-2398-478d-8064-b3db7543e82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026815905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.1026815905
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.41005217
Short name T1196
Test name
Test status
Simulation time 3260613633 ps
CPU time 36.13 seconds
Started May 07 12:57:14 PM PDT 24
Finished May 07 12:57:51 PM PDT 24
Peak memory 493360 kb
Host smart-f79abe89-75e5-40f9-8d57-fb67d420a65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41005217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.41005217
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3263998777
Short name T84
Test name
Test status
Simulation time 241135793 ps
CPU time 1.05 seconds
Started May 07 12:57:16 PM PDT 24
Finished May 07 12:57:18 PM PDT 24
Peak memory 203852 kb
Host smart-0d729d5b-f9d1-4fb4-ab91-2c95d2c47afe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263998777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3263998777
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.2997023091
Short name T326
Test name
Test status
Simulation time 224708183 ps
CPU time 6.37 seconds
Started May 07 12:57:14 PM PDT 24
Finished May 07 12:57:21 PM PDT 24
Peak memory 203848 kb
Host smart-de57ce76-368d-4c6f-aedc-2001f315f3cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997023091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.2997023091
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2604906227
Short name T1326
Test name
Test status
Simulation time 16368102657 ps
CPU time 96.3 seconds
Started May 07 12:57:14 PM PDT 24
Finished May 07 12:58:51 PM PDT 24
Peak memory 1152936 kb
Host smart-2dfe8ebe-1308-4167-a9dd-aab9567f908a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604906227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2604906227
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.2938458026
Short name T800
Test name
Test status
Simulation time 294868980 ps
CPU time 3.91 seconds
Started May 07 12:57:22 PM PDT 24
Finished May 07 12:57:27 PM PDT 24
Peak memory 203968 kb
Host smart-69f34ec4-a7cf-4c0d-a1f6-32ce6cedfd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938458026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.2938458026
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.332261779
Short name T1034
Test name
Test status
Simulation time 8598769452 ps
CPU time 45.68 seconds
Started May 07 12:57:22 PM PDT 24
Finished May 07 12:58:08 PM PDT 24
Peak memory 358236 kb
Host smart-e0a3e966-3b32-4997-9ed4-333177a9badb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332261779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.332261779
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.3884026516
Short name T938
Test name
Test status
Simulation time 22380170 ps
CPU time 0.65 seconds
Started May 07 12:57:16 PM PDT 24
Finished May 07 12:57:17 PM PDT 24
Peak memory 203728 kb
Host smart-2316b45d-73c0-426c-8f96-a2a3a31d03f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884026516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.3884026516
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.580997250
Short name T924
Test name
Test status
Simulation time 12521380083 ps
CPU time 746.11 seconds
Started May 07 12:57:14 PM PDT 24
Finished May 07 01:09:41 PM PDT 24
Peak memory 2895568 kb
Host smart-f97855c3-24e0-44eb-87cd-f05783222ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580997250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.580997250
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.2614638827
Short name T860
Test name
Test status
Simulation time 1539105111 ps
CPU time 31.99 seconds
Started May 07 12:57:15 PM PDT 24
Finished May 07 12:57:48 PM PDT 24
Peak memory 365904 kb
Host smart-ceff43fc-1039-4d5b-9b9d-7813427dbcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614638827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.2614638827
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.3154189890
Short name T1024
Test name
Test status
Simulation time 2953671435 ps
CPU time 13.39 seconds
Started May 07 12:57:16 PM PDT 24
Finished May 07 12:57:30 PM PDT 24
Peak memory 215392 kb
Host smart-5ec75527-d9ad-4803-be69-da3fc6bed59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154189890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3154189890
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.3125371421
Short name T667
Test name
Test status
Simulation time 1756565995 ps
CPU time 4.41 seconds
Started May 07 12:57:20 PM PDT 24
Finished May 07 12:57:25 PM PDT 24
Peak memory 212160 kb
Host smart-0487deae-2696-4f7c-a243-915494b76573
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125371421 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.3125371421
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.1226217017
Short name T928
Test name
Test status
Simulation time 10065123734 ps
CPU time 77.14 seconds
Started May 07 12:57:22 PM PDT 24
Finished May 07 12:58:40 PM PDT 24
Peak memory 433144 kb
Host smart-9a35bb4d-4ad3-4114-bd81-d3924ca4585a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226217017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.1226217017
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.992281016
Short name T460
Test name
Test status
Simulation time 10328485370 ps
CPU time 13.68 seconds
Started May 07 12:57:19 PM PDT 24
Finished May 07 12:57:34 PM PDT 24
Peak memory 275668 kb
Host smart-fad48e42-9444-4ff8-8403-c81db7054625
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992281016 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_fifo_reset_tx.992281016
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.2018093643
Short name T28
Test name
Test status
Simulation time 2176730234 ps
CPU time 3.11 seconds
Started May 07 12:57:19 PM PDT 24
Finished May 07 12:57:23 PM PDT 24
Peak memory 203972 kb
Host smart-d8ec135a-3401-4e40-8f30-c208ff0335bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018093643 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.2018093643
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.1305332653
Short name T1220
Test name
Test status
Simulation time 2089388886 ps
CPU time 5.36 seconds
Started May 07 12:57:24 PM PDT 24
Finished May 07 12:57:30 PM PDT 24
Peak memory 210188 kb
Host smart-e7bb3f59-2758-4d71-80f4-e73192677bd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305332653 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.1305332653
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.1682142891
Short name T1149
Test name
Test status
Simulation time 26470114805 ps
CPU time 6.76 seconds
Started May 07 12:57:20 PM PDT 24
Finished May 07 12:57:27 PM PDT 24
Peak memory 203932 kb
Host smart-293f1245-b067-43bd-a631-bab2a872a42e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682142891 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.1682142891
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.4141665659
Short name T585
Test name
Test status
Simulation time 1448892126 ps
CPU time 9.63 seconds
Started May 07 12:57:19 PM PDT 24
Finished May 07 12:57:30 PM PDT 24
Peak memory 203856 kb
Host smart-a9b0d127-5220-4387-9d65-152fd9a533c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141665659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.4141665659
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.583453819
Short name T590
Test name
Test status
Simulation time 4604323002 ps
CPU time 29.87 seconds
Started May 07 12:57:20 PM PDT 24
Finished May 07 12:57:51 PM PDT 24
Peak memory 203908 kb
Host smart-dd3073ca-79d7-47d4-8504-b65dab1ec7a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583453819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_rd.583453819
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.4275750904
Short name T307
Test name
Test status
Simulation time 25193459215 ps
CPU time 21.95 seconds
Started May 07 12:57:21 PM PDT 24
Finished May 07 12:57:44 PM PDT 24
Peak memory 459656 kb
Host smart-5f366def-5158-4681-a511-5f4566ca2eff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275750904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.4275750904
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.3689125924
Short name T1337
Test name
Test status
Simulation time 21120955961 ps
CPU time 402.57 seconds
Started May 07 12:57:23 PM PDT 24
Finished May 07 01:04:06 PM PDT 24
Peak memory 1277160 kb
Host smart-4cf96ef4-2b79-4d92-92a4-6109b26d7b43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689125924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.3689125924
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.2775129026
Short name T563
Test name
Test status
Simulation time 2474529686 ps
CPU time 6.54 seconds
Started May 07 12:57:21 PM PDT 24
Finished May 07 12:57:29 PM PDT 24
Peak memory 212164 kb
Host smart-a1aff141-f9f3-4395-a426-7763fc7e4eb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775129026 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.2775129026
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.83755789
Short name T120
Test name
Test status
Simulation time 89654056 ps
CPU time 0.62 seconds
Started May 07 12:57:37 PM PDT 24
Finished May 07 12:57:38 PM PDT 24
Peak memory 203780 kb
Host smart-56cdf629-26d3-4c86-862c-2d84f8eb01a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83755789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.83755789
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.565779106
Short name T758
Test name
Test status
Simulation time 92923804 ps
CPU time 1.54 seconds
Started May 07 12:57:28 PM PDT 24
Finished May 07 12:57:31 PM PDT 24
Peak memory 212056 kb
Host smart-1cb8aa62-5d59-43e1-8404-4f553bf2b860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565779106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.565779106
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.3284756808
Short name T1029
Test name
Test status
Simulation time 878240671 ps
CPU time 17.94 seconds
Started May 07 12:57:28 PM PDT 24
Finished May 07 12:57:47 PM PDT 24
Peak memory 269788 kb
Host smart-cf3241b3-061e-40a3-971a-e9d31f8be7fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284756808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.3284756808
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.796962182
Short name T469
Test name
Test status
Simulation time 1553963433 ps
CPU time 100.78 seconds
Started May 07 12:57:29 PM PDT 24
Finished May 07 12:59:11 PM PDT 24
Peak memory 510036 kb
Host smart-8097b5ff-c0d0-4366-8ee5-a13a5467d138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796962182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.796962182
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.2181813220
Short name T943
Test name
Test status
Simulation time 7326371595 ps
CPU time 151.46 seconds
Started May 07 12:57:29 PM PDT 24
Finished May 07 01:00:02 PM PDT 24
Peak memory 679816 kb
Host smart-2907b4fc-3bdf-4b77-b8c1-60967a50d36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181813220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2181813220
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.2018698849
Short name T1042
Test name
Test status
Simulation time 98846793 ps
CPU time 0.96 seconds
Started May 07 12:57:27 PM PDT 24
Finished May 07 12:57:29 PM PDT 24
Peak memory 203744 kb
Host smart-4debd2a0-1389-42ae-a4b9-396d2cd0c8f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018698849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.2018698849
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.3845414100
Short name T478
Test name
Test status
Simulation time 202392053 ps
CPU time 11.88 seconds
Started May 07 12:57:28 PM PDT 24
Finished May 07 12:57:41 PM PDT 24
Peak memory 242464 kb
Host smart-83faafaa-5f7e-4697-8c63-dbdcf2a25daf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845414100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.3845414100
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.1819892632
Short name T906
Test name
Test status
Simulation time 4591226028 ps
CPU time 152.72 seconds
Started May 07 12:57:27 PM PDT 24
Finished May 07 01:00:01 PM PDT 24
Peak memory 773188 kb
Host smart-a010f280-2d04-43a7-84b6-94872b8610ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819892632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1819892632
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.1462519236
Short name T1360
Test name
Test status
Simulation time 1107157351 ps
CPU time 4.85 seconds
Started May 07 12:57:33 PM PDT 24
Finished May 07 12:57:39 PM PDT 24
Peak memory 203948 kb
Host smart-79d196c7-12b9-4aff-9e81-d43a8eefc7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462519236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.1462519236
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.3974073683
Short name T1238
Test name
Test status
Simulation time 8395661835 ps
CPU time 38.18 seconds
Started May 07 12:57:34 PM PDT 24
Finished May 07 12:58:13 PM PDT 24
Peak memory 384956 kb
Host smart-068fd0da-aec1-41c1-b3f1-52ead8a553f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974073683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.3974073683
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.1619971396
Short name T271
Test name
Test status
Simulation time 43122335 ps
CPU time 0.69 seconds
Started May 07 12:57:27 PM PDT 24
Finished May 07 12:57:29 PM PDT 24
Peak memory 203716 kb
Host smart-63581fcc-6239-4565-aec2-7fbdec1262b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619971396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.1619971396
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.293467330
Short name T282
Test name
Test status
Simulation time 2902497619 ps
CPU time 83.54 seconds
Started May 07 12:57:28 PM PDT 24
Finished May 07 12:58:53 PM PDT 24
Peak memory 822944 kb
Host smart-db2fc56b-64e3-48ea-bdc7-fbe9de1e265f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293467330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.293467330
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.1096421171
Short name T1312
Test name
Test status
Simulation time 1022913166 ps
CPU time 22.59 seconds
Started May 07 12:57:20 PM PDT 24
Finished May 07 12:57:44 PM PDT 24
Peak memory 332028 kb
Host smart-2daeeff0-6ad5-4c92-9132-91eff0aec37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096421171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.1096421171
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.3569837566
Short name T865
Test name
Test status
Simulation time 68222750158 ps
CPU time 882.8 seconds
Started May 07 12:57:28 PM PDT 24
Finished May 07 01:12:12 PM PDT 24
Peak memory 3840344 kb
Host smart-c805a342-568f-4fe9-8587-9a16def422e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569837566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.3569837566
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.574197019
Short name T795
Test name
Test status
Simulation time 730718162 ps
CPU time 12.14 seconds
Started May 07 12:57:27 PM PDT 24
Finished May 07 12:57:40 PM PDT 24
Peak memory 220192 kb
Host smart-37491f1a-b1d4-4154-86be-1b741f8e32c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574197019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.574197019
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.1209725059
Short name T342
Test name
Test status
Simulation time 1161378999 ps
CPU time 3.17 seconds
Started May 07 12:57:26 PM PDT 24
Finished May 07 12:57:31 PM PDT 24
Peak memory 203908 kb
Host smart-9f8330a8-d519-45ca-932e-a146083f6f27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209725059 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.1209725059
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.1552495346
Short name T418
Test name
Test status
Simulation time 10164247916 ps
CPU time 32.03 seconds
Started May 07 12:57:28 PM PDT 24
Finished May 07 12:58:01 PM PDT 24
Peak memory 355560 kb
Host smart-1ac22f07-c3eb-41c6-bb7f-9b85a8c22f87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552495346 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.1552495346
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.1165390679
Short name T721
Test name
Test status
Simulation time 10508155238 ps
CPU time 13.72 seconds
Started May 07 12:57:27 PM PDT 24
Finished May 07 12:57:42 PM PDT 24
Peak memory 280372 kb
Host smart-ce7fccaf-e833-4971-983d-65e104f11e5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165390679 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.1165390679
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.2248804979
Short name T845
Test name
Test status
Simulation time 1755467040 ps
CPU time 2.86 seconds
Started May 07 12:57:27 PM PDT 24
Finished May 07 12:57:31 PM PDT 24
Peak memory 203884 kb
Host smart-ab31267d-f037-4a6c-90b5-876f42aa5253
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248804979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.2248804979
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.141684990
Short name T615
Test name
Test status
Simulation time 2583680759 ps
CPU time 6 seconds
Started May 07 12:57:26 PM PDT 24
Finished May 07 12:57:32 PM PDT 24
Peak memory 220092 kb
Host smart-9cf5ba20-a49b-4580-b86f-0026862c8ea1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141684990 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_intr_smoke.141684990
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.2993874158
Short name T735
Test name
Test status
Simulation time 11980102574 ps
CPU time 11.09 seconds
Started May 07 12:57:26 PM PDT 24
Finished May 07 12:57:39 PM PDT 24
Peak memory 298396 kb
Host smart-56155323-6364-4ed9-96c0-ba9c661091a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993874158 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.2993874158
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.2932225062
Short name T677
Test name
Test status
Simulation time 3573653147 ps
CPU time 32.56 seconds
Started May 07 12:57:30 PM PDT 24
Finished May 07 12:58:03 PM PDT 24
Peak memory 203912 kb
Host smart-28986b30-ba6f-4b3f-aac0-31662af32697
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932225062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.2932225062
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.2487277331
Short name T1232
Test name
Test status
Simulation time 2752301289 ps
CPU time 10.6 seconds
Started May 07 12:57:28 PM PDT 24
Finished May 07 12:57:40 PM PDT 24
Peak memory 212920 kb
Host smart-180a390b-9ec8-43d5-a58c-6b4ff129ce39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487277331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.2487277331
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.2992169296
Short name T573
Test name
Test status
Simulation time 34520294471 ps
CPU time 353.37 seconds
Started May 07 12:57:30 PM PDT 24
Finished May 07 01:03:24 PM PDT 24
Peak memory 3723304 kb
Host smart-85c5f879-6ea6-4ebf-876e-7851fd94dd17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992169296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.2992169296
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2896108564
Short name T900
Test name
Test status
Simulation time 12863834478 ps
CPU time 1306.93 seconds
Started May 07 12:57:26 PM PDT 24
Finished May 07 01:19:14 PM PDT 24
Peak memory 2925368 kb
Host smart-76bec3de-519d-440a-84ac-7c5bee3bb68d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896108564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2896108564
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.2512942342
Short name T680
Test name
Test status
Simulation time 1262841789 ps
CPU time 7.26 seconds
Started May 07 12:57:28 PM PDT 24
Finished May 07 12:57:37 PM PDT 24
Peak memory 220148 kb
Host smart-5425ba73-32d3-4aae-8ebd-7b74f63a2bb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512942342 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.2512942342
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_unexp_stop.1852145108
Short name T1071
Test name
Test status
Simulation time 1193981399 ps
CPU time 7.33 seconds
Started May 07 12:57:27 PM PDT 24
Finished May 07 12:57:36 PM PDT 24
Peak memory 220156 kb
Host smart-4a27ac8e-2b6b-4b00-98be-1be8b63a1d05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852145108 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.i2c_target_unexp_stop.1852145108
Directory /workspace/35.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/36.i2c_alert_test.358025685
Short name T1262
Test name
Test status
Simulation time 40607295 ps
CPU time 0.62 seconds
Started May 07 12:57:44 PM PDT 24
Finished May 07 12:57:46 PM PDT 24
Peak memory 203712 kb
Host smart-a15775e1-ec03-46d1-bb9b-266d26063e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358025685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.358025685
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.1663465668
Short name T1251
Test name
Test status
Simulation time 106605295 ps
CPU time 1.54 seconds
Started May 07 12:57:33 PM PDT 24
Finished May 07 12:57:36 PM PDT 24
Peak memory 212416 kb
Host smart-a37602ad-a9bd-41a6-8e69-9b842131ea77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663465668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.1663465668
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.3555190550
Short name T463
Test name
Test status
Simulation time 799080151 ps
CPU time 19.45 seconds
Started May 07 12:57:34 PM PDT 24
Finished May 07 12:57:55 PM PDT 24
Peak memory 281724 kb
Host smart-62cb7f90-f562-41f5-84a2-aa0123552bc7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555190550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.3555190550
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.4237001784
Short name T784
Test name
Test status
Simulation time 7854899503 ps
CPU time 60.85 seconds
Started May 07 12:57:33 PM PDT 24
Finished May 07 12:58:35 PM PDT 24
Peak memory 675148 kb
Host smart-70ee1c5c-48b1-4660-b828-6a00c2d1056d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237001784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.4237001784
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.177254264
Short name T946
Test name
Test status
Simulation time 1446342494 ps
CPU time 48.07 seconds
Started May 07 12:57:34 PM PDT 24
Finished May 07 12:58:23 PM PDT 24
Peak memory 549716 kb
Host smart-48ec479f-5a7c-4f6f-b3c4-7b51bc6a0355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177254264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.177254264
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.247984803
Short name T404
Test name
Test status
Simulation time 896508194 ps
CPU time 0.96 seconds
Started May 07 12:57:38 PM PDT 24
Finished May 07 12:57:39 PM PDT 24
Peak memory 203776 kb
Host smart-af625fb5-43fd-453a-8b86-a1682e09119d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247984803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fm
t.247984803
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.367268930
Short name T1353
Test name
Test status
Simulation time 500580406 ps
CPU time 4.42 seconds
Started May 07 12:57:33 PM PDT 24
Finished May 07 12:57:38 PM PDT 24
Peak memory 235580 kb
Host smart-9aaca5c0-6ead-4505-8d09-e4aa5e9c2e25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367268930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.
367268930
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.1008822946
Short name T238
Test name
Test status
Simulation time 2947362053 ps
CPU time 82.9 seconds
Started May 07 12:57:33 PM PDT 24
Finished May 07 12:58:57 PM PDT 24
Peak memory 900524 kb
Host smart-90853d41-da53-4987-8cf5-2dd30f748cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008822946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.1008822946
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.2472952282
Short name T965
Test name
Test status
Simulation time 764623312 ps
CPU time 7.53 seconds
Started May 07 12:57:42 PM PDT 24
Finished May 07 12:57:51 PM PDT 24
Peak memory 203896 kb
Host smart-2ef70552-b714-4ccd-816e-adb909f12661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472952282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.2472952282
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.3599150361
Short name T1266
Test name
Test status
Simulation time 2699974330 ps
CPU time 68.88 seconds
Started May 07 12:57:40 PM PDT 24
Finished May 07 12:58:50 PM PDT 24
Peak memory 349296 kb
Host smart-c4aa2ab2-4427-461f-ac88-b8326643069c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599150361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.3599150361
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.26060187
Short name T619
Test name
Test status
Simulation time 270815409 ps
CPU time 0.66 seconds
Started May 07 12:57:35 PM PDT 24
Finished May 07 12:57:37 PM PDT 24
Peak memory 203712 kb
Host smart-ce8962a9-b50a-4da7-bd01-dc3f7fd376a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26060187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.26060187
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.56948847
Short name T1286
Test name
Test status
Simulation time 8455872598 ps
CPU time 60.94 seconds
Started May 07 12:57:33 PM PDT 24
Finished May 07 12:58:34 PM PDT 24
Peak memory 690764 kb
Host smart-6f221ac3-8399-47e3-b4b8-c5668fa99500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56948847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.56948847
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.4153722305
Short name T1354
Test name
Test status
Simulation time 994141048 ps
CPU time 20.44 seconds
Started May 07 12:57:33 PM PDT 24
Finished May 07 12:57:55 PM PDT 24
Peak memory 317008 kb
Host smart-669c9ef3-4a7a-47cc-a1d5-0849ed32e746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153722305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.4153722305
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.132695868
Short name T915
Test name
Test status
Simulation time 114950315264 ps
CPU time 1921.34 seconds
Started May 07 12:57:34 PM PDT 24
Finished May 07 01:29:37 PM PDT 24
Peak memory 3456604 kb
Host smart-865b2536-b31c-4e1d-8056-747e88478cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132695868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.132695868
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.2871398979
Short name T371
Test name
Test status
Simulation time 529137381 ps
CPU time 8.16 seconds
Started May 07 12:57:33 PM PDT 24
Finished May 07 12:57:43 PM PDT 24
Peak memory 220304 kb
Host smart-830fde47-4f2d-4ded-806a-4711dca181a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871398979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.2871398979
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.936467264
Short name T885
Test name
Test status
Simulation time 3361497074 ps
CPU time 3.94 seconds
Started May 07 12:57:37 PM PDT 24
Finished May 07 12:57:41 PM PDT 24
Peak memory 212976 kb
Host smart-eb0ea499-37b8-4b4e-8924-34c742e67582
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936467264 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.936467264
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.3324859195
Short name T839
Test name
Test status
Simulation time 10035632435 ps
CPU time 62.58 seconds
Started May 07 12:57:36 PM PDT 24
Finished May 07 12:58:39 PM PDT 24
Peak memory 491940 kb
Host smart-a34bc9c4-2740-4907-9d24-ccc578485c56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324859195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.3324859195
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.1033919586
Short name T68
Test name
Test status
Simulation time 10058632950 ps
CPU time 94.54 seconds
Started May 07 12:57:36 PM PDT 24
Finished May 07 12:59:11 PM PDT 24
Peak memory 572872 kb
Host smart-b8cc9dea-03b3-44b7-9318-ef6876e7edb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033919586 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.1033919586
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.4212669518
Short name T876
Test name
Test status
Simulation time 460893451 ps
CPU time 2.44 seconds
Started May 07 12:57:35 PM PDT 24
Finished May 07 12:57:39 PM PDT 24
Peak memory 203756 kb
Host smart-ba37550c-ffeb-4167-9de3-89dec6bc1ae5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212669518 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.4212669518
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.1808761106
Short name T373
Test name
Test status
Simulation time 1230191131 ps
CPU time 6.24 seconds
Started May 07 12:57:33 PM PDT 24
Finished May 07 12:57:40 PM PDT 24
Peak memory 218080 kb
Host smart-1fcad52b-8e8b-4df4-88c7-4b433e168a0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808761106 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.1808761106
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.745060500
Short name T517
Test name
Test status
Simulation time 15361769235 ps
CPU time 38.72 seconds
Started May 07 12:57:35 PM PDT 24
Finished May 07 12:58:14 PM PDT 24
Peak memory 957512 kb
Host smart-753c9e2b-d0a4-4e3e-9a6e-b62c386d079a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745060500 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.745060500
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.1841539667
Short name T495
Test name
Test status
Simulation time 563750646 ps
CPU time 9.39 seconds
Started May 07 12:57:35 PM PDT 24
Finished May 07 12:57:45 PM PDT 24
Peak memory 203788 kb
Host smart-da8ed908-ee11-48a3-affc-d5d438b4028b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841539667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.1841539667
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.1220237724
Short name T696
Test name
Test status
Simulation time 1371875869 ps
CPU time 59.58 seconds
Started May 07 12:57:33 PM PDT 24
Finished May 07 12:58:33 PM PDT 24
Peak memory 205628 kb
Host smart-0e765505-65e5-432c-9803-58e55c95b99a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220237724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.1220237724
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.1648087940
Short name T578
Test name
Test status
Simulation time 14320005364 ps
CPU time 29.89 seconds
Started May 07 12:57:34 PM PDT 24
Finished May 07 12:58:05 PM PDT 24
Peak memory 203940 kb
Host smart-92290606-cad4-4060-bfc1-f559fd12ee4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648087940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.1648087940
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.630549532
Short name T964
Test name
Test status
Simulation time 24831478112 ps
CPU time 502.22 seconds
Started May 07 12:57:35 PM PDT 24
Finished May 07 01:05:58 PM PDT 24
Peak memory 2820884 kb
Host smart-0feedb4b-028b-4467-bb07-35804fc7c1d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630549532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_t
arget_stretch.630549532
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.2021514013
Short name T955
Test name
Test status
Simulation time 5572455203 ps
CPU time 7.14 seconds
Started May 07 12:57:32 PM PDT 24
Finished May 07 12:57:40 PM PDT 24
Peak memory 203964 kb
Host smart-392949e0-4d55-4540-9655-38e0e5028674
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021514013 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.2021514013
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.902787896
Short name T1078
Test name
Test status
Simulation time 48128775 ps
CPU time 0.63 seconds
Started May 07 12:57:51 PM PDT 24
Finished May 07 12:57:53 PM PDT 24
Peak memory 203676 kb
Host smart-b7d1332c-b190-4f10-9431-143d740a3f38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902787896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.902787896
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.2502212407
Short name T432
Test name
Test status
Simulation time 234760927 ps
CPU time 1.41 seconds
Started May 07 12:57:41 PM PDT 24
Finished May 07 12:57:43 PM PDT 24
Peak memory 220312 kb
Host smart-289fbaac-f64c-42d4-8105-895190f3cdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502212407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.2502212407
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.765225283
Short name T620
Test name
Test status
Simulation time 692641991 ps
CPU time 9.59 seconds
Started May 07 12:57:39 PM PDT 24
Finished May 07 12:57:49 PM PDT 24
Peak memory 238720 kb
Host smart-81897c6b-1ad0-4064-9d5d-ccc00678ec97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765225283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empt
y.765225283
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.4037460162
Short name T77
Test name
Test status
Simulation time 1600868603 ps
CPU time 56.13 seconds
Started May 07 12:57:40 PM PDT 24
Finished May 07 12:58:37 PM PDT 24
Peak memory 593780 kb
Host smart-1e8ed310-5e3e-4aad-8c74-6bf1ea876e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037460162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.4037460162
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.120263464
Short name T712
Test name
Test status
Simulation time 9429735879 ps
CPU time 72.45 seconds
Started May 07 12:57:39 PM PDT 24
Finished May 07 12:58:53 PM PDT 24
Peak memory 793404 kb
Host smart-ef0ebecb-4960-4725-a098-ef97a6e11b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120263464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.120263464
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.53744057
Short name T461
Test name
Test status
Simulation time 1308889446 ps
CPU time 0.98 seconds
Started May 07 12:57:42 PM PDT 24
Finished May 07 12:57:44 PM PDT 24
Peak memory 203800 kb
Host smart-8ae5c0e0-3e8e-4511-b603-2bd7dc3768ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53744057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fmt
.53744057
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.3986141513
Short name T328
Test name
Test status
Simulation time 712750233 ps
CPU time 10.49 seconds
Started May 07 12:57:43 PM PDT 24
Finished May 07 12:57:55 PM PDT 24
Peak memory 237936 kb
Host smart-6535fc8a-64f4-48d9-ab06-79fb4c571b41
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986141513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.3986141513
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1955827804
Short name T376
Test name
Test status
Simulation time 12826119258 ps
CPU time 216.29 seconds
Started May 07 12:57:40 PM PDT 24
Finished May 07 01:01:17 PM PDT 24
Peak memory 945596 kb
Host smart-35e3b4d9-47d9-4dad-9925-1f7cb5a7bec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955827804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1955827804
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.4248637458
Short name T603
Test name
Test status
Simulation time 1780905829 ps
CPU time 11.65 seconds
Started May 07 12:57:46 PM PDT 24
Finished May 07 12:57:59 PM PDT 24
Peak memory 203884 kb
Host smart-5b9931e4-ee10-458e-bc72-71c853737f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248637458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.4248637458
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.2516614503
Short name T601
Test name
Test status
Simulation time 1251996805 ps
CPU time 54.73 seconds
Started May 07 12:57:45 PM PDT 24
Finished May 07 12:58:41 PM PDT 24
Peak memory 341320 kb
Host smart-05996d6e-513e-4f6d-b681-ce3616b58c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516614503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.2516614503
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.4187598611
Short name T1270
Test name
Test status
Simulation time 19208796 ps
CPU time 0.66 seconds
Started May 07 12:57:41 PM PDT 24
Finished May 07 12:57:43 PM PDT 24
Peak memory 203724 kb
Host smart-1e8d1669-27d8-4141-b3ae-6619f5e9bfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187598611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.4187598611
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.1613934948
Short name T44
Test name
Test status
Simulation time 54061763081 ps
CPU time 1699.69 seconds
Started May 07 12:57:41 PM PDT 24
Finished May 07 01:26:02 PM PDT 24
Peak memory 3237164 kb
Host smart-35c04be2-8395-4021-a792-41281f3f8971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613934948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.1613934948
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.2124879922
Short name T625
Test name
Test status
Simulation time 6862616873 ps
CPU time 92.77 seconds
Started May 07 12:57:41 PM PDT 24
Finished May 07 12:59:16 PM PDT 24
Peak memory 373704 kb
Host smart-979c1614-367f-4735-9541-baaf68674ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124879922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.2124879922
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.1430481784
Short name T440
Test name
Test status
Simulation time 33446096952 ps
CPU time 3032.4 seconds
Started May 07 12:57:39 PM PDT 24
Finished May 07 01:48:13 PM PDT 24
Peak memory 4021372 kb
Host smart-371ed15b-eeef-45fa-85ab-44fcea2ed583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430481784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.1430481784
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.2271165830
Short name T526
Test name
Test status
Simulation time 1924675654 ps
CPU time 24.15 seconds
Started May 07 12:57:43 PM PDT 24
Finished May 07 12:58:08 PM PDT 24
Peak memory 212004 kb
Host smart-d795639a-933f-4b0c-b2f4-017234ba7adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271165830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.2271165830
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.2413771204
Short name T651
Test name
Test status
Simulation time 1109850393 ps
CPU time 5.39 seconds
Started May 07 12:57:48 PM PDT 24
Finished May 07 12:57:55 PM PDT 24
Peak memory 214044 kb
Host smart-2958fe94-bffe-4dce-bcce-0676b8e2a5b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413771204 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2413771204
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.3693234785
Short name T754
Test name
Test status
Simulation time 10225565062 ps
CPU time 32.15 seconds
Started May 07 12:57:41 PM PDT 24
Finished May 07 12:58:15 PM PDT 24
Peak memory 378616 kb
Host smart-53ab47cb-baba-4ca4-a2b2-8f52a9910398
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693234785 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.3693234785
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.2043042516
Short name T516
Test name
Test status
Simulation time 10186183206 ps
CPU time 33.01 seconds
Started May 07 12:57:40 PM PDT 24
Finished May 07 12:58:14 PM PDT 24
Peak memory 386320 kb
Host smart-3ae6888a-6278-4921-a98c-7197f56b846a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043042516 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.2043042516
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.1783783872
Short name T958
Test name
Test status
Simulation time 930323672 ps
CPU time 2.76 seconds
Started May 07 12:57:44 PM PDT 24
Finished May 07 12:57:48 PM PDT 24
Peak memory 203924 kb
Host smart-9957c49b-443e-4ec9-91ec-1fa777c68e93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783783872 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.1783783872
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.2744996815
Short name T806
Test name
Test status
Simulation time 2479996354 ps
CPU time 4.05 seconds
Started May 07 12:57:41 PM PDT 24
Finished May 07 12:57:47 PM PDT 24
Peak memory 204436 kb
Host smart-6fa246c0-98f0-4ee3-a753-3021eeb21caf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744996815 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.2744996815
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.401818923
Short name T963
Test name
Test status
Simulation time 15490676214 ps
CPU time 154.39 seconds
Started May 07 12:57:42 PM PDT 24
Finished May 07 01:00:18 PM PDT 24
Peak memory 2101860 kb
Host smart-8379adb1-89f1-476c-96eb-1ef20cb08036
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401818923 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.401818923
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.3650957061
Short name T1152
Test name
Test status
Simulation time 3331820226 ps
CPU time 11.87 seconds
Started May 07 12:57:40 PM PDT 24
Finished May 07 12:57:53 PM PDT 24
Peak memory 203912 kb
Host smart-57299735-eda5-45ca-a8ed-32d0abb7eb41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650957061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.3650957061
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.3327544422
Short name T1264
Test name
Test status
Simulation time 8049887594 ps
CPU time 35.74 seconds
Started May 07 12:57:40 PM PDT 24
Finished May 07 12:58:17 PM PDT 24
Peak memory 230376 kb
Host smart-b12ae337-4514-48d5-a274-f10d6af1d4b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327544422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.3327544422
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.72165161
Short name T967
Test name
Test status
Simulation time 55629988237 ps
CPU time 597.55 seconds
Started May 07 12:57:39 PM PDT 24
Finished May 07 01:07:37 PM PDT 24
Peak memory 5101424 kb
Host smart-89328b69-4384-4b5e-a734-82891cb4bc4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72165161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stress_wr.72165161
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.3388106524
Short name T1107
Test name
Test status
Simulation time 11433569235 ps
CPU time 137.91 seconds
Started May 07 12:57:42 PM PDT 24
Finished May 07 01:00:01 PM PDT 24
Peak memory 658044 kb
Host smart-bc7581c5-78b0-44f3-8fc1-cb04954383b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388106524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.3388106524
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.3408357846
Short name T658
Test name
Test status
Simulation time 5610494323 ps
CPU time 7.01 seconds
Started May 07 12:57:40 PM PDT 24
Finished May 07 12:57:48 PM PDT 24
Peak memory 220272 kb
Host smart-3a2cda8d-fb3c-4911-86d4-968d0dd6641e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408357846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.3408357846
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_unexp_stop.3555800126
Short name T1047
Test name
Test status
Simulation time 3582735931 ps
CPU time 7.28 seconds
Started May 07 12:57:41 PM PDT 24
Finished May 07 12:57:49 PM PDT 24
Peak memory 203956 kb
Host smart-bd914445-6f55-45e9-ae6c-65329d19f3f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555800126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.i2c_target_unexp_stop.3555800126
Directory /workspace/37.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/38.i2c_alert_test.2994263629
Short name T968
Test name
Test status
Simulation time 17556523 ps
CPU time 0.65 seconds
Started May 07 12:57:52 PM PDT 24
Finished May 07 12:57:54 PM PDT 24
Peak memory 203752 kb
Host smart-65847583-544b-42b2-9469-2c274683d8cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994263629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.2994263629
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.1757911971
Short name T1060
Test name
Test status
Simulation time 214111853 ps
CPU time 1.3 seconds
Started May 07 12:57:46 PM PDT 24
Finished May 07 12:57:48 PM PDT 24
Peak memory 212332 kb
Host smart-d897ff11-6d0a-4d64-b1a5-084e4bc2f59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757911971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.1757911971
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2339277720
Short name T785
Test name
Test status
Simulation time 111460039 ps
CPU time 5.06 seconds
Started May 07 12:57:45 PM PDT 24
Finished May 07 12:57:51 PM PDT 24
Peak memory 218864 kb
Host smart-299b85f0-3f63-433e-9a39-511c5ca1961a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339277720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2339277720
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.1681653295
Short name T662
Test name
Test status
Simulation time 3168190679 ps
CPU time 104.17 seconds
Started May 07 12:57:47 PM PDT 24
Finished May 07 12:59:33 PM PDT 24
Peak memory 589268 kb
Host smart-3e1d1ca4-ae0c-44c6-8498-9d0e6ebd5791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681653295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.1681653295
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.46558676
Short name T542
Test name
Test status
Simulation time 5787233174 ps
CPU time 101.17 seconds
Started May 07 12:57:46 PM PDT 24
Finished May 07 12:59:28 PM PDT 24
Peak memory 550920 kb
Host smart-b2e48636-c15d-4de7-b580-c119eb718082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46558676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.46558676
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.3211073645
Short name T420
Test name
Test status
Simulation time 676662664 ps
CPU time 1.06 seconds
Started May 07 12:57:51 PM PDT 24
Finished May 07 12:57:54 PM PDT 24
Peak memory 203732 kb
Host smart-cb622a80-6848-4a52-8b00-b171bc6e0039
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211073645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.3211073645
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.4148222600
Short name T375
Test name
Test status
Simulation time 190155065 ps
CPU time 4.49 seconds
Started May 07 12:57:46 PM PDT 24
Finished May 07 12:57:52 PM PDT 24
Peak memory 203884 kb
Host smart-37a20602-3307-4676-b826-bef3ae2b4ef0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148222600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.4148222600
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.3612376971
Short name T528
Test name
Test status
Simulation time 38146422744 ps
CPU time 287.72 seconds
Started May 07 12:57:46 PM PDT 24
Finished May 07 01:02:35 PM PDT 24
Peak memory 1125540 kb
Host smart-f448cf02-cbc8-4bad-aecc-232f41c41dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612376971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.3612376971
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.3492284734
Short name T1277
Test name
Test status
Simulation time 550278644 ps
CPU time 4.21 seconds
Started May 07 12:57:54 PM PDT 24
Finished May 07 12:57:59 PM PDT 24
Peak memory 203916 kb
Host smart-3cc0ca75-49ed-4890-9e46-f5774127b4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492284734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.3492284734
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.2247299725
Short name T1308
Test name
Test status
Simulation time 7412060793 ps
CPU time 31.91 seconds
Started May 07 12:57:52 PM PDT 24
Finished May 07 12:58:25 PM PDT 24
Peak memory 358924 kb
Host smart-e5d75da6-3b96-4377-a8a5-71f8ae916f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247299725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.2247299725
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.2603510169
Short name T53
Test name
Test status
Simulation time 19188856 ps
CPU time 0.66 seconds
Started May 07 12:57:49 PM PDT 24
Finished May 07 12:57:50 PM PDT 24
Peak memory 203724 kb
Host smart-85d4cc9c-69d3-496e-b578-893725c91ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603510169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.2603510169
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.904294345
Short name T343
Test name
Test status
Simulation time 2951817483 ps
CPU time 42.29 seconds
Started May 07 12:57:46 PM PDT 24
Finished May 07 12:58:29 PM PDT 24
Peak memory 315060 kb
Host smart-726666f0-c265-4e79-8e66-02880418978c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904294345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.904294345
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.1465424198
Short name T1079
Test name
Test status
Simulation time 16052563997 ps
CPU time 67.83 seconds
Started May 07 12:57:49 PM PDT 24
Finished May 07 12:59:02 PM PDT 24
Peak memory 299912 kb
Host smart-444cc242-2fcf-4e97-b7c2-f7e42d24fd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465424198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1465424198
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.3135200406
Short name T802
Test name
Test status
Simulation time 1844004227 ps
CPU time 20.54 seconds
Started May 07 12:57:46 PM PDT 24
Finished May 07 12:58:07 PM PDT 24
Peak memory 212092 kb
Host smart-c990d9e1-f940-47dc-b65f-3ad727d16d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135200406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.3135200406
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.3685976810
Short name T1159
Test name
Test status
Simulation time 1843033214 ps
CPU time 2.79 seconds
Started May 07 12:57:52 PM PDT 24
Finished May 07 12:57:56 PM PDT 24
Peak memory 203884 kb
Host smart-eb38cccc-5ba8-46d9-879f-e3ed6e0f6a7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685976810 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.3685976810
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.3982275553
Short name T1274
Test name
Test status
Simulation time 10724410136 ps
CPU time 11.93 seconds
Started May 07 12:57:53 PM PDT 24
Finished May 07 12:58:07 PM PDT 24
Peak memory 267456 kb
Host smart-7b5e314e-bb44-4d7a-8eb2-7f8b918d7ab8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982275553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.3982275553
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.654474650
Short name T498
Test name
Test status
Simulation time 10484649793 ps
CPU time 14.35 seconds
Started May 07 12:57:52 PM PDT 24
Finished May 07 12:58:07 PM PDT 24
Peak memory 293408 kb
Host smart-317c512c-dd61-4a39-b8aa-a8485b4c8dc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654474650 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_fifo_reset_tx.654474650
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.67220609
Short name T266
Test name
Test status
Simulation time 378218535 ps
CPU time 2.61 seconds
Started May 07 12:57:55 PM PDT 24
Finished May 07 12:57:58 PM PDT 24
Peak memory 203940 kb
Host smart-a49f20ce-b86c-4ed6-ace4-41421e0033e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67220609 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.i2c_target_hrst.67220609
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.520787756
Short name T914
Test name
Test status
Simulation time 3015030553 ps
CPU time 7.81 seconds
Started May 07 12:57:56 PM PDT 24
Finished May 07 12:58:05 PM PDT 24
Peak memory 220052 kb
Host smart-92f6f445-62b2-4d37-80dd-ec8f78c5feeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520787756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_intr_smoke.520787756
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.988903306
Short name T370
Test name
Test status
Simulation time 18870052092 ps
CPU time 290.22 seconds
Started May 07 12:57:54 PM PDT 24
Finished May 07 01:02:45 PM PDT 24
Peak memory 2955048 kb
Host smart-28f31111-c8d1-4292-a64c-307b63d3bf20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988903306 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.988903306
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.1410500104
Short name T665
Test name
Test status
Simulation time 6326736024 ps
CPU time 31.48 seconds
Started May 07 12:57:45 PM PDT 24
Finished May 07 12:58:18 PM PDT 24
Peak memory 203940 kb
Host smart-c4014f4b-e65a-40d7-9e0c-ce95bfc5ebc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410500104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.1410500104
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.757479969
Short name T300
Test name
Test status
Simulation time 261779773 ps
CPU time 4.46 seconds
Started May 07 12:57:49 PM PDT 24
Finished May 07 12:57:54 PM PDT 24
Peak memory 203812 kb
Host smart-43c904f1-3b49-40f3-a165-f9a27cb134a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757479969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_rd.757479969
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.125306009
Short name T491
Test name
Test status
Simulation time 50783053440 ps
CPU time 405.05 seconds
Started May 07 12:57:44 PM PDT 24
Finished May 07 01:04:31 PM PDT 24
Peak memory 3857864 kb
Host smart-45e7422a-bfcf-476a-9831-7c1578804c09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125306009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_wr.125306009
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.443880774
Short name T996
Test name
Test status
Simulation time 20959336415 ps
CPU time 330.64 seconds
Started May 07 12:57:54 PM PDT 24
Finished May 07 01:03:26 PM PDT 24
Peak memory 2091328 kb
Host smart-adeebeb0-c7d1-4e64-927e-b18f87007d05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443880774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_t
arget_stretch.443880774
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.3957253363
Short name T1237
Test name
Test status
Simulation time 4915740316 ps
CPU time 7.35 seconds
Started May 07 12:57:52 PM PDT 24
Finished May 07 12:58:01 PM PDT 24
Peak memory 212124 kb
Host smart-fd0120ef-98f8-42e9-8651-ec6529ef0aab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957253363 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.3957253363
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1200553287
Short name T947
Test name
Test status
Simulation time 24555892 ps
CPU time 0.63 seconds
Started May 07 12:58:07 PM PDT 24
Finished May 07 12:58:09 PM PDT 24
Peak memory 203792 kb
Host smart-dbb889db-9db9-4bae-8b2e-181844b94705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200553287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1200553287
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.4132551245
Short name T1098
Test name
Test status
Simulation time 103987427 ps
CPU time 1.8 seconds
Started May 07 12:58:04 PM PDT 24
Finished May 07 12:58:07 PM PDT 24
Peak memory 220432 kb
Host smart-412c03eb-4df3-440f-9101-a6dd7d743b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132551245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.4132551245
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.588452287
Short name T467
Test name
Test status
Simulation time 323976969 ps
CPU time 5.79 seconds
Started May 07 12:58:03 PM PDT 24
Finished May 07 12:58:10 PM PDT 24
Peak memory 264256 kb
Host smart-20c4724a-c0cd-44ec-ae1d-c9787d435681
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588452287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empt
y.588452287
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.3386985027
Short name T1256
Test name
Test status
Simulation time 40789478949 ps
CPU time 97.64 seconds
Started May 07 12:58:01 PM PDT 24
Finished May 07 12:59:40 PM PDT 24
Peak memory 796512 kb
Host smart-65b0aa08-5873-4ebd-bc92-225ce435b863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386985027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.3386985027
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.2688199320
Short name T654
Test name
Test status
Simulation time 1218535690 ps
CPU time 29.78 seconds
Started May 07 12:57:51 PM PDT 24
Finished May 07 12:58:22 PM PDT 24
Peak memory 494144 kb
Host smart-1626b880-2e09-4fec-8987-f52a6e593672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688199320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2688199320
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.2757061972
Short name T1317
Test name
Test status
Simulation time 92286210 ps
CPU time 0.9 seconds
Started May 07 12:58:03 PM PDT 24
Finished May 07 12:58:05 PM PDT 24
Peak memory 203740 kb
Host smart-ed95b189-e192-449a-8de3-e09b72df5da5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757061972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.2757061972
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.260011250
Short name T1310
Test name
Test status
Simulation time 875960837 ps
CPU time 11.3 seconds
Started May 07 12:58:07 PM PDT 24
Finished May 07 12:58:20 PM PDT 24
Peak memory 241148 kb
Host smart-e194bfd6-e178-42ef-bbd4-cf17216c8946
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260011250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.
260011250
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.1857940837
Short name T986
Test name
Test status
Simulation time 19823521860 ps
CPU time 326.86 seconds
Started May 07 12:57:54 PM PDT 24
Finished May 07 01:03:22 PM PDT 24
Peak memory 1165072 kb
Host smart-b036386e-6eb5-489b-9b6e-8ecff1985f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857940837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1857940837
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.665261204
Short name T191
Test name
Test status
Simulation time 1253106503 ps
CPU time 14 seconds
Started May 07 12:58:08 PM PDT 24
Finished May 07 12:58:24 PM PDT 24
Peak memory 203888 kb
Host smart-cced8979-3807-498a-83b6-e67435803d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665261204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.665261204
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.2329668312
Short name T1333
Test name
Test status
Simulation time 4464250177 ps
CPU time 72.92 seconds
Started May 07 12:58:07 PM PDT 24
Finished May 07 12:59:21 PM PDT 24
Peak memory 336884 kb
Host smart-7dcb4012-c685-47b1-88da-f2c2d8e35bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329668312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.2329668312
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.3823964525
Short name T851
Test name
Test status
Simulation time 128083630 ps
CPU time 0.61 seconds
Started May 07 12:57:52 PM PDT 24
Finished May 07 12:57:54 PM PDT 24
Peak memory 203728 kb
Host smart-1c0a24e6-6ca4-44b9-8546-8430dd3a87fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823964525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.3823964525
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.3685313836
Short name T475
Test name
Test status
Simulation time 7617340147 ps
CPU time 380.11 seconds
Started May 07 12:58:06 PM PDT 24
Finished May 07 01:04:28 PM PDT 24
Peak memory 845700 kb
Host smart-f44cd0e6-94a1-4efc-9f8a-ae0bd9ed6e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685313836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.3685313836
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.3758830672
Short name T320
Test name
Test status
Simulation time 1129274592 ps
CPU time 27.08 seconds
Started May 07 12:57:54 PM PDT 24
Finished May 07 12:58:23 PM PDT 24
Peak memory 349628 kb
Host smart-1e0cd56d-2c68-4837-9f14-95c49567f8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758830672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.3758830672
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.2556410261
Short name T106
Test name
Test status
Simulation time 657684350 ps
CPU time 12.29 seconds
Started May 07 12:58:01 PM PDT 24
Finished May 07 12:58:15 PM PDT 24
Peak memory 220164 kb
Host smart-1298199f-7eb7-4ba4-a20c-71f3a4bc5edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556410261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.2556410261
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.121517824
Short name T1120
Test name
Test status
Simulation time 2712658431 ps
CPU time 3.63 seconds
Started May 07 12:58:02 PM PDT 24
Finished May 07 12:58:07 PM PDT 24
Peak memory 203952 kb
Host smart-81b97911-874b-4f3e-9ce2-a334c7ef8e2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121517824 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.121517824
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.3093173379
Short name T72
Test name
Test status
Simulation time 10055952853 ps
CPU time 72.89 seconds
Started May 07 12:58:06 PM PDT 24
Finished May 07 12:59:20 PM PDT 24
Peak memory 509944 kb
Host smart-8f829672-dc55-49cf-9894-9ad70ecc369b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093173379 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.3093173379
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.1646683577
Short name T1322
Test name
Test status
Simulation time 10108006205 ps
CPU time 76.07 seconds
Started May 07 12:58:01 PM PDT 24
Finished May 07 12:59:18 PM PDT 24
Peak memory 469084 kb
Host smart-e091ef6a-807a-4151-a68b-2e196013f8f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646683577 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.1646683577
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.2196411412
Short name T1181
Test name
Test status
Simulation time 803529452 ps
CPU time 2.7 seconds
Started May 07 12:58:02 PM PDT 24
Finished May 07 12:58:06 PM PDT 24
Peak memory 203888 kb
Host smart-8d7ec7fa-6238-4ed1-9f2c-c5918c16cbf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196411412 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.2196411412
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.1771537422
Short name T344
Test name
Test status
Simulation time 1092631021 ps
CPU time 6 seconds
Started May 07 12:58:02 PM PDT 24
Finished May 07 12:58:10 PM PDT 24
Peak memory 212140 kb
Host smart-933b76ac-0d32-442f-86f5-56be1df9e341
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771537422 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.1771537422
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.2709162219
Short name T1023
Test name
Test status
Simulation time 8103894075 ps
CPU time 20.57 seconds
Started May 07 12:58:02 PM PDT 24
Finished May 07 12:58:24 PM PDT 24
Peak memory 359188 kb
Host smart-c457f27f-1627-4a02-b23f-cac57d5e0e1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709162219 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.2709162219
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.3864761413
Short name T1280
Test name
Test status
Simulation time 3513656727 ps
CPU time 11.9 seconds
Started May 07 12:58:07 PM PDT 24
Finished May 07 12:58:21 PM PDT 24
Peak memory 203920 kb
Host smart-28f6ceb3-0afc-4817-ac6f-0a18a29ed775
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864761413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.3864761413
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.3682999778
Short name T1058
Test name
Test status
Simulation time 10657363827 ps
CPU time 64.73 seconds
Started May 07 12:58:08 PM PDT 24
Finished May 07 12:59:15 PM PDT 24
Peak memory 207960 kb
Host smart-18ad8cb5-c708-475a-b1f1-74011ae125a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682999778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.3682999778
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.3062855733
Short name T19
Test name
Test status
Simulation time 45226070661 ps
CPU time 753.15 seconds
Started May 07 12:58:07 PM PDT 24
Finished May 07 01:10:41 PM PDT 24
Peak memory 6107940 kb
Host smart-c8db0c40-8a88-4277-95d2-0915bae18399
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062855733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.3062855733
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.3831306107
Short name T1345
Test name
Test status
Simulation time 4660679959 ps
CPU time 6.23 seconds
Started May 07 12:58:03 PM PDT 24
Finished May 07 12:58:10 PM PDT 24
Peak memory 219608 kb
Host smart-5bcf0473-a9f0-4a9f-85c2-65ab7085b419
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831306107 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.3831306107
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.115088291
Short name T1187
Test name
Test status
Simulation time 16964560 ps
CPU time 0.62 seconds
Started May 07 12:52:50 PM PDT 24
Finished May 07 12:52:52 PM PDT 24
Peak memory 203804 kb
Host smart-e764e64e-ceeb-443b-9093-47740f51ee0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115088291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.115088291
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.61237110
Short name T626
Test name
Test status
Simulation time 70896972 ps
CPU time 1.56 seconds
Started May 07 12:52:43 PM PDT 24
Finished May 07 12:52:46 PM PDT 24
Peak memory 212132 kb
Host smart-3d5c03d9-3c5d-4853-ab30-825dcbcd85ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61237110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.61237110
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.154954509
Short name T1164
Test name
Test status
Simulation time 970885992 ps
CPU time 8.66 seconds
Started May 07 12:52:39 PM PDT 24
Finished May 07 12:52:49 PM PDT 24
Peak memory 310456 kb
Host smart-c9d40cd6-c828-41aa-9df6-c0fb44144ab8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154954509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty
.154954509
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.1585394003
Short name T157
Test name
Test status
Simulation time 3632440788 ps
CPU time 52.27 seconds
Started May 07 12:52:43 PM PDT 24
Finished May 07 12:53:37 PM PDT 24
Peak memory 544284 kb
Host smart-2b44df07-cd79-4fbd-8da3-9ae1ee08cb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585394003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.1585394003
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.1406236953
Short name T584
Test name
Test status
Simulation time 1341353592 ps
CPU time 90.5 seconds
Started May 07 12:52:39 PM PDT 24
Finished May 07 12:54:10 PM PDT 24
Peak memory 526484 kb
Host smart-7e287448-ef42-4ccb-b0e6-042915afc297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406236953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.1406236953
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2822361476
Short name T988
Test name
Test status
Simulation time 178704097 ps
CPU time 1.01 seconds
Started May 07 12:52:38 PM PDT 24
Finished May 07 12:52:40 PM PDT 24
Peak memory 203760 kb
Host smart-6c898dda-0912-4e88-9cc6-09ec645c3a14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822361476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2822361476
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.870249116
Short name T1048
Test name
Test status
Simulation time 322762438 ps
CPU time 7.39 seconds
Started May 07 12:52:38 PM PDT 24
Finished May 07 12:52:47 PM PDT 24
Peak memory 203744 kb
Host smart-7b461440-07fd-4a9c-8ea5-6fe32ed8438e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870249116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.870249116
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.2979287891
Short name T576
Test name
Test status
Simulation time 38053595060 ps
CPU time 98.23 seconds
Started May 07 12:52:37 PM PDT 24
Finished May 07 12:54:16 PM PDT 24
Peak memory 1000524 kb
Host smart-b565c8a7-8b74-45a1-9833-6d283d80dbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979287891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.2979287891
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.661336425
Short name T919
Test name
Test status
Simulation time 1010622453 ps
CPU time 10.04 seconds
Started May 07 12:52:51 PM PDT 24
Finished May 07 12:53:02 PM PDT 24
Peak memory 204004 kb
Host smart-1470bb33-f933-4cbf-b36b-f534815a6111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661336425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.661336425
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.3127365091
Short name T42
Test name
Test status
Simulation time 1344566672 ps
CPU time 64.09 seconds
Started May 07 12:52:50 PM PDT 24
Finished May 07 12:53:55 PM PDT 24
Peak memory 326184 kb
Host smart-8980dc74-a214-412e-9db0-2b7d065c61d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127365091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.3127365091
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.3472150351
Short name T561
Test name
Test status
Simulation time 30964468 ps
CPU time 0.64 seconds
Started May 07 12:52:38 PM PDT 24
Finished May 07 12:52:40 PM PDT 24
Peak memory 203676 kb
Host smart-29eb9479-8303-41b4-92c5-1d0052778e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472150351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.3472150351
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.2266929804
Short name T329
Test name
Test status
Simulation time 5518864216 ps
CPU time 87.09 seconds
Started May 07 12:52:44 PM PDT 24
Finished May 07 12:54:12 PM PDT 24
Peak memory 881872 kb
Host smart-dde7ddcb-fe81-4803-af09-00880fdc93d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266929804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.2266929804
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.694942937
Short name T305
Test name
Test status
Simulation time 1395666270 ps
CPU time 27.15 seconds
Started May 07 12:52:37 PM PDT 24
Finished May 07 12:53:05 PM PDT 24
Peak memory 305432 kb
Host smart-8e01498b-f303-49dc-a2cb-501d70965ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694942937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.694942937
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.177073793
Short name T875
Test name
Test status
Simulation time 640682288 ps
CPU time 12.68 seconds
Started May 07 12:52:45 PM PDT 24
Finished May 07 12:52:59 PM PDT 24
Peak memory 213784 kb
Host smart-073215c5-6b09-478a-a98c-64a36337209e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177073793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.177073793
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.1281794635
Short name T124
Test name
Test status
Simulation time 188639664 ps
CPU time 0.87 seconds
Started May 07 12:52:50 PM PDT 24
Finished May 07 12:52:52 PM PDT 24
Peak memory 221316 kb
Host smart-5b1e1f44-e358-4063-a712-0edc08ebc215
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281794635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.1281794635
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.3925129888
Short name T631
Test name
Test status
Simulation time 5189085063 ps
CPU time 4.4 seconds
Started May 07 12:52:53 PM PDT 24
Finished May 07 12:52:58 PM PDT 24
Peak memory 204040 kb
Host smart-751ccd01-6ddd-4d45-a080-2f5e583a025c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925129888 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.3925129888
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.724912885
Short name T509
Test name
Test status
Simulation time 10136124498 ps
CPU time 20.69 seconds
Started May 07 12:52:43 PM PDT 24
Finished May 07 12:53:05 PM PDT 24
Peak memory 271864 kb
Host smart-f25abdc7-88a6-4310-a65d-c09035003a93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724912885 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_acq.724912885
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.1396915487
Short name T1213
Test name
Test status
Simulation time 10091953925 ps
CPU time 14.45 seconds
Started May 07 12:52:44 PM PDT 24
Finished May 07 12:52:59 PM PDT 24
Peak memory 267608 kb
Host smart-8cc53852-e35c-4f2e-b99c-643b39590e6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396915487 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.1396915487
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.1536943668
Short name T25
Test name
Test status
Simulation time 1806224299 ps
CPU time 2.73 seconds
Started May 07 12:52:51 PM PDT 24
Finished May 07 12:52:55 PM PDT 24
Peak memory 203892 kb
Host smart-d7f2390d-950b-4cf2-93f3-7ebe9ba6a1fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536943668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.1536943668
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.2539598928
Short name T351
Test name
Test status
Simulation time 426590637 ps
CPU time 2.87 seconds
Started May 07 12:52:44 PM PDT 24
Finished May 07 12:52:48 PM PDT 24
Peak memory 203968 kb
Host smart-1589093c-6fe1-4416-ae95-5230acf3673e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539598928 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.2539598928
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.1499155441
Short name T593
Test name
Test status
Simulation time 22821676701 ps
CPU time 7.73 seconds
Started May 07 12:52:45 PM PDT 24
Finished May 07 12:52:53 PM PDT 24
Peak memory 203916 kb
Host smart-b24788e3-e47f-4b0f-a69a-7af9ed7116fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499155441 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.1499155441
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.1729347100
Short name T1007
Test name
Test status
Simulation time 2009835041 ps
CPU time 28 seconds
Started May 07 12:52:44 PM PDT 24
Finished May 07 12:53:13 PM PDT 24
Peak memory 203936 kb
Host smart-1c2e28d2-e616-44b7-878b-e8ae6190986d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729347100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.1729347100
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.3970062708
Short name T131
Test name
Test status
Simulation time 1587294245 ps
CPU time 69.47 seconds
Started May 07 12:52:43 PM PDT 24
Finished May 07 12:53:54 PM PDT 24
Peak memory 205792 kb
Host smart-821627b7-9893-4f04-bcdd-3f6324ca0e3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970062708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.3970062708
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.3465779937
Short name T331
Test name
Test status
Simulation time 70537731353 ps
CPU time 150.05 seconds
Started May 07 12:52:43 PM PDT 24
Finished May 07 12:55:14 PM PDT 24
Peak memory 1703972 kb
Host smart-0ed64dfd-60dd-4b1c-8068-e31d066868ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465779937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.3465779937
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.3973608951
Short name T1343
Test name
Test status
Simulation time 16831761543 ps
CPU time 976.12 seconds
Started May 07 12:52:44 PM PDT 24
Finished May 07 01:09:02 PM PDT 24
Peak memory 3137840 kb
Host smart-2c02eea0-75e7-4c28-9d08-daea14b62e40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973608951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.3973608951
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1080501070
Short name T447
Test name
Test status
Simulation time 1674577011 ps
CPU time 7.78 seconds
Started May 07 12:52:43 PM PDT 24
Finished May 07 12:52:52 PM PDT 24
Peak memory 220196 kb
Host smart-9e73c0c7-d45e-412b-a512-b2c84d26f9fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080501070 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1080501070
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.2329643773
Short name T303
Test name
Test status
Simulation time 47167309 ps
CPU time 0.64 seconds
Started May 07 12:58:14 PM PDT 24
Finished May 07 12:58:16 PM PDT 24
Peak memory 203968 kb
Host smart-a7badf45-340a-448b-9762-4f1d2f759f9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329643773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.2329643773
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.248661660
Short name T822
Test name
Test status
Simulation time 131564344 ps
CPU time 1.36 seconds
Started May 07 12:58:11 PM PDT 24
Finished May 07 12:58:14 PM PDT 24
Peak memory 211804 kb
Host smart-e9c37756-da98-45da-ae95-7b9aea1de788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248661660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.248661660
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.1483877995
Short name T1093
Test name
Test status
Simulation time 773407329 ps
CPU time 8.44 seconds
Started May 07 12:58:07 PM PDT 24
Finished May 07 12:58:17 PM PDT 24
Peak memory 284664 kb
Host smart-09f71b60-3570-4c6b-87cc-c870324307a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483877995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.1483877995
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.863505717
Short name T471
Test name
Test status
Simulation time 12684255951 ps
CPU time 140.08 seconds
Started May 07 12:58:07 PM PDT 24
Finished May 07 01:00:29 PM PDT 24
Peak memory 679840 kb
Host smart-c04cbf92-56b0-4167-b3c9-55b2ac3df985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863505717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.863505717
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.2274020771
Short name T476
Test name
Test status
Simulation time 4138159351 ps
CPU time 141.94 seconds
Started May 07 12:58:06 PM PDT 24
Finished May 07 01:00:29 PM PDT 24
Peak memory 645204 kb
Host smart-33d9cd3c-7fb7-4e1c-aa98-b3bbea3db2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274020771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.2274020771
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.1374736245
Short name T1173
Test name
Test status
Simulation time 134292055 ps
CPU time 1.13 seconds
Started May 07 12:58:06 PM PDT 24
Finished May 07 12:58:09 PM PDT 24
Peak memory 203852 kb
Host smart-a06ee3fd-6bdb-4ec1-ad6c-b203005dfd7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374736245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.1374736245
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.2821217325
Short name T954
Test name
Test status
Simulation time 241665261 ps
CPU time 2.7 seconds
Started May 07 12:58:06 PM PDT 24
Finished May 07 12:58:10 PM PDT 24
Peak memory 203984 kb
Host smart-b314bd45-28e7-4f0b-a265-70ce294ad1b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821217325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.2821217325
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.2743664403
Short name T62
Test name
Test status
Simulation time 4105361365 ps
CPU time 309.59 seconds
Started May 07 12:58:06 PM PDT 24
Finished May 07 01:03:17 PM PDT 24
Peak memory 1118900 kb
Host smart-ea28d763-6b90-416e-bc0f-cad177c21221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743664403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.2743664403
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.2594505280
Short name T1090
Test name
Test status
Simulation time 473351113 ps
CPU time 3.94 seconds
Started May 07 12:58:11 PM PDT 24
Finished May 07 12:58:16 PM PDT 24
Peak memory 203960 kb
Host smart-23ce7976-5a6a-4e2e-80a8-7d065ddddb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594505280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.2594505280
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.406806307
Short name T1301
Test name
Test status
Simulation time 1693281647 ps
CPU time 81.12 seconds
Started May 07 12:58:16 PM PDT 24
Finished May 07 12:59:38 PM PDT 24
Peak memory 340868 kb
Host smart-77707b81-a0ff-4dd4-bf1a-0f5994a7909f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406806307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.406806307
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.4244955567
Short name T1276
Test name
Test status
Simulation time 22038522 ps
CPU time 0.66 seconds
Started May 07 12:58:08 PM PDT 24
Finished May 07 12:58:11 PM PDT 24
Peak memory 203728 kb
Host smart-f988baa6-27b2-4748-90b5-b61f2d4828ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244955567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.4244955567
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.2540585458
Short name T1030
Test name
Test status
Simulation time 177697726 ps
CPU time 3.64 seconds
Started May 07 12:58:11 PM PDT 24
Finished May 07 12:58:17 PM PDT 24
Peak memory 228444 kb
Host smart-fe1704f2-ad67-4c1d-965e-6890cbc99605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540585458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.2540585458
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.2379638246
Short name T291
Test name
Test status
Simulation time 10945393793 ps
CPU time 28.28 seconds
Started May 07 12:58:08 PM PDT 24
Finished May 07 12:58:38 PM PDT 24
Peak memory 313204 kb
Host smart-c7e33eef-3cb4-456f-8f32-772bcd0d1ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379638246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2379638246
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.1959749100
Short name T210
Test name
Test status
Simulation time 70901804704 ps
CPU time 655.16 seconds
Started May 07 12:58:09 PM PDT 24
Finished May 07 01:09:06 PM PDT 24
Peak memory 2551608 kb
Host smart-95f99bc8-125e-4969-b865-ea839fe1194b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959749100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.1959749100
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.233046275
Short name T797
Test name
Test status
Simulation time 447555107 ps
CPU time 7.65 seconds
Started May 07 12:58:06 PM PDT 24
Finished May 07 12:58:15 PM PDT 24
Peak memory 214696 kb
Host smart-fcd90f17-dba5-43d9-a04d-32fa80ece76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233046275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.233046275
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.1948606358
Short name T846
Test name
Test status
Simulation time 1648555538 ps
CPU time 4.77 seconds
Started May 07 12:58:07 PM PDT 24
Finished May 07 12:58:13 PM PDT 24
Peak memory 212396 kb
Host smart-676213f7-7dda-483e-a62b-7dc857f8c670
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948606358 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.1948606358
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.1606743626
Short name T1064
Test name
Test status
Simulation time 10104427456 ps
CPU time 6.63 seconds
Started May 07 12:58:08 PM PDT 24
Finished May 07 12:58:16 PM PDT 24
Peak memory 227688 kb
Host smart-e843b22f-3e44-4c64-9042-ba6c71006973
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606743626 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.1606743626
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.2155852241
Short name T76
Test name
Test status
Simulation time 10079039952 ps
CPU time 13.16 seconds
Started May 07 12:58:08 PM PDT 24
Finished May 07 12:58:23 PM PDT 24
Peak memory 288576 kb
Host smart-1b1c2545-f229-434b-b472-4016f9a958b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155852241 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.2155852241
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.1793429845
Short name T676
Test name
Test status
Simulation time 940638324 ps
CPU time 2.91 seconds
Started May 07 12:58:12 PM PDT 24
Finished May 07 12:58:17 PM PDT 24
Peak memory 203908 kb
Host smart-ba475ec9-18a8-447d-b8c9-75531c39040a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793429845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.1793429845
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.2540740407
Short name T190
Test name
Test status
Simulation time 1051101221 ps
CPU time 5.6 seconds
Started May 07 12:58:07 PM PDT 24
Finished May 07 12:58:15 PM PDT 24
Peak memory 210468 kb
Host smart-7ebfa025-168b-40f7-a1c8-cfcb157c42e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540740407 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.2540740407
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.4115269814
Short name T908
Test name
Test status
Simulation time 8890562913 ps
CPU time 112.39 seconds
Started May 07 12:58:08 PM PDT 24
Finished May 07 01:00:02 PM PDT 24
Peak memory 2232908 kb
Host smart-118f75b9-ea81-4205-83af-6120b1214b8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115269814 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.4115269814
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.838394560
Short name T558
Test name
Test status
Simulation time 3016046457 ps
CPU time 11.7 seconds
Started May 07 12:58:11 PM PDT 24
Finished May 07 12:58:25 PM PDT 24
Peak memory 203632 kb
Host smart-7f740b75-cf8e-453e-9630-5af217d8d3cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838394560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.838394560
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.3023383103
Short name T849
Test name
Test status
Simulation time 395303981 ps
CPU time 4.84 seconds
Started May 07 12:58:11 PM PDT 24
Finished May 07 12:58:18 PM PDT 24
Peak memory 203748 kb
Host smart-a39b9d4a-0aac-41ff-b179-66cdb032c034
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023383103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.3023383103
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.2291515168
Short name T1028
Test name
Test status
Simulation time 68738774794 ps
CPU time 2587.7 seconds
Started May 07 12:58:06 PM PDT 24
Finished May 07 01:41:16 PM PDT 24
Peak memory 12067804 kb
Host smart-34829961-82a6-4677-9f76-64e692d259e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291515168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.2291515168
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1498086825
Short name T1283
Test name
Test status
Simulation time 48690287919 ps
CPU time 105.23 seconds
Started May 07 12:58:06 PM PDT 24
Finished May 07 12:59:52 PM PDT 24
Peak memory 879188 kb
Host smart-87fdb247-574d-4dad-b8c8-96c07125b060
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498086825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1498086825
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.1254127800
Short name T482
Test name
Test status
Simulation time 1520710623 ps
CPU time 7.32 seconds
Started May 07 12:58:08 PM PDT 24
Finished May 07 12:58:17 PM PDT 24
Peak memory 212048 kb
Host smart-0febec3c-7b25-4aaf-abd1-468dd948d7d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254127800 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.1254127800
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.2958430056
Short name T470
Test name
Test status
Simulation time 65442781 ps
CPU time 0.62 seconds
Started May 07 12:58:20 PM PDT 24
Finished May 07 12:58:22 PM PDT 24
Peak memory 203832 kb
Host smart-7a3436e5-388b-44ca-9a58-c5efd8ca3a6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958430056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.2958430056
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.1990950875
Short name T852
Test name
Test status
Simulation time 112255223 ps
CPU time 1.54 seconds
Started May 07 12:58:13 PM PDT 24
Finished May 07 12:58:15 PM PDT 24
Peak memory 212232 kb
Host smart-e1147a70-b7d0-4a95-ad18-f8b1ce94f015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990950875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.1990950875
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.1616653494
Short name T909
Test name
Test status
Simulation time 330579845 ps
CPU time 16.94 seconds
Started May 07 12:58:14 PM PDT 24
Finished May 07 12:58:32 PM PDT 24
Peak memory 272740 kb
Host smart-313945a8-7c50-47d7-9700-5821f93efe6c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616653494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.1616653494
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.942864718
Short name T97
Test name
Test status
Simulation time 10802466188 ps
CPU time 137.14 seconds
Started May 07 12:58:16 PM PDT 24
Finished May 07 01:00:35 PM PDT 24
Peak memory 604888 kb
Host smart-eaba5153-c2fd-43c4-b598-797b2676c153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942864718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.942864718
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.1496618669
Short name T1281
Test name
Test status
Simulation time 5164182644 ps
CPU time 50.77 seconds
Started May 07 12:58:12 PM PDT 24
Finished May 07 12:59:04 PM PDT 24
Peak memory 629140 kb
Host smart-f31a1242-a67c-4dd5-bb21-0a719679f754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496618669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1496618669
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.1283306984
Short name T679
Test name
Test status
Simulation time 117314055 ps
CPU time 1.03 seconds
Started May 07 12:58:12 PM PDT 24
Finished May 07 12:58:14 PM PDT 24
Peak memory 203776 kb
Host smart-519a6d0e-68bf-4c18-a06d-d230b495f807
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283306984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.1283306984
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.291950658
Short name T278
Test name
Test status
Simulation time 520344447 ps
CPU time 3.95 seconds
Started May 07 12:58:16 PM PDT 24
Finished May 07 12:58:21 PM PDT 24
Peak memory 226820 kb
Host smart-e1be1b1c-1d1d-4958-b1c5-e74524244585
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291950658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.
291950658
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.4175056851
Short name T969
Test name
Test status
Simulation time 5585304820 ps
CPU time 65.2 seconds
Started May 07 12:58:11 PM PDT 24
Finished May 07 12:59:18 PM PDT 24
Peak memory 883260 kb
Host smart-3c65a3e5-ef17-4044-80c9-332fbd5e2570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175056851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.4175056851
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.3961458203
Short name T1224
Test name
Test status
Simulation time 2016831947 ps
CPU time 8.28 seconds
Started May 07 12:58:18 PM PDT 24
Finished May 07 12:58:28 PM PDT 24
Peak memory 203928 kb
Host smart-35a64750-6a11-4041-8193-f05f97f6775d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961458203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.3961458203
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.3848247794
Short name T1261
Test name
Test status
Simulation time 1777975871 ps
CPU time 29.25 seconds
Started May 07 12:58:27 PM PDT 24
Finished May 07 12:58:58 PM PDT 24
Peak memory 375120 kb
Host smart-d059bf8a-d094-45f5-a27f-1284a12ad2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848247794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.3848247794
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.3646525721
Short name T1175
Test name
Test status
Simulation time 54331508 ps
CPU time 0.67 seconds
Started May 07 12:58:11 PM PDT 24
Finished May 07 12:58:14 PM PDT 24
Peak memory 203568 kb
Host smart-f460b83a-b9ab-4b93-a168-4b3c19ec3f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646525721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3646525721
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.3087421107
Short name T656
Test name
Test status
Simulation time 25442535659 ps
CPU time 1275.5 seconds
Started May 07 12:58:12 PM PDT 24
Finished May 07 01:19:29 PM PDT 24
Peak memory 3689188 kb
Host smart-d07d932d-f903-4069-9706-e4ee82581ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087421107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.3087421107
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2254135489
Short name T285
Test name
Test status
Simulation time 1372462966 ps
CPU time 23.64 seconds
Started May 07 12:58:16 PM PDT 24
Finished May 07 12:58:41 PM PDT 24
Peak memory 321500 kb
Host smart-b876cb74-288f-41f9-b791-2c9fe605f417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254135489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2254135489
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.3146473285
Short name T6
Test name
Test status
Simulation time 3019078070 ps
CPU time 12.86 seconds
Started May 07 12:58:12 PM PDT 24
Finished May 07 12:58:26 PM PDT 24
Peak memory 228500 kb
Host smart-7e7aa1db-d37d-4f55-9327-3c3de4d9429d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146473285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3146473285
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.3956859842
Short name T734
Test name
Test status
Simulation time 1490630494 ps
CPU time 3.91 seconds
Started May 07 12:58:18 PM PDT 24
Finished May 07 12:58:24 PM PDT 24
Peak memory 203880 kb
Host smart-67158e94-9d7a-4f49-a3e2-4c5dff593856
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956859842 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.3956859842
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.1889505913
Short name T901
Test name
Test status
Simulation time 10101511264 ps
CPU time 68.35 seconds
Started May 07 12:58:18 PM PDT 24
Finished May 07 12:59:27 PM PDT 24
Peak memory 486812 kb
Host smart-6f9f5737-747f-4c5b-9cc4-5d1999246f1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889505913 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.1889505913
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.831571403
Short name T26
Test name
Test status
Simulation time 378507610 ps
CPU time 2.69 seconds
Started May 07 12:58:22 PM PDT 24
Finished May 07 12:58:26 PM PDT 24
Peak memory 203880 kb
Host smart-b81131de-5f46-47b7-836a-5a3dcea5c5bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831571403 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.i2c_target_hrst.831571403
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.1917728960
Short name T346
Test name
Test status
Simulation time 11572593384 ps
CPU time 4.67 seconds
Started May 07 12:58:19 PM PDT 24
Finished May 07 12:58:25 PM PDT 24
Peak memory 204320 kb
Host smart-5778fb01-f3fb-4d62-96e4-4f204315e693
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917728960 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.1917728960
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.3659619427
Short name T1183
Test name
Test status
Simulation time 6934122115 ps
CPU time 12.25 seconds
Started May 07 12:58:20 PM PDT 24
Finished May 07 12:58:34 PM PDT 24
Peak memory 538172 kb
Host smart-37fcfdd1-56f4-4bf0-917e-e92b01c3a0a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659619427 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.3659619427
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.3682538552
Short name T987
Test name
Test status
Simulation time 11806861180 ps
CPU time 12.39 seconds
Started May 07 12:58:12 PM PDT 24
Finished May 07 12:58:26 PM PDT 24
Peak memory 203908 kb
Host smart-59280c11-f9f6-4752-99d6-6b24e94000a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682538552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.3682538552
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.592779889
Short name T640
Test name
Test status
Simulation time 2525042913 ps
CPU time 10.5 seconds
Started May 07 12:58:14 PM PDT 24
Finished May 07 12:58:26 PM PDT 24
Peak memory 209080 kb
Host smart-61c991af-a943-4f40-af8e-1a753ed0af00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592779889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_rd.592779889
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.621958091
Short name T586
Test name
Test status
Simulation time 12813564780 ps
CPU time 2.77 seconds
Started May 07 12:58:16 PM PDT 24
Finished May 07 12:58:20 PM PDT 24
Peak memory 203952 kb
Host smart-8cbe7112-f812-4e56-aeb1-fbfe3517fe50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621958091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_wr.621958091
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.4119638988
Short name T1150
Test name
Test status
Simulation time 4237814425 ps
CPU time 43.42 seconds
Started May 07 12:58:20 PM PDT 24
Finished May 07 12:59:05 PM PDT 24
Peak memory 626700 kb
Host smart-aa7b9ed3-42e3-4619-83b4-595fd726a3a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119638988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.4119638988
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.3807919793
Short name T596
Test name
Test status
Simulation time 1775212668 ps
CPU time 8.03 seconds
Started May 07 12:58:18 PM PDT 24
Finished May 07 12:58:27 PM PDT 24
Peak memory 216952 kb
Host smart-beb0822b-65ec-4eca-906a-b84df5c8e0dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807919793 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.3807919793
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.4197239323
Short name T723
Test name
Test status
Simulation time 17168865 ps
CPU time 0.62 seconds
Started May 07 12:58:23 PM PDT 24
Finished May 07 12:58:25 PM PDT 24
Peak memory 203732 kb
Host smart-5e7ca2c9-8b55-43b1-a37a-419ebba8dfbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197239323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.4197239323
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.2672823046
Short name T684
Test name
Test status
Simulation time 274394516 ps
CPU time 1.21 seconds
Started May 07 12:58:18 PM PDT 24
Finished May 07 12:58:20 PM PDT 24
Peak memory 212220 kb
Host smart-3a191e6c-212d-4021-94ec-102021fc4d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672823046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2672823046
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.1766223585
Short name T622
Test name
Test status
Simulation time 1101945838 ps
CPU time 16.65 seconds
Started May 07 12:58:18 PM PDT 24
Finished May 07 12:58:36 PM PDT 24
Peak memory 269584 kb
Host smart-8b293a20-e9d0-4e83-a263-d9ab39e2d17e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766223585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.1766223585
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.1330798309
Short name T739
Test name
Test status
Simulation time 1400319661 ps
CPU time 93.94 seconds
Started May 07 12:58:20 PM PDT 24
Finished May 07 12:59:55 PM PDT 24
Peak memory 537820 kb
Host smart-49d039fa-493d-4eb3-bd1a-74d3dc99f475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330798309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.1330798309
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.3762958339
Short name T1087
Test name
Test status
Simulation time 8761956713 ps
CPU time 66.07 seconds
Started May 07 12:58:17 PM PDT 24
Finished May 07 12:59:25 PM PDT 24
Peak memory 682840 kb
Host smart-0e1ee746-8dac-4d3b-b0f3-e51399fedb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762958339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.3762958339
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.2223586821
Short name T377
Test name
Test status
Simulation time 511730881 ps
CPU time 1.03 seconds
Started May 07 12:58:17 PM PDT 24
Finished May 07 12:58:19 PM PDT 24
Peak memory 203880 kb
Host smart-9cdd4025-ed3e-4c62-8994-3b24cef7e645
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223586821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.2223586821
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3349987613
Short name T330
Test name
Test status
Simulation time 182303768 ps
CPU time 3.67 seconds
Started May 07 12:58:16 PM PDT 24
Finished May 07 12:58:21 PM PDT 24
Peak memory 203876 kb
Host smart-5a2bc935-ac57-467e-b257-da57504b14af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349987613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.3349987613
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.114799182
Short name T983
Test name
Test status
Simulation time 17327081808 ps
CPU time 338.95 seconds
Started May 07 12:58:21 PM PDT 24
Finished May 07 01:04:01 PM PDT 24
Peak memory 1250512 kb
Host smart-4b9e683b-ac2e-4928-aed6-8e37a8058d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114799182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.114799182
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.3530488448
Short name T1296
Test name
Test status
Simulation time 1147652203 ps
CPU time 4.92 seconds
Started May 07 12:58:26 PM PDT 24
Finished May 07 12:58:32 PM PDT 24
Peak memory 203812 kb
Host smart-f8f85ff0-3cf7-4298-9ed9-bc9f10b7a4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530488448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.3530488448
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.1414288334
Short name T82
Test name
Test status
Simulation time 3052769328 ps
CPU time 24.79 seconds
Started May 07 12:58:24 PM PDT 24
Finished May 07 12:58:50 PM PDT 24
Peak memory 345560 kb
Host smart-2bff8742-394b-4505-8f11-44915b9d5c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414288334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.1414288334
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.2544475475
Short name T772
Test name
Test status
Simulation time 43248892 ps
CPU time 0.63 seconds
Started May 07 12:58:27 PM PDT 24
Finished May 07 12:58:29 PM PDT 24
Peak memory 203396 kb
Host smart-22c19acc-8a14-401c-96c1-c33da780a47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544475475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2544475475
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.3238037114
Short name T1193
Test name
Test status
Simulation time 12257439735 ps
CPU time 648 seconds
Started May 07 12:58:17 PM PDT 24
Finished May 07 01:09:06 PM PDT 24
Peak memory 2795784 kb
Host smart-d2303981-7304-4ab2-aada-ee5c63c4dff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238037114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.3238037114
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.956619970
Short name T1131
Test name
Test status
Simulation time 4548110313 ps
CPU time 15 seconds
Started May 07 12:58:24 PM PDT 24
Finished May 07 12:58:40 PM PDT 24
Peak memory 300032 kb
Host smart-2c4736f3-35fe-4df4-9cec-05686903856e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956619970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.956619970
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.1547210162
Short name T1265
Test name
Test status
Simulation time 24606691779 ps
CPU time 552.4 seconds
Started May 07 12:58:23 PM PDT 24
Finished May 07 01:07:36 PM PDT 24
Peak memory 1624644 kb
Host smart-e16428c9-c5d8-4fde-bda0-25a05d611bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547210162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.1547210162
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.1455216657
Short name T507
Test name
Test status
Simulation time 656286164 ps
CPU time 12.32 seconds
Started May 07 12:58:20 PM PDT 24
Finished May 07 12:58:33 PM PDT 24
Peak memory 220328 kb
Host smart-672865d2-bb99-45e8-8eaa-567edd09d050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455216657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.1455216657
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.2924082638
Short name T937
Test name
Test status
Simulation time 15666820095 ps
CPU time 3.95 seconds
Started May 07 12:58:22 PM PDT 24
Finished May 07 12:58:27 PM PDT 24
Peak memory 203916 kb
Host smart-62d2c808-5103-4075-98be-2b8579d0fa12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924082638 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.2924082638
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.4259619230
Short name T1043
Test name
Test status
Simulation time 10062868025 ps
CPU time 35.53 seconds
Started May 07 12:58:24 PM PDT 24
Finished May 07 12:59:01 PM PDT 24
Peak memory 383356 kb
Host smart-20c155bd-4cf1-45b2-b937-f8188d819be0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259619230 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.4259619230
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.1340138206
Short name T1122
Test name
Test status
Simulation time 4082082486 ps
CPU time 2.21 seconds
Started May 07 12:58:24 PM PDT 24
Finished May 07 12:58:28 PM PDT 24
Peak memory 203848 kb
Host smart-ce89e475-a0bc-4486-926a-ac52372eb49a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340138206 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.1340138206
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.2643189481
Short name T617
Test name
Test status
Simulation time 9199431604 ps
CPU time 8.74 seconds
Started May 07 12:58:19 PM PDT 24
Finished May 07 12:58:29 PM PDT 24
Peak memory 218240 kb
Host smart-49723b04-2e44-43e3-afe6-7ce40013222b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643189481 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.2643189481
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.1174721452
Short name T957
Test name
Test status
Simulation time 15128785035 ps
CPU time 150.86 seconds
Started May 07 12:58:19 PM PDT 24
Finished May 07 01:00:52 PM PDT 24
Peak memory 1965408 kb
Host smart-26d4137c-6c43-46e7-a2f5-743362c44173
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174721452 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.1174721452
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.612559302
Short name T112
Test name
Test status
Simulation time 3469975780 ps
CPU time 13.95 seconds
Started May 07 12:58:27 PM PDT 24
Finished May 07 12:58:42 PM PDT 24
Peak memory 203964 kb
Host smart-c5bf9ce4-7b42-46b7-847b-79894708a8a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612559302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_tar
get_smoke.612559302
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.444867983
Short name T738
Test name
Test status
Simulation time 983766969 ps
CPU time 17.78 seconds
Started May 07 12:58:17 PM PDT 24
Finished May 07 12:58:36 PM PDT 24
Peak memory 212244 kb
Host smart-aef86f98-0a06-4e9c-9065-eb28588fc9f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444867983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_rd.444867983
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.2108426889
Short name T810
Test name
Test status
Simulation time 59519359785 ps
CPU time 2069.68 seconds
Started May 07 12:58:19 PM PDT 24
Finished May 07 01:32:51 PM PDT 24
Peak memory 10096556 kb
Host smart-de8b3ed0-7363-4ad4-8517-778cb6db8ca6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108426889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.2108426889
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.3841541120
Short name T1332
Test name
Test status
Simulation time 37895396103 ps
CPU time 965.26 seconds
Started May 07 12:58:19 PM PDT 24
Finished May 07 01:14:26 PM PDT 24
Peak memory 2247580 kb
Host smart-f2627f43-710c-46df-a966-5de1a393192f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841541120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.3841541120
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.4108690381
Short name T236
Test name
Test status
Simulation time 1254543353 ps
CPU time 6.62 seconds
Started May 07 12:58:19 PM PDT 24
Finished May 07 12:58:27 PM PDT 24
Peak memory 212052 kb
Host smart-b096939f-b4ad-4424-9efc-aa69442e3744
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108690381 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.4108690381
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.100521496
Short name T1016
Test name
Test status
Simulation time 28330337 ps
CPU time 0.62 seconds
Started May 07 12:58:28 PM PDT 24
Finished May 07 12:58:30 PM PDT 24
Peak memory 203800 kb
Host smart-a1480aee-7c21-4470-8441-806cd0e6aaeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100521496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.100521496
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.1182668157
Short name T641
Test name
Test status
Simulation time 70591937 ps
CPU time 1.4 seconds
Started May 07 12:58:30 PM PDT 24
Finished May 07 12:58:33 PM PDT 24
Peak memory 212208 kb
Host smart-60052057-46e2-4676-bd03-3dc1364294b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182668157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1182668157
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.1530908032
Short name T292
Test name
Test status
Simulation time 496603660 ps
CPU time 17.28 seconds
Started May 07 12:58:30 PM PDT 24
Finished May 07 12:58:49 PM PDT 24
Peak memory 274864 kb
Host smart-b138bb3d-6815-4178-a246-dbeb2558a49e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530908032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.1530908032
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.3010255544
Short name T607
Test name
Test status
Simulation time 2065256306 ps
CPU time 70.3 seconds
Started May 07 12:58:30 PM PDT 24
Finished May 07 12:59:42 PM PDT 24
Peak memory 632616 kb
Host smart-74242bbd-437e-4fe9-bfa0-2e114b56dd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010255544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.3010255544
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.1057666656
Short name T524
Test name
Test status
Simulation time 1569367879 ps
CPU time 111.41 seconds
Started May 07 12:58:22 PM PDT 24
Finished May 07 01:00:14 PM PDT 24
Peak memory 575344 kb
Host smart-3648f6ee-013f-4cd0-bc21-d6d0b47aa2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057666656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.1057666656
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.257167521
Short name T711
Test name
Test status
Simulation time 106515106 ps
CPU time 1.06 seconds
Started May 07 12:58:23 PM PDT 24
Finished May 07 12:58:25 PM PDT 24
Peak memory 203900 kb
Host smart-ddca7e69-ae2f-4b80-8a5c-e2eaf6170fd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257167521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.257167521
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.2232864535
Short name T672
Test name
Test status
Simulation time 363411799 ps
CPU time 2.45 seconds
Started May 07 12:58:30 PM PDT 24
Finished May 07 12:58:35 PM PDT 24
Peak memory 203912 kb
Host smart-3281d32d-4df7-4170-8ff3-284596b7cb3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232864535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.2232864535
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.1882560521
Short name T189
Test name
Test status
Simulation time 25022148021 ps
CPU time 94.16 seconds
Started May 07 12:58:23 PM PDT 24
Finished May 07 12:59:58 PM PDT 24
Peak memory 1111568 kb
Host smart-c478f9c6-5a4a-4f08-a7be-56da19a3b550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882560521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.1882560521
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.1412180398
Short name T720
Test name
Test status
Simulation time 3000340919 ps
CPU time 9.35 seconds
Started May 07 12:58:31 PM PDT 24
Finished May 07 12:58:42 PM PDT 24
Peak memory 203868 kb
Host smart-ac30ef64-882b-4757-96cb-84ada23ef074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412180398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.1412180398
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.2075174759
Short name T850
Test name
Test status
Simulation time 1760365803 ps
CPU time 25.55 seconds
Started May 07 12:58:35 PM PDT 24
Finished May 07 12:59:01 PM PDT 24
Peak memory 309112 kb
Host smart-b1ee139b-2f87-45e1-8fa0-2a818a170b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075174759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.2075174759
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.1723920321
Short name T405
Test name
Test status
Simulation time 17913647 ps
CPU time 0.68 seconds
Started May 07 12:58:22 PM PDT 24
Finished May 07 12:58:24 PM PDT 24
Peak memory 203784 kb
Host smart-92587fd3-bf7a-404b-9346-292f1c06781f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723920321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1723920321
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.2451900808
Short name T1068
Test name
Test status
Simulation time 10382472037 ps
CPU time 17.57 seconds
Started May 07 12:58:29 PM PDT 24
Finished May 07 12:58:48 PM PDT 24
Peak memory 220000 kb
Host smart-05aa457e-e52e-4dd7-90ab-e5b2e52cb4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451900808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.2451900808
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.1499004070
Short name T1307
Test name
Test status
Simulation time 1419301399 ps
CPU time 25.01 seconds
Started May 07 12:58:22 PM PDT 24
Finished May 07 12:58:48 PM PDT 24
Peak memory 344252 kb
Host smart-8ca0224a-b287-4b20-b09b-a1f75e1ad11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499004070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.1499004070
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.890793970
Short name T246
Test name
Test status
Simulation time 12378272380 ps
CPU time 1530.58 seconds
Started May 07 12:58:28 PM PDT 24
Finished May 07 01:24:00 PM PDT 24
Peak memory 2500232 kb
Host smart-1e191428-aff0-4e80-b48a-6d918760dfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890793970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.890793970
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.2036261135
Short name T308
Test name
Test status
Simulation time 2490461489 ps
CPU time 10.43 seconds
Started May 07 12:58:29 PM PDT 24
Finished May 07 12:58:42 PM PDT 24
Peak memory 217864 kb
Host smart-3f8bcb37-d43d-438d-b961-209a5b4b450c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036261135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.2036261135
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.3565783493
Short name T692
Test name
Test status
Simulation time 930511823 ps
CPU time 5.16 seconds
Started May 07 12:58:29 PM PDT 24
Finished May 07 12:58:37 PM PDT 24
Peak memory 212496 kb
Host smart-949ca54a-4d2a-44d4-897a-c1e1c15b172a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565783493 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.3565783493
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.1292511925
Short name T99
Test name
Test status
Simulation time 10147014415 ps
CPU time 31.78 seconds
Started May 07 12:58:31 PM PDT 24
Finished May 07 12:59:05 PM PDT 24
Peak memory 299340 kb
Host smart-3b0ce4eb-1c0d-4f83-a7f7-2d161650ad25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292511925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.1292511925
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.70691051
Short name T835
Test name
Test status
Simulation time 10245681105 ps
CPU time 15.66 seconds
Started May 07 12:58:30 PM PDT 24
Finished May 07 12:58:48 PM PDT 24
Peak memory 271664 kb
Host smart-918f01ed-02ca-4bc3-9182-b9ace8056e78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70691051 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_fifo_reset_tx.70691051
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.4030416521
Short name T409
Test name
Test status
Simulation time 1617602652 ps
CPU time 2.11 seconds
Started May 07 12:58:29 PM PDT 24
Finished May 07 12:58:34 PM PDT 24
Peak memory 203944 kb
Host smart-33db79a8-fc36-4d1c-b222-3970c1dee0a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030416521 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.4030416521
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.2923771024
Short name T782
Test name
Test status
Simulation time 1307398614 ps
CPU time 3.63 seconds
Started May 07 12:58:30 PM PDT 24
Finished May 07 12:58:36 PM PDT 24
Peak memory 203888 kb
Host smart-454957f8-835e-43e1-95a5-0b1f9392343c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923771024 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.2923771024
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.3665007638
Short name T354
Test name
Test status
Simulation time 24148406262 ps
CPU time 177.36 seconds
Started May 07 12:58:28 PM PDT 24
Finished May 07 01:01:27 PM PDT 24
Peak memory 2813292 kb
Host smart-36ab1acf-b8a8-43af-b2c2-ef48809ba048
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665007638 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.3665007638
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.26895703
Short name T1285
Test name
Test status
Simulation time 1084842428 ps
CPU time 6.74 seconds
Started May 07 12:58:31 PM PDT 24
Finished May 07 12:58:39 PM PDT 24
Peak memory 203904 kb
Host smart-249ff6ad-3271-4b78-a017-f230e0d69753
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26895703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_targ
et_smoke.26895703
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.3158309153
Short name T1233
Test name
Test status
Simulation time 1351131064 ps
CPU time 21.61 seconds
Started May 07 12:58:30 PM PDT 24
Finished May 07 12:58:53 PM PDT 24
Peak memory 223412 kb
Host smart-5c0d3cf7-d95a-40f0-837c-e988df89fdef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158309153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.3158309153
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.3975154477
Short name T771
Test name
Test status
Simulation time 58517612988 ps
CPU time 234.94 seconds
Started May 07 12:58:30 PM PDT 24
Finished May 07 01:02:27 PM PDT 24
Peak memory 2701552 kb
Host smart-9972822d-ac73-47d7-be83-93ee0c69d40a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975154477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.3975154477
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.1766170470
Short name T600
Test name
Test status
Simulation time 27204430327 ps
CPU time 163.17 seconds
Started May 07 12:58:33 PM PDT 24
Finished May 07 01:01:18 PM PDT 24
Peak memory 1527844 kb
Host smart-203e041e-5c21-41ff-be67-66ecb91250f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766170470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.1766170470
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.2232878874
Short name T109
Test name
Test status
Simulation time 5629710851 ps
CPU time 8.5 seconds
Started May 07 12:58:30 PM PDT 24
Finished May 07 12:58:41 PM PDT 24
Peak memory 212140 kb
Host smart-fba9aceb-3391-4de2-8056-6005de276998
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232878874 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.2232878874
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.2546770088
Short name T1172
Test name
Test status
Simulation time 15521859 ps
CPU time 0.6 seconds
Started May 07 12:58:42 PM PDT 24
Finished May 07 12:58:43 PM PDT 24
Peak memory 203808 kb
Host smart-6a38e84c-ee01-4fd1-be1b-a44cbb22666f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546770088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2546770088
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.2497248435
Short name T660
Test name
Test status
Simulation time 484242915 ps
CPU time 1.35 seconds
Started May 07 12:58:36 PM PDT 24
Finished May 07 12:58:38 PM PDT 24
Peak memory 212204 kb
Host smart-aff6d104-346d-4f3f-80f6-d2852cd7dd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497248435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.2497248435
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.3028132378
Short name T1204
Test name
Test status
Simulation time 187629854 ps
CPU time 9.45 seconds
Started May 07 12:58:36 PM PDT 24
Finished May 07 12:58:46 PM PDT 24
Peak memory 236688 kb
Host smart-876a39f2-247a-4b49-801f-fe33c35e3fd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028132378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.3028132378
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.1206583380
Short name T414
Test name
Test status
Simulation time 2308965344 ps
CPU time 78.09 seconds
Started May 07 12:58:36 PM PDT 24
Finished May 07 12:59:55 PM PDT 24
Peak memory 682336 kb
Host smart-4cf12ace-65bc-4307-9df6-1530d9e2d2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206583380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.1206583380
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.3157150413
Short name T1199
Test name
Test status
Simulation time 15440488689 ps
CPU time 67.68 seconds
Started May 07 12:58:35 PM PDT 24
Finished May 07 12:59:43 PM PDT 24
Peak memory 413444 kb
Host smart-3887d1f8-5d87-48c9-92fe-f6bf49c1bfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157150413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.3157150413
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.2616795616
Short name T523
Test name
Test status
Simulation time 91741577 ps
CPU time 1.04 seconds
Started May 07 12:58:36 PM PDT 24
Finished May 07 12:58:38 PM PDT 24
Peak memory 203852 kb
Host smart-2fe39b87-431d-4c94-83b7-0113f7ce07c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616795616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.2616795616
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.2132727371
Short name T401
Test name
Test status
Simulation time 122111791 ps
CPU time 3.32 seconds
Started May 07 12:58:38 PM PDT 24
Finished May 07 12:58:42 PM PDT 24
Peak memory 220968 kb
Host smart-889087ae-4515-4e0c-9429-7e6f763ddea9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132727371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.2132727371
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.67032276
Short name T553
Test name
Test status
Simulation time 12192918130 ps
CPU time 80.07 seconds
Started May 07 12:58:34 PM PDT 24
Finished May 07 12:59:55 PM PDT 24
Peak memory 882664 kb
Host smart-5561786d-2b93-458f-bcf9-39fdff5f8094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67032276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.67032276
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.4172986158
Short name T392
Test name
Test status
Simulation time 704499295 ps
CPU time 7.32 seconds
Started May 07 12:58:43 PM PDT 24
Finished May 07 12:58:52 PM PDT 24
Peak memory 203892 kb
Host smart-8cede064-83db-45e0-9657-9cfe322e6ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172986158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.4172986158
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.2995367134
Short name T807
Test name
Test status
Simulation time 2832313041 ps
CPU time 67.61 seconds
Started May 07 12:58:45 PM PDT 24
Finished May 07 12:59:53 PM PDT 24
Peak memory 317004 kb
Host smart-9fc58036-ccde-47d5-b2f3-d0d6201d3aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995367134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.2995367134
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.354532070
Short name T204
Test name
Test status
Simulation time 137126366 ps
CPU time 0.68 seconds
Started May 07 12:58:36 PM PDT 24
Finished May 07 12:58:38 PM PDT 24
Peak memory 203712 kb
Host smart-e4878bd7-9961-473c-860d-4e1e9a7c4edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354532070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.354532070
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.1671001225
Short name T311
Test name
Test status
Simulation time 7025213863 ps
CPU time 104.2 seconds
Started May 07 12:58:35 PM PDT 24
Finished May 07 01:00:20 PM PDT 24
Peak memory 203924 kb
Host smart-94f63935-c1ac-477e-9a73-f5778a057dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671001225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.1671001225
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.1579659229
Short name T1032
Test name
Test status
Simulation time 1649224467 ps
CPU time 30.55 seconds
Started May 07 12:58:31 PM PDT 24
Finished May 07 12:59:03 PM PDT 24
Peak memory 293764 kb
Host smart-33afbe20-00d9-4cc9-bd5d-36313324c1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579659229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.1579659229
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.1620776788
Short name T1169
Test name
Test status
Simulation time 648182047 ps
CPU time 12.86 seconds
Started May 07 12:58:35 PM PDT 24
Finished May 07 12:58:49 PM PDT 24
Peak memory 216564 kb
Host smart-92f2498f-fd38-4261-9852-ffcd7b0e23c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620776788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1620776788
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.449932767
Short name T32
Test name
Test status
Simulation time 4918508948 ps
CPU time 5.13 seconds
Started May 07 12:58:41 PM PDT 24
Finished May 07 12:58:47 PM PDT 24
Peak memory 205300 kb
Host smart-1a73ac19-81ee-474b-b960-185d463e6ebe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449932767 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.449932767
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.1716580179
Short name T448
Test name
Test status
Simulation time 10084790320 ps
CPU time 71.94 seconds
Started May 07 12:58:43 PM PDT 24
Finished May 07 12:59:56 PM PDT 24
Peak memory 440852 kb
Host smart-35f8bdc6-98e7-44b3-8c1e-03ba4ca84e49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716580179 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.1716580179
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.2175807429
Short name T1319
Test name
Test status
Simulation time 10267603066 ps
CPU time 14.02 seconds
Started May 07 12:58:43 PM PDT 24
Finished May 07 12:58:58 PM PDT 24
Peak memory 260496 kb
Host smart-aaf5ccb4-041f-40b7-b625-593c8dc5d57a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175807429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.2175807429
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.1086839585
Short name T1022
Test name
Test status
Simulation time 413282999 ps
CPU time 2.64 seconds
Started May 07 12:58:53 PM PDT 24
Finished May 07 12:58:56 PM PDT 24
Peak memory 203924 kb
Host smart-817b19c1-3fcf-451f-a9ff-512f0cfc9d16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086839585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.1086839585
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.3524002843
Short name T648
Test name
Test status
Simulation time 5448635335 ps
CPU time 5.49 seconds
Started May 07 12:58:42 PM PDT 24
Finished May 07 12:58:49 PM PDT 24
Peak memory 212192 kb
Host smart-17b70551-28d9-4673-9467-aea3303b9359
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524002843 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.3524002843
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.2543435321
Short name T1260
Test name
Test status
Simulation time 16284029548 ps
CPU time 29.51 seconds
Started May 07 12:58:42 PM PDT 24
Finished May 07 12:59:13 PM PDT 24
Peak memory 578056 kb
Host smart-58e596a1-0c1c-4958-b20b-3fa44aaa6dd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543435321 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.2543435321
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.3487476063
Short name T1153
Test name
Test status
Simulation time 2229082715 ps
CPU time 18.06 seconds
Started May 07 12:58:38 PM PDT 24
Finished May 07 12:58:57 PM PDT 24
Peak memory 203980 kb
Host smart-9b9ff267-56f1-4b35-b874-f0b9a802b81b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487476063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.3487476063
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.2391764999
Short name T1344
Test name
Test status
Simulation time 14931325628 ps
CPU time 27.64 seconds
Started May 07 12:58:53 PM PDT 24
Finished May 07 12:59:21 PM PDT 24
Peak memory 233076 kb
Host smart-a6c09c68-a1cc-49a7-99ff-44c3221100cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391764999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.2391764999
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.715959501
Short name T649
Test name
Test status
Simulation time 25712040135 ps
CPU time 109.25 seconds
Started May 07 12:58:53 PM PDT 24
Finished May 07 01:00:43 PM PDT 24
Peak memory 1590528 kb
Host smart-afe3e18c-ac18-4d41-a3e0-86a7a418c33f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715959501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_wr.715959501
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.876781465
Short name T1200
Test name
Test status
Simulation time 39361067941 ps
CPU time 2783 seconds
Started May 07 12:58:43 PM PDT 24
Finished May 07 01:45:07 PM PDT 24
Peak memory 4454664 kb
Host smart-ac0366f5-4eaa-4bb4-b16d-a6cd31f92e0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876781465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_t
arget_stretch.876781465
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.766938700
Short name T657
Test name
Test status
Simulation time 2569708739 ps
CPU time 6.77 seconds
Started May 07 12:58:42 PM PDT 24
Finished May 07 12:58:50 PM PDT 24
Peak memory 217064 kb
Host smart-c2fb3868-7bdb-4634-98b2-baf3a6022c36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766938700 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_timeout.766938700
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.3900463408
Short name T1005
Test name
Test status
Simulation time 39554283 ps
CPU time 0.65 seconds
Started May 07 12:58:47 PM PDT 24
Finished May 07 12:58:49 PM PDT 24
Peak memory 203784 kb
Host smart-bcf83d4f-bbe5-4988-9deb-6884feb1b5cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900463408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.3900463408
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.1549211335
Short name T333
Test name
Test status
Simulation time 59131533 ps
CPU time 1.09 seconds
Started May 07 12:58:50 PM PDT 24
Finished May 07 12:58:52 PM PDT 24
Peak memory 204068 kb
Host smart-c560678e-bc6d-4d71-9038-c47c4254da10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549211335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.1549211335
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.2937841669
Short name T332
Test name
Test status
Simulation time 5913688801 ps
CPU time 7.06 seconds
Started May 07 12:58:49 PM PDT 24
Finished May 07 12:58:57 PM PDT 24
Peak memory 282164 kb
Host smart-6304270f-e695-4b19-b507-bbe8b8e75123
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937841669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.2937841669
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.2440420854
Short name T767
Test name
Test status
Simulation time 10533232586 ps
CPU time 95.13 seconds
Started May 07 12:58:51 PM PDT 24
Finished May 07 01:00:27 PM PDT 24
Peak memory 833684 kb
Host smart-b829afde-207c-4318-a30f-eb28f59f1616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440420854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.2440420854
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.853424531
Short name T1236
Test name
Test status
Simulation time 1708198866 ps
CPU time 121.2 seconds
Started May 07 12:58:49 PM PDT 24
Finished May 07 01:00:51 PM PDT 24
Peak memory 598672 kb
Host smart-ea1dba1b-108a-436f-ae6f-1ecd462b66a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853424531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.853424531
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.2080785605
Short name T638
Test name
Test status
Simulation time 211892159 ps
CPU time 6.14 seconds
Started May 07 12:58:49 PM PDT 24
Finished May 07 12:58:56 PM PDT 24
Peak memory 246100 kb
Host smart-d522ffed-cbfb-4300-b253-5b9363c620cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080785605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.2080785605
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.2117463855
Short name T761
Test name
Test status
Simulation time 4062392969 ps
CPU time 119.02 seconds
Started May 07 12:58:54 PM PDT 24
Finished May 07 01:00:55 PM PDT 24
Peak memory 1204524 kb
Host smart-69557ceb-de9b-400a-8c7e-f7979a90297e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117463855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.2117463855
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.114400494
Short name T1258
Test name
Test status
Simulation time 7516794678 ps
CPU time 26.5 seconds
Started May 07 12:58:54 PM PDT 24
Finished May 07 12:59:22 PM PDT 24
Peak memory 350112 kb
Host smart-0f2c9400-8edc-422e-bc76-9d05bfd9e90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114400494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.114400494
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.1348285776
Short name T54
Test name
Test status
Simulation time 64120491 ps
CPU time 0.69 seconds
Started May 07 12:58:43 PM PDT 24
Finished May 07 12:58:45 PM PDT 24
Peak memory 203704 kb
Host smart-e4e181ed-e0fb-4846-b508-6d82b31fabdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348285776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.1348285776
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.722244204
Short name T1250
Test name
Test status
Simulation time 13080685488 ps
CPU time 92.75 seconds
Started May 07 12:58:50 PM PDT 24
Finished May 07 01:00:24 PM PDT 24
Peak memory 269600 kb
Host smart-300babc7-25bd-4a00-915f-aa2dd8f7b040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722244204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.722244204
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.2297919997
Short name T1255
Test name
Test status
Simulation time 3073653375 ps
CPU time 31.02 seconds
Started May 07 12:58:53 PM PDT 24
Finished May 07 12:59:25 PM PDT 24
Peak memory 348208 kb
Host smart-f1d5527d-e6cd-4048-97a0-72984f87afca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297919997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.2297919997
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.110909427
Short name T1271
Test name
Test status
Simulation time 69861135857 ps
CPU time 1292.89 seconds
Started May 07 12:58:50 PM PDT 24
Finished May 07 01:20:24 PM PDT 24
Peak memory 2112036 kb
Host smart-68ac012e-0e6c-4186-b864-f55e352ee3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110909427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.110909427
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.2617884316
Short name T1351
Test name
Test status
Simulation time 1128225588 ps
CPU time 24.85 seconds
Started May 07 12:58:54 PM PDT 24
Finished May 07 12:59:20 PM PDT 24
Peak memory 212104 kb
Host smart-e58f039e-7c1f-486d-afe9-0f76d664d9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617884316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.2617884316
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.2899517607
Short name T953
Test name
Test status
Simulation time 868162923 ps
CPU time 3.97 seconds
Started May 07 12:58:49 PM PDT 24
Finished May 07 12:58:54 PM PDT 24
Peak memory 212036 kb
Host smart-edb4f368-e8b2-4486-8cac-5864cdff813c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899517607 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.2899517607
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.1121155176
Short name T212
Test name
Test status
Simulation time 10949467847 ps
CPU time 4.41 seconds
Started May 07 12:58:49 PM PDT 24
Finished May 07 12:58:54 PM PDT 24
Peak memory 220528 kb
Host smart-bc6675f9-d612-4ea1-b105-3f836792f97f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121155176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.1121155176
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.3318531209
Short name T960
Test name
Test status
Simulation time 10216378710 ps
CPU time 14.82 seconds
Started May 07 12:58:48 PM PDT 24
Finished May 07 12:59:04 PM PDT 24
Peak memory 297076 kb
Host smart-8e414c13-7b82-4ebe-b122-6a2ae0978bbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318531209 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.3318531209
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.2059723529
Short name T1290
Test name
Test status
Simulation time 5829967191 ps
CPU time 3.12 seconds
Started May 07 12:58:50 PM PDT 24
Finished May 07 12:58:54 PM PDT 24
Peak memory 203980 kb
Host smart-f0348c5b-2648-4b39-b3c0-5c2c4aa8d41a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059723529 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.2059723529
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.2702945641
Short name T1147
Test name
Test status
Simulation time 1030067968 ps
CPU time 5.32 seconds
Started May 07 12:58:49 PM PDT 24
Finished May 07 12:58:56 PM PDT 24
Peak memory 206412 kb
Host smart-890add66-7352-4499-86d0-e2c1f0797110
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702945641 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.2702945641
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.1696909212
Short name T1092
Test name
Test status
Simulation time 17052532557 ps
CPU time 141.29 seconds
Started May 07 12:58:54 PM PDT 24
Finished May 07 01:01:17 PM PDT 24
Peak memory 1979556 kb
Host smart-cda3144d-9651-41eb-8925-fa670e382ce7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696909212 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.1696909212
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.4232979788
Short name T618
Test name
Test status
Simulation time 1262388704 ps
CPU time 16 seconds
Started May 07 12:58:47 PM PDT 24
Finished May 07 12:59:04 PM PDT 24
Peak memory 203776 kb
Host smart-254a2883-7534-4300-ae46-2a5beafd93b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232979788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.4232979788
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.381004579
Short name T813
Test name
Test status
Simulation time 3607147149 ps
CPU time 16.08 seconds
Started May 07 12:58:51 PM PDT 24
Finished May 07 12:59:08 PM PDT 24
Peak memory 218532 kb
Host smart-79dafbaa-f36e-484f-b799-a61a41fbf836
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381004579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.381004579
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.3732399557
Short name T433
Test name
Test status
Simulation time 41662625725 ps
CPU time 26.53 seconds
Started May 07 12:58:49 PM PDT 24
Finished May 07 12:59:17 PM PDT 24
Peak memory 610552 kb
Host smart-f0f557a8-973a-4814-8a17-a60d9b1746dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732399557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.3732399557
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.3218187925
Short name T337
Test name
Test status
Simulation time 14329770215 ps
CPU time 529.99 seconds
Started May 07 12:58:51 PM PDT 24
Finished May 07 01:07:42 PM PDT 24
Peak memory 3087232 kb
Host smart-62c67652-f144-47a4-a35c-796d560644a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218187925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.3218187925
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.2749063631
Short name T325
Test name
Test status
Simulation time 1172974492 ps
CPU time 6.1 seconds
Started May 07 12:58:50 PM PDT 24
Finished May 07 12:58:57 PM PDT 24
Peak memory 212084 kb
Host smart-e30cb747-bf6e-41d3-88ec-58e877001ef8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749063631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.2749063631
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.1045985400
Short name T1166
Test name
Test status
Simulation time 17918176 ps
CPU time 0.62 seconds
Started May 07 12:59:05 PM PDT 24
Finished May 07 12:59:07 PM PDT 24
Peak memory 203796 kb
Host smart-2e89d894-7724-48e4-9aa7-32d8213edcf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045985400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1045985400
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.2280002414
Short name T1314
Test name
Test status
Simulation time 80413449 ps
CPU time 1.46 seconds
Started May 07 12:58:57 PM PDT 24
Finished May 07 12:59:00 PM PDT 24
Peak memory 212188 kb
Host smart-2d4fbef3-ef9f-47d1-baf4-168f9fdc1208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280002414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.2280002414
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.518089271
Short name T1077
Test name
Test status
Simulation time 230568044 ps
CPU time 11.21 seconds
Started May 07 12:58:56 PM PDT 24
Finished May 07 12:59:08 PM PDT 24
Peak memory 239152 kb
Host smart-585a4fa6-b69f-41e6-bd7e-7fe1f0138eb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518089271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empt
y.518089271
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.1629329949
Short name T612
Test name
Test status
Simulation time 3088899600 ps
CPU time 95.04 seconds
Started May 07 12:58:56 PM PDT 24
Finished May 07 01:00:32 PM PDT 24
Peak memory 472572 kb
Host smart-78cb8b12-dcf7-4e4c-9c2a-9fde99308458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629329949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1629329949
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.1825848184
Short name T765
Test name
Test status
Simulation time 4259501446 ps
CPU time 77.15 seconds
Started May 07 12:58:56 PM PDT 24
Finished May 07 01:00:14 PM PDT 24
Peak memory 693420 kb
Host smart-16820a85-e57f-49e3-bc51-26c3401e0ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825848184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.1825848184
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2641355712
Short name T1243
Test name
Test status
Simulation time 236164291 ps
CPU time 2.89 seconds
Started May 07 12:58:56 PM PDT 24
Finished May 07 12:59:00 PM PDT 24
Peak memory 203852 kb
Host smart-a58b22b7-246f-4b4a-a490-9277788b13e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641355712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.2641355712
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.4103132498
Short name T1212
Test name
Test status
Simulation time 3849790032 ps
CPU time 271.78 seconds
Started May 07 12:58:56 PM PDT 24
Finished May 07 01:03:29 PM PDT 24
Peak memory 1123496 kb
Host smart-ce0d86fc-68d6-4fda-b42f-d4a111577680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103132498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.4103132498
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.3477704298
Short name T276
Test name
Test status
Simulation time 349002760 ps
CPU time 5.53 seconds
Started May 07 12:59:02 PM PDT 24
Finished May 07 12:59:08 PM PDT 24
Peak memory 203948 kb
Host smart-f4036d3b-a864-451e-b295-7e1a703c1f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477704298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.3477704298
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.891695175
Short name T689
Test name
Test status
Simulation time 4493538628 ps
CPU time 71.5 seconds
Started May 07 12:59:04 PM PDT 24
Finished May 07 01:00:17 PM PDT 24
Peak memory 326916 kb
Host smart-438dfbd9-d977-4f35-a237-bc76b5d94f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891695175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.891695175
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.1176150049
Short name T599
Test name
Test status
Simulation time 110847836 ps
CPU time 0.67 seconds
Started May 07 12:58:54 PM PDT 24
Finished May 07 12:58:55 PM PDT 24
Peak memory 203728 kb
Host smart-9a047e91-ae12-4066-b8e8-5e0712684451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176150049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.1176150049
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.2208775679
Short name T1273
Test name
Test status
Simulation time 535498635 ps
CPU time 2.36 seconds
Started May 07 12:58:55 PM PDT 24
Finished May 07 12:58:58 PM PDT 24
Peak memory 203976 kb
Host smart-b2a9008b-1b54-4b36-bba4-f86028683015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208775679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.2208775679
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.765131959
Short name T1315
Test name
Test status
Simulation time 7520734159 ps
CPU time 20.53 seconds
Started May 07 12:58:56 PM PDT 24
Finished May 07 12:59:18 PM PDT 24
Peak memory 310628 kb
Host smart-eb473f8b-0d6d-4d5c-b7a7-a7069f57a959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765131959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.765131959
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.3350459855
Short name T888
Test name
Test status
Simulation time 11498384697 ps
CPU time 727.27 seconds
Started May 07 12:58:55 PM PDT 24
Finished May 07 01:11:04 PM PDT 24
Peak memory 2474408 kb
Host smart-25b9d122-1f15-4a07-b06c-b9d664786ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350459855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.3350459855
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.2055547362
Short name T933
Test name
Test status
Simulation time 9419567555 ps
CPU time 26.35 seconds
Started May 07 12:58:55 PM PDT 24
Finished May 07 12:59:22 PM PDT 24
Peak memory 212180 kb
Host smart-e6778874-efad-4886-8306-32478355960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055547362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2055547362
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.1885384181
Short name T1176
Test name
Test status
Simulation time 885517588 ps
CPU time 4.62 seconds
Started May 07 12:58:57 PM PDT 24
Finished May 07 12:59:03 PM PDT 24
Peak memory 212128 kb
Host smart-29d9ac7f-1f10-4ac3-8a0c-d16a6209cd5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885384181 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.1885384181
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.4206017433
Short name T69
Test name
Test status
Simulation time 10088876355 ps
CPU time 75.82 seconds
Started May 07 12:58:57 PM PDT 24
Finished May 07 01:00:14 PM PDT 24
Peak memory 518408 kb
Host smart-b914c7b8-d9de-4244-bc11-7546f20cd0ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206017433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.4206017433
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.3298061736
Short name T1062
Test name
Test status
Simulation time 10082149978 ps
CPU time 98.23 seconds
Started May 07 12:58:56 PM PDT 24
Finished May 07 01:00:36 PM PDT 24
Peak memory 541912 kb
Host smart-51bfb5fe-839d-47a7-8a36-dd66d2931d10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298061736 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.3298061736
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.2879355943
Short name T942
Test name
Test status
Simulation time 407988406 ps
CPU time 2.73 seconds
Started May 07 12:58:55 PM PDT 24
Finished May 07 12:58:58 PM PDT 24
Peak memory 203904 kb
Host smart-97f19763-0410-41d7-a8ce-53d0dc2e675d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879355943 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.2879355943
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.350992068
Short name T1352
Test name
Test status
Simulation time 1617232656 ps
CPU time 6.87 seconds
Started May 07 12:58:56 PM PDT 24
Finished May 07 12:59:04 PM PDT 24
Peak memory 212120 kb
Host smart-48c41b74-0524-4dc5-a1f0-cd628c242e1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350992068 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.350992068
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.1417452627
Short name T1257
Test name
Test status
Simulation time 3805112471 ps
CPU time 3.09 seconds
Started May 07 12:58:56 PM PDT 24
Finished May 07 12:59:01 PM PDT 24
Peak memory 203896 kb
Host smart-a6a63c4a-6222-4dd2-a9bb-15f52cc32c25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417452627 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.1417452627
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.747248777
Short name T557
Test name
Test status
Simulation time 1286871244 ps
CPU time 23.61 seconds
Started May 07 12:58:56 PM PDT 24
Finished May 07 12:59:21 PM PDT 24
Peak memory 203888 kb
Host smart-1ec14f98-b234-4788-895a-46086c60d728
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747248777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_tar
get_smoke.747248777
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.728105210
Short name T854
Test name
Test status
Simulation time 381643590 ps
CPU time 16.15 seconds
Started May 07 12:58:55 PM PDT 24
Finished May 07 12:59:12 PM PDT 24
Peak memory 203872 kb
Host smart-570be0cc-ea1f-4013-95e2-7409ac2224e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728105210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_rd.728105210
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.708142371
Short name T18
Test name
Test status
Simulation time 31035243123 ps
CPU time 8.34 seconds
Started May 07 12:58:55 PM PDT 24
Finished May 07 12:59:04 PM PDT 24
Peak memory 230204 kb
Host smart-6c295df6-8d22-44ba-80db-0fbd0c363046
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708142371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_wr.708142371
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.4217434013
Short name T1125
Test name
Test status
Simulation time 34122894622 ps
CPU time 372.38 seconds
Started May 07 12:58:54 PM PDT 24
Finished May 07 01:05:08 PM PDT 24
Peak memory 1185384 kb
Host smart-afabbdde-cf3e-464d-b3c8-fa5827e6eb43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217434013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.4217434013
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.3946795038
Short name T1027
Test name
Test status
Simulation time 1183059056 ps
CPU time 6.36 seconds
Started May 07 12:58:56 PM PDT 24
Finished May 07 12:59:04 PM PDT 24
Peak memory 212124 kb
Host smart-30e90737-7a56-4f8f-999c-0b4b5d452b96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946795038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.3946795038
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.2602298570
Short name T390
Test name
Test status
Simulation time 16447821 ps
CPU time 0.62 seconds
Started May 07 12:59:07 PM PDT 24
Finished May 07 12:59:09 PM PDT 24
Peak memory 203768 kb
Host smart-6f4f7d43-df44-4e91-a8d2-8abd52946be9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602298570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.2602298570
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.3314747173
Short name T1051
Test name
Test status
Simulation time 108132482 ps
CPU time 1.84 seconds
Started May 07 12:59:08 PM PDT 24
Finished May 07 12:59:11 PM PDT 24
Peak memory 220416 kb
Host smart-af222c1d-47e8-42af-977c-1f550e187f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314747173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.3314747173
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.1678662668
Short name T497
Test name
Test status
Simulation time 563814752 ps
CPU time 5.45 seconds
Started May 07 12:59:02 PM PDT 24
Finished May 07 12:59:09 PM PDT 24
Peak memory 257856 kb
Host smart-d689b7a3-648d-47aa-baa6-03ea71f654fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678662668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.1678662668
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.519077728
Short name T75
Test name
Test status
Simulation time 3033057496 ps
CPU time 35.57 seconds
Started May 07 12:59:08 PM PDT 24
Finished May 07 12:59:45 PM PDT 24
Peak memory 418992 kb
Host smart-52999dcc-deaa-469d-b56d-daa0a3a8a621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519077728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.519077728
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.2787380398
Short name T468
Test name
Test status
Simulation time 1377833410 ps
CPU time 90.09 seconds
Started May 07 12:59:00 PM PDT 24
Finished May 07 01:00:32 PM PDT 24
Peak memory 522776 kb
Host smart-92079675-2b0e-4c92-8b49-8edf53edfc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787380398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.2787380398
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.2591375664
Short name T486
Test name
Test status
Simulation time 612030411 ps
CPU time 1.2 seconds
Started May 07 12:59:01 PM PDT 24
Finished May 07 12:59:03 PM PDT 24
Peak memory 203888 kb
Host smart-2d9b77a2-6140-4280-b76a-d1a1090f2b7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591375664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.2591375664
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1587668950
Short name T283
Test name
Test status
Simulation time 220410004 ps
CPU time 4.37 seconds
Started May 07 12:59:00 PM PDT 24
Finished May 07 12:59:06 PM PDT 24
Peak memory 203880 kb
Host smart-63842dce-6bfd-4c9d-b9d2-b962b6451122
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587668950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.1587668950
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.766147066
Short name T183
Test name
Test status
Simulation time 53008386982 ps
CPU time 77.91 seconds
Started May 07 12:59:02 PM PDT 24
Finished May 07 01:00:21 PM PDT 24
Peak memory 997504 kb
Host smart-73acde9f-6b11-4168-a9e8-d0d3d2899597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766147066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.766147066
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.4156443097
Short name T345
Test name
Test status
Simulation time 1048087982 ps
CPU time 6.13 seconds
Started May 07 12:59:09 PM PDT 24
Finished May 07 12:59:17 PM PDT 24
Peak memory 203920 kb
Host smart-f0c671f7-c67a-40a7-bfea-9fd2d28761fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156443097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.4156443097
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.2132620120
Short name T811
Test name
Test status
Simulation time 3275257994 ps
CPU time 40.68 seconds
Started May 07 12:59:08 PM PDT 24
Finished May 07 12:59:50 PM PDT 24
Peak memory 309976 kb
Host smart-e2fc0d7d-1ee2-4657-a10d-e09d2fe4f7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132620120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.2132620120
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.2792657028
Short name T979
Test name
Test status
Simulation time 26771244 ps
CPU time 0.72 seconds
Started May 07 12:59:00 PM PDT 24
Finished May 07 12:59:02 PM PDT 24
Peak memory 203732 kb
Host smart-94dbf546-10f3-459d-ae42-5a59792e394b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792657028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2792657028
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.280423453
Short name T1070
Test name
Test status
Simulation time 52221790733 ps
CPU time 178.8 seconds
Started May 07 12:59:06 PM PDT 24
Finished May 07 01:02:06 PM PDT 24
Peak memory 1203040 kb
Host smart-219d21fe-3d1f-4bc1-8d00-0f0e36b88a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280423453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.280423453
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.246361442
Short name T717
Test name
Test status
Simulation time 10007320219 ps
CPU time 17.06 seconds
Started May 07 12:59:01 PM PDT 24
Finished May 07 12:59:19 PM PDT 24
Peak memory 248416 kb
Host smart-9da319db-32af-4ac3-b291-0af1ecc50c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246361442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.246361442
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.534779579
Short name T249
Test name
Test status
Simulation time 16596847901 ps
CPU time 617.39 seconds
Started May 07 12:59:06 PM PDT 24
Finished May 07 01:09:25 PM PDT 24
Peak memory 1287124 kb
Host smart-31a73b53-fc0b-401e-9b20-02b33b2143f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534779579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.534779579
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.1046787121
Short name T970
Test name
Test status
Simulation time 536538092 ps
CPU time 9.85 seconds
Started May 07 12:59:03 PM PDT 24
Finished May 07 12:59:14 PM PDT 24
Peak memory 213948 kb
Host smart-8ed60aa8-f4cf-41d8-826b-a4fc4c4c36b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046787121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.1046787121
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.252360032
Short name T1309
Test name
Test status
Simulation time 1787340163 ps
CPU time 4.25 seconds
Started May 07 12:59:08 PM PDT 24
Finished May 07 12:59:14 PM PDT 24
Peak memory 212100 kb
Host smart-d3b2f3c5-e575-4673-82d9-c6126bc8f0af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252360032 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.252360032
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.1285801792
Short name T115
Test name
Test status
Simulation time 10168008113 ps
CPU time 5.03 seconds
Started May 07 12:59:01 PM PDT 24
Finished May 07 12:59:07 PM PDT 24
Peak memory 227160 kb
Host smart-0f89613c-131e-4020-89d4-6f7f8dde17a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285801792 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.1285801792
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.3125025821
Short name T891
Test name
Test status
Simulation time 10063259334 ps
CPU time 81.55 seconds
Started May 07 12:59:01 PM PDT 24
Finished May 07 01:00:24 PM PDT 24
Peak memory 550224 kb
Host smart-b394f703-b11f-4e6e-8277-c89dae18c071
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125025821 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.3125025821
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.4063397107
Short name T15
Test name
Test status
Simulation time 3143251025 ps
CPU time 3.08 seconds
Started May 07 12:59:02 PM PDT 24
Finished May 07 12:59:07 PM PDT 24
Peak memory 204016 kb
Host smart-5900a943-b97b-4d45-b5b0-4208f6055848
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063397107 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.4063397107
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.543200936
Short name T778
Test name
Test status
Simulation time 1741999248 ps
CPU time 4.16 seconds
Started May 07 12:59:01 PM PDT 24
Finished May 07 12:59:06 PM PDT 24
Peak memory 203884 kb
Host smart-553add71-872e-4855-9ec5-45cf2668e0fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543200936 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_intr_smoke.543200936
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.897894678
Short name T1349
Test name
Test status
Simulation time 10182975122 ps
CPU time 8.25 seconds
Started May 07 12:59:06 PM PDT 24
Finished May 07 12:59:15 PM PDT 24
Peak memory 245276 kb
Host smart-185a6aa0-48e3-4d43-b52b-acb7a9ad97b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897894678 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.897894678
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.2995440323
Short name T496
Test name
Test status
Simulation time 694825762 ps
CPU time 8.49 seconds
Started May 07 12:58:59 PM PDT 24
Finished May 07 12:59:08 PM PDT 24
Peak memory 203840 kb
Host smart-9493307e-3220-4f05-b9ab-d74bdf9a2fca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995440323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.2995440323
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.3897328205
Short name T1148
Test name
Test status
Simulation time 1549690526 ps
CPU time 58.54 seconds
Started May 07 12:59:08 PM PDT 24
Finished May 07 01:00:08 PM PDT 24
Peak memory 205176 kb
Host smart-87e9f4a2-9a52-4145-8898-e0159807098e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897328205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.3897328205
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.4077349103
Short name T81
Test name
Test status
Simulation time 11151652235 ps
CPU time 20.21 seconds
Started May 07 12:59:03 PM PDT 24
Finished May 07 12:59:24 PM PDT 24
Peak memory 203864 kb
Host smart-8fca457e-93f4-4f2c-8e22-d233eb20ca9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077349103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.4077349103
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.3984487417
Short name T367
Test name
Test status
Simulation time 24709695082 ps
CPU time 192.05 seconds
Started May 07 12:59:00 PM PDT 24
Finished May 07 01:02:13 PM PDT 24
Peak memory 1514300 kb
Host smart-ac861960-08c4-40b9-a0da-5c38817e70df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984487417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.3984487417
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1977406050
Short name T51
Test name
Test status
Simulation time 5438831889 ps
CPU time 8.01 seconds
Started May 07 12:59:03 PM PDT 24
Finished May 07 12:59:12 PM PDT 24
Peak memory 218624 kb
Host smart-26350d2e-99cf-4bcb-a5da-758a48cf2527
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977406050 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1977406050
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.4008332217
Short name T121
Test name
Test status
Simulation time 16420556 ps
CPU time 0.64 seconds
Started May 07 12:59:17 PM PDT 24
Finished May 07 12:59:20 PM PDT 24
Peak memory 203784 kb
Host smart-8c0b72ea-b100-471e-ab6f-1075f529d5f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008332217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.4008332217
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.2908205954
Short name T926
Test name
Test status
Simulation time 82604894 ps
CPU time 1.51 seconds
Started May 07 12:59:08 PM PDT 24
Finished May 07 12:59:12 PM PDT 24
Peak memory 212220 kb
Host smart-a54b77d5-4499-4799-89a3-f82fe76b0ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908205954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.2908205954
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.1991932688
Short name T1291
Test name
Test status
Simulation time 1719147420 ps
CPU time 14.2 seconds
Started May 07 12:59:11 PM PDT 24
Finished May 07 12:59:26 PM PDT 24
Peak memory 240088 kb
Host smart-c59ddb13-b72b-4296-860b-4d98e7014b7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991932688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.1991932688
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.837016702
Short name T630
Test name
Test status
Simulation time 8249918391 ps
CPU time 83.83 seconds
Started May 07 12:59:09 PM PDT 24
Finished May 07 01:00:34 PM PDT 24
Peak memory 328660 kb
Host smart-efc7bb42-e0b1-4543-a5f5-c96632930742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837016702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.837016702
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.2847680877
Short name T102
Test name
Test status
Simulation time 4524086923 ps
CPU time 31.18 seconds
Started May 07 12:59:10 PM PDT 24
Finished May 07 12:59:43 PM PDT 24
Peak memory 418472 kb
Host smart-2a9d02ea-411b-4eb0-a1fc-32e3770b70b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847680877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.2847680877
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.1470946841
Short name T487
Test name
Test status
Simulation time 143613759 ps
CPU time 1.12 seconds
Started May 07 12:59:10 PM PDT 24
Finished May 07 12:59:13 PM PDT 24
Peak memory 203916 kb
Host smart-7ddb79fc-43f8-4110-a178-9213f83334e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470946841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.1470946841
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3240123771
Short name T554
Test name
Test status
Simulation time 119911452 ps
CPU time 6.68 seconds
Started May 07 12:59:09 PM PDT 24
Finished May 07 12:59:18 PM PDT 24
Peak memory 220576 kb
Host smart-b8b6b259-3786-4c1c-8c12-b0f09cc132be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240123771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3240123771
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.819117712
Short name T187
Test name
Test status
Simulation time 7380129816 ps
CPU time 90.15 seconds
Started May 07 12:59:07 PM PDT 24
Finished May 07 01:00:39 PM PDT 24
Peak memory 1082484 kb
Host smart-a87fd06b-39b7-422e-b2a7-341a50988276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819117712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.819117712
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.1829247210
Short name T809
Test name
Test status
Simulation time 405305602 ps
CPU time 16.79 seconds
Started May 07 12:59:17 PM PDT 24
Finished May 07 12:59:36 PM PDT 24
Peak memory 203904 kb
Host smart-e943927d-dfd3-4981-94de-38eaea16ab31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829247210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.1829247210
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.3685555387
Short name T48
Test name
Test status
Simulation time 8695685957 ps
CPU time 54.95 seconds
Started May 07 12:59:20 PM PDT 24
Finished May 07 01:00:17 PM PDT 24
Peak memory 467360 kb
Host smart-a7422d35-e852-43bf-a246-f1f14ea83698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685555387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.3685555387
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.698454176
Short name T1112
Test name
Test status
Simulation time 216023969 ps
CPU time 0.66 seconds
Started May 07 12:59:08 PM PDT 24
Finished May 07 12:59:10 PM PDT 24
Peak memory 203724 kb
Host smart-6d3fa409-3da0-4123-9572-2208c7b0987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698454176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.698454176
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.2443468376
Short name T1231
Test name
Test status
Simulation time 6628482331 ps
CPU time 286.23 seconds
Started May 07 12:59:11 PM PDT 24
Finished May 07 01:03:58 PM PDT 24
Peak memory 261816 kb
Host smart-8699cea7-6189-4877-aedf-c9f87d1c8599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443468376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.2443468376
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.1094318733
Short name T1095
Test name
Test status
Simulation time 1193965298 ps
CPU time 24.07 seconds
Started May 07 12:59:09 PM PDT 24
Finished May 07 12:59:35 PM PDT 24
Peak memory 303596 kb
Host smart-20fb7dc1-5cbb-4315-b2d2-a316876b46e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094318733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.1094318733
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.1080328852
Short name T537
Test name
Test status
Simulation time 3385452550 ps
CPU time 10.01 seconds
Started May 07 12:59:06 PM PDT 24
Finished May 07 12:59:18 PM PDT 24
Peak memory 228936 kb
Host smart-906b814f-5c43-4d86-928e-2032e84940da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080328852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.1080328852
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.580298952
Short name T848
Test name
Test status
Simulation time 2454372953 ps
CPU time 3.59 seconds
Started May 07 12:59:14 PM PDT 24
Finished May 07 12:59:19 PM PDT 24
Peak memory 204004 kb
Host smart-216a0586-ac23-4fa6-9936-3b8c570e83d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580298952 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.580298952
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.4271851194
Short name T1084
Test name
Test status
Simulation time 10300105732 ps
CPU time 11.09 seconds
Started May 07 12:59:19 PM PDT 24
Finished May 07 12:59:32 PM PDT 24
Peak memory 255604 kb
Host smart-2bbd3dc1-2ffb-4344-bf90-f8e3daa4e9f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271851194 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.4271851194
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.4008498553
Short name T11
Test name
Test status
Simulation time 394043968 ps
CPU time 2.51 seconds
Started May 07 12:59:18 PM PDT 24
Finished May 07 12:59:22 PM PDT 24
Peak memory 203848 kb
Host smart-c856819f-3b41-4a05-9750-bc1145a1875c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008498553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.4008498553
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.1379290241
Short name T262
Test name
Test status
Simulation time 4003180429 ps
CPU time 5.09 seconds
Started May 07 12:59:10 PM PDT 24
Finished May 07 12:59:17 PM PDT 24
Peak memory 215092 kb
Host smart-4a6f0424-7886-47e3-abe0-3dbfebf000ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379290241 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.1379290241
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.2593618688
Short name T1336
Test name
Test status
Simulation time 18913617118 ps
CPU time 51.06 seconds
Started May 07 12:59:07 PM PDT 24
Finished May 07 01:00:00 PM PDT 24
Peak memory 824148 kb
Host smart-5e293aad-5a27-4135-8a68-3ecb653e97c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593618688 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.2593618688
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.3959373602
Short name T940
Test name
Test status
Simulation time 1223917236 ps
CPU time 19.18 seconds
Started May 07 12:59:07 PM PDT 24
Finished May 07 12:59:28 PM PDT 24
Peak memory 203928 kb
Host smart-441a683c-dbb0-4313-be05-9cd95d8066a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959373602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.3959373602
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.3412799137
Short name T916
Test name
Test status
Simulation time 3815647928 ps
CPU time 42.13 seconds
Started May 07 12:59:09 PM PDT 24
Finished May 07 12:59:53 PM PDT 24
Peak memory 203980 kb
Host smart-7497fab2-6d97-4a04-be59-7301be00e5f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412799137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.3412799137
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.998599138
Short name T1364
Test name
Test status
Simulation time 24187412763 ps
CPU time 37.05 seconds
Started May 07 12:59:06 PM PDT 24
Finished May 07 12:59:45 PM PDT 24
Peak memory 596808 kb
Host smart-669ada6e-a09c-4ed6-b680-b765a06f553b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998599138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_wr.998599138
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.3055886369
Short name T1362
Test name
Test status
Simulation time 15009048951 ps
CPU time 2120.72 seconds
Started May 07 12:59:08 PM PDT 24
Finished May 07 01:34:31 PM PDT 24
Peak memory 3612740 kb
Host smart-a8b964fb-005d-4ee9-88e9-945af063163a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055886369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.3055886369
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.933822484
Short name T545
Test name
Test status
Simulation time 2409530057 ps
CPU time 6.3 seconds
Started May 07 12:59:07 PM PDT 24
Finished May 07 12:59:15 PM PDT 24
Peak memory 204024 kb
Host smart-aeb6fea9-efcd-4efd-9042-3983d2c6f548
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933822484 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_timeout.933822484
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_unexp_stop.2927475484
Short name T357
Test name
Test status
Simulation time 6002295439 ps
CPU time 8.52 seconds
Started May 07 12:59:09 PM PDT 24
Finished May 07 12:59:20 PM PDT 24
Peak memory 212140 kb
Host smart-27ea2529-292a-45b1-95a8-2b5ef5514297
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927475484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.i2c_target_unexp_stop.2927475484
Directory /workspace/48.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/49.i2c_alert_test.1502705263
Short name T842
Test name
Test status
Simulation time 30489602 ps
CPU time 0.62 seconds
Started May 07 12:59:26 PM PDT 24
Finished May 07 12:59:29 PM PDT 24
Peak memory 203780 kb
Host smart-cd4060a2-90c2-4df8-954b-2c73dfc4de60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502705263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.1502705263
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.1002482130
Short name T338
Test name
Test status
Simulation time 319832761 ps
CPU time 1.47 seconds
Started May 07 12:59:15 PM PDT 24
Finished May 07 12:59:19 PM PDT 24
Peak memory 212132 kb
Host smart-37e7dae4-dbad-4c81-8862-0af74156cc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002482130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.1002482130
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.3542180038
Short name T364
Test name
Test status
Simulation time 148339559 ps
CPU time 7.72 seconds
Started May 07 12:59:20 PM PDT 24
Finished May 07 12:59:30 PM PDT 24
Peak memory 226044 kb
Host smart-0b36c4a8-6751-47ad-9a9b-a93949891314
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542180038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.3542180038
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.2473743328
Short name T347
Test name
Test status
Simulation time 7981001985 ps
CPU time 66.19 seconds
Started May 07 12:59:19 PM PDT 24
Finished May 07 01:00:27 PM PDT 24
Peak memory 710264 kb
Host smart-85cee240-7367-42e2-b999-b5f5b46b6e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473743328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.2473743328
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.2309851934
Short name T505
Test name
Test status
Simulation time 63639601 ps
CPU time 0.81 seconds
Started May 07 12:59:15 PM PDT 24
Finished May 07 12:59:17 PM PDT 24
Peak memory 203796 kb
Host smart-92d67893-5bd6-4c49-b340-02856f8f85ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309851934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.2309851934
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.486385653
Short name T1054
Test name
Test status
Simulation time 222759705 ps
CPU time 3.32 seconds
Started May 07 12:59:16 PM PDT 24
Finished May 07 12:59:21 PM PDT 24
Peak memory 218956 kb
Host smart-2e0c0986-4409-4420-a29c-3440078669d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486385653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.
486385653
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.1834389617
Short name T280
Test name
Test status
Simulation time 15660935330 ps
CPU time 107.27 seconds
Started May 07 12:59:16 PM PDT 24
Finished May 07 01:01:05 PM PDT 24
Peak memory 1007564 kb
Host smart-1724d137-b128-4cd5-b94a-bae9dfb2763f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834389617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.1834389617
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.1201407838
Short name T2
Test name
Test status
Simulation time 1944302556 ps
CPU time 6.14 seconds
Started May 07 12:59:28 PM PDT 24
Finished May 07 12:59:35 PM PDT 24
Peak memory 203976 kb
Host smart-18f71f53-e49f-4662-8329-7abdbfbb2a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201407838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.1201407838
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.194768254
Short name T302
Test name
Test status
Simulation time 4597142623 ps
CPU time 19.58 seconds
Started May 07 12:59:26 PM PDT 24
Finished May 07 12:59:47 PM PDT 24
Peak memory 268488 kb
Host smart-248b82b4-ef9d-4052-b645-009c366811f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194768254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.194768254
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.3597813466
Short name T389
Test name
Test status
Simulation time 52896458 ps
CPU time 0.68 seconds
Started May 07 12:59:18 PM PDT 24
Finished May 07 12:59:21 PM PDT 24
Peak memory 203596 kb
Host smart-c79f66a9-e47d-4a9c-90d0-1daa85e0f576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597813466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.3597813466
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.1807027216
Short name T1202
Test name
Test status
Simulation time 12232229365 ps
CPU time 39.67 seconds
Started May 07 12:59:17 PM PDT 24
Finished May 07 12:59:59 PM PDT 24
Peak memory 556776 kb
Host smart-7f2e420c-9a5c-46e3-b3ba-bf3639296535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807027216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1807027216
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.945613023
Short name T821
Test name
Test status
Simulation time 6801954498 ps
CPU time 31.68 seconds
Started May 07 12:59:15 PM PDT 24
Finished May 07 12:59:48 PM PDT 24
Peak memory 351228 kb
Host smart-bbfa627c-b093-4a7b-87dc-64dcc0aa4adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945613023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.945613023
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.2560607608
Short name T1179
Test name
Test status
Simulation time 62776254406 ps
CPU time 625.06 seconds
Started May 07 12:59:20 PM PDT 24
Finished May 07 01:09:48 PM PDT 24
Peak memory 2235112 kb
Host smart-90b8baf0-de83-4b90-bbd6-0be9da85125e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560607608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.2560607608
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.4266688934
Short name T192
Test name
Test status
Simulation time 405506098 ps
CPU time 17.76 seconds
Started May 07 12:59:17 PM PDT 24
Finished May 07 12:59:37 PM PDT 24
Peak memory 212172 kb
Host smart-8ce080aa-6dc6-40e8-8cae-be4191f97ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266688934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.4266688934
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.2743786779
Short name T352
Test name
Test status
Simulation time 3876525513 ps
CPU time 5.14 seconds
Started May 07 12:59:19 PM PDT 24
Finished May 07 12:59:26 PM PDT 24
Peak memory 212224 kb
Host smart-4fc9e029-7ec0-4e24-a34f-aa50e835b324
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743786779 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.2743786779
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.2166475454
Short name T1104
Test name
Test status
Simulation time 10687759165 ps
CPU time 3.77 seconds
Started May 07 12:59:24 PM PDT 24
Finished May 07 12:59:30 PM PDT 24
Peak memory 212980 kb
Host smart-a92aa4d7-c9de-4ce4-9a69-1e87da5908e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166475454 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.2166475454
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.4100535754
Short name T1180
Test name
Test status
Simulation time 10355532700 ps
CPU time 8.7 seconds
Started May 07 12:59:20 PM PDT 24
Finished May 07 12:59:31 PM PDT 24
Peak memory 270156 kb
Host smart-04c79c39-aada-49c1-b575-9215a56f9035
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100535754 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.4100535754
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.2421284099
Short name T853
Test name
Test status
Simulation time 1436271271 ps
CPU time 2.22 seconds
Started May 07 12:59:23 PM PDT 24
Finished May 07 12:59:27 PM PDT 24
Peak memory 203852 kb
Host smart-702578e6-c6e7-415a-9198-566847ab9294
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421284099 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.2421284099
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1142577755
Short name T334
Test name
Test status
Simulation time 1066247600 ps
CPU time 5.57 seconds
Started May 07 12:59:21 PM PDT 24
Finished May 07 12:59:29 PM PDT 24
Peak memory 206744 kb
Host smart-7c54446b-42f3-44d9-926b-8eaf5e614c60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142577755 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1142577755
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.3367031112
Short name T1021
Test name
Test status
Simulation time 12493619860 ps
CPU time 67.96 seconds
Started May 07 12:59:23 PM PDT 24
Finished May 07 01:00:33 PM PDT 24
Peak memory 1522160 kb
Host smart-8d2b6195-a929-4584-85f4-5f4126e03bfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367031112 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.3367031112
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.330837157
Short name T1214
Test name
Test status
Simulation time 901478637 ps
CPU time 11.5 seconds
Started May 07 12:59:21 PM PDT 24
Finished May 07 12:59:36 PM PDT 24
Peak memory 203912 kb
Host smart-948c9130-abaa-4b90-ba5e-a6a5d7069b00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330837157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_tar
get_smoke.330837157
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.3466688919
Short name T196
Test name
Test status
Simulation time 3061386959 ps
CPU time 12.86 seconds
Started May 07 12:59:22 PM PDT 24
Finished May 07 12:59:37 PM PDT 24
Peak memory 217180 kb
Host smart-064c98a9-fe4c-4e4f-9264-3e34e70ae9ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466688919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.3466688919
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.2903554199
Short name T760
Test name
Test status
Simulation time 11986139314 ps
CPU time 21.91 seconds
Started May 07 12:59:20 PM PDT 24
Finished May 07 12:59:44 PM PDT 24
Peak memory 203968 kb
Host smart-d70f4aa5-f6a9-43dc-b277-2bd910573794
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903554199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.2903554199
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.280048132
Short name T1298
Test name
Test status
Simulation time 41151048827 ps
CPU time 1150.39 seconds
Started May 07 12:59:21 PM PDT 24
Finished May 07 01:18:34 PM PDT 24
Peak memory 4880032 kb
Host smart-7e1765ed-88de-4305-a2a9-0d57ae80442f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280048132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_t
arget_stretch.280048132
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.864606470
Short name T823
Test name
Test status
Simulation time 3461320842 ps
CPU time 7.27 seconds
Started May 07 12:59:22 PM PDT 24
Finished May 07 12:59:32 PM PDT 24
Peak memory 203964 kb
Host smart-cb77ca41-6c87-47e5-a563-4f1cfc3118f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864606470 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_timeout.864606470
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.2779056005
Short name T725
Test name
Test status
Simulation time 46044228 ps
CPU time 0.61 seconds
Started May 07 12:52:57 PM PDT 24
Finished May 07 12:52:59 PM PDT 24
Peak memory 203812 kb
Host smart-36c9206b-eb08-4b77-b72c-e2acc473fa44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779056005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.2779056005
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.278568723
Short name T394
Test name
Test status
Simulation time 159293205 ps
CPU time 1.48 seconds
Started May 07 12:52:49 PM PDT 24
Finished May 07 12:52:52 PM PDT 24
Peak memory 212176 kb
Host smart-02c1ebc0-7932-41a2-9f74-946fbd3ca36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278568723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.278568723
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.424586311
Short name T989
Test name
Test status
Simulation time 158291262 ps
CPU time 8.47 seconds
Started May 07 12:52:52 PM PDT 24
Finished May 07 12:53:02 PM PDT 24
Peak memory 231488 kb
Host smart-dce1eb4f-57ea-41c6-a8ed-32166af67454
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424586311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty
.424586311
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2666360212
Short name T608
Test name
Test status
Simulation time 10014713502 ps
CPU time 65.17 seconds
Started May 07 12:52:52 PM PDT 24
Finished May 07 12:53:58 PM PDT 24
Peak memory 679732 kb
Host smart-6d9b16d4-30fe-4266-9164-8bca40b6ce28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666360212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2666360212
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.3777322385
Short name T306
Test name
Test status
Simulation time 2239816444 ps
CPU time 51.02 seconds
Started May 07 12:52:50 PM PDT 24
Finished May 07 12:53:42 PM PDT 24
Peak memory 581640 kb
Host smart-b8998299-ef62-4d82-9063-1cf1c43c4ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777322385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.3777322385
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.1800949028
Short name T843
Test name
Test status
Simulation time 589733760 ps
CPU time 1.03 seconds
Started May 07 12:52:47 PM PDT 24
Finished May 07 12:52:49 PM PDT 24
Peak memory 203780 kb
Host smart-10e6d4f5-c1c0-4b54-965a-4657442eef4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800949028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.1800949028
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.4119464680
Short name T695
Test name
Test status
Simulation time 239008540 ps
CPU time 6.09 seconds
Started May 07 12:52:50 PM PDT 24
Finished May 07 12:52:57 PM PDT 24
Peak memory 203896 kb
Host smart-8fa6bb94-6ec6-4cc2-8443-8d85ecfe4103
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119464680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
4119464680
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.3139104678
Short name T289
Test name
Test status
Simulation time 18674912195 ps
CPU time 152.77 seconds
Started May 07 12:52:50 PM PDT 24
Finished May 07 12:55:24 PM PDT 24
Peak memory 1321048 kb
Host smart-da911310-d4e8-410f-aa42-c29936bcf7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139104678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3139104678
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.2228135892
Short name T870
Test name
Test status
Simulation time 409518652 ps
CPU time 6.57 seconds
Started May 07 12:52:57 PM PDT 24
Finished May 07 12:53:05 PM PDT 24
Peak memory 203896 kb
Host smart-374a2e91-8ec0-4e55-b612-86df7810496d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228135892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.2228135892
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.2239910833
Short name T1144
Test name
Test status
Simulation time 6664145766 ps
CPU time 30.82 seconds
Started May 07 12:52:58 PM PDT 24
Finished May 07 12:53:30 PM PDT 24
Peak memory 324196 kb
Host smart-bf9e6937-ca04-4899-8d08-f17f23ae0e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239910833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.2239910833
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.4194704911
Short name T799
Test name
Test status
Simulation time 96069141 ps
CPU time 0.65 seconds
Started May 07 12:52:52 PM PDT 24
Finished May 07 12:52:54 PM PDT 24
Peak memory 203632 kb
Host smart-20bdbdab-1197-4cc9-a502-4548a3a8b9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194704911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.4194704911
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.3367372496
Short name T1288
Test name
Test status
Simulation time 6488168635 ps
CPU time 377.83 seconds
Started May 07 12:52:53 PM PDT 24
Finished May 07 12:59:11 PM PDT 24
Peak memory 780824 kb
Host smart-01d3ffd7-9af5-4d7c-af6a-8a3eb3dfa082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367372496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.3367372496
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.2870639865
Short name T483
Test name
Test status
Simulation time 10911064705 ps
CPU time 18.32 seconds
Started May 07 12:52:51 PM PDT 24
Finished May 07 12:53:10 PM PDT 24
Peak memory 292860 kb
Host smart-ebb1b619-b4cf-41b2-8df7-3359ed90d838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870639865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.2870639865
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.2487410248
Short name T193
Test name
Test status
Simulation time 65601263152 ps
CPU time 153.36 seconds
Started May 07 12:52:48 PM PDT 24
Finished May 07 12:55:23 PM PDT 24
Peak memory 1064216 kb
Host smart-ece236ff-bfc9-4559-8a74-021bcb9a007f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487410248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.2487410248
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.2979905646
Short name T820
Test name
Test status
Simulation time 1769277673 ps
CPU time 18.78 seconds
Started May 07 12:52:50 PM PDT 24
Finished May 07 12:53:10 PM PDT 24
Peak memory 212144 kb
Host smart-cfe610a1-2107-44dc-b389-750f9a03c926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979905646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.2979905646
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.2534979070
Short name T873
Test name
Test status
Simulation time 2074103820 ps
CPU time 2.94 seconds
Started May 07 12:53:01 PM PDT 24
Finished May 07 12:53:05 PM PDT 24
Peak memory 203928 kb
Host smart-aed5f5d9-d3e9-46ab-b0d9-5dfa008425c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534979070 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2534979070
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.3877126393
Short name T1003
Test name
Test status
Simulation time 10065315528 ps
CPU time 32.44 seconds
Started May 07 12:53:01 PM PDT 24
Finished May 07 12:53:35 PM PDT 24
Peak memory 321588 kb
Host smart-66982fdf-79f7-4669-841f-4335b7f49375
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877126393 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.3877126393
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.1092541795
Short name T67
Test name
Test status
Simulation time 10115046001 ps
CPU time 77.2 seconds
Started May 07 12:52:56 PM PDT 24
Finished May 07 12:54:14 PM PDT 24
Peak memory 584404 kb
Host smart-70d89408-7cf6-4b5f-a8d5-d3fe492e0c2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092541795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.1092541795
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.1485492254
Short name T828
Test name
Test status
Simulation time 1651124665 ps
CPU time 2.7 seconds
Started May 07 12:52:57 PM PDT 24
Finished May 07 12:53:01 PM PDT 24
Peak memory 203904 kb
Host smart-511f573c-670e-4e4e-a8f7-71c4e7784561
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485492254 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.1485492254
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.1504336616
Short name T834
Test name
Test status
Simulation time 3561019057 ps
CPU time 4.76 seconds
Started May 07 12:52:59 PM PDT 24
Finished May 07 12:53:04 PM PDT 24
Peak memory 210484 kb
Host smart-6537c2d9-caa8-47a2-a03f-6aa787657c80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504336616 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.1504336616
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.3651177835
Short name T559
Test name
Test status
Simulation time 7765143307 ps
CPU time 103.49 seconds
Started May 07 12:52:56 PM PDT 24
Finished May 07 12:54:41 PM PDT 24
Peak memory 1995888 kb
Host smart-3443e9cb-81cd-4309-a575-6723ba6c0d74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651177835 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3651177835
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.975578102
Short name T9
Test name
Test status
Simulation time 2593646710 ps
CPU time 21.07 seconds
Started May 07 12:52:49 PM PDT 24
Finished May 07 12:53:11 PM PDT 24
Peak memory 203964 kb
Host smart-4a84f413-838b-475f-93c4-6cf8488981a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975578102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_targ
et_smoke.975578102
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.1552429943
Short name T997
Test name
Test status
Simulation time 367413681 ps
CPU time 16 seconds
Started May 07 12:53:01 PM PDT 24
Finished May 07 12:53:19 PM PDT 24
Peak memory 203936 kb
Host smart-bc73c182-f9ac-4bf6-b499-ca8125cf8998
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552429943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.1552429943
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.1170378764
Short name T477
Test name
Test status
Simulation time 51117759299 ps
CPU time 345.64 seconds
Started May 07 12:52:57 PM PDT 24
Finished May 07 12:58:44 PM PDT 24
Peak memory 3444916 kb
Host smart-42350006-b653-4900-bdf6-2b5d907b3b71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170378764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.1170378764
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.3506484987
Short name T324
Test name
Test status
Simulation time 3271844342 ps
CPU time 47.59 seconds
Started May 07 12:52:57 PM PDT 24
Finished May 07 12:53:46 PM PDT 24
Peak memory 667456 kb
Host smart-789dcfda-72aa-4b1f-8cb9-a2337cafd376
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506484987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.3506484987
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.3433125847
Short name T587
Test name
Test status
Simulation time 1195085781 ps
CPU time 6.91 seconds
Started May 07 12:52:56 PM PDT 24
Finished May 07 12:53:04 PM PDT 24
Peak memory 213072 kb
Host smart-866b1ed4-5976-4d10-b2d2-f461c132fed8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433125847 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.3433125847
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.3268929773
Short name T669
Test name
Test status
Simulation time 90010722 ps
CPU time 0.63 seconds
Started May 07 12:53:10 PM PDT 24
Finished May 07 12:53:12 PM PDT 24
Peak memory 203792 kb
Host smart-0fc81ee3-4211-4c26-9648-837c3ed27725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268929773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.3268929773
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.3170170586
Short name T775
Test name
Test status
Simulation time 406207289 ps
CPU time 1.5 seconds
Started May 07 12:53:10 PM PDT 24
Finished May 07 12:53:13 PM PDT 24
Peak memory 212184 kb
Host smart-38f8d917-f687-4b84-9431-84ba0a2fa714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170170586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.3170170586
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.1184383444
Short name T1178
Test name
Test status
Simulation time 1628271340 ps
CPU time 21.34 seconds
Started May 07 12:53:02 PM PDT 24
Finished May 07 12:53:25 PM PDT 24
Peak memory 290688 kb
Host smart-8bebfe8b-59d8-47b5-961f-c6b709be55fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184383444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.1184383444
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.301632023
Short name T1269
Test name
Test status
Simulation time 4042038869 ps
CPU time 152.73 seconds
Started May 07 12:53:04 PM PDT 24
Finished May 07 12:55:39 PM PDT 24
Peak memory 673980 kb
Host smart-b6bc3f00-6433-420e-ac3b-af0c5e47c182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301632023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.301632023
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.1381359799
Short name T425
Test name
Test status
Simulation time 1992584277 ps
CPU time 73.34 seconds
Started May 07 12:53:09 PM PDT 24
Finished May 07 12:54:23 PM PDT 24
Peak memory 699568 kb
Host smart-9dcd4caa-67dc-49a8-b00f-97beb73a002f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381359799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1381359799
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.590161265
Short name T1348
Test name
Test status
Simulation time 91621114 ps
CPU time 0.91 seconds
Started May 07 12:53:10 PM PDT 24
Finished May 07 12:53:12 PM PDT 24
Peak memory 203756 kb
Host smart-0e252476-ef6e-45f7-bfff-f39cca97bcca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590161265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt
.590161265
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.1660497890
Short name T826
Test name
Test status
Simulation time 751677900 ps
CPU time 9.62 seconds
Started May 07 12:53:02 PM PDT 24
Finished May 07 12:53:14 PM PDT 24
Peak memory 203904 kb
Host smart-7308f2d6-b824-427c-9f80-be92e8a91bd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660497890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
1660497890
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.2979969475
Short name T1217
Test name
Test status
Simulation time 9559932425 ps
CPU time 55.38 seconds
Started May 07 12:53:02 PM PDT 24
Finished May 07 12:53:59 PM PDT 24
Peak memory 796976 kb
Host smart-24ffa915-8b5b-4be1-bbdd-997b91ae6ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979969475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2979969475
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.2059920661
Short name T762
Test name
Test status
Simulation time 383477686 ps
CPU time 16.43 seconds
Started May 07 12:53:11 PM PDT 24
Finished May 07 12:53:29 PM PDT 24
Peak memory 203768 kb
Host smart-28e9532f-dcb6-4c2d-93a8-ff75bd11cb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059920661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.2059920661
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.3539431100
Short name T825
Test name
Test status
Simulation time 10269777615 ps
CPU time 24.67 seconds
Started May 07 12:53:11 PM PDT 24
Finished May 07 12:53:37 PM PDT 24
Peak memory 323988 kb
Host smart-6cb7a31b-da9c-4645-9ff6-cd2a503f7953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539431100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.3539431100
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.2291289845
Short name T481
Test name
Test status
Simulation time 24221866 ps
CPU time 0.66 seconds
Started May 07 12:53:03 PM PDT 24
Finished May 07 12:53:05 PM PDT 24
Peak memory 203788 kb
Host smart-c0f9192b-1d55-4673-960c-d3adbfed0fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291289845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.2291289845
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.3781953034
Short name T89
Test name
Test status
Simulation time 7607740503 ps
CPU time 55.33 seconds
Started May 07 12:53:02 PM PDT 24
Finished May 07 12:53:59 PM PDT 24
Peak memory 241876 kb
Host smart-7b65d994-efd5-4f0e-982f-3518b792d2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781953034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.3781953034
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.3355402577
Short name T569
Test name
Test status
Simulation time 2625133210 ps
CPU time 65.36 seconds
Started May 07 12:52:58 PM PDT 24
Finished May 07 12:54:04 PM PDT 24
Peak memory 358196 kb
Host smart-d8a615c3-8eab-4d89-95cd-85d84524ea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355402577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.3355402577
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.2937057210
Short name T840
Test name
Test status
Simulation time 2324445185 ps
CPU time 8.57 seconds
Started May 07 12:53:10 PM PDT 24
Finished May 07 12:53:21 PM PDT 24
Peak memory 212264 kb
Host smart-1fa13bc3-58ba-4381-a02f-2a60b0af8175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937057210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.2937057210
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.3233784265
Short name T1072
Test name
Test status
Simulation time 2108489399 ps
CPU time 3.17 seconds
Started May 07 12:53:11 PM PDT 24
Finished May 07 12:53:16 PM PDT 24
Peak memory 203960 kb
Host smart-aa1b26ff-bd48-4962-a9dc-91207a5b2c35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233784265 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.3233784265
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2615339460
Short name T668
Test name
Test status
Simulation time 10103376752 ps
CPU time 77.35 seconds
Started May 07 12:53:03 PM PDT 24
Finished May 07 12:54:23 PM PDT 24
Peak memory 435984 kb
Host smart-843453a8-3248-40dd-84e3-30f175e0ca0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615339460 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2615339460
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.857222620
Short name T1012
Test name
Test status
Simulation time 10140880139 ps
CPU time 13.76 seconds
Started May 07 12:53:11 PM PDT 24
Finished May 07 12:53:26 PM PDT 24
Peak memory 297056 kb
Host smart-3e161998-a581-4545-adb1-d2c1d2485b2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857222620 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.857222620
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.1230942624
Short name T318
Test name
Test status
Simulation time 222335620 ps
CPU time 1.85 seconds
Started May 07 12:53:09 PM PDT 24
Finished May 07 12:53:12 PM PDT 24
Peak memory 203816 kb
Host smart-1cb62342-f34b-4f11-b45a-eb796fd85352
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230942624 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.1230942624
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3272751537
Short name T1069
Test name
Test status
Simulation time 5472985390 ps
CPU time 4.6 seconds
Started May 07 12:53:01 PM PDT 24
Finished May 07 12:53:07 PM PDT 24
Peak memory 204308 kb
Host smart-c1ce2762-13fb-4de9-88e0-93d721fdb364
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272751537 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3272751537
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.2819727616
Short name T837
Test name
Test status
Simulation time 6570988262 ps
CPU time 12.69 seconds
Started May 07 12:53:02 PM PDT 24
Finished May 07 12:53:17 PM PDT 24
Peak memory 558424 kb
Host smart-b5b9ad90-0e2e-4886-b623-d8d0e8b8b9e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819727616 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.2819727616
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.1270199402
Short name T1306
Test name
Test status
Simulation time 3726261712 ps
CPU time 33.86 seconds
Started May 07 12:53:04 PM PDT 24
Finished May 07 12:53:41 PM PDT 24
Peak memory 203944 kb
Host smart-2c6f03c9-1fbd-440d-b99f-a5539c0c967c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270199402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.1270199402
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.1764304754
Short name T543
Test name
Test status
Simulation time 1121514079 ps
CPU time 46.37 seconds
Started May 07 12:53:09 PM PDT 24
Finished May 07 12:53:57 PM PDT 24
Peak memory 203920 kb
Host smart-df8d0c8e-8d30-488a-acba-9c5b08255633
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764304754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.1764304754
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.1992790850
Short name T230
Test name
Test status
Simulation time 36420751229 ps
CPU time 465.36 seconds
Started May 07 12:53:01 PM PDT 24
Finished May 07 01:00:49 PM PDT 24
Peak memory 4056028 kb
Host smart-6225ff68-a753-4278-9cd3-6a74afea925e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992790850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.1992790850
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.2025260249
Short name T396
Test name
Test status
Simulation time 16298439543 ps
CPU time 86.46 seconds
Started May 07 12:53:04 PM PDT 24
Finished May 07 12:54:33 PM PDT 24
Peak memory 1004972 kb
Host smart-3249b4cc-8380-4dfc-b13d-493e1bd011df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025260249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.2025260249
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.1844372879
Short name T1167
Test name
Test status
Simulation time 9415388492 ps
CPU time 6.94 seconds
Started May 07 12:53:04 PM PDT 24
Finished May 07 12:53:13 PM PDT 24
Peak memory 218056 kb
Host smart-67cc47af-67f2-471a-a7bf-e3061fc24890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844372879 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.1844372879
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.4005697261
Short name T863
Test name
Test status
Simulation time 43938572 ps
CPU time 0.62 seconds
Started May 07 12:53:15 PM PDT 24
Finished May 07 12:53:17 PM PDT 24
Peak memory 203728 kb
Host smart-1b63de01-2493-45ba-ad80-29b1fd835b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005697261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.4005697261
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.121534089
Short name T466
Test name
Test status
Simulation time 120537563 ps
CPU time 1.56 seconds
Started May 07 12:53:20 PM PDT 24
Finished May 07 12:53:22 PM PDT 24
Peak memory 212264 kb
Host smart-b54595d3-c2cb-4e89-824e-ee3fa53ba3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121534089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.121534089
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.799347033
Short name T1123
Test name
Test status
Simulation time 5449808584 ps
CPU time 17.69 seconds
Started May 07 12:53:15 PM PDT 24
Finished May 07 12:53:34 PM PDT 24
Peak memory 271852 kb
Host smart-429fe8e1-f177-4284-a81d-7494d4834441
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799347033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.799347033
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.1061168535
Short name T1278
Test name
Test status
Simulation time 7892308007 ps
CPU time 130.75 seconds
Started May 07 12:53:16 PM PDT 24
Finished May 07 12:55:28 PM PDT 24
Peak memory 589808 kb
Host smart-4f3bbc64-4cbd-43b5-899f-6493b6e4eae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061168535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.1061168535
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.3729431886
Short name T304
Test name
Test status
Simulation time 6278220294 ps
CPU time 53.42 seconds
Started May 07 12:53:10 PM PDT 24
Finished May 07 12:54:05 PM PDT 24
Peak memory 608836 kb
Host smart-bf9ee10c-3731-4a51-a4dd-c640f0edc1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729431886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.3729431886
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.4223612007
Short name T643
Test name
Test status
Simulation time 158969692 ps
CPU time 0.94 seconds
Started May 07 12:53:11 PM PDT 24
Finished May 07 12:53:13 PM PDT 24
Peak memory 203740 kb
Host smart-511ed62d-4de1-4bd4-811c-a6bd362f76e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223612007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.4223612007
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.4137022841
Short name T1259
Test name
Test status
Simulation time 169031271 ps
CPU time 4.14 seconds
Started May 07 12:53:15 PM PDT 24
Finished May 07 12:53:20 PM PDT 24
Peak memory 203956 kb
Host smart-d3d0cca2-5849-4194-abd8-99afd71a83a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137022841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
4137022841
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3076992138
Short name T184
Test name
Test status
Simulation time 4441971583 ps
CPU time 107.87 seconds
Started May 07 12:53:09 PM PDT 24
Finished May 07 12:54:58 PM PDT 24
Peak memory 1285004 kb
Host smart-ecedac15-b24c-4161-aaca-7c98d0fb436e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076992138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3076992138
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.745215821
Short name T1218
Test name
Test status
Simulation time 544482474 ps
CPU time 15.83 seconds
Started May 07 12:53:16 PM PDT 24
Finished May 07 12:53:33 PM PDT 24
Peak memory 203876 kb
Host smart-5d999180-3ab2-4ea8-9826-36f1e386bbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745215821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.745215821
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.1544903350
Short name T47
Test name
Test status
Simulation time 2022422826 ps
CPU time 40.8 seconds
Started May 07 12:53:17 PM PDT 24
Finished May 07 12:53:59 PM PDT 24
Peak memory 477860 kb
Host smart-83f9b42d-bd15-4f70-b32a-033fb2fc4422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544903350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.1544903350
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.2492486820
Short name T857
Test name
Test status
Simulation time 80026725 ps
CPU time 0.69 seconds
Started May 07 12:53:09 PM PDT 24
Finished May 07 12:53:11 PM PDT 24
Peak memory 203684 kb
Host smart-693390ec-45fc-42a6-8a3c-18e52c24c26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492486820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.2492486820
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.2907825305
Short name T86
Test name
Test status
Simulation time 75703431829 ps
CPU time 143.97 seconds
Started May 07 12:53:15 PM PDT 24
Finished May 07 12:55:40 PM PDT 24
Peak memory 861524 kb
Host smart-d9d5b913-f5e2-4e58-8859-07e24fc79c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907825305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.2907825305
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.4107666777
Short name T1089
Test name
Test status
Simulation time 6531127073 ps
CPU time 71.36 seconds
Started May 07 12:53:11 PM PDT 24
Finished May 07 12:54:23 PM PDT 24
Peak memory 346440 kb
Host smart-764f58a7-b379-4434-a73a-f81d2a035b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107666777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.4107666777
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.792290839
Short name T1295
Test name
Test status
Simulation time 12533763773 ps
CPU time 698.83 seconds
Started May 07 12:53:14 PM PDT 24
Finished May 07 01:04:54 PM PDT 24
Peak memory 1220180 kb
Host smart-12c2b137-140a-4945-9d76-8694b6935909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792290839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.792290839
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.656731387
Short name T245
Test name
Test status
Simulation time 693286434 ps
CPU time 31.91 seconds
Started May 07 12:53:17 PM PDT 24
Finished May 07 12:53:50 PM PDT 24
Peak memory 212056 kb
Host smart-a701e584-a194-4ccc-9c4f-a1f53030ccd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656731387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.656731387
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.1099771889
Short name T579
Test name
Test status
Simulation time 4523396481 ps
CPU time 5.36 seconds
Started May 07 12:53:16 PM PDT 24
Finished May 07 12:53:23 PM PDT 24
Peak memory 212696 kb
Host smart-5c8529f6-3859-49fa-8edb-b79e82440eb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099771889 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.1099771889
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.1026527300
Short name T1188
Test name
Test status
Simulation time 10036955543 ps
CPU time 73.93 seconds
Started May 07 12:53:20 PM PDT 24
Finished May 07 12:54:35 PM PDT 24
Peak memory 468692 kb
Host smart-5c299ec6-c952-4cd8-9069-d86ac11a3eb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026527300 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.1026527300
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.3636719940
Short name T645
Test name
Test status
Simulation time 10027444833 ps
CPU time 80.5 seconds
Started May 07 12:53:15 PM PDT 24
Finished May 07 12:54:36 PM PDT 24
Peak memory 557844 kb
Host smart-deecd342-db2e-4c05-8445-70500ac71208
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636719940 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.3636719940
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.2223974777
Short name T14
Test name
Test status
Simulation time 404703605 ps
CPU time 2.4 seconds
Started May 07 12:53:17 PM PDT 24
Finished May 07 12:53:20 PM PDT 24
Peak memory 203868 kb
Host smart-2fa1e10a-9e92-43f9-bc2f-1813e06ab56c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223974777 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.2223974777
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.3698226637
Short name T736
Test name
Test status
Simulation time 603303540 ps
CPU time 3.57 seconds
Started May 07 12:53:16 PM PDT 24
Finished May 07 12:53:21 PM PDT 24
Peak memory 203908 kb
Host smart-3cee82de-365d-47c4-af7a-f8cc5bea2227
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698226637 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.3698226637
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.843843508
Short name T912
Test name
Test status
Simulation time 4347839616 ps
CPU time 9.36 seconds
Started May 07 12:53:16 PM PDT 24
Finished May 07 12:53:27 PM PDT 24
Peak memory 203936 kb
Host smart-c8ebe98b-8180-4182-b64b-d901aab66bde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843843508 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.843843508
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.484209488
Short name T1320
Test name
Test status
Simulation time 1080546946 ps
CPU time 13.06 seconds
Started May 07 12:53:17 PM PDT 24
Finished May 07 12:53:31 PM PDT 24
Peak memory 203896 kb
Host smart-628d19df-3775-4522-8beb-9818fad14e46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484209488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_targ
et_smoke.484209488
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.403112586
Short name T515
Test name
Test status
Simulation time 380748076 ps
CPU time 6.78 seconds
Started May 07 12:53:15 PM PDT 24
Finished May 07 12:53:23 PM PDT 24
Peak memory 203904 kb
Host smart-8af5f237-09a6-4527-ac1a-460b1c1df06a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403112586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_rd.403112586
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.26988390
Short name T1097
Test name
Test status
Simulation time 62446875962 ps
CPU time 221.59 seconds
Started May 07 12:53:17 PM PDT 24
Finished May 07 12:57:00 PM PDT 24
Peak memory 2607816 kb
Host smart-5d9f8ccb-8aaa-4ac8-b86e-ed0f6d1ca287
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26988390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stress_wr.26988390
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.3971867621
Short name T727
Test name
Test status
Simulation time 35842440842 ps
CPU time 2593.62 seconds
Started May 07 12:53:16 PM PDT 24
Finished May 07 01:36:31 PM PDT 24
Peak memory 4342832 kb
Host smart-3b76d653-80d5-42ec-b295-980d394c5baf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971867621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.3971867621
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1945273445
Short name T691
Test name
Test status
Simulation time 2416997007 ps
CPU time 6.46 seconds
Started May 07 12:53:16 PM PDT 24
Finished May 07 12:53:24 PM PDT 24
Peak memory 212160 kb
Host smart-3bb077e9-7fa4-4cc4-a9c9-5aa759b02812
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945273445 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1945273445
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.2271709434
Short name T1358
Test name
Test status
Simulation time 25071149 ps
CPU time 0.59 seconds
Started May 07 12:53:28 PM PDT 24
Finished May 07 12:53:31 PM PDT 24
Peak memory 203800 kb
Host smart-9bd85145-6597-46fd-a4ad-2aa7061c83a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271709434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.2271709434
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.1091099921
Short name T540
Test name
Test status
Simulation time 179994211 ps
CPU time 1.22 seconds
Started May 07 12:53:30 PM PDT 24
Finished May 07 12:53:33 PM PDT 24
Peak memory 212188 kb
Host smart-6c33f4d5-caad-4a22-a616-e15a4372b436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091099921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.1091099921
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.726854277
Short name T737
Test name
Test status
Simulation time 1623051145 ps
CPU time 21.25 seconds
Started May 07 12:53:22 PM PDT 24
Finished May 07 12:53:44 PM PDT 24
Peak memory 293216 kb
Host smart-e5b18904-01e6-4b13-b56f-c1cb5b7e97a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726854277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty
.726854277
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.2454036870
Short name T419
Test name
Test status
Simulation time 5926625878 ps
CPU time 35.62 seconds
Started May 07 12:53:24 PM PDT 24
Finished May 07 12:54:01 PM PDT 24
Peak memory 220292 kb
Host smart-777c713a-a6fe-4f35-81d1-03437e0b3640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454036870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2454036870
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.2758139385
Short name T1327
Test name
Test status
Simulation time 2070133049 ps
CPU time 67.36 seconds
Started May 07 12:53:16 PM PDT 24
Finished May 07 12:54:25 PM PDT 24
Peak memory 667852 kb
Host smart-bbf99612-c76a-4b93-8ee5-3a43004801b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758139385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.2758139385
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.426493979
Short name T715
Test name
Test status
Simulation time 434934486 ps
CPU time 0.94 seconds
Started May 07 12:53:23 PM PDT 24
Finished May 07 12:53:25 PM PDT 24
Peak memory 203824 kb
Host smart-e6447121-d31c-4fb5-aabe-f06f51439dda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426493979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt
.426493979
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.4150726060
Short name T864
Test name
Test status
Simulation time 172257816 ps
CPU time 9.43 seconds
Started May 07 12:53:23 PM PDT 24
Finished May 07 12:53:33 PM PDT 24
Peak memory 234000 kb
Host smart-d1b9bf57-515f-40af-962d-9196fd134d80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150726060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
4150726060
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.557770050
Short name T188
Test name
Test status
Simulation time 16254116852 ps
CPU time 95.38 seconds
Started May 07 12:53:16 PM PDT 24
Finished May 07 12:54:53 PM PDT 24
Peak memory 1121384 kb
Host smart-712db47e-0adc-4e80-97e4-055e4dc6ebdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557770050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.557770050
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.4064659283
Short name T479
Test name
Test status
Simulation time 2062085335 ps
CPU time 5.93 seconds
Started May 07 12:53:27 PM PDT 24
Finished May 07 12:53:34 PM PDT 24
Peak memory 203892 kb
Host smart-4e6d07f6-660b-4952-98d2-0893818b937a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064659283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.4064659283
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.109843064
Short name T407
Test name
Test status
Simulation time 1490011837 ps
CPU time 31.57 seconds
Started May 07 12:53:28 PM PDT 24
Finished May 07 12:54:01 PM PDT 24
Peak memory 362484 kb
Host smart-f2b6cd78-a041-4bb4-817f-6783831c9a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109843064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.109843064
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.2366252571
Short name T1182
Test name
Test status
Simulation time 15413125 ps
CPU time 0.68 seconds
Started May 07 12:53:16 PM PDT 24
Finished May 07 12:53:18 PM PDT 24
Peak memory 203712 kb
Host smart-d80ce76d-1365-402b-acfb-6dad491325c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366252571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.2366252571
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1296010145
Short name T78
Test name
Test status
Simulation time 395830803 ps
CPU time 3.56 seconds
Started May 07 12:53:23 PM PDT 24
Finished May 07 12:53:28 PM PDT 24
Peak memory 212516 kb
Host smart-2b956400-df35-400e-a1e3-969af4c47c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296010145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1296010145
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.1701210996
Short name T79
Test name
Test status
Simulation time 5463133705 ps
CPU time 71.24 seconds
Started May 07 12:53:20 PM PDT 24
Finished May 07 12:54:32 PM PDT 24
Peak memory 331000 kb
Host smart-cc0acbf9-e882-40a5-81e0-23b3185eb7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701210996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.1701210996
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.2657284160
Short name T1340
Test name
Test status
Simulation time 35323097069 ps
CPU time 1083.18 seconds
Started May 07 12:53:23 PM PDT 24
Finished May 07 01:11:27 PM PDT 24
Peak memory 1787696 kb
Host smart-7b1cab3e-7922-43f7-bf5d-386e2887ecb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657284160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.2657284160
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.536247656
Short name T267
Test name
Test status
Simulation time 437284840 ps
CPU time 7.72 seconds
Started May 07 12:53:22 PM PDT 24
Finished May 07 12:53:31 PM PDT 24
Peak memory 220492 kb
Host smart-f97f5198-a422-4140-ba52-12dad7882e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536247656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.536247656
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.3366722041
Short name T1133
Test name
Test status
Simulation time 4374168180 ps
CPU time 5.01 seconds
Started May 07 12:53:29 PM PDT 24
Finished May 07 12:53:35 PM PDT 24
Peak memory 212228 kb
Host smart-7faf96eb-d884-4d71-8f49-ae2bf3517294
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366722041 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3366722041
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.2384599023
Short name T592
Test name
Test status
Simulation time 10159744237 ps
CPU time 13.94 seconds
Started May 07 12:53:29 PM PDT 24
Finished May 07 12:53:45 PM PDT 24
Peak memory 284716 kb
Host smart-529b7247-a51e-40e4-98bd-e307e264bb17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384599023 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.2384599023
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2390441651
Short name T514
Test name
Test status
Simulation time 10034193996 ps
CPU time 68.21 seconds
Started May 07 12:53:27 PM PDT 24
Finished May 07 12:54:37 PM PDT 24
Peak memory 454404 kb
Host smart-69740c2d-6922-4154-b5e3-14c6fd611e09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390441651 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2390441651
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.2995841611
Short name T1355
Test name
Test status
Simulation time 1476859816 ps
CPU time 2.63 seconds
Started May 07 12:53:29 PM PDT 24
Finished May 07 12:53:33 PM PDT 24
Peak memory 203904 kb
Host smart-19aedb0e-ec4d-40f5-98f8-414bf45d7ade
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995841611 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.2995841611
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.3156280899
Short name T546
Test name
Test status
Simulation time 6056830852 ps
CPU time 6.72 seconds
Started May 07 12:53:23 PM PDT 24
Finished May 07 12:53:31 PM PDT 24
Peak memory 212124 kb
Host smart-96ab527e-3dbd-4521-9aae-ea83a34e475c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156280899 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.3156280899
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.4076047948
Short name T646
Test name
Test status
Simulation time 21912015378 ps
CPU time 331.41 seconds
Started May 07 12:53:23 PM PDT 24
Finished May 07 12:58:56 PM PDT 24
Peak memory 3816404 kb
Host smart-dc4770a4-efab-46a0-8b15-6fd820e110bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076047948 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.4076047948
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.2132295379
Short name T883
Test name
Test status
Simulation time 798590863 ps
CPU time 11.78 seconds
Started May 07 12:53:30 PM PDT 24
Finished May 07 12:53:43 PM PDT 24
Peak memory 203868 kb
Host smart-c0971b1a-1bcd-4280-9343-a46ff9fd1da7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132295379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.2132295379
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.681162164
Short name T209
Test name
Test status
Simulation time 306525392 ps
CPU time 5.82 seconds
Started May 07 12:53:30 PM PDT 24
Finished May 07 12:53:37 PM PDT 24
Peak memory 203940 kb
Host smart-44e2102a-fd43-4d92-a431-e4a718c5dd84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681162164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_rd.681162164
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.3814377116
Short name T1014
Test name
Test status
Simulation time 51881161526 ps
CPU time 12.3 seconds
Started May 07 12:53:25 PM PDT 24
Finished May 07 12:53:38 PM PDT 24
Peak memory 327836 kb
Host smart-cb904dd6-31b9-46fe-8096-93fddcd63529
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814377116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.3814377116
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.548045484
Short name T263
Test name
Test status
Simulation time 1590821646 ps
CPU time 7.79 seconds
Started May 07 12:53:23 PM PDT 24
Finished May 07 12:53:32 PM PDT 24
Peak memory 203804 kb
Host smart-c4c401f8-a810-4b21-b22c-6976c3be77fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548045484 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_timeout.548045484
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.3261739031
Short name T794
Test name
Test status
Simulation time 30107935 ps
CPU time 0.61 seconds
Started May 07 12:53:42 PM PDT 24
Finished May 07 12:53:44 PM PDT 24
Peak memory 203788 kb
Host smart-65e0ae4a-2709-4055-9da4-6560948f28ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261739031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.3261739031
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.3298347244
Short name T732
Test name
Test status
Simulation time 122999979 ps
CPU time 1.18 seconds
Started May 07 12:53:28 PM PDT 24
Finished May 07 12:53:30 PM PDT 24
Peak memory 220308 kb
Host smart-7aa8e5ae-f70d-439e-b6fc-ebae14c80f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298347244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3298347244
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.2240558044
Short name T551
Test name
Test status
Simulation time 905847379 ps
CPU time 23.54 seconds
Started May 07 12:53:28 PM PDT 24
Finished May 07 12:53:53 PM PDT 24
Peak memory 290948 kb
Host smart-ef759148-8cc2-49f7-ac91-7521f0d58b83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240558044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.2240558044
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.2336474898
Short name T336
Test name
Test status
Simulation time 10838362808 ps
CPU time 119.95 seconds
Started May 07 12:53:27 PM PDT 24
Finished May 07 12:55:28 PM PDT 24
Peak memory 610312 kb
Host smart-dcf3d506-5ba1-4f6b-ae31-2c1bf6f72e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336474898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.2336474898
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.3264705372
Short name T1096
Test name
Test status
Simulation time 6110761375 ps
CPU time 97.65 seconds
Started May 07 12:53:29 PM PDT 24
Finished May 07 12:55:08 PM PDT 24
Peak memory 495180 kb
Host smart-d46fd4d7-2f7d-46ef-bf8c-7556358abdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264705372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.3264705372
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.219525709
Short name T531
Test name
Test status
Simulation time 119229420 ps
CPU time 1.03 seconds
Started May 07 12:53:27 PM PDT 24
Finished May 07 12:53:29 PM PDT 24
Peak memory 203896 kb
Host smart-4bd9d753-24e3-463b-8aa4-effbd607cb0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219525709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt
.219525709
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.1084831198
Short name T400
Test name
Test status
Simulation time 175345356 ps
CPU time 4.44 seconds
Started May 07 12:53:28 PM PDT 24
Finished May 07 12:53:34 PM PDT 24
Peak memory 234372 kb
Host smart-b3eaf615-d08c-4f81-8d50-8fd6d18a2edd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084831198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
1084831198
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.1196732052
Short name T977
Test name
Test status
Simulation time 12809603531 ps
CPU time 73.49 seconds
Started May 07 12:53:28 PM PDT 24
Finished May 07 12:54:43 PM PDT 24
Peak memory 999736 kb
Host smart-dd1745fd-e7e2-471b-b937-adfb83623e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196732052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1196732052
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.2752541672
Short name T412
Test name
Test status
Simulation time 2025887607 ps
CPU time 12.08 seconds
Started May 07 12:53:33 PM PDT 24
Finished May 07 12:53:46 PM PDT 24
Peak memory 203948 kb
Host smart-ddc6a558-20f6-4a20-844b-836faeb7607b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752541672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.2752541672
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.2838751797
Short name T222
Test name
Test status
Simulation time 5534036318 ps
CPU time 21.01 seconds
Started May 07 12:53:33 PM PDT 24
Finished May 07 12:53:56 PM PDT 24
Peak memory 326212 kb
Host smart-a38865ee-1b5e-4351-bb06-f4cb1b980608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838751797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.2838751797
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.2504582293
Short name T939
Test name
Test status
Simulation time 29247307 ps
CPU time 0.68 seconds
Started May 07 12:53:28 PM PDT 24
Finished May 07 12:53:30 PM PDT 24
Peak memory 203732 kb
Host smart-314811be-797b-431d-a8e1-cb17c79c7835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504582293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2504582293
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.481149011
Short name T572
Test name
Test status
Simulation time 2584304654 ps
CPU time 14.52 seconds
Started May 07 12:53:28 PM PDT 24
Finished May 07 12:53:44 PM PDT 24
Peak memory 258376 kb
Host smart-3fd1afb9-eb6a-4d6b-a666-247c4f8779d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481149011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.481149011
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.3923033788
Short name T386
Test name
Test status
Simulation time 1585423424 ps
CPU time 22.4 seconds
Started May 07 12:53:31 PM PDT 24
Finished May 07 12:53:55 PM PDT 24
Peak memory 349304 kb
Host smart-404ccfd2-0410-4984-a46a-c12fb9841748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923033788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.3923033788
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.2520845021
Short name T1052
Test name
Test status
Simulation time 8539367016 ps
CPU time 352.21 seconds
Started May 07 12:53:33 PM PDT 24
Finished May 07 12:59:27 PM PDT 24
Peak memory 2069936 kb
Host smart-e7d84ac8-36cd-41cc-b3a7-3fb6c5219ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520845021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.2520845021
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.2174847542
Short name T241
Test name
Test status
Simulation time 858465069 ps
CPU time 6.97 seconds
Started May 07 12:53:28 PM PDT 24
Finished May 07 12:53:36 PM PDT 24
Peak memory 215112 kb
Host smart-9e65d242-fd78-4834-a572-48c68a64c193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174847542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.2174847542
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.779707574
Short name T713
Test name
Test status
Simulation time 4164844137 ps
CPU time 2.98 seconds
Started May 07 12:53:34 PM PDT 24
Finished May 07 12:53:38 PM PDT 24
Peak memory 212404 kb
Host smart-e2451327-d428-4525-8a3f-346e1b2c3e87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779707574 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.779707574
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.2938267211
Short name T532
Test name
Test status
Simulation time 10207104959 ps
CPU time 15.66 seconds
Started May 07 12:53:39 PM PDT 24
Finished May 07 12:53:56 PM PDT 24
Peak memory 253984 kb
Host smart-35d1116d-884e-40fa-85c0-a43863f9fb12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938267211 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.2938267211
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.2703023995
Short name T258
Test name
Test status
Simulation time 10173676788 ps
CPU time 31.74 seconds
Started May 07 12:53:33 PM PDT 24
Finished May 07 12:54:07 PM PDT 24
Peak memory 396068 kb
Host smart-583273a9-faec-462b-aec1-f63114f34b9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703023995 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.2703023995
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.3409786124
Short name T1129
Test name
Test status
Simulation time 308084560 ps
CPU time 2.52 seconds
Started May 07 12:53:39 PM PDT 24
Finished May 07 12:53:42 PM PDT 24
Peak memory 203872 kb
Host smart-f31f0841-fbcf-403d-91f3-847bcdd810f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409786124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.3409786124
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.847579075
Short name T434
Test name
Test status
Simulation time 6515801860 ps
CPU time 7.76 seconds
Started May 07 12:53:34 PM PDT 24
Finished May 07 12:53:43 PM PDT 24
Peak memory 220136 kb
Host smart-2f68ed41-1fe9-42d8-810a-459c5f4d502b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847579075 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_intr_smoke.847579075
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.3754772848
Short name T804
Test name
Test status
Simulation time 20230312777 ps
CPU time 436.23 seconds
Started May 07 12:53:33 PM PDT 24
Finished May 07 01:00:51 PM PDT 24
Peak memory 4933468 kb
Host smart-c06c443f-d65d-4102-a92f-119c5bb1b363
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754772848 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.3754772848
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.1669344450
Short name T981
Test name
Test status
Simulation time 6168810665 ps
CPU time 20.7 seconds
Started May 07 12:53:33 PM PDT 24
Finished May 07 12:53:55 PM PDT 24
Peak memory 203956 kb
Host smart-5801b70a-380a-4fb7-aaa4-2a5b52859a46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669344450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.1669344450
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.2982509298
Short name T1010
Test name
Test status
Simulation time 1477753561 ps
CPU time 26.84 seconds
Started May 07 12:53:34 PM PDT 24
Finished May 07 12:54:02 PM PDT 24
Peak memory 227284 kb
Host smart-d0c8e722-3203-4337-806c-e8aee94aee61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982509298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.2982509298
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.2763844131
Short name T801
Test name
Test status
Simulation time 11535644151 ps
CPU time 6.85 seconds
Started May 07 12:53:35 PM PDT 24
Finished May 07 12:53:43 PM PDT 24
Peak memory 203912 kb
Host smart-6b1cbf26-68ba-4b26-9e27-5ad3c7a1eefc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763844131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.2763844131
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.336396919
Short name T21
Test name
Test status
Simulation time 4774995769 ps
CPU time 7.1 seconds
Started May 07 12:53:39 PM PDT 24
Finished May 07 12:53:47 PM PDT 24
Peak memory 220196 kb
Host smart-783da722-4cb1-46fe-a085-52e291f4a50f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336396919 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_timeout.336396919
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_unexp_stop.3433563358
Short name T1201
Test name
Test status
Simulation time 581613000 ps
CPU time 4.19 seconds
Started May 07 12:53:33 PM PDT 24
Finished May 07 12:53:39 PM PDT 24
Peak memory 203940 kb
Host smart-d33d5434-6ccd-4957-a163-4fc6370d665f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433563358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.i2c_target_unexp_stop.3433563358
Directory /workspace/9.i2c_target_unexp_stop/latest
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