Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	877056	1			T1	2		T2	26504		T3	2
all_values[1]	877056	1			T1	2		T2	26504		T3	2
all_values[2]	877056	1			T1	2		T2	26504		T3	2
all_values[3]	877056	1			T1	2		T2	26504		T3	2
all_values[4]	877056	1			T1	2		T2	26504		T3	2
all_values[5]	877056	1			T1	2		T2	26504		T3	2
all_values[6]	877056	1			T1	2		T2	26504		T3	2
all_values[7]	877056	1			T1	2		T2	26504		T3	2
all_values[8]	877056	1			T1	2		T2	26504		T3	2
all_values[9]	877056	1			T1	2		T2	26504		T3	2
all_values[10]	877056	1			T1	2		T2	26504		T3	2
all_values[11]	877056	1			T1	2		T2	26504		T3	2
all_values[12]	877056	1			T1	2		T2	26504		T3	2
all_values[13]	877056	1			T1	2		T2	26504		T3	2
all_values[14]	877056	1			T1	2		T2	26504		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9376716

1

T1

26

T2

273713

T3

26

auto[1]

3779124

1

T1

4

T2

123847

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11267792

1

T1

30

T2

397438

T3

30

auto[1]

1888048

1

T2

122

T80

154286

T63

211

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12] , all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	90039	1			T2	2749		T5	1		T10	1
all_values[0]	auto[0]	auto[1]	13780	1			T2	5		T80	351		T63	10
all_values[0]	auto[1]	auto[0]	662174	1			T1	2		T2	23746		T3	2
all_values[0]	auto[1]	auto[1]	111063	1			T2	4		T80	10662		T63	7
all_values[1]	auto[0]	auto[0]	744709	1			T1	2		T2	26497		T3	2
all_values[1]	auto[0]	auto[1]	131694	1			T2	3		T80	11006		T63	14
all_values[1]	auto[1]	auto[0]	396	1			T2	3		T98	48		T39	3
all_values[1]	auto[1]	auto[1]	257	1			T2	1		T80	6		T63	2
all_values[2]	auto[0]	auto[0]	746291	1			T1	2		T2	26495		T3	2
all_values[2]	auto[0]	auto[1]	130547	1			T2	6		T80	11006		T63	8
all_values[2]	auto[1]	auto[1]	218	1			T2	3		T80	7		T63	1
all_values[3]	auto[0]	auto[0]	755035	1			T1	2		T2	26496		T3	2
all_values[3]	auto[0]	auto[1]	121753	1			T2	4		T80	11006		T63	8
all_values[3]	auto[1]	auto[1]	268	1			T2	4		T80	6		T63	1
all_values[4]	auto[0]	auto[0]	745097	1			T1	2		T2	26497		T3	2
all_values[4]	auto[0]	auto[1]	131720	1			T2	5		T80	11009		T63	13
all_values[4]	auto[1]	auto[0]	22	1			T73	2		T74	2		T219	1
all_values[4]	auto[1]	auto[1]	217	1			T2	2		T80	5		T63	3
all_values[5]	auto[0]	auto[0]	746682	1			T1	2		T2	26495		T3	2
all_values[5]	auto[0]	auto[1]	130109	1			T2	3		T80	11003		T63	5
all_values[5]	auto[1]	auto[1]	265	1			T2	6		T80	10		T63	3
all_values[6]	auto[0]	auto[0]	166891	1			T1	2		T2	2799		T3	2
all_values[6]	auto[0]	auto[1]	25773	1			T2	2		T80	1308		T63	7
all_values[6]	auto[1]	auto[0]	604808	1			T2	23698		T10	1		T47	13
all_values[6]	auto[1]	auto[1]	79584	1			T2	5		T80	9704		T63	10
all_values[7]	auto[0]	auto[0]	718453	1			T1	2		T2	25912		T3	2
all_values[7]	auto[0]	auto[1]	127249	1			T2	6		T80	10878		T63	9
all_values[7]	auto[1]	auto[0]	26703	1			T2	584		T10	1		T47	67
all_values[7]	auto[1]	auto[1]	4651	1			T2	2		T80	136		T63	8
all_values[8]	auto[0]	auto[0]	133198	1			T1	2		T2	1440		T3	2
all_values[8]	auto[0]	auto[1]	23821	1			T2	4		T80	92		T63	7
all_values[8]	auto[1]	auto[0]	622840	1			T2	25056		T10	1		T47	36
all_values[8]	auto[1]	auto[1]	97197	1			T2	4		T80	10		T63	9
all_values[9]	auto[0]	auto[0]	155552	1			T1	2		T2	2262		T3	2
all_values[9]	auto[0]	auto[1]	27529	1			T2	2		T80	1292		T63	4
all_values[9]	auto[1]	auto[0]	589914	1			T2	24233		T4	1		T6	1
all_values[9]	auto[1]	auto[1]	104061	1			T2	7		T80	9722		T63	4
all_values[10]	auto[0]	auto[0]	750690	1			T1	2		T2	26495		T3	2
all_values[10]	auto[0]	auto[1]	126156	1			T2	3		T80	11008		T63	11
all_values[10]	auto[1]	auto[1]	210	1			T2	6		T80	6		T63	5
all_values[11]	auto[0]	auto[0]	2880	1			T2	32		T5	1		T10	1
all_values[11]	auto[0]	auto[1]	625	1			T2	5		T80	30		T63	8
all_values[11]	auto[1]	auto[0]	768823	1			T1	2		T2	26463		T3	2
all_values[11]	auto[1]	auto[1]	104728	1			T2	4		T80	10982		T63	8
all_values[12]	auto[0]	auto[0]	745119	1			T1	2		T2	26495		T3	2
all_values[12]	auto[0]	auto[1]	131730	1			T2	4		T80	11006		T63	12
all_values[12]	auto[1]	auto[1]	207	1			T2	5		T80	7		T63	3
all_values[13]	auto[0]	auto[0]	746313	1			T1	2		T2	26495		T3	2
all_values[13]	auto[0]	auto[1]	130485	1			T2	3		T80	11006		T63	9
all_values[13]	auto[1]	auto[1]	258	1			T2	6		T80	8		T63	6
all_values[14]	auto[0]	auto[0]	745163	1			T1	2		T2	26496		T3	2
all_values[14]	auto[0]	auto[1]	131633	1			T2	3		T80	11007		T63	10
all_values[14]	auto[1]	auto[1]	260	1			T2	5		T80	7		T63	6