Summary for Variable cp_acq_fifo_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_acq_fifo_size
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
not_empty |
125294958 |
1 |
|
|
T1 |
5783 |
|
T3 |
1650 |
|
T4 |
390526 |
empty |
83891113 |
1 |
|
|
T2 |
939771 |
|
T6 |
5728 |
|
T9 |
259 |
Summary for Variable cp_host_mode_stretch
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_host_mode_stretch
Excluded/Illegal bins
NAME | COUNT | STATUS |
unused |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
stretch |
51633797 |
1 |
|
|
T2 |
607579 |
|
T10 |
57313 |
|
T47 |
57278 |
Summary for Variable cp_target_scl_stretch_addr_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_target_scl_stretch_addr_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
addr_write_byte_stretch |
526806 |
1 |
|
|
T4 |
4018 |
|
T17 |
10138 |
|
T18 |
1451 |
Summary for Variable cp_tx_fifo_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_tx_fifo_size
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
not_empty |
44689533 |
1 |
|
|
T1 |
4153 |
|
T3 |
1362 |
|
T6 |
123092 |
empty |
164496573 |
1 |
|
|
T1 |
1630 |
|
T2 |
939771 |
|
T3 |
288 |
Summary for Cross cp_target_scl_stretch_read
Samples crossed: cp_acq_fifo_size cp_tx_fifo_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
User Defined Cross Bins |
2 |
0 |
2 |
100.00 |
|
Automatically Generated Cross Bins for cp_target_scl_stretch_read
Bins
cp_acq_fifo_size | cp_tx_fifo_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
empty |
not_empty |
54 |
1 |
|
|
T193 |
7 |
|
T249 |
47 |
|
- |
- |
empty |
empty |
1309323 |
1 |
|
|
T2 |
22 |
|
T6 |
5728 |
|
T9 |
259 |
User Defined Cross Bins for cp_target_scl_stretch_read
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
read_byte_stretch |
464781 |
1 |
|
|
T1 |
727 |
|
T3 |
288 |
|
T6 |
613 |
scl_stretch_read_request |
44902339 |
1 |
|
|
T1 |
4880 |
|
T3 |
1650 |
|
T6 |
123705 |