Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	877056	1			T1	2		T2	26504		T3	2
all_pins[1]	877056	1			T1	2		T2	26504		T3	2
all_pins[2]	877056	1			T1	2		T2	26504		T3	2
all_pins[3]	877056	1			T1	2		T2	26504		T3	2
all_pins[4]	877056	1			T1	2		T2	26504		T3	2
all_pins[5]	877056	1			T1	2		T2	26504		T3	2
all_pins[6]	877056	1			T1	2		T2	26504		T3	2
all_pins[7]	877056	1			T1	2		T2	26504		T3	2
all_pins[8]	877056	1			T1	2		T2	26504		T3	2
all_pins[9]	877056	1			T1	2		T2	26504		T3	2
all_pins[10]	877056	1			T1	2		T2	26504		T3	2
all_pins[11]	877056	1			T1	2		T2	26504		T3	2
all_pins[12]	877056	1			T1	2		T2	26504		T3	2
all_pins[13]	877056	1			T1	2		T2	26504		T3	2
all_pins[14]	877056	1			T1	2		T2	26504		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9381372	1			T1	26		T2	273632		T3	26
values[0x1]	3774468	1			T1	4		T2	123928		T3	4
transitions[0x0=>0x1]	3037397	1			T1	4		T2	98651		T3	4
transitions[0x1=>0x0]	3036370	1			T1	3		T2	98651		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	106777	1			T2	2761		T5	1		T10	1
all_pins[0]	values[0x1]	770279	1			T1	2		T2	23743		T3	2
all_pins[0]	transitions[0x0=>0x1]	769743	1			T1	2		T2	23738		T3	2
all_pins[0]	transitions[0x1=>0x0]	74	1			T2	1		T80	4		T39	1
all_pins[1]	values[0x0]	876446	1			T1	2		T2	26498		T3	2
all_pins[1]	values[0x1]	610	1			T2	6		T98	62		T80	4
all_pins[1]	transitions[0x0=>0x1]	582	1			T2	5		T98	62		T80	4
all_pins[1]	transitions[0x1=>0x0]	80	1			T80	1		T63	1		T39	1
all_pins[2]	values[0x0]	876948	1			T1	2		T2	26503		T3	2
all_pins[2]	values[0x1]	108	1			T2	1		T80	1		T63	1
all_pins[2]	transitions[0x0=>0x1]	84	1			T2	1		T80	1		T63	1
all_pins[2]	transitions[0x1=>0x0]	117	1			T80	2		T39	3		T99	2
all_pins[3]	values[0x0]	876915	1			T1	2		T2	26504		T3	2
all_pins[3]	values[0x1]	141	1			T80	2		T39	3		T99	2
all_pins[3]	transitions[0x0=>0x1]	116	1			T80	2		T39	3		T99	1
all_pins[3]	transitions[0x1=>0x0]	101	1			T2	1		T63	1		T73	2
all_pins[4]	values[0x0]	876930	1			T1	2		T2	26503		T3	2
all_pins[4]	values[0x1]	126	1			T2	1		T63	1		T73	2
all_pins[4]	transitions[0x0=>0x1]	101	1			T63	1		T73	2		T99	1
all_pins[4]	transitions[0x1=>0x0]	102	1			T2	1		T80	7		T63	2
all_pins[5]	values[0x0]	876929	1			T1	2		T2	26502		T3	2
all_pins[5]	values[0x1]	127	1			T2	2		T80	7		T63	2
all_pins[5]	transitions[0x0=>0x1]	94	1			T2	1		T80	7		T82	3
all_pins[5]	transitions[0x1=>0x0]	684059	1			T2	23700		T10	1		T47	13
all_pins[6]	values[0x0]	192964	1			T1	2		T2	2803		T3	2
all_pins[6]	values[0x1]	684092	1			T2	23701		T10	1		T47	13
all_pins[6]	transitions[0x0=>0x1]	663112	1			T2	23205		T47	11		T48	1
all_pins[6]	transitions[0x1=>0x0]	13585	1			T2	207		T47	73		T37	14
all_pins[7]	values[0x0]	842491	1			T1	2		T2	25801		T3	2
all_pins[7]	values[0x1]	34565	1			T2	703		T10	1		T47	75
all_pins[7]	transitions[0x0=>0x1]	11077	1			T2	166		T47	67		T37	13
all_pins[7]	transitions[0x1=>0x0]	696306	1			T2	24520		T47	30		T37	5
all_pins[8]	values[0x0]	157262	1			T1	2		T2	1447		T3	2
all_pins[8]	values[0x1]	719794	1			T2	25057		T10	1		T47	38
all_pins[8]	transitions[0x0=>0x1]	28065	1			T2	826		T47	33		T37	6
all_pins[8]	transitions[0x1=>0x0]	2165	1			T2	8		T4	1		T6	1
all_pins[9]	values[0x0]	183162	1			T1	2		T2	2265		T3	2
all_pins[9]	values[0x1]	693894	1			T2	24239		T4	1		T6	1
all_pins[9]	transitions[0x0=>0x1]	693872	1			T2	24237		T4	1		T6	1
all_pins[9]	transitions[0x1=>0x0]	78	1			T80	5		T63	2		T39	1
all_pins[10]	values[0x0]	876956	1			T1	2		T2	26502		T3	2
all_pins[10]	values[0x1]	100	1			T2	2		T80	5		T63	2
all_pins[10]	transitions[0x0=>0x1]	73	1			T2	2		T80	5		T39	1
all_pins[10]	transitions[0x1=>0x0]	870225	1			T1	2		T2	26465		T3	2
all_pins[11]	values[0x0]	6804	1			T2	39		T5	1		T10	1
all_pins[11]	values[0x1]	870252	1			T1	2		T2	26465		T3	2
all_pins[11]	transitions[0x0=>0x1]	870221	1			T1	2		T2	26464		T3	2
all_pins[11]	transitions[0x1=>0x0]	78	1			T2	2		T80	2		T64	1
all_pins[12]	values[0x0]	876947	1			T1	2		T2	26501		T3	2
all_pins[12]	values[0x1]	109	1			T2	3		T80	3		T99	1
all_pins[12]	transitions[0x0=>0x1]	83	1			T2	2		T80	2		T64	2
all_pins[12]	transitions[0x1=>0x0]	109	1			T2	3		T80	3		T63	2
all_pins[13]	values[0x0]	876921	1			T1	2		T2	26500		T3	2
all_pins[13]	values[0x1]	135	1			T2	4		T80	4		T63	2
all_pins[13]	transitions[0x0=>0x1]	97	1			T2	3		T80	3		T63	2
all_pins[13]	transitions[0x1=>0x0]	98	1			T80	5		T63	3		T101	1
all_pins[14]	values[0x0]	876920	1			T1	2		T2	26503		T3	2
all_pins[14]	values[0x1]	136	1			T2	1		T80	6		T63	3
all_pins[14]	transitions[0x0=>0x1]	77	1			T2	1		T80	4		T63	2
all_pins[14]	transitions[0x1=>0x0]	769193	1			T1	1		T2	23743		T3	1