Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	532	1			T2	7		T80	14		T63	8
all_values[1]	532	1			T2	7		T80	14		T63	8
all_values[2]	532	1			T2	7		T80	14		T63	8
all_values[3]	532	1			T2	7		T80	14		T63	8
all_values[4]	532	1			T2	7		T80	14		T63	8
all_values[5]	532	1			T2	7		T80	14		T63	8
all_values[6]	532	1			T2	7		T80	14		T63	8
all_values[7]	532	1			T2	7		T80	14		T63	8
all_values[8]	532	1			T2	7		T80	14		T63	8
all_values[9]	532	1			T2	7		T80	14		T63	8
all_values[10]	532	1			T2	7		T80	14		T63	8
all_values[11]	532	1			T2	7		T80	14		T63	8
all_values[12]	532	1			T2	7		T80	14		T63	8
all_values[13]	532	1			T2	7		T80	14		T63	8
all_values[14]	532	1			T2	7		T80	14		T63	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4213

1

T2

55

T80

97

T63

68

auto[1]

3767

1

T2

50

T80

113

T63

52

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1302

1

T2

13

T80

20

T63

28

auto[1]

6678

1

T2

92

T80

190

T63

92

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4762

1

T2

52

T80

122

T63

79

auto[1]

3218

1

T2

53

T80

88

T63

41

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	43	1			T64	2		T82	1		T243	1
all_values[0]	auto[0]	auto[0]	auto[1]	111	1			T2	1		T80	3		T63	6
all_values[0]	auto[0]	auto[1]	auto[0]	30	1			T80	1		T64	1		T82	1
all_values[0]	auto[0]	auto[1]	auto[1]	128	1			T2	2		T80	7		T64	1
all_values[0]	auto[1]	auto[0]	auto[1]	103	1			T2	2		T80	1		T63	1
all_values[0]	auto[1]	auto[1]	auto[1]	117	1			T2	2		T80	2		T63	1
all_values[1]	auto[0]	auto[0]	auto[0]	53	1			T2	4		T80	2		T39	2
all_values[1]	auto[0]	auto[0]	auto[1]	115	1			T80	1		T63	2		T99	1
all_values[1]	auto[0]	auto[1]	auto[0]	27	1			T2	1		T63	1		T99	1
all_values[1]	auto[0]	auto[1]	auto[1]	111	1			T2	1		T80	5		T63	3
all_values[1]	auto[1]	auto[0]	auto[1]	124	1			T80	2		T63	1		T99	2
all_values[1]	auto[1]	auto[1]	auto[1]	102	1			T2	1		T80	4		T63	1
all_values[2]	auto[0]	auto[0]	auto[0]	50	1			T80	1		T63	3		T82	1
all_values[2]	auto[0]	auto[0]	auto[1]	112	1			T2	3		T80	4		T63	2
all_values[2]	auto[0]	auto[1]	auto[0]	27	1			T63	1		T101	1		T218	1
all_values[2]	auto[0]	auto[1]	auto[1]	125	1			T2	1		T80	2		T63	1
all_values[2]	auto[1]	auto[0]	auto[1]	119	1			T2	2		T80	6		T39	1
all_values[2]	auto[1]	auto[1]	auto[1]	99	1			T2	1		T80	1		T63	1
all_values[3]	auto[0]	auto[0]	auto[0]	57	1			T2	1		T63	1		T82	1
all_values[3]	auto[0]	auto[0]	auto[1]	114	1			T2	1		T80	4		T63	3
all_values[3]	auto[0]	auto[1]	auto[0]	33	1			T80	2		T63	3		T64	1
all_values[3]	auto[0]	auto[1]	auto[1]	119	1			T2	1		T80	2		T39	2
all_values[3]	auto[1]	auto[0]	auto[1]	113	1			T2	3		T80	2		T63	1
all_values[3]	auto[1]	auto[1]	auto[1]	96	1			T2	1		T80	4		T99	1
all_values[4]	auto[0]	auto[0]	auto[0]	58	1			T2	2		T63	1		T64	2
all_values[4]	auto[0]	auto[0]	auto[1]	122	1			T2	1		T80	2		T63	1
all_values[4]	auto[0]	auto[1]	auto[0]	31	1			T64	3		T101	1		T244	3
all_values[4]	auto[0]	auto[1]	auto[1]	104	1			T2	2		T80	7		T63	3
all_values[4]	auto[1]	auto[0]	auto[1]	123	1			T2	1		T80	5		T63	2
all_values[4]	auto[1]	auto[1]	auto[1]	94	1			T2	1		T63	1		T39	1
all_values[5]	auto[0]	auto[0]	auto[0]	36	1			T80	1		T63	2		T82	1
all_values[5]	auto[0]	auto[0]	auto[1]	112	1			T2	2		T39	2		T99	2
all_values[5]	auto[0]	auto[1]	auto[0]	49	1			T63	3		T39	1		T99	1
all_values[5]	auto[0]	auto[1]	auto[1]	111	1			T2	1		T80	2		T63	1
all_values[5]	auto[1]	auto[0]	auto[1]	123	1			T2	2		T80	4		T64	1
all_values[5]	auto[1]	auto[1]	auto[1]	101	1			T2	2		T80	7		T63	2
all_values[6]	auto[0]	auto[0]	auto[0]	46	1			T64	1		T82	1		T52	2
all_values[6]	auto[0]	auto[0]	auto[1]	130	1			T2	1		T80	5		T63	1
all_values[6]	auto[0]	auto[1]	auto[0]	35	1			T2	2		T80	2		T64	1
all_values[6]	auto[0]	auto[1]	auto[1]	97	1			T2	1		T80	4		T63	2
all_values[6]	auto[1]	auto[0]	auto[1]	111	1			T2	1		T80	3		T63	3
all_values[6]	auto[1]	auto[1]	auto[1]	113	1			T2	2		T63	2		T39	2
all_values[7]	auto[0]	auto[0]	auto[0]	51	1			T82	1		T52	2		T243	4
all_values[7]	auto[0]	auto[0]	auto[1]	117	1			T2	4		T80	2		T63	3
all_values[7]	auto[0]	auto[1]	auto[0]	42	1			T2	1		T101	3		T218	1
all_values[7]	auto[0]	auto[1]	auto[1]	119	1			T2	1		T80	7		T63	1
all_values[7]	auto[1]	auto[0]	auto[1]	104	1			T80	4		T63	2		T39	1
all_values[7]	auto[1]	auto[1]	auto[1]	99	1			T2	1		T80	1		T63	2
all_values[8]	auto[0]	auto[0]	auto[0]	51	1			T80	4		T218	4		T245	1
all_values[8]	auto[0]	auto[0]	auto[1]	108	1			T2	2		T80	1		T63	3
all_values[8]	auto[0]	auto[1]	auto[0]	54	1			T2	1		T80	4		T63	1
all_values[8]	auto[0]	auto[1]	auto[1]	119	1			T2	1		T80	1		T63	2
all_values[8]	auto[1]	auto[0]	auto[1]	99	1			T2	2		T80	2		T63	1
all_values[8]	auto[1]	auto[1]	auto[1]	101	1			T2	1		T80	2		T63	1
all_values[9]	auto[0]	auto[0]	auto[0]	41	1			T63	1		T82	1		T243	3
all_values[9]	auto[0]	auto[0]	auto[1]	110	1			T80	3		T63	2		T39	1
all_values[9]	auto[0]	auto[1]	auto[0]	30	1			T63	4		T243	1		T101	1
all_values[9]	auto[0]	auto[1]	auto[1]	138	1			T2	2		T80	4		T39	1
all_values[9]	auto[1]	auto[0]	auto[1]	109	1			T2	2		T80	4		T63	1
all_values[9]	auto[1]	auto[1]	auto[1]	104	1			T2	3		T80	3		T99	2
all_values[10]	auto[0]	auto[0]	auto[0]	48	1			T63	1		T99	1		T82	2
all_values[10]	auto[0]	auto[0]	auto[1]	118	1			T2	1		T80	4		T63	1
all_values[10]	auto[0]	auto[1]	auto[0]	47	1			T99	3		T64	1		T101	1
all_values[10]	auto[0]	auto[1]	auto[1]	109	1			T80	4		T63	1		T39	1
all_values[10]	auto[1]	auto[0]	auto[1]	125	1			T2	4		T80	1		T63	3
all_values[10]	auto[1]	auto[1]	auto[1]	85	1			T2	2		T80	5		T63	2
all_values[11]	auto[0]	auto[0]	auto[0]	39	1			T80	1		T63	1		T82	1
all_values[11]	auto[0]	auto[0]	auto[1]	111	1			T2	1		T80	1		T63	1
all_values[11]	auto[0]	auto[1]	auto[0]	44	1			T80	1		T99	2		T52	4
all_values[11]	auto[0]	auto[1]	auto[1]	121	1			T2	2		T80	5		T63	3
all_values[11]	auto[1]	auto[0]	auto[1]	123	1			T2	2		T80	3		T63	1
all_values[11]	auto[1]	auto[1]	auto[1]	94	1			T2	2		T80	3		T63	2
all_values[12]	auto[0]	auto[0]	auto[0]	63	1			T80	1		T63	1		T39	4
all_values[12]	auto[0]	auto[0]	auto[1]	138	1			T2	1		T80	2		T63	3
all_values[12]	auto[0]	auto[1]	auto[0]	25	1			T63	1		T99	1		T52	1
all_values[12]	auto[0]	auto[1]	auto[1]	99	1			T2	1		T80	4		T99	2
all_values[12]	auto[1]	auto[0]	auto[1]	112	1			T2	2		T80	4		T63	3
all_values[12]	auto[1]	auto[1]	auto[1]	95	1			T2	3		T80	3		T64	2
all_values[13]	auto[0]	auto[0]	auto[0]	64	1			T63	2		T39	1		T243	1
all_values[13]	auto[0]	auto[0]	auto[1]	121	1			T80	5		T63	1		T39	1
all_values[13]	auto[0]	auto[1]	auto[0]	30	1			T101	2		T244	3		T107	1
all_values[13]	auto[0]	auto[1]	auto[1]	102	1			T2	2		T80	3		T63	1
all_values[13]	auto[1]	auto[0]	auto[1]	105	1			T2	1		T80	2		T63	3
all_values[13]	auto[1]	auto[1]	auto[1]	110	1			T2	4		T80	4		T63	1
all_values[14]	auto[0]	auto[0]	auto[0]	55	1			T2	1		T52	1		T243	3
all_values[14]	auto[0]	auto[0]	auto[1]	114	1			T2	2		T80	5		T63	3
all_values[14]	auto[0]	auto[1]	auto[0]	43	1			T63	1		T39	4		T99	2
all_values[14]	auto[0]	auto[1]	auto[1]	105	1			T2	1		T80	3		T63	1
all_values[14]	auto[1]	auto[0]	auto[1]	112	1			T2	3		T80	2		T63	1
all_values[14]	auto[1]	auto[1]	auto[1]	103	1			T80	4		T63	2		T99	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal