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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.38 97.15 90.91 97.67 83.58 94.42 98.45 91.47


Total test records in report: 1475
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T1307 /workspace/coverage/default/12.i2c_host_stress_all.324544523 May 09 12:47:36 PM PDT 24 May 09 12:59:03 PM PDT 24 7018877974 ps
T1308 /workspace/coverage/default/37.i2c_target_intr_stress_wr.3906238558 May 09 12:51:03 PM PDT 24 May 09 12:51:23 PM PDT 24 8470832204 ps
T1309 /workspace/coverage/default/16.i2c_host_fifo_watermark.2426270236 May 09 12:48:03 PM PDT 24 May 09 12:51:32 PM PDT 24 3050056263 ps
T1310 /workspace/coverage/default/30.i2c_host_override.2308918695 May 09 12:50:03 PM PDT 24 May 09 12:50:06 PM PDT 24 93915982 ps
T1311 /workspace/coverage/default/8.i2c_host_error_intr.103454860 May 09 12:46:50 PM PDT 24 May 09 12:46:54 PM PDT 24 160417803 ps
T1312 /workspace/coverage/default/47.i2c_target_smoke.967511464 May 09 12:52:24 PM PDT 24 May 09 12:52:58 PM PDT 24 1627027128 ps
T1313 /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2803472617 May 09 12:48:29 PM PDT 24 May 09 12:48:50 PM PDT 24 505722168 ps
T1314 /workspace/coverage/default/20.i2c_target_intr_smoke.646187261 May 09 12:48:44 PM PDT 24 May 09 12:48:49 PM PDT 24 2265581387 ps
T1315 /workspace/coverage/default/4.i2c_target_stress_rd.3210428624 May 09 12:46:21 PM PDT 24 May 09 12:46:35 PM PDT 24 655972717 ps
T1316 /workspace/coverage/default/37.i2c_host_fifo_watermark.4294905733 May 09 12:51:01 PM PDT 24 May 09 12:52:37 PM PDT 24 7469687526 ps
T1317 /workspace/coverage/default/46.i2c_host_fifo_full.863871019 May 09 12:52:02 PM PDT 24 May 09 12:52:35 PM PDT 24 18012310534 ps
T1318 /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1658361105 May 09 12:48:56 PM PDT 24 May 09 12:50:00 PM PDT 24 10141971047 ps
T1319 /workspace/coverage/default/30.i2c_target_hrst.471124190 May 09 12:50:11 PM PDT 24 May 09 12:50:16 PM PDT 24 450154501 ps
T1320 /workspace/coverage/default/0.i2c_host_may_nack.1844659366 May 09 12:45:38 PM PDT 24 May 09 12:45:46 PM PDT 24 364111930 ps
T1321 /workspace/coverage/default/18.i2c_host_stress_all.4278869535 May 09 12:48:25 PM PDT 24 May 09 01:06:27 PM PDT 24 27096130095 ps
T1322 /workspace/coverage/default/23.i2c_target_stress_wr.2278469388 May 09 12:49:07 PM PDT 24 May 09 12:55:59 PM PDT 24 49287948106 ps
T1323 /workspace/coverage/default/9.i2c_host_fifo_full.2438582043 May 09 12:47:12 PM PDT 24 May 09 12:47:39 PM PDT 24 1090894943 ps
T1324 /workspace/coverage/default/43.i2c_host_fifo_full.3728344429 May 09 12:51:46 PM PDT 24 May 09 12:53:00 PM PDT 24 1096098325 ps
T1325 /workspace/coverage/default/34.i2c_target_stretch.3672863435 May 09 12:50:37 PM PDT 24 May 09 01:24:39 PM PDT 24 36685873619 ps
T1326 /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.2984301734 May 09 12:51:54 PM PDT 24 May 09 12:52:02 PM PDT 24 232066906 ps
T1327 /workspace/coverage/default/9.i2c_host_stretch_timeout.241494268 May 09 12:47:10 PM PDT 24 May 09 12:47:22 PM PDT 24 1108777986 ps
T1328 /workspace/coverage/default/45.i2c_target_timeout.1295297521 May 09 12:52:05 PM PDT 24 May 09 12:52:15 PM PDT 24 1064541452 ps
T1329 /workspace/coverage/default/33.i2c_host_may_nack.2034172608 May 09 12:50:29 PM PDT 24 May 09 12:50:37 PM PDT 24 1939663032 ps
T1330 /workspace/coverage/default/39.i2c_target_bad_addr.3920976628 May 09 12:51:16 PM PDT 24 May 09 12:51:23 PM PDT 24 5384254974 ps
T1331 /workspace/coverage/default/6.i2c_target_timeout.3456188247 May 09 12:46:39 PM PDT 24 May 09 12:46:47 PM PDT 24 1342297009 ps
T1332 /workspace/coverage/default/2.i2c_target_intr_smoke.2779522021 May 09 12:45:53 PM PDT 24 May 09 12:46:01 PM PDT 24 12924107790 ps
T1333 /workspace/coverage/default/33.i2c_host_override.2543578186 May 09 12:50:17 PM PDT 24 May 09 12:50:19 PM PDT 24 27734727 ps
T1334 /workspace/coverage/default/9.i2c_target_hrst.1276633203 May 09 12:47:10 PM PDT 24 May 09 12:47:14 PM PDT 24 3487086052 ps
T1335 /workspace/coverage/default/21.i2c_target_smoke.344088070 May 09 12:48:56 PM PDT 24 May 09 12:49:15 PM PDT 24 4730438957 ps
T1336 /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.3063366433 May 09 12:47:24 PM PDT 24 May 09 12:47:27 PM PDT 24 418964237 ps
T1337 /workspace/coverage/default/17.i2c_host_mode_toggle.2832268571 May 09 12:48:29 PM PDT 24 May 09 12:48:53 PM PDT 24 6436999756 ps
T1338 /workspace/coverage/default/5.i2c_host_stress_all.694801103 May 09 12:46:34 PM PDT 24 May 09 01:08:32 PM PDT 24 314429034420 ps
T1339 /workspace/coverage/default/6.i2c_host_fifo_reset_rx.1219292247 May 09 12:46:36 PM PDT 24 May 09 12:46:42 PM PDT 24 610876498 ps
T1340 /workspace/coverage/default/38.i2c_target_fifo_reset_tx.1263353218 May 09 12:51:15 PM PDT 24 May 09 12:51:59 PM PDT 24 10167995953 ps
T1341 /workspace/coverage/default/18.i2c_target_stress_wr.47598613 May 09 12:48:23 PM PDT 24 May 09 01:11:32 PM PDT 24 52735752636 ps
T1342 /workspace/coverage/default/30.i2c_host_error_intr.420538906 May 09 12:50:00 PM PDT 24 May 09 12:50:04 PM PDT 24 364577696 ps
T1343 /workspace/coverage/default/24.i2c_host_fifo_reset_rx.1737333297 May 09 12:49:18 PM PDT 24 May 09 12:49:26 PM PDT 24 125256001 ps
T1344 /workspace/coverage/default/8.i2c_target_fifo_reset_tx.3076246890 May 09 12:46:59 PM PDT 24 May 09 12:48:03 PM PDT 24 10051731104 ps
T1345 /workspace/coverage/default/26.i2c_target_bad_addr.2464757416 May 09 12:49:38 PM PDT 24 May 09 12:49:44 PM PDT 24 680195621 ps
T1346 /workspace/coverage/default/20.i2c_alert_test.1790207616 May 09 12:48:44 PM PDT 24 May 09 12:48:46 PM PDT 24 89268459 ps
T1347 /workspace/coverage/default/4.i2c_target_stretch.2829142485 May 09 12:46:22 PM PDT 24 May 09 12:47:22 PM PDT 24 2769181807 ps
T1348 /workspace/coverage/default/27.i2c_host_smoke.2143889641 May 09 12:49:37 PM PDT 24 May 09 12:50:28 PM PDT 24 3887785938 ps
T1349 /workspace/coverage/default/49.i2c_target_stress_rd.2291550701 May 09 12:52:32 PM PDT 24 May 09 12:52:42 PM PDT 24 6962459551 ps
T1350 /workspace/coverage/default/22.i2c_target_intr_smoke.1419593160 May 09 12:49:05 PM PDT 24 May 09 12:49:14 PM PDT 24 5409491492 ps
T1351 /workspace/coverage/default/8.i2c_host_fifo_watermark.2415725698 May 09 12:46:57 PM PDT 24 May 09 12:49:10 PM PDT 24 2108737160 ps
T1352 /workspace/coverage/default/18.i2c_host_smoke.1698140744 May 09 12:48:27 PM PDT 24 May 09 12:48:55 PM PDT 24 2465201162 ps
T75 /workspace/coverage/default/43.i2c_host_perf.1424372959 May 09 12:51:44 PM PDT 24 May 09 12:52:22 PM PDT 24 23449733764 ps
T1353 /workspace/coverage/default/43.i2c_target_fifo_reset_tx.61355717 May 09 12:51:44 PM PDT 24 May 09 12:52:02 PM PDT 24 10179448512 ps
T1354 /workspace/coverage/default/0.i2c_host_mode_toggle.4196520238 May 09 12:45:42 PM PDT 24 May 09 12:46:03 PM PDT 24 1248915511 ps
T1355 /workspace/coverage/default/25.i2c_target_stress_wr.2252052472 May 09 12:49:29 PM PDT 24 May 09 12:49:58 PM PDT 24 28547055351 ps
T1356 /workspace/coverage/default/42.i2c_target_smoke.2481336859 May 09 12:51:31 PM PDT 24 May 09 12:52:13 PM PDT 24 1032538468 ps
T1357 /workspace/coverage/default/45.i2c_target_hrst.817997355 May 09 12:52:05 PM PDT 24 May 09 12:52:10 PM PDT 24 936103711 ps
T1358 /workspace/coverage/default/7.i2c_host_may_nack.4169348382 May 09 12:46:51 PM PDT 24 May 09 12:46:59 PM PDT 24 1960744193 ps
T1359 /workspace/coverage/default/0.i2c_target_fifo_reset_tx.555751731 May 09 12:45:25 PM PDT 24 May 09 12:46:52 PM PDT 24 10053243281 ps
T1360 /workspace/coverage/default/27.i2c_target_hrst.3751470156 May 09 12:49:41 PM PDT 24 May 09 12:49:45 PM PDT 24 1411048792 ps
T20 /workspace/coverage/default/1.i2c_target_glitch.819813559 May 09 12:45:41 PM PDT 24 May 09 12:45:56 PM PDT 24 2609562652 ps
T1361 /workspace/coverage/default/46.i2c_host_perf.3402778996 May 09 12:52:04 PM PDT 24 May 09 12:52:58 PM PDT 24 6401973412 ps
T1362 /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.1022623913 May 09 12:49:22 PM PDT 24 May 09 12:49:28 PM PDT 24 110328517 ps
T1363 /workspace/coverage/default/23.i2c_host_error_intr.3362733502 May 09 12:49:09 PM PDT 24 May 09 12:49:13 PM PDT 24 126846214 ps
T1364 /workspace/coverage/default/39.i2c_host_fifo_full.260022156 May 09 12:51:17 PM PDT 24 May 09 12:52:32 PM PDT 24 26839259160 ps
T134 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3765230596 May 09 12:38:10 PM PDT 24 May 09 12:38:29 PM PDT 24 62215936 ps
T87 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3147217809 May 09 12:37:52 PM PDT 24 May 09 12:38:04 PM PDT 24 153063623 ps
T135 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.887226322 May 09 12:38:10 PM PDT 24 May 09 12:38:29 PM PDT 24 16109230 ps
T154 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.4287662050 May 09 12:37:59 PM PDT 24 May 09 12:38:16 PM PDT 24 72367739 ps
T155 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3725701956 May 09 12:37:56 PM PDT 24 May 09 12:38:12 PM PDT 24 64537288 ps
T1365 /workspace/coverage/cover_reg_top/28.i2c_intr_test.3241927205 May 09 12:38:05 PM PDT 24 May 09 12:38:23 PM PDT 24 25311186 ps
T169 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2958469088 May 09 12:37:56 PM PDT 24 May 09 12:38:11 PM PDT 24 39840511 ps
T170 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3314315008 May 09 12:38:00 PM PDT 24 May 09 12:38:17 PM PDT 24 329697294 ps
T173 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4275197089 May 09 12:38:05 PM PDT 24 May 09 12:38:23 PM PDT 24 1001353109 ps
T1366 /workspace/coverage/cover_reg_top/43.i2c_intr_test.2647167106 May 09 12:38:13 PM PDT 24 May 09 12:38:32 PM PDT 24 30746800 ps
T1367 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2086334031 May 09 12:37:48 PM PDT 24 May 09 12:37:58 PM PDT 24 19079448 ps
T88 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.708866769 May 09 12:37:52 PM PDT 24 May 09 12:38:04 PM PDT 24 130640470 ps
T171 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1545253832 May 09 12:37:51 PM PDT 24 May 09 12:38:04 PM PDT 24 45623876 ps
T186 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2913562554 May 09 12:38:05 PM PDT 24 May 09 12:38:23 PM PDT 24 66948854 ps
T1368 /workspace/coverage/cover_reg_top/12.i2c_intr_test.123244472 May 09 12:38:03 PM PDT 24 May 09 12:38:19 PM PDT 24 31282203 ps
T180 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1768727003 May 09 12:38:03 PM PDT 24 May 09 12:38:21 PM PDT 24 297983025 ps
T1369 /workspace/coverage/cover_reg_top/23.i2c_intr_test.1890888003 May 09 12:38:13 PM PDT 24 May 09 12:38:32 PM PDT 24 50893509 ps
T172 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3893903657 May 09 12:38:02 PM PDT 24 May 09 12:38:20 PM PDT 24 191575589 ps
T187 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3000963487 May 09 12:37:56 PM PDT 24 May 09 12:38:10 PM PDT 24 89000219 ps
T1370 /workspace/coverage/cover_reg_top/2.i2c_intr_test.3078041715 May 09 12:38:03 PM PDT 24 May 09 12:38:20 PM PDT 24 35349466 ps
T89 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.4248643674 May 09 12:38:14 PM PDT 24 May 09 12:38:33 PM PDT 24 24812362 ps
T205 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3802133744 May 09 12:38:04 PM PDT 24 May 09 12:38:22 PM PDT 24 183147206 ps
T1371 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3628729086 May 09 12:37:58 PM PDT 24 May 09 12:38:16 PM PDT 24 275993090 ps
T1372 /workspace/coverage/cover_reg_top/15.i2c_intr_test.1856366360 May 09 12:38:06 PM PDT 24 May 09 12:38:23 PM PDT 24 24811760 ps
T90 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.412223955 May 09 12:38:19 PM PDT 24 May 09 12:38:38 PM PDT 24 79768527 ps
T188 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2327744525 May 09 12:38:08 PM PDT 24 May 09 12:38:27 PM PDT 24 35578859 ps
T1373 /workspace/coverage/cover_reg_top/10.i2c_intr_test.4266521874 May 09 12:38:04 PM PDT 24 May 09 12:38:21 PM PDT 24 15542765 ps
T1374 /workspace/coverage/cover_reg_top/29.i2c_intr_test.1912631868 May 09 12:38:08 PM PDT 24 May 09 12:38:26 PM PDT 24 35559249 ps
T91 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.727937057 May 09 12:38:08 PM PDT 24 May 09 12:38:27 PM PDT 24 41306765 ps
T1375 /workspace/coverage/cover_reg_top/40.i2c_intr_test.2342378894 May 09 12:38:12 PM PDT 24 May 09 12:38:31 PM PDT 24 16438055 ps
T184 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2465796122 May 09 12:38:05 PM PDT 24 May 09 12:38:23 PM PDT 24 510781764 ps
T206 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.758394601 May 09 12:38:05 PM PDT 24 May 09 12:38:23 PM PDT 24 53728217 ps
T1376 /workspace/coverage/cover_reg_top/7.i2c_intr_test.2820328205 May 09 12:38:04 PM PDT 24 May 09 12:38:21 PM PDT 24 49682961 ps
T1377 /workspace/coverage/cover_reg_top/11.i2c_intr_test.2509849388 May 09 12:38:09 PM PDT 24 May 09 12:38:28 PM PDT 24 25410513 ps
T1378 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2157516588 May 09 12:38:05 PM PDT 24 May 09 12:38:23 PM PDT 24 47401138 ps
T1379 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3850623163 May 09 12:38:10 PM PDT 24 May 09 12:38:29 PM PDT 24 131616821 ps
T1380 /workspace/coverage/cover_reg_top/13.i2c_intr_test.3208197504 May 09 12:38:06 PM PDT 24 May 09 12:38:24 PM PDT 24 34426427 ps
T1381 /workspace/coverage/cover_reg_top/6.i2c_intr_test.2567067421 May 09 12:37:51 PM PDT 24 May 09 12:38:03 PM PDT 24 77575246 ps
T1382 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3780562669 May 09 12:38:02 PM PDT 24 May 09 12:38:19 PM PDT 24 69594480 ps
T1383 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1425818555 May 09 12:38:05 PM PDT 24 May 09 12:38:24 PM PDT 24 66881636 ps
T1384 /workspace/coverage/cover_reg_top/37.i2c_intr_test.498030655 May 09 12:38:10 PM PDT 24 May 09 12:38:28 PM PDT 24 18616823 ps
T92 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1017802464 May 09 12:38:05 PM PDT 24 May 09 12:38:23 PM PDT 24 87655296 ps
T93 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2178658967 May 09 12:38:07 PM PDT 24 May 09 12:38:26 PM PDT 24 117526866 ps
T94 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.352900854 May 09 12:38:05 PM PDT 24 May 09 12:38:25 PM PDT 24 162394977 ps
T228 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1161193821 May 09 12:38:09 PM PDT 24 May 09 12:38:28 PM PDT 24 152035647 ps
T1385 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1545466451 May 09 12:38:08 PM PDT 24 May 09 12:38:28 PM PDT 24 91156012 ps
T174 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3076019257 May 09 12:37:56 PM PDT 24 May 09 12:38:11 PM PDT 24 276111393 ps
T207 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3635411101 May 09 12:38:08 PM PDT 24 May 09 12:38:26 PM PDT 24 19108107 ps
T175 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.271270942 May 09 12:38:06 PM PDT 24 May 09 12:38:25 PM PDT 24 162144548 ps
T95 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2071835916 May 09 12:38:02 PM PDT 24 May 09 12:38:20 PM PDT 24 155416229 ps
T1386 /workspace/coverage/cover_reg_top/4.i2c_intr_test.820081946 May 09 12:38:00 PM PDT 24 May 09 12:38:16 PM PDT 24 60989774 ps
T1387 /workspace/coverage/cover_reg_top/20.i2c_intr_test.2848602095 May 09 12:38:11 PM PDT 24 May 09 12:38:30 PM PDT 24 38572570 ps
T96 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.552420501 May 09 12:38:09 PM PDT 24 May 09 12:38:28 PM PDT 24 54264945 ps
T133 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3315076076 May 09 12:38:06 PM PDT 24 May 09 12:38:24 PM PDT 24 64467481 ps
T1388 /workspace/coverage/cover_reg_top/5.i2c_intr_test.806956802 May 09 12:37:56 PM PDT 24 May 09 12:38:11 PM PDT 24 19447797 ps
T1389 /workspace/coverage/cover_reg_top/49.i2c_intr_test.100071319 May 09 12:38:15 PM PDT 24 May 09 12:38:33 PM PDT 24 36469200 ps
T192 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2045942768 May 09 12:38:03 PM PDT 24 May 09 12:38:20 PM PDT 24 36715738 ps
T181 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1226112545 May 09 12:38:02 PM PDT 24 May 09 12:38:20 PM PDT 24 76575267 ps
T208 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.283506539 May 09 12:38:08 PM PDT 24 May 09 12:38:26 PM PDT 24 105810614 ps
T1390 /workspace/coverage/cover_reg_top/46.i2c_intr_test.2767849919 May 09 12:38:14 PM PDT 24 May 09 12:38:32 PM PDT 24 21204640 ps
T1391 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.434313691 May 09 12:38:04 PM PDT 24 May 09 12:38:22 PM PDT 24 71333867 ps
T1392 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.333330928 May 09 12:38:09 PM PDT 24 May 09 12:38:27 PM PDT 24 508812488 ps
T1393 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.471782653 May 09 12:38:07 PM PDT 24 May 09 12:38:24 PM PDT 24 24398094 ps
T209 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3080960251 May 09 12:38:03 PM PDT 24 May 09 12:38:21 PM PDT 24 28052186 ps
T1394 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1277763146 May 09 12:38:04 PM PDT 24 May 09 12:38:22 PM PDT 24 85968272 ps
T193 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3420291447 May 09 12:37:58 PM PDT 24 May 09 12:38:13 PM PDT 24 28958063 ps
T1395 /workspace/coverage/cover_reg_top/35.i2c_intr_test.3215214629 May 09 12:38:14 PM PDT 24 May 09 12:38:33 PM PDT 24 26696945 ps
T1396 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3768444719 May 09 12:38:03 PM PDT 24 May 09 12:38:21 PM PDT 24 182441408 ps
T201 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1705534463 May 09 12:38:03 PM PDT 24 May 09 12:38:25 PM PDT 24 655328047 ps
T178 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3272734303 May 09 12:38:29 PM PDT 24 May 09 12:38:47 PM PDT 24 83569481 ps
T1397 /workspace/coverage/cover_reg_top/41.i2c_intr_test.2747775672 May 09 12:38:09 PM PDT 24 May 09 12:38:28 PM PDT 24 59269605 ps
T1398 /workspace/coverage/cover_reg_top/18.i2c_intr_test.164491658 May 09 12:38:14 PM PDT 24 May 09 12:38:33 PM PDT 24 21719612 ps
T1399 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1358839394 May 09 12:38:01 PM PDT 24 May 09 12:38:17 PM PDT 24 157967873 ps
T1400 /workspace/coverage/cover_reg_top/32.i2c_intr_test.435808036 May 09 12:38:08 PM PDT 24 May 09 12:38:27 PM PDT 24 47186159 ps
T1401 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2911607433 May 09 12:38:14 PM PDT 24 May 09 12:38:34 PM PDT 24 1663635743 ps
T1402 /workspace/coverage/cover_reg_top/30.i2c_intr_test.1976369383 May 09 12:38:06 PM PDT 24 May 09 12:38:23 PM PDT 24 19428266 ps
T1403 /workspace/coverage/cover_reg_top/22.i2c_intr_test.1888340838 May 09 12:38:19 PM PDT 24 May 09 12:38:37 PM PDT 24 42188061 ps
T1404 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3926836842 May 09 12:38:09 PM PDT 24 May 09 12:38:27 PM PDT 24 104777546 ps
T1405 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1363027369 May 09 12:38:08 PM PDT 24 May 09 12:38:27 PM PDT 24 778309275 ps
T194 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2446729043 May 09 12:38:05 PM PDT 24 May 09 12:38:22 PM PDT 24 36887404 ps
T1406 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.412694697 May 09 12:37:48 PM PDT 24 May 09 12:37:58 PM PDT 24 172825544 ps
T1407 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.35561030 May 09 12:37:52 PM PDT 24 May 09 12:38:04 PM PDT 24 34674759 ps
T195 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1527216815 May 09 12:38:06 PM PDT 24 May 09 12:38:23 PM PDT 24 148056639 ps
T1408 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.325580758 May 09 12:38:06 PM PDT 24 May 09 12:38:23 PM PDT 24 45384377 ps
T1409 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.4159096556 May 09 12:37:56 PM PDT 24 May 09 12:38:11 PM PDT 24 58470973 ps
T196 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.476790416 May 09 12:38:19 PM PDT 24 May 09 12:38:37 PM PDT 24 30498389 ps
T1410 /workspace/coverage/cover_reg_top/16.i2c_intr_test.2594612158 May 09 12:38:07 PM PDT 24 May 09 12:38:25 PM PDT 24 74507113 ps
T1411 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.677274431 May 09 12:38:13 PM PDT 24 May 09 12:38:34 PM PDT 24 178104568 ps
T1412 /workspace/coverage/cover_reg_top/26.i2c_intr_test.711444029 May 09 12:38:06 PM PDT 24 May 09 12:38:24 PM PDT 24 15776798 ps
T1413 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1310165117 May 09 12:37:58 PM PDT 24 May 09 12:38:14 PM PDT 24 18971328 ps
T1414 /workspace/coverage/cover_reg_top/25.i2c_intr_test.2907244549 May 09 12:38:10 PM PDT 24 May 09 12:38:29 PM PDT 24 16891641 ps
T1415 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2016224981 May 09 12:37:55 PM PDT 24 May 09 12:38:09 PM PDT 24 51974812 ps
T1416 /workspace/coverage/cover_reg_top/19.i2c_intr_test.3095744084 May 09 12:38:08 PM PDT 24 May 09 12:38:26 PM PDT 24 49034357 ps
T197 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.39384568 May 09 12:38:02 PM PDT 24 May 09 12:38:20 PM PDT 24 77868735 ps
T1417 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.660297236 May 09 12:37:47 PM PDT 24 May 09 12:37:57 PM PDT 24 18624332 ps
T1418 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1825661783 May 09 12:38:03 PM PDT 24 May 09 12:38:20 PM PDT 24 33507273 ps
T1419 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2532678828 May 09 12:38:00 PM PDT 24 May 09 12:38:17 PM PDT 24 125807325 ps
T1420 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.4184597485 May 09 12:38:09 PM PDT 24 May 09 12:38:28 PM PDT 24 83400543 ps
T198 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.4169550547 May 09 12:38:10 PM PDT 24 May 09 12:38:29 PM PDT 24 336584185 ps
T199 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.4002229542 May 09 12:38:10 PM PDT 24 May 09 12:38:29 PM PDT 24 20346931 ps
T1421 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.403039610 May 09 12:37:59 PM PDT 24 May 09 12:38:15 PM PDT 24 60668223 ps
T1422 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3636420660 May 09 12:38:06 PM PDT 24 May 09 12:38:24 PM PDT 24 300258370 ps
T1423 /workspace/coverage/cover_reg_top/34.i2c_intr_test.2300110668 May 09 12:38:12 PM PDT 24 May 09 12:38:31 PM PDT 24 17056579 ps
T1424 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3936284432 May 09 12:38:06 PM PDT 24 May 09 12:38:23 PM PDT 24 51642833 ps
T1425 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.778099779 May 09 12:38:05 PM PDT 24 May 09 12:38:23 PM PDT 24 43376747 ps
T1426 /workspace/coverage/cover_reg_top/31.i2c_intr_test.2901634786 May 09 12:38:03 PM PDT 24 May 09 12:38:20 PM PDT 24 18000948 ps
T200 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2031127611 May 09 12:38:05 PM PDT 24 May 09 12:38:23 PM PDT 24 363779939 ps
T179 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1692585180 May 09 12:38:04 PM PDT 24 May 09 12:38:22 PM PDT 24 88964820 ps
T1427 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2384807472 May 09 12:38:10 PM PDT 24 May 09 12:38:29 PM PDT 24 123519868 ps
T202 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.641350409 May 09 12:38:03 PM PDT 24 May 09 12:38:20 PM PDT 24 46775238 ps
T203 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3174534311 May 09 12:37:56 PM PDT 24 May 09 12:38:11 PM PDT 24 509578142 ps
T204 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2590711182 May 09 12:37:59 PM PDT 24 May 09 12:38:17 PM PDT 24 260227273 ps
T1428 /workspace/coverage/cover_reg_top/17.i2c_intr_test.1847500330 May 09 12:38:17 PM PDT 24 May 09 12:38:36 PM PDT 24 73961358 ps
T1429 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1235582337 May 09 12:38:04 PM PDT 24 May 09 12:38:22 PM PDT 24 237654472 ps
T183 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.4018250664 May 09 12:38:07 PM PDT 24 May 09 12:38:26 PM PDT 24 93249430 ps
T1430 /workspace/coverage/cover_reg_top/27.i2c_intr_test.188473048 May 09 12:38:06 PM PDT 24 May 09 12:38:24 PM PDT 24 49054180 ps
T1431 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3547075200 May 09 12:38:04 PM PDT 24 May 09 12:38:22 PM PDT 24 30060503 ps
T1432 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1263522941 May 09 12:38:15 PM PDT 24 May 09 12:38:34 PM PDT 24 27755055 ps
T1433 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.4169276265 May 09 12:37:57 PM PDT 24 May 09 12:38:12 PM PDT 24 52733849 ps
T1434 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2625851302 May 09 12:38:30 PM PDT 24 May 09 12:38:48 PM PDT 24 63263810 ps
T1435 /workspace/coverage/cover_reg_top/8.i2c_intr_test.1399947220 May 09 12:38:05 PM PDT 24 May 09 12:38:23 PM PDT 24 46505453 ps
T1436 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1319873007 May 09 12:38:07 PM PDT 24 May 09 12:38:25 PM PDT 24 27367901 ps
T1437 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1906057566 May 09 12:38:03 PM PDT 24 May 09 12:38:21 PM PDT 24 27001408 ps
T1438 /workspace/coverage/cover_reg_top/24.i2c_intr_test.2092338253 May 09 12:38:13 PM PDT 24 May 09 12:38:32 PM PDT 24 18355900 ps
T1439 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.750657270 May 09 12:38:08 PM PDT 24 May 09 12:38:27 PM PDT 24 138024144 ps
T1440 /workspace/coverage/cover_reg_top/42.i2c_intr_test.4134811437 May 09 12:38:05 PM PDT 24 May 09 12:38:23 PM PDT 24 16520727 ps
T1441 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3424641882 May 09 12:38:12 PM PDT 24 May 09 12:38:31 PM PDT 24 80661959 ps
T1442 /workspace/coverage/cover_reg_top/47.i2c_intr_test.4135382090 May 09 12:38:31 PM PDT 24 May 09 12:38:48 PM PDT 24 37778819 ps
T1443 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2700488720 May 09 12:38:05 PM PDT 24 May 09 12:38:24 PM PDT 24 143358530 ps
T176 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.4018203685 May 09 12:38:06 PM PDT 24 May 09 12:38:25 PM PDT 24 49361914 ps
T1444 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3007271528 May 09 12:38:04 PM PDT 24 May 09 12:38:22 PM PDT 24 22231410 ps
T1445 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3210581204 May 09 12:37:52 PM PDT 24 May 09 12:38:05 PM PDT 24 217395534 ps
T1446 /workspace/coverage/cover_reg_top/21.i2c_intr_test.1510642009 May 09 12:38:08 PM PDT 24 May 09 12:38:26 PM PDT 24 45793703 ps
T1447 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1985363082 May 09 12:37:59 PM PDT 24 May 09 12:38:15 PM PDT 24 17513103 ps
T1448 /workspace/coverage/cover_reg_top/38.i2c_intr_test.3821843170 May 09 12:38:06 PM PDT 24 May 09 12:38:24 PM PDT 24 76945019 ps
T1449 /workspace/coverage/cover_reg_top/48.i2c_intr_test.2963962315 May 09 12:38:09 PM PDT 24 May 09 12:38:28 PM PDT 24 17792607 ps
T1450 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1986058305 May 09 12:38:06 PM PDT 24 May 09 12:38:25 PM PDT 24 102605801 ps
T1451 /workspace/coverage/cover_reg_top/0.i2c_intr_test.1636214018 May 09 12:37:52 PM PDT 24 May 09 12:38:04 PM PDT 24 32680133 ps
T177 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.169685830 May 09 12:38:02 PM PDT 24 May 09 12:38:21 PM PDT 24 134003963 ps
T1452 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2010024448 May 09 12:38:04 PM PDT 24 May 09 12:38:23 PM PDT 24 368537069 ps
T1453 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3477849119 May 09 12:38:00 PM PDT 24 May 09 12:38:16 PM PDT 24 20035833 ps
T1454 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2442657342 May 09 12:38:00 PM PDT 24 May 09 12:38:19 PM PDT 24 344630391 ps
T1455 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2990834027 May 09 12:38:11 PM PDT 24 May 09 12:38:30 PM PDT 24 136611070 ps
T1456 /workspace/coverage/cover_reg_top/36.i2c_intr_test.536023418 May 09 12:38:28 PM PDT 24 May 09 12:38:45 PM PDT 24 49067934 ps
T1457 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2353732130 May 09 12:38:08 PM PDT 24 May 09 12:38:26 PM PDT 24 64260000 ps
T1458 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2131737660 May 09 12:38:02 PM PDT 24 May 09 12:38:20 PM PDT 24 133325360 ps
T1459 /workspace/coverage/cover_reg_top/3.i2c_intr_test.3845033704 May 09 12:38:07 PM PDT 24 May 09 12:38:25 PM PDT 24 16032884 ps
T1460 /workspace/coverage/cover_reg_top/9.i2c_intr_test.2708489904 May 09 12:37:59 PM PDT 24 May 09 12:38:15 PM PDT 24 16736041 ps
T249 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2145121009 May 09 12:38:03 PM PDT 24 May 09 12:38:20 PM PDT 24 21321390 ps
T1461 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3347278648 May 09 12:37:49 PM PDT 24 May 09 12:38:00 PM PDT 24 106600273 ps
T1462 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1617793622 May 09 12:38:10 PM PDT 24 May 09 12:38:29 PM PDT 24 26645137 ps
T1463 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.605246922 May 09 12:37:51 PM PDT 24 May 09 12:38:04 PM PDT 24 228957806 ps
T1464 /workspace/coverage/cover_reg_top/39.i2c_intr_test.3827701511 May 09 12:38:14 PM PDT 24 May 09 12:38:32 PM PDT 24 18430667 ps
T1465 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.609281218 May 09 12:38:06 PM PDT 24 May 09 12:38:25 PM PDT 24 115391172 ps
T1466 /workspace/coverage/cover_reg_top/33.i2c_intr_test.485804544 May 09 12:38:09 PM PDT 24 May 09 12:38:28 PM PDT 24 48022716 ps
T1467 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4016314306 May 09 12:38:03 PM PDT 24 May 09 12:38:21 PM PDT 24 304965716 ps
T1468 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3404157516 May 09 12:37:51 PM PDT 24 May 09 12:38:04 PM PDT 24 493514747 ps
T1469 /workspace/coverage/cover_reg_top/45.i2c_intr_test.3534429935 May 09 12:38:09 PM PDT 24 May 09 12:38:28 PM PDT 24 30951803 ps
T182 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3410370163 May 09 12:38:04 PM PDT 24 May 09 12:38:22 PM PDT 24 73178452 ps
T1470 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3724284772 May 09 12:38:06 PM PDT 24 May 09 12:38:24 PM PDT 24 31067925 ps
T1471 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.4177027605 May 09 12:37:57 PM PDT 24 May 09 12:38:12 PM PDT 24 23169279 ps
T1472 /workspace/coverage/cover_reg_top/44.i2c_intr_test.103530155 May 09 12:38:26 PM PDT 24 May 09 12:38:44 PM PDT 24 17186737 ps
T1473 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2149319857 May 09 12:37:51 PM PDT 24 May 09 12:38:06 PM PDT 24 437004900 ps
T1474 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3128303340 May 09 12:38:10 PM PDT 24 May 09 12:38:30 PM PDT 24 404471402 ps
T1475 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3154399730 May 09 12:38:03 PM PDT 24 May 09 12:38:20 PM PDT 24 27766193 ps

Test location /workspace/coverage/default/38.i2c_host_stress_all.602124259
Short name T2
Test name
Test status
Simulation time 15298457843 ps
CPU time 1658.56 seconds
Started May 09 12:50:59 PM PDT 24
Finished May 09 01:18:39 PM PDT 24
Peak memory 2588684 kb
Host smart-57767ba6-26ed-449a-9c6d-af16cb155671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602124259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.602124259
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.208793047
Short name T3
Test name
Test status
Simulation time 6331812949 ps
CPU time 7.33 seconds
Started May 09 12:50:10 PM PDT 24
Finished May 09 12:50:20 PM PDT 24
Peak memory 212580 kb
Host smart-be0845d6-66cd-4bca-9860-76bb74c2bec1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208793047 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_intr_smoke.208793047
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.1459870342
Short name T19
Test name
Test status
Simulation time 3899824165 ps
CPU time 9.74 seconds
Started May 09 12:45:14 PM PDT 24
Finished May 09 12:45:25 PM PDT 24
Peak memory 213056 kb
Host smart-a1b6d199-242f-4580-9bef-77adff63c576
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459870342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.1459870342
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.708866769
Short name T88
Test name
Test status
Simulation time 130640470 ps
CPU time 0.92 seconds
Started May 09 12:37:52 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 203700 kb
Host smart-77b4f007-e93d-4131-89bd-33d909be31f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708866769 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.708866769
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.1377649704
Short name T49
Test name
Test status
Simulation time 10064705667 ps
CPU time 77.92 seconds
Started May 09 12:48:16 PM PDT 24
Finished May 09 12:49:37 PM PDT 24
Peak memory 471760 kb
Host smart-973a83ea-3228-4ebf-8966-647bc64046ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377649704 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.1377649704
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.1486034760
Short name T82
Test name
Test status
Simulation time 88562365609 ps
CPU time 978.04 seconds
Started May 09 12:52:13 PM PDT 24
Finished May 09 01:08:33 PM PDT 24
Peak memory 2692812 kb
Host smart-c7c67093-4161-47b0-bbb8-b215b26ae01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486034760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.1486034760
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_override.4262374724
Short name T121
Test name
Test status
Simulation time 27428473 ps
CPU time 0.68 seconds
Started May 09 12:48:33 PM PDT 24
Finished May 09 12:48:36 PM PDT 24
Peak memory 204012 kb
Host smart-ffe6846d-d97c-49fa-9927-37a3f32a1d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262374724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.4262374724
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.2887110066
Short name T219
Test name
Test status
Simulation time 1411105748 ps
CPU time 5.65 seconds
Started May 09 12:47:27 PM PDT 24
Finished May 09 12:47:36 PM PDT 24
Peak memory 204420 kb
Host smart-faa23ebc-827f-4e17-8d67-501477853138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887110066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.2887110066
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.1815269673
Short name T4
Test name
Test status
Simulation time 29330219383 ps
CPU time 67.75 seconds
Started May 09 12:46:37 PM PDT 24
Finished May 09 12:47:47 PM PDT 24
Peak memory 1177904 kb
Host smart-01412b06-2275-4250-bd4b-d677a0748938
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815269673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.1815269673
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.1550750753
Short name T80
Test name
Test status
Simulation time 23572407748 ps
CPU time 1659.44 seconds
Started May 09 12:48:34 PM PDT 24
Finished May 09 01:16:16 PM PDT 24
Peak memory 2205520 kb
Host smart-f28907a8-2c14-493f-a3d2-fba29d00b4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550750753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.1550750753
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1444417224
Short name T158
Test name
Test status
Simulation time 42943174 ps
CPU time 0.84 seconds
Started May 09 12:45:37 PM PDT 24
Finished May 09 12:45:39 PM PDT 24
Peak memory 221380 kb
Host smart-f6a0aff0-ca89-4a89-a292-80e7ebcc4e86
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444417224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1444417224
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_alert_test.1514714920
Short name T286
Test name
Test status
Simulation time 42648334 ps
CPU time 0.62 seconds
Started May 09 12:45:38 PM PDT 24
Finished May 09 12:45:40 PM PDT 24
Peak memory 204176 kb
Host smart-07fbc00d-de18-46dc-9d2a-e4500b281554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514714920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.1514714920
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.1817730293
Short name T190
Test name
Test status
Simulation time 1455312940 ps
CPU time 7.77 seconds
Started May 09 12:47:25 PM PDT 24
Finished May 09 12:47:36 PM PDT 24
Peak memory 220640 kb
Host smart-4edd8f8e-89f2-4310-9b46-8bfa74731b28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817730293 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.1817730293
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.4002229542
Short name T199
Test name
Test status
Simulation time 20346931 ps
CPU time 0.69 seconds
Started May 09 12:38:10 PM PDT 24
Finished May 09 12:38:29 PM PDT 24
Peak memory 203668 kb
Host smart-4f915573-d773-4e06-9aee-4bd4e0347057
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002229542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.4002229542
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.271270942
Short name T175
Test name
Test status
Simulation time 162144548 ps
CPU time 2.12 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:25 PM PDT 24
Peak memory 203928 kb
Host smart-34f472c8-3872-4c0f-b82d-d095bc948c70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271270942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.271270942
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.3862130471
Short name T77
Test name
Test status
Simulation time 147749329 ps
CPU time 1.12 seconds
Started May 09 12:47:57 PM PDT 24
Finished May 09 12:48:00 PM PDT 24
Peak memory 204232 kb
Host smart-61f22923-50bf-4373-88b6-f75cbbea01fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862130471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.3862130471
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.3041958313
Short name T232
Test name
Test status
Simulation time 20420525845 ps
CPU time 182.28 seconds
Started May 09 12:47:11 PM PDT 24
Finished May 09 12:50:15 PM PDT 24
Peak memory 1402608 kb
Host smart-1af505bf-4fea-4c85-8827-5cda917bb824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041958313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.3041958313
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.2343614607
Short name T237
Test name
Test status
Simulation time 829395272 ps
CPU time 4.48 seconds
Started May 09 12:49:51 PM PDT 24
Finished May 09 12:49:57 PM PDT 24
Peak memory 204332 kb
Host smart-4915ba9b-cebe-41d8-829a-ff4a1b4455ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343614607 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.2343614607
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.1006175351
Short name T242
Test name
Test status
Simulation time 6463830087 ps
CPU time 2.76 seconds
Started May 09 12:52:23 PM PDT 24
Finished May 09 12:52:29 PM PDT 24
Peak memory 204452 kb
Host smart-7ac5d637-4027-411d-b491-8d25c680b2a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006175351 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.1006175351
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.3725701956
Short name T155
Test name
Test status
Simulation time 64537288 ps
CPU time 1.73 seconds
Started May 09 12:37:56 PM PDT 24
Finished May 09 12:38:12 PM PDT 24
Peak memory 203956 kb
Host smart-55192f39-ea62-4853-9cbb-e34d9aaebd10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725701956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.3725701956
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.1655256857
Short name T41
Test name
Test status
Simulation time 3392078565 ps
CPU time 31.63 seconds
Started May 09 12:51:35 PM PDT 24
Finished May 09 12:52:08 PM PDT 24
Peak memory 358876 kb
Host smart-97ff422c-fd2e-483e-978a-983c0faae8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655256857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.1655256857
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.4125646514
Short name T55
Test name
Test status
Simulation time 65472231572 ps
CPU time 1709.96 seconds
Started May 09 12:49:19 PM PDT 24
Finished May 09 01:17:53 PM PDT 24
Peak memory 2901804 kb
Host smart-d9a2c1bf-5d6e-4d0d-a94e-82eb8f4daf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125646514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.4125646514
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.1890662747
Short name T63
Test name
Test status
Simulation time 60454667182 ps
CPU time 770.19 seconds
Started May 09 12:52:04 PM PDT 24
Finished May 09 01:04:57 PM PDT 24
Peak memory 2558544 kb
Host smart-f80808fd-c0f3-4734-968f-92cdb7d5bbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890662747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.1890662747
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.3105813466
Short name T214
Test name
Test status
Simulation time 389246383 ps
CPU time 5.62 seconds
Started May 09 12:47:43 PM PDT 24
Finished May 09 12:47:51 PM PDT 24
Peak memory 204436 kb
Host smart-14abf02f-a616-4d36-ae6d-2c600e84c552
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105813466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.3105813466
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.1534510560
Short name T52
Test name
Test status
Simulation time 48061467320 ps
CPU time 1313.71 seconds
Started May 09 12:50:16 PM PDT 24
Finished May 09 01:12:12 PM PDT 24
Peak memory 2013320 kb
Host smart-09b6cfd7-3442-467b-bd07-cda9f07cfd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534510560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.1534510560
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3765230596
Short name T134
Test name
Test status
Simulation time 62215936 ps
CPU time 0.87 seconds
Started May 09 12:38:10 PM PDT 24
Finished May 09 12:38:29 PM PDT 24
Peak memory 203704 kb
Host smart-a32d3df6-b8af-4bad-acb2-926b13430787
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765230596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.3765230596
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.i2c_target_stress_all.2365265881
Short name T797
Test name
Test status
Simulation time 18353773776 ps
CPU time 33.27 seconds
Started May 09 12:47:14 PM PDT 24
Finished May 09 12:47:51 PM PDT 24
Peak memory 220756 kb
Host smart-9593a49e-9f10-4c07-b92b-90f6743be1c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365265881 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.i2c_target_stress_all.2365265881
Directory /workspace/10.i2c_target_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.180951726
Short name T215
Test name
Test status
Simulation time 54937912834 ps
CPU time 1652.49 seconds
Started May 09 12:50:28 PM PDT 24
Finished May 09 01:18:04 PM PDT 24
Peak memory 2544388 kb
Host smart-4f1973a5-1a0a-4ca2-9c6a-d7614511b5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180951726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.180951726
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.3090607777
Short name T248
Test name
Test status
Simulation time 1257225102 ps
CPU time 44.89 seconds
Started May 09 12:51:23 PM PDT 24
Finished May 09 12:52:11 PM PDT 24
Peak memory 204380 kb
Host smart-184b632e-2e7e-4557-8d1b-1048e8067f01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090607777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.3090607777
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.546338028
Short name T212
Test name
Test status
Simulation time 10062159360 ps
CPU time 79.38 seconds
Started May 09 12:47:33 PM PDT 24
Finished May 09 12:48:55 PM PDT 24
Peak memory 401516 kb
Host smart-c7109e4e-149e-4b7d-9956-5c27b6f74348
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546338028 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_acq.546338028
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.388633310
Short name T217
Test name
Test status
Simulation time 191305157 ps
CPU time 0.81 seconds
Started May 09 12:48:36 PM PDT 24
Finished May 09 12:48:39 PM PDT 24
Peak memory 204168 kb
Host smart-5007b041-5b4b-4a79-bb1e-e161db4dd4c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388633310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fm
t.388633310
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.1794952138
Short name T106
Test name
Test status
Simulation time 192917240275 ps
CPU time 785.38 seconds
Started May 09 12:50:02 PM PDT 24
Finished May 09 01:03:09 PM PDT 24
Peak memory 2742212 kb
Host smart-e15b2f58-8d54-4535-be64-e7ac16dbf8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794952138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.1794952138
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.3947498672
Short name T222
Test name
Test status
Simulation time 61765775001 ps
CPU time 689.11 seconds
Started May 09 12:51:20 PM PDT 24
Finished May 09 01:02:51 PM PDT 24
Peak memory 2148440 kb
Host smart-7f293886-af1c-4f71-a6fc-e086fb666202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947498672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.3947498672
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.1087725549
Short name T59
Test name
Test status
Simulation time 10118014149 ps
CPU time 81.77 seconds
Started May 09 12:46:19 PM PDT 24
Finished May 09 12:47:42 PM PDT 24
Peak memory 572368 kb
Host smart-d409d8e9-5858-4a44-acef-24740e7f2904
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087725549 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.1087725549
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3272734303
Short name T178
Test name
Test status
Simulation time 83569481 ps
CPU time 2.12 seconds
Started May 09 12:38:29 PM PDT 24
Finished May 09 12:38:47 PM PDT 24
Peak memory 203964 kb
Host smart-45f7f062-51fb-4141-bc85-f195bf4ae2ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272734303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.3272734303
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.3065149460
Short name T445
Test name
Test status
Simulation time 2458018456 ps
CPU time 58.63 seconds
Started May 09 12:47:44 PM PDT 24
Finished May 09 12:48:45 PM PDT 24
Peak memory 331352 kb
Host smart-f44f7aa1-7617-4f4f-9267-5c69a59fd163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065149460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.3065149460
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_perf.1424372959
Short name T75
Test name
Test status
Simulation time 23449733764 ps
CPU time 33.19 seconds
Started May 09 12:51:44 PM PDT 24
Finished May 09 12:52:22 PM PDT 24
Peak memory 380004 kb
Host smart-69ac246a-9b6a-479f-b889-d633eead443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424372959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.1424372959
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2145121009
Short name T249
Test name
Test status
Simulation time 21321390 ps
CPU time 0.78 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 203816 kb
Host smart-6a19880a-f89d-4122-972d-199407890313
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145121009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2145121009
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.2276011297
Short name T233
Test name
Test status
Simulation time 7488858172 ps
CPU time 77.09 seconds
Started May 09 12:49:10 PM PDT 24
Finished May 09 12:50:30 PM PDT 24
Peak memory 208252 kb
Host smart-3ad86e32-afd0-4620-a215-27e12c5a1b25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276011297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.2276011297
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.169685830
Short name T177
Test name
Test status
Simulation time 134003963 ps
CPU time 2.38 seconds
Started May 09 12:38:02 PM PDT 24
Finished May 09 12:38:21 PM PDT 24
Peak memory 204024 kb
Host smart-5ebcc476-ab39-4959-a47b-58267b5e19f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169685830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.169685830
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1545253832
Short name T171
Test name
Test status
Simulation time 45623876 ps
CPU time 2.06 seconds
Started May 09 12:37:51 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 203908 kb
Host smart-1c5f5726-3ba0-4b08-aac5-5d72f74d070d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545253832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1545253832
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.352900854
Short name T94
Test name
Test status
Simulation time 162394977 ps
CPU time 2.39 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:38:25 PM PDT 24
Peak memory 203968 kb
Host smart-61a44392-0f74-4ec9-b97d-94d9565f5c19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352900854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.352900854
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.4018250664
Short name T183
Test name
Test status
Simulation time 93249430 ps
CPU time 1.41 seconds
Started May 09 12:38:07 PM PDT 24
Finished May 09 12:38:26 PM PDT 24
Peak memory 204012 kb
Host smart-d1f83b5c-7fe8-4c1a-9d08-ec8c52310b2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018250664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.4018250664
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.4018203685
Short name T176
Test name
Test status
Simulation time 49361914 ps
CPU time 1.43 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:25 PM PDT 24
Peak memory 203932 kb
Host smart-56b93973-96aa-41b0-a8cb-9cca5930f7be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018203685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.4018203685
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/11.i2c_host_override.3805340553
Short name T44
Test name
Test status
Simulation time 44951308 ps
CPU time 0.69 seconds
Started May 09 12:47:25 PM PDT 24
Finished May 09 12:47:29 PM PDT 24
Peak memory 204156 kb
Host smart-a1a08238-233c-4c20-99b9-26408a7aa89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805340553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.3805340553
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2689409244
Short name T1306
Test name
Test status
Simulation time 10325692783 ps
CPU time 11.11 seconds
Started May 09 12:47:53 PM PDT 24
Finished May 09 12:48:05 PM PDT 24
Peak memory 252180 kb
Host smart-b3389782-e521-41b4-ae3a-408fca107735
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689409244 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2689409244
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2700488720
Short name T1443
Test name
Test status
Simulation time 143358530 ps
CPU time 2.2 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:38:24 PM PDT 24
Peak memory 203968 kb
Host smart-b9fa3b97-75b5-4cf4-bce5-325205c6668f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700488720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2700488720
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3628729086
Short name T1371
Test name
Test status
Simulation time 275993090 ps
CPU time 2.83 seconds
Started May 09 12:37:58 PM PDT 24
Finished May 09 12:38:16 PM PDT 24
Peak memory 203880 kb
Host smart-476c8981-1e78-4e75-82f7-6c974b83269c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628729086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.3628729086
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3724284772
Short name T1470
Test name
Test status
Simulation time 31067925 ps
CPU time 0.75 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:24 PM PDT 24
Peak memory 203696 kb
Host smart-8695577a-98ab-4c2b-8f7e-1f08edad4aa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724284772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.3724284772
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.1636214018
Short name T1451
Test name
Test status
Simulation time 32680133 ps
CPU time 0.62 seconds
Started May 09 12:37:52 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 203600 kb
Host smart-cae797ee-591a-42c7-8c29-0b911d166a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636214018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1636214018
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3768444719
Short name T1396
Test name
Test status
Simulation time 182441408 ps
CPU time 1.15 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:21 PM PDT 24
Peak memory 204028 kb
Host smart-40602a80-198b-4628-9898-d1f2783da391
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768444719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.3768444719
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.1017802464
Short name T92
Test name
Test status
Simulation time 87655296 ps
CPU time 1.45 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 204036 kb
Host smart-18bc9b68-6e24-4898-b4f5-20f4c845b89f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017802464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.1017802464
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2131737660
Short name T1458
Test name
Test status
Simulation time 133325360 ps
CPU time 2.11 seconds
Started May 09 12:38:02 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 204020 kb
Host smart-46c8bd41-eab4-46b2-9f0a-f1552d6757dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131737660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2131737660
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2149319857
Short name T1473
Test name
Test status
Simulation time 437004900 ps
CPU time 5.14 seconds
Started May 09 12:37:51 PM PDT 24
Finished May 09 12:38:06 PM PDT 24
Peak memory 203968 kb
Host smart-68d906d4-6115-4881-904b-0587aad7dc1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149319857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2149319857
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2086334031
Short name T1367
Test name
Test status
Simulation time 19079448 ps
CPU time 0.77 seconds
Started May 09 12:37:48 PM PDT 24
Finished May 09 12:37:58 PM PDT 24
Peak memory 203752 kb
Host smart-9bd957ea-cb96-41ec-9eed-d5698e0549f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086334031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2086334031
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3780562669
Short name T1382
Test name
Test status
Simulation time 69594480 ps
CPU time 1.09 seconds
Started May 09 12:38:02 PM PDT 24
Finished May 09 12:38:19 PM PDT 24
Peak memory 203836 kb
Host smart-ec043b65-2106-4a7d-bc9e-a6225f4f69d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780562669 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.3780562669
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.403039610
Short name T1421
Test name
Test status
Simulation time 60668223 ps
CPU time 0.64 seconds
Started May 09 12:37:59 PM PDT 24
Finished May 09 12:38:15 PM PDT 24
Peak memory 203692 kb
Host smart-9f94e4cc-f0ba-4ce0-a3b4-3e57aecaa798
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403039610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.403039610
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3477849119
Short name T1453
Test name
Test status
Simulation time 20035833 ps
CPU time 0.67 seconds
Started May 09 12:38:00 PM PDT 24
Finished May 09 12:38:16 PM PDT 24
Peak memory 203616 kb
Host smart-87fb4bb4-5a83-4c6c-9a56-6e0b5a9dbc87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477849119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3477849119
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1825661783
Short name T1418
Test name
Test status
Simulation time 33507273 ps
CPU time 0.86 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 203764 kb
Host smart-5b30617d-6423-4107-8357-dfd02c204b78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825661783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.1825661783
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.609281218
Short name T1465
Test name
Test status
Simulation time 115391172 ps
CPU time 2.13 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:25 PM PDT 24
Peak memory 203960 kb
Host smart-bc509f82-d1b1-4d38-b35b-c30a66f0de11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609281218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.609281218
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3147217809
Short name T87
Test name
Test status
Simulation time 153063623 ps
CPU time 1.48 seconds
Started May 09 12:37:52 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 204036 kb
Host smart-bda198f9-7935-48b1-8812-ee59096fcd34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147217809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.3147217809
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2990834027
Short name T1455
Test name
Test status
Simulation time 136611070 ps
CPU time 1.26 seconds
Started May 09 12:38:11 PM PDT 24
Finished May 09 12:38:30 PM PDT 24
Peak memory 204044 kb
Host smart-69a973fb-ef96-496b-bb62-55cca56acc6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990834027 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.2990834027
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.476790416
Short name T196
Test name
Test status
Simulation time 30498389 ps
CPU time 0.78 seconds
Started May 09 12:38:19 PM PDT 24
Finished May 09 12:38:37 PM PDT 24
Peak memory 203664 kb
Host smart-ae15e27f-8b8a-40fc-b705-996d611d1227
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476790416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.476790416
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.4266521874
Short name T1373
Test name
Test status
Simulation time 15542765 ps
CPU time 0.64 seconds
Started May 09 12:38:04 PM PDT 24
Finished May 09 12:38:21 PM PDT 24
Peak memory 203620 kb
Host smart-14555302-995f-4b95-a554-57a381b19d75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266521874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.4266521874
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.325580758
Short name T1408
Test name
Test status
Simulation time 45384377 ps
CPU time 0.89 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 203720 kb
Host smart-2f8fe9ed-dbe5-416a-847d-cbc93a122b52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325580758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_ou
tstanding.325580758
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.4184597485
Short name T1420
Test name
Test status
Simulation time 83400543 ps
CPU time 1.29 seconds
Started May 09 12:38:09 PM PDT 24
Finished May 09 12:38:28 PM PDT 24
Peak memory 203936 kb
Host smart-877a60fb-f25c-488c-83b2-ac4d32a88726
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184597485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.4184597485
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2327744525
Short name T188
Test name
Test status
Simulation time 35578859 ps
CPU time 1.76 seconds
Started May 09 12:38:08 PM PDT 24
Finished May 09 12:38:27 PM PDT 24
Peak memory 203980 kb
Host smart-69cf6de7-c60a-4783-aa13-46afda9b4917
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327744525 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.2327744525
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3635411101
Short name T207
Test name
Test status
Simulation time 19108107 ps
CPU time 0.69 seconds
Started May 09 12:38:08 PM PDT 24
Finished May 09 12:38:26 PM PDT 24
Peak memory 203660 kb
Host smart-d5caedfa-1a56-4fe0-9f1d-28a61c316fe8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635411101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3635411101
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.2509849388
Short name T1377
Test name
Test status
Simulation time 25410513 ps
CPU time 0.67 seconds
Started May 09 12:38:09 PM PDT 24
Finished May 09 12:38:28 PM PDT 24
Peak memory 203636 kb
Host smart-4621ce01-8bde-43be-bbcc-fd4b5aff2c05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509849388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.2509849388
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3080960251
Short name T209
Test name
Test status
Simulation time 28052186 ps
CPU time 1.1 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:21 PM PDT 24
Peak memory 204028 kb
Host smart-c61c2389-0139-4bea-b7c0-44a22cc540f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080960251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.3080960251
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.2911607433
Short name T1401
Test name
Test status
Simulation time 1663635743 ps
CPU time 2.36 seconds
Started May 09 12:38:14 PM PDT 24
Finished May 09 12:38:34 PM PDT 24
Peak memory 203876 kb
Host smart-101bf669-e572-4bfc-99a8-cad38d3cb902
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911607433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2911607433
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1226112545
Short name T181
Test name
Test status
Simulation time 76575267 ps
CPU time 1.54 seconds
Started May 09 12:38:02 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 204052 kb
Host smart-6520ac84-a61a-437e-92cb-5f8df8904ef1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226112545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1226112545
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2157516588
Short name T1378
Test name
Test status
Simulation time 47401138 ps
CPU time 0.75 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 203656 kb
Host smart-e4b6ba55-d9f5-44d1-af73-e0be6f80fb2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157516588 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.2157516588
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3154399730
Short name T1475
Test name
Test status
Simulation time 27766193 ps
CPU time 0.74 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 203700 kb
Host smart-cbb2a57d-aa1d-43a3-8b17-dd3f5b30e389
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154399730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3154399730
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.123244472
Short name T1368
Test name
Test status
Simulation time 31282203 ps
CPU time 0.65 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:19 PM PDT 24
Peak memory 203628 kb
Host smart-37dee206-893e-43ba-b148-fe8b67e72355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123244472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.123244472
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1986058305
Short name T1450
Test name
Test status
Simulation time 102605801 ps
CPU time 2.32 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:25 PM PDT 24
Peak memory 203964 kb
Host smart-7c9e2c32-fa22-47c7-87a0-0061177c041c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986058305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1986058305
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1692585180
Short name T179
Test name
Test status
Simulation time 88964820 ps
CPU time 1.46 seconds
Started May 09 12:38:04 PM PDT 24
Finished May 09 12:38:22 PM PDT 24
Peak memory 203928 kb
Host smart-c3d7f320-6dd6-46eb-bcd3-b1ca93c81187
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692585180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.1692585180
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2913562554
Short name T186
Test name
Test status
Simulation time 66948854 ps
CPU time 1.13 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 203764 kb
Host smart-9b542763-c5e6-40bb-a8c1-34f853f83f88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913562554 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2913562554
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1310165117
Short name T1413
Test name
Test status
Simulation time 18971328 ps
CPU time 0.69 seconds
Started May 09 12:37:58 PM PDT 24
Finished May 09 12:38:14 PM PDT 24
Peak memory 203700 kb
Host smart-791823b1-ba3b-46b4-b4ea-bae17b43fb6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310165117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1310165117
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.3208197504
Short name T1380
Test name
Test status
Simulation time 34426427 ps
CPU time 0.65 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:24 PM PDT 24
Peak memory 203580 kb
Host smart-61d8fbb6-df39-49e7-b0d3-c7f9ae2ae6ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208197504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3208197504
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1235582337
Short name T1429
Test name
Test status
Simulation time 237654472 ps
CPU time 1.23 seconds
Started May 09 12:38:04 PM PDT 24
Finished May 09 12:38:22 PM PDT 24
Peak memory 203916 kb
Host smart-cc4ade6f-70c7-4470-884f-fdc75cd3d40e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235582337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.1235582337
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.677274431
Short name T1411
Test name
Test status
Simulation time 178104568 ps
CPU time 2.56 seconds
Started May 09 12:38:13 PM PDT 24
Finished May 09 12:38:34 PM PDT 24
Peak memory 203920 kb
Host smart-5ff2f225-a528-4ba1-9d52-35c8b1b5c36d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677274431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.677274431
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.4275197089
Short name T173
Test name
Test status
Simulation time 1001353109 ps
CPU time 1.44 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 203940 kb
Host smart-4c890f27-faed-4fc8-89ac-f4aae43c86b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275197089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.4275197089
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.727937057
Short name T91
Test name
Test status
Simulation time 41306765 ps
CPU time 0.97 seconds
Started May 09 12:38:08 PM PDT 24
Finished May 09 12:38:27 PM PDT 24
Peak memory 203780 kb
Host smart-b33ba133-407b-473b-86f5-36530a0ce9ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727937057 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.727937057
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.887226322
Short name T135
Test name
Test status
Simulation time 16109230 ps
CPU time 0.72 seconds
Started May 09 12:38:10 PM PDT 24
Finished May 09 12:38:29 PM PDT 24
Peak memory 203784 kb
Host smart-ab905aa6-9360-4b6f-aba0-b3635a5afa0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887226322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.887226322
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3850623163
Short name T1379
Test name
Test status
Simulation time 131616821 ps
CPU time 0.64 seconds
Started May 09 12:38:10 PM PDT 24
Finished May 09 12:38:29 PM PDT 24
Peak memory 203500 kb
Host smart-1abe60bd-c4c2-415a-b384-e6987ea57209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850623163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3850623163
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.283506539
Short name T208
Test name
Test status
Simulation time 105810614 ps
CPU time 1.2 seconds
Started May 09 12:38:08 PM PDT 24
Finished May 09 12:38:26 PM PDT 24
Peak memory 204012 kb
Host smart-5fde7110-ba4e-4476-8fc6-490d43fb752a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283506539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_ou
tstanding.283506539
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.2465796122
Short name T184
Test name
Test status
Simulation time 510781764 ps
CPU time 1.48 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 203860 kb
Host smart-95a82b1f-68e5-4908-bcbb-b3bc440509d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465796122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.2465796122
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.750657270
Short name T1439
Test name
Test status
Simulation time 138024144 ps
CPU time 1.06 seconds
Started May 09 12:38:08 PM PDT 24
Finished May 09 12:38:27 PM PDT 24
Peak memory 203812 kb
Host smart-6e2b16da-78e1-41ec-9ef3-f9ee7cb28023
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750657270 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.750657270
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2031127611
Short name T200
Test name
Test status
Simulation time 363779939 ps
CPU time 0.8 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 203776 kb
Host smart-c2342986-5f37-4410-b6be-e6c11265ad18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031127611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2031127611
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.1856366360
Short name T1372
Test name
Test status
Simulation time 24811760 ps
CPU time 0.63 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 203508 kb
Host smart-c8904f49-4286-47e8-8fef-11b7f0af2efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856366360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1856366360
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3547075200
Short name T1431
Test name
Test status
Simulation time 30060503 ps
CPU time 1.08 seconds
Started May 09 12:38:04 PM PDT 24
Finished May 09 12:38:22 PM PDT 24
Peak memory 204000 kb
Host smart-e3c4cdea-ef5f-43d5-bf10-dbc57013a8c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547075200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.3547075200
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.412223955
Short name T90
Test name
Test status
Simulation time 79768527 ps
CPU time 1.63 seconds
Started May 09 12:38:19 PM PDT 24
Finished May 09 12:38:38 PM PDT 24
Peak memory 204000 kb
Host smart-4613f627-015d-49af-a7f3-dbb60a294a91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412223955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.412223955
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3128303340
Short name T1474
Test name
Test status
Simulation time 404471402 ps
CPU time 1.37 seconds
Started May 09 12:38:10 PM PDT 24
Finished May 09 12:38:30 PM PDT 24
Peak memory 203924 kb
Host smart-c3e52d75-501b-4e16-b120-5aee64a50965
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128303340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3128303340
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1319873007
Short name T1436
Test name
Test status
Simulation time 27367901 ps
CPU time 0.81 seconds
Started May 09 12:38:07 PM PDT 24
Finished May 09 12:38:25 PM PDT 24
Peak memory 203808 kb
Host smart-e006bbbe-ed4a-4ad3-8f62-66c5f7db745c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319873007 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1319873007
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.2594612158
Short name T1410
Test name
Test status
Simulation time 74507113 ps
CPU time 0.63 seconds
Started May 09 12:38:07 PM PDT 24
Finished May 09 12:38:25 PM PDT 24
Peak memory 203632 kb
Host smart-80617a54-1bee-4c58-a2a3-e988c6ee12e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594612158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2594612158
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3007271528
Short name T1444
Test name
Test status
Simulation time 22231410 ps
CPU time 0.87 seconds
Started May 09 12:38:04 PM PDT 24
Finished May 09 12:38:22 PM PDT 24
Peak memory 203644 kb
Host smart-9d8e0bdc-394d-4add-bfac-554c09c9b0ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007271528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.3007271528
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.2010024448
Short name T1452
Test name
Test status
Simulation time 368537069 ps
CPU time 2.18 seconds
Started May 09 12:38:04 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 203956 kb
Host smart-edb45c20-0606-4e26-8355-a192dde10af9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010024448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.2010024448
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2384807472
Short name T1427
Test name
Test status
Simulation time 123519868 ps
CPU time 0.78 seconds
Started May 09 12:38:10 PM PDT 24
Finished May 09 12:38:29 PM PDT 24
Peak memory 203836 kb
Host smart-7a2b5845-ca76-4790-893f-d38593846582
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384807472 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.2384807472
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2625851302
Short name T1434
Test name
Test status
Simulation time 63263810 ps
CPU time 0.76 seconds
Started May 09 12:38:30 PM PDT 24
Finished May 09 12:38:48 PM PDT 24
Peak memory 203708 kb
Host smart-0bc77957-8d58-4aca-a7da-6095a5f81a31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625851302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2625851302
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.1847500330
Short name T1428
Test name
Test status
Simulation time 73961358 ps
CPU time 0.61 seconds
Started May 09 12:38:17 PM PDT 24
Finished May 09 12:38:36 PM PDT 24
Peak memory 203640 kb
Host smart-a8edaebf-a5af-4bcb-8e2b-8e5f3775a5a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847500330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1847500330
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.3424641882
Short name T1441
Test name
Test status
Simulation time 80661959 ps
CPU time 1.08 seconds
Started May 09 12:38:12 PM PDT 24
Finished May 09 12:38:31 PM PDT 24
Peak memory 204028 kb
Host smart-4b261a2d-37c9-446a-8c06-9f28a69997c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424641882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.3424641882
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1425818555
Short name T1383
Test name
Test status
Simulation time 66881636 ps
CPU time 1.78 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:38:24 PM PDT 24
Peak memory 204004 kb
Host smart-db7d5e67-b6e6-42e2-a720-f32bed140412
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425818555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1425818555
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1768727003
Short name T180
Test name
Test status
Simulation time 297983025 ps
CPU time 2.02 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:21 PM PDT 24
Peak memory 203964 kb
Host smart-579247bb-529f-471a-b07b-3e4068f56e2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768727003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1768727003
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.778099779
Short name T1425
Test name
Test status
Simulation time 43376747 ps
CPU time 1.06 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 203816 kb
Host smart-8a3f3db2-b566-4558-843e-8404107889fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778099779 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.778099779
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3936284432
Short name T1424
Test name
Test status
Simulation time 51642833 ps
CPU time 0.75 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 203784 kb
Host smart-381bb31b-b936-4bab-9bbb-18ad59f98e36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936284432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3936284432
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.164491658
Short name T1398
Test name
Test status
Simulation time 21719612 ps
CPU time 0.65 seconds
Started May 09 12:38:14 PM PDT 24
Finished May 09 12:38:33 PM PDT 24
Peak memory 203616 kb
Host smart-c46495fb-87ae-4e5a-8557-e4dd89bb2266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164491658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.164491658
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1617793622
Short name T1462
Test name
Test status
Simulation time 26645137 ps
CPU time 1.14 seconds
Started May 09 12:38:10 PM PDT 24
Finished May 09 12:38:29 PM PDT 24
Peak memory 203956 kb
Host smart-c4348022-64e6-48fe-93ca-499d7373bab0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617793622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.1617793622
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1545466451
Short name T1385
Test name
Test status
Simulation time 91156012 ps
CPU time 1.99 seconds
Started May 09 12:38:08 PM PDT 24
Finished May 09 12:38:28 PM PDT 24
Peak memory 203972 kb
Host smart-44e97ee2-2e39-4e14-a762-ed6c1822a99a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545466451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1545466451
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1161193821
Short name T228
Test name
Test status
Simulation time 152035647 ps
CPU time 2.21 seconds
Started May 09 12:38:09 PM PDT 24
Finished May 09 12:38:28 PM PDT 24
Peak memory 204056 kb
Host smart-8e2a9c7d-caff-42d2-bdc5-542d944fa5bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161193821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1161193821
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3926836842
Short name T1404
Test name
Test status
Simulation time 104777546 ps
CPU time 0.98 seconds
Started May 09 12:38:09 PM PDT 24
Finished May 09 12:38:27 PM PDT 24
Peak memory 203816 kb
Host smart-587c033c-e4e2-4ba7-8a80-dfb89e58027a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926836842 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3926836842
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.4248643674
Short name T89
Test name
Test status
Simulation time 24812362 ps
CPU time 0.7 seconds
Started May 09 12:38:14 PM PDT 24
Finished May 09 12:38:33 PM PDT 24
Peak memory 203756 kb
Host smart-67ce231f-1af9-44f3-b2ce-6abfaa3b5d75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248643674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.4248643674
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.3095744084
Short name T1416
Test name
Test status
Simulation time 49034357 ps
CPU time 0.63 seconds
Started May 09 12:38:08 PM PDT 24
Finished May 09 12:38:26 PM PDT 24
Peak memory 203600 kb
Host smart-a03335e3-2194-484f-88b7-1e054a915d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095744084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.3095744084
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1363027369
Short name T1405
Test name
Test status
Simulation time 778309275 ps
CPU time 2.33 seconds
Started May 09 12:38:08 PM PDT 24
Finished May 09 12:38:27 PM PDT 24
Peak memory 203980 kb
Host smart-36a4e6a3-8565-4bb5-b1a6-39c0ca3abf6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363027369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.1363027369
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.1263522941
Short name T1432
Test name
Test status
Simulation time 27755055 ps
CPU time 1.25 seconds
Started May 09 12:38:15 PM PDT 24
Finished May 09 12:38:34 PM PDT 24
Peak memory 204012 kb
Host smart-f85d5ede-2122-4287-8bc9-d317e6f8a646
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263522941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.1263522941
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3174534311
Short name T203
Test name
Test status
Simulation time 509578142 ps
CPU time 2.14 seconds
Started May 09 12:37:56 PM PDT 24
Finished May 09 12:38:11 PM PDT 24
Peak memory 203944 kb
Host smart-bb986297-aaec-48f8-907a-a33d141b7663
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174534311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3174534311
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.1705534463
Short name T201
Test name
Test status
Simulation time 655328047 ps
CPU time 6.04 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:25 PM PDT 24
Peak memory 203916 kb
Host smart-daf5abc0-6a01-42ec-aea4-d34f5de3e19e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705534463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.1705534463
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2045942768
Short name T192
Test name
Test status
Simulation time 36715738 ps
CPU time 0.65 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 203708 kb
Host smart-4c9827b4-552a-4666-a22a-9173e868767f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045942768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2045942768
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.434313691
Short name T1391
Test name
Test status
Simulation time 71333867 ps
CPU time 0.97 seconds
Started May 09 12:38:04 PM PDT 24
Finished May 09 12:38:22 PM PDT 24
Peak memory 203832 kb
Host smart-a7c97731-8c35-42c7-8e9c-a3d6425ac67a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434313691 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.434313691
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2446729043
Short name T194
Test name
Test status
Simulation time 36887404 ps
CPU time 0.65 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:38:22 PM PDT 24
Peak memory 203688 kb
Host smart-fa5657f7-7bd6-4571-9942-5c443c799fc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446729043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2446729043
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.3078041715
Short name T1370
Test name
Test status
Simulation time 35349466 ps
CPU time 0.65 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 203600 kb
Host smart-cb99515c-0d2d-4915-a4c6-97355ae3efe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078041715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.3078041715
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1358839394
Short name T1399
Test name
Test status
Simulation time 157967873 ps
CPU time 0.88 seconds
Started May 09 12:38:01 PM PDT 24
Finished May 09 12:38:17 PM PDT 24
Peak memory 203736 kb
Host smart-6daa5ffa-85eb-4452-9801-e2a4f67165a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358839394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1358839394
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2071835916
Short name T95
Test name
Test status
Simulation time 155416229 ps
CPU time 2.33 seconds
Started May 09 12:38:02 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 203984 kb
Host smart-434ce0a0-e9c7-4080-a87e-88c268853680
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071835916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.2071835916
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.4287662050
Short name T154
Test name
Test status
Simulation time 72367739 ps
CPU time 1.38 seconds
Started May 09 12:37:59 PM PDT 24
Finished May 09 12:38:16 PM PDT 24
Peak memory 204056 kb
Host smart-9a22873f-ee60-483e-ad50-56aa60f9fd4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287662050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.4287662050
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.2848602095
Short name T1387
Test name
Test status
Simulation time 38572570 ps
CPU time 0.65 seconds
Started May 09 12:38:11 PM PDT 24
Finished May 09 12:38:30 PM PDT 24
Peak memory 203584 kb
Host smart-129cb440-3738-4a32-9c47-9a49edca6c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848602095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2848602095
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.1510642009
Short name T1446
Test name
Test status
Simulation time 45793703 ps
CPU time 0.7 seconds
Started May 09 12:38:08 PM PDT 24
Finished May 09 12:38:26 PM PDT 24
Peak memory 203608 kb
Host smart-7ea2af51-3c76-4905-90d1-ef2227825c07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510642009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1510642009
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.1888340838
Short name T1403
Test name
Test status
Simulation time 42188061 ps
CPU time 0.65 seconds
Started May 09 12:38:19 PM PDT 24
Finished May 09 12:38:37 PM PDT 24
Peak memory 203580 kb
Host smart-2915ffa1-e41b-4085-a824-1e86e116e666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888340838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1888340838
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.1890888003
Short name T1369
Test name
Test status
Simulation time 50893509 ps
CPU time 0.62 seconds
Started May 09 12:38:13 PM PDT 24
Finished May 09 12:38:32 PM PDT 24
Peak memory 203564 kb
Host smart-6901ff28-841a-4a12-a64f-f1d63349286b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890888003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1890888003
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.2092338253
Short name T1438
Test name
Test status
Simulation time 18355900 ps
CPU time 0.63 seconds
Started May 09 12:38:13 PM PDT 24
Finished May 09 12:38:32 PM PDT 24
Peak memory 203540 kb
Host smart-7530a410-6c03-4b89-8003-a9bf14d9be4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092338253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2092338253
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.2907244549
Short name T1414
Test name
Test status
Simulation time 16891641 ps
CPU time 0.66 seconds
Started May 09 12:38:10 PM PDT 24
Finished May 09 12:38:29 PM PDT 24
Peak memory 203612 kb
Host smart-5bb022dc-2192-4eaf-864b-d0808135859b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907244549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.2907244549
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.711444029
Short name T1412
Test name
Test status
Simulation time 15776798 ps
CPU time 0.63 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:24 PM PDT 24
Peak memory 203620 kb
Host smart-3ac2e0ca-25e2-4163-b9cb-192b8ba0b504
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711444029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.711444029
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.188473048
Short name T1430
Test name
Test status
Simulation time 49054180 ps
CPU time 0.68 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:24 PM PDT 24
Peak memory 203596 kb
Host smart-20c23b06-4a2c-4cc9-a4fd-6d00ddb8bbcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188473048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.188473048
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.3241927205
Short name T1365
Test name
Test status
Simulation time 25311186 ps
CPU time 0.64 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 203640 kb
Host smart-4c79f914-aea9-44f9-ad78-b6f5cb95252b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241927205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3241927205
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.1912631868
Short name T1374
Test name
Test status
Simulation time 35559249 ps
CPU time 0.63 seconds
Started May 09 12:38:08 PM PDT 24
Finished May 09 12:38:26 PM PDT 24
Peak memory 203612 kb
Host smart-3f9b59f6-4569-49ec-a57d-36f5430e4409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912631868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.1912631868
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.39384568
Short name T197
Test name
Test status
Simulation time 77868735 ps
CPU time 1.39 seconds
Started May 09 12:38:02 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 203908 kb
Host smart-fe187a34-bff7-42a1-a4dd-6f5f6f51f66a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39384568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.39384568
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.605246922
Short name T1463
Test name
Test status
Simulation time 228957806 ps
CPU time 3.18 seconds
Started May 09 12:37:51 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 203968 kb
Host smart-9c514478-cf11-45ed-b5e6-0c8b4641b46b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605246922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.605246922
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1527216815
Short name T195
Test name
Test status
Simulation time 148056639 ps
CPU time 0.76 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 203716 kb
Host smart-94975278-0f8a-4a95-aa23-73e1f17d98c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527216815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1527216815
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3000963487
Short name T187
Test name
Test status
Simulation time 89000219 ps
CPU time 0.85 seconds
Started May 09 12:37:56 PM PDT 24
Finished May 09 12:38:10 PM PDT 24
Peak memory 203840 kb
Host smart-b37bbc0c-392d-4ad8-8892-2f7b00d343cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000963487 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3000963487
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.660297236
Short name T1417
Test name
Test status
Simulation time 18624332 ps
CPU time 0.72 seconds
Started May 09 12:37:47 PM PDT 24
Finished May 09 12:37:57 PM PDT 24
Peak memory 203792 kb
Host smart-0b37aae8-381e-432a-8b28-5034b8020668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660297236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.660297236
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.3845033704
Short name T1459
Test name
Test status
Simulation time 16032884 ps
CPU time 0.7 seconds
Started May 09 12:38:07 PM PDT 24
Finished May 09 12:38:25 PM PDT 24
Peak memory 203612 kb
Host smart-a7b5af67-6100-40a2-9220-58dccf83ce72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845033704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.3845033704
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3802133744
Short name T205
Test name
Test status
Simulation time 183147206 ps
CPU time 1.2 seconds
Started May 09 12:38:04 PM PDT 24
Finished May 09 12:38:22 PM PDT 24
Peak memory 204012 kb
Host smart-c406c385-6722-49c6-856d-e981139b0c82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802133744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.3802133744
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1906057566
Short name T1437
Test name
Test status
Simulation time 27001408 ps
CPU time 1.16 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:21 PM PDT 24
Peak memory 204016 kb
Host smart-5fe0d552-8456-403a-a27e-04ef5c25263c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906057566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1906057566
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3410370163
Short name T182
Test name
Test status
Simulation time 73178452 ps
CPU time 1.47 seconds
Started May 09 12:38:04 PM PDT 24
Finished May 09 12:38:22 PM PDT 24
Peak memory 204016 kb
Host smart-850c03d3-5e2b-457b-b646-533edcbf1a74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410370163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3410370163
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.1976369383
Short name T1402
Test name
Test status
Simulation time 19428266 ps
CPU time 0.67 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 203644 kb
Host smart-70fe8987-c378-4a17-99e1-dcd346f4b0db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976369383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1976369383
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2901634786
Short name T1426
Test name
Test status
Simulation time 18000948 ps
CPU time 0.68 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 203640 kb
Host smart-abeaac41-871b-4963-a830-0fc0d0d32418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901634786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2901634786
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.435808036
Short name T1400
Test name
Test status
Simulation time 47186159 ps
CPU time 0.66 seconds
Started May 09 12:38:08 PM PDT 24
Finished May 09 12:38:27 PM PDT 24
Peak memory 203632 kb
Host smart-8a9b0dca-532e-496e-8bca-cfa686ca581e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435808036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.435808036
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.485804544
Short name T1466
Test name
Test status
Simulation time 48022716 ps
CPU time 0.62 seconds
Started May 09 12:38:09 PM PDT 24
Finished May 09 12:38:28 PM PDT 24
Peak memory 203620 kb
Host smart-46643663-7880-4175-8afc-a36be6dd6a50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485804544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.485804544
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.2300110668
Short name T1423
Test name
Test status
Simulation time 17056579 ps
CPU time 0.64 seconds
Started May 09 12:38:12 PM PDT 24
Finished May 09 12:38:31 PM PDT 24
Peak memory 203564 kb
Host smart-7d6716a9-3b2d-4eb9-bd97-f8b26c715dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300110668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2300110668
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.3215214629
Short name T1395
Test name
Test status
Simulation time 26696945 ps
CPU time 0.66 seconds
Started May 09 12:38:14 PM PDT 24
Finished May 09 12:38:33 PM PDT 24
Peak memory 203584 kb
Host smart-f72ea12d-d1f6-4236-9f9d-057063733730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215214629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3215214629
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.536023418
Short name T1456
Test name
Test status
Simulation time 49067934 ps
CPU time 0.64 seconds
Started May 09 12:38:28 PM PDT 24
Finished May 09 12:38:45 PM PDT 24
Peak memory 203616 kb
Host smart-1081ff1b-1ff2-42d0-b1bd-661199b54ea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536023418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.536023418
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.498030655
Short name T1384
Test name
Test status
Simulation time 18616823 ps
CPU time 0.66 seconds
Started May 09 12:38:10 PM PDT 24
Finished May 09 12:38:28 PM PDT 24
Peak memory 203572 kb
Host smart-59b21c88-450f-4e5f-8219-3e348e473d64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498030655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.498030655
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.3821843170
Short name T1448
Test name
Test status
Simulation time 76945019 ps
CPU time 0.71 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:24 PM PDT 24
Peak memory 203584 kb
Host smart-064d6975-b9fc-4e88-b5dc-cb9ae751e019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821843170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.3821843170
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.3827701511
Short name T1464
Test name
Test status
Simulation time 18430667 ps
CPU time 0.68 seconds
Started May 09 12:38:14 PM PDT 24
Finished May 09 12:38:32 PM PDT 24
Peak memory 203564 kb
Host smart-312118a5-e609-4a93-a99e-f164d20957ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827701511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3827701511
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2590711182
Short name T204
Test name
Test status
Simulation time 260227273 ps
CPU time 2.15 seconds
Started May 09 12:37:59 PM PDT 24
Finished May 09 12:38:17 PM PDT 24
Peak memory 204032 kb
Host smart-84cb5eff-eac2-4efb-bc8e-e436c5052c2c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590711182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2590711182
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2442657342
Short name T1454
Test name
Test status
Simulation time 344630391 ps
CPU time 3.35 seconds
Started May 09 12:38:00 PM PDT 24
Finished May 09 12:38:19 PM PDT 24
Peak memory 203972 kb
Host smart-0905a18f-a1af-442a-8bf2-2fa509b442d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442657342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.2442657342
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.3420291447
Short name T193
Test name
Test status
Simulation time 28958063 ps
CPU time 0.75 seconds
Started May 09 12:37:58 PM PDT 24
Finished May 09 12:38:13 PM PDT 24
Peak memory 203640 kb
Host smart-9aa705c9-cf20-4ba1-b97b-1b98ebbdef31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420291447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.3420291447
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.471782653
Short name T1393
Test name
Test status
Simulation time 24398094 ps
CPU time 0.76 seconds
Started May 09 12:38:07 PM PDT 24
Finished May 09 12:38:24 PM PDT 24
Peak memory 203692 kb
Host smart-664111a3-c657-4fdb-8e08-521a9dba3ea9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471782653 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.471782653
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2016224981
Short name T1415
Test name
Test status
Simulation time 51974812 ps
CPU time 0.68 seconds
Started May 09 12:37:55 PM PDT 24
Finished May 09 12:38:09 PM PDT 24
Peak memory 203644 kb
Host smart-91c42863-ea88-47df-97f8-baf2c316b4cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016224981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2016224981
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.820081946
Short name T1386
Test name
Test status
Simulation time 60989774 ps
CPU time 0.67 seconds
Started May 09 12:38:00 PM PDT 24
Finished May 09 12:38:16 PM PDT 24
Peak memory 203580 kb
Host smart-144cf536-9999-4446-bdbe-4a506831b799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820081946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.820081946
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.4159096556
Short name T1409
Test name
Test status
Simulation time 58470973 ps
CPU time 0.84 seconds
Started May 09 12:37:56 PM PDT 24
Finished May 09 12:38:11 PM PDT 24
Peak memory 203712 kb
Host smart-cb875660-0cd2-43ab-9482-8fa1775cb956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159096556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.4159096556
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.3210581204
Short name T1445
Test name
Test status
Simulation time 217395534 ps
CPU time 2.4 seconds
Started May 09 12:37:52 PM PDT 24
Finished May 09 12:38:05 PM PDT 24
Peak memory 203952 kb
Host smart-07242850-3e87-41fa-a831-080b6cbf3e92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210581204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3210581204
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3404157516
Short name T1468
Test name
Test status
Simulation time 493514747 ps
CPU time 2.33 seconds
Started May 09 12:37:51 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 203972 kb
Host smart-1dc81f9f-5d98-4ef8-babb-1542e4af6da5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404157516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3404157516
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.2342378894
Short name T1375
Test name
Test status
Simulation time 16438055 ps
CPU time 0.64 seconds
Started May 09 12:38:12 PM PDT 24
Finished May 09 12:38:31 PM PDT 24
Peak memory 203564 kb
Host smart-899fbbac-9f0e-499b-8130-3b34cf99353f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342378894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2342378894
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.2747775672
Short name T1397
Test name
Test status
Simulation time 59269605 ps
CPU time 0.63 seconds
Started May 09 12:38:09 PM PDT 24
Finished May 09 12:38:28 PM PDT 24
Peak memory 203588 kb
Host smart-ebb6195b-1823-44cf-a360-1b687715ebb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747775672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2747775672
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.4134811437
Short name T1440
Test name
Test status
Simulation time 16520727 ps
CPU time 0.66 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 203592 kb
Host smart-1ea234db-72cf-475c-bdde-7efa006b1e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134811437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.4134811437
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.2647167106
Short name T1366
Test name
Test status
Simulation time 30746800 ps
CPU time 0.65 seconds
Started May 09 12:38:13 PM PDT 24
Finished May 09 12:38:32 PM PDT 24
Peak memory 203580 kb
Host smart-e8927388-9b73-4067-8c0a-65916b9606be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647167106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.2647167106
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.103530155
Short name T1472
Test name
Test status
Simulation time 17186737 ps
CPU time 0.69 seconds
Started May 09 12:38:26 PM PDT 24
Finished May 09 12:38:44 PM PDT 24
Peak memory 203580 kb
Host smart-db938925-0437-4487-aed6-aeadfec6fba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103530155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.103530155
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.3534429935
Short name T1469
Test name
Test status
Simulation time 30951803 ps
CPU time 0.64 seconds
Started May 09 12:38:09 PM PDT 24
Finished May 09 12:38:28 PM PDT 24
Peak memory 203612 kb
Host smart-fc656e57-f81d-4cff-a60d-6dcbeef4ffb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534429935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.3534429935
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.2767849919
Short name T1390
Test name
Test status
Simulation time 21204640 ps
CPU time 0.66 seconds
Started May 09 12:38:14 PM PDT 24
Finished May 09 12:38:32 PM PDT 24
Peak memory 203572 kb
Host smart-9b5b88db-c655-4ce1-b918-1c3f7244b3a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767849919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2767849919
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.4135382090
Short name T1442
Test name
Test status
Simulation time 37778819 ps
CPU time 0.63 seconds
Started May 09 12:38:31 PM PDT 24
Finished May 09 12:38:48 PM PDT 24
Peak memory 203460 kb
Host smart-413dbb09-2644-405f-ad68-101d608c3248
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135382090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.4135382090
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.2963962315
Short name T1449
Test name
Test status
Simulation time 17792607 ps
CPU time 0.65 seconds
Started May 09 12:38:09 PM PDT 24
Finished May 09 12:38:28 PM PDT 24
Peak memory 203628 kb
Host smart-21f88aa4-fdbb-4549-a1db-faa49265b7e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963962315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2963962315
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.100071319
Short name T1389
Test name
Test status
Simulation time 36469200 ps
CPU time 0.65 seconds
Started May 09 12:38:15 PM PDT 24
Finished May 09 12:38:33 PM PDT 24
Peak memory 203584 kb
Host smart-51fcbedf-c531-4239-9ba0-0872eb8fc543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100071319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.100071319
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.412694697
Short name T1406
Test name
Test status
Simulation time 172825544 ps
CPU time 0.78 seconds
Started May 09 12:37:48 PM PDT 24
Finished May 09 12:37:58 PM PDT 24
Peak memory 203756 kb
Host smart-522a53d2-d8a9-4917-9ae3-b990b9fcad8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412694697 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.412694697
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.641350409
Short name T202
Test name
Test status
Simulation time 46775238 ps
CPU time 0.77 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 203744 kb
Host smart-586a806a-48a3-42c2-92f1-09938f0a4b13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641350409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.641350409
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.806956802
Short name T1388
Test name
Test status
Simulation time 19447797 ps
CPU time 0.68 seconds
Started May 09 12:37:56 PM PDT 24
Finished May 09 12:38:11 PM PDT 24
Peak memory 203580 kb
Host smart-8ff10325-8ab7-4e38-91dd-f43f9a3cda88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806956802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.806956802
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3315076076
Short name T133
Test name
Test status
Simulation time 64467481 ps
CPU time 1.2 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:24 PM PDT 24
Peak memory 203988 kb
Host smart-06dc768b-a595-4555-8256-b92293d0b907
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315076076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.3315076076
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3076019257
Short name T174
Test name
Test status
Simulation time 276111393 ps
CPU time 2.08 seconds
Started May 09 12:37:56 PM PDT 24
Finished May 09 12:38:11 PM PDT 24
Peak memory 204052 kb
Host smart-2c427243-6e2c-4466-8f96-2c087978e9a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076019257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3076019257
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3636420660
Short name T1422
Test name
Test status
Simulation time 300258370 ps
CPU time 1.12 seconds
Started May 09 12:38:06 PM PDT 24
Finished May 09 12:38:24 PM PDT 24
Peak memory 203912 kb
Host smart-ccc93daf-2ff1-4f2b-8e8c-556a80354448
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636420660 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3636420660
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.4169276265
Short name T1433
Test name
Test status
Simulation time 52733849 ps
CPU time 0.73 seconds
Started May 09 12:37:57 PM PDT 24
Finished May 09 12:38:12 PM PDT 24
Peak memory 203664 kb
Host smart-4f946b2d-61dc-480d-aea3-33bf422f2ae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169276265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.4169276265
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.2567067421
Short name T1381
Test name
Test status
Simulation time 77575246 ps
CPU time 0.65 seconds
Started May 09 12:37:51 PM PDT 24
Finished May 09 12:38:03 PM PDT 24
Peak memory 203612 kb
Host smart-d56c66e2-5f79-4f67-ad04-beddbb2d2479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567067421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2567067421
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2532678828
Short name T1419
Test name
Test status
Simulation time 125807325 ps
CPU time 1.2 seconds
Started May 09 12:38:00 PM PDT 24
Finished May 09 12:38:17 PM PDT 24
Peak memory 204020 kb
Host smart-2cc168d6-3f40-414f-b22b-eb9d315c227d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532678828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.2532678828
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.35561030
Short name T1407
Test name
Test status
Simulation time 34674759 ps
CPU time 1.63 seconds
Started May 09 12:37:52 PM PDT 24
Finished May 09 12:38:04 PM PDT 24
Peak memory 204000 kb
Host smart-59d54394-0954-44e5-b65b-9fee981e423f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35561030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.35561030
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.4016314306
Short name T1467
Test name
Test status
Simulation time 304965716 ps
CPU time 1.5 seconds
Started May 09 12:38:03 PM PDT 24
Finished May 09 12:38:21 PM PDT 24
Peak memory 203952 kb
Host smart-5e66a137-56ee-4a18-b470-231314494d73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016314306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.4016314306
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2178658967
Short name T93
Test name
Test status
Simulation time 117526866 ps
CPU time 0.95 seconds
Started May 09 12:38:07 PM PDT 24
Finished May 09 12:38:26 PM PDT 24
Peak memory 203848 kb
Host smart-a3e0ceb5-7c55-474c-b408-be37cbf8911d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178658967 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2178658967
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.1985363082
Short name T1447
Test name
Test status
Simulation time 17513103 ps
CPU time 0.65 seconds
Started May 09 12:37:59 PM PDT 24
Finished May 09 12:38:15 PM PDT 24
Peak memory 203788 kb
Host smart-27e6edef-833c-4140-9221-e13cc7c219e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985363082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1985363082
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.2820328205
Short name T1376
Test name
Test status
Simulation time 49682961 ps
CPU time 0.67 seconds
Started May 09 12:38:04 PM PDT 24
Finished May 09 12:38:21 PM PDT 24
Peak memory 203584 kb
Host smart-b1412980-5ed4-42f1-9677-2321f644ae8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820328205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2820328205
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3347278648
Short name T1461
Test name
Test status
Simulation time 106600273 ps
CPU time 1.19 seconds
Started May 09 12:37:49 PM PDT 24
Finished May 09 12:38:00 PM PDT 24
Peak memory 204000 kb
Host smart-db054e89-6251-43a1-bf02-cdb2c5220fd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347278648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.3347278648
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3893903657
Short name T172
Test name
Test status
Simulation time 191575589 ps
CPU time 1.56 seconds
Started May 09 12:38:02 PM PDT 24
Finished May 09 12:38:20 PM PDT 24
Peak memory 203980 kb
Host smart-6320bcba-c886-4a03-bb1b-0ea90a25786e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893903657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3893903657
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.3314315008
Short name T170
Test name
Test status
Simulation time 329697294 ps
CPU time 1.47 seconds
Started May 09 12:38:00 PM PDT 24
Finished May 09 12:38:17 PM PDT 24
Peak memory 204028 kb
Host smart-78a78e5f-7f81-4f21-9142-64f2ddc28b41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314315008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.3314315008
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.4177027605
Short name T1471
Test name
Test status
Simulation time 23169279 ps
CPU time 0.79 seconds
Started May 09 12:37:57 PM PDT 24
Finished May 09 12:38:12 PM PDT 24
Peak memory 203732 kb
Host smart-aca55aa0-b84a-4857-ae51-c683549845f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177027605 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.4177027605
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.4169550547
Short name T198
Test name
Test status
Simulation time 336584185 ps
CPU time 0.76 seconds
Started May 09 12:38:10 PM PDT 24
Finished May 09 12:38:29 PM PDT 24
Peak memory 203692 kb
Host smart-eef560c8-2182-4ec4-909b-ffed1e0638b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169550547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.4169550547
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1399947220
Short name T1435
Test name
Test status
Simulation time 46505453 ps
CPU time 0.65 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 203520 kb
Host smart-dd3a63f7-8987-4b92-b44e-0eed46597174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399947220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1399947220
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1277763146
Short name T1394
Test name
Test status
Simulation time 85968272 ps
CPU time 0.83 seconds
Started May 09 12:38:04 PM PDT 24
Finished May 09 12:38:22 PM PDT 24
Peak memory 203776 kb
Host smart-c7b99bdc-3d8b-4a87-bdee-e7b00f028467
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277763146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.1277763146
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.333330928
Short name T1392
Test name
Test status
Simulation time 508812488 ps
CPU time 1.33 seconds
Started May 09 12:38:09 PM PDT 24
Finished May 09 12:38:27 PM PDT 24
Peak memory 203996 kb
Host smart-409a215f-d662-4976-9fd5-6ceb6a746a28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333330928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.333330928
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2353732130
Short name T1457
Test name
Test status
Simulation time 64260000 ps
CPU time 0.91 seconds
Started May 09 12:38:08 PM PDT 24
Finished May 09 12:38:26 PM PDT 24
Peak memory 203772 kb
Host smart-4fd33a8c-718a-4c7e-b6ab-3bf95381b438
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353732130 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2353732130
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.552420501
Short name T96
Test name
Test status
Simulation time 54264945 ps
CPU time 0.69 seconds
Started May 09 12:38:09 PM PDT 24
Finished May 09 12:38:28 PM PDT 24
Peak memory 203660 kb
Host smart-1d507ad7-f0ca-4cbe-97a8-de32c29e78f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552420501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.552420501
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.2708489904
Short name T1460
Test name
Test status
Simulation time 16736041 ps
CPU time 0.66 seconds
Started May 09 12:37:59 PM PDT 24
Finished May 09 12:38:15 PM PDT 24
Peak memory 203572 kb
Host smart-e07ce980-2501-42fd-8b49-9043331053b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708489904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2708489904
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.758394601
Short name T206
Test name
Test status
Simulation time 53728217 ps
CPU time 0.79 seconds
Started May 09 12:38:05 PM PDT 24
Finished May 09 12:38:23 PM PDT 24
Peak memory 203768 kb
Host smart-af6a594b-e562-490e-bf6f-ee46f1dfebbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758394601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_out
standing.758394601
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.2958469088
Short name T169
Test name
Test status
Simulation time 39840511 ps
CPU time 1.81 seconds
Started May 09 12:37:56 PM PDT 24
Finished May 09 12:38:11 PM PDT 24
Peak memory 203964 kb
Host smart-f2d759f9-a57f-417f-b369-81644c8e72b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958469088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2958469088
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.3384113238
Short name T328
Test name
Test status
Simulation time 129199205 ps
CPU time 1.15 seconds
Started May 09 12:45:08 PM PDT 24
Finished May 09 12:45:11 PM PDT 24
Peak memory 204564 kb
Host smart-31e84fc3-d692-4478-bee7-9b47d3b488e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384113238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.3384113238
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.4128546632
Short name T627
Test name
Test status
Simulation time 977711538 ps
CPU time 4.44 seconds
Started May 09 12:45:09 PM PDT 24
Finished May 09 12:45:15 PM PDT 24
Peak memory 251480 kb
Host smart-46fd1ad8-e45e-4ddf-91c1-19ea9079bde6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128546632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.4128546632
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3322028986
Short name T569
Test name
Test status
Simulation time 3291533252 ps
CPU time 45.66 seconds
Started May 09 12:45:10 PM PDT 24
Finished May 09 12:45:57 PM PDT 24
Peak memory 568644 kb
Host smart-c23918e4-f6a3-452b-a0d6-cbd269a2db27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322028986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3322028986
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.987136555
Short name T1018
Test name
Test status
Simulation time 9778298506 ps
CPU time 76.65 seconds
Started May 09 12:45:07 PM PDT 24
Finished May 09 12:46:25 PM PDT 24
Peak memory 766732 kb
Host smart-25d364fd-299e-46ad-b592-19f93340e6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987136555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.987136555
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.866401628
Short name T1027
Test name
Test status
Simulation time 72478934 ps
CPU time 0.84 seconds
Started May 09 12:45:10 PM PDT 24
Finished May 09 12:45:12 PM PDT 24
Peak memory 204076 kb
Host smart-c35a5c1d-e49c-4df3-90dd-29033ee72e86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866401628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt
.866401628
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.3938458886
Short name T1088
Test name
Test status
Simulation time 168042220 ps
CPU time 9.05 seconds
Started May 09 12:45:09 PM PDT 24
Finished May 09 12:45:20 PM PDT 24
Peak memory 234036 kb
Host smart-10717552-29c8-46fd-b256-a87e71230bad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938458886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
3938458886
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.464146666
Short name T290
Test name
Test status
Simulation time 8592327953 ps
CPU time 319.34 seconds
Started May 09 12:45:13 PM PDT 24
Finished May 09 12:50:34 PM PDT 24
Peak memory 1153860 kb
Host smart-772d3d86-ccdf-4dce-a777-7c8e4c98c3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464146666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.464146666
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.1844659366
Short name T1320
Test name
Test status
Simulation time 364111930 ps
CPU time 5.8 seconds
Started May 09 12:45:38 PM PDT 24
Finished May 09 12:45:46 PM PDT 24
Peak memory 204432 kb
Host smart-71cc4c46-9aed-45a8-9369-e7fcf3d5c02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844659366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.1844659366
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.4196520238
Short name T1354
Test name
Test status
Simulation time 1248915511 ps
CPU time 19.45 seconds
Started May 09 12:45:42 PM PDT 24
Finished May 09 12:46:03 PM PDT 24
Peak memory 314348 kb
Host smart-f91f2980-ce20-49e0-8946-7b1d177378a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196520238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.4196520238
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.492784581
Short name T126
Test name
Test status
Simulation time 41772240 ps
CPU time 0.64 seconds
Started May 09 12:45:14 PM PDT 24
Finished May 09 12:45:16 PM PDT 24
Peak memory 204112 kb
Host smart-dc0e16fd-40fb-4633-b8cc-42f9cec0dab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492784581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.492784581
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.4126213561
Short name T167
Test name
Test status
Simulation time 12488696672 ps
CPU time 46.78 seconds
Started May 09 12:45:09 PM PDT 24
Finished May 09 12:45:58 PM PDT 24
Peak memory 204468 kb
Host smart-3001b1da-a84a-4103-86fc-684cba5603eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126213561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.4126213561
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.1531888154
Short name T426
Test name
Test status
Simulation time 1106698965 ps
CPU time 20.26 seconds
Started May 09 12:45:09 PM PDT 24
Finished May 09 12:45:31 PM PDT 24
Peak memory 282364 kb
Host smart-47280d9b-b8b7-4de6-a841-b42d9a683258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531888154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.1531888154
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.3849771692
Short name T1034
Test name
Test status
Simulation time 107280026610 ps
CPU time 1233.15 seconds
Started May 09 12:45:07 PM PDT 24
Finished May 09 01:05:42 PM PDT 24
Peak memory 2461404 kb
Host smart-e024d638-7f70-4af5-a254-2de79941c18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849771692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.3849771692
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.2264776636
Short name T710
Test name
Test status
Simulation time 2303208388 ps
CPU time 10.49 seconds
Started May 09 12:45:10 PM PDT 24
Finished May 09 12:45:23 PM PDT 24
Peak memory 220920 kb
Host smart-bd37f4af-00e3-43ef-92ba-51b4b3799862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264776636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.2264776636
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.2949950009
Short name T879
Test name
Test status
Simulation time 2059907586 ps
CPU time 4.91 seconds
Started May 09 12:45:25 PM PDT 24
Finished May 09 12:45:33 PM PDT 24
Peak memory 212632 kb
Host smart-3a67b60c-8991-44a4-b07a-f33a84aef0af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949950009 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.2949950009
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.259735430
Short name T292
Test name
Test status
Simulation time 10444239520 ps
CPU time 14.25 seconds
Started May 09 12:45:24 PM PDT 24
Finished May 09 12:45:40 PM PDT 24
Peak memory 281124 kb
Host smart-b6b203d8-b21d-430b-9cf8-1f3da57bb02a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259735430 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_acq.259735430
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.555751731
Short name T1359
Test name
Test status
Simulation time 10053243281 ps
CPU time 84.35 seconds
Started May 09 12:45:25 PM PDT 24
Finished May 09 12:46:52 PM PDT 24
Peak memory 507888 kb
Host smart-fceae628-4d5b-4b62-ab0a-8ad2dc9bafe7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555751731 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_fifo_reset_tx.555751731
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.236784183
Short name T24
Test name
Test status
Simulation time 475251203 ps
CPU time 2.17 seconds
Started May 09 12:45:40 PM PDT 24
Finished May 09 12:45:44 PM PDT 24
Peak memory 204396 kb
Host smart-5f595d7f-5a89-4609-8b42-54781b1da4a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236784183 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 0.i2c_target_hrst.236784183
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.2066820613
Short name T840
Test name
Test status
Simulation time 3270819242 ps
CPU time 4.59 seconds
Started May 09 12:45:23 PM PDT 24
Finished May 09 12:45:29 PM PDT 24
Peak memory 208812 kb
Host smart-9b8a7b7a-39b9-4dae-8e61-0cd5de1a5bbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066820613 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.2066820613
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.887525817
Short name T1165
Test name
Test status
Simulation time 12041452200 ps
CPU time 65.35 seconds
Started May 09 12:45:24 PM PDT 24
Finished May 09 12:46:31 PM PDT 24
Peak memory 1509992 kb
Host smart-559458d7-8c0e-4eb6-a06e-f9040503bee2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887525817 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.887525817
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.2137495522
Short name T164
Test name
Test status
Simulation time 920700384 ps
CPU time 10.96 seconds
Started May 09 12:45:23 PM PDT 24
Finished May 09 12:45:36 PM PDT 24
Peak memory 204364 kb
Host smart-59359266-0bb6-4347-8475-61ea50b8c697
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137495522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.2137495522
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.483200671
Short name T843
Test name
Test status
Simulation time 879892852 ps
CPU time 16.03 seconds
Started May 09 12:45:24 PM PDT 24
Finished May 09 12:45:42 PM PDT 24
Peak memory 211688 kb
Host smart-411b92f4-a71a-447e-8ad9-1d521dbcb855
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483200671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_rd.483200671
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.2036592010
Short name T1195
Test name
Test status
Simulation time 50962411773 ps
CPU time 1191.98 seconds
Started May 09 12:45:24 PM PDT 24
Finished May 09 01:05:19 PM PDT 24
Peak memory 7785188 kb
Host smart-f6ac60eb-4bdc-429c-b4e5-1af6678463c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036592010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.2036592010
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.2633172794
Short name T761
Test name
Test status
Simulation time 8177770833 ps
CPU time 21.34 seconds
Started May 09 12:45:23 PM PDT 24
Finished May 09 12:45:46 PM PDT 24
Peak memory 405912 kb
Host smart-7e5cd2eb-fea0-45a6-95e8-2b8e3a304d2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633172794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.2633172794
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.1420792978
Short name T732
Test name
Test status
Simulation time 2472741156 ps
CPU time 7.18 seconds
Started May 09 12:45:24 PM PDT 24
Finished May 09 12:45:34 PM PDT 24
Peak memory 212732 kb
Host smart-4dd0047d-ff4d-4d77-9f08-9353afe6414b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420792978 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.1420792978
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.2651291337
Short name T907
Test name
Test status
Simulation time 30353704 ps
CPU time 0.62 seconds
Started May 09 12:45:42 PM PDT 24
Finished May 09 12:45:44 PM PDT 24
Peak memory 204216 kb
Host smart-828f5daa-d7c5-4819-bccd-4336355b4639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651291337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.2651291337
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.3776255814
Short name T1184
Test name
Test status
Simulation time 141536808 ps
CPU time 1.6 seconds
Started May 09 12:45:37 PM PDT 24
Finished May 09 12:45:40 PM PDT 24
Peak memory 215804 kb
Host smart-45413d96-1d53-4471-9be6-7f9a288e1d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776255814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3776255814
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.291532795
Short name T168
Test name
Test status
Simulation time 846252341 ps
CPU time 7.39 seconds
Started May 09 12:45:40 PM PDT 24
Finished May 09 12:45:49 PM PDT 24
Peak memory 229336 kb
Host smart-f09c2dfa-f7ca-4f8d-9097-47dc9c4a4563
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291532795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.291532795
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.2060128404
Short name T1162
Test name
Test status
Simulation time 3753148758 ps
CPU time 58.67 seconds
Started May 09 12:45:39 PM PDT 24
Finished May 09 12:46:40 PM PDT 24
Peak memory 670624 kb
Host smart-a0ae8ccd-ca47-4922-95c3-84c6fcabb747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060128404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.2060128404
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.555987515
Short name T1049
Test name
Test status
Simulation time 3842473616 ps
CPU time 127.99 seconds
Started May 09 12:45:39 PM PDT 24
Finished May 09 12:47:49 PM PDT 24
Peak memory 620444 kb
Host smart-9a0825bd-ca1c-4cbf-a470-717eeb014505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555987515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.555987515
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.3506259591
Short name T1154
Test name
Test status
Simulation time 371092913 ps
CPU time 0.86 seconds
Started May 09 12:45:37 PM PDT 24
Finished May 09 12:45:40 PM PDT 24
Peak memory 204072 kb
Host smart-6ba7c2e9-421b-41f4-9ea2-0614a62e8be3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506259591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.3506259591
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.3057619910
Short name T730
Test name
Test status
Simulation time 254898875 ps
CPU time 7.03 seconds
Started May 09 12:45:39 PM PDT 24
Finished May 09 12:45:48 PM PDT 24
Peak memory 204416 kb
Host smart-0eb52b84-2a65-400c-b14b-9f46bccfa8be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057619910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
3057619910
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.480433015
Short name T602
Test name
Test status
Simulation time 4228877473 ps
CPU time 307.85 seconds
Started May 09 12:45:37 PM PDT 24
Finished May 09 12:50:45 PM PDT 24
Peak memory 1243780 kb
Host smart-610125e0-36c8-4b84-8f27-ad91e6bf1c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480433015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.480433015
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.3957895178
Short name T590
Test name
Test status
Simulation time 488414939 ps
CPU time 7.63 seconds
Started May 09 12:45:42 PM PDT 24
Finished May 09 12:45:51 PM PDT 24
Peak memory 204344 kb
Host smart-6ca81fa0-fd70-4900-b9fb-d71b1a10e470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957895178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.3957895178
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.3167308192
Short name T1201
Test name
Test status
Simulation time 1215632149 ps
CPU time 21.1 seconds
Started May 09 12:45:41 PM PDT 24
Finished May 09 12:46:03 PM PDT 24
Peak memory 350432 kb
Host smart-60ceafc9-dc6d-41a2-b115-3390f47bcb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167308192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.3167308192
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.2738705366
Short name T1296
Test name
Test status
Simulation time 21639107 ps
CPU time 0.75 seconds
Started May 09 12:45:37 PM PDT 24
Finished May 09 12:45:39 PM PDT 24
Peak memory 204076 kb
Host smart-59dd9f8f-0e9b-4c53-aa18-ec8d56cff3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738705366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2738705366
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.3842434707
Short name T220
Test name
Test status
Simulation time 5273579165 ps
CPU time 215.13 seconds
Started May 09 12:45:37 PM PDT 24
Finished May 09 12:49:14 PM PDT 24
Peak memory 246092 kb
Host smart-60e4278f-69b0-4557-8f52-485a62c17468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842434707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.3842434707
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.1236927413
Short name T839
Test name
Test status
Simulation time 20630532112 ps
CPU time 21.94 seconds
Started May 09 12:45:38 PM PDT 24
Finished May 09 12:46:02 PM PDT 24
Peak memory 301944 kb
Host smart-6f64cca9-959f-460d-adee-7d889462a370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236927413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.1236927413
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.790500313
Short name T1187
Test name
Test status
Simulation time 5412134675 ps
CPU time 89.79 seconds
Started May 09 12:45:37 PM PDT 24
Finished May 09 12:47:08 PM PDT 24
Peak memory 713052 kb
Host smart-8e25c02a-f159-4c57-9e24-7fb219d57002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790500313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.790500313
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.2198056755
Short name T925
Test name
Test status
Simulation time 1120759649 ps
CPU time 10.19 seconds
Started May 09 12:45:36 PM PDT 24
Finished May 09 12:45:47 PM PDT 24
Peak memory 212776 kb
Host smart-06e53830-b6a7-4686-a652-1d2e37d0909c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198056755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2198056755
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.1680014985
Short name T157
Test name
Test status
Simulation time 94460365 ps
CPU time 0.93 seconds
Started May 09 12:45:41 PM PDT 24
Finished May 09 12:45:44 PM PDT 24
Peak memory 222424 kb
Host smart-9cc03594-c34b-435a-8171-c1d9b6600827
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680014985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.1680014985
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.1612506643
Short name T894
Test name
Test status
Simulation time 1066631593 ps
CPU time 2.99 seconds
Started May 09 12:45:39 PM PDT 24
Finished May 09 12:45:44 PM PDT 24
Peak memory 204428 kb
Host smart-00fef1a4-1db4-49b4-b05a-ea145a1cd311
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612506643 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.1612506643
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.921564277
Short name T6
Test name
Test status
Simulation time 10102587192 ps
CPU time 66.83 seconds
Started May 09 12:45:38 PM PDT 24
Finished May 09 12:46:46 PM PDT 24
Peak memory 530564 kb
Host smart-b4afe046-2a26-41f1-a37a-51e57bd71c1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921564277 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_acq.921564277
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.2907368212
Short name T735
Test name
Test status
Simulation time 10580707201 ps
CPU time 13.08 seconds
Started May 09 12:45:39 PM PDT 24
Finished May 09 12:45:54 PM PDT 24
Peak memory 257804 kb
Host smart-cccaa7d7-b382-4f37-9ee5-2cc369fb5c1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907368212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.2907368212
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.819813559
Short name T20
Test name
Test status
Simulation time 2609562652 ps
CPU time 12.93 seconds
Started May 09 12:45:41 PM PDT 24
Finished May 09 12:45:56 PM PDT 24
Peak memory 213016 kb
Host smart-1b9690ad-1486-4163-80c3-5153f60e7f63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819813559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.819813559
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.2855810006
Short name T549
Test name
Test status
Simulation time 439252997 ps
CPU time 2.52 seconds
Started May 09 12:45:39 PM PDT 24
Finished May 09 12:45:43 PM PDT 24
Peak memory 204448 kb
Host smart-0a8d428b-7e42-4822-9893-a29c4e40fba1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855810006 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.2855810006
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.4224355302
Short name T323
Test name
Test status
Simulation time 3831679590 ps
CPU time 4.87 seconds
Started May 09 12:45:38 PM PDT 24
Finished May 09 12:45:45 PM PDT 24
Peak memory 204516 kb
Host smart-09d7d830-d84f-4acb-b9db-4353f3cccb2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224355302 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.4224355302
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.3975220073
Short name T1038
Test name
Test status
Simulation time 12405572203 ps
CPU time 201.08 seconds
Started May 09 12:45:37 PM PDT 24
Finished May 09 12:49:00 PM PDT 24
Peak memory 2979236 kb
Host smart-047e3026-dbde-4db2-870b-15515c3358e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975220073 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.3975220073
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.2786431420
Short name T926
Test name
Test status
Simulation time 1754246726 ps
CPU time 11.85 seconds
Started May 09 12:45:38 PM PDT 24
Finished May 09 12:45:51 PM PDT 24
Peak memory 204476 kb
Host smart-d7389536-127b-4c6b-94c9-9f4449242c41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786431420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.2786431420
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.2225062096
Short name T995
Test name
Test status
Simulation time 1478683020 ps
CPU time 23.91 seconds
Started May 09 12:45:39 PM PDT 24
Finished May 09 12:46:05 PM PDT 24
Peak memory 217912 kb
Host smart-25be5859-870a-483e-8638-b35a25c0d27f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225062096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.2225062096
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.4057786972
Short name T1234
Test name
Test status
Simulation time 53255040309 ps
CPU time 1236.63 seconds
Started May 09 12:45:37 PM PDT 24
Finished May 09 01:06:16 PM PDT 24
Peak memory 8159964 kb
Host smart-fb251adc-e5f0-4ce0-a8e8-c37e191e3b23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057786972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.4057786972
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.2447986439
Short name T440
Test name
Test status
Simulation time 44184275206 ps
CPU time 1290.67 seconds
Started May 09 12:45:39 PM PDT 24
Finished May 09 01:07:12 PM PDT 24
Peak memory 5047080 kb
Host smart-2d75c1b7-021f-4926-bfbb-b6a631205ed5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447986439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.2447986439
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.2796853819
Short name T1236
Test name
Test status
Simulation time 3370280776 ps
CPU time 7.28 seconds
Started May 09 12:45:41 PM PDT 24
Finished May 09 12:45:50 PM PDT 24
Peak memory 219732 kb
Host smart-6e06daba-2f6b-4eb2-9587-879c9a7ee5d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796853819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.2796853819
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.3288102219
Short name T954
Test name
Test status
Simulation time 42109135 ps
CPU time 0.61 seconds
Started May 09 12:47:25 PM PDT 24
Finished May 09 12:47:28 PM PDT 24
Peak memory 204084 kb
Host smart-6fdb725a-adbb-42a3-9315-1fbefea99d02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288102219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.3288102219
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.3142511542
Short name T526
Test name
Test status
Simulation time 101400547 ps
CPU time 1.19 seconds
Started May 09 12:47:16 PM PDT 24
Finished May 09 12:47:19 PM PDT 24
Peak memory 204576 kb
Host smart-785e9784-a6ee-4f13-806d-11cfb6e5dd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142511542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.3142511542
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.3539655251
Short name T655
Test name
Test status
Simulation time 345207138 ps
CPU time 6.41 seconds
Started May 09 12:47:14 PM PDT 24
Finished May 09 12:47:24 PM PDT 24
Peak memory 280320 kb
Host smart-f769eb3b-13b4-4b1e-8a5b-695146d787b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539655251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.3539655251
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.229307642
Short name T1249
Test name
Test status
Simulation time 6170398022 ps
CPU time 32.91 seconds
Started May 09 12:47:15 PM PDT 24
Finished May 09 12:47:51 PM PDT 24
Peak memory 382160 kb
Host smart-35a68f2f-1e08-475c-8931-cdee47c0b689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229307642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.229307642
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.1298857614
Short name T332
Test name
Test status
Simulation time 1256420712 ps
CPU time 38.58 seconds
Started May 09 12:47:14 PM PDT 24
Finished May 09 12:47:56 PM PDT 24
Peak memory 507308 kb
Host smart-d5c55edd-16e5-4ea2-b15c-891eed3b73c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298857614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1298857614
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.3237841451
Short name T697
Test name
Test status
Simulation time 95117380 ps
CPU time 0.91 seconds
Started May 09 12:47:12 PM PDT 24
Finished May 09 12:47:16 PM PDT 24
Peak memory 204216 kb
Host smart-d5de5373-b6b2-4144-9cad-4d579d0b59fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237841451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.3237841451
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.3299321086
Short name T536
Test name
Test status
Simulation time 634927977 ps
CPU time 8.38 seconds
Started May 09 12:47:15 PM PDT 24
Finished May 09 12:47:26 PM PDT 24
Peak memory 231240 kb
Host smart-8194b574-8ffd-4dc5-bd49-934758939e4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299321086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.3299321086
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.708323993
Short name T142
Test name
Test status
Simulation time 3903576049 ps
CPU time 117.58 seconds
Started May 09 12:47:11 PM PDT 24
Finished May 09 12:49:10 PM PDT 24
Peak memory 1118388 kb
Host smart-83e91fcd-fbcb-43bf-b898-9530a6ff5fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708323993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.708323993
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.2944429820
Short name T363
Test name
Test status
Simulation time 1523615760 ps
CPU time 28.98 seconds
Started May 09 12:47:23 PM PDT 24
Finished May 09 12:47:54 PM PDT 24
Peak memory 316592 kb
Host smart-cbda98e3-5440-4f7c-917b-19d109e43480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944429820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.2944429820
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.3764982915
Short name T123
Test name
Test status
Simulation time 30111830 ps
CPU time 0.73 seconds
Started May 09 12:47:12 PM PDT 24
Finished May 09 12:47:14 PM PDT 24
Peak memory 204156 kb
Host smart-f32424c0-27ae-42aa-87ae-c273f65d22c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764982915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3764982915
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.460080546
Short name T1059
Test name
Test status
Simulation time 74664395321 ps
CPU time 417.8 seconds
Started May 09 12:47:12 PM PDT 24
Finished May 09 12:54:12 PM PDT 24
Peak memory 2167352 kb
Host smart-92ec12ca-9961-4aad-b735-8e8b3c4a0eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460080546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.460080546
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.1788286667
Short name T279
Test name
Test status
Simulation time 3915375134 ps
CPU time 48.05 seconds
Started May 09 12:47:13 PM PDT 24
Finished May 09 12:48:04 PM PDT 24
Peak memory 310372 kb
Host smart-427ca905-d551-4a5c-a910-849b68a07bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788286667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.1788286667
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.4165902115
Short name T495
Test name
Test status
Simulation time 50749140151 ps
CPU time 697.76 seconds
Started May 09 12:47:12 PM PDT 24
Finished May 09 12:58:53 PM PDT 24
Peak memory 2721468 kb
Host smart-109c683e-2620-4df1-86b0-398f2d1f524e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165902115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.4165902115
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.2262725768
Short name T1009
Test name
Test status
Simulation time 776971434 ps
CPU time 15.57 seconds
Started May 09 12:47:11 PM PDT 24
Finished May 09 12:47:29 PM PDT 24
Peak memory 220856 kb
Host smart-374a0d00-d2f7-40d0-bf40-a5003dd9c858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262725768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.2262725768
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.278599321
Short name T1239
Test name
Test status
Simulation time 1503404917 ps
CPU time 2.18 seconds
Started May 09 12:47:25 PM PDT 24
Finished May 09 12:47:31 PM PDT 24
Peak memory 204496 kb
Host smart-c7b7d061-ff5a-4cc1-8d53-9ee8702b3ae5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278599321 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.278599321
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.328311101
Short name T60
Test name
Test status
Simulation time 10084507037 ps
CPU time 78.64 seconds
Started May 09 12:47:14 PM PDT 24
Finished May 09 12:48:36 PM PDT 24
Peak memory 432520 kb
Host smart-3e288c89-8d65-446d-85b0-a40f896308b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328311101 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_acq.328311101
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.1960307224
Short name T793
Test name
Test status
Simulation time 10225037276 ps
CPU time 27.77 seconds
Started May 09 12:47:14 PM PDT 24
Finished May 09 12:47:45 PM PDT 24
Peak memory 313540 kb
Host smart-f464a7bc-81e1-4d40-9f3f-fddf2a99c2ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960307224 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.1960307224
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.1220715409
Short name T724
Test name
Test status
Simulation time 380446416 ps
CPU time 2.55 seconds
Started May 09 12:47:25 PM PDT 24
Finished May 09 12:47:31 PM PDT 24
Peak memory 204372 kb
Host smart-50617df7-2167-488d-98e7-d42c40e7ed5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220715409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.1220715409
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.20282075
Short name T299
Test name
Test status
Simulation time 1134556524 ps
CPU time 6.07 seconds
Started May 09 12:47:13 PM PDT 24
Finished May 09 12:47:22 PM PDT 24
Peak memory 212608 kb
Host smart-41705d93-1633-461f-a305-b36454852ef5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20282075 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_intr_smoke.20282075
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.2926583054
Short name T250
Test name
Test status
Simulation time 13664481232 ps
CPU time 31.24 seconds
Started May 09 12:47:16 PM PDT 24
Finished May 09 12:47:50 PM PDT 24
Peak memory 864904 kb
Host smart-a3c26146-2583-4704-b4d8-dbbea4c80c9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926583054 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.2926583054
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.3244857106
Short name T910
Test name
Test status
Simulation time 443551322 ps
CPU time 14.61 seconds
Started May 09 12:47:12 PM PDT 24
Finished May 09 12:47:29 PM PDT 24
Peak memory 204416 kb
Host smart-52cf86c6-897e-4d98-9ac4-3e1043d62ae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244857106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.3244857106
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.1451646656
Short name T1134
Test name
Test status
Simulation time 2150485889 ps
CPU time 16.25 seconds
Started May 09 12:47:16 PM PDT 24
Finished May 09 12:47:35 PM PDT 24
Peak memory 219864 kb
Host smart-ea99ac30-2171-41a7-afc5-61f4649e51b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451646656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.1451646656
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.2261983046
Short name T583
Test name
Test status
Simulation time 27639035945 ps
CPU time 127.41 seconds
Started May 09 12:47:13 PM PDT 24
Finished May 09 12:49:23 PM PDT 24
Peak memory 1933460 kb
Host smart-09cb534e-eb5d-432a-8320-ccbd903acca6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261983046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.2261983046
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.325389882
Short name T384
Test name
Test status
Simulation time 5168732034 ps
CPU time 8.74 seconds
Started May 09 12:47:16 PM PDT 24
Finished May 09 12:47:28 PM PDT 24
Peak memory 273236 kb
Host smart-19e6518b-3da3-48ac-bd0c-58546a5ef04f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325389882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_t
arget_stretch.325389882
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.1731897501
Short name T1019
Test name
Test status
Simulation time 1167032799 ps
CPU time 7.15 seconds
Started May 09 12:47:16 PM PDT 24
Finished May 09 12:47:26 PM PDT 24
Peak memory 220508 kb
Host smart-9f1a5b2e-8176-477f-b778-99b569cbfffe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731897501 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.1731897501
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.3660512342
Short name T733
Test name
Test status
Simulation time 18297227 ps
CPU time 0.6 seconds
Started May 09 12:47:38 PM PDT 24
Finished May 09 12:47:42 PM PDT 24
Peak memory 204216 kb
Host smart-4ef23ef2-6438-414a-8b17-5d50adc0ae01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660512342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.3660512342
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.2232712202
Short name T988
Test name
Test status
Simulation time 304282506 ps
CPU time 1.33 seconds
Started May 09 12:47:23 PM PDT 24
Finished May 09 12:47:26 PM PDT 24
Peak memory 212676 kb
Host smart-0fbc081b-fadd-4265-8828-a0138ada8d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232712202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.2232712202
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.3002343299
Short name T265
Test name
Test status
Simulation time 281046458 ps
CPU time 5.01 seconds
Started May 09 12:47:26 PM PDT 24
Finished May 09 12:47:34 PM PDT 24
Peak memory 259820 kb
Host smart-ddaf4caf-0b16-4c8d-9001-9332e72ff1cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002343299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.3002343299
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.208405006
Short name T1199
Test name
Test status
Simulation time 2147389603 ps
CPU time 54.52 seconds
Started May 09 12:47:28 PM PDT 24
Finished May 09 12:48:26 PM PDT 24
Peak memory 556268 kb
Host smart-1e0a5643-52b5-41f3-ad65-09117f27dfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208405006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.208405006
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.2113253493
Short name T698
Test name
Test status
Simulation time 5630769275 ps
CPU time 97.57 seconds
Started May 09 12:47:23 PM PDT 24
Finished May 09 12:49:02 PM PDT 24
Peak memory 501516 kb
Host smart-36da211d-f892-42f7-9ed8-f176ba9395ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113253493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.2113253493
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.3063366433
Short name T1336
Test name
Test status
Simulation time 418964237 ps
CPU time 0.81 seconds
Started May 09 12:47:24 PM PDT 24
Finished May 09 12:47:27 PM PDT 24
Peak memory 204184 kb
Host smart-db613e35-8888-4e98-ad1b-8593f9fe5102
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063366433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.3063366433
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.1287916566
Short name T504
Test name
Test status
Simulation time 134673634 ps
CPU time 3.34 seconds
Started May 09 12:47:30 PM PDT 24
Finished May 09 12:47:35 PM PDT 24
Peak memory 223492 kb
Host smart-b7784864-7b0d-4311-b954-3ed978c3049e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287916566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.1287916566
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.4012689443
Short name T1205
Test name
Test status
Simulation time 13969654157 ps
CPU time 259.26 seconds
Started May 09 12:47:26 PM PDT 24
Finished May 09 12:51:48 PM PDT 24
Peak memory 1048092 kb
Host smart-160957b0-7e39-48f0-af35-7ee865541dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012689443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.4012689443
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.3823089416
Short name T854
Test name
Test status
Simulation time 1328952326 ps
CPU time 9.64 seconds
Started May 09 12:47:36 PM PDT 24
Finished May 09 12:47:49 PM PDT 24
Peak memory 204344 kb
Host smart-fccbe6f5-e6af-4b13-b612-df6c85742a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823089416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.3823089416
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.3210745709
Short name T1274
Test name
Test status
Simulation time 1459143831 ps
CPU time 62.09 seconds
Started May 09 12:47:35 PM PDT 24
Finished May 09 12:48:41 PM PDT 24
Peak memory 346516 kb
Host smart-5f62fedc-da64-4202-abb1-22841e3ff59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210745709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.3210745709
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_perf.1775859215
Short name T419
Test name
Test status
Simulation time 7875562337 ps
CPU time 83.8 seconds
Started May 09 12:47:25 PM PDT 24
Finished May 09 12:48:51 PM PDT 24
Peak memory 204488 kb
Host smart-850ea0ec-16bc-4edb-9af9-5081211f90ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775859215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.1775859215
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.3397999603
Short name T671
Test name
Test status
Simulation time 1352425061 ps
CPU time 24.08 seconds
Started May 09 12:47:24 PM PDT 24
Finished May 09 12:47:51 PM PDT 24
Peak memory 356972 kb
Host smart-5d9daa82-3311-423f-93af-83c79a8c2cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397999603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.3397999603
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.4045732730
Short name T243
Test name
Test status
Simulation time 20260580863 ps
CPU time 554.91 seconds
Started May 09 12:47:24 PM PDT 24
Finished May 09 12:56:41 PM PDT 24
Peak memory 1467856 kb
Host smart-08b1292b-290f-44b3-b7e1-7ed2ea3cc0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045732730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.4045732730
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.2622325551
Short name T117
Test name
Test status
Simulation time 2597686898 ps
CPU time 18.23 seconds
Started May 09 12:47:22 PM PDT 24
Finished May 09 12:47:42 PM PDT 24
Peak memory 212692 kb
Host smart-a17f4818-7c52-4f0b-ae1d-ddb637c0aebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622325551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.2622325551
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.4082530699
Short name T532
Test name
Test status
Simulation time 5253865562 ps
CPU time 5.62 seconds
Started May 09 12:47:24 PM PDT 24
Finished May 09 12:47:32 PM PDT 24
Peak memory 212664 kb
Host smart-3641289b-623d-416c-85ff-2112f1709d98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082530699 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.4082530699
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.1234182127
Short name T644
Test name
Test status
Simulation time 10192254038 ps
CPU time 5.33 seconds
Started May 09 12:47:28 PM PDT 24
Finished May 09 12:47:36 PM PDT 24
Peak memory 221196 kb
Host smart-9c0bb831-5d88-4911-8447-6e550952e6e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234182127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.1234182127
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.3790908756
Short name T980
Test name
Test status
Simulation time 10354802649 ps
CPU time 15.99 seconds
Started May 09 12:47:25 PM PDT 24
Finished May 09 12:47:44 PM PDT 24
Peak memory 288704 kb
Host smart-fad20d54-4f79-403f-9885-f66f186eb736
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790908756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.3790908756
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.1275733813
Short name T25
Test name
Test status
Simulation time 1757498120 ps
CPU time 2.59 seconds
Started May 09 12:47:24 PM PDT 24
Finished May 09 12:47:30 PM PDT 24
Peak memory 204452 kb
Host smart-c74faac6-eaf8-46dd-82f7-921b3a47e2bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275733813 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.1275733813
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.1332376597
Short name T254
Test name
Test status
Simulation time 3589829395 ps
CPU time 4.99 seconds
Started May 09 12:47:30 PM PDT 24
Finished May 09 12:47:38 PM PDT 24
Peak memory 204552 kb
Host smart-f0461d87-2d83-42b4-bd1a-52a4e39b63da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332376597 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.1332376597
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.1890361619
Short name T146
Test name
Test status
Simulation time 21318126341 ps
CPU time 380.46 seconds
Started May 09 12:47:29 PM PDT 24
Finished May 09 12:53:52 PM PDT 24
Peak memory 3500980 kb
Host smart-efd864a8-c474-409a-bf20-a5b9d8f0aae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890361619 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.1890361619
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.533882981
Short name T150
Test name
Test status
Simulation time 1063536876 ps
CPU time 45.64 seconds
Started May 09 12:47:24 PM PDT 24
Finished May 09 12:48:12 PM PDT 24
Peak memory 204440 kb
Host smart-75a05264-8d15-4927-afab-9622095ab274
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533882981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_tar
get_smoke.533882981
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.1472181037
Short name T496
Test name
Test status
Simulation time 1196280726 ps
CPU time 49.6 seconds
Started May 09 12:47:22 PM PDT 24
Finished May 09 12:48:14 PM PDT 24
Peak memory 204784 kb
Host smart-89040eb8-11dd-47c4-96ce-f05292b2fa62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472181037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.1472181037
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.791995777
Short name T421
Test name
Test status
Simulation time 8577057477 ps
CPU time 6.02 seconds
Started May 09 12:47:24 PM PDT 24
Finished May 09 12:47:32 PM PDT 24
Peak memory 204480 kb
Host smart-c6af2e5e-bcd9-4030-ba45-defd16c032d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791995777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_wr.791995777
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.187422303
Short name T742
Test name
Test status
Simulation time 29284708099 ps
CPU time 1753.65 seconds
Started May 09 12:47:28 PM PDT 24
Finished May 09 01:16:45 PM PDT 24
Peak memory 6564872 kb
Host smart-7d7c2e2f-3739-4a27-9932-bd503c05616a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187422303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_t
arget_stretch.187422303
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_alert_test.4283735784
Short name T284
Test name
Test status
Simulation time 33060073 ps
CPU time 0.61 seconds
Started May 09 12:47:35 PM PDT 24
Finished May 09 12:47:39 PM PDT 24
Peak memory 204148 kb
Host smart-43fc1ed4-7adc-4a88-8ae7-2760a319eb5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283735784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.4283735784
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3452887536
Short name T1175
Test name
Test status
Simulation time 102374739 ps
CPU time 1.76 seconds
Started May 09 12:47:34 PM PDT 24
Finished May 09 12:47:40 PM PDT 24
Peak memory 212772 kb
Host smart-35a66a3d-48fc-4aaa-bdc7-4ae9b6ef2151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452887536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3452887536
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.3684962778
Short name T398
Test name
Test status
Simulation time 259961968 ps
CPU time 5.88 seconds
Started May 09 12:47:34 PM PDT 24
Finished May 09 12:47:43 PM PDT 24
Peak memory 256048 kb
Host smart-2dd600d1-3577-4e40-8fd0-061eeae3d73a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684962778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.3684962778
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.2209378114
Short name T1032
Test name
Test status
Simulation time 4940253389 ps
CPU time 80.49 seconds
Started May 09 12:47:37 PM PDT 24
Finished May 09 12:49:01 PM PDT 24
Peak memory 747496 kb
Host smart-a67d1d9e-bffe-4d25-ae67-3857f1f6ac8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209378114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.2209378114
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.4289804754
Short name T1282
Test name
Test status
Simulation time 6843540928 ps
CPU time 76.89 seconds
Started May 09 12:47:44 PM PDT 24
Finished May 09 12:49:03 PM PDT 24
Peak memory 708640 kb
Host smart-fed44d24-e915-49ac-bc0a-822656bad393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289804754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.4289804754
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.2533765035
Short name T1052
Test name
Test status
Simulation time 1024411060 ps
CPU time 1 seconds
Started May 09 12:47:33 PM PDT 24
Finished May 09 12:47:37 PM PDT 24
Peak memory 204404 kb
Host smart-82925096-5eb5-44f0-9eb9-e8b103e7c456
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533765035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.2533765035
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.2727994063
Short name T1045
Test name
Test status
Simulation time 260282748 ps
CPU time 4.07 seconds
Started May 09 12:47:37 PM PDT 24
Finished May 09 12:47:45 PM PDT 24
Peak memory 227028 kb
Host smart-483665b9-e289-4804-9b11-2c304b486980
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727994063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.2727994063
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.3955835986
Short name T1001
Test name
Test status
Simulation time 10675008857 ps
CPU time 300.83 seconds
Started May 09 12:47:38 PM PDT 24
Finished May 09 12:52:42 PM PDT 24
Peak memory 1186296 kb
Host smart-88d07f0d-d7b6-4551-a723-f6c795879444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955835986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.3955835986
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.961617980
Short name T280
Test name
Test status
Simulation time 240606903 ps
CPU time 4.9 seconds
Started May 09 12:47:36 PM PDT 24
Finished May 09 12:47:45 PM PDT 24
Peak memory 204444 kb
Host smart-abfed3c7-f6c3-4220-85bc-fb2d492c0e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961617980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.961617980
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.1820369425
Short name T71
Test name
Test status
Simulation time 5814359013 ps
CPU time 49.77 seconds
Started May 09 12:47:34 PM PDT 24
Finished May 09 12:48:27 PM PDT 24
Peak memory 342396 kb
Host smart-7362b0a9-3768-4312-bb6e-7049136a0c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820369425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.1820369425
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.169588354
Short name T462
Test name
Test status
Simulation time 77111511 ps
CPU time 0.66 seconds
Started May 09 12:47:33 PM PDT 24
Finished May 09 12:47:37 PM PDT 24
Peak memory 204136 kb
Host smart-bf6ea3ba-60fc-4974-9eb8-164fc00b5370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169588354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.169588354
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.2820215041
Short name T379
Test name
Test status
Simulation time 30973152425 ps
CPU time 119.22 seconds
Started May 09 12:47:36 PM PDT 24
Finished May 09 12:49:39 PM PDT 24
Peak memory 212712 kb
Host smart-f8ca5eea-5ed2-4b7d-977f-b77bc2f12034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820215041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2820215041
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.1064455901
Short name T908
Test name
Test status
Simulation time 10538966685 ps
CPU time 25.7 seconds
Started May 09 12:47:34 PM PDT 24
Finished May 09 12:48:03 PM PDT 24
Peak memory 284920 kb
Host smart-ca93ce16-bbd9-48a1-afc2-4b3fefa1f33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064455901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.1064455901
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.324544523
Short name T1307
Test name
Test status
Simulation time 7018877974 ps
CPU time 683.12 seconds
Started May 09 12:47:36 PM PDT 24
Finished May 09 12:59:03 PM PDT 24
Peak memory 1416008 kb
Host smart-39d7e404-3496-4cac-9f37-7eba1c37d8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324544523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.324544523
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.2567223106
Short name T727
Test name
Test status
Simulation time 711836928 ps
CPU time 32.08 seconds
Started May 09 12:47:34 PM PDT 24
Finished May 09 12:48:10 PM PDT 24
Peak memory 212616 kb
Host smart-96c5a61e-f21f-49f0-81a4-f5967645ad6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567223106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.2567223106
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.2461196532
Short name T875
Test name
Test status
Simulation time 1006473947 ps
CPU time 4.76 seconds
Started May 09 12:47:44 PM PDT 24
Finished May 09 12:47:51 PM PDT 24
Peak memory 212616 kb
Host smart-5f2d4059-c75b-47f2-97d5-8c5df21d1ca7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461196532 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.2461196532
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.1215613902
Short name T1254
Test name
Test status
Simulation time 10144944032 ps
CPU time 31.63 seconds
Started May 09 12:47:34 PM PDT 24
Finished May 09 12:48:08 PM PDT 24
Peak memory 373196 kb
Host smart-d4072455-c9b9-41e6-8605-3768fa44080d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215613902 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.1215613902
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.3731303094
Short name T964
Test name
Test status
Simulation time 1696747841 ps
CPU time 2.69 seconds
Started May 09 12:47:44 PM PDT 24
Finished May 09 12:47:48 PM PDT 24
Peak memory 204428 kb
Host smart-c93ce4fc-d736-4fa5-89e2-6eb98f3032b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731303094 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.3731303094
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.1874184260
Short name T240
Test name
Test status
Simulation time 4053065492 ps
CPU time 5.1 seconds
Started May 09 12:47:35 PM PDT 24
Finished May 09 12:47:44 PM PDT 24
Peak memory 204540 kb
Host smart-d6577153-999f-4d89-8a42-0cae1a5881ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874184260 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.1874184260
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.4154053219
Short name T234
Test name
Test status
Simulation time 11079819898 ps
CPU time 58.54 seconds
Started May 09 12:47:36 PM PDT 24
Finished May 09 12:48:38 PM PDT 24
Peak memory 1361488 kb
Host smart-284c0d01-3e01-485d-8592-d2edfae09427
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154053219 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.4154053219
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.1153859944
Short name T447
Test name
Test status
Simulation time 639065986 ps
CPU time 8.4 seconds
Started May 09 12:47:33 PM PDT 24
Finished May 09 12:47:44 PM PDT 24
Peak memory 204340 kb
Host smart-5486368b-3cf5-40b6-9e92-5a50f902d2d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153859944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.1153859944
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.1911021620
Short name T189
Test name
Test status
Simulation time 1331347443 ps
CPU time 58.13 seconds
Started May 09 12:47:34 PM PDT 24
Finished May 09 12:48:35 PM PDT 24
Peak memory 205280 kb
Host smart-6d793965-bbd8-42b8-8b2c-e3342bcc61f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911021620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.1911021620
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.2675104399
Short name T885
Test name
Test status
Simulation time 38894230651 ps
CPU time 38.28 seconds
Started May 09 12:47:37 PM PDT 24
Finished May 09 12:48:19 PM PDT 24
Peak memory 767916 kb
Host smart-d591467d-24f5-4538-94e5-ecb22640a343
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675104399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.2675104399
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.1422458076
Short name T674
Test name
Test status
Simulation time 7136470475 ps
CPU time 11.05 seconds
Started May 09 12:47:36 PM PDT 24
Finished May 09 12:47:51 PM PDT 24
Peak memory 298676 kb
Host smart-29c13062-268f-4c00-ab49-61855921dccb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422458076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.1422458076
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.217146279
Short name T329
Test name
Test status
Simulation time 1494329445 ps
CPU time 6.61 seconds
Started May 09 12:47:44 PM PDT 24
Finished May 09 12:47:52 PM PDT 24
Peak memory 209672 kb
Host smart-b85db6b2-411a-42ef-b7cf-f2782c820cae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217146279 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_timeout.217146279
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.4176117158
Short name T105
Test name
Test status
Simulation time 25576846 ps
CPU time 0.61 seconds
Started May 09 12:47:43 PM PDT 24
Finished May 09 12:47:45 PM PDT 24
Peak memory 204232 kb
Host smart-a29a5809-d15f-44ac-a6ea-82762a5c006c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176117158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.4176117158
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.90051197
Short name T414
Test name
Test status
Simulation time 203642378 ps
CPU time 1.33 seconds
Started May 09 12:47:36 PM PDT 24
Finished May 09 12:47:41 PM PDT 24
Peak memory 212560 kb
Host smart-8e705c00-393a-4c15-b66b-3f9e37e75d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90051197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.90051197
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.1372282791
Short name T970
Test name
Test status
Simulation time 1037268679 ps
CPU time 14.57 seconds
Started May 09 12:47:34 PM PDT 24
Finished May 09 12:47:52 PM PDT 24
Peak memory 251360 kb
Host smart-63d2f3bd-3c11-4571-a01d-c6774af7daa9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372282791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.1372282791
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.2020116176
Short name T1268
Test name
Test status
Simulation time 1461513024 ps
CPU time 98.68 seconds
Started May 09 12:47:44 PM PDT 24
Finished May 09 12:49:24 PM PDT 24
Peak memory 553168 kb
Host smart-cba73735-1852-4297-babd-1047a05cab4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020116176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.2020116176
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.2393961338
Short name T547
Test name
Test status
Simulation time 12734954359 ps
CPU time 88.16 seconds
Started May 09 12:47:39 PM PDT 24
Finished May 09 12:49:10 PM PDT 24
Peak memory 476712 kb
Host smart-3d3a6f99-4572-462e-87fc-e76700461dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393961338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.2393961338
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.3944292829
Short name T985
Test name
Test status
Simulation time 176296193 ps
CPU time 1.07 seconds
Started May 09 12:47:36 PM PDT 24
Finished May 09 12:47:40 PM PDT 24
Peak memory 204276 kb
Host smart-7cd76a32-46a2-47f4-8841-b17b25f6c0c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944292829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.3944292829
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.1193929638
Short name T657
Test name
Test status
Simulation time 128458919 ps
CPU time 3.27 seconds
Started May 09 12:47:35 PM PDT 24
Finished May 09 12:47:42 PM PDT 24
Peak memory 223364 kb
Host smart-95a3f892-8d82-4317-8e35-6324f56e1113
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193929638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.1193929638
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.2229919847
Short name T570
Test name
Test status
Simulation time 2171643823 ps
CPU time 137.7 seconds
Started May 09 12:47:35 PM PDT 24
Finished May 09 12:49:56 PM PDT 24
Peak memory 714432 kb
Host smart-8c045ad1-51da-4d87-bb85-8ab853bfa5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229919847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.2229919847
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.915819396
Short name T1085
Test name
Test status
Simulation time 513937188 ps
CPU time 8.59 seconds
Started May 09 12:47:43 PM PDT 24
Finished May 09 12:47:54 PM PDT 24
Peak memory 204316 kb
Host smart-fa4f6584-008d-4dcd-8c51-2bca48a8a9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915819396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.915819396
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_override.337011496
Short name T978
Test name
Test status
Simulation time 87568378 ps
CPU time 0.72 seconds
Started May 09 12:47:39 PM PDT 24
Finished May 09 12:47:42 PM PDT 24
Peak memory 204152 kb
Host smart-32f0f773-883f-436a-9ca8-05dfb1188af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337011496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.337011496
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.962799260
Short name T407
Test name
Test status
Simulation time 12760012439 ps
CPU time 296.49 seconds
Started May 09 12:47:37 PM PDT 24
Finished May 09 12:52:37 PM PDT 24
Peak memory 1692304 kb
Host smart-bf2d57af-2710-4731-8b40-e9fe3f57a037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962799260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.962799260
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.862554895
Short name T455
Test name
Test status
Simulation time 25037880905 ps
CPU time 64.4 seconds
Started May 09 12:47:34 PM PDT 24
Finished May 09 12:48:41 PM PDT 24
Peak memory 327376 kb
Host smart-61c7444e-5307-4965-879a-6bb1c600e40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862554895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.862554895
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.1790267484
Short name T110
Test name
Test status
Simulation time 82722683534 ps
CPU time 1286.77 seconds
Started May 09 12:47:34 PM PDT 24
Finished May 09 01:09:05 PM PDT 24
Peak memory 2531316 kb
Host smart-d4d7acce-8703-455a-b409-3fe2e299897d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790267484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.1790267484
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.4148186
Short name T357
Test name
Test status
Simulation time 413065056 ps
CPU time 7.02 seconds
Started May 09 12:47:35 PM PDT 24
Finished May 09 12:47:45 PM PDT 24
Peak memory 217692 kb
Host smart-b3658225-5838-455c-a6c0-6acc18ec16e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.4148186
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.2086002550
Short name T1173
Test name
Test status
Simulation time 1307304591 ps
CPU time 2.6 seconds
Started May 09 12:47:46 PM PDT 24
Finished May 09 12:47:50 PM PDT 24
Peak memory 204476 kb
Host smart-971607cf-3a13-449f-a746-a577b9949695
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086002550 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.2086002550
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.1902754265
Short name T276
Test name
Test status
Simulation time 10787958370 ps
CPU time 8.9 seconds
Started May 09 12:47:43 PM PDT 24
Finished May 09 12:47:54 PM PDT 24
Peak memory 243532 kb
Host smart-b4393ee8-13bc-46cf-8d20-2c3a1dc196d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902754265 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.1902754265
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.1471449596
Short name T61
Test name
Test status
Simulation time 10240288118 ps
CPU time 15.41 seconds
Started May 09 12:47:44 PM PDT 24
Finished May 09 12:48:02 PM PDT 24
Peak memory 273516 kb
Host smart-c4532a83-6132-43ed-8a99-c67f7fa95559
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471449596 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.1471449596
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.3882249415
Short name T542
Test name
Test status
Simulation time 489125281 ps
CPU time 3.35 seconds
Started May 09 12:47:44 PM PDT 24
Finished May 09 12:47:49 PM PDT 24
Peak memory 204732 kb
Host smart-c148db02-d952-431a-ad78-89a409a7c658
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882249415 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.3882249415
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.4038958600
Short name T1111
Test name
Test status
Simulation time 2312178156 ps
CPU time 6.2 seconds
Started May 09 12:47:37 PM PDT 24
Finished May 09 12:47:46 PM PDT 24
Peak memory 207484 kb
Host smart-58bf931d-7c96-47e1-9102-b71f67fc017d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038958600 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.4038958600
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.2764082070
Short name T1258
Test name
Test status
Simulation time 20203722131 ps
CPU time 330.36 seconds
Started May 09 12:47:39 PM PDT 24
Finished May 09 12:53:12 PM PDT 24
Peak memory 3224112 kb
Host smart-485f040a-daa2-4665-b10f-55cc26da281b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764082070 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.2764082070
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.2980762965
Short name T397
Test name
Test status
Simulation time 1035366775 ps
CPU time 14.65 seconds
Started May 09 12:47:36 PM PDT 24
Finished May 09 12:47:54 PM PDT 24
Peak memory 204280 kb
Host smart-3789d67e-a400-4a7a-b85e-9d0da8d3bca4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980762965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.2980762965
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.3329437896
Short name T1121
Test name
Test status
Simulation time 5864041424 ps
CPU time 63.94 seconds
Started May 09 12:47:35 PM PDT 24
Finished May 09 12:48:42 PM PDT 24
Peak memory 206980 kb
Host smart-37f47d02-e3d4-4914-8779-2a1cf60541a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329437896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.3329437896
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.3666246775
Short name T28
Test name
Test status
Simulation time 43213822888 ps
CPU time 773.88 seconds
Started May 09 12:47:37 PM PDT 24
Finished May 09 01:00:35 PM PDT 24
Peak memory 5971604 kb
Host smart-adf5c7c6-f3c3-4945-8567-ae96b1b0d810
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666246775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.3666246775
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.1709705946
Short name T1147
Test name
Test status
Simulation time 24873722740 ps
CPU time 220.95 seconds
Started May 09 12:47:34 PM PDT 24
Finished May 09 12:51:19 PM PDT 24
Peak memory 1599156 kb
Host smart-04131b56-6cbf-4cf9-a1c8-e25941c323d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709705946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.1709705946
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.4058798145
Short name T377
Test name
Test status
Simulation time 11209967583 ps
CPU time 7.34 seconds
Started May 09 12:47:42 PM PDT 24
Finished May 09 12:47:52 PM PDT 24
Peak memory 220812 kb
Host smart-7eb976ee-cba3-4f55-9531-e22c4702b335
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058798145 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.4058798145
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.3302198174
Short name T152
Test name
Test status
Simulation time 32727374 ps
CPU time 0.61 seconds
Started May 09 12:47:51 PM PDT 24
Finished May 09 12:47:53 PM PDT 24
Peak memory 204212 kb
Host smart-566cec7c-4be2-44ba-8dc2-7b9e5cb5b34e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302198174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.3302198174
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.2309602178
Short name T654
Test name
Test status
Simulation time 296560062 ps
CPU time 1.6 seconds
Started May 09 12:47:43 PM PDT 24
Finished May 09 12:47:47 PM PDT 24
Peak memory 212700 kb
Host smart-3688d577-6152-4acb-901d-55119ba9c0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309602178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.2309602178
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.1663793249
Short name T541
Test name
Test status
Simulation time 1214948655 ps
CPU time 5.84 seconds
Started May 09 12:47:43 PM PDT 24
Finished May 09 12:47:51 PM PDT 24
Peak memory 264176 kb
Host smart-412ffde1-9d91-4512-8a6f-132bdc52d024
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663793249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.1663793249
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.1184515287
Short name T658
Test name
Test status
Simulation time 4325991177 ps
CPU time 74.25 seconds
Started May 09 12:47:46 PM PDT 24
Finished May 09 12:49:01 PM PDT 24
Peak memory 669860 kb
Host smart-6c891511-c40c-4f78-867c-100037825e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184515287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.1184515287
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.3785083536
Short name T739
Test name
Test status
Simulation time 5039687045 ps
CPU time 66.56 seconds
Started May 09 12:47:45 PM PDT 24
Finished May 09 12:48:53 PM PDT 24
Peak memory 307088 kb
Host smart-76c33928-1df3-4412-a40d-3b9e13372e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785083536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3785083536
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2401885536
Short name T887
Test name
Test status
Simulation time 179114897 ps
CPU time 1.16 seconds
Started May 09 12:47:46 PM PDT 24
Finished May 09 12:47:49 PM PDT 24
Peak memory 204260 kb
Host smart-2da1b6c1-ee90-487e-8dcc-822a776d8c83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401885536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2401885536
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.1809882078
Short name T370
Test name
Test status
Simulation time 14072404380 ps
CPU time 202.09 seconds
Started May 09 12:47:46 PM PDT 24
Finished May 09 12:51:10 PM PDT 24
Peak memory 915304 kb
Host smart-f775c7d9-6bd7-4a8d-bbd4-279ffcb4174d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809882078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.1809882078
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.4205001023
Short name T834
Test name
Test status
Simulation time 782093228 ps
CPU time 12.07 seconds
Started May 09 12:47:51 PM PDT 24
Finished May 09 12:48:05 PM PDT 24
Peak memory 204420 kb
Host smart-edf91148-0114-464e-a2c8-82daf49a67ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205001023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.4205001023
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.4250827874
Short name T1016
Test name
Test status
Simulation time 2414559382 ps
CPU time 47.06 seconds
Started May 09 12:47:54 PM PDT 24
Finished May 09 12:48:43 PM PDT 24
Peak memory 279484 kb
Host smart-cbef3148-131b-43da-ae46-5791f5a2140b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250827874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.4250827874
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.1167271401
Short name T573
Test name
Test status
Simulation time 150189115 ps
CPU time 0.63 seconds
Started May 09 12:47:45 PM PDT 24
Finished May 09 12:47:47 PM PDT 24
Peak memory 204048 kb
Host smart-5e813837-7303-48f7-95fb-145acebe812e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167271401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1167271401
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.2543126939
Short name T958
Test name
Test status
Simulation time 29176727949 ps
CPU time 86.34 seconds
Started May 09 12:47:44 PM PDT 24
Finished May 09 12:49:12 PM PDT 24
Peak memory 357132 kb
Host smart-e09b79e9-1fb7-422f-92df-7f4c368ca9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543126939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.2543126939
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.3415152497
Short name T554
Test name
Test status
Simulation time 6653986317 ps
CPU time 14.29 seconds
Started May 09 12:47:42 PM PDT 24
Finished May 09 12:47:58 PM PDT 24
Peak memory 245896 kb
Host smart-7d0ea44f-58f3-47bf-88bf-09e69e69da3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415152497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3415152497
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.1165558983
Short name T227
Test name
Test status
Simulation time 8259735006 ps
CPU time 160.95 seconds
Started May 09 12:47:53 PM PDT 24
Finished May 09 12:50:35 PM PDT 24
Peak memory 1318976 kb
Host smart-4b8d994b-0b24-4301-89fa-cd41dffc5448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165558983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.1165558983
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.252822246
Short name T750
Test name
Test status
Simulation time 682313559 ps
CPU time 13.35 seconds
Started May 09 12:47:43 PM PDT 24
Finished May 09 12:47:58 PM PDT 24
Peak memory 214976 kb
Host smart-17215613-09a7-4f79-a0e7-343f571c6a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252822246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.252822246
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.341938757
Short name T451
Test name
Test status
Simulation time 1209890359 ps
CPU time 4.07 seconds
Started May 09 12:47:54 PM PDT 24
Finished May 09 12:48:00 PM PDT 24
Peak memory 212572 kb
Host smart-ecc3ba21-86af-4cca-b116-dbf253469821
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341938757 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.341938757
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.4223057580
Short name T878
Test name
Test status
Simulation time 10129286845 ps
CPU time 31.04 seconds
Started May 09 12:47:52 PM PDT 24
Finished May 09 12:48:25 PM PDT 24
Peak memory 324380 kb
Host smart-6801c436-34a0-40be-822a-064b975792be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223057580 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.4223057580
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.643131919
Short name T937
Test name
Test status
Simulation time 1161879300 ps
CPU time 1.96 seconds
Started May 09 12:47:52 PM PDT 24
Finished May 09 12:47:56 PM PDT 24
Peak memory 204260 kb
Host smart-038711ba-0dce-4783-b4db-3cb1d2a30d7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643131919 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.i2c_target_hrst.643131919
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.2634590547
Short name T632
Test name
Test status
Simulation time 1056260928 ps
CPU time 5.53 seconds
Started May 09 12:47:52 PM PDT 24
Finished May 09 12:47:59 PM PDT 24
Peak memory 204376 kb
Host smart-2ca3f822-9737-44c0-a38d-d820f3bcbce4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634590547 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.2634590547
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.694620579
Short name T472
Test name
Test status
Simulation time 18261270755 ps
CPU time 41.23 seconds
Started May 09 12:47:53 PM PDT 24
Finished May 09 12:48:36 PM PDT 24
Peak memory 778460 kb
Host smart-bfb38802-5140-4cd2-9084-2f473da468f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694620579 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.694620579
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.3044955126
Short name T953
Test name
Test status
Simulation time 612671955 ps
CPU time 8.32 seconds
Started May 09 12:47:52 PM PDT 24
Finished May 09 12:48:02 PM PDT 24
Peak memory 204480 kb
Host smart-864d0346-8cc0-4fe3-b256-a1327db0921f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044955126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.3044955126
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.233682907
Short name T611
Test name
Test status
Simulation time 959882220 ps
CPU time 17.34 seconds
Started May 09 12:47:51 PM PDT 24
Finished May 09 12:48:11 PM PDT 24
Peak memory 214060 kb
Host smart-1843c22b-978b-43a1-b42a-ebd68e747838
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233682907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_rd.233682907
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.3935368364
Short name T236
Test name
Test status
Simulation time 23018182759 ps
CPU time 9.23 seconds
Started May 09 12:47:52 PM PDT 24
Finished May 09 12:48:03 PM PDT 24
Peak memory 204496 kb
Host smart-831f718d-a3e5-4d51-97f3-a1cc80701de3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935368364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.3935368364
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1495750761
Short name T1115
Test name
Test status
Simulation time 3396999083 ps
CPU time 63.73 seconds
Started May 09 12:47:54 PM PDT 24
Finished May 09 12:48:59 PM PDT 24
Peak memory 927896 kb
Host smart-cc8ba0cf-7d08-452e-8383-5b2f8d11c204
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495750761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1495750761
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.1572095619
Short name T1119
Test name
Test status
Simulation time 3273510438 ps
CPU time 7.9 seconds
Started May 09 12:47:57 PM PDT 24
Finished May 09 12:48:07 PM PDT 24
Peak memory 220728 kb
Host smart-e15d3839-0036-4349-bd7d-ad684ed1a777
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572095619 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.1572095619
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.1449275560
Short name T410
Test name
Test status
Simulation time 16900463 ps
CPU time 0.63 seconds
Started May 09 12:48:02 PM PDT 24
Finished May 09 12:48:05 PM PDT 24
Peak memory 204164 kb
Host smart-48bb93d2-5c14-4f61-ab71-be424ac08f32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449275560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.1449275560
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.4136441978
Short name T1223
Test name
Test status
Simulation time 82974086 ps
CPU time 1.3 seconds
Started May 09 12:48:02 PM PDT 24
Finished May 09 12:48:07 PM PDT 24
Peak memory 212628 kb
Host smart-0bb6e401-88f5-4c7d-b8f2-a54d53265cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136441978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.4136441978
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.4044738178
Short name T896
Test name
Test status
Simulation time 444751916 ps
CPU time 23.95 seconds
Started May 09 12:48:06 PM PDT 24
Finished May 09 12:48:32 PM PDT 24
Peak memory 297612 kb
Host smart-395b5fe9-02d9-4717-a410-6c6f42fdb19d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044738178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.4044738178
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.431341962
Short name T66
Test name
Test status
Simulation time 9726469064 ps
CPU time 118.95 seconds
Started May 09 12:48:06 PM PDT 24
Finished May 09 12:50:08 PM PDT 24
Peak memory 583792 kb
Host smart-f3a18473-015f-48fb-b366-5249cc1cdebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431341962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.431341962
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.3352613477
Short name T151
Test name
Test status
Simulation time 2707500414 ps
CPU time 43.01 seconds
Started May 09 12:47:55 PM PDT 24
Finished May 09 12:48:39 PM PDT 24
Peak memory 528060 kb
Host smart-1091aa57-c679-4737-8553-cd5777e2c62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352613477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.3352613477
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.1918744988
Short name T558
Test name
Test status
Simulation time 187155196 ps
CPU time 4.89 seconds
Started May 09 12:48:01 PM PDT 24
Finished May 09 12:48:08 PM PDT 24
Peak memory 204424 kb
Host smart-3a3af4d1-bea0-4cd4-97ca-2657ab1651cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918744988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.1918744988
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.3781190152
Short name T939
Test name
Test status
Simulation time 46329420389 ps
CPU time 102.31 seconds
Started May 09 12:47:53 PM PDT 24
Finished May 09 12:49:37 PM PDT 24
Peak memory 1241728 kb
Host smart-b121a84f-a2c9-4190-aa18-d60872bfbe55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781190152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.3781190152
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.486596975
Short name T563
Test name
Test status
Simulation time 633596247 ps
CPU time 8.05 seconds
Started May 09 12:48:02 PM PDT 24
Finished May 09 12:48:14 PM PDT 24
Peak memory 204468 kb
Host smart-28c197d1-131d-46e0-8ff5-ded61d18e433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486596975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.486596975
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.3747429123
Short name T1221
Test name
Test status
Simulation time 7024992750 ps
CPU time 35.67 seconds
Started May 09 12:48:03 PM PDT 24
Finished May 09 12:48:42 PM PDT 24
Peak memory 350660 kb
Host smart-f689424d-7ae2-435f-828f-5ec09768d36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747429123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.3747429123
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.2132062531
Short name T1137
Test name
Test status
Simulation time 114070746 ps
CPU time 0.67 seconds
Started May 09 12:47:57 PM PDT 24
Finished May 09 12:48:00 PM PDT 24
Peak memory 204148 kb
Host smart-1983f69c-242a-4472-894b-51d4e4b956f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132062531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.2132062531
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.52468705
Short name T1135
Test name
Test status
Simulation time 46803435763 ps
CPU time 1737.03 seconds
Started May 09 12:48:04 PM PDT 24
Finished May 09 01:17:05 PM PDT 24
Peak memory 225968 kb
Host smart-6e926957-f9d6-4a11-800d-d8a3370d09a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52468705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.52468705
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.2231854094
Short name T406
Test name
Test status
Simulation time 1378356146 ps
CPU time 72.01 seconds
Started May 09 12:47:54 PM PDT 24
Finished May 09 12:49:07 PM PDT 24
Peak memory 375980 kb
Host smart-38208996-2fb0-4329-b749-08a7d613f08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231854094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.2231854094
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.175584426
Short name T550
Test name
Test status
Simulation time 24297305677 ps
CPU time 846.32 seconds
Started May 09 12:48:04 PM PDT 24
Finished May 09 01:02:13 PM PDT 24
Peak memory 2587756 kb
Host smart-3e1d1a5d-7920-433b-bf01-df727d734b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175584426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.175584426
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.83707351
Short name T1090
Test name
Test status
Simulation time 2834672525 ps
CPU time 32.26 seconds
Started May 09 12:48:04 PM PDT 24
Finished May 09 12:48:39 PM PDT 24
Peak memory 212692 kb
Host smart-00ddd73e-043b-46b6-a97e-561bed9a7df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83707351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.83707351
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.1120996322
Short name T1048
Test name
Test status
Simulation time 619782184 ps
CPU time 2.68 seconds
Started May 09 12:48:03 PM PDT 24
Finished May 09 12:48:09 PM PDT 24
Peak memory 204452 kb
Host smart-65b24867-4d78-4db8-bbcf-35a84d19029a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120996322 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.1120996322
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.4198240322
Short name T977
Test name
Test status
Simulation time 10073111482 ps
CPU time 60.52 seconds
Started May 09 12:48:02 PM PDT 24
Finished May 09 12:49:06 PM PDT 24
Peak memory 381208 kb
Host smart-ecb8a0a6-d6e3-4b45-95e2-b11c764d5e59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198240322 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.4198240322
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.3679137120
Short name T890
Test name
Test status
Simulation time 10123960820 ps
CPU time 32.14 seconds
Started May 09 12:48:04 PM PDT 24
Finished May 09 12:48:40 PM PDT 24
Peak memory 316016 kb
Host smart-83ac5cbe-3cb9-493f-9a8b-8edd89ef0de2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679137120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.3679137120
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.3503078363
Short name T702
Test name
Test status
Simulation time 360657138 ps
CPU time 2.44 seconds
Started May 09 12:48:03 PM PDT 24
Finished May 09 12:48:09 PM PDT 24
Peak memory 204432 kb
Host smart-fed07e2b-7115-4c80-81b1-bac504ae12b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503078363 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.3503078363
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.337637213
Short name T1128
Test name
Test status
Simulation time 940153115 ps
CPU time 4.74 seconds
Started May 09 12:48:04 PM PDT 24
Finished May 09 12:48:12 PM PDT 24
Peak memory 206876 kb
Host smart-a0626c25-d064-43aa-a0b5-d76d0453e5a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337637213 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_intr_smoke.337637213
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.1466322290
Short name T663
Test name
Test status
Simulation time 8234854620 ps
CPU time 4.15 seconds
Started May 09 12:48:04 PM PDT 24
Finished May 09 12:48:11 PM PDT 24
Peak memory 204432 kb
Host smart-4bdb06a1-0c92-432b-ac9a-42c67ec30a41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466322290 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.1466322290
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.882869918
Short name T1101
Test name
Test status
Simulation time 2672210466 ps
CPU time 20.98 seconds
Started May 09 12:48:03 PM PDT 24
Finished May 09 12:48:27 PM PDT 24
Peak memory 204528 kb
Host smart-092d19d3-1fc2-4c5f-bbce-8a943536d32f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882869918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_tar
get_smoke.882869918
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.1486898154
Short name T294
Test name
Test status
Simulation time 4516093844 ps
CPU time 17.22 seconds
Started May 09 12:48:03 PM PDT 24
Finished May 09 12:48:23 PM PDT 24
Peak memory 217968 kb
Host smart-29f37623-b971-48ee-813b-5d603c29a5aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486898154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.1486898154
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.1189001812
Short name T484
Test name
Test status
Simulation time 64569237154 ps
CPU time 289.42 seconds
Started May 09 12:48:04 PM PDT 24
Finished May 09 12:52:57 PM PDT 24
Peak memory 2860952 kb
Host smart-afb387dc-ba31-49ca-a5f1-27f3f2386f03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189001812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.1189001812
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.250936975
Short name T1089
Test name
Test status
Simulation time 5452028211 ps
CPU time 21.02 seconds
Started May 09 12:48:02 PM PDT 24
Finished May 09 12:48:27 PM PDT 24
Peak memory 372612 kb
Host smart-5df7bcdc-e37e-4c17-aa6f-8feb01a55b46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250936975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_t
arget_stretch.250936975
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.462570220
Short name T7
Test name
Test status
Simulation time 1485603933 ps
CPU time 7.68 seconds
Started May 09 12:48:03 PM PDT 24
Finished May 09 12:48:14 PM PDT 24
Peak memory 212656 kb
Host smart-20bde5d1-8d2b-4f77-929d-852019270bef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462570220 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_timeout.462570220
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.2125231492
Short name T1176
Test name
Test status
Simulation time 19959151 ps
CPU time 0.63 seconds
Started May 09 12:48:16 PM PDT 24
Finished May 09 12:48:20 PM PDT 24
Peak memory 204188 kb
Host smart-a6a165bb-1eca-4bc0-8994-2b0065b1d385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125231492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.2125231492
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.1275405879
Short name T641
Test name
Test status
Simulation time 101123478 ps
CPU time 1.58 seconds
Started May 09 12:48:20 PM PDT 24
Finished May 09 12:48:23 PM PDT 24
Peak memory 212748 kb
Host smart-8a476314-a9db-4559-826d-6d14571cf336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275405879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.1275405879
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.2899442585
Short name T1265
Test name
Test status
Simulation time 636439353 ps
CPU time 3.81 seconds
Started May 09 12:48:14 PM PDT 24
Finished May 09 12:48:21 PM PDT 24
Peak memory 233780 kb
Host smart-e11e8e6c-0af0-4d03-902e-75d2912cd3eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899442585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.2899442585
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2016558593
Short name T607
Test name
Test status
Simulation time 2212074247 ps
CPU time 38.6 seconds
Started May 09 12:48:17 PM PDT 24
Finished May 09 12:48:58 PM PDT 24
Peak memory 468448 kb
Host smart-06ae2ab8-6232-4c25-b178-a14002f1e69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016558593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2016558593
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.2811285019
Short name T1298
Test name
Test status
Simulation time 2349087825 ps
CPU time 69.09 seconds
Started May 09 12:48:18 PM PDT 24
Finished May 09 12:49:30 PM PDT 24
Peak memory 755108 kb
Host smart-70e70416-b2fb-48a2-8e86-45a75e57051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811285019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.2811285019
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.581731430
Short name T695
Test name
Test status
Simulation time 232244044 ps
CPU time 1 seconds
Started May 09 12:48:14 PM PDT 24
Finished May 09 12:48:18 PM PDT 24
Peak memory 204212 kb
Host smart-8cd6df51-fe3e-4571-9e56-c4c7f009d90f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581731430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fm
t.581731430
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.2136490561
Short name T596
Test name
Test status
Simulation time 379907596 ps
CPU time 9.8 seconds
Started May 09 12:48:17 PM PDT 24
Finished May 09 12:48:30 PM PDT 24
Peak memory 204412 kb
Host smart-491b5849-6811-45a0-9fac-e152d5a9b8ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136490561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.2136490561
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.2426270236
Short name T1309
Test name
Test status
Simulation time 3050056263 ps
CPU time 205.61 seconds
Started May 09 12:48:03 PM PDT 24
Finished May 09 12:51:32 PM PDT 24
Peak memory 930476 kb
Host smart-a4434139-8b18-4da8-8890-4dd636be2ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426270236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.2426270236
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.2767822821
Short name T951
Test name
Test status
Simulation time 312307007 ps
CPU time 13.59 seconds
Started May 09 12:48:13 PM PDT 24
Finished May 09 12:48:30 PM PDT 24
Peak memory 204352 kb
Host smart-fbe06904-9220-452b-a35c-0ff2efbad8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767822821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.2767822821
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.395165378
Short name T34
Test name
Test status
Simulation time 6786049100 ps
CPU time 30.14 seconds
Started May 09 12:48:18 PM PDT 24
Finished May 09 12:48:50 PM PDT 24
Peak memory 307052 kb
Host smart-5e6193ac-ecef-4862-a753-3e58bf06121c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395165378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.395165378
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.1474047342
Short name T45
Test name
Test status
Simulation time 39965421 ps
CPU time 0.62 seconds
Started May 09 12:48:03 PM PDT 24
Finished May 09 12:48:07 PM PDT 24
Peak memory 204148 kb
Host smart-40172b29-f03d-416c-8787-9716d31e22d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474047342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.1474047342
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.332963395
Short name T766
Test name
Test status
Simulation time 1101956643 ps
CPU time 44.58 seconds
Started May 09 12:48:16 PM PDT 24
Finished May 09 12:49:04 PM PDT 24
Peak memory 237908 kb
Host smart-c69afaf3-10f8-44f0-97a2-373fd5561eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332963395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.332963395
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.428759937
Short name T1152
Test name
Test status
Simulation time 1690953539 ps
CPU time 81.55 seconds
Started May 09 12:48:02 PM PDT 24
Finished May 09 12:49:26 PM PDT 24
Peak memory 331540 kb
Host smart-2c90ca33-44c0-48bd-8b27-cf69f9803c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428759937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.428759937
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.2797944778
Short name T109
Test name
Test status
Simulation time 10112336211 ps
CPU time 138.74 seconds
Started May 09 12:48:12 PM PDT 24
Finished May 09 12:50:34 PM PDT 24
Peak memory 1236212 kb
Host smart-6bb7f4b1-d752-41a3-a3a2-86c6bca80ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797944778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2797944778
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.3554736459
Short name T800
Test name
Test status
Simulation time 1559165577 ps
CPU time 38.4 seconds
Started May 09 12:48:13 PM PDT 24
Finished May 09 12:48:55 PM PDT 24
Peak memory 212760 kb
Host smart-5b0a2887-9ed2-4319-915b-31bd3d70b82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554736459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.3554736459
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.3181905608
Short name T1132
Test name
Test status
Simulation time 2962855580 ps
CPU time 3.61 seconds
Started May 09 12:48:16 PM PDT 24
Finished May 09 12:48:23 PM PDT 24
Peak memory 204580 kb
Host smart-2b353e65-a6c4-4bb0-8c32-5632e1a9eb26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181905608 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.3181905608
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.3730078196
Short name T902
Test name
Test status
Simulation time 10281882239 ps
CPU time 10.86 seconds
Started May 09 12:48:21 PM PDT 24
Finished May 09 12:48:33 PM PDT 24
Peak memory 235196 kb
Host smart-5f4b4a44-97c7-4ee4-98ac-a2629ee61c8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730078196 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.3730078196
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.726861741
Short name T1025
Test name
Test status
Simulation time 1258414826 ps
CPU time 3.18 seconds
Started May 09 12:48:21 PM PDT 24
Finished May 09 12:48:25 PM PDT 24
Peak memory 204252 kb
Host smart-f170f1a8-8416-4614-ae1d-c6e2ab2ecfe3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726861741 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.i2c_target_hrst.726861741
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.1342444123
Short name T338
Test name
Test status
Simulation time 1456188182 ps
CPU time 5.28 seconds
Started May 09 12:48:15 PM PDT 24
Finished May 09 12:48:23 PM PDT 24
Peak memory 213352 kb
Host smart-e77a3678-7d04-482e-9ea1-f7c42608c9e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342444123 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.1342444123
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3570152259
Short name T345
Test name
Test status
Simulation time 7872887803 ps
CPU time 3.05 seconds
Started May 09 12:48:14 PM PDT 24
Finished May 09 12:48:20 PM PDT 24
Peak memory 204536 kb
Host smart-48bd0cc6-ec70-4158-a240-b7e9b53d0caf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570152259 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3570152259
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.458691162
Short name T1226
Test name
Test status
Simulation time 1455573765 ps
CPU time 12.27 seconds
Started May 09 12:48:14 PM PDT 24
Finished May 09 12:48:29 PM PDT 24
Peak memory 204400 kb
Host smart-fb8eb540-c413-47e3-bb6a-a8f12203a93a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458691162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_tar
get_smoke.458691162
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.3017555216
Short name T272
Test name
Test status
Simulation time 3964869938 ps
CPU time 16.43 seconds
Started May 09 12:48:18 PM PDT 24
Finished May 09 12:48:37 PM PDT 24
Peak memory 222948 kb
Host smart-9b9e13c8-f2d3-4de0-b998-7bb7acd28274
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017555216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.3017555216
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.2633740055
Short name T1263
Test name
Test status
Simulation time 59759050906 ps
CPU time 123.51 seconds
Started May 09 12:48:14 PM PDT 24
Finished May 09 12:50:21 PM PDT 24
Peak memory 1618060 kb
Host smart-61af9ba9-10f1-4359-b6bf-e7648f39b07f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633740055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.2633740055
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.1829966612
Short name T1253
Test name
Test status
Simulation time 33188150636 ps
CPU time 51.57 seconds
Started May 09 12:48:13 PM PDT 24
Finished May 09 12:49:07 PM PDT 24
Peak memory 587548 kb
Host smart-44377489-a279-46c0-8110-47794d3c1d8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829966612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.1829966612
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.2419705009
Short name T646
Test name
Test status
Simulation time 6191407197 ps
CPU time 7.49 seconds
Started May 09 12:48:13 PM PDT 24
Finished May 09 12:48:23 PM PDT 24
Peak memory 220732 kb
Host smart-79063710-e51a-4846-ada5-0d2ec9c60593
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419705009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.2419705009
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.732104986
Short name T1235
Test name
Test status
Simulation time 43878009 ps
CPU time 0.61 seconds
Started May 09 12:48:24 PM PDT 24
Finished May 09 12:48:28 PM PDT 24
Peak memory 204204 kb
Host smart-3a63cbe2-dafe-4a35-b56f-4f8f0fe0a07c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732104986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.732104986
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.3899166623
Short name T795
Test name
Test status
Simulation time 166880539 ps
CPU time 1.42 seconds
Started May 09 12:48:16 PM PDT 24
Finished May 09 12:48:21 PM PDT 24
Peak memory 212744 kb
Host smart-3fb3f414-33dc-4eae-9709-9bc656ff7fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899166623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3899166623
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.787635318
Short name T694
Test name
Test status
Simulation time 972533427 ps
CPU time 12.65 seconds
Started May 09 12:48:17 PM PDT 24
Finished May 09 12:48:32 PM PDT 24
Peak memory 253448 kb
Host smart-b3fcd9c8-66c6-451b-92b8-2825b7d5f5e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787635318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empt
y.787635318
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.2904162458
Short name T760
Test name
Test status
Simulation time 1608312749 ps
CPU time 42.63 seconds
Started May 09 12:48:17 PM PDT 24
Finished May 09 12:49:02 PM PDT 24
Peak memory 518896 kb
Host smart-947a08ee-33b1-4bb1-a758-226532dbb629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904162458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.2904162458
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.633799897
Short name T720
Test name
Test status
Simulation time 6215467890 ps
CPU time 104.86 seconds
Started May 09 12:48:17 PM PDT 24
Finished May 09 12:50:05 PM PDT 24
Peak memory 551176 kb
Host smart-3ea74339-6ce5-4bc4-aab4-e77c15130178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633799897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.633799897
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.3656431622
Short name T79
Test name
Test status
Simulation time 467401408 ps
CPU time 1.04 seconds
Started May 09 12:48:21 PM PDT 24
Finished May 09 12:48:23 PM PDT 24
Peak memory 204384 kb
Host smart-f4e95a79-94be-4b4d-8b95-fb811080cc7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656431622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.3656431622
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.3117645668
Short name T506
Test name
Test status
Simulation time 131760605 ps
CPU time 3.37 seconds
Started May 09 12:48:14 PM PDT 24
Finished May 09 12:48:20 PM PDT 24
Peak memory 204420 kb
Host smart-79c51701-0353-4c75-a896-9defb61ebb98
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117645668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.3117645668
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.3950112327
Short name T85
Test name
Test status
Simulation time 12604429802 ps
CPU time 77.66 seconds
Started May 09 12:48:13 PM PDT 24
Finished May 09 12:49:33 PM PDT 24
Peak memory 990252 kb
Host smart-5e9a4d72-3ee0-4705-a0d4-63f5a5069117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950112327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.3950112327
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.2159857169
Short name T73
Test name
Test status
Simulation time 757162536 ps
CPU time 9.5 seconds
Started May 09 12:48:28 PM PDT 24
Finished May 09 12:48:40 PM PDT 24
Peak memory 204400 kb
Host smart-01690ae8-4ab1-4a10-964b-898b18db428e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159857169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.2159857169
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.2832268571
Short name T1337
Test name
Test status
Simulation time 6436999756 ps
CPU time 22.13 seconds
Started May 09 12:48:29 PM PDT 24
Finished May 09 12:48:53 PM PDT 24
Peak memory 353616 kb
Host smart-aa017675-85bb-4f53-a461-4b4e53ad59e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832268571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.2832268571
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.405906526
Short name T5
Test name
Test status
Simulation time 118052542 ps
CPU time 0.65 seconds
Started May 09 12:48:17 PM PDT 24
Finished May 09 12:48:21 PM PDT 24
Peak memory 204132 kb
Host smart-6b83bfe3-0190-487a-a870-cc2bf1029b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405906526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.405906526
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.4280836572
Short name T295
Test name
Test status
Simulation time 3356277169 ps
CPU time 10.17 seconds
Started May 09 12:48:12 PM PDT 24
Finished May 09 12:48:25 PM PDT 24
Peak memory 226824 kb
Host smart-d4c34edd-0ec4-4a93-95df-1bc0176c10c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280836572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.4280836572
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.817071637
Short name T1099
Test name
Test status
Simulation time 3917221539 ps
CPU time 54.39 seconds
Started May 09 12:48:17 PM PDT 24
Finished May 09 12:49:14 PM PDT 24
Peak memory 370532 kb
Host smart-b91203ca-4fa2-4fae-9709-b4e38af48486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817071637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.817071637
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.4096603268
Short name T593
Test name
Test status
Simulation time 10686254568 ps
CPU time 1148.45 seconds
Started May 09 12:48:14 PM PDT 24
Finished May 09 01:07:25 PM PDT 24
Peak memory 2237344 kb
Host smart-9b51b9b4-ce7a-40b7-a3d4-b14b467fab25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096603268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.4096603268
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.2505853652
Short name T777
Test name
Test status
Simulation time 860873072 ps
CPU time 14.97 seconds
Started May 09 12:48:18 PM PDT 24
Finished May 09 12:48:36 PM PDT 24
Peak memory 228780 kb
Host smart-4502aaf6-1cb2-4f32-84af-d89c237a5a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505853652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.2505853652
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.938334977
Short name T1046
Test name
Test status
Simulation time 4176470540 ps
CPU time 5.13 seconds
Started May 09 12:48:22 PM PDT 24
Finished May 09 12:48:29 PM PDT 24
Peak memory 204496 kb
Host smart-2845484b-90ec-4a59-9b2d-85374f50b305
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938334977 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.938334977
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.1647401036
Short name T935
Test name
Test status
Simulation time 10144840750 ps
CPU time 69.47 seconds
Started May 09 12:48:12 PM PDT 24
Finished May 09 12:49:24 PM PDT 24
Peak memory 432700 kb
Host smart-8c96ae3e-cfcd-474e-94cc-a25597e9d8e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647401036 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.1647401036
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.3164930132
Short name T881
Test name
Test status
Simulation time 10044854485 ps
CPU time 71.08 seconds
Started May 09 12:48:13 PM PDT 24
Finished May 09 12:49:26 PM PDT 24
Peak memory 526372 kb
Host smart-0938d002-9686-4fb1-83b3-157461db72cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164930132 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.3164930132
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.3867979226
Short name T791
Test name
Test status
Simulation time 877691104 ps
CPU time 2.6 seconds
Started May 09 12:48:23 PM PDT 24
Finished May 09 12:48:28 PM PDT 24
Peak memory 204224 kb
Host smart-2f807b75-c280-4bc8-9e67-5abb93d5eab3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867979226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.3867979226
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.3783977878
Short name T1262
Test name
Test status
Simulation time 1022577827 ps
CPU time 5.29 seconds
Started May 09 12:48:14 PM PDT 24
Finished May 09 12:48:22 PM PDT 24
Peak memory 212464 kb
Host smart-876fb612-a1c0-4d9b-9621-6179cd515da0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783977878 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.3783977878
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.1804337359
Short name T1224
Test name
Test status
Simulation time 14264939464 ps
CPU time 56.52 seconds
Started May 09 12:48:14 PM PDT 24
Finished May 09 12:49:13 PM PDT 24
Peak memory 1249340 kb
Host smart-f6d6bad9-0ceb-4d09-8b6d-d5f26ff4c828
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804337359 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.1804337359
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.1974146241
Short name T1037
Test name
Test status
Simulation time 1178290408 ps
CPU time 20.97 seconds
Started May 09 12:48:15 PM PDT 24
Finished May 09 12:48:39 PM PDT 24
Peak memory 204372 kb
Host smart-0c94fc64-6178-4a64-a7ec-ef0f97bb7db8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974146241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.1974146241
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.3038663013
Short name T1067
Test name
Test status
Simulation time 4023696255 ps
CPU time 28.38 seconds
Started May 09 12:48:17 PM PDT 24
Finished May 09 12:48:48 PM PDT 24
Peak memory 204484 kb
Host smart-d80f54e4-d5fb-4218-b6ef-7d904bc4a842
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038663013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.3038663013
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.3300282559
Short name T987
Test name
Test status
Simulation time 9591002312 ps
CPU time 10.01 seconds
Started May 09 12:48:17 PM PDT 24
Finished May 09 12:48:30 PM PDT 24
Peak memory 204324 kb
Host smart-f42050c5-8b71-427c-b01b-9ad847c57af5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300282559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.3300282559
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.3613838009
Short name T373
Test name
Test status
Simulation time 12166682770 ps
CPU time 1591.69 seconds
Started May 09 12:48:12 PM PDT 24
Finished May 09 01:14:47 PM PDT 24
Peak memory 2954412 kb
Host smart-36e5ca31-1f40-4d9b-9b55-3ebd950fabb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613838009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.3613838009
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.4083103245
Short name T350
Test name
Test status
Simulation time 1533258802 ps
CPU time 7.15 seconds
Started May 09 12:48:15 PM PDT 24
Finished May 09 12:48:26 PM PDT 24
Peak memory 218476 kb
Host smart-d0f45ad4-148e-4953-9976-07fbc5708dc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083103245 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.4083103245
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.145064019
Short name T359
Test name
Test status
Simulation time 22526925 ps
CPU time 0.67 seconds
Started May 09 12:48:24 PM PDT 24
Finished May 09 12:48:26 PM PDT 24
Peak memory 204464 kb
Host smart-d1dfe7b6-597b-4abf-9fd3-28219889384c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145064019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.145064019
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.1027625854
Short name T770
Test name
Test status
Simulation time 369790583 ps
CPU time 1.23 seconds
Started May 09 12:48:23 PM PDT 24
Finished May 09 12:48:26 PM PDT 24
Peak memory 212772 kb
Host smart-784bf067-3e0a-4caa-80b1-d72e9f7c9477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027625854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.1027625854
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2803472617
Short name T1313
Test name
Test status
Simulation time 505722168 ps
CPU time 19.45 seconds
Started May 09 12:48:29 PM PDT 24
Finished May 09 12:48:50 PM PDT 24
Peak memory 285624 kb
Host smart-1249869b-4aad-4d73-a712-364e661e73a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803472617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.2803472617
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.447753128
Short name T719
Test name
Test status
Simulation time 5506657645 ps
CPU time 210.47 seconds
Started May 09 12:48:24 PM PDT 24
Finished May 09 12:51:57 PM PDT 24
Peak memory 863728 kb
Host smart-793e53c3-1e03-4935-bff3-ec5aeb6b0806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447753128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.447753128
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.2710303293
Short name T802
Test name
Test status
Simulation time 3854764366 ps
CPU time 146.26 seconds
Started May 09 12:48:24 PM PDT 24
Finished May 09 12:50:53 PM PDT 24
Peak memory 646772 kb
Host smart-519e1375-36b7-4ef5-b9de-81dfa4ac2934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710303293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2710303293
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.925792787
Short name T313
Test name
Test status
Simulation time 99972412 ps
CPU time 0.84 seconds
Started May 09 12:48:25 PM PDT 24
Finished May 09 12:48:29 PM PDT 24
Peak memory 204208 kb
Host smart-43b859b4-30eb-4065-a593-c63426de5fda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925792787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fm
t.925792787
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.1817238619
Short name T629
Test name
Test status
Simulation time 2742007014 ps
CPU time 4.17 seconds
Started May 09 12:48:27 PM PDT 24
Finished May 09 12:48:34 PM PDT 24
Peak memory 204468 kb
Host smart-cdfb008c-5003-45d0-babc-0257e6baf923
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817238619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.1817238619
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.2083872501
Short name T478
Test name
Test status
Simulation time 9976027510 ps
CPU time 61.55 seconds
Started May 09 12:48:26 PM PDT 24
Finished May 09 12:49:30 PM PDT 24
Peak memory 754552 kb
Host smart-7af624e9-570b-4dbe-a8ff-d53a969af23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083872501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.2083872501
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.748159257
Short name T931
Test name
Test status
Simulation time 411056251 ps
CPU time 15.62 seconds
Started May 09 12:48:24 PM PDT 24
Finished May 09 12:48:42 PM PDT 24
Peak memory 204412 kb
Host smart-91f32b84-5ef6-477b-9ed8-d2e9e355cdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748159257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.748159257
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.3755108643
Short name T816
Test name
Test status
Simulation time 4735075608 ps
CPU time 57.05 seconds
Started May 09 12:48:27 PM PDT 24
Finished May 09 12:49:27 PM PDT 24
Peak memory 313060 kb
Host smart-1323a611-2485-488b-bcd4-1fcbb9fb5c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755108643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.3755108643
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.2887601775
Short name T119
Test name
Test status
Simulation time 30692404 ps
CPU time 0.66 seconds
Started May 09 12:48:28 PM PDT 24
Finished May 09 12:48:31 PM PDT 24
Peak memory 204148 kb
Host smart-412d95e9-9ea3-4572-ad53-4d0b91a1c58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887601775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2887601775
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.1171118216
Short name T711
Test name
Test status
Simulation time 24776325530 ps
CPU time 174.8 seconds
Started May 09 12:48:28 PM PDT 24
Finished May 09 12:51:25 PM PDT 24
Peak memory 212728 kb
Host smart-e7d51648-14d3-44ff-b549-3d345898d513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171118216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1171118216
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.1698140744
Short name T1352
Test name
Test status
Simulation time 2465201162 ps
CPU time 25.73 seconds
Started May 09 12:48:27 PM PDT 24
Finished May 09 12:48:55 PM PDT 24
Peak memory 334132 kb
Host smart-f1836096-ac6b-4577-989c-2ee13b700f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698140744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1698140744
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.4278869535
Short name T1321
Test name
Test status
Simulation time 27096130095 ps
CPU time 1078.38 seconds
Started May 09 12:48:25 PM PDT 24
Finished May 09 01:06:27 PM PDT 24
Peak memory 1997920 kb
Host smart-e984864b-3f43-4467-92f3-d70df46195b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278869535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.4278869535
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.1778755431
Short name T870
Test name
Test status
Simulation time 630552619 ps
CPU time 11.27 seconds
Started May 09 12:48:23 PM PDT 24
Finished May 09 12:48:36 PM PDT 24
Peak memory 220492 kb
Host smart-af604f43-3f79-4f4e-8fcb-4b7a99191a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778755431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.1778755431
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.2423485180
Short name T26
Test name
Test status
Simulation time 744967649 ps
CPU time 3.98 seconds
Started May 09 12:48:24 PM PDT 24
Finished May 09 12:48:31 PM PDT 24
Peak memory 204408 kb
Host smart-1943f658-88ca-4537-a583-01420325cdb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423485180 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.2423485180
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.4212870553
Short name T1207
Test name
Test status
Simulation time 10501601084 ps
CPU time 17.19 seconds
Started May 09 12:48:23 PM PDT 24
Finished May 09 12:48:42 PM PDT 24
Peak memory 256344 kb
Host smart-4bd3ffef-b208-4313-8151-24ab658b1991
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212870553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.4212870553
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.2659075720
Short name T572
Test name
Test status
Simulation time 10102919834 ps
CPU time 82.75 seconds
Started May 09 12:48:24 PM PDT 24
Finished May 09 12:49:49 PM PDT 24
Peak memory 472756 kb
Host smart-e3e4d48e-3c65-4d43-86ea-b489c2ed0b7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659075720 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.2659075720
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.2594847264
Short name T241
Test name
Test status
Simulation time 7660827357 ps
CPU time 2.38 seconds
Started May 09 12:48:26 PM PDT 24
Finished May 09 12:48:32 PM PDT 24
Peak memory 204384 kb
Host smart-eed16866-8735-46bb-97ba-247addca5d8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594847264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.2594847264
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.3844758332
Short name T1022
Test name
Test status
Simulation time 1548487035 ps
CPU time 4.57 seconds
Started May 09 12:48:25 PM PDT 24
Finished May 09 12:48:32 PM PDT 24
Peak memory 204864 kb
Host smart-0aa18c09-5399-4410-92b3-fde1b1b75cc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844758332 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.3844758332
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.504007352
Short name T705
Test name
Test status
Simulation time 14608474540 ps
CPU time 31.6 seconds
Started May 09 12:48:24 PM PDT 24
Finished May 09 12:48:58 PM PDT 24
Peak memory 895556 kb
Host smart-dbb077ad-cd28-462d-8ec0-1f1f3c0ece65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504007352 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.504007352
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.271518313
Short name T477
Test name
Test status
Simulation time 2092026832 ps
CPU time 37.92 seconds
Started May 09 12:48:26 PM PDT 24
Finished May 09 12:49:07 PM PDT 24
Peak memory 204360 kb
Host smart-45a529b8-68b1-4f8e-b275-19bf574c2910
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271518313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_tar
get_smoke.271518313
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.3661277742
Short name T662
Test name
Test status
Simulation time 5622569538 ps
CPU time 13.73 seconds
Started May 09 12:48:27 PM PDT 24
Finished May 09 12:48:43 PM PDT 24
Peak memory 209600 kb
Host smart-0b0f0165-4925-4305-93b5-eb0eb0694a83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661277742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.3661277742
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.47598613
Short name T1341
Test name
Test status
Simulation time 52735752636 ps
CPU time 1386.77 seconds
Started May 09 12:48:23 PM PDT 24
Finished May 09 01:11:32 PM PDT 24
Peak memory 8101180 kb
Host smart-dd317311-d641-40a0-a4e4-7ca74244b511
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47598613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stress_wr.47598613
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.4056468863
Short name T1289
Test name
Test status
Simulation time 4135374357 ps
CPU time 16.35 seconds
Started May 09 12:48:24 PM PDT 24
Finished May 09 12:48:43 PM PDT 24
Peak memory 381940 kb
Host smart-94c9e34c-63e4-43c0-8685-fd337a0675ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056468863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.4056468863
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.725586137
Short name T1287
Test name
Test status
Simulation time 1327340798 ps
CPU time 6.84 seconds
Started May 09 12:48:24 PM PDT 24
Finished May 09 12:48:34 PM PDT 24
Peak memory 204444 kb
Host smart-93939366-6ab6-40f7-8987-cf504a663744
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725586137 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_timeout.725586137
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_unexp_stop.3823774660
Short name T1051
Test name
Test status
Simulation time 2386309692 ps
CPU time 7.36 seconds
Started May 09 12:48:24 PM PDT 24
Finished May 09 12:48:33 PM PDT 24
Peak memory 212708 kb
Host smart-6de8e0e0-9a7f-4fcb-8e15-e7158c689c51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823774660 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.i2c_target_unexp_stop.3823774660
Directory /workspace/18.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/19.i2c_alert_test.1975431524
Short name T473
Test name
Test status
Simulation time 27973723 ps
CPU time 0.63 seconds
Started May 09 12:48:35 PM PDT 24
Finished May 09 12:48:38 PM PDT 24
Peak memory 204080 kb
Host smart-dc5b276c-2369-4c35-9758-448067b0b6b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975431524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.1975431524
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.1576747632
Short name T1171
Test name
Test status
Simulation time 118101237 ps
CPU time 1.72 seconds
Started May 09 12:48:37 PM PDT 24
Finished May 09 12:48:41 PM PDT 24
Peak memory 212748 kb
Host smart-1f48124e-9b4e-4f8d-b91a-2d6439b581d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576747632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.1576747632
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.531192871
Short name T1071
Test name
Test status
Simulation time 699921478 ps
CPU time 19.27 seconds
Started May 09 12:48:35 PM PDT 24
Finished May 09 12:48:57 PM PDT 24
Peak memory 283312 kb
Host smart-db370832-f6bd-4ef7-a14f-6c7e5ed501a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531192871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empt
y.531192871
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.3952320397
Short name T425
Test name
Test status
Simulation time 22604480987 ps
CPU time 80.53 seconds
Started May 09 12:48:39 PM PDT 24
Finished May 09 12:50:01 PM PDT 24
Peak memory 769700 kb
Host smart-d9a3311b-334b-4220-abf8-a8ca0fd1e5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952320397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.3952320397
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.655492232
Short name T1062
Test name
Test status
Simulation time 9556274095 ps
CPU time 39.76 seconds
Started May 09 12:48:35 PM PDT 24
Finished May 09 12:49:17 PM PDT 24
Peak memory 487200 kb
Host smart-749450a8-077d-4001-8f5d-1834a7ebe170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655492232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.655492232
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.1635045081
Short name T811
Test name
Test status
Simulation time 137547067 ps
CPU time 3.38 seconds
Started May 09 12:48:34 PM PDT 24
Finished May 09 12:48:40 PM PDT 24
Peak memory 204428 kb
Host smart-5397de40-f045-44a5-ae74-b1066de50af4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635045081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.1635045081
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.2780992206
Short name T145
Test name
Test status
Simulation time 10223548432 ps
CPU time 67.78 seconds
Started May 09 12:48:34 PM PDT 24
Finished May 09 12:49:44 PM PDT 24
Peak memory 784120 kb
Host smart-134e5c96-40c2-4398-a0fd-e9b11e12f057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780992206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.2780992206
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.2107301186
Short name T1267
Test name
Test status
Simulation time 221249337 ps
CPU time 3.82 seconds
Started May 09 12:48:33 PM PDT 24
Finished May 09 12:48:39 PM PDT 24
Peak memory 204464 kb
Host smart-752fa1f1-8807-48ec-b5be-65d1cb3caa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107301186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.2107301186
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.208208663
Short name T392
Test name
Test status
Simulation time 1500188546 ps
CPU time 22.49 seconds
Started May 09 12:48:35 PM PDT 24
Finished May 09 12:49:00 PM PDT 24
Peak memory 334404 kb
Host smart-879a4ba0-507a-49fe-9441-6b4bd6c475eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208208663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.208208663
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.1907671775
Short name T487
Test name
Test status
Simulation time 31411849 ps
CPU time 0.62 seconds
Started May 09 12:48:28 PM PDT 24
Finished May 09 12:48:31 PM PDT 24
Peak memory 204152 kb
Host smart-d380d5ad-7360-4792-b6ff-a4f3b874db2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907671775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.1907671775
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.5810797
Short name T1113
Test name
Test status
Simulation time 7357993487 ps
CPU time 52.82 seconds
Started May 09 12:48:35 PM PDT 24
Finished May 09 12:49:30 PM PDT 24
Peak memory 204576 kb
Host smart-03a734bc-7758-4edd-820c-5d0f08c957dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5810797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.5810797
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.3025815158
Short name T1065
Test name
Test status
Simulation time 6653129112 ps
CPU time 54.45 seconds
Started May 09 12:48:28 PM PDT 24
Finished May 09 12:49:25 PM PDT 24
Peak memory 265060 kb
Host smart-10c822b2-d8db-4319-af83-7204c36a5625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025815158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.3025815158
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.3579463629
Short name T400
Test name
Test status
Simulation time 1394411023 ps
CPU time 31.87 seconds
Started May 09 12:48:38 PM PDT 24
Finished May 09 12:49:12 PM PDT 24
Peak memory 212684 kb
Host smart-e191ca6a-b58e-48e9-a282-3942d09c1a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579463629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3579463629
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.722347217
Short name T689
Test name
Test status
Simulation time 3911335816 ps
CPU time 4.87 seconds
Started May 09 12:48:35 PM PDT 24
Finished May 09 12:48:42 PM PDT 24
Peak memory 212740 kb
Host smart-b2cf9a95-ebda-4518-b5c0-f0dfbf6cf581
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722347217 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.722347217
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.1444938302
Short name T685
Test name
Test status
Simulation time 10033299001 ps
CPU time 65.02 seconds
Started May 09 12:48:33 PM PDT 24
Finished May 09 12:49:40 PM PDT 24
Peak memory 492988 kb
Host smart-bc4779da-83b3-4b74-9cbf-8d8a4f858614
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444938302 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.1444938302
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.1758752270
Short name T62
Test name
Test status
Simulation time 10283778242 ps
CPU time 17.01 seconds
Started May 09 12:48:35 PM PDT 24
Finished May 09 12:48:54 PM PDT 24
Peak memory 313176 kb
Host smart-d48fdf8d-bcc5-4b43-80ea-3a877c564906
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758752270 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.1758752270
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.1575418534
Short name T326
Test name
Test status
Simulation time 2052581376 ps
CPU time 3.05 seconds
Started May 09 12:48:33 PM PDT 24
Finished May 09 12:48:38 PM PDT 24
Peak memory 204420 kb
Host smart-384d3074-ca8c-43ce-bec8-aaa3372a262f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575418534 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.1575418534
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.4007964416
Short name T1013
Test name
Test status
Simulation time 3052772294 ps
CPU time 4.38 seconds
Started May 09 12:48:35 PM PDT 24
Finished May 09 12:48:42 PM PDT 24
Peak memory 204504 kb
Host smart-2edde96d-2f70-4ccc-bd1e-2460ed5292b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007964416 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.4007964416
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.3380525441
Short name T948
Test name
Test status
Simulation time 6464060633 ps
CPU time 14.5 seconds
Started May 09 12:48:33 PM PDT 24
Finished May 09 12:48:50 PM PDT 24
Peak memory 204424 kb
Host smart-f92676aa-1b61-4b46-8c37-4314d6b0067f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380525441 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.3380525441
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.3479529780
Short name T565
Test name
Test status
Simulation time 2620682978 ps
CPU time 23.87 seconds
Started May 09 12:48:33 PM PDT 24
Finished May 09 12:49:00 PM PDT 24
Peak memory 204464 kb
Host smart-4b10f4a5-0d60-4510-92ef-2db87c640bd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479529780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.3479529780
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.1586399728
Short name T1257
Test name
Test status
Simulation time 384772564 ps
CPU time 7.04 seconds
Started May 09 12:48:34 PM PDT 24
Finished May 09 12:48:43 PM PDT 24
Peak memory 204348 kb
Host smart-aa71535a-3305-457d-8ef9-8b1790098e46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586399728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.1586399728
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.56459502
Short name T716
Test name
Test status
Simulation time 28545748478 ps
CPU time 26.3 seconds
Started May 09 12:48:36 PM PDT 24
Finished May 09 12:49:05 PM PDT 24
Peak memory 551788 kb
Host smart-4bffdfd5-afd0-4052-8a4b-a6ed9882e04b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56459502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stress_wr.56459502
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.3524062199
Short name T1131
Test name
Test status
Simulation time 22873098590 ps
CPU time 186.99 seconds
Started May 09 12:48:36 PM PDT 24
Finished May 09 12:51:45 PM PDT 24
Peak memory 1384780 kb
Host smart-467acd99-6483-4f7f-8e28-2f7c414c5750
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524062199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.3524062199
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.3682952831
Short name T865
Test name
Test status
Simulation time 2412315659 ps
CPU time 6.49 seconds
Started May 09 12:48:34 PM PDT 24
Finished May 09 12:48:43 PM PDT 24
Peak memory 219884 kb
Host smart-38ee4ca2-f539-422d-80f1-8ba6fbe85237
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682952831 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.3682952831
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.1222729098
Short name T114
Test name
Test status
Simulation time 19548328 ps
CPU time 0.62 seconds
Started May 09 12:45:52 PM PDT 24
Finished May 09 12:45:54 PM PDT 24
Peak memory 204180 kb
Host smart-6b51035d-fb46-4e19-b399-fd8d57990c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222729098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.1222729098
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.947998721
Short name T1047
Test name
Test status
Simulation time 165234932 ps
CPU time 1.27 seconds
Started May 09 12:45:42 PM PDT 24
Finished May 09 12:45:45 PM PDT 24
Peak memory 204464 kb
Host smart-45ee94c4-ff83-4bda-9ad8-2c80341156dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947998721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.947998721
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.2153817438
Short name T424
Test name
Test status
Simulation time 275927369 ps
CPU time 6.13 seconds
Started May 09 12:45:42 PM PDT 24
Finished May 09 12:45:50 PM PDT 24
Peak memory 262536 kb
Host smart-62c6d222-ef93-419e-98cf-172d4163e866
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153817438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.2153817438
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.218094658
Short name T51
Test name
Test status
Simulation time 2336917319 ps
CPU time 61.21 seconds
Started May 09 12:45:41 PM PDT 24
Finished May 09 12:46:44 PM PDT 24
Peak memory 263960 kb
Host smart-19b242f6-6815-4eed-a083-286215666e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218094658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.218094658
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.1044049357
Short name T1299
Test name
Test status
Simulation time 8164094936 ps
CPU time 75.12 seconds
Started May 09 12:45:40 PM PDT 24
Finished May 09 12:46:57 PM PDT 24
Peak memory 711632 kb
Host smart-735021c2-f8ec-440b-a51a-2793690a43d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044049357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.1044049357
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.788292881
Short name T758
Test name
Test status
Simulation time 307744428 ps
CPU time 0.86 seconds
Started May 09 12:45:42 PM PDT 24
Finished May 09 12:45:44 PM PDT 24
Peak memory 204144 kb
Host smart-d3d776e6-8a88-4ec5-b31b-5f7c698f82b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788292881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt
.788292881
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.4131808035
Short name T1004
Test name
Test status
Simulation time 134442814 ps
CPU time 3.68 seconds
Started May 09 12:45:41 PM PDT 24
Finished May 09 12:45:46 PM PDT 24
Peak memory 223868 kb
Host smart-6f98e6a2-8701-408a-a54b-0ae1901a2482
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131808035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
4131808035
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.2415680834
Short name T1189
Test name
Test status
Simulation time 13875322112 ps
CPU time 251.23 seconds
Started May 09 12:45:41 PM PDT 24
Finished May 09 12:49:54 PM PDT 24
Peak memory 1031816 kb
Host smart-34a17911-69af-46a2-bb05-2e8f87e85f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415680834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.2415680834
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.1041768091
Short name T404
Test name
Test status
Simulation time 271477877 ps
CPU time 10.88 seconds
Started May 09 12:45:57 PM PDT 24
Finished May 09 12:46:09 PM PDT 24
Peak memory 204336 kb
Host smart-554d8b01-7930-42c1-abda-509c033f1e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041768091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.1041768091
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.1650057647
Short name T748
Test name
Test status
Simulation time 4115286461 ps
CPU time 52.32 seconds
Started May 09 12:45:51 PM PDT 24
Finished May 09 12:46:45 PM PDT 24
Peak memory 334540 kb
Host smart-ec62b8a6-1345-4b37-8111-374bb366b33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650057647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.1650057647
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.3484783674
Short name T651
Test name
Test status
Simulation time 26832132 ps
CPU time 0.7 seconds
Started May 09 12:45:42 PM PDT 24
Finished May 09 12:45:44 PM PDT 24
Peak memory 204076 kb
Host smart-556c7355-b763-432f-9f79-f4d837cb687b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484783674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.3484783674
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.1570585885
Short name T817
Test name
Test status
Simulation time 5804087481 ps
CPU time 41.45 seconds
Started May 09 12:45:42 PM PDT 24
Finished May 09 12:46:25 PM PDT 24
Peak memory 531936 kb
Host smart-a260cd88-dc7d-4643-bb7b-8dd0cadef93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570585885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.1570585885
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.3342129750
Short name T581
Test name
Test status
Simulation time 4249990460 ps
CPU time 20.18 seconds
Started May 09 12:45:41 PM PDT 24
Finished May 09 12:46:03 PM PDT 24
Peak memory 278020 kb
Host smart-5e597f14-3f82-4f5e-a0d7-8e2adeadf846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342129750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.3342129750
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.2889719571
Short name T244
Test name
Test status
Simulation time 66368385464 ps
CPU time 649.3 seconds
Started May 09 12:45:42 PM PDT 24
Finished May 09 12:56:33 PM PDT 24
Peak memory 1301840 kb
Host smart-063e9d2c-79f4-4412-9881-63cc88fe3843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889719571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.2889719571
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.2132532899
Short name T1123
Test name
Test status
Simulation time 1129893510 ps
CPU time 6.96 seconds
Started May 09 12:45:38 PM PDT 24
Finished May 09 12:45:47 PM PDT 24
Peak memory 220352 kb
Host smart-7647f235-5aae-48d4-85d2-f98970617e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132532899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.2132532899
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.3404522256
Short name T156
Test name
Test status
Simulation time 132420920 ps
CPU time 0.84 seconds
Started May 09 12:45:53 PM PDT 24
Finished May 09 12:45:55 PM PDT 24
Peak memory 221460 kb
Host smart-00e1bac2-2a27-4b00-98dc-6a6f73eb85d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404522256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.3404522256
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.2411273949
Short name T1216
Test name
Test status
Simulation time 1276261691 ps
CPU time 3.49 seconds
Started May 09 12:45:52 PM PDT 24
Finished May 09 12:45:56 PM PDT 24
Peak memory 204392 kb
Host smart-24feb409-0dbc-49b6-8973-ca1b85e9279c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411273949 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.2411273949
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.317357277
Short name T287
Test name
Test status
Simulation time 10241209586 ps
CPU time 13.67 seconds
Started May 09 12:45:55 PM PDT 24
Finished May 09 12:46:10 PM PDT 24
Peak memory 247284 kb
Host smart-dd17b1dd-8e93-453a-93ce-bf8b1402a1a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317357277 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_acq.317357277
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3524106257
Short name T374
Test name
Test status
Simulation time 10048320600 ps
CPU time 72.28 seconds
Started May 09 12:45:54 PM PDT 24
Finished May 09 12:47:08 PM PDT 24
Peak memory 475956 kb
Host smart-2d4f8f09-155d-41b9-9e3a-67b74bd7b56a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524106257 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3524106257
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.1402684037
Short name T701
Test name
Test status
Simulation time 630943889 ps
CPU time 3.55 seconds
Started May 09 12:45:53 PM PDT 24
Finished May 09 12:45:57 PM PDT 24
Peak memory 204404 kb
Host smart-7c8fb181-004c-4e33-b8f3-3a25ff9922d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402684037 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.1402684037
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2779522021
Short name T1332
Test name
Test status
Simulation time 12924107790 ps
CPU time 6.57 seconds
Started May 09 12:45:53 PM PDT 24
Finished May 09 12:46:01 PM PDT 24
Peak memory 219356 kb
Host smart-1722958e-471f-4df1-ba6b-4843bf2bd131
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779522021 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2779522021
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.3376432505
Short name T1053
Test name
Test status
Simulation time 3230418865 ps
CPU time 4.12 seconds
Started May 09 12:45:54 PM PDT 24
Finished May 09 12:45:59 PM PDT 24
Peak memory 204356 kb
Host smart-9179b803-b50d-417c-8d90-cdc04bdb3f34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376432505 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.3376432505
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.3524992036
Short name T1102
Test name
Test status
Simulation time 1108264945 ps
CPU time 14.12 seconds
Started May 09 12:45:55 PM PDT 24
Finished May 09 12:46:10 PM PDT 24
Peak memory 204420 kb
Host smart-276163aa-c857-4f75-b3ef-cf3509f9315a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524992036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.3524992036
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_all.1177735126
Short name T235
Test name
Test status
Simulation time 77687833720 ps
CPU time 279.82 seconds
Started May 09 12:45:57 PM PDT 24
Finished May 09 12:50:38 PM PDT 24
Peak memory 2005240 kb
Host smart-76adb5a6-4cbc-4218-83b1-15f0156a8ab9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177735126 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.i2c_target_stress_all.1177735126
Directory /workspace/2.i2c_target_stress_all/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1454472357
Short name T998
Test name
Test status
Simulation time 5140320475 ps
CPU time 77.65 seconds
Started May 09 12:45:53 PM PDT 24
Finished May 09 12:47:12 PM PDT 24
Peak memory 208888 kb
Host smart-61385bbe-bba8-4533-a196-fda9a283228e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454472357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1454472357
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.861504671
Short name T537
Test name
Test status
Simulation time 15899527495 ps
CPU time 15.94 seconds
Started May 09 12:45:53 PM PDT 24
Finished May 09 12:46:10 PM PDT 24
Peak memory 204452 kb
Host smart-94349434-24c8-41bc-8990-fd7e28949386
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861504671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_wr.861504671
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.401293173
Short name T624
Test name
Test status
Simulation time 17338734534 ps
CPU time 106.68 seconds
Started May 09 12:45:54 PM PDT 24
Finished May 09 12:47:43 PM PDT 24
Peak memory 1054300 kb
Host smart-116f85df-ea42-4fa3-bbfe-db2678e11abf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401293173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_ta
rget_stretch.401293173
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.4037276709
Short name T1
Test name
Test status
Simulation time 2834920513 ps
CPU time 8.17 seconds
Started May 09 12:45:57 PM PDT 24
Finished May 09 12:46:06 PM PDT 24
Peak memory 218344 kb
Host smart-51f9c766-0904-4ff1-80b0-b043dbaf6243
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037276709 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.4037276709
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1790207616
Short name T1346
Test name
Test status
Simulation time 89268459 ps
CPU time 0.6 seconds
Started May 09 12:48:44 PM PDT 24
Finished May 09 12:48:46 PM PDT 24
Peak memory 204200 kb
Host smart-6c9e421c-2f1b-4061-8e5b-006ab7eaf420
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790207616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1790207616
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.2539764424
Short name T838
Test name
Test status
Simulation time 181521139 ps
CPU time 1.53 seconds
Started May 09 12:48:44 PM PDT 24
Finished May 09 12:48:47 PM PDT 24
Peak memory 212728 kb
Host smart-f776d69a-2fe2-4f3d-b036-6ceb09fbd309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539764424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.2539764424
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.1278888872
Short name T1055
Test name
Test status
Simulation time 988052399 ps
CPU time 26.79 seconds
Started May 09 12:48:36 PM PDT 24
Finished May 09 12:49:05 PM PDT 24
Peak memory 314412 kb
Host smart-49f198f3-1a47-4f41-ad10-cde4c292f9b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278888872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.1278888872
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.4235040873
Short name T136
Test name
Test status
Simulation time 4220860771 ps
CPU time 57.15 seconds
Started May 09 12:48:33 PM PDT 24
Finished May 09 12:49:33 PM PDT 24
Peak memory 564924 kb
Host smart-68c90fdd-24e3-4aff-b236-355c557f3bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235040873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.4235040873
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.3188983141
Short name T307
Test name
Test status
Simulation time 1713633579 ps
CPU time 37.05 seconds
Started May 09 12:48:34 PM PDT 24
Finished May 09 12:49:13 PM PDT 24
Peak memory 538164 kb
Host smart-474d16c2-fc0f-4c48-a33f-5fbb2eff90c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188983141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.3188983141
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.3384443386
Short name T316
Test name
Test status
Simulation time 368054927 ps
CPU time 0.81 seconds
Started May 09 12:48:32 PM PDT 24
Finished May 09 12:48:35 PM PDT 24
Peak memory 204208 kb
Host smart-7fe9b0ac-c130-484c-b942-093ac13aa595
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384443386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.3384443386
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.3854549689
Short name T1196
Test name
Test status
Simulation time 260583556 ps
CPU time 3.55 seconds
Started May 09 12:48:36 PM PDT 24
Finished May 09 12:48:42 PM PDT 24
Peak memory 204444 kb
Host smart-5a47fed4-4d75-4279-87a6-8dd4db6789b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854549689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.3854549689
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.696061173
Short name T782
Test name
Test status
Simulation time 4479142704 ps
CPU time 119.66 seconds
Started May 09 12:48:32 PM PDT 24
Finished May 09 12:50:34 PM PDT 24
Peak memory 1261208 kb
Host smart-d85fb90e-7d80-42d6-9ee0-ea1ddc439feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696061173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.696061173
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.786330629
Short name T575
Test name
Test status
Simulation time 607215396 ps
CPU time 8.48 seconds
Started May 09 12:48:45 PM PDT 24
Finished May 09 12:48:56 PM PDT 24
Peak memory 204432 kb
Host smart-5341609e-a03d-46b6-b568-a76967a39cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786330629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.786330629
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.2553005219
Short name T1179
Test name
Test status
Simulation time 2887167548 ps
CPU time 20.92 seconds
Started May 09 12:48:43 PM PDT 24
Finished May 09 12:49:06 PM PDT 24
Peak memory 309884 kb
Host smart-094f7ee1-2bd0-477d-85ed-f2a87309e06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553005219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.2553005219
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_perf.729070107
Short name T1194
Test name
Test status
Simulation time 2884608884 ps
CPU time 39.98 seconds
Started May 09 12:48:38 PM PDT 24
Finished May 09 12:49:20 PM PDT 24
Peak memory 260848 kb
Host smart-96ad0ba3-570f-427c-aed6-d81a627ff196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729070107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.729070107
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1131447672
Short name T832
Test name
Test status
Simulation time 947185303 ps
CPU time 43.96 seconds
Started May 09 12:48:38 PM PDT 24
Finished May 09 12:49:24 PM PDT 24
Peak memory 282468 kb
Host smart-d852a991-3a2e-4ac8-9b23-323b0a7ffe9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131447672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1131447672
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.4249678264
Short name T98
Test name
Test status
Simulation time 32140233128 ps
CPU time 174.21 seconds
Started May 09 12:48:43 PM PDT 24
Finished May 09 12:51:40 PM PDT 24
Peak memory 1491024 kb
Host smart-d606bb6a-e086-4ba1-a7c3-f91bf1fe16d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249678264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.4249678264
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.1392992880
Short name T829
Test name
Test status
Simulation time 1090486791 ps
CPU time 21.51 seconds
Started May 09 12:48:43 PM PDT 24
Finished May 09 12:49:07 PM PDT 24
Peak memory 212656 kb
Host smart-28e5a04d-aa40-444d-98b8-73ff6f9bd19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392992880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.1392992880
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.2427059713
Short name T1078
Test name
Test status
Simulation time 2803475606 ps
CPU time 3.62 seconds
Started May 09 12:48:43 PM PDT 24
Finished May 09 12:48:49 PM PDT 24
Peak memory 204540 kb
Host smart-8f87a672-510f-41f1-802a-da6f917be4eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427059713 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.2427059713
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.3551971065
Short name T1140
Test name
Test status
Simulation time 10053585316 ps
CPU time 60.29 seconds
Started May 09 12:48:43 PM PDT 24
Finished May 09 12:49:46 PM PDT 24
Peak memory 450744 kb
Host smart-b302a950-f943-48df-9b7d-f68a349ab69c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551971065 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.3551971065
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.3831307592
Short name T652
Test name
Test status
Simulation time 10040127424 ps
CPU time 82.01 seconds
Started May 09 12:48:46 PM PDT 24
Finished May 09 12:50:10 PM PDT 24
Peak memory 540244 kb
Host smart-a89bbe71-97d1-4867-ae59-9b58e2d81c9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831307592 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.3831307592
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.926605861
Short name T874
Test name
Test status
Simulation time 1889726605 ps
CPU time 2.76 seconds
Started May 09 12:48:45 PM PDT 24
Finished May 09 12:48:50 PM PDT 24
Peak memory 204392 kb
Host smart-c39525b9-0976-45c9-8144-4a0d12f0c57c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926605861 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.i2c_target_hrst.926605861
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.646187261
Short name T1314
Test name
Test status
Simulation time 2265581387 ps
CPU time 3.66 seconds
Started May 09 12:48:44 PM PDT 24
Finished May 09 12:48:49 PM PDT 24
Peak memory 204444 kb
Host smart-19a1dafe-b1a5-4743-8e53-ab929d76e536
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646187261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_intr_smoke.646187261
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.821289153
Short name T261
Test name
Test status
Simulation time 11975954927 ps
CPU time 18.52 seconds
Started May 09 12:48:45 PM PDT 24
Finished May 09 12:49:06 PM PDT 24
Peak memory 429404 kb
Host smart-22fb772c-89d3-4b58-a5a7-f94624c498a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821289153 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.821289153
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.1827658931
Short name T1041
Test name
Test status
Simulation time 2595865887 ps
CPU time 11.73 seconds
Started May 09 12:48:45 PM PDT 24
Finished May 09 12:48:59 PM PDT 24
Peak memory 204488 kb
Host smart-dd121580-a55f-4da9-bfd8-67a3ccbc2c0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827658931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.1827658931
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.670573853
Short name T903
Test name
Test status
Simulation time 2188780503 ps
CPU time 9.28 seconds
Started May 09 12:48:51 PM PDT 24
Finished May 09 12:49:01 PM PDT 24
Peak memory 204616 kb
Host smart-802b69e4-4071-47fe-9d94-54149f505fec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670573853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_rd.670573853
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.2909263885
Short name T584
Test name
Test status
Simulation time 36238789950 ps
CPU time 428.54 seconds
Started May 09 12:48:44 PM PDT 24
Finished May 09 12:55:54 PM PDT 24
Peak memory 4074896 kb
Host smart-7df42ad4-7af6-4220-a165-50285c9ad884
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909263885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.2909263885
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.2316195731
Short name T460
Test name
Test status
Simulation time 14580896269 ps
CPU time 2042.41 seconds
Started May 09 12:48:49 PM PDT 24
Finished May 09 01:22:53 PM PDT 24
Peak memory 3540460 kb
Host smart-d6221899-2eeb-4ef0-88d1-4423f353d878
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316195731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.2316195731
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.1517887826
Short name T446
Test name
Test status
Simulation time 6421007097 ps
CPU time 8.07 seconds
Started May 09 12:48:44 PM PDT 24
Finished May 09 12:48:55 PM PDT 24
Peak memory 212564 kb
Host smart-75fe4187-eb91-41bc-a4de-3222d46d90c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517887826 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.1517887826
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.2289196617
Short name T813
Test name
Test status
Simulation time 50725312 ps
CPU time 0.63 seconds
Started May 09 12:48:54 PM PDT 24
Finished May 09 12:48:56 PM PDT 24
Peak memory 204216 kb
Host smart-2c5d1f4b-2f65-4c32-b6bd-30e3d2e6a145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289196617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2289196617
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.1446568973
Short name T1200
Test name
Test status
Simulation time 88415732 ps
CPU time 1.99 seconds
Started May 09 12:48:55 PM PDT 24
Finished May 09 12:48:58 PM PDT 24
Peak memory 212764 kb
Host smart-4baaad66-91f4-4a68-a715-1a23aacf199f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446568973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.1446568973
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.42148404
Short name T715
Test name
Test status
Simulation time 1033862237 ps
CPU time 6.53 seconds
Started May 09 12:48:44 PM PDT 24
Finished May 09 12:48:52 PM PDT 24
Peak memory 263780 kb
Host smart-4d2fbe13-b6e7-4309-82bb-373d9b03cef7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42148404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empty
.42148404
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.937494436
Short name T50
Test name
Test status
Simulation time 5791412983 ps
CPU time 37.93 seconds
Started May 09 12:48:45 PM PDT 24
Finished May 09 12:49:25 PM PDT 24
Peak memory 472904 kb
Host smart-92f88211-987e-4de8-9aa9-4d12240c2db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937494436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.937494436
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.2654144719
Short name T731
Test name
Test status
Simulation time 1848599949 ps
CPU time 63.47 seconds
Started May 09 12:48:46 PM PDT 24
Finished May 09 12:49:51 PM PDT 24
Peak memory 641172 kb
Host smart-44cffa38-63af-4c5c-9b9a-91b612aba603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654144719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.2654144719
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.2454175794
Short name T1141
Test name
Test status
Simulation time 380273789 ps
CPU time 0.94 seconds
Started May 09 12:48:43 PM PDT 24
Finished May 09 12:48:46 PM PDT 24
Peak memory 204144 kb
Host smart-d34b495c-b7a9-4cdc-992a-a20a4e5b6fd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454175794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.2454175794
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.3475491354
Short name T528
Test name
Test status
Simulation time 380094389 ps
CPU time 4.05 seconds
Started May 09 12:48:49 PM PDT 24
Finished May 09 12:48:54 PM PDT 24
Peak memory 204452 kb
Host smart-e6319cc6-a00f-4ecd-b709-cc3bd61b3eea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475491354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.3475491354
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.3846662704
Short name T100
Test name
Test status
Simulation time 17743305199 ps
CPU time 105.41 seconds
Started May 09 12:48:46 PM PDT 24
Finished May 09 12:50:33 PM PDT 24
Peak memory 1132896 kb
Host smart-d22e7d44-78ea-4c26-a476-bab5c8d2ab64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846662704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.3846662704
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.111415269
Short name T993
Test name
Test status
Simulation time 327224768 ps
CPU time 2.19 seconds
Started May 09 12:48:56 PM PDT 24
Finished May 09 12:49:00 PM PDT 24
Peak memory 204360 kb
Host smart-fee1b4e4-edc8-40c5-8d65-d585bed6f500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111415269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.111415269
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.536294263
Short name T36
Test name
Test status
Simulation time 1946314984 ps
CPU time 42.72 seconds
Started May 09 12:48:55 PM PDT 24
Finished May 09 12:49:39 PM PDT 24
Peak memory 268824 kb
Host smart-f5b5284c-8445-425f-b2cc-296b15014e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536294263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.536294263
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.1604994733
Short name T448
Test name
Test status
Simulation time 28237463 ps
CPU time 0.7 seconds
Started May 09 12:48:48 PM PDT 24
Finished May 09 12:48:50 PM PDT 24
Peak memory 204152 kb
Host smart-553addbb-b4e5-4727-ab0c-febc7709ffd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604994733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.1604994733
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.2377422498
Short name T636
Test name
Test status
Simulation time 6077880653 ps
CPU time 54.27 seconds
Started May 09 12:48:43 PM PDT 24
Finished May 09 12:49:39 PM PDT 24
Peak memory 212744 kb
Host smart-e4bd8c87-6f3b-4b20-90c0-dab259cf8799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377422498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2377422498
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.1553773424
Short name T963
Test name
Test status
Simulation time 3633045739 ps
CPU time 16.94 seconds
Started May 09 12:48:42 PM PDT 24
Finished May 09 12:49:00 PM PDT 24
Peak memory 285112 kb
Host smart-14e11aba-8dd4-486a-891d-977ca240d371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553773424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.1553773424
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.315465309
Short name T64
Test name
Test status
Simulation time 16679154350 ps
CPU time 1261.83 seconds
Started May 09 12:48:54 PM PDT 24
Finished May 09 01:09:57 PM PDT 24
Peak memory 2089140 kb
Host smart-76073b64-4dad-4746-a5cb-61e910712421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315465309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.315465309
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.4258816359
Short name T278
Test name
Test status
Simulation time 411694128 ps
CPU time 18.77 seconds
Started May 09 12:48:43 PM PDT 24
Finished May 09 12:49:03 PM PDT 24
Peak memory 212672 kb
Host smart-2bbb2818-9f17-4170-9add-e00d3cd6eac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258816359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.4258816359
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.1117111800
Short name T352
Test name
Test status
Simulation time 3011754772 ps
CPU time 3.65 seconds
Started May 09 12:48:55 PM PDT 24
Finished May 09 12:49:01 PM PDT 24
Peak memory 204556 kb
Host smart-a3c30c66-8a3a-4e43-94b5-5e949de3d2aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117111800 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.1117111800
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1658361105
Short name T1318
Test name
Test status
Simulation time 10141971047 ps
CPU time 63.26 seconds
Started May 09 12:48:56 PM PDT 24
Finished May 09 12:50:00 PM PDT 24
Peak memory 505120 kb
Host smart-878aa9c1-16a6-44af-ac8f-75daf9b63331
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658361105 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.1658361105
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.2555183532
Short name T1302
Test name
Test status
Simulation time 10037041521 ps
CPU time 65.5 seconds
Started May 09 12:48:55 PM PDT 24
Finished May 09 12:50:02 PM PDT 24
Peak memory 537892 kb
Host smart-d71d1129-20fd-41d3-99cd-35a907ee6368
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555183532 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.2555183532
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.232353798
Short name T382
Test name
Test status
Simulation time 2329123085 ps
CPU time 3.69 seconds
Started May 09 12:48:54 PM PDT 24
Finished May 09 12:48:59 PM PDT 24
Peak memory 204528 kb
Host smart-75a80bd9-00e4-4ead-ae4f-3a84159501bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232353798 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.i2c_target_hrst.232353798
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.17159784
Short name T1138
Test name
Test status
Simulation time 1581532247 ps
CPU time 4.31 seconds
Started May 09 12:48:57 PM PDT 24
Finished May 09 12:49:03 PM PDT 24
Peak memory 206896 kb
Host smart-ff66938d-9479-42f0-b2cf-90ade49638d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17159784 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_intr_smoke.17159784
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.2127538887
Short name T351
Test name
Test status
Simulation time 27524791562 ps
CPU time 73.5 seconds
Started May 09 12:48:56 PM PDT 24
Finished May 09 12:50:12 PM PDT 24
Peak memory 1410548 kb
Host smart-8bebb519-5c05-458b-9178-b41ee0edfa2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127538887 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.2127538887
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.344088070
Short name T1335
Test name
Test status
Simulation time 4730438957 ps
CPU time 16.9 seconds
Started May 09 12:48:56 PM PDT 24
Finished May 09 12:49:15 PM PDT 24
Peak memory 204432 kb
Host smart-508cf1c9-616c-4bc1-81c3-58ee31040c19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344088070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_tar
get_smoke.344088070
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.1929862830
Short name T1114
Test name
Test status
Simulation time 357335195 ps
CPU time 5.8 seconds
Started May 09 12:48:55 PM PDT 24
Finished May 09 12:49:03 PM PDT 24
Peak memory 204420 kb
Host smart-48fb37f1-a351-4b38-ae15-5b68fab761aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929862830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.1929862830
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.138174832
Short name T1118
Test name
Test status
Simulation time 30635275566 ps
CPU time 203.64 seconds
Started May 09 12:48:55 PM PDT 24
Finished May 09 12:52:20 PM PDT 24
Peak memory 2472944 kb
Host smart-b8e68036-f15b-4b88-964a-3dbc510326e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138174832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_wr.138174832
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.168962516
Short name T507
Test name
Test status
Simulation time 30011521553 ps
CPU time 1950.59 seconds
Started May 09 12:48:56 PM PDT 24
Finished May 09 01:21:29 PM PDT 24
Peak memory 7264880 kb
Host smart-068ec2e5-670e-4a00-be73-a1d7dc7aafef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168962516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_t
arget_stretch.168962516
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2834139594
Short name T1150
Test name
Test status
Simulation time 1600297399 ps
CPU time 8.34 seconds
Started May 09 12:48:54 PM PDT 24
Finished May 09 12:49:04 PM PDT 24
Peak memory 220644 kb
Host smart-795fc31b-5dd4-417d-8695-d5cc8e1639ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834139594 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2834139594
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.1008325418
Short name T941
Test name
Test status
Simulation time 42271680 ps
CPU time 0.59 seconds
Started May 09 12:49:09 PM PDT 24
Finished May 09 12:49:13 PM PDT 24
Peak memory 204228 kb
Host smart-ae7b5841-0608-4cef-b48c-cfebb7a2e46e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008325418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.1008325418
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.3101686898
Short name T930
Test name
Test status
Simulation time 271985748 ps
CPU time 1.21 seconds
Started May 09 12:49:07 PM PDT 24
Finished May 09 12:49:11 PM PDT 24
Peak memory 212732 kb
Host smart-bf5fc0eb-37d2-41dc-9775-7dc7e7a26bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101686898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.3101686898
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.2948279434
Short name T556
Test name
Test status
Simulation time 392753327 ps
CPU time 8.79 seconds
Started May 09 12:49:09 PM PDT 24
Finished May 09 12:49:21 PM PDT 24
Peak memory 286756 kb
Host smart-0ba64bde-31dc-4edf-b461-6872b0083dae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948279434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.2948279434
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.1017796059
Short name T803
Test name
Test status
Simulation time 7407692518 ps
CPU time 157.55 seconds
Started May 09 12:49:09 PM PDT 24
Finished May 09 12:51:49 PM PDT 24
Peak memory 722324 kb
Host smart-6132c373-377e-47b9-ae47-ba2298e82591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017796059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.1017796059
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.1786648392
Short name T281
Test name
Test status
Simulation time 20010506458 ps
CPU time 37.92 seconds
Started May 09 12:49:06 PM PDT 24
Finished May 09 12:49:45 PM PDT 24
Peak memory 504564 kb
Host smart-a3158a37-9b32-4325-9919-f44066c0136d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786648392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.1786648392
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.4215105986
Short name T616
Test name
Test status
Simulation time 284800598 ps
CPU time 0.92 seconds
Started May 09 12:49:11 PM PDT 24
Finished May 09 12:49:15 PM PDT 24
Peak memory 204224 kb
Host smart-53712109-3f7f-4d09-890a-2159499df7d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215105986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.4215105986
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.2022345741
Short name T722
Test name
Test status
Simulation time 550937195 ps
CPU time 8.46 seconds
Started May 09 12:49:06 PM PDT 24
Finished May 09 12:49:16 PM PDT 24
Peak memory 204392 kb
Host smart-51b2bbc2-27f9-421e-9897-25fa0026a0c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022345741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.2022345741
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.625703908
Short name T864
Test name
Test status
Simulation time 4046764479 ps
CPU time 265.52 seconds
Started May 09 12:49:06 PM PDT 24
Finished May 09 12:53:33 PM PDT 24
Peak memory 978092 kb
Host smart-1932c8f3-00c4-49cc-b2b2-8065db625d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625703908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.625703908
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.4163206418
Short name T979
Test name
Test status
Simulation time 762171593 ps
CPU time 6.18 seconds
Started May 09 12:49:08 PM PDT 24
Finished May 09 12:49:17 PM PDT 24
Peak memory 204684 kb
Host smart-eec567c7-d490-4483-a25c-f3f42534c312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163206418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.4163206418
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.2144831089
Short name T901
Test name
Test status
Simulation time 6219497035 ps
CPU time 23.12 seconds
Started May 09 12:49:09 PM PDT 24
Finished May 09 12:49:35 PM PDT 24
Peak memory 310716 kb
Host smart-78cd746f-e05a-4d1c-a37d-6c7706ba5101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144831089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.2144831089
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.3556360108
Short name T898
Test name
Test status
Simulation time 28196776 ps
CPU time 0.69 seconds
Started May 09 12:48:57 PM PDT 24
Finished May 09 12:49:00 PM PDT 24
Peak memory 204156 kb
Host smart-49b2f564-0558-4724-b113-c4873f87d88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556360108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.3556360108
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.3908727050
Short name T479
Test name
Test status
Simulation time 6937323309 ps
CPU time 251.1 seconds
Started May 09 12:49:09 PM PDT 24
Finished May 09 12:53:23 PM PDT 24
Peak memory 994720 kb
Host smart-99e58d86-49d2-4be4-9f98-7d0d593f38af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908727050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.3908727050
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.1491129227
Short name T809
Test name
Test status
Simulation time 5886888399 ps
CPU time 25.05 seconds
Started May 09 12:48:57 PM PDT 24
Finished May 09 12:49:24 PM PDT 24
Peak memory 359028 kb
Host smart-7cff8279-ea19-49be-b0bb-5eeb497415ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491129227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.1491129227
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.605441294
Short name T111
Test name
Test status
Simulation time 10954280715 ps
CPU time 154.7 seconds
Started May 09 12:49:08 PM PDT 24
Finished May 09 12:51:45 PM PDT 24
Peak memory 643616 kb
Host smart-c937aa85-8c54-41a9-9cbb-7ee1486e0251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605441294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.605441294
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.1821035978
Short name T692
Test name
Test status
Simulation time 2087730506 ps
CPU time 8.74 seconds
Started May 09 12:49:08 PM PDT 24
Finished May 09 12:49:20 PM PDT 24
Peak memory 220852 kb
Host smart-823bfa97-cf60-4d56-aaea-848ef621d5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821035978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.1821035978
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.2814407750
Short name T751
Test name
Test status
Simulation time 1538539374 ps
CPU time 3.65 seconds
Started May 09 12:49:08 PM PDT 24
Finished May 09 12:49:15 PM PDT 24
Peak memory 217424 kb
Host smart-c18a4797-338f-4457-9338-8b78310c09a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814407750 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.2814407750
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.2023553564
Short name T659
Test name
Test status
Simulation time 10077979013 ps
CPU time 71.32 seconds
Started May 09 12:49:07 PM PDT 24
Finished May 09 12:50:22 PM PDT 24
Peak memory 516756 kb
Host smart-5d79fb9d-c81b-4a1c-8433-c2c5c7565372
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023553564 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.2023553564
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.396264435
Short name T576
Test name
Test status
Simulation time 10293470263 ps
CPU time 27.71 seconds
Started May 09 12:49:06 PM PDT 24
Finished May 09 12:49:36 PM PDT 24
Peak memory 364600 kb
Host smart-72efd018-2b62-4f4b-aea6-7f1c09ba4281
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396264435 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.i2c_target_fifo_reset_tx.396264435
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.520968489
Short name T1260
Test name
Test status
Simulation time 6899226326 ps
CPU time 2.76 seconds
Started May 09 12:49:07 PM PDT 24
Finished May 09 12:49:13 PM PDT 24
Peak memory 204512 kb
Host smart-b1b01c56-31b7-41ca-8e5f-90c361f0c4f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520968489 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_hrst.520968489
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.1419593160
Short name T1350
Test name
Test status
Simulation time 5409491492 ps
CPU time 7.24 seconds
Started May 09 12:49:05 PM PDT 24
Finished May 09 12:49:14 PM PDT 24
Peak memory 218504 kb
Host smart-66d56c30-cc19-43a1-9adb-13372ab6a6b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419593160 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.1419593160
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.3480156668
Short name T1070
Test name
Test status
Simulation time 10325037742 ps
CPU time 54.34 seconds
Started May 09 12:49:07 PM PDT 24
Finished May 09 12:50:04 PM PDT 24
Peak memory 1297104 kb
Host smart-5458f755-8b15-4893-8465-38ae5abfaece
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480156668 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.3480156668
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.1032430236
Short name T871
Test name
Test status
Simulation time 849814748 ps
CPU time 14.3 seconds
Started May 09 12:49:06 PM PDT 24
Finished May 09 12:49:22 PM PDT 24
Peak memory 204460 kb
Host smart-2e4ef6a5-00da-452c-8ad6-7fe9ccd69450
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032430236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.1032430236
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.1471054484
Short name T229
Test name
Test status
Simulation time 11154187055 ps
CPU time 127.59 seconds
Started May 09 12:49:08 PM PDT 24
Finished May 09 12:51:18 PM PDT 24
Peak memory 1369012 kb
Host smart-f45f4eca-7d16-472a-868c-99ff778fef99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471054484 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_stress_all.1471054484
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.2457477018
Short name T667
Test name
Test status
Simulation time 23233530645 ps
CPU time 14.52 seconds
Started May 09 12:49:09 PM PDT 24
Finished May 09 12:49:26 PM PDT 24
Peak memory 254556 kb
Host smart-40a3e976-a7e3-4745-8347-5a498da8c5ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457477018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.2457477018
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.1937800811
Short name T772
Test name
Test status
Simulation time 27224023635 ps
CPU time 1735.14 seconds
Started May 09 12:49:10 PM PDT 24
Finished May 09 01:18:08 PM PDT 24
Peak memory 6755428 kb
Host smart-81d551c4-ef9c-4872-8177-157b845df834
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937800811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.1937800811
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.901586337
Short name T873
Test name
Test status
Simulation time 1103116232 ps
CPU time 6.77 seconds
Started May 09 12:49:07 PM PDT 24
Finished May 09 12:49:16 PM PDT 24
Peak memory 220752 kb
Host smart-723fb8ba-feeb-4771-9bc0-7ffb547a4f92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901586337 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_timeout.901586337
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.934662266
Short name T1146
Test name
Test status
Simulation time 48500266 ps
CPU time 0.61 seconds
Started May 09 12:49:20 PM PDT 24
Finished May 09 12:49:25 PM PDT 24
Peak memory 204176 kb
Host smart-0c6770f3-83fc-486c-86b1-c81a6beeb1bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934662266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.934662266
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.3362733502
Short name T1363
Test name
Test status
Simulation time 126846214 ps
CPU time 1.61 seconds
Started May 09 12:49:09 PM PDT 24
Finished May 09 12:49:13 PM PDT 24
Peak memory 212692 kb
Host smart-273b847f-e5b3-4546-991c-90c58e5f8799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362733502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.3362733502
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.2539206102
Short name T1056
Test name
Test status
Simulation time 576422723 ps
CPU time 10.2 seconds
Started May 09 12:49:06 PM PDT 24
Finished May 09 12:49:18 PM PDT 24
Peak memory 300552 kb
Host smart-da120758-dfc2-423d-bbdb-299a079f4408
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539206102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.2539206102
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.1614071121
Short name T1143
Test name
Test status
Simulation time 1230995032 ps
CPU time 33.89 seconds
Started May 09 12:49:11 PM PDT 24
Finished May 09 12:49:47 PM PDT 24
Peak memory 479684 kb
Host smart-ef19c855-7658-4429-85af-72399e85eeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614071121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1614071121
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.2205267027
Short name T670
Test name
Test status
Simulation time 3647377082 ps
CPU time 48.71 seconds
Started May 09 12:49:07 PM PDT 24
Finished May 09 12:49:59 PM PDT 24
Peak memory 579116 kb
Host smart-d1808c12-bcfb-4858-b907-6f4761eef6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205267027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.2205267027
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.2130489574
Short name T943
Test name
Test status
Simulation time 104532951 ps
CPU time 0.76 seconds
Started May 09 12:49:08 PM PDT 24
Finished May 09 12:49:11 PM PDT 24
Peak memory 204188 kb
Host smart-73b3271d-3a51-46dc-83dc-d4242aae9260
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130489574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.2130489574
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.4234551987
Short name T1105
Test name
Test status
Simulation time 197029110 ps
CPU time 5.26 seconds
Started May 09 12:49:07 PM PDT 24
Finished May 09 12:49:15 PM PDT 24
Peak memory 238008 kb
Host smart-2cecf654-cdb4-4c17-8af4-09dc55a4010b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234551987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.4234551987
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.1171304335
Short name T603
Test name
Test status
Simulation time 8329297641 ps
CPU time 330.72 seconds
Started May 09 12:49:07 PM PDT 24
Finished May 09 12:54:40 PM PDT 24
Peak memory 1213620 kb
Host smart-bae89249-e29c-4d66-b348-42927e24cbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171304335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.1171304335
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.256538610
Short name T72
Test name
Test status
Simulation time 638568962 ps
CPU time 5.04 seconds
Started May 09 12:49:20 PM PDT 24
Finished May 09 12:49:29 PM PDT 24
Peak memory 204352 kb
Host smart-68686bd8-3688-4620-946d-c193f4e2ec0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256538610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.256538610
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.1399379665
Short name T586
Test name
Test status
Simulation time 944564876 ps
CPU time 14.85 seconds
Started May 09 12:49:18 PM PDT 24
Finished May 09 12:49:37 PM PDT 24
Peak memory 300028 kb
Host smart-a7bde581-666d-4c29-9bcd-08eb4c2af181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399379665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.1399379665
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.281785613
Short name T127
Test name
Test status
Simulation time 102372980 ps
CPU time 0.69 seconds
Started May 09 12:49:08 PM PDT 24
Finished May 09 12:49:11 PM PDT 24
Peak memory 204152 kb
Host smart-56eee584-75d2-44ef-b0fc-c20e8e1342cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281785613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.281785613
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.3854769125
Short name T348
Test name
Test status
Simulation time 24812869983 ps
CPU time 346.62 seconds
Started May 09 12:49:06 PM PDT 24
Finished May 09 12:54:54 PM PDT 24
Peak memory 204528 kb
Host smart-ec290f6e-e113-4c48-abc2-f7a0fd89f172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854769125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3854769125
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.2960477649
Short name T1170
Test name
Test status
Simulation time 1010853930 ps
CPU time 22.33 seconds
Started May 09 12:49:10 PM PDT 24
Finished May 09 12:49:35 PM PDT 24
Peak memory 314760 kb
Host smart-66ddb41a-2df5-4eea-9c97-1809d9c6529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960477649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.2960477649
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.1584508465
Short name T1072
Test name
Test status
Simulation time 12067667653 ps
CPU time 289.38 seconds
Started May 09 12:49:06 PM PDT 24
Finished May 09 12:53:57 PM PDT 24
Peak memory 970584 kb
Host smart-4b64a942-01da-4c66-b63d-5971fa81e714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584508465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.1584508465
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.1207478205
Short name T1294
Test name
Test status
Simulation time 1039366748 ps
CPU time 22.66 seconds
Started May 09 12:49:08 PM PDT 24
Finished May 09 12:49:33 PM PDT 24
Peak memory 212644 kb
Host smart-44f6f0e9-e0fa-42b0-9b8d-3e799e4ef1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207478205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.1207478205
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.112936141
Short name T845
Test name
Test status
Simulation time 567479125 ps
CPU time 3.08 seconds
Started May 09 12:49:18 PM PDT 24
Finished May 09 12:49:26 PM PDT 24
Peak memory 204368 kb
Host smart-23234011-046c-486e-ab58-aec086cb5ef8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112936141 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.112936141
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.4269677922
Short name T981
Test name
Test status
Simulation time 10915353659 ps
CPU time 4.04 seconds
Started May 09 12:49:17 PM PDT 24
Finished May 09 12:49:25 PM PDT 24
Peak memory 217376 kb
Host smart-200daeab-ea3e-4407-b877-95cde02cee39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269677922 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.4269677922
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.3790953723
Short name T481
Test name
Test status
Simulation time 10053822260 ps
CPU time 32.93 seconds
Started May 09 12:49:18 PM PDT 24
Finished May 09 12:49:55 PM PDT 24
Peak memory 318500 kb
Host smart-8a912549-6581-4eba-ac62-57fd0de41c84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790953723 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.3790953723
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.3107633667
Short name T22
Test name
Test status
Simulation time 476631171 ps
CPU time 2.93 seconds
Started May 09 12:49:17 PM PDT 24
Finished May 09 12:49:24 PM PDT 24
Peak memory 204388 kb
Host smart-a7f03302-3cf5-43c0-89ee-5fa680d62186
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107633667 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.3107633667
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.3698768148
Short name T341
Test name
Test status
Simulation time 1226692987 ps
CPU time 3.41 seconds
Started May 09 12:49:07 PM PDT 24
Finished May 09 12:49:12 PM PDT 24
Peak memory 204476 kb
Host smart-3411ddae-c947-43c7-9ee3-4ac5dc8d880c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698768148 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.3698768148
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.3589135109
Short name T1185
Test name
Test status
Simulation time 22462736175 ps
CPU time 65.59 seconds
Started May 09 12:49:07 PM PDT 24
Finished May 09 12:50:15 PM PDT 24
Peak memory 872144 kb
Host smart-96da7d79-b832-4788-a1ab-48724346840e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589135109 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.3589135109
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2344576394
Short name T749
Test name
Test status
Simulation time 1281812586 ps
CPU time 19.13 seconds
Started May 09 12:49:13 PM PDT 24
Finished May 09 12:49:34 PM PDT 24
Peak memory 204440 kb
Host smart-e3b2abde-212a-4a1c-bf71-3d999316b936
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344576394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2344576394
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2056574501
Short name T405
Test name
Test status
Simulation time 4718037061 ps
CPU time 22.23 seconds
Started May 09 12:49:06 PM PDT 24
Finished May 09 12:49:29 PM PDT 24
Peak memory 220268 kb
Host smart-48903f48-1092-42dd-8579-7d7a05d46cad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056574501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2056574501
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.2278469388
Short name T1322
Test name
Test status
Simulation time 49287948106 ps
CPU time 409.14 seconds
Started May 09 12:49:07 PM PDT 24
Finished May 09 12:55:59 PM PDT 24
Peak memory 3745276 kb
Host smart-a2e8b088-b07b-4b92-b6bc-a5215a647f49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278469388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.2278469388
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.2799509336
Short name T246
Test name
Test status
Simulation time 20123362668 ps
CPU time 147.68 seconds
Started May 09 12:49:08 PM PDT 24
Finished May 09 12:51:39 PM PDT 24
Peak memory 1201596 kb
Host smart-cb8e0b06-4012-4a32-8a11-881339d9923a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799509336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.2799509336
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.2911152200
Short name T617
Test name
Test status
Simulation time 1150066512 ps
CPU time 6.28 seconds
Started May 09 12:49:09 PM PDT 24
Finished May 09 12:49:18 PM PDT 24
Peak memory 212688 kb
Host smart-10a415f1-4e51-4ada-802f-58899d1b79f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911152200 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.2911152200
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.182283447
Short name T821
Test name
Test status
Simulation time 17786124 ps
CPU time 0.66 seconds
Started May 09 12:49:22 PM PDT 24
Finished May 09 12:49:28 PM PDT 24
Peak memory 204200 kb
Host smart-38eef079-fb3c-40be-bb47-1e5f11b71db3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182283447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.182283447
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.209744510
Short name T1006
Test name
Test status
Simulation time 54199127 ps
CPU time 1.13 seconds
Started May 09 12:49:18 PM PDT 24
Finished May 09 12:49:23 PM PDT 24
Peak memory 212704 kb
Host smart-17897902-73cd-4d69-91a3-3fbe7200eb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209744510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.209744510
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3212661547
Short name T1081
Test name
Test status
Simulation time 455202024 ps
CPU time 22.52 seconds
Started May 09 12:49:18 PM PDT 24
Finished May 09 12:49:45 PM PDT 24
Peak memory 286088 kb
Host smart-09050e10-cf40-4f03-acf1-b034bea59857
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212661547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.3212661547
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2854256634
Short name T1304
Test name
Test status
Simulation time 1996116021 ps
CPU time 68.05 seconds
Started May 09 12:49:21 PM PDT 24
Finished May 09 12:50:34 PM PDT 24
Peak memory 673612 kb
Host smart-f53981f6-521f-4790-b3f9-c5a3c59efe4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854256634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2854256634
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.835560145
Short name T857
Test name
Test status
Simulation time 17009665183 ps
CPU time 154.77 seconds
Started May 09 12:49:19 PM PDT 24
Finished May 09 12:51:58 PM PDT 24
Peak memory 712012 kb
Host smart-72593b6f-027a-4300-9f73-85f1de6913b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835560145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.835560145
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.1834899597
Short name T394
Test name
Test status
Simulation time 261727561 ps
CPU time 1.22 seconds
Started May 09 12:49:17 PM PDT 24
Finished May 09 12:49:22 PM PDT 24
Peak memory 204448 kb
Host smart-da4ab942-9b37-448c-8799-2e69e2cf628e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834899597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.1834899597
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.1737333297
Short name T1343
Test name
Test status
Simulation time 125256001 ps
CPU time 3.36 seconds
Started May 09 12:49:18 PM PDT 24
Finished May 09 12:49:26 PM PDT 24
Peak memory 221196 kb
Host smart-9ab569d2-fd77-49a5-a879-555d01c480dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737333297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.1737333297
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.4189485134
Short name T273
Test name
Test status
Simulation time 4190761097 ps
CPU time 102.7 seconds
Started May 09 12:49:17 PM PDT 24
Finished May 09 12:51:03 PM PDT 24
Peak memory 1036600 kb
Host smart-91aa8b65-0f83-4016-b249-15f8d67d32e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189485134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.4189485134
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.2359079053
Short name T490
Test name
Test status
Simulation time 236771257 ps
CPU time 9.49 seconds
Started May 09 12:49:22 PM PDT 24
Finished May 09 12:49:36 PM PDT 24
Peak memory 204492 kb
Host smart-243d573a-2862-41d7-a71d-ce29df50a35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359079053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.2359079053
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.1795290292
Short name T804
Test name
Test status
Simulation time 4090180361 ps
CPU time 42.24 seconds
Started May 09 12:49:19 PM PDT 24
Finished May 09 12:50:06 PM PDT 24
Peak memory 357036 kb
Host smart-f3f3a7a9-8e85-4f56-84b5-e390506ad4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795290292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.1795290292
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.3606707244
Short name T430
Test name
Test status
Simulation time 88166233 ps
CPU time 0.67 seconds
Started May 09 12:49:16 PM PDT 24
Finished May 09 12:49:20 PM PDT 24
Peak memory 204096 kb
Host smart-e1104c51-2c75-43fd-b403-27fed1c8377a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606707244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.3606707244
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.1116910934
Short name T534
Test name
Test status
Simulation time 12143603913 ps
CPU time 764.67 seconds
Started May 09 12:49:20 PM PDT 24
Finished May 09 01:02:09 PM PDT 24
Peak memory 1322924 kb
Host smart-5e1068a2-4b5d-4936-a73f-30d8f563de46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116910934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.1116910934
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.3171349138
Short name T798
Test name
Test status
Simulation time 6100285993 ps
CPU time 28.51 seconds
Started May 09 12:49:17 PM PDT 24
Finished May 09 12:49:49 PM PDT 24
Peak memory 350296 kb
Host smart-bdf55b07-fc0c-4f03-aa9f-cfcfaf9fc175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171349138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.3171349138
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.3255327698
Short name T1203
Test name
Test status
Simulation time 9759664533 ps
CPU time 22.36 seconds
Started May 09 12:49:20 PM PDT 24
Finished May 09 12:49:47 PM PDT 24
Peak memory 212776 kb
Host smart-6147d362-6f49-481f-ad8a-1196c081197b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255327698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3255327698
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.583806418
Short name T806
Test name
Test status
Simulation time 1450459050 ps
CPU time 3.58 seconds
Started May 09 12:49:22 PM PDT 24
Finished May 09 12:49:31 PM PDT 24
Peak memory 204472 kb
Host smart-cf3b6c7a-87bf-408a-adeb-5d7ac6cf980b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583806418 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.583806418
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.3509022664
Short name T986
Test name
Test status
Simulation time 10110743247 ps
CPU time 27.64 seconds
Started May 09 12:49:17 PM PDT 24
Finished May 09 12:49:48 PM PDT 24
Peak memory 330192 kb
Host smart-e0b9c4b9-396b-4b3f-b513-55df69f3f0d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509022664 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.3509022664
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.2522901813
Short name T239
Test name
Test status
Simulation time 10278988364 ps
CPU time 33.94 seconds
Started May 09 12:49:20 PM PDT 24
Finished May 09 12:49:59 PM PDT 24
Peak memory 350268 kb
Host smart-8fd5cad6-2154-4a1e-8ff2-e6bdad7f0cd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522901813 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.2522901813
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.2237935929
Short name T266
Test name
Test status
Simulation time 943504208 ps
CPU time 2.92 seconds
Started May 09 12:49:20 PM PDT 24
Finished May 09 12:49:28 PM PDT 24
Peak memory 204416 kb
Host smart-d06213ce-f321-428b-ba41-a929bb0883f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237935929 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.2237935929
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.2957342719
Short name T1209
Test name
Test status
Simulation time 6096853536 ps
CPU time 7.57 seconds
Started May 09 12:49:20 PM PDT 24
Finished May 09 12:49:32 PM PDT 24
Peak memory 220796 kb
Host smart-e9e5bf6e-d10a-4644-8aaf-beba926c55cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957342719 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.2957342719
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.1602856102
Short name T1241
Test name
Test status
Simulation time 22086904992 ps
CPU time 403.13 seconds
Started May 09 12:49:21 PM PDT 24
Finished May 09 12:56:09 PM PDT 24
Peak memory 3933104 kb
Host smart-af7c3ccd-c481-41fb-b06a-c9ba7e4cd97c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602856102 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.1602856102
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.316700678
Short name T788
Test name
Test status
Simulation time 1634812947 ps
CPU time 13.49 seconds
Started May 09 12:49:21 PM PDT 24
Finished May 09 12:49:40 PM PDT 24
Peak memory 204360 kb
Host smart-e409a756-1cd3-4ae1-b699-13cc03afbc40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316700678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_tar
get_smoke.316700678
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.3655462223
Short name T1157
Test name
Test status
Simulation time 2493560612 ps
CPU time 24.73 seconds
Started May 09 12:49:19 PM PDT 24
Finished May 09 12:49:48 PM PDT 24
Peak memory 219228 kb
Host smart-a7f9433f-21e2-4f6f-96bf-dfbab9300331
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655462223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.3655462223
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.393917429
Short name T682
Test name
Test status
Simulation time 23497565978 ps
CPU time 9.66 seconds
Started May 09 12:49:18 PM PDT 24
Finished May 09 12:49:31 PM PDT 24
Peak memory 204452 kb
Host smart-a6ea56af-af35-4a3c-9f7e-bbaac9f80841
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393917429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_wr.393917429
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.2348294022
Short name T291
Test name
Test status
Simulation time 24937389660 ps
CPU time 1386.16 seconds
Started May 09 12:49:18 PM PDT 24
Finished May 09 01:12:29 PM PDT 24
Peak memory 2756916 kb
Host smart-3dad50e7-a641-40b3-baaa-b116c389bf13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348294022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.2348294022
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.938686861
Short name T776
Test name
Test status
Simulation time 5258124923 ps
CPU time 7.04 seconds
Started May 09 12:49:19 PM PDT 24
Finished May 09 12:49:31 PM PDT 24
Peak memory 215640 kb
Host smart-011cbf43-0a55-46d8-8b63-78cd51275e97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938686861 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_timeout.938686861
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.871404551
Short name T544
Test name
Test status
Simulation time 27842273 ps
CPU time 0.62 seconds
Started May 09 12:49:28 PM PDT 24
Finished May 09 12:49:33 PM PDT 24
Peak memory 204196 kb
Host smart-17787be4-5390-488c-8c9e-eb6be160e37b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871404551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.871404551
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.2847429478
Short name T623
Test name
Test status
Simulation time 83628027 ps
CPU time 1.6 seconds
Started May 09 12:49:21 PM PDT 24
Finished May 09 12:49:28 PM PDT 24
Peak memory 212748 kb
Host smart-9dff329e-b3c5-4b33-886e-2203f4eee189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847429478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.2847429478
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2662071386
Short name T577
Test name
Test status
Simulation time 1060901512 ps
CPU time 13.21 seconds
Started May 09 12:49:23 PM PDT 24
Finished May 09 12:49:42 PM PDT 24
Peak memory 254596 kb
Host smart-0e2f4aaa-6097-4b3c-a406-866ab12750e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662071386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2662071386
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.2270874469
Short name T707
Test name
Test status
Simulation time 1377027009 ps
CPU time 30.66 seconds
Started May 09 12:49:23 PM PDT 24
Finished May 09 12:49:59 PM PDT 24
Peak memory 304704 kb
Host smart-999fdbfc-cad2-46f3-969e-02ba8b783235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270874469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.2270874469
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.544351550
Short name T932
Test name
Test status
Simulation time 1107722584 ps
CPU time 34.56 seconds
Started May 09 12:49:22 PM PDT 24
Finished May 09 12:50:01 PM PDT 24
Peak memory 478472 kb
Host smart-a2f7d450-aa2a-45af-8aff-6c9551cc3c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544351550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.544351550
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.1022623913
Short name T1362
Test name
Test status
Simulation time 110328517 ps
CPU time 1.01 seconds
Started May 09 12:49:22 PM PDT 24
Finished May 09 12:49:28 PM PDT 24
Peak memory 204436 kb
Host smart-cc8efbc5-f44f-4784-9b05-10e0eb021a75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022623913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.1022623913
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.1571615263
Short name T474
Test name
Test status
Simulation time 179456935 ps
CPU time 8.72 seconds
Started May 09 12:49:21 PM PDT 24
Finished May 09 12:49:35 PM PDT 24
Peak memory 204436 kb
Host smart-a17b3cca-253b-4c06-a8ae-f91ac7ad3530
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571615263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.1571615263
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.2920914043
Short name T640
Test name
Test status
Simulation time 2281389684 ps
CPU time 143.84 seconds
Started May 09 12:49:23 PM PDT 24
Finished May 09 12:51:52 PM PDT 24
Peak memory 745688 kb
Host smart-a2daaa48-4e6e-4c8d-9ca5-efb7b65b1588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920914043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.2920914043
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.3759195190
Short name T1264
Test name
Test status
Simulation time 646013420 ps
CPU time 5.82 seconds
Started May 09 12:49:35 PM PDT 24
Finished May 09 12:49:44 PM PDT 24
Peak memory 204456 kb
Host smart-8df02987-b9b9-4154-99e6-942847435a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759195190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.3759195190
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.3022515353
Short name T493
Test name
Test status
Simulation time 1460068116 ps
CPU time 74.47 seconds
Started May 09 12:49:31 PM PDT 24
Finished May 09 12:50:50 PM PDT 24
Peak memory 365096 kb
Host smart-4482c4e7-f074-4197-8ca4-a3b8cf20550c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022515353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.3022515353
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.100401846
Short name T589
Test name
Test status
Simulation time 131537028 ps
CPU time 0.66 seconds
Started May 09 12:49:21 PM PDT 24
Finished May 09 12:49:27 PM PDT 24
Peak memory 204128 kb
Host smart-95c6a489-11ab-40f4-959e-0c9d96007701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100401846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.100401846
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.2440907341
Short name T324
Test name
Test status
Simulation time 5025197830 ps
CPU time 63.46 seconds
Started May 09 12:49:21 PM PDT 24
Finished May 09 12:50:30 PM PDT 24
Peak memory 225816 kb
Host smart-fb767577-1a36-4588-9523-ced3700b1fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440907341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.2440907341
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.4093164094
Short name T1177
Test name
Test status
Simulation time 4900451265 ps
CPU time 59.2 seconds
Started May 09 12:49:21 PM PDT 24
Finished May 09 12:50:26 PM PDT 24
Peak memory 301980 kb
Host smart-10967a5a-89d8-4df6-b49b-00b1e832ef1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093164094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.4093164094
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.3858267974
Short name T529
Test name
Test status
Simulation time 3012520556 ps
CPU time 17.74 seconds
Started May 09 12:49:23 PM PDT 24
Finished May 09 12:49:46 PM PDT 24
Peak memory 229132 kb
Host smart-1bcde387-2aab-4414-8228-44f9550eebe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858267974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.3858267974
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.842576997
Short name T452
Test name
Test status
Simulation time 889378529 ps
CPU time 4.42 seconds
Started May 09 12:49:36 PM PDT 24
Finished May 09 12:49:44 PM PDT 24
Peak memory 212636 kb
Host smart-0692c1d8-d4a4-47b3-99c1-412cf504e79a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842576997 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.842576997
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.2574472156
Short name T863
Test name
Test status
Simulation time 10263846228 ps
CPU time 13.75 seconds
Started May 09 12:49:35 PM PDT 24
Finished May 09 12:49:52 PM PDT 24
Peak memory 253896 kb
Host smart-5c32d85b-8f51-407f-9e82-e048b231afc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574472156 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.2574472156
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.1608865235
Short name T57
Test name
Test status
Simulation time 10077157599 ps
CPU time 71.62 seconds
Started May 09 12:49:30 PM PDT 24
Finished May 09 12:50:46 PM PDT 24
Peak memory 556824 kb
Host smart-c503a3b4-4a8a-4576-b7eb-09030a2bb858
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608865235 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.1608865235
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.2379678134
Short name T959
Test name
Test status
Simulation time 412719802 ps
CPU time 2.61 seconds
Started May 09 12:49:30 PM PDT 24
Finished May 09 12:49:37 PM PDT 24
Peak memory 204456 kb
Host smart-e23a8dec-b4ea-4a92-9f1a-78cb39211d9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379678134 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.2379678134
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.3862858095
Short name T725
Test name
Test status
Simulation time 2435711381 ps
CPU time 4 seconds
Started May 09 12:49:31 PM PDT 24
Finished May 09 12:49:39 PM PDT 24
Peak memory 204544 kb
Host smart-b7f20432-378c-40fe-81c5-1115f10300d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862858095 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.3862858095
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.3419102708
Short name T818
Test name
Test status
Simulation time 15393269084 ps
CPU time 4.51 seconds
Started May 09 12:49:36 PM PDT 24
Finished May 09 12:49:43 PM PDT 24
Peak memory 204436 kb
Host smart-564668f7-4013-4861-9ff0-039e233f0c31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419102708 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.3419102708
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.3128193193
Short name T729
Test name
Test status
Simulation time 782902147 ps
CPU time 13.35 seconds
Started May 09 12:49:36 PM PDT 24
Finished May 09 12:49:52 PM PDT 24
Peak memory 204436 kb
Host smart-bbebacb1-a697-4feb-ae3f-ddced9fb7fed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128193193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.3128193193
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.3864567663
Short name T637
Test name
Test status
Simulation time 2126563951 ps
CPU time 7.25 seconds
Started May 09 12:49:28 PM PDT 24
Finished May 09 12:49:39 PM PDT 24
Peak memory 204484 kb
Host smart-bf95aec0-9219-4535-8914-4f1a8e916a5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864567663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.3864567663
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.2252052472
Short name T1355
Test name
Test status
Simulation time 28547055351 ps
CPU time 24.36 seconds
Started May 09 12:49:29 PM PDT 24
Finished May 09 12:49:58 PM PDT 24
Peak memory 547272 kb
Host smart-395ca3ce-cc7a-43d0-8009-fbad48693c5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252052472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.2252052472
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.2047644279
Short name T1227
Test name
Test status
Simulation time 19644433763 ps
CPU time 304.34 seconds
Started May 09 12:49:26 PM PDT 24
Finished May 09 12:54:35 PM PDT 24
Peak memory 2364344 kb
Host smart-d500a465-3163-4521-b6f2-1cbd06c04e10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047644279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.2047644279
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.898401661
Short name T928
Test name
Test status
Simulation time 1404421150 ps
CPU time 7.82 seconds
Started May 09 12:49:31 PM PDT 24
Finished May 09 12:49:43 PM PDT 24
Peak memory 220972 kb
Host smart-333710ed-3eb0-4690-bedd-611603288cc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898401661 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_timeout.898401661
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.364683311
Short name T579
Test name
Test status
Simulation time 14799631 ps
CPU time 0.61 seconds
Started May 09 12:49:39 PM PDT 24
Finished May 09 12:49:43 PM PDT 24
Peak memory 204188 kb
Host smart-92e8f21d-31c3-43e7-967c-f46826fb7037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364683311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.364683311
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.750566839
Short name T1003
Test name
Test status
Simulation time 112818857 ps
CPU time 1.6 seconds
Started May 09 12:49:27 PM PDT 24
Finished May 09 12:49:33 PM PDT 24
Peak memory 220916 kb
Host smart-e2dc8a7e-adab-47ff-8283-6c60a0974d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750566839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.750566839
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.484127905
Short name T1219
Test name
Test status
Simulation time 301838582 ps
CPU time 4.87 seconds
Started May 09 12:49:34 PM PDT 24
Finished May 09 12:49:42 PM PDT 24
Peak memory 229740 kb
Host smart-d8e6828f-7c2a-4c75-9173-d1b919ad85a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484127905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empt
y.484127905
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.982247992
Short name T961
Test name
Test status
Simulation time 12503367486 ps
CPU time 96.57 seconds
Started May 09 12:49:31 PM PDT 24
Finished May 09 12:51:12 PM PDT 24
Peak memory 490100 kb
Host smart-9bd6c7a1-c328-4cdf-b973-8e411c3e49bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982247992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.982247992
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.1992701415
Short name T610
Test name
Test status
Simulation time 2131307550 ps
CPU time 66.28 seconds
Started May 09 12:49:36 PM PDT 24
Finished May 09 12:50:45 PM PDT 24
Peak memory 732256 kb
Host smart-a11e823d-db85-4f39-b1f4-d2857fb3ca8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992701415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.1992701415
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.1017533942
Short name T519
Test name
Test status
Simulation time 98671980 ps
CPU time 0.92 seconds
Started May 09 12:49:36 PM PDT 24
Finished May 09 12:49:41 PM PDT 24
Peak memory 204224 kb
Host smart-f52ba116-b284-49b8-b12c-dff1379bf0ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017533942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.1017533942
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.2974404015
Short name T917
Test name
Test status
Simulation time 105239893 ps
CPU time 5.57 seconds
Started May 09 12:49:37 PM PDT 24
Finished May 09 12:49:45 PM PDT 24
Peak memory 204432 kb
Host smart-f013a2d0-35a1-453e-a700-e670bd3c452f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974404015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.2974404015
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.1129579403
Short name T1076
Test name
Test status
Simulation time 4255766719 ps
CPU time 364.12 seconds
Started May 09 12:49:31 PM PDT 24
Finished May 09 12:55:39 PM PDT 24
Peak memory 1260808 kb
Host smart-92fd1cf7-752c-4dc3-8015-32be0918cff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129579403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.1129579403
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.827098886
Short name T810
Test name
Test status
Simulation time 1442669149 ps
CPU time 15.39 seconds
Started May 09 12:49:38 PM PDT 24
Finished May 09 12:49:56 PM PDT 24
Peak memory 204404 kb
Host smart-9a8e6f76-0716-4360-acea-ea681e317ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827098886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.827098886
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.4148272569
Short name T1142
Test name
Test status
Simulation time 11921481769 ps
CPU time 40.58 seconds
Started May 09 12:49:39 PM PDT 24
Finished May 09 12:50:22 PM PDT 24
Peak memory 327076 kb
Host smart-8ce5d728-406b-4bac-8e3a-cb43f8fdb08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148272569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.4148272569
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.4008697756
Short name T282
Test name
Test status
Simulation time 91292164 ps
CPU time 0.67 seconds
Started May 09 12:49:32 PM PDT 24
Finished May 09 12:49:37 PM PDT 24
Peak memory 204132 kb
Host smart-25cc65e2-17f6-4726-8acd-8f3995e9ec59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008697756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.4008697756
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.3086767893
Short name T893
Test name
Test status
Simulation time 27544078568 ps
CPU time 1108.71 seconds
Started May 09 12:49:30 PM PDT 24
Finished May 09 01:08:03 PM PDT 24
Peak memory 204532 kb
Host smart-8030e79e-756b-4fd1-8b17-322bd364b92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086767893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.3086767893
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.509374158
Short name T676
Test name
Test status
Simulation time 2404248299 ps
CPU time 25.89 seconds
Started May 09 12:49:29 PM PDT 24
Finished May 09 12:49:59 PM PDT 24
Peak memory 316488 kb
Host smart-032322ae-5887-4dd7-b1c0-df13f2a7b13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509374158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.509374158
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.1483348928
Short name T99
Test name
Test status
Simulation time 27501637541 ps
CPU time 191.84 seconds
Started May 09 12:49:36 PM PDT 24
Finished May 09 12:52:51 PM PDT 24
Peak memory 860528 kb
Host smart-a4c52683-3480-46f6-b676-680279c1fbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483348928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.1483348928
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.2795782850
Short name T956
Test name
Test status
Simulation time 2342383214 ps
CPU time 9.07 seconds
Started May 09 12:49:27 PM PDT 24
Finished May 09 12:49:41 PM PDT 24
Peak memory 219548 kb
Host smart-7a9c484b-fc84-4d01-862a-112e6c718755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795782850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.2795782850
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.2464757416
Short name T1345
Test name
Test status
Simulation time 680195621 ps
CPU time 3.43 seconds
Started May 09 12:49:38 PM PDT 24
Finished May 09 12:49:44 PM PDT 24
Peak memory 204448 kb
Host smart-f845cea0-62aa-436f-a33c-95cb3bfe5b81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464757416 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.2464757416
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.3999317183
Short name T436
Test name
Test status
Simulation time 10056313262 ps
CPU time 78.46 seconds
Started May 09 12:49:30 PM PDT 24
Finished May 09 12:50:53 PM PDT 24
Peak memory 453556 kb
Host smart-7d26d8f7-fecd-4507-ba73-ef65bfc65188
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999317183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.3999317183
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.226022036
Short name T67
Test name
Test status
Simulation time 10050879947 ps
CPU time 79.91 seconds
Started May 09 12:49:35 PM PDT 24
Finished May 09 12:50:59 PM PDT 24
Peak memory 484196 kb
Host smart-d1c5ec64-153a-4504-96de-8e0eaaa6176b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226022036 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_fifo_reset_tx.226022036
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.4094515509
Short name T1261
Test name
Test status
Simulation time 739807123 ps
CPU time 2.21 seconds
Started May 09 12:49:38 PM PDT 24
Finished May 09 12:49:43 PM PDT 24
Peak memory 204500 kb
Host smart-1b8ba15f-22d1-4225-9e59-73182e177b83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094515509 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.4094515509
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.721191498
Short name T614
Test name
Test status
Simulation time 1218355713 ps
CPU time 3.46 seconds
Started May 09 12:49:35 PM PDT 24
Finished May 09 12:49:42 PM PDT 24
Peak memory 204348 kb
Host smart-e3d72c14-7335-42db-a0e3-462fadf782e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721191498 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_intr_smoke.721191498
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.1625974161
Short name T1269
Test name
Test status
Simulation time 12947321605 ps
CPU time 108.53 seconds
Started May 09 12:49:35 PM PDT 24
Finished May 09 12:51:27 PM PDT 24
Peak memory 1630416 kb
Host smart-377f4d57-5fed-4b2c-9c88-2bd20dce407c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625974161 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.1625974161
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.327606664
Short name T149
Test name
Test status
Simulation time 738528855 ps
CPU time 28.66 seconds
Started May 09 12:49:35 PM PDT 24
Finished May 09 12:50:07 PM PDT 24
Peak memory 204444 kb
Host smart-1e176838-780d-49f0-b121-b8dbcf5849a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327606664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_tar
get_smoke.327606664
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3716778598
Short name T247
Test name
Test status
Simulation time 1278506547 ps
CPU time 21.93 seconds
Started May 09 12:49:29 PM PDT 24
Finished May 09 12:49:55 PM PDT 24
Peak memory 214220 kb
Host smart-c5ca7106-9b6b-4ed4-bb05-8204c561a75d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716778598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3716778598
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.1565629340
Short name T1077
Test name
Test status
Simulation time 51744498386 ps
CPU time 170.53 seconds
Started May 09 12:49:29 PM PDT 24
Finished May 09 12:52:24 PM PDT 24
Peak memory 2100332 kb
Host smart-62ae06b7-3e73-4ae7-8f28-f43f1316e00c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565629340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.1565629340
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.1726771665
Short name T952
Test name
Test status
Simulation time 8225233273 ps
CPU time 629.83 seconds
Started May 09 12:49:32 PM PDT 24
Finished May 09 01:00:06 PM PDT 24
Peak memory 1976708 kb
Host smart-3af28dd1-488d-4257-af8f-48f5a72948d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726771665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.1726771665
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.2501214153
Short name T141
Test name
Test status
Simulation time 1407092741 ps
CPU time 7.38 seconds
Started May 09 12:49:29 PM PDT 24
Finished May 09 12:49:41 PM PDT 24
Peak memory 218672 kb
Host smart-4a8ec3ad-99bc-4ca4-960d-cfa048cbb968
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501214153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.2501214153
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.874687028
Short name T946
Test name
Test status
Simulation time 18642565 ps
CPU time 0.64 seconds
Started May 09 12:49:40 PM PDT 24
Finished May 09 12:49:43 PM PDT 24
Peak memory 204120 kb
Host smart-ab0bafb8-ce2d-4554-a408-50faa1871a4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874687028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.874687028
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.3127487510
Short name T438
Test name
Test status
Simulation time 187086723 ps
CPU time 1.41 seconds
Started May 09 12:49:49 PM PDT 24
Finished May 09 12:49:52 PM PDT 24
Peak memory 212672 kb
Host smart-acdaa4d7-1e1d-499e-b8e3-f6d1d2a73178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127487510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3127487510
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.3012985308
Short name T1151
Test name
Test status
Simulation time 506408590 ps
CPU time 5.39 seconds
Started May 09 12:49:42 PM PDT 24
Finished May 09 12:49:49 PM PDT 24
Peak memory 261044 kb
Host smart-70fbe3b8-1f2f-479d-9e39-19a8603a4715
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012985308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.3012985308
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.1993158347
Short name T774
Test name
Test status
Simulation time 2330144500 ps
CPU time 66.42 seconds
Started May 09 12:49:39 PM PDT 24
Finished May 09 12:50:48 PM PDT 24
Peak memory 646640 kb
Host smart-99891101-d525-46a1-8cbe-4c166669cef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993158347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.1993158347
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.1524319925
Short name T1125
Test name
Test status
Simulation time 10625255215 ps
CPU time 137.17 seconds
Started May 09 12:49:40 PM PDT 24
Finished May 09 12:52:00 PM PDT 24
Peak memory 653176 kb
Host smart-ea77ffe7-4e14-4c1a-893b-25d06896f4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524319925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.1524319925
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.420335131
Short name T503
Test name
Test status
Simulation time 414463946 ps
CPU time 0.95 seconds
Started May 09 12:49:49 PM PDT 24
Finished May 09 12:49:52 PM PDT 24
Peak memory 204108 kb
Host smart-c85832e1-bf1c-4a18-a77a-13660f95105a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420335131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fm
t.420335131
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.1462590390
Short name T505
Test name
Test status
Simulation time 1127758729 ps
CPU time 8.63 seconds
Started May 09 12:49:37 PM PDT 24
Finished May 09 12:49:49 PM PDT 24
Peak memory 204452 kb
Host smart-86d0c54f-810c-4c97-b7d4-b1dc58c82e85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462590390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.1462590390
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.3441567913
Short name T781
Test name
Test status
Simulation time 8666663042 ps
CPU time 281.22 seconds
Started May 09 12:49:49 PM PDT 24
Finished May 09 12:54:32 PM PDT 24
Peak memory 1093400 kb
Host smart-1f8a8eea-efc9-4455-873e-98ff5f2e6108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441567913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3441567913
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.4254963822
Short name T899
Test name
Test status
Simulation time 961465329 ps
CPU time 13.61 seconds
Started May 09 12:49:36 PM PDT 24
Finished May 09 12:49:53 PM PDT 24
Peak memory 204372 kb
Host smart-4bf33241-17c0-4589-9099-d2694f26fc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254963822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.4254963822
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.1651790827
Short name T35
Test name
Test status
Simulation time 4410262748 ps
CPU time 52.74 seconds
Started May 09 12:49:39 PM PDT 24
Finished May 09 12:50:35 PM PDT 24
Peak memory 309900 kb
Host smart-0e410b45-7dad-4ca5-b1a8-ab8873111665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651790827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.1651790827
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.705789696
Short name T305
Test name
Test status
Simulation time 24165384 ps
CPU time 0.67 seconds
Started May 09 12:49:37 PM PDT 24
Finished May 09 12:49:41 PM PDT 24
Peak memory 204140 kb
Host smart-15e035cc-0212-476c-be75-d5cf7558876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705789696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.705789696
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.409547708
Short name T371
Test name
Test status
Simulation time 29109350096 ps
CPU time 50.54 seconds
Started May 09 12:49:42 PM PDT 24
Finished May 09 12:50:34 PM PDT 24
Peak memory 297504 kb
Host smart-855ca6c9-57b2-472c-8950-11164ed46434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409547708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.409547708
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.2143889641
Short name T1348
Test name
Test status
Simulation time 3887785938 ps
CPU time 47.83 seconds
Started May 09 12:49:37 PM PDT 24
Finished May 09 12:50:28 PM PDT 24
Peak memory 299604 kb
Host smart-485c8b37-814a-416b-8971-821e3a7c5cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143889641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.2143889641
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.3744915290
Short name T936
Test name
Test status
Simulation time 16228857656 ps
CPU time 1041.96 seconds
Started May 09 12:49:39 PM PDT 24
Finished May 09 01:07:04 PM PDT 24
Peak memory 2888600 kb
Host smart-374e4268-0991-4532-ac48-bf9ea8b2f58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744915290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.3744915290
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.4267754790
Short name T297
Test name
Test status
Simulation time 2302671784 ps
CPU time 10.75 seconds
Started May 09 12:49:38 PM PDT 24
Finished May 09 12:49:53 PM PDT 24
Peak memory 220552 kb
Host smart-db1896da-80ab-4a55-8276-a007f4f601ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267754790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.4267754790
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.1475955720
Short name T165
Test name
Test status
Simulation time 995198069 ps
CPU time 5.19 seconds
Started May 09 12:49:40 PM PDT 24
Finished May 09 12:49:48 PM PDT 24
Peak memory 204652 kb
Host smart-a144a6a9-2149-4f2a-b403-8735d34d5f8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475955720 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.1475955720
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.3915903462
Short name T1112
Test name
Test status
Simulation time 10068070773 ps
CPU time 81.36 seconds
Started May 09 12:49:38 PM PDT 24
Finished May 09 12:51:03 PM PDT 24
Peak memory 440072 kb
Host smart-a7b1c7cb-8946-4a76-8a05-57daa13828ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915903462 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.3915903462
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.2235591243
Short name T1283
Test name
Test status
Simulation time 10095375319 ps
CPU time 75.21 seconds
Started May 09 12:49:38 PM PDT 24
Finished May 09 12:50:57 PM PDT 24
Peak memory 597552 kb
Host smart-1e72e5f8-990b-4cce-994f-e9b46809047f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235591243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.2235591243
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.3751470156
Short name T1360
Test name
Test status
Simulation time 1411048792 ps
CPU time 2.37 seconds
Started May 09 12:49:41 PM PDT 24
Finished May 09 12:49:45 PM PDT 24
Peak memory 204492 kb
Host smart-c81c5827-591f-4c88-a172-d266c6c69cd8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751470156 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.3751470156
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.2463700416
Short name T967
Test name
Test status
Simulation time 4422311626 ps
CPU time 5.94 seconds
Started May 09 12:49:40 PM PDT 24
Finished May 09 12:49:49 PM PDT 24
Peak memory 208068 kb
Host smart-abc8452e-fc62-40f7-9d90-b8c0ece67063
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463700416 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.2463700416
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.213443839
Short name T561
Test name
Test status
Simulation time 10515438306 ps
CPU time 9.48 seconds
Started May 09 12:49:38 PM PDT 24
Finished May 09 12:49:51 PM PDT 24
Peak memory 424520 kb
Host smart-86cda356-899e-4e91-9806-5c3bffd85602
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213443839 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.213443839
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.486165558
Short name T934
Test name
Test status
Simulation time 4285781448 ps
CPU time 27.24 seconds
Started May 09 12:49:37 PM PDT 24
Finished May 09 12:50:08 PM PDT 24
Peak memory 204464 kb
Host smart-c476c57c-c5e4-4ca4-941a-fe0976f57e32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486165558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_tar
get_smoke.486165558
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.3481463057
Short name T1215
Test name
Test status
Simulation time 212721642 ps
CPU time 8.82 seconds
Started May 09 12:49:49 PM PDT 24
Finished May 09 12:49:59 PM PDT 24
Peak memory 204340 kb
Host smart-25ff9d73-0cd4-4397-af86-a1fdf3e7b4d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481463057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.3481463057
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.1925682450
Short name T509
Test name
Test status
Simulation time 56714517624 ps
CPU time 1479.87 seconds
Started May 09 12:49:41 PM PDT 24
Finished May 09 01:14:24 PM PDT 24
Peak memory 8904060 kb
Host smart-6c930f99-5c84-4862-8540-3108bbc7f0dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925682450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.1925682450
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.2213481665
Short name T1092
Test name
Test status
Simulation time 24048036878 ps
CPU time 193.47 seconds
Started May 09 12:49:41 PM PDT 24
Finished May 09 12:52:57 PM PDT 24
Peak memory 1471592 kb
Host smart-6c05283c-6c75-4f2a-89b6-d7d899eaee77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213481665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.2213481665
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.92010409
Short name T643
Test name
Test status
Simulation time 2031401523 ps
CPU time 6.48 seconds
Started May 09 12:49:37 PM PDT 24
Finished May 09 12:49:47 PM PDT 24
Peak memory 217024 kb
Host smart-171ff4af-5858-4fa8-ab87-2eba4587e2a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92010409 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_timeout.92010409
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.52584197
Short name T457
Test name
Test status
Simulation time 26118186 ps
CPU time 0.61 seconds
Started May 09 12:49:49 PM PDT 24
Finished May 09 12:49:52 PM PDT 24
Peak memory 204184 kb
Host smart-e9344cab-1262-4d87-831f-c44b91cdc713
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52584197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.52584197
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.2612135948
Short name T308
Test name
Test status
Simulation time 521047111 ps
CPU time 1.49 seconds
Started May 09 03:24:47 PM PDT 24
Finished May 09 03:25:22 PM PDT 24
Peak memory 212768 kb
Host smart-7af35dba-2dce-4acc-b9ab-968d6c2321c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612135948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.2612135948
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.585188989
Short name T764
Test name
Test status
Simulation time 1513151060 ps
CPU time 12.21 seconds
Started May 09 12:49:50 PM PDT 24
Finished May 09 12:50:04 PM PDT 24
Peak memory 249352 kb
Host smart-47a317db-a5fa-4562-b505-687a67ae322a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585188989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empt
y.585188989
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.2235013642
Short name T185
Test name
Test status
Simulation time 2458030961 ps
CPU time 54.87 seconds
Started May 09 12:49:52 PM PDT 24
Finished May 09 12:50:48 PM PDT 24
Peak memory 407128 kb
Host smart-baf7129a-4739-4b81-adc9-7f38ed231e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235013642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.2235013642
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.1665842480
Short name T449
Test name
Test status
Simulation time 19666746017 ps
CPU time 35.09 seconds
Started May 09 12:49:36 PM PDT 24
Finished May 09 12:50:14 PM PDT 24
Peak memory 418864 kb
Host smart-375b691e-d8b7-4966-b55c-c2dbe040f7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665842480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.1665842480
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.788758177
Short name T933
Test name
Test status
Simulation time 147855671 ps
CPU time 1.09 seconds
Started May 09 12:49:40 PM PDT 24
Finished May 09 12:49:44 PM PDT 24
Peak memory 204188 kb
Host smart-ff762d83-8b6c-439c-b8b5-b68eb58d900f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788758177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fm
t.788758177
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.624805585
Short name T48
Test name
Test status
Simulation time 298876276 ps
CPU time 5.76 seconds
Started May 09 12:49:52 PM PDT 24
Finished May 09 12:50:00 PM PDT 24
Peak memory 204464 kb
Host smart-6da9e071-0b86-4754-b864-0662c32f36d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624805585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.
624805585
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.2025234625
Short name T1054
Test name
Test status
Simulation time 7461925790 ps
CPU time 103.6 seconds
Started May 09 12:49:38 PM PDT 24
Finished May 09 12:51:25 PM PDT 24
Peak memory 1056620 kb
Host smart-2bf75e25-6ba5-49d2-916b-a786d5f65c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025234625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.2025234625
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.3944029580
Short name T1251
Test name
Test status
Simulation time 885878459 ps
CPU time 3.94 seconds
Started May 09 12:49:50 PM PDT 24
Finished May 09 12:49:55 PM PDT 24
Peak memory 204396 kb
Host smart-e9a00c8e-b52a-4c52-9c9e-2d17f02cd34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944029580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.3944029580
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.136541855
Short name T522
Test name
Test status
Simulation time 6397134826 ps
CPU time 31.41 seconds
Started May 09 12:49:49 PM PDT 24
Finished May 09 12:50:22 PM PDT 24
Peak memory 336880 kb
Host smart-576d3cd4-c333-49d0-936c-08e664db1e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136541855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.136541855
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.78183986
Short name T124
Test name
Test status
Simulation time 16986429 ps
CPU time 0.66 seconds
Started May 09 12:49:49 PM PDT 24
Finished May 09 12:49:51 PM PDT 24
Peak memory 204052 kb
Host smart-91ded314-f0ec-493a-9d84-27f2e9ba4d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78183986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.78183986
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.1441453739
Short name T699
Test name
Test status
Simulation time 12735370070 ps
CPU time 123.54 seconds
Started May 09 12:49:52 PM PDT 24
Finished May 09 12:51:58 PM PDT 24
Peak memory 217128 kb
Host smart-2552e3a2-d68e-4ffc-8cd4-1a57d2dea80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441453739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.1441453739
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.3529376731
Short name T296
Test name
Test status
Simulation time 4737068231 ps
CPU time 21.83 seconds
Started May 09 12:49:39 PM PDT 24
Finished May 09 12:50:04 PM PDT 24
Peak memory 308532 kb
Host smart-3d56374b-e1a5-49e3-957e-00c6a10a2282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529376731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.3529376731
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.4059324490
Short name T101
Test name
Test status
Simulation time 8793716179 ps
CPU time 244.14 seconds
Started May 09 03:13:24 PM PDT 24
Finished May 09 03:17:29 PM PDT 24
Peak memory 1555972 kb
Host smart-dc032624-3833-4b39-81ad-3d67fd724b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059324490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.4059324490
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.357755707
Short name T915
Test name
Test status
Simulation time 572289980 ps
CPU time 11.12 seconds
Started May 09 12:49:50 PM PDT 24
Finished May 09 12:50:03 PM PDT 24
Peak memory 214616 kb
Host smart-694cfbf8-d713-4815-be4d-4b5538ca2418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357755707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.357755707
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.238647018
Short name T1139
Test name
Test status
Simulation time 10218199453 ps
CPU time 12.79 seconds
Started May 09 12:49:49 PM PDT 24
Finished May 09 12:50:04 PM PDT 24
Peak memory 264920 kb
Host smart-8d3dd581-bfa0-4253-b3a3-d0d5dbedfb20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238647018 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_acq.238647018
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.2297152636
Short name T812
Test name
Test status
Simulation time 10043408401 ps
CPU time 75.87 seconds
Started May 09 12:49:49 PM PDT 24
Finished May 09 12:51:06 PM PDT 24
Peak memory 549048 kb
Host smart-cc3c0b95-dfab-4b06-a012-dab9b8c9b0af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297152636 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.2297152636
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.1086683130
Short name T842
Test name
Test status
Simulation time 460890595 ps
CPU time 1.98 seconds
Started May 09 12:49:48 PM PDT 24
Finished May 09 12:49:52 PM PDT 24
Peak memory 204488 kb
Host smart-cd1f7dca-8d17-49f7-9153-e5cb5a1f734c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086683130 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.1086683130
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.2144117685
Short name T911
Test name
Test status
Simulation time 2259210579 ps
CPU time 6.44 seconds
Started May 09 12:49:54 PM PDT 24
Finished May 09 12:50:02 PM PDT 24
Peak memory 217596 kb
Host smart-bae8b575-46b9-4de0-8f4f-65ff101721ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144117685 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.2144117685
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.1381298034
Short name T794
Test name
Test status
Simulation time 8566160854 ps
CPU time 107.81 seconds
Started May 09 12:49:49 PM PDT 24
Finished May 09 12:51:39 PM PDT 24
Peak memory 2155756 kb
Host smart-1daf85ea-0f15-43a0-bedd-45cf06b83c41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381298034 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.1381298034
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.3637352986
Short name T458
Test name
Test status
Simulation time 1276011691 ps
CPU time 43.32 seconds
Started May 09 12:49:54 PM PDT 24
Finished May 09 12:50:39 PM PDT 24
Peak memory 204340 kb
Host smart-d354cc89-522e-44f4-896f-0bca5299b842
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637352986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.3637352986
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.3342208108
Short name T131
Test name
Test status
Simulation time 2997417912 ps
CPU time 33.36 seconds
Started May 09 12:49:52 PM PDT 24
Finished May 09 12:50:27 PM PDT 24
Peak memory 204528 kb
Host smart-daf19ab1-c32f-4464-8314-82c55d82aa8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342208108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.3342208108
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.913288003
Short name T344
Test name
Test status
Simulation time 7891475331 ps
CPU time 16.19 seconds
Started May 09 03:24:41 PM PDT 24
Finished May 09 03:25:27 PM PDT 24
Peak memory 204524 kb
Host smart-351dcab9-a07f-476a-8190-96e1f64cfaf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913288003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c
_target_stress_wr.913288003
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.278867025
Short name T668
Test name
Test status
Simulation time 23000732768 ps
CPU time 1178.15 seconds
Started May 09 12:49:49 PM PDT 24
Finished May 09 01:09:29 PM PDT 24
Peak memory 2697956 kb
Host smart-fd01da0c-9aaf-4d41-ab2a-05c8f59d1522
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278867025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_t
arget_stretch.278867025
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.404227584
Short name T883
Test name
Test status
Simulation time 5566252272 ps
CPU time 7.07 seconds
Started May 09 12:49:48 PM PDT 24
Finished May 09 12:49:56 PM PDT 24
Peak memory 220748 kb
Host smart-6d69de2f-ecc9-44dd-ac26-a965d41aeaee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404227584 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_timeout.404227584
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.312206268
Short name T823
Test name
Test status
Simulation time 16912071 ps
CPU time 0.62 seconds
Started May 09 12:50:00 PM PDT 24
Finished May 09 12:50:02 PM PDT 24
Peak memory 204216 kb
Host smart-2c0cc032-105b-4f3e-bc36-fdc8745d55ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312206268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.312206268
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.2241282416
Short name T231
Test name
Test status
Simulation time 241975818 ps
CPU time 1.36 seconds
Started May 09 12:50:03 PM PDT 24
Finished May 09 12:50:07 PM PDT 24
Peak memory 215796 kb
Host smart-1e73691d-0867-4e61-a209-8597f94524a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241282416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.2241282416
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.2048212994
Short name T683
Test name
Test status
Simulation time 545190723 ps
CPU time 4.54 seconds
Started May 09 12:49:52 PM PDT 24
Finished May 09 12:49:58 PM PDT 24
Peak memory 235636 kb
Host smart-4b7f3ac6-e4a5-4167-8fdb-32869275385f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048212994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.2048212994
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.2685136720
Short name T304
Test name
Test status
Simulation time 20572106841 ps
CPU time 86.63 seconds
Started May 09 12:50:01 PM PDT 24
Finished May 09 12:51:30 PM PDT 24
Peak memory 768572 kb
Host smart-0d389a64-6aeb-47a5-9958-4a5ba087933d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685136720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.2685136720
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.3034220671
Short name T588
Test name
Test status
Simulation time 1874125443 ps
CPU time 63.78 seconds
Started May 09 12:49:54 PM PDT 24
Finished May 09 12:50:59 PM PDT 24
Peak memory 660760 kb
Host smart-6a514d84-8ffb-4d1c-a2e8-f290e382316e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034220671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.3034220671
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.2907023745
Short name T343
Test name
Test status
Simulation time 1243248110 ps
CPU time 0.96 seconds
Started May 09 12:49:54 PM PDT 24
Finished May 09 12:49:56 PM PDT 24
Peak memory 204140 kb
Host smart-25a36d9c-1c50-428a-86fc-0caf6c52a302
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907023745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.2907023745
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.672708360
Short name T213
Test name
Test status
Simulation time 424297891 ps
CPU time 7.84 seconds
Started May 09 12:49:49 PM PDT 24
Finished May 09 12:49:59 PM PDT 24
Peak memory 227256 kb
Host smart-9701b5e2-7d34-4122-a87b-e7456ec3759a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672708360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
672708360
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.2547757160
Short name T97
Test name
Test status
Simulation time 3227442180 ps
CPU time 81.03 seconds
Started May 09 12:49:51 PM PDT 24
Finished May 09 12:51:14 PM PDT 24
Peak memory 1005056 kb
Host smart-2d7d621d-1773-4ba1-a295-fbc58bbd12c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547757160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.2547757160
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.4232420973
Short name T74
Test name
Test status
Simulation time 1936330890 ps
CPU time 8.07 seconds
Started May 09 12:50:01 PM PDT 24
Finished May 09 12:50:11 PM PDT 24
Peak memory 204484 kb
Host smart-1bcfa168-26ea-4265-9503-4832f771a200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232420973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.4232420973
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.2653480293
Short name T866
Test name
Test status
Simulation time 8509771759 ps
CPU time 22.03 seconds
Started May 09 12:50:02 PM PDT 24
Finished May 09 12:50:26 PM PDT 24
Peak memory 301696 kb
Host smart-30210768-9ede-4714-843f-e86c8f36b680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653480293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.2653480293
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.1098822357
Short name T485
Test name
Test status
Simulation time 16506247 ps
CPU time 0.67 seconds
Started May 09 12:49:51 PM PDT 24
Finished May 09 12:49:54 PM PDT 24
Peak memory 204152 kb
Host smart-e1d3b3df-5d49-440c-8328-bccb65904f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098822357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.1098822357
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.1366248773
Short name T717
Test name
Test status
Simulation time 5021555977 ps
CPU time 52.89 seconds
Started May 09 12:49:59 PM PDT 24
Finished May 09 12:50:54 PM PDT 24
Peak memory 229028 kb
Host smart-817b2660-02fa-46f5-9f68-e291e02b3221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366248773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.1366248773
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.2905886368
Short name T734
Test name
Test status
Simulation time 799922344 ps
CPU time 15.09 seconds
Started May 09 12:49:50 PM PDT 24
Finished May 09 12:50:07 PM PDT 24
Peak memory 272556 kb
Host smart-27369620-1640-4b19-b34f-54069cc3817b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905886368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.2905886368
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.3822006298
Short name T851
Test name
Test status
Simulation time 3131511948 ps
CPU time 15.96 seconds
Started May 09 12:50:00 PM PDT 24
Finished May 09 12:50:18 PM PDT 24
Peak memory 228924 kb
Host smart-47b22c41-a2f7-41de-9efa-f76027705a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822006298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.3822006298
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.3782272010
Short name T525
Test name
Test status
Simulation time 3190314297 ps
CPU time 4.27 seconds
Started May 09 12:50:10 PM PDT 24
Finished May 09 12:50:17 PM PDT 24
Peak memory 204416 kb
Host smart-26c0b923-17c5-446a-a759-476d1bd8fa18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782272010 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.3782272010
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.3223462275
Short name T336
Test name
Test status
Simulation time 10075481407 ps
CPU time 69.15 seconds
Started May 09 12:49:59 PM PDT 24
Finished May 09 12:51:10 PM PDT 24
Peak memory 451276 kb
Host smart-8bcd88b2-eb57-4f31-9ce2-ecfa2ac7416e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223462275 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.3223462275
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3024007930
Short name T1213
Test name
Test status
Simulation time 10143155748 ps
CPU time 71.6 seconds
Started May 09 12:50:08 PM PDT 24
Finished May 09 12:51:22 PM PDT 24
Peak memory 485816 kb
Host smart-8481c300-b9c2-4e69-bcc0-d4b47b12ad47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024007930 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3024007930
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.127887318
Short name T551
Test name
Test status
Simulation time 375673174 ps
CPU time 2.42 seconds
Started May 09 12:50:01 PM PDT 24
Finished May 09 12:50:06 PM PDT 24
Peak memory 204440 kb
Host smart-d7d6075c-b4d1-4cc0-b0bb-abbbfe00be80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127887318 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.i2c_target_hrst.127887318
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.1563491646
Short name T18
Test name
Test status
Simulation time 11916143560 ps
CPU time 88.77 seconds
Started May 09 12:50:01 PM PDT 24
Finished May 09 12:51:32 PM PDT 24
Peak memory 1353172 kb
Host smart-7e0ef288-0e2f-476c-8143-cde25c8f5bbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563491646 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.1563491646
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.4033825404
Short name T601
Test name
Test status
Simulation time 5320829397 ps
CPU time 16.08 seconds
Started May 09 12:50:02 PM PDT 24
Finished May 09 12:50:20 PM PDT 24
Peak memory 204364 kb
Host smart-0a03af25-0123-44eb-883f-c4a715c84fcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033825404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.4033825404
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.3779793074
Short name T796
Test name
Test status
Simulation time 1893924271 ps
CPU time 38.56 seconds
Started May 09 12:49:59 PM PDT 24
Finished May 09 12:50:40 PM PDT 24
Peak memory 204392 kb
Host smart-8546f54a-dfa9-4921-ae57-3fe6142dd765
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779793074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.3779793074
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.891543196
Short name T368
Test name
Test status
Simulation time 28351417152 ps
CPU time 4.72 seconds
Started May 09 12:50:08 PM PDT 24
Finished May 09 12:50:15 PM PDT 24
Peak memory 204448 kb
Host smart-247f4982-fd53-450a-8421-c2eb7996708e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891543196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_wr.891543196
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.2886880137
Short name T337
Test name
Test status
Simulation time 6994300569 ps
CPU time 144.23 seconds
Started May 09 12:50:10 PM PDT 24
Finished May 09 12:52:37 PM PDT 24
Peak memory 1004948 kb
Host smart-1899b5ad-6f70-4550-822d-2200a2bc9293
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886880137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.2886880137
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.1143338546
Short name T255
Test name
Test status
Simulation time 1418734725 ps
CPU time 6.81 seconds
Started May 09 12:50:08 PM PDT 24
Finished May 09 12:50:17 PM PDT 24
Peak memory 220064 kb
Host smart-117a87a9-5575-41ca-9eba-2b24e5f21481
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143338546 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.1143338546
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.3279672708
Short name T841
Test name
Test status
Simulation time 22113112 ps
CPU time 0.59 seconds
Started May 09 12:46:19 PM PDT 24
Finished May 09 12:46:21 PM PDT 24
Peak memory 204124 kb
Host smart-78066085-e9fd-4017-8551-a46b02bfadec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279672708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.3279672708
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3571528111
Short name T559
Test name
Test status
Simulation time 95860440 ps
CPU time 1.75 seconds
Started May 09 12:46:21 PM PDT 24
Finished May 09 12:46:25 PM PDT 24
Peak memory 212792 kb
Host smart-88fa6dd6-4874-4e4f-92f6-51c46ec113ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571528111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3571528111
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2302727650
Short name T362
Test name
Test status
Simulation time 4068266328 ps
CPU time 20.57 seconds
Started May 09 12:45:53 PM PDT 24
Finished May 09 12:46:15 PM PDT 24
Peak memory 288176 kb
Host smart-75cb7d9c-d023-42df-bedd-0e74e9494e0c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302727650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2302727650
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3054641149
Short name T139
Test name
Test status
Simulation time 1411834148 ps
CPU time 39.79 seconds
Started May 09 12:45:56 PM PDT 24
Finished May 09 12:46:37 PM PDT 24
Peak memory 438808 kb
Host smart-6ae4b2da-0405-46e1-90a8-8cd39ff976bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054641149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3054641149
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.1441738248
Short name T356
Test name
Test status
Simulation time 8145060112 ps
CPU time 141.31 seconds
Started May 09 12:45:55 PM PDT 24
Finished May 09 12:48:18 PM PDT 24
Peak memory 637048 kb
Host smart-63d58372-9aa6-4283-910d-5c465e419cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441738248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.1441738248
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.1241013702
Short name T1116
Test name
Test status
Simulation time 90873512 ps
CPU time 0.99 seconds
Started May 09 12:45:57 PM PDT 24
Finished May 09 12:45:59 PM PDT 24
Peak memory 204348 kb
Host smart-e7b374f1-2e69-465d-ad6c-868026dc1680
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241013702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.1241013702
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.3986003471
Short name T1069
Test name
Test status
Simulation time 745037379 ps
CPU time 3.87 seconds
Started May 09 12:45:58 PM PDT 24
Finished May 09 12:46:03 PM PDT 24
Peak memory 204320 kb
Host smart-0835c3f8-10d7-4bc9-a877-66af355cb01b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986003471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
3986003471
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.4265347584
Short name T1206
Test name
Test status
Simulation time 4212725819 ps
CPU time 332.53 seconds
Started May 09 12:45:55 PM PDT 24
Finished May 09 12:51:29 PM PDT 24
Peak memory 1252876 kb
Host smart-542d52c1-36f7-4d33-9285-54aa503a906b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265347584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.4265347584
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.679603973
Short name T1168
Test name
Test status
Simulation time 647566749 ps
CPU time 8.68 seconds
Started May 09 12:46:19 PM PDT 24
Finished May 09 12:46:29 PM PDT 24
Peak memory 204464 kb
Host smart-5b71c658-e2db-4f3f-bbfb-67d39c336643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679603973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.679603973
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.3368038617
Short name T820
Test name
Test status
Simulation time 8239888978 ps
CPU time 94.58 seconds
Started May 09 12:46:19 PM PDT 24
Finished May 09 12:47:54 PM PDT 24
Peak memory 359132 kb
Host smart-b11ab8b6-45a9-42a7-909a-0a8c96421033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368038617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.3368038617
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.4034408113
Short name T1043
Test name
Test status
Simulation time 33520155 ps
CPU time 0.64 seconds
Started May 09 12:45:54 PM PDT 24
Finished May 09 12:45:56 PM PDT 24
Peak memory 204120 kb
Host smart-9b0034fc-f740-48b9-8cd1-d5c86eca4b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034408113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.4034408113
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.4174799251
Short name T880
Test name
Test status
Simulation time 5639200034 ps
CPU time 5.27 seconds
Started May 09 12:45:55 PM PDT 24
Finished May 09 12:46:02 PM PDT 24
Peak memory 263136 kb
Host smart-cee916df-6135-4acf-82e5-c333b7798a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174799251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.4174799251
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.139623922
Short name T1280
Test name
Test status
Simulation time 1797623064 ps
CPU time 28.88 seconds
Started May 09 12:45:53 PM PDT 24
Finished May 09 12:46:23 PM PDT 24
Peak memory 324436 kb
Host smart-82dce913-433d-4104-ab78-f643408a44cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139623922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.139623922
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.553634086
Short name T604
Test name
Test status
Simulation time 585222823 ps
CPU time 10.38 seconds
Started May 09 12:45:57 PM PDT 24
Finished May 09 12:46:09 PM PDT 24
Peak memory 220776 kb
Host smart-54599efd-ba97-46e4-bdb1-28b54d4b15c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553634086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.553634086
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.813997041
Short name T160
Test name
Test status
Simulation time 71813211 ps
CPU time 0.92 seconds
Started May 09 12:46:21 PM PDT 24
Finished May 09 12:46:24 PM PDT 24
Peak memory 221404 kb
Host smart-81e1334e-7668-4ade-ac8d-6861c97a4ed4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813997041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.813997041
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.452746083
Short name T947
Test name
Test status
Simulation time 624247542 ps
CPU time 3.36 seconds
Started May 09 12:46:22 PM PDT 24
Finished May 09 12:46:27 PM PDT 24
Peak memory 204456 kb
Host smart-3a71c7b6-00b4-4bc3-86b3-e57adaa5ebba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452746083 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.452746083
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.3294638382
Short name T924
Test name
Test status
Simulation time 10131098449 ps
CPU time 70.2 seconds
Started May 09 12:46:22 PM PDT 24
Finished May 09 12:47:34 PM PDT 24
Peak memory 440532 kb
Host smart-ddad8f5b-c184-4ca3-b85f-b3aacc006abc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294638382 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.3294638382
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.2348640128
Short name T11
Test name
Test status
Simulation time 918431899 ps
CPU time 3.05 seconds
Started May 09 12:46:22 PM PDT 24
Finished May 09 12:46:27 PM PDT 24
Peak memory 204448 kb
Host smart-bd420920-7e7c-4e2c-9581-288a2ef1428e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348640128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.2348640128
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.684593857
Short name T330
Test name
Test status
Simulation time 768825834 ps
CPU time 3.88 seconds
Started May 09 12:45:52 PM PDT 24
Finished May 09 12:45:57 PM PDT 24
Peak memory 204352 kb
Host smart-93a3f0ac-badd-42ae-8387-1472cfe73f5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684593857 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_intr_smoke.684593857
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3714717130
Short name T1080
Test name
Test status
Simulation time 5375770403 ps
CPU time 8.31 seconds
Started May 09 12:45:58 PM PDT 24
Finished May 09 12:46:07 PM PDT 24
Peak memory 426624 kb
Host smart-ffcbfe43-dcb8-4c4c-a0df-fb88aebff890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714717130 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3714717130
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.228713798
Short name T994
Test name
Test status
Simulation time 9778914193 ps
CPU time 46.02 seconds
Started May 09 12:45:51 PM PDT 24
Finished May 09 12:46:38 PM PDT 24
Peak memory 204340 kb
Host smart-5e4cac90-09a8-414d-966c-a8cf02f42cdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228713798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_targ
et_smoke.228713798
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.3564904025
Short name T300
Test name
Test status
Simulation time 1938728761 ps
CPU time 15.32 seconds
Started May 09 12:45:57 PM PDT 24
Finished May 09 12:46:13 PM PDT 24
Peak memory 219660 kb
Host smart-d0d95108-5385-4e3c-852c-e142d27e3c2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564904025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.3564904025
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.47866869
Short name T997
Test name
Test status
Simulation time 36218867256 ps
CPU time 32.28 seconds
Started May 09 12:45:54 PM PDT 24
Finished May 09 12:46:28 PM PDT 24
Peak memory 675648 kb
Host smart-5b0097e9-4c5d-425f-9f98-f31df9c3e907
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47866869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stress_wr.47866869
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.1055214326
Short name T1029
Test name
Test status
Simulation time 11839311976 ps
CPU time 36.92 seconds
Started May 09 12:45:53 PM PDT 24
Finished May 09 12:46:31 PM PDT 24
Peak memory 508248 kb
Host smart-bdbe75df-5ba3-4ecc-9c70-4f8c09af3c00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055214326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.1055214326
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.2920961634
Short name T850
Test name
Test status
Simulation time 1147212485 ps
CPU time 6.72 seconds
Started May 09 12:45:55 PM PDT 24
Finished May 09 12:46:03 PM PDT 24
Peak memory 204460 kb
Host smart-adc00119-c88f-42db-9025-1e3322cd1206
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920961634 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.2920961634
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_unexp_stop.1139700991
Short name T15
Test name
Test status
Simulation time 842601642 ps
CPU time 5.2 seconds
Started May 09 12:45:53 PM PDT 24
Finished May 09 12:46:00 PM PDT 24
Peak memory 204300 kb
Host smart-9b60b911-a640-45a4-a948-3c7947504052
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139700991 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.i2c_target_unexp_stop.1139700991
Directory /workspace/3.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/30.i2c_alert_test.4237857505
Short name T501
Test name
Test status
Simulation time 44931612 ps
CPU time 0.63 seconds
Started May 09 12:50:09 PM PDT 24
Finished May 09 12:50:12 PM PDT 24
Peak memory 204244 kb
Host smart-52ceabb9-8468-4b99-8dfd-9d9d650c939b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237857505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.4237857505
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.420538906
Short name T1342
Test name
Test status
Simulation time 364577696 ps
CPU time 1.74 seconds
Started May 09 12:50:00 PM PDT 24
Finished May 09 12:50:04 PM PDT 24
Peak memory 216504 kb
Host smart-24ea1b2b-2b08-4fa9-bc72-ec9e2b1df977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420538906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.420538906
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1403814380
Short name T1277
Test name
Test status
Simulation time 711269403 ps
CPU time 17.45 seconds
Started May 09 12:49:59 PM PDT 24
Finished May 09 12:50:18 PM PDT 24
Peak memory 271272 kb
Host smart-b7eebdde-270d-4c3e-a910-99624faf69d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403814380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1403814380
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.1384016224
Short name T476
Test name
Test status
Simulation time 5692981039 ps
CPU time 23.02 seconds
Started May 09 12:49:59 PM PDT 24
Finished May 09 12:50:24 PM PDT 24
Peak memory 378080 kb
Host smart-44a211c5-a7e9-4e68-a938-2bce2a799765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384016224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.1384016224
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.2664303721
Short name T428
Test name
Test status
Simulation time 10128652742 ps
CPU time 124.8 seconds
Started May 09 12:50:01 PM PDT 24
Finished May 09 12:52:07 PM PDT 24
Peak memory 631952 kb
Host smart-0553a5a2-8ea4-4523-be21-60f3e2978a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664303721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.2664303721
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.3733169569
Short name T945
Test name
Test status
Simulation time 364642261 ps
CPU time 0.88 seconds
Started May 09 12:50:01 PM PDT 24
Finished May 09 12:50:04 PM PDT 24
Peak memory 204208 kb
Host smart-c5e2437d-9172-47d4-9d2c-0d383994decc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733169569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.3733169569
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.2458317163
Short name T148
Test name
Test status
Simulation time 439753118 ps
CPU time 3.31 seconds
Started May 09 12:50:01 PM PDT 24
Finished May 09 12:50:06 PM PDT 24
Peak memory 220472 kb
Host smart-d21c5e42-6747-4733-aff2-c19c9065f311
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458317163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.2458317163
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.3811683091
Short name T102
Test name
Test status
Simulation time 3997956226 ps
CPU time 91.55 seconds
Started May 09 12:50:00 PM PDT 24
Finished May 09 12:51:33 PM PDT 24
Peak memory 1146880 kb
Host smart-65bb1e45-d2d8-4191-bcb1-cc4bd2fb90d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811683091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3811683091
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.4276455546
Short name T620
Test name
Test status
Simulation time 306404677 ps
CPU time 4.87 seconds
Started May 09 12:50:09 PM PDT 24
Finished May 09 12:50:16 PM PDT 24
Peak memory 204488 kb
Host smart-d4ea9604-ac63-4e1a-aef7-bd90ace6ef6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276455546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.4276455546
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.3315056303
Short name T664
Test name
Test status
Simulation time 3279818671 ps
CPU time 25.46 seconds
Started May 09 12:50:08 PM PDT 24
Finished May 09 12:50:36 PM PDT 24
Peak memory 312088 kb
Host smart-b46c1967-2922-4e00-9a54-a32871d3e228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315056303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.3315056303
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.2308918695
Short name T1310
Test name
Test status
Simulation time 93915982 ps
CPU time 0.7 seconds
Started May 09 12:50:03 PM PDT 24
Finished May 09 12:50:06 PM PDT 24
Peak memory 204152 kb
Host smart-6b8decb4-2b0c-4b4a-88cd-dbad25ba4e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308918695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.2308918695
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.4090048622
Short name T912
Test name
Test status
Simulation time 12793886981 ps
CPU time 25.27 seconds
Started May 09 12:50:10 PM PDT 24
Finished May 09 12:50:38 PM PDT 24
Peak memory 220544 kb
Host smart-c58327a3-9010-4d4e-8cdf-e8f735e8857f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090048622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.4090048622
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.3911332157
Short name T712
Test name
Test status
Simulation time 7264636857 ps
CPU time 96.54 seconds
Started May 09 12:50:04 PM PDT 24
Finished May 09 12:51:42 PM PDT 24
Peak memory 373424 kb
Host smart-9ac9bb94-707b-4bec-90ee-95b48d67f5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911332157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.3911332157
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.456906964
Short name T666
Test name
Test status
Simulation time 41865155566 ps
CPU time 1207.83 seconds
Started May 09 12:49:58 PM PDT 24
Finished May 09 01:10:08 PM PDT 24
Peak memory 2040164 kb
Host smart-07b480a0-fa56-424d-a2b9-4be0642d97d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456906964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.456906964
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.647781786
Short name T1273
Test name
Test status
Simulation time 408724365 ps
CPU time 19.35 seconds
Started May 09 12:50:01 PM PDT 24
Finished May 09 12:50:22 PM PDT 24
Peak memory 212620 kb
Host smart-71bc243b-8629-4441-a74f-b18c0cffb1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647781786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.647781786
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.924554202
Short name T1110
Test name
Test status
Simulation time 589241662 ps
CPU time 3.34 seconds
Started May 09 12:50:08 PM PDT 24
Finished May 09 12:50:14 PM PDT 24
Peak memory 204292 kb
Host smart-4e873bda-8e72-4889-abbf-68625049e6b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924554202 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.924554202
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.1832346249
Short name T1106
Test name
Test status
Simulation time 10107109130 ps
CPU time 15.33 seconds
Started May 09 12:50:07 PM PDT 24
Finished May 09 12:50:24 PM PDT 24
Peak memory 263592 kb
Host smart-85d78832-7f59-4cf0-8ec7-96d99b7e1ba4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832346249 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.1832346249
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.1872834761
Short name T921
Test name
Test status
Simulation time 10061901919 ps
CPU time 31.2 seconds
Started May 09 12:50:07 PM PDT 24
Finished May 09 12:50:40 PM PDT 24
Peak memory 335780 kb
Host smart-f300e3c0-a67e-44c7-9e7f-238363d26afe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872834761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.1872834761
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.471124190
Short name T1319
Test name
Test status
Simulation time 450154501 ps
CPU time 2.4 seconds
Started May 09 12:50:11 PM PDT 24
Finished May 09 12:50:16 PM PDT 24
Peak memory 204328 kb
Host smart-26c83d10-8c83-4223-9d41-b9e2c3d5809c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471124190 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.i2c_target_hrst.471124190
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.472066072
Short name T1232
Test name
Test status
Simulation time 2521902932 ps
CPU time 5.41 seconds
Started May 09 12:50:00 PM PDT 24
Finished May 09 12:50:07 PM PDT 24
Peak memory 212632 kb
Host smart-93d87d86-4a5b-4a69-91ba-a09f3157798f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472066072 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_intr_smoke.472066072
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.968587157
Short name T510
Test name
Test status
Simulation time 4349227442 ps
CPU time 3.61 seconds
Started May 09 12:49:59 PM PDT 24
Finished May 09 12:50:05 PM PDT 24
Peak memory 204396 kb
Host smart-1b8bf548-93b8-4bf6-911c-d35aa5306a6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968587157 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.968587157
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.2559918355
Short name T283
Test name
Test status
Simulation time 4335073985 ps
CPU time 45.35 seconds
Started May 09 12:50:02 PM PDT 24
Finished May 09 12:50:50 PM PDT 24
Peak memory 204520 kb
Host smart-fc0bfdfe-3e72-407b-b7ea-39d1b023e6d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559918355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.2559918355
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.3271927054
Short name T112
Test name
Test status
Simulation time 5543965370 ps
CPU time 22.45 seconds
Started May 09 12:50:07 PM PDT 24
Finished May 09 12:50:32 PM PDT 24
Peak memory 222684 kb
Host smart-d3dfaefb-bb98-4c22-9c1a-cc1d5fa858ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271927054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.3271927054
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.3515068159
Short name T769
Test name
Test status
Simulation time 12252768084 ps
CPU time 25.01 seconds
Started May 09 12:50:07 PM PDT 24
Finished May 09 12:50:34 PM PDT 24
Peak memory 204456 kb
Host smart-18074e2b-fb5c-43a7-9021-84822b5b1d0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515068159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.3515068159
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.3031294163
Short name T1292
Test name
Test status
Simulation time 5985521828 ps
CPU time 24.84 seconds
Started May 09 12:50:01 PM PDT 24
Finished May 09 12:50:28 PM PDT 24
Peak memory 430880 kb
Host smart-ea51823b-8b37-4a2e-ac5f-ffb46c39df7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031294163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.3031294163
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.652043150
Short name T32
Test name
Test status
Simulation time 2631375264 ps
CPU time 7.49 seconds
Started May 09 12:50:08 PM PDT 24
Finished May 09 12:50:18 PM PDT 24
Peak memory 217232 kb
Host smart-478dafba-dd9b-438d-bd12-1c78f8bdcec6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652043150 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_timeout.652043150
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.2434409853
Short name T1007
Test name
Test status
Simulation time 15900770 ps
CPU time 0.63 seconds
Started May 09 12:50:15 PM PDT 24
Finished May 09 12:50:17 PM PDT 24
Peak memory 204232 kb
Host smart-5696ee57-a06a-4f59-a93a-631791c8e02e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434409853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2434409853
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.4280790731
Short name T703
Test name
Test status
Simulation time 50446646 ps
CPU time 1.18 seconds
Started May 09 12:50:08 PM PDT 24
Finished May 09 12:50:12 PM PDT 24
Peak memory 212616 kb
Host smart-713a0fc7-5156-4050-a98b-29e79fca6a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280790731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.4280790731
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.4049073701
Short name T897
Test name
Test status
Simulation time 508799335 ps
CPU time 9.99 seconds
Started May 09 12:50:07 PM PDT 24
Finished May 09 12:50:19 PM PDT 24
Peak memory 317940 kb
Host smart-4f3b9b8c-3888-4070-aa27-6f900a2069f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049073701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.4049073701
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.2731725920
Short name T868
Test name
Test status
Simulation time 2117241347 ps
CPU time 74.54 seconds
Started May 09 12:50:10 PM PDT 24
Finished May 09 12:51:26 PM PDT 24
Peak memory 678956 kb
Host smart-55d1a5a0-0411-42a3-b2bf-dbebd35256af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731725920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.2731725920
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.545975169
Short name T443
Test name
Test status
Simulation time 2146332242 ps
CPU time 64.56 seconds
Started May 09 12:50:11 PM PDT 24
Finished May 09 12:51:18 PM PDT 24
Peak memory 627028 kb
Host smart-84757d58-2736-41b9-a183-a7a43dc76134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545975169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.545975169
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.1345625419
Short name T680
Test name
Test status
Simulation time 129745978 ps
CPU time 1.1 seconds
Started May 09 12:50:11 PM PDT 24
Finished May 09 12:50:14 PM PDT 24
Peak memory 204240 kb
Host smart-581ba77a-5a02-49a2-8bbf-4f39562d2c11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345625419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.1345625419
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.2704833616
Short name T310
Test name
Test status
Simulation time 2680859573 ps
CPU time 8.84 seconds
Started May 09 12:50:09 PM PDT 24
Finished May 09 12:50:20 PM PDT 24
Peak memory 234900 kb
Host smart-492ad63f-b3e7-4e25-a885-03a8da5a54a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704833616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.2704833616
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.924612106
Short name T1058
Test name
Test status
Simulation time 3424294350 ps
CPU time 252.9 seconds
Started May 09 12:50:10 PM PDT 24
Finished May 09 12:54:26 PM PDT 24
Peak memory 1044788 kb
Host smart-5053f0cf-0051-4a6a-baab-9e3bf74dd181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924612106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.924612106
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.2809504843
Short name T399
Test name
Test status
Simulation time 645295455 ps
CPU time 13.29 seconds
Started May 09 12:50:18 PM PDT 24
Finished May 09 12:50:33 PM PDT 24
Peak memory 204364 kb
Host smart-3e8975a0-88cd-4071-9445-ba3e8a209aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809504843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2809504843
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.778415467
Short name T463
Test name
Test status
Simulation time 2017558172 ps
CPU time 43.11 seconds
Started May 09 12:50:08 PM PDT 24
Finished May 09 12:50:54 PM PDT 24
Peak memory 265176 kb
Host smart-4ac94636-8f2b-4ebf-8c56-dbc383f6960c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778415467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.778415467
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.2311351501
Short name T125
Test name
Test status
Simulation time 18937224 ps
CPU time 0.66 seconds
Started May 09 12:50:07 PM PDT 24
Finished May 09 12:50:09 PM PDT 24
Peak memory 204044 kb
Host smart-6c5febd1-e22c-4815-9935-4d7fd31d8440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311351501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2311351501
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3978451072
Short name T511
Test name
Test status
Simulation time 12619537228 ps
CPU time 236.5 seconds
Started May 09 12:50:07 PM PDT 24
Finished May 09 12:54:05 PM PDT 24
Peak memory 936200 kb
Host smart-61c4d48f-f618-4e13-9762-6bbf42e42fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978451072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3978451072
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.1796057903
Short name T257
Test name
Test status
Simulation time 1712601358 ps
CPU time 34.37 seconds
Started May 09 12:50:05 PM PDT 24
Finished May 09 12:50:42 PM PDT 24
Peak memory 326248 kb
Host smart-844057fe-ab01-4581-a831-c6ee89ab5cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796057903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.1796057903
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.2445892305
Short name T1188
Test name
Test status
Simulation time 8711955269 ps
CPU time 395.49 seconds
Started May 09 12:50:08 PM PDT 24
Finished May 09 12:56:46 PM PDT 24
Peak memory 1349324 kb
Host smart-1f4a2d6f-4f2c-438d-9df6-0587af39afdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445892305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.2445892305
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.1865066986
Short name T714
Test name
Test status
Simulation time 724767654 ps
CPU time 9.06 seconds
Started May 09 12:50:08 PM PDT 24
Finished May 09 12:50:19 PM PDT 24
Peak memory 214988 kb
Host smart-c02a125b-3c1c-4ef8-9a39-fbd8c7b39087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865066986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1865066986
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.3922584605
Short name T867
Test name
Test status
Simulation time 1065554684 ps
CPU time 4.53 seconds
Started May 09 12:50:05 PM PDT 24
Finished May 09 12:50:12 PM PDT 24
Peak memory 212664 kb
Host smart-66c10819-baed-4f8e-9016-4fa2e8bfb63e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922584605 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.3922584605
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.4191800347
Short name T491
Test name
Test status
Simulation time 10246382035 ps
CPU time 3.4 seconds
Started May 09 12:50:10 PM PDT 24
Finished May 09 12:50:16 PM PDT 24
Peak memory 220852 kb
Host smart-326cbd1b-e590-43d8-94f3-6bec346805a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191800347 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.4191800347
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.42090210
Short name T779
Test name
Test status
Simulation time 10047857098 ps
CPU time 77.53 seconds
Started May 09 12:50:10 PM PDT 24
Finished May 09 12:51:30 PM PDT 24
Peak memory 488028 kb
Host smart-461efb3a-9568-4b85-9b7f-af00de3e93a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42090210 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.i2c_target_fifo_reset_tx.42090210
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.3297712996
Short name T30
Test name
Test status
Simulation time 529960466 ps
CPU time 2.84 seconds
Started May 09 12:50:10 PM PDT 24
Finished May 09 12:50:16 PM PDT 24
Peak memory 204336 kb
Host smart-056dc57e-91a8-4634-af4b-319de1a9f1fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297712996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.3297712996
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.2201722384
Short name T852
Test name
Test status
Simulation time 10625815108 ps
CPU time 5.67 seconds
Started May 09 12:50:06 PM PDT 24
Finished May 09 12:50:14 PM PDT 24
Peak memory 214208 kb
Host smart-028c5fc7-25c6-4e85-8223-df56962f4200
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201722384 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.2201722384
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.721432937
Short name T104
Test name
Test status
Simulation time 11430296964 ps
CPU time 170.7 seconds
Started May 09 12:50:11 PM PDT 24
Finished May 09 12:53:04 PM PDT 24
Peak memory 2822832 kb
Host smart-cde4f293-05b1-424e-bc63-d952d3cd6be9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721432937 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.721432937
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.3297517807
Short name T518
Test name
Test status
Simulation time 3270527125 ps
CPU time 12.25 seconds
Started May 09 12:50:09 PM PDT 24
Finished May 09 12:50:24 PM PDT 24
Peak memory 204508 kb
Host smart-73b0e9ff-31ef-4b1e-a9e7-ebd04fa3720f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297517807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.3297517807
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.3343947025
Short name T166
Test name
Test status
Simulation time 731940463 ps
CPU time 30.7 seconds
Started May 09 12:50:08 PM PDT 24
Finished May 09 12:50:41 PM PDT 24
Peak memory 204352 kb
Host smart-33ed168e-0960-41cc-b2bb-78fa6b234397
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343947025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.3343947025
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.2233130493
Short name T1229
Test name
Test status
Simulation time 52888974201 ps
CPU time 459.35 seconds
Started May 09 12:50:07 PM PDT 24
Finished May 09 12:57:49 PM PDT 24
Peak memory 4119988 kb
Host smart-470d112b-414a-4f8d-ae06-595be50c2593
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233130493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.2233130493
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.1387765998
Short name T517
Test name
Test status
Simulation time 15947747092 ps
CPU time 326.92 seconds
Started May 09 12:50:08 PM PDT 24
Finished May 09 12:55:38 PM PDT 24
Peak memory 1180360 kb
Host smart-d26e8631-f88c-4fd0-aab2-0aa4f7dc165d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387765998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.1387765998
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.387079339
Short name T1087
Test name
Test status
Simulation time 4444807872 ps
CPU time 6.49 seconds
Started May 09 12:50:10 PM PDT 24
Finished May 09 12:50:19 PM PDT 24
Peak memory 204264 kb
Host smart-66d30294-0a4b-46a9-9e9a-e54435c878ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387079339 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_timeout.387079339
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.3769734081
Short name T1039
Test name
Test status
Simulation time 15395623 ps
CPU time 0.61 seconds
Started May 09 12:50:19 PM PDT 24
Finished May 09 12:50:22 PM PDT 24
Peak memory 204192 kb
Host smart-12404178-64a9-461b-b9cb-0fb7be718371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769734081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.3769734081
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.2008683702
Short name T681
Test name
Test status
Simulation time 130973099 ps
CPU time 1.6 seconds
Started May 09 12:50:15 PM PDT 24
Finished May 09 12:50:18 PM PDT 24
Peak memory 220824 kb
Host smart-a808e483-3802-4cf3-800c-902049cc3862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008683702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.2008683702
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.2297117823
Short name T592
Test name
Test status
Simulation time 1110269608 ps
CPU time 14.26 seconds
Started May 09 12:50:17 PM PDT 24
Finished May 09 12:50:33 PM PDT 24
Peak memory 242328 kb
Host smart-5f336ebe-1bdb-4d74-85d6-a79578320e1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297117823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.2297117823
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.1454730447
Short name T53
Test name
Test status
Simulation time 5750130788 ps
CPU time 94.19 seconds
Started May 09 12:50:16 PM PDT 24
Finished May 09 12:51:53 PM PDT 24
Peak memory 850900 kb
Host smart-f8873a24-89b7-4ecb-9a04-6d6fa3ddef97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454730447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.1454730447
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.1388570254
Short name T888
Test name
Test status
Simulation time 2238018356 ps
CPU time 35.28 seconds
Started May 09 12:50:17 PM PDT 24
Finished May 09 12:50:54 PM PDT 24
Peak memory 477120 kb
Host smart-951fa161-bdf2-4554-a7cb-2dc41f033604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388570254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1388570254
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.1683338742
Short name T78
Test name
Test status
Simulation time 969834746 ps
CPU time 0.85 seconds
Started May 09 12:50:16 PM PDT 24
Finished May 09 12:50:19 PM PDT 24
Peak memory 204192 kb
Host smart-e2ef0c74-75e6-4fd8-b5f6-d9d92208ae74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683338742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.1683338742
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.2400374214
Short name T1192
Test name
Test status
Simulation time 151889375 ps
CPU time 3.4 seconds
Started May 09 12:50:17 PM PDT 24
Finished May 09 12:50:23 PM PDT 24
Peak memory 204408 kb
Host smart-9651bdbc-7600-412a-a45d-d2f84864c896
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400374214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.2400374214
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2167746282
Short name T1198
Test name
Test status
Simulation time 3925545566 ps
CPU time 268.83 seconds
Started May 09 12:50:15 PM PDT 24
Finished May 09 12:54:45 PM PDT 24
Peak memory 1115092 kb
Host smart-f4528763-2235-498d-9a56-7201ee29d1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167746282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2167746282
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.3236187654
Short name T673
Test name
Test status
Simulation time 877279275 ps
CPU time 2.93 seconds
Started May 09 12:50:20 PM PDT 24
Finished May 09 12:50:25 PM PDT 24
Peak memory 204420 kb
Host smart-b5492a8f-5f51-4c2a-be57-2637fadbb012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236187654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.3236187654
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.3565812047
Short name T230
Test name
Test status
Simulation time 2530609082 ps
CPU time 42.27 seconds
Started May 09 12:50:19 PM PDT 24
Finished May 09 12:51:04 PM PDT 24
Peak memory 284480 kb
Host smart-2e57020e-37ba-41ae-8ba7-304c4e1bd8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565812047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.3565812047
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.123273063
Short name T1021
Test name
Test status
Simulation time 20468621 ps
CPU time 0.65 seconds
Started May 09 12:50:16 PM PDT 24
Finished May 09 12:50:18 PM PDT 24
Peak memory 204104 kb
Host smart-7c1f9aec-b46d-45db-90ae-314e577f46e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123273063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.123273063
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.2259201371
Short name T1097
Test name
Test status
Simulation time 12193138527 ps
CPU time 356.2 seconds
Started May 09 12:50:22 PM PDT 24
Finished May 09 12:56:20 PM PDT 24
Peak memory 1619164 kb
Host smart-b5c03930-0906-4b02-8d9d-dd5d99db944a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259201371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.2259201371
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.1990013410
Short name T1281
Test name
Test status
Simulation time 5826442089 ps
CPU time 66.25 seconds
Started May 09 12:50:15 PM PDT 24
Finished May 09 12:51:23 PM PDT 24
Peak memory 333548 kb
Host smart-44c24468-e2b9-4218-b75f-bf918d671671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990013410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.1990013410
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.3160988775
Short name T1291
Test name
Test status
Simulation time 5816885711 ps
CPU time 25.2 seconds
Started May 09 12:50:16 PM PDT 24
Finished May 09 12:50:43 PM PDT 24
Peak memory 212688 kb
Host smart-a666eb1e-a8ab-4359-b32f-f97ebd8ea4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160988775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.3160988775
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.2192658696
Short name T856
Test name
Test status
Simulation time 845774326 ps
CPU time 4.67 seconds
Started May 09 12:50:16 PM PDT 24
Finished May 09 12:50:23 PM PDT 24
Peak memory 212656 kb
Host smart-a3a077f3-502b-4889-8ddb-4953b3edf0bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192658696 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.2192658696
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.3178715224
Short name T211
Test name
Test status
Simulation time 10037530762 ps
CPU time 71.46 seconds
Started May 09 12:50:20 PM PDT 24
Finished May 09 12:51:34 PM PDT 24
Peak memory 399636 kb
Host smart-7e40cece-c962-479f-b884-3ef4dd9e27ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178715224 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.3178715224
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.1922857124
Short name T913
Test name
Test status
Simulation time 10453213360 ps
CPU time 12.22 seconds
Started May 09 12:50:18 PM PDT 24
Finished May 09 12:50:32 PM PDT 24
Peak memory 264572 kb
Host smart-ab2023e3-0da2-4623-890c-519927d198be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922857124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.1922857124
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.439577682
Short name T258
Test name
Test status
Simulation time 586650342 ps
CPU time 3.23 seconds
Started May 09 12:50:16 PM PDT 24
Finished May 09 12:50:20 PM PDT 24
Peak memory 204320 kb
Host smart-fefb986e-e4a1-4953-a953-fddd04a8ab5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439577682 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.i2c_target_hrst.439577682
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.3569352955
Short name T470
Test name
Test status
Simulation time 1092003649 ps
CPU time 6.15 seconds
Started May 09 12:50:18 PM PDT 24
Finished May 09 12:50:26 PM PDT 24
Peak memory 204408 kb
Host smart-63735a08-7298-4e8a-ae8d-d8e8e3b61326
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569352955 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.3569352955
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.2859799166
Short name T413
Test name
Test status
Simulation time 17831174709 ps
CPU time 382.86 seconds
Started May 09 12:50:19 PM PDT 24
Finished May 09 12:56:45 PM PDT 24
Peak memory 4363464 kb
Host smart-8da6b60e-f10c-4014-a5fe-007b8c118b40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859799166 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.2859799166
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3445647676
Short name T433
Test name
Test status
Simulation time 4716460986 ps
CPU time 15.74 seconds
Started May 09 12:50:18 PM PDT 24
Finished May 09 12:50:36 PM PDT 24
Peak memory 204492 kb
Host smart-653d5cf6-5602-4ab1-a955-55c828d32875
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445647676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3445647676
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.3784003446
Short name T523
Test name
Test status
Simulation time 953135167 ps
CPU time 16.84 seconds
Started May 09 12:50:16 PM PDT 24
Finished May 09 12:50:34 PM PDT 24
Peak memory 212760 kb
Host smart-c8c0c3c9-a508-46eb-af73-debc8e383b5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784003446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.3784003446
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.1727275604
Short name T598
Test name
Test status
Simulation time 23832000874 ps
CPU time 6.87 seconds
Started May 09 12:50:18 PM PDT 24
Finished May 09 12:50:27 PM PDT 24
Peak memory 204400 kb
Host smart-5bf0a69c-6785-480d-8d0a-c273a61d2d12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727275604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.1727275604
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1001594314
Short name T321
Test name
Test status
Simulation time 20464885800 ps
CPU time 327.56 seconds
Started May 09 12:50:18 PM PDT 24
Finished May 09 12:55:48 PM PDT 24
Peak memory 1129680 kb
Host smart-84911af3-7759-42b5-8b27-387fa1ead913
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001594314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1001594314
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.2853780305
Short name T318
Test name
Test status
Simulation time 1311754387 ps
CPU time 6.84 seconds
Started May 09 12:50:19 PM PDT 24
Finished May 09 12:50:28 PM PDT 24
Peak memory 212664 kb
Host smart-b87ebaa8-64e5-4f9f-821e-4026da773139
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853780305 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.2853780305
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.4013675846
Short name T675
Test name
Test status
Simulation time 17894470 ps
CPU time 0.62 seconds
Started May 09 12:50:26 PM PDT 24
Finished May 09 12:50:28 PM PDT 24
Peak memory 204148 kb
Host smart-9500d1a3-ed28-413f-81e0-4249f4504f9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013675846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.4013675846
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.1960822990
Short name T1060
Test name
Test status
Simulation time 121323390 ps
CPU time 1.42 seconds
Started May 09 12:50:28 PM PDT 24
Finished May 09 12:50:33 PM PDT 24
Peak memory 220872 kb
Host smart-771dceaa-ac52-4870-b303-0af573f1da04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960822990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.1960822990
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.2465320806
Short name T1117
Test name
Test status
Simulation time 663541447 ps
CPU time 8.74 seconds
Started May 09 12:50:28 PM PDT 24
Finished May 09 12:50:40 PM PDT 24
Peak memory 231752 kb
Host smart-c5fab448-2ee9-45ff-8dbe-22bae90eb13f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465320806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.2465320806
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.336410989
Short name T942
Test name
Test status
Simulation time 2310782827 ps
CPU time 74.97 seconds
Started May 09 12:50:29 PM PDT 24
Finished May 09 12:51:47 PM PDT 24
Peak memory 730784 kb
Host smart-3825ad5b-f98e-4916-a80d-16c14e2123c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336410989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.336410989
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.3538424654
Short name T884
Test name
Test status
Simulation time 4892455341 ps
CPU time 86.46 seconds
Started May 09 12:50:31 PM PDT 24
Finished May 09 12:52:00 PM PDT 24
Peak memory 510152 kb
Host smart-93e9e53e-5cc6-4e3c-b314-739793bfcc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538424654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.3538424654
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.1635549566
Short name T983
Test name
Test status
Simulation time 98181763 ps
CPU time 0.99 seconds
Started May 09 12:50:31 PM PDT 24
Finished May 09 12:50:35 PM PDT 24
Peak memory 204448 kb
Host smart-90adfcda-a534-4378-aac5-c73775cbbbf3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635549566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.1635549566
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.1875226613
Short name T1286
Test name
Test status
Simulation time 1095226011 ps
CPU time 7 seconds
Started May 09 12:50:27 PM PDT 24
Finished May 09 12:50:37 PM PDT 24
Peak memory 204424 kb
Host smart-0ae7c1ed-9bc9-4ec4-82ff-13d0d1571329
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875226613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.1875226613
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.63112099
Short name T1167
Test name
Test status
Simulation time 6544613422 ps
CPU time 70.4 seconds
Started May 09 12:50:22 PM PDT 24
Finished May 09 12:51:34 PM PDT 24
Peak memory 969884 kb
Host smart-d6800508-ede4-4cb5-b3a6-407dfc7ebbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63112099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.63112099
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.2034172608
Short name T1329
Test name
Test status
Simulation time 1939663032 ps
CPU time 5.72 seconds
Started May 09 12:50:29 PM PDT 24
Finished May 09 12:50:37 PM PDT 24
Peak memory 204476 kb
Host smart-2af63bcf-5d86-4e15-96d6-b160d0f78810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034172608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2034172608
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.3183198865
Short name T886
Test name
Test status
Simulation time 3867182238 ps
CPU time 36 seconds
Started May 09 12:50:26 PM PDT 24
Finished May 09 12:51:03 PM PDT 24
Peak memory 404532 kb
Host smart-77a05273-7460-4c15-8b5d-baf6f1de184d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183198865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.3183198865
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.2543578186
Short name T1333
Test name
Test status
Simulation time 27734727 ps
CPU time 0.66 seconds
Started May 09 12:50:17 PM PDT 24
Finished May 09 12:50:19 PM PDT 24
Peak memory 204132 kb
Host smart-706a6009-766e-4bcd-98e5-cac1bf98c94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543578186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.2543578186
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.1287887745
Short name T1181
Test name
Test status
Simulation time 51653504133 ps
CPU time 445.73 seconds
Started May 09 12:50:27 PM PDT 24
Finished May 09 12:57:57 PM PDT 24
Peak memory 1579436 kb
Host smart-4d3ad9a6-66ad-439a-a33e-e3fb77972b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287887745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.1287887745
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.4175712277
Short name T325
Test name
Test status
Simulation time 3805627571 ps
CPU time 42 seconds
Started May 09 12:50:17 PM PDT 24
Finished May 09 12:51:01 PM PDT 24
Peak memory 332172 kb
Host smart-0699340e-ea3d-4447-a98e-34c8edffdaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175712277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.4175712277
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.4012797988
Short name T971
Test name
Test status
Simulation time 2354620269 ps
CPU time 26.6 seconds
Started May 09 12:50:29 PM PDT 24
Finished May 09 12:50:59 PM PDT 24
Peak memory 212672 kb
Host smart-80243c20-06e5-4766-ac23-5e55715573a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012797988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.4012797988
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3265914803
Short name T1288
Test name
Test status
Simulation time 11582887567 ps
CPU time 3.42 seconds
Started May 09 12:50:27 PM PDT 24
Finished May 09 12:50:34 PM PDT 24
Peak memory 212676 kb
Host smart-8e686a71-a0c0-407b-9e74-26f64567c418
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265914803 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3265914803
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.214283631
Short name T1042
Test name
Test status
Simulation time 10104001742 ps
CPU time 31.88 seconds
Started May 09 12:50:27 PM PDT 24
Finished May 09 12:51:01 PM PDT 24
Peak memory 306448 kb
Host smart-327e4ff9-04cc-4501-b139-c175f2eda481
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214283631 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_acq.214283631
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.2252210767
Short name T805
Test name
Test status
Simulation time 10313186001 ps
CPU time 7.68 seconds
Started May 09 12:50:27 PM PDT 24
Finished May 09 12:50:37 PM PDT 24
Peak memory 263440 kb
Host smart-47cab53b-6bb4-470f-bab5-57a382d2f081
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252210767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.2252210767
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.3845609314
Short name T12
Test name
Test status
Simulation time 1829757783 ps
CPU time 2.5 seconds
Started May 09 12:50:32 PM PDT 24
Finished May 09 12:50:37 PM PDT 24
Peak memory 204504 kb
Host smart-65a7ef45-f66f-45b0-bc88-2621c43df47a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845609314 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.3845609314
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.3430395953
Short name T1082
Test name
Test status
Simulation time 2395588203 ps
CPU time 3.58 seconds
Started May 09 12:50:27 PM PDT 24
Finished May 09 12:50:33 PM PDT 24
Peak memory 204492 kb
Host smart-1e42eb53-6a6b-45af-aa7e-8a9e201a06eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430395953 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.3430395953
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.3758124744
Short name T808
Test name
Test status
Simulation time 23483644606 ps
CPU time 59.12 seconds
Started May 09 12:50:27 PM PDT 24
Finished May 09 12:51:29 PM PDT 24
Peak memory 1253208 kb
Host smart-4461ce64-53b1-4fd7-b084-cf4ebd43722d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758124744 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.3758124744
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.3692916097
Short name T306
Test name
Test status
Simulation time 14602312630 ps
CPU time 33.39 seconds
Started May 09 12:50:27 PM PDT 24
Finished May 09 12:51:03 PM PDT 24
Peak memory 204448 kb
Host smart-ab499434-aaad-42a5-8b50-10cd99f2f84d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692916097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.3692916097
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.1859763852
Short name T621
Test name
Test status
Simulation time 518472398 ps
CPU time 9.55 seconds
Started May 09 12:50:28 PM PDT 24
Finished May 09 12:50:40 PM PDT 24
Peak memory 205572 kb
Host smart-0f93e176-e45b-41f1-a806-83b2860861b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859763852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.1859763852
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.2797275610
Short name T1220
Test name
Test status
Simulation time 36602014215 ps
CPU time 157.88 seconds
Started May 09 12:50:30 PM PDT 24
Finished May 09 12:53:11 PM PDT 24
Peak memory 2159916 kb
Host smart-6469f507-0b8d-49f2-a859-128b9f215010
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797275610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.2797275610
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.3053721428
Short name T535
Test name
Test status
Simulation time 4075842493 ps
CPU time 6.83 seconds
Started May 09 12:50:29 PM PDT 24
Finished May 09 12:50:39 PM PDT 24
Peak memory 220844 kb
Host smart-9e9c72c2-6ab9-4a55-9392-f4c8bd32f973
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053721428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.3053721428
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.1006854196
Short name T648
Test name
Test status
Simulation time 22518782 ps
CPU time 0.63 seconds
Started May 09 12:50:37 PM PDT 24
Finished May 09 12:50:39 PM PDT 24
Peak memory 204212 kb
Host smart-d0096cd4-1838-4137-adb2-c8ee95aae6c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006854196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.1006854196
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3315212139
Short name T1256
Test name
Test status
Simulation time 104296763 ps
CPU time 1.36 seconds
Started May 09 12:50:29 PM PDT 24
Finished May 09 12:50:33 PM PDT 24
Peak memory 212748 kb
Host smart-cca906ae-b8a6-43f0-80c0-c7da6b0e734d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315212139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3315212139
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.392292232
Short name T1093
Test name
Test status
Simulation time 1629551982 ps
CPU time 22.97 seconds
Started May 09 12:50:29 PM PDT 24
Finished May 09 12:50:55 PM PDT 24
Peak memory 297424 kb
Host smart-f16b15c3-8417-4757-9901-f5b189751deb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392292232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empt
y.392292232
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.3688785344
Short name T461
Test name
Test status
Simulation time 2150345473 ps
CPU time 147.67 seconds
Started May 09 12:50:27 PM PDT 24
Finished May 09 12:52:58 PM PDT 24
Peak memory 700400 kb
Host smart-6ca1cca7-4297-4d0b-8caf-bea7c3cf0744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688785344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.3688785344
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.2229467658
Short name T303
Test name
Test status
Simulation time 5755718907 ps
CPU time 69.06 seconds
Started May 09 12:50:27 PM PDT 24
Finished May 09 12:51:39 PM PDT 24
Peak memory 678544 kb
Host smart-58896c6e-44f4-4c42-903b-d2aee7b17609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229467658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2229467658
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3312851602
Short name T387
Test name
Test status
Simulation time 542504884 ps
CPU time 0.86 seconds
Started May 09 12:50:29 PM PDT 24
Finished May 09 12:50:34 PM PDT 24
Peak memory 204216 kb
Host smart-de34220d-c863-4b45-9da9-28f9749d3d90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312851602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3312851602
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.1635488291
Short name T317
Test name
Test status
Simulation time 386033671 ps
CPU time 6.39 seconds
Started May 09 12:50:28 PM PDT 24
Finished May 09 12:50:37 PM PDT 24
Peak memory 222112 kb
Host smart-054a9ca6-8eb9-4ac8-87ee-9cf0fa868d91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635488291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.1635488291
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2246343803
Short name T437
Test name
Test status
Simulation time 8376481586 ps
CPU time 312.55 seconds
Started May 09 12:50:26 PM PDT 24
Finished May 09 12:55:41 PM PDT 24
Peak memory 1203848 kb
Host smart-06337235-4b79-42da-87d4-83f2998d5537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246343803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2246343803
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.30426124
Short name T346
Test name
Test status
Simulation time 368611650 ps
CPU time 4.36 seconds
Started May 09 12:50:40 PM PDT 24
Finished May 09 12:50:46 PM PDT 24
Peak memory 204452 kb
Host smart-e666676a-bb83-4d61-866c-e0349c7c1803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30426124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.30426124
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.977027532
Short name T1193
Test name
Test status
Simulation time 7844606532 ps
CPU time 86.75 seconds
Started May 09 12:50:36 PM PDT 24
Finished May 09 12:52:05 PM PDT 24
Peak memory 298320 kb
Host smart-413548cd-cd0d-4568-a9be-e0b1e99a946e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977027532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.977027532
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.1103550615
Short name T741
Test name
Test status
Simulation time 42882942 ps
CPU time 0.65 seconds
Started May 09 12:50:28 PM PDT 24
Finished May 09 12:50:31 PM PDT 24
Peak memory 204120 kb
Host smart-ddf3ea42-aa6f-45a9-9af0-0da48a33604f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103550615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1103550615
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.2795253182
Short name T83
Test name
Test status
Simulation time 77402506521 ps
CPU time 78.76 seconds
Started May 09 12:50:30 PM PDT 24
Finished May 09 12:51:52 PM PDT 24
Peak memory 218100 kb
Host smart-2c3aa465-0cdc-4b7f-bcba-0d5f42738544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795253182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.2795253182
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.928141950
Short name T512
Test name
Test status
Simulation time 6056811999 ps
CPU time 22.77 seconds
Started May 09 12:50:29 PM PDT 24
Finished May 09 12:50:55 PM PDT 24
Peak memory 294244 kb
Host smart-735b9d70-a964-4f9f-aca8-47e62b83a877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928141950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.928141950
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.2996119135
Short name T409
Test name
Test status
Simulation time 18026287915 ps
CPU time 2682.02 seconds
Started May 09 12:50:28 PM PDT 24
Finished May 09 01:35:14 PM PDT 24
Peak memory 3696112 kb
Host smart-b24ddcaa-bdcf-4177-9a97-2f1104d00d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996119135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.2996119135
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.3227277636
Short name T597
Test name
Test status
Simulation time 3065565518 ps
CPU time 25.65 seconds
Started May 09 12:50:29 PM PDT 24
Finished May 09 12:50:57 PM PDT 24
Peak memory 212716 kb
Host smart-887665aa-5ce4-475c-ba31-fe972e3ea635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227277636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3227277636
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.2294975353
Short name T1153
Test name
Test status
Simulation time 555509407 ps
CPU time 2.26 seconds
Started May 09 12:50:35 PM PDT 24
Finished May 09 12:50:39 PM PDT 24
Peak memory 204420 kb
Host smart-7fc07d96-a10d-4592-8866-ab00b5e8acc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294975353 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.2294975353
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.3735865588
Short name T68
Test name
Test status
Simulation time 10068316113 ps
CPU time 24.85 seconds
Started May 09 12:50:41 PM PDT 24
Finished May 09 12:51:07 PM PDT 24
Peak memory 296296 kb
Host smart-e86a1cac-faa0-40a9-8053-c5bd88e45768
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735865588 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.3735865588
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.3882891550
Short name T502
Test name
Test status
Simulation time 10038355131 ps
CPU time 73.34 seconds
Started May 09 12:50:47 PM PDT 24
Finished May 09 12:52:02 PM PDT 24
Peak memory 445752 kb
Host smart-f8468588-eca0-43d6-96b0-d095b9575aea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882891550 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.3882891550
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.1799133099
Short name T1293
Test name
Test status
Simulation time 1611959799 ps
CPU time 2.22 seconds
Started May 09 12:50:46 PM PDT 24
Finished May 09 12:50:49 PM PDT 24
Peak memory 204488 kb
Host smart-ed9dc399-9845-4b16-b953-ddec959124d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799133099 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.1799133099
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.4211907935
Short name T1155
Test name
Test status
Simulation time 3947642899 ps
CPU time 4.56 seconds
Started May 09 12:50:42 PM PDT 24
Finished May 09 12:50:48 PM PDT 24
Peak memory 207968 kb
Host smart-967f2c6e-178d-4567-8f3a-1212ae1016d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211907935 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.4211907935
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.1109511303
Short name T555
Test name
Test status
Simulation time 4100588815 ps
CPU time 13.62 seconds
Started May 09 12:50:41 PM PDT 24
Finished May 09 12:50:56 PM PDT 24
Peak memory 635796 kb
Host smart-23761b94-a1d9-4bf1-83fa-56acbc7a768b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109511303 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.1109511303
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.3472332851
Short name T645
Test name
Test status
Simulation time 991837050 ps
CPU time 8.79 seconds
Started May 09 12:50:30 PM PDT 24
Finished May 09 12:50:42 PM PDT 24
Peak memory 204396 kb
Host smart-c77615ef-cd6f-4322-a8a3-1e6af99126ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472332851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.3472332851
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_all.1631477956
Short name T1246
Test name
Test status
Simulation time 31947846721 ps
CPU time 59.23 seconds
Started May 09 12:50:39 PM PDT 24
Finished May 09 12:51:40 PM PDT 24
Peak memory 452408 kb
Host smart-6c1daf34-624a-4666-9bc4-6a711289ae64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631477956 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.i2c_target_stress_all.1631477956
Directory /workspace/34.i2c_target_stress_all/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.1049481257
Short name T737
Test name
Test status
Simulation time 6357406199 ps
CPU time 42.44 seconds
Started May 09 12:50:39 PM PDT 24
Finished May 09 12:51:23 PM PDT 24
Peak memory 205432 kb
Host smart-682413a6-b031-4208-8f83-2744d8ea544f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049481257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.1049481257
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.3172045998
Short name T1211
Test name
Test status
Simulation time 30232249946 ps
CPU time 216.96 seconds
Started May 09 12:50:37 PM PDT 24
Finished May 09 12:54:16 PM PDT 24
Peak memory 2706016 kb
Host smart-8079f11f-c777-4eb5-8062-6efb04111546
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172045998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.3172045998
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.3672863435
Short name T1325
Test name
Test status
Simulation time 36685873619 ps
CPU time 2039.08 seconds
Started May 09 12:50:37 PM PDT 24
Finished May 09 01:24:39 PM PDT 24
Peak memory 4085060 kb
Host smart-45ca99ad-8511-46f4-9db7-efe0af35e999
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672863435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.3672863435
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.2324847546
Short name T500
Test name
Test status
Simulation time 5306643057 ps
CPU time 7.04 seconds
Started May 09 12:50:42 PM PDT 24
Finished May 09 12:50:50 PM PDT 24
Peak memory 214996 kb
Host smart-e7338cc6-10fc-4ff2-89bc-dd67cf1efe20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324847546 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.2324847546
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2399401403
Short name T765
Test name
Test status
Simulation time 40463036 ps
CPU time 0.6 seconds
Started May 09 12:50:51 PM PDT 24
Finished May 09 12:50:52 PM PDT 24
Peak memory 204200 kb
Host smart-6bf3192e-eba2-4665-b6b9-c452c4557f82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399401403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2399401403
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.1651994569
Short name T824
Test name
Test status
Simulation time 295771644 ps
CPU time 1.66 seconds
Started May 09 12:50:40 PM PDT 24
Finished May 09 12:50:44 PM PDT 24
Peak memory 212780 kb
Host smart-e3cb06fa-221d-4017-ad3c-45aa73489fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651994569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.1651994569
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.2648023949
Short name T1074
Test name
Test status
Simulation time 1150752059 ps
CPU time 14.67 seconds
Started May 09 12:50:40 PM PDT 24
Finished May 09 12:50:57 PM PDT 24
Peak memory 261948 kb
Host smart-ea720c1a-2872-486e-993e-6365791f7ce3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648023949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.2648023949
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.471037220
Short name T1084
Test name
Test status
Simulation time 1516042456 ps
CPU time 99.47 seconds
Started May 09 12:50:37 PM PDT 24
Finished May 09 12:52:18 PM PDT 24
Peak memory 569780 kb
Host smart-6cd0a6ae-b7b0-4dbf-8e67-73ddc73ea69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471037220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.471037220
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.1647176049
Short name T1026
Test name
Test status
Simulation time 1413905522 ps
CPU time 42.25 seconds
Started May 09 12:50:37 PM PDT 24
Finished May 09 12:51:21 PM PDT 24
Peak memory 519928 kb
Host smart-49a78b5b-5562-4dcd-95d0-5f85b66e579d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647176049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.1647176049
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.3164216175
Short name T718
Test name
Test status
Simulation time 444302518 ps
CPU time 0.87 seconds
Started May 09 12:50:41 PM PDT 24
Finished May 09 12:50:44 PM PDT 24
Peak memory 204140 kb
Host smart-3524736d-4b4b-4037-bf29-f0105409e010
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164216175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.3164216175
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.2214037349
Short name T327
Test name
Test status
Simulation time 202965207 ps
CPU time 2.93 seconds
Started May 09 12:50:37 PM PDT 24
Finished May 09 12:50:42 PM PDT 24
Peak memory 220664 kb
Host smart-80375ca6-abc5-464f-a984-a6d8c2bfde95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214037349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.2214037349
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.1020548069
Short name T389
Test name
Test status
Simulation time 7141384656 ps
CPU time 107.47 seconds
Started May 09 12:50:42 PM PDT 24
Finished May 09 12:52:31 PM PDT 24
Peak memory 1094272 kb
Host smart-2b10ab84-d5f7-4c76-87a6-5dd298cee982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020548069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1020548069
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.207993326
Short name T450
Test name
Test status
Simulation time 181417909 ps
CPU time 3.01 seconds
Started May 09 12:50:52 PM PDT 24
Finished May 09 12:50:56 PM PDT 24
Peak memory 204508 kb
Host smart-b492f4dd-90cc-479b-ac7c-4eeb934176cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207993326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.207993326
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.3941305949
Short name T431
Test name
Test status
Simulation time 2878983431 ps
CPU time 64.99 seconds
Started May 09 12:50:48 PM PDT 24
Finished May 09 12:51:55 PM PDT 24
Peak memory 301988 kb
Host smart-0cee5fa0-cc3d-4df3-9d92-dec6a0495bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941305949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.3941305949
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.4158518036
Short name T412
Test name
Test status
Simulation time 90464401 ps
CPU time 0.67 seconds
Started May 09 12:50:37 PM PDT 24
Finished May 09 12:50:39 PM PDT 24
Peak memory 204008 kb
Host smart-b6937bec-4aa4-491e-bfbb-cf6ca0235d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158518036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.4158518036
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.3232588912
Short name T630
Test name
Test status
Simulation time 6810609310 ps
CPU time 76.92 seconds
Started May 09 12:50:37 PM PDT 24
Finished May 09 12:51:56 PM PDT 24
Peak memory 246172 kb
Host smart-84ea4796-b582-4f20-8f8e-3fba634270a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232588912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.3232588912
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.3146338876
Short name T47
Test name
Test status
Simulation time 7151261826 ps
CPU time 27.82 seconds
Started May 09 12:50:47 PM PDT 24
Finished May 09 12:51:17 PM PDT 24
Peak memory 355936 kb
Host smart-4ed0ee54-abb8-4dff-ac2d-3773295d73b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146338876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.3146338876
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.2012236874
Short name T107
Test name
Test status
Simulation time 7609009017 ps
CPU time 15.66 seconds
Started May 09 12:50:37 PM PDT 24
Finished May 09 12:50:54 PM PDT 24
Peak memory 229348 kb
Host smart-14233ba6-13d8-4c67-bc5c-7239aa3efd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012236874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.2012236874
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.644552841
Short name T1035
Test name
Test status
Simulation time 767081599 ps
CPU time 8.27 seconds
Started May 09 12:50:37 PM PDT 24
Finished May 09 12:50:47 PM PDT 24
Peak memory 214776 kb
Host smart-c1c79d08-d84e-4b44-a0a3-e9e6fbf0b492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644552841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.644552841
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.2179979373
Short name T743
Test name
Test status
Simulation time 668034541 ps
CPU time 3.48 seconds
Started May 09 12:50:50 PM PDT 24
Finished May 09 12:50:55 PM PDT 24
Peak memory 204492 kb
Host smart-af8c57df-9694-4f93-af29-df25e9651ae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179979373 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.2179979373
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.4137122692
Short name T482
Test name
Test status
Simulation time 10471300110 ps
CPU time 13.84 seconds
Started May 09 12:50:41 PM PDT 24
Finished May 09 12:50:56 PM PDT 24
Peak memory 270108 kb
Host smart-5980aaca-eed3-49e8-9aa3-07395f65daf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137122692 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.4137122692
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.2539707197
Short name T1061
Test name
Test status
Simulation time 10126076656 ps
CPU time 79.13 seconds
Started May 09 12:50:47 PM PDT 24
Finished May 09 12:52:09 PM PDT 24
Peak memory 447096 kb
Host smart-1df4632a-ec03-46b8-b0b8-e82c08e0766b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539707197 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.2539707197
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.2693811875
Short name T540
Test name
Test status
Simulation time 316659174 ps
CPU time 2.03 seconds
Started May 09 12:50:46 PM PDT 24
Finished May 09 12:50:50 PM PDT 24
Peak memory 204428 kb
Host smart-dcec3108-1200-4295-b0cc-e9a9ca5c3b10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693811875 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.2693811875
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.4004985391
Short name T441
Test name
Test status
Simulation time 2151593963 ps
CPU time 5.66 seconds
Started May 09 12:50:40 PM PDT 24
Finished May 09 12:50:48 PM PDT 24
Peak memory 207128 kb
Host smart-4dfd14d7-8b8e-452f-b669-8c0a285d2ca8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004985391 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.4004985391
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.3501170825
Short name T1217
Test name
Test status
Simulation time 3656491220 ps
CPU time 33.17 seconds
Started May 09 12:50:37 PM PDT 24
Finished May 09 12:51:12 PM PDT 24
Peak memory 1041932 kb
Host smart-9d35d43d-eb37-4de6-9612-655cf8b13880
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501170825 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.3501170825
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.1083805709
Short name T366
Test name
Test status
Simulation time 3780637903 ps
CPU time 15.97 seconds
Started May 09 12:50:37 PM PDT 24
Finished May 09 12:50:55 PM PDT 24
Peak memory 204512 kb
Host smart-eda94cf8-2384-46b0-81c7-69822bf8442e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083805709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.1083805709
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.2971433935
Short name T364
Test name
Test status
Simulation time 3648558092 ps
CPU time 32.17 seconds
Started May 09 12:50:39 PM PDT 24
Finished May 09 12:51:14 PM PDT 24
Peak memory 204456 kb
Host smart-db215091-14b7-4d7a-8214-4ebf4901eccb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971433935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.2971433935
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.1167628070
Short name T342
Test name
Test status
Simulation time 64037717407 ps
CPU time 272.32 seconds
Started May 09 12:50:35 PM PDT 24
Finished May 09 12:55:09 PM PDT 24
Peak memory 2751044 kb
Host smart-a83a432a-905f-4ce5-979c-10d999df07f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167628070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.1167628070
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.2611598805
Short name T1083
Test name
Test status
Simulation time 1516267266 ps
CPU time 6.88 seconds
Started May 09 12:50:35 PM PDT 24
Finished May 09 12:50:44 PM PDT 24
Peak memory 212620 kb
Host smart-8cf3b373-dbcb-449d-9e87-0efbd0fd7855
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611598805 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.2611598805
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.3115532420
Short name T1191
Test name
Test status
Simulation time 14717164 ps
CPU time 0.63 seconds
Started May 09 12:51:02 PM PDT 24
Finished May 09 12:51:06 PM PDT 24
Peak memory 204220 kb
Host smart-8d3c96b6-ebb7-4aaa-8bf8-bb8e7c910bc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115532420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.3115532420
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.3719008442
Short name T548
Test name
Test status
Simulation time 146770506 ps
CPU time 1.2 seconds
Started May 09 12:50:46 PM PDT 24
Finished May 09 12:50:48 PM PDT 24
Peak memory 204476 kb
Host smart-44e76663-90ee-4db0-b529-baee502275f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719008442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.3719008442
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.1461796962
Short name T545
Test name
Test status
Simulation time 818681912 ps
CPU time 4.6 seconds
Started May 09 12:50:52 PM PDT 24
Finished May 09 12:50:58 PM PDT 24
Peak memory 244456 kb
Host smart-243f26aa-f261-4a94-841c-085ce8ee7b7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461796962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.1461796962
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.1852001812
Short name T391
Test name
Test status
Simulation time 7425712115 ps
CPU time 53.89 seconds
Started May 09 12:50:46 PM PDT 24
Finished May 09 12:51:42 PM PDT 24
Peak memory 570108 kb
Host smart-e1852da4-8114-44ae-b178-dd95f142e488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852001812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.1852001812
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.297673310
Short name T1240
Test name
Test status
Simulation time 5604550888 ps
CPU time 38.7 seconds
Started May 09 12:50:48 PM PDT 24
Finished May 09 12:51:29 PM PDT 24
Peak memory 459000 kb
Host smart-4b6194a2-d07b-418b-b544-c58c5a899ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297673310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.297673310
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3620303710
Short name T383
Test name
Test status
Simulation time 487390509 ps
CPU time 0.98 seconds
Started May 09 12:50:46 PM PDT 24
Finished May 09 12:50:48 PM PDT 24
Peak memory 204160 kb
Host smart-2ae84e47-21f8-4bdc-96cc-f9e5e6291dbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620303710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3620303710
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.529740741
Short name T469
Test name
Test status
Simulation time 630013089 ps
CPU time 4.8 seconds
Started May 09 12:50:48 PM PDT 24
Finished May 09 12:50:55 PM PDT 24
Peak memory 234740 kb
Host smart-a3db983e-633d-45c2-8089-95d6c5c67d20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529740741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.
529740741
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.2063665613
Short name T147
Test name
Test status
Simulation time 3456438924 ps
CPU time 77.03 seconds
Started May 09 12:50:48 PM PDT 24
Finished May 09 12:52:07 PM PDT 24
Peak memory 997144 kb
Host smart-b9dc3be4-1ee2-483e-8cd6-093d33962225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063665613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.2063665613
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.38195183
Short name T1285
Test name
Test status
Simulation time 425888312 ps
CPU time 3.13 seconds
Started May 09 12:50:52 PM PDT 24
Finished May 09 12:50:56 PM PDT 24
Peak memory 204396 kb
Host smart-ea6ca719-3f5d-4938-b84e-5e7eebe6ce16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38195183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.38195183
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.1840068392
Short name T678
Test name
Test status
Simulation time 1285779022 ps
CPU time 62.6 seconds
Started May 09 12:50:48 PM PDT 24
Finished May 09 12:51:53 PM PDT 24
Peak memory 351044 kb
Host smart-b6ec612f-8e4c-4426-bbf4-736c06ca3e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840068392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.1840068392
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.850601393
Short name T322
Test name
Test status
Simulation time 16726494 ps
CPU time 0.66 seconds
Started May 09 12:50:48 PM PDT 24
Finished May 09 12:50:51 PM PDT 24
Peak memory 204116 kb
Host smart-a8ad84dd-adfd-4aed-a370-54b4ef06429c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850601393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.850601393
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.403461259
Short name T1164
Test name
Test status
Simulation time 13479941255 ps
CPU time 38.15 seconds
Started May 09 12:50:48 PM PDT 24
Finished May 09 12:51:28 PM PDT 24
Peak memory 212696 kb
Host smart-88a23843-b001-415e-bcb3-c42e3ffb1457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403461259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.403461259
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.262502903
Short name T754
Test name
Test status
Simulation time 1239621947 ps
CPU time 18.36 seconds
Started May 09 12:50:46 PM PDT 24
Finished May 09 12:51:06 PM PDT 24
Peak memory 284812 kb
Host smart-17b6389e-c3f0-4bc6-ac2d-a9d73bb06183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262502903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.262502903
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.3132501107
Short name T975
Test name
Test status
Simulation time 20470891030 ps
CPU time 1906.22 seconds
Started May 09 12:50:52 PM PDT 24
Finished May 09 01:22:40 PM PDT 24
Peak memory 1767468 kb
Host smart-45bd3ff7-997b-4990-8f28-018fe0d27fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132501107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.3132501107
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.3795171396
Short name T226
Test name
Test status
Simulation time 1568521634 ps
CPU time 14.54 seconds
Started May 09 12:50:48 PM PDT 24
Finished May 09 12:51:05 PM PDT 24
Peak memory 218856 kb
Host smart-f50f94fc-38ef-4d99-a8de-569422115106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795171396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.3795171396
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.640307573
Short name T618
Test name
Test status
Simulation time 2971165099 ps
CPU time 4.1 seconds
Started May 09 12:50:51 PM PDT 24
Finished May 09 12:50:56 PM PDT 24
Peak memory 220736 kb
Host smart-1d93ca4e-6156-4e4f-8d0b-1fd049395dd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640307573 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.640307573
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.657732397
Short name T1238
Test name
Test status
Simulation time 10029479091 ps
CPU time 84.63 seconds
Started May 09 12:50:48 PM PDT 24
Finished May 09 12:52:15 PM PDT 24
Peak memory 440196 kb
Host smart-675a0a8c-3896-477e-a4d9-ffc85a0cae1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657732397 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_acq.657732397
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.91329313
Short name T594
Test name
Test status
Simulation time 10081700421 ps
CPU time 29.5 seconds
Started May 09 12:50:49 PM PDT 24
Finished May 09 12:51:21 PM PDT 24
Peak memory 362904 kb
Host smart-2a6eb0f0-7e63-4cd2-b48b-0499005d5bed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91329313 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.i2c_target_fifo_reset_tx.91329313
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.2759295037
Short name T560
Test name
Test status
Simulation time 1459519063 ps
CPU time 2.68 seconds
Started May 09 12:50:47 PM PDT 24
Finished May 09 12:50:52 PM PDT 24
Peak memory 204660 kb
Host smart-1d1a3040-0549-44f6-a1d5-8aaa17a37577
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759295037 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.2759295037
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2084052410
Short name T1028
Test name
Test status
Simulation time 10449890823 ps
CPU time 5.58 seconds
Started May 09 12:50:46 PM PDT 24
Finished May 09 12:50:53 PM PDT 24
Peak memory 209920 kb
Host smart-854aa2c3-ad83-476e-8691-04dfa1cc33dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084052410 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2084052410
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.1320634043
Short name T456
Test name
Test status
Simulation time 21321600757 ps
CPU time 153.48 seconds
Started May 09 12:50:48 PM PDT 24
Finished May 09 12:53:24 PM PDT 24
Peak memory 1800484 kb
Host smart-9e9c2858-42a8-42e6-a68a-ceaef137d5f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320634043 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.1320634043
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.3881104991
Short name T1068
Test name
Test status
Simulation time 4632086546 ps
CPU time 15.48 seconds
Started May 09 12:50:48 PM PDT 24
Finished May 09 12:51:06 PM PDT 24
Peak memory 204372 kb
Host smart-87180c5c-e90a-4007-9c61-fea341e41424
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881104991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.3881104991
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.3623582967
Short name T546
Test name
Test status
Simulation time 1440074944 ps
CPU time 65.76 seconds
Started May 09 12:50:47 PM PDT 24
Finished May 09 12:51:55 PM PDT 24
Peak memory 206632 kb
Host smart-3a6c166b-b05d-4d7e-a0ff-e7ae4ceda152
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623582967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_rd.3623582967
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.1898577611
Short name T1202
Test name
Test status
Simulation time 47569997055 ps
CPU time 1214.89 seconds
Started May 09 12:50:46 PM PDT 24
Finished May 09 01:11:03 PM PDT 24
Peak memory 6908196 kb
Host smart-626ac59f-c225-4bc3-baec-f2ca332729bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898577611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.1898577611
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.510988718
Short name T938
Test name
Test status
Simulation time 6521633135 ps
CPU time 65.49 seconds
Started May 09 12:50:48 PM PDT 24
Finished May 09 12:51:56 PM PDT 24
Peak memory 880452 kb
Host smart-3d459f0f-ad4e-4f63-ad6e-f96da43f8dfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510988718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_t
arget_stretch.510988718
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.4114191874
Short name T395
Test name
Test status
Simulation time 10877825996 ps
CPU time 6.65 seconds
Started May 09 12:50:48 PM PDT 24
Finished May 09 12:50:57 PM PDT 24
Peak memory 212744 kb
Host smart-1206c47d-5670-49df-a849-a50ee5189af8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114191874 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.4114191874
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.3693927555
Short name T1104
Test name
Test status
Simulation time 33069629 ps
CPU time 0.59 seconds
Started May 09 12:51:00 PM PDT 24
Finished May 09 12:51:03 PM PDT 24
Peak memory 204092 kb
Host smart-de1be0ab-b30c-418a-b6a2-6a25075d8607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693927555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.3693927555
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.4089552468
Short name T771
Test name
Test status
Simulation time 468950383 ps
CPU time 1.59 seconds
Started May 09 12:51:03 PM PDT 24
Finished May 09 12:51:07 PM PDT 24
Peak memory 212712 kb
Host smart-6b7635f0-6361-4aef-bc62-e7055c512647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089552468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.4089552468
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3218212713
Short name T464
Test name
Test status
Simulation time 887371224 ps
CPU time 11.34 seconds
Started May 09 12:51:00 PM PDT 24
Finished May 09 12:51:13 PM PDT 24
Peak memory 245920 kb
Host smart-6bedfa46-708b-45f4-882e-5ecda1a1f3e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218212713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3218212713
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.4071368189
Short name T1305
Test name
Test status
Simulation time 8132884417 ps
CPU time 68.69 seconds
Started May 09 12:51:04 PM PDT 24
Finished May 09 12:52:15 PM PDT 24
Peak memory 624704 kb
Host smart-00846533-a978-46aa-8b20-2ca2a4ea745a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071368189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.4071368189
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.3002303104
Short name T1017
Test name
Test status
Simulation time 2834364324 ps
CPU time 43.89 seconds
Started May 09 12:50:58 PM PDT 24
Finished May 09 12:51:44 PM PDT 24
Peak memory 550504 kb
Host smart-fe176249-3b5c-4017-8a0c-f323fe27f71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002303104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.3002303104
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.3379315161
Short name T969
Test name
Test status
Simulation time 90888753 ps
CPU time 0.89 seconds
Started May 09 12:51:02 PM PDT 24
Finished May 09 12:51:05 PM PDT 24
Peak memory 204192 kb
Host smart-b04525f2-8eec-4f15-bf20-a5024ef37aeb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379315161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.3379315161
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.2856837381
Short name T752
Test name
Test status
Simulation time 224684509 ps
CPU time 2.58 seconds
Started May 09 12:51:01 PM PDT 24
Finished May 09 12:51:06 PM PDT 24
Peak memory 204364 kb
Host smart-3b378418-9849-4473-a739-4f07d5ed708f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856837381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.2856837381
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.4294905733
Short name T1316
Test name
Test status
Simulation time 7469687526 ps
CPU time 93.33 seconds
Started May 09 12:51:01 PM PDT 24
Finished May 09 12:52:37 PM PDT 24
Peak memory 1001928 kb
Host smart-58743f26-7ac2-442b-b272-b030ee607ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294905733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.4294905733
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.3743287026
Short name T585
Test name
Test status
Simulation time 257446786 ps
CPU time 3.34 seconds
Started May 09 12:51:00 PM PDT 24
Finished May 09 12:51:05 PM PDT 24
Peak memory 204504 kb
Host smart-8d30c561-7f61-473b-9845-c1e06d917c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743287026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.3743287026
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.481460992
Short name T40
Test name
Test status
Simulation time 5339435949 ps
CPU time 38.45 seconds
Started May 09 12:51:00 PM PDT 24
Finished May 09 12:51:41 PM PDT 24
Peak memory 457620 kb
Host smart-d7da7ea1-ff2a-4a1c-ad7c-b3c7606e6753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481460992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.481460992
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.2078752818
Short name T539
Test name
Test status
Simulation time 43980916 ps
CPU time 0.73 seconds
Started May 09 12:51:00 PM PDT 24
Finished May 09 12:51:03 PM PDT 24
Peak memory 204136 kb
Host smart-27256a6e-3b75-4bd7-a774-028169ca30c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078752818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.2078752818
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.3975079592
Short name T1124
Test name
Test status
Simulation time 27349671082 ps
CPU time 374.79 seconds
Started May 09 12:51:03 PM PDT 24
Finished May 09 12:57:21 PM PDT 24
Peak memory 254584 kb
Host smart-7ea11f2f-c29d-48c1-90be-f772b0718021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975079592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3975079592
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.3302536674
Short name T333
Test name
Test status
Simulation time 4839672627 ps
CPU time 54.25 seconds
Started May 09 12:51:01 PM PDT 24
Finished May 09 12:51:58 PM PDT 24
Peak memory 285140 kb
Host smart-6ab80a97-969c-4d0e-91d3-1c310ad4ac9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302536674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3302536674
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.3274889199
Short name T225
Test name
Test status
Simulation time 141643087732 ps
CPU time 937.7 seconds
Started May 09 12:51:00 PM PDT 24
Finished May 09 01:06:40 PM PDT 24
Peak memory 3058444 kb
Host smart-e2691918-3af9-4060-ad26-db926b57476a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274889199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.3274889199
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.585813866
Short name T916
Test name
Test status
Simulation time 2037790783 ps
CPU time 32.44 seconds
Started May 09 12:51:00 PM PDT 24
Finished May 09 12:51:34 PM PDT 24
Peak memory 212844 kb
Host smart-3b3782ad-3ab4-4e49-9bd7-47c2c13f10b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585813866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.585813866
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.1986261658
Short name T599
Test name
Test status
Simulation time 3045541489 ps
CPU time 4.02 seconds
Started May 09 12:51:02 PM PDT 24
Finished May 09 12:51:08 PM PDT 24
Peak memory 204508 kb
Host smart-481eaad8-e07d-4a74-8769-fbae0720f5cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986261658 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.1986261658
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.4101713018
Short name T118
Test name
Test status
Simulation time 10225593529 ps
CPU time 6.34 seconds
Started May 09 12:50:59 PM PDT 24
Finished May 09 12:51:07 PM PDT 24
Peak memory 225168 kb
Host smart-0bbbbec5-8ffa-40e6-ad55-cc7a17d8a0f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101713018 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.4101713018
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.2608416541
Short name T1103
Test name
Test status
Simulation time 10046814262 ps
CPU time 69.36 seconds
Started May 09 12:51:02 PM PDT 24
Finished May 09 12:52:14 PM PDT 24
Peak memory 542148 kb
Host smart-4f32bd58-e5e8-4f5f-81e6-d0054a994085
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608416541 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.2608416541
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.3250780968
Short name T128
Test name
Test status
Simulation time 2933531420 ps
CPU time 2.91 seconds
Started May 09 12:50:59 PM PDT 24
Finished May 09 12:51:03 PM PDT 24
Peak memory 204440 kb
Host smart-f5e38274-359b-4601-a3f9-7f7244f91172
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250780968 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.3250780968
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.4032452503
Short name T315
Test name
Test status
Simulation time 971002152 ps
CPU time 5.25 seconds
Started May 09 12:51:04 PM PDT 24
Finished May 09 12:51:12 PM PDT 24
Peak memory 204864 kb
Host smart-4c6c53e4-b61e-40a1-921a-99d7522682f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032452503 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.4032452503
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.3906238558
Short name T1308
Test name
Test status
Simulation time 8470832204 ps
CPU time 17.94 seconds
Started May 09 12:51:03 PM PDT 24
Finished May 09 12:51:23 PM PDT 24
Peak memory 607632 kb
Host smart-72e1420a-0089-446d-a9d0-c1c698065f5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906238558 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.3906238558
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.3606346153
Short name T1186
Test name
Test status
Simulation time 13667544807 ps
CPU time 14.8 seconds
Started May 09 12:50:59 PM PDT 24
Finished May 09 12:51:16 PM PDT 24
Peak memory 204484 kb
Host smart-8f964777-4ac1-4eea-8c94-846dcb6f6d6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606346153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.3606346153
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.2802723766
Short name T262
Test name
Test status
Simulation time 2639136630 ps
CPU time 25.08 seconds
Started May 09 12:51:01 PM PDT 24
Finished May 09 12:51:28 PM PDT 24
Peak memory 204548 kb
Host smart-9c7684ea-c9c9-463c-a98d-93222e0d69c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802723766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.2802723766
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.1277011991
Short name T679
Test name
Test status
Simulation time 28824633916 ps
CPU time 183.81 seconds
Started May 09 12:50:59 PM PDT 24
Finished May 09 12:54:04 PM PDT 24
Peak memory 2396776 kb
Host smart-a085a815-5a0a-45e0-9b05-9e246459384f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277011991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.1277011991
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.1104805292
Short name T1245
Test name
Test status
Simulation time 29805097069 ps
CPU time 151.81 seconds
Started May 09 12:51:05 PM PDT 24
Finished May 09 12:53:39 PM PDT 24
Peak memory 1399812 kb
Host smart-fd916e45-67c8-472b-9fc4-fb6beeb3a846
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104805292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.1104805292
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.1637501526
Short name T1290
Test name
Test status
Simulation time 2284819577 ps
CPU time 6.71 seconds
Started May 09 12:50:58 PM PDT 24
Finished May 09 12:51:06 PM PDT 24
Peak memory 212664 kb
Host smart-aeac208b-a9bf-4ddd-a7ef-8cbaa6c99982
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637501526 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.1637501526
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.1421619062
Short name T489
Test name
Test status
Simulation time 43470083 ps
CPU time 0.62 seconds
Started May 09 12:51:13 PM PDT 24
Finished May 09 12:51:14 PM PDT 24
Peak memory 204216 kb
Host smart-65dc7f44-cb7c-41b4-a47b-5ffa2074920e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421619062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1421619062
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.434393303
Short name T381
Test name
Test status
Simulation time 114779267 ps
CPU time 1.31 seconds
Started May 09 12:51:04 PM PDT 24
Finished May 09 12:51:08 PM PDT 24
Peak memory 212696 kb
Host smart-c843c6b0-26e2-49b5-b358-d4a2ec4b40be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434393303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.434393303
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2014632582
Short name T1300
Test name
Test status
Simulation time 350817331 ps
CPU time 18.81 seconds
Started May 09 12:51:00 PM PDT 24
Finished May 09 12:51:21 PM PDT 24
Peak memory 278168 kb
Host smart-22a1fd99-2577-470a-ac66-bd481fe6c841
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014632582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2014632582
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.2986863782
Short name T1237
Test name
Test status
Simulation time 2454383070 ps
CPU time 71.23 seconds
Started May 09 12:51:02 PM PDT 24
Finished May 09 12:52:16 PM PDT 24
Peak memory 718744 kb
Host smart-858e342e-43b4-41fa-a465-69aa8e0fdb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986863782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.2986863782
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.37227907
Short name T706
Test name
Test status
Simulation time 4422846994 ps
CPU time 32.78 seconds
Started May 09 12:50:59 PM PDT 24
Finished May 09 12:51:33 PM PDT 24
Peak memory 413352 kb
Host smart-ac8e37d4-5733-4caa-ada0-0337bc6c1466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37227907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.37227907
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.361863545
Short name T1024
Test name
Test status
Simulation time 429111774 ps
CPU time 1.04 seconds
Started May 09 12:51:02 PM PDT 24
Finished May 09 12:51:06 PM PDT 24
Peak memory 204212 kb
Host smart-b40f48d2-d1df-47dc-bfb6-0ace7fcb4d6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361863545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fm
t.361863545
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.1951978751
Short name T631
Test name
Test status
Simulation time 212455346 ps
CPU time 3.22 seconds
Started May 09 12:51:00 PM PDT 24
Finished May 09 12:51:05 PM PDT 24
Peak memory 219348 kb
Host smart-632be317-8025-4c8c-9e6f-df1fcd09543e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951978751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.1951978751
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.872405811
Short name T740
Test name
Test status
Simulation time 8111815666 ps
CPU time 176.85 seconds
Started May 09 12:51:01 PM PDT 24
Finished May 09 12:53:59 PM PDT 24
Peak memory 820388 kb
Host smart-2c5c7161-1a26-45d6-8381-acdfad2084f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872405811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.872405811
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.4272980338
Short name T486
Test name
Test status
Simulation time 376818996 ps
CPU time 6.03 seconds
Started May 09 12:51:15 PM PDT 24
Finished May 09 12:51:22 PM PDT 24
Peak memory 204484 kb
Host smart-d168c5eb-deaf-419c-8f70-cb0947101e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272980338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.4272980338
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.3108665147
Short name T757
Test name
Test status
Simulation time 1581799907 ps
CPU time 23.83 seconds
Started May 09 12:51:16 PM PDT 24
Finished May 09 12:51:42 PM PDT 24
Peak memory 288848 kb
Host smart-f529f249-2588-459a-9a2e-302975b9f579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108665147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.3108665147
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.734604222
Short name T690
Test name
Test status
Simulation time 80004430 ps
CPU time 0.68 seconds
Started May 09 12:51:02 PM PDT 24
Finished May 09 12:51:06 PM PDT 24
Peak memory 204132 kb
Host smart-0a963b7b-f470-4705-89e6-94059f8be220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734604222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.734604222
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.3955036907
Short name T270
Test name
Test status
Simulation time 419867302 ps
CPU time 2.08 seconds
Started May 09 12:51:02 PM PDT 24
Finished May 09 12:51:07 PM PDT 24
Peak memory 213512 kb
Host smart-ae9230b4-8f7f-4662-a719-88b3de4fde08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955036907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.3955036907
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.2108320152
Short name T76
Test name
Test status
Simulation time 1112701485 ps
CPU time 22.64 seconds
Started May 09 12:51:01 PM PDT 24
Finished May 09 12:51:25 PM PDT 24
Peak memory 334368 kb
Host smart-8eb7a06e-042a-472a-9641-f5c8d6b83373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108320152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.2108320152
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.4024507599
Short name T1295
Test name
Test status
Simulation time 371512900 ps
CPU time 7.62 seconds
Started May 09 12:50:59 PM PDT 24
Finished May 09 12:51:08 PM PDT 24
Peak memory 212640 kb
Host smart-1fe191fd-18d2-499d-a641-fb8025f4d94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024507599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.4024507599
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.2595966857
Short name T1276
Test name
Test status
Simulation time 1265276975 ps
CPU time 3.48 seconds
Started May 09 12:51:17 PM PDT 24
Finished May 09 12:51:23 PM PDT 24
Peak memory 204416 kb
Host smart-69ec35fa-594b-45da-a8d7-8fde4314ffec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595966857 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.2595966857
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.566370372
Short name T334
Test name
Test status
Simulation time 10521760273 ps
CPU time 7.71 seconds
Started May 09 12:51:18 PM PDT 24
Finished May 09 12:51:28 PM PDT 24
Peak memory 242680 kb
Host smart-e190575b-d76b-489b-a30c-3654a50c2410
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566370372 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_acq.566370372
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.1263353218
Short name T1340
Test name
Test status
Simulation time 10167995953 ps
CPU time 42.99 seconds
Started May 09 12:51:15 PM PDT 24
Finished May 09 12:51:59 PM PDT 24
Peak memory 371228 kb
Host smart-838f0c38-a7bf-4d33-8862-cc6867104125
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263353218 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.1263353218
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.2201361699
Short name T21
Test name
Test status
Simulation time 685079957 ps
CPU time 2.34 seconds
Started May 09 12:51:15 PM PDT 24
Finished May 09 12:51:19 PM PDT 24
Peak memory 204424 kb
Host smart-c183fc95-39b6-4c68-a754-af89bd8815de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201361699 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.2201361699
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.1702361197
Short name T1002
Test name
Test status
Simulation time 5742975638 ps
CPU time 6.41 seconds
Started May 09 12:51:14 PM PDT 24
Finished May 09 12:51:21 PM PDT 24
Peak memory 219028 kb
Host smart-2069160b-3b0e-4b34-b5a3-3d3890944f24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702361197 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.1702361197
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.365006129
Short name T877
Test name
Test status
Simulation time 9482991359 ps
CPU time 6.62 seconds
Started May 09 12:51:16 PM PDT 24
Finished May 09 12:51:25 PM PDT 24
Peak memory 204520 kb
Host smart-fec3758f-d718-4576-b716-02d52a308a27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365006129 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.365006129
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.2337581401
Short name T587
Test name
Test status
Simulation time 998014853 ps
CPU time 34.19 seconds
Started May 09 12:51:01 PM PDT 24
Finished May 09 12:51:37 PM PDT 24
Peak memory 204360 kb
Host smart-a008953a-20f8-4225-916c-503d33833a44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337581401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.2337581401
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_all.3273683087
Short name T1144
Test name
Test status
Simulation time 37959394170 ps
CPU time 79.67 seconds
Started May 09 12:51:15 PM PDT 24
Finished May 09 12:52:36 PM PDT 24
Peak memory 1475908 kb
Host smart-f68f5dbd-e8b4-4b39-9756-ac498aba0af1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273683087 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.i2c_target_stress_all.3273683087
Directory /workspace/38.i2c_target_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.3534657985
Short name T253
Test name
Test status
Simulation time 3722160175 ps
CPU time 17.18 seconds
Started May 09 12:51:18 PM PDT 24
Finished May 09 12:51:37 PM PDT 24
Peak memory 213536 kb
Host smart-057b4b5a-5e50-4621-9f93-f453ca94d8fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534657985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.3534657985
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.2046592563
Short name T789
Test name
Test status
Simulation time 62207696685 ps
CPU time 1776.32 seconds
Started May 09 12:51:14 PM PDT 24
Finished May 09 01:20:52 PM PDT 24
Peak memory 10327952 kb
Host smart-76070247-5afc-4daf-8642-26316ec9155d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046592563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.2046592563
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.2234338500
Short name T686
Test name
Test status
Simulation time 35359258186 ps
CPU time 3186.98 seconds
Started May 09 12:51:13 PM PDT 24
Finished May 09 01:44:22 PM PDT 24
Peak memory 4439552 kb
Host smart-bc6fcedf-6228-407a-9983-9b146fa8f735
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234338500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.2234338500
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.2345896815
Short name T768
Test name
Test status
Simulation time 2491923644 ps
CPU time 6.79 seconds
Started May 09 12:51:12 PM PDT 24
Finished May 09 12:51:20 PM PDT 24
Peak memory 210936 kb
Host smart-a1603fc2-7f15-403a-b94d-bfa2c5416e24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345896815 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.2345896815
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_unexp_stop.3898930017
Short name T16
Test name
Test status
Simulation time 711493324 ps
CPU time 4.31 seconds
Started May 09 12:51:18 PM PDT 24
Finished May 09 12:51:24 PM PDT 24
Peak memory 203996 kb
Host smart-245214dd-0603-4a24-85f5-2a76208ffa79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898930017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.i2c_target_unexp_stop.3898930017
Directory /workspace/38.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/39.i2c_alert_test.2790879435
Short name T396
Test name
Test status
Simulation time 25578231 ps
CPU time 0.61 seconds
Started May 09 12:51:21 PM PDT 24
Finished May 09 12:51:24 PM PDT 24
Peak memory 204228 kb
Host smart-91ecb588-851c-4c3f-b7f3-c77c004ed24c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790879435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.2790879435
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.4227838798
Short name T940
Test name
Test status
Simulation time 239182831 ps
CPU time 1.15 seconds
Started May 09 12:51:15 PM PDT 24
Finished May 09 12:51:18 PM PDT 24
Peak memory 204504 kb
Host smart-c0205f1f-ba33-4c2d-b469-83aab095f55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227838798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.4227838798
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.173720020
Short name T423
Test name
Test status
Simulation time 314551688 ps
CPU time 5.16 seconds
Started May 09 12:51:16 PM PDT 24
Finished May 09 12:51:24 PM PDT 24
Peak memory 247804 kb
Host smart-2e66510d-fd8f-4217-ac12-ddec97275df5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173720020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empt
y.173720020
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.260022156
Short name T1364
Test name
Test status
Simulation time 26839259160 ps
CPU time 73.43 seconds
Started May 09 12:51:17 PM PDT 24
Finished May 09 12:52:32 PM PDT 24
Peak memory 715048 kb
Host smart-4e7976bf-9ea8-4685-a22c-2945215dd4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260022156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.260022156
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.3526590288
Short name T669
Test name
Test status
Simulation time 3275465596 ps
CPU time 57.34 seconds
Started May 09 12:51:14 PM PDT 24
Finished May 09 12:52:13 PM PDT 24
Peak memory 596324 kb
Host smart-73f3e95a-469d-469b-aab3-c61e1af72f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526590288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.3526590288
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.1976772640
Short name T1000
Test name
Test status
Simulation time 324689778 ps
CPU time 1.01 seconds
Started May 09 12:51:15 PM PDT 24
Finished May 09 12:51:18 PM PDT 24
Peak memory 204484 kb
Host smart-ba62c703-270e-446e-8dc7-9ef1416052c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976772640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.1976772640
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.823689349
Short name T1126
Test name
Test status
Simulation time 120628991 ps
CPU time 6.35 seconds
Started May 09 12:51:15 PM PDT 24
Finished May 09 12:51:23 PM PDT 24
Peak memory 204432 kb
Host smart-16894ca1-6d87-4a96-b986-932d26a0d327
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823689349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.
823689349
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.3015250528
Short name T1279
Test name
Test status
Simulation time 5167467928 ps
CPU time 173.98 seconds
Started May 09 12:51:14 PM PDT 24
Finished May 09 12:54:09 PM PDT 24
Peak memory 795140 kb
Host smart-8e257023-41c5-4a5d-956a-e296a6ce4269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015250528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3015250528
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.2977558799
Short name T347
Test name
Test status
Simulation time 970868419 ps
CPU time 9.38 seconds
Started May 09 12:51:17 PM PDT 24
Finished May 09 12:51:28 PM PDT 24
Peak memory 204468 kb
Host smart-a6c3a3e4-eb00-4c3f-bdf3-6323c86d4e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977558799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.2977558799
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.508225425
Short name T552
Test name
Test status
Simulation time 1635186926 ps
CPU time 33.24 seconds
Started May 09 12:51:16 PM PDT 24
Finished May 09 12:51:51 PM PDT 24
Peak memory 347128 kb
Host smart-f9450b07-ca26-4004-9ee0-ffc5dd7b5158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508225425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.508225425
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.1853264507
Short name T661
Test name
Test status
Simulation time 50558658 ps
CPU time 0.67 seconds
Started May 09 12:51:14 PM PDT 24
Finished May 09 12:51:16 PM PDT 24
Peak memory 204120 kb
Host smart-259b7b7c-693e-4499-bce2-cf077f92aac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853264507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.1853264507
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.3814358933
Short name T1301
Test name
Test status
Simulation time 1068856803 ps
CPU time 18.49 seconds
Started May 09 12:51:18 PM PDT 24
Finished May 09 12:51:38 PM PDT 24
Peak memory 287396 kb
Host smart-92c25d91-4ac5-45f2-8170-983bf94bc927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814358933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.3814358933
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.2219534780
Short name T801
Test name
Test status
Simulation time 4200110808 ps
CPU time 21.29 seconds
Started May 09 12:51:19 PM PDT 24
Finished May 09 12:51:42 PM PDT 24
Peak memory 277940 kb
Host smart-6a301229-7ee7-4dc1-913f-934b9dd377de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219534780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.2219534780
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.1816196941
Short name T218
Test name
Test status
Simulation time 82186558442 ps
CPU time 1487.24 seconds
Started May 09 12:51:16 PM PDT 24
Finished May 09 01:16:05 PM PDT 24
Peak memory 3653004 kb
Host smart-f3443e3c-111f-46af-b381-f2895704439b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816196941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.1816196941
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.2705359098
Short name T132
Test name
Test status
Simulation time 341375666 ps
CPU time 5.41 seconds
Started May 09 12:51:16 PM PDT 24
Finished May 09 12:51:23 PM PDT 24
Peak memory 212620 kb
Host smart-1a9338d1-a100-4986-8eaf-0e4e6f74929f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705359098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.2705359098
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.3920976628
Short name T1330
Test name
Test status
Simulation time 5384254974 ps
CPU time 4.67 seconds
Started May 09 12:51:16 PM PDT 24
Finished May 09 12:51:23 PM PDT 24
Peak memory 204556 kb
Host smart-69ea9391-57a9-4c1c-8e23-e3cce6590ed9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920976628 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.3920976628
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2316658659
Short name T622
Test name
Test status
Simulation time 10082804507 ps
CPU time 81.8 seconds
Started May 09 12:51:15 PM PDT 24
Finished May 09 12:52:38 PM PDT 24
Peak memory 450196 kb
Host smart-5b89e0f9-ebde-499c-b9b6-a9d886eb4003
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316658659 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.2316658659
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.2450972149
Short name T65
Test name
Test status
Simulation time 10114191181 ps
CPU time 17.96 seconds
Started May 09 12:51:15 PM PDT 24
Finished May 09 12:51:34 PM PDT 24
Peak memory 296604 kb
Host smart-93111feb-5012-4792-b9ca-4821702ffda4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450972149 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.2450972149
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.1423071915
Short name T372
Test name
Test status
Simulation time 1699134716 ps
CPU time 2.7 seconds
Started May 09 12:51:14 PM PDT 24
Finished May 09 12:51:17 PM PDT 24
Peak memory 204460 kb
Host smart-075b5ca3-41bf-4f00-ba71-275ee26eea68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423071915 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.1423071915
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.2035724101
Short name T1166
Test name
Test status
Simulation time 1361405184 ps
CPU time 3.95 seconds
Started May 09 12:51:15 PM PDT 24
Finished May 09 12:51:21 PM PDT 24
Peak memory 204468 kb
Host smart-b33522c0-75ea-4265-805e-2dc064631ae9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035724101 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.2035724101
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.1266183501
Short name T33
Test name
Test status
Simulation time 11228304121 ps
CPU time 177.4 seconds
Started May 09 12:51:15 PM PDT 24
Finished May 09 12:54:14 PM PDT 24
Peak memory 2753220 kb
Host smart-cd5947bb-4c36-4a04-a047-c537e09b4d12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266183501 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.1266183501
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.3118844594
Short name T835
Test name
Test status
Simulation time 8568787302 ps
CPU time 32.76 seconds
Started May 09 12:51:17 PM PDT 24
Finished May 09 12:51:52 PM PDT 24
Peak memory 204400 kb
Host smart-e5389793-49df-4248-8ae6-f73e07c6ca5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118844594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.3118844594
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.4079034047
Short name T900
Test name
Test status
Simulation time 1013741118 ps
CPU time 10.63 seconds
Started May 09 12:51:13 PM PDT 24
Finished May 09 12:51:25 PM PDT 24
Peak memory 204292 kb
Host smart-8df17fb1-643d-46ea-a288-560c9c5a8010
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079034047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.4079034047
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.59391693
Short name T480
Test name
Test status
Simulation time 23644467714 ps
CPU time 31.4 seconds
Started May 09 12:51:12 PM PDT 24
Finished May 09 12:51:44 PM PDT 24
Peak memory 603440 kb
Host smart-6b94ed19-86d0-40af-857e-5dc77519f4b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59391693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stress_wr.59391693
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.3118508901
Short name T615
Test name
Test status
Simulation time 12257128548 ps
CPU time 44.82 seconds
Started May 09 12:51:14 PM PDT 24
Finished May 09 12:52:00 PM PDT 24
Peak memory 578048 kb
Host smart-d365f4bd-117d-4b9e-ad9d-b7dfb41741d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118508901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.3118508901
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.2112970914
Short name T999
Test name
Test status
Simulation time 4180907688 ps
CPU time 5.86 seconds
Started May 09 12:51:18 PM PDT 24
Finished May 09 12:51:26 PM PDT 24
Peak memory 212732 kb
Host smart-e6c25148-80e4-4144-b329-dc0385e5ae7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112970914 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.2112970914
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.2058684868
Short name T390
Test name
Test status
Simulation time 15253550 ps
CPU time 0.66 seconds
Started May 09 12:46:22 PM PDT 24
Finished May 09 12:46:25 PM PDT 24
Peak memory 204244 kb
Host smart-c495df27-2c69-457b-835f-931567646fd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058684868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.2058684868
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.437295172
Short name T516
Test name
Test status
Simulation time 40129561 ps
CPU time 1.07 seconds
Started May 09 12:46:19 PM PDT 24
Finished May 09 12:46:21 PM PDT 24
Peak memory 212748 kb
Host smart-11381358-281d-4583-bb5f-17d57aa6e047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437295172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.437295172
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.3035048065
Short name T606
Test name
Test status
Simulation time 698582477 ps
CPU time 17.52 seconds
Started May 09 12:46:20 PM PDT 24
Finished May 09 12:46:39 PM PDT 24
Peak memory 276388 kb
Host smart-9e011fdc-838c-4cd3-8e0c-5009fabd9cfe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035048065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.3035048065
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.3511038954
Short name T1136
Test name
Test status
Simulation time 2265599665 ps
CPU time 65.82 seconds
Started May 09 12:46:21 PM PDT 24
Finished May 09 12:47:29 PM PDT 24
Peak memory 691484 kb
Host smart-7310304f-cb41-4aca-8f73-1952d166e7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511038954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3511038954
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.1579933039
Short name T277
Test name
Test status
Simulation time 3227006539 ps
CPU time 119.48 seconds
Started May 09 12:46:22 PM PDT 24
Finished May 09 12:48:23 PM PDT 24
Peak memory 591124 kb
Host smart-cc199cbe-852c-4da4-86f8-33d1ec339120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579933039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.1579933039
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2125838062
Short name T595
Test name
Test status
Simulation time 152456357 ps
CPU time 0.88 seconds
Started May 09 12:46:20 PM PDT 24
Finished May 09 12:46:23 PM PDT 24
Peak memory 204176 kb
Host smart-6033464c-6ae4-43ea-8a8d-81cb6692195f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125838062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2125838062
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.3467487623
Short name T1208
Test name
Test status
Simulation time 785425108 ps
CPU time 5.03 seconds
Started May 09 12:46:20 PM PDT 24
Finished May 09 12:46:26 PM PDT 24
Peak memory 238072 kb
Host smart-27a96345-a896-48e3-b9a9-f33224f428ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467487623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
3467487623
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.3254051028
Short name T876
Test name
Test status
Simulation time 7280901229 ps
CPU time 257.1 seconds
Started May 09 12:46:20 PM PDT 24
Finished May 09 12:50:39 PM PDT 24
Peak memory 1072688 kb
Host smart-2d43d834-e55e-48b7-907d-3f9d6d16b90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254051028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.3254051028
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.270188209
Short name T684
Test name
Test status
Simulation time 426740029 ps
CPU time 7.11 seconds
Started May 09 12:46:21 PM PDT 24
Finished May 09 12:46:30 PM PDT 24
Peak memory 204448 kb
Host smart-694be8e0-ba52-410c-8f1b-db397500231f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270188209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.270188209
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.1553485918
Short name T444
Test name
Test status
Simulation time 2276500641 ps
CPU time 51.54 seconds
Started May 09 12:46:22 PM PDT 24
Finished May 09 12:47:16 PM PDT 24
Peak memory 260856 kb
Host smart-4fdf3318-4e54-41f5-b6f3-658288818549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553485918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.1553485918
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.130412757
Short name T483
Test name
Test status
Simulation time 29809415 ps
CPU time 0.67 seconds
Started May 09 12:46:20 PM PDT 24
Finished May 09 12:46:22 PM PDT 24
Peak memory 204144 kb
Host smart-01233cf5-091a-427b-bb07-47f835658e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130412757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.130412757
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.3833973126
Short name T210
Test name
Test status
Simulation time 26358031674 ps
CPU time 419.4 seconds
Started May 09 12:46:21 PM PDT 24
Finished May 09 12:53:22 PM PDT 24
Peak memory 1058340 kb
Host smart-a77b1efa-fb09-4d0c-84d4-dc21fc814f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833973126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3833973126
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.3635377673
Short name T420
Test name
Test status
Simulation time 987936373 ps
CPU time 15.67 seconds
Started May 09 12:46:22 PM PDT 24
Finished May 09 12:46:40 PM PDT 24
Peak memory 265800 kb
Host smart-dde02dc8-92fc-44ea-adc3-676811a50822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635377673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.3635377673
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.1877640488
Short name T1183
Test name
Test status
Simulation time 29533627380 ps
CPU time 527 seconds
Started May 09 12:46:22 PM PDT 24
Finished May 09 12:55:11 PM PDT 24
Peak memory 996612 kb
Host smart-5278eeea-5c21-49b2-bd3f-9ca49b7867a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877640488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.1877640488
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.3489837232
Short name T252
Test name
Test status
Simulation time 498619809 ps
CPU time 9.26 seconds
Started May 09 12:46:22 PM PDT 24
Finished May 09 12:46:33 PM PDT 24
Peak memory 220792 kb
Host smart-622ffd34-4bb0-4d0b-ab36-d374994906d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489837232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.3489837232
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.4019664025
Short name T159
Test name
Test status
Simulation time 115380538 ps
CPU time 0.8 seconds
Started May 09 12:46:20 PM PDT 24
Finished May 09 12:46:22 PM PDT 24
Peak memory 221424 kb
Host smart-9342c676-104f-422e-a75e-c73512f92cb1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019664025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.4019664025
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.2854658241
Short name T693
Test name
Test status
Simulation time 990352763 ps
CPU time 2.46 seconds
Started May 09 12:46:20 PM PDT 24
Finished May 09 12:46:24 PM PDT 24
Peak memory 204292 kb
Host smart-fb47c033-00e4-45ea-922c-eb2071559973
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854658241 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.2854658241
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.2753970098
Short name T56
Test name
Test status
Simulation time 10112662072 ps
CPU time 29.21 seconds
Started May 09 12:46:20 PM PDT 24
Finished May 09 12:46:51 PM PDT 24
Peak memory 335772 kb
Host smart-793e4717-6a55-48be-b949-8445571930fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753970098 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.2753970098
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.4041647612
Short name T320
Test name
Test status
Simulation time 10085910284 ps
CPU time 40.68 seconds
Started May 09 12:46:22 PM PDT 24
Finished May 09 12:47:05 PM PDT 24
Peak memory 341744 kb
Host smart-96ca8e7c-f021-45b9-9e33-6e31e78f56bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041647612 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.4041647612
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.2065285527
Short name T982
Test name
Test status
Simulation time 2578161489 ps
CPU time 2.41 seconds
Started May 09 12:46:21 PM PDT 24
Finished May 09 12:46:26 PM PDT 24
Peak memory 204544 kb
Host smart-fc5fd59a-b1c8-4925-a5e4-3158acd494f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065285527 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.2065285527
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.315443503
Short name T799
Test name
Test status
Simulation time 1673364821 ps
CPU time 4.43 seconds
Started May 09 12:46:19 PM PDT 24
Finished May 09 12:46:24 PM PDT 24
Peak memory 204344 kb
Host smart-595fd2b4-c269-4852-a014-823cb9cbd539
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315443503 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_intr_smoke.315443503
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.1922902284
Short name T895
Test name
Test status
Simulation time 37366574418 ps
CPU time 61.4 seconds
Started May 09 12:46:19 PM PDT 24
Finished May 09 12:47:22 PM PDT 24
Peak memory 1248588 kb
Host smart-873f62d8-efa2-4139-9a94-5048334dcb97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922902284 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.1922902284
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.2135014123
Short name T996
Test name
Test status
Simulation time 815063484 ps
CPU time 30.77 seconds
Started May 09 12:46:20 PM PDT 24
Finished May 09 12:46:52 PM PDT 24
Peak memory 204704 kb
Host smart-6591e8c7-5401-47d3-a909-232a00bd1bc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135014123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.2135014123
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.3210428624
Short name T1315
Test name
Test status
Simulation time 655972717 ps
CPU time 12.38 seconds
Started May 09 12:46:21 PM PDT 24
Finished May 09 12:46:35 PM PDT 24
Peak memory 206328 kb
Host smart-656f83f9-9ca9-456a-a9c2-290e9b6103eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210428624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.3210428624
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2591410455
Short name T704
Test name
Test status
Simulation time 47405647490 ps
CPU time 834.33 seconds
Started May 09 12:46:20 PM PDT 24
Finished May 09 01:00:17 PM PDT 24
Peak memory 6324836 kb
Host smart-c0fffbe6-097b-4855-a124-7d91f355fdf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591410455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2591410455
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.2829142485
Short name T1347
Test name
Test status
Simulation time 2769181807 ps
CPU time 58.17 seconds
Started May 09 12:46:22 PM PDT 24
Finished May 09 12:47:22 PM PDT 24
Peak memory 435292 kb
Host smart-3160fca2-06e0-4aa7-8b9b-fa780dcefc15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829142485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.2829142485
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.2583660309
Short name T453
Test name
Test status
Simulation time 29106625191 ps
CPU time 7.79 seconds
Started May 09 12:46:21 PM PDT 24
Finished May 09 12:46:31 PM PDT 24
Peak memory 216896 kb
Host smart-722e1f11-304b-44f9-b959-0697e2fdf5c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583660309 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.2583660309
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.151908346
Short name T1297
Test name
Test status
Simulation time 88109819 ps
CPU time 0.61 seconds
Started May 09 12:51:28 PM PDT 24
Finished May 09 12:51:31 PM PDT 24
Peak memory 204116 kb
Host smart-d0883ce5-71eb-43b2-ad39-9f3cf59d7909
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151908346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.151908346
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.2179485984
Short name T775
Test name
Test status
Simulation time 1044300945 ps
CPU time 1.3 seconds
Started May 09 12:51:22 PM PDT 24
Finished May 09 12:51:26 PM PDT 24
Peak memory 212800 kb
Host smart-478bc305-0c58-42d5-9606-cf2c1acd81c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179485984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.2179485984
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.2260763497
Short name T271
Test name
Test status
Simulation time 1467178378 ps
CPU time 8.47 seconds
Started May 09 12:51:22 PM PDT 24
Finished May 09 12:51:33 PM PDT 24
Peak memory 284704 kb
Host smart-04e8a0b7-f286-48e1-9567-71ae067c2dc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260763497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.2260763497
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.1796582015
Short name T471
Test name
Test status
Simulation time 4381208324 ps
CPU time 55 seconds
Started May 09 12:51:20 PM PDT 24
Finished May 09 12:52:17 PM PDT 24
Peak memory 642052 kb
Host smart-80b9bd45-8ffc-49d8-bd2e-a85712a2c97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796582015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.1796582015
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.1551486768
Short name T432
Test name
Test status
Simulation time 1392814226 ps
CPU time 95.37 seconds
Started May 09 12:51:21 PM PDT 24
Finished May 09 12:52:59 PM PDT 24
Peak memory 544416 kb
Host smart-a81e6aac-a7b8-41e7-9382-9f161dd2da28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551486768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1551486768
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.3314520865
Short name T708
Test name
Test status
Simulation time 416613021 ps
CPU time 0.88 seconds
Started May 09 12:51:21 PM PDT 24
Finished May 09 12:51:24 PM PDT 24
Peak memory 204176 kb
Host smart-6db230d5-3981-44ff-8e75-207f21567386
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314520865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.3314520865
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.941025573
Short name T1091
Test name
Test status
Simulation time 622065399 ps
CPU time 4.57 seconds
Started May 09 12:51:24 PM PDT 24
Finished May 09 12:51:31 PM PDT 24
Peak memory 237264 kb
Host smart-eadfcc71-1244-4fe4-b490-7300befc6dd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941025573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.
941025573
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.1462157505
Short name T848
Test name
Test status
Simulation time 16441102813 ps
CPU time 110.09 seconds
Started May 09 12:51:18 PM PDT 24
Finished May 09 12:53:10 PM PDT 24
Peak memory 1196616 kb
Host smart-1f10ee0a-78f3-46ff-b8e9-687febe90b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462157505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.1462157505
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.1249041461
Short name T1197
Test name
Test status
Simulation time 621950742 ps
CPU time 12.4 seconds
Started May 09 12:51:23 PM PDT 24
Finished May 09 12:51:38 PM PDT 24
Peak memory 204440 kb
Host smart-6848a232-f9d6-48b0-aa4a-4d9cd7a72a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249041461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.1249041461
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.1897207834
Short name T319
Test name
Test status
Simulation time 888111333 ps
CPU time 16.9 seconds
Started May 09 12:51:22 PM PDT 24
Finished May 09 12:51:42 PM PDT 24
Peak memory 275668 kb
Host smart-39ac0a66-12ac-418c-ad0b-adae68073f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897207834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.1897207834
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.2243089428
Short name T909
Test name
Test status
Simulation time 27581659 ps
CPU time 0.66 seconds
Started May 09 12:51:19 PM PDT 24
Finished May 09 12:51:21 PM PDT 24
Peak memory 204132 kb
Host smart-f696c3b5-5458-4e6f-bb0f-2e48ebcdadd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243089428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.2243089428
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.1930132210
Short name T918
Test name
Test status
Simulation time 2833366881 ps
CPU time 17.41 seconds
Started May 09 12:51:19 PM PDT 24
Finished May 09 12:51:38 PM PDT 24
Peak memory 401520 kb
Host smart-2102fc87-e4bb-447d-a54c-9843c5fa0d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930132210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.1930132210
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.1673859402
Short name T140
Test name
Test status
Simulation time 6752710509 ps
CPU time 66.89 seconds
Started May 09 12:51:21 PM PDT 24
Finished May 09 12:52:30 PM PDT 24
Peak memory 318304 kb
Host smart-f1037f67-646d-46d4-9685-efcc3e31e674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673859402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.1673859402
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.2249861557
Short name T807
Test name
Test status
Simulation time 498335451 ps
CPU time 9.76 seconds
Started May 09 12:51:20 PM PDT 24
Finished May 09 12:51:32 PM PDT 24
Peak memory 220764 kb
Host smart-b47643c8-76b1-44ba-a0d8-ffa2d37f9470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249861557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.2249861557
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.15151846
Short name T633
Test name
Test status
Simulation time 642914291 ps
CPU time 3.35 seconds
Started May 09 12:51:21 PM PDT 24
Finished May 09 12:51:27 PM PDT 24
Peak memory 204500 kb
Host smart-76c3eb26-1f70-4fa7-b046-c4e8546e26a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15151846 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_bad_addr.15151846
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.4012849424
Short name T785
Test name
Test status
Simulation time 10383580964 ps
CPU time 12.5 seconds
Started May 09 12:51:27 PM PDT 24
Finished May 09 12:51:41 PM PDT 24
Peak memory 262136 kb
Host smart-dc688fcc-a55c-4f43-8e2d-b418534884c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012849424 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.4012849424
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.3745947436
Short name T380
Test name
Test status
Simulation time 10131679246 ps
CPU time 14.63 seconds
Started May 09 12:51:22 PM PDT 24
Finished May 09 12:51:40 PM PDT 24
Peak memory 301608 kb
Host smart-72ac5d99-4d62-492f-8a3c-f59842ab6868
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745947436 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.3745947436
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.3063397962
Short name T814
Test name
Test status
Simulation time 523407381 ps
CPU time 2.27 seconds
Started May 09 12:51:27 PM PDT 24
Finished May 09 12:51:31 PM PDT 24
Peak memory 204352 kb
Host smart-5a0f5921-50ba-4de3-a717-0a69f7433489
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063397962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.3063397962
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.249467673
Short name T267
Test name
Test status
Simulation time 926449611 ps
CPU time 5.32 seconds
Started May 09 12:51:25 PM PDT 24
Finished May 09 12:51:33 PM PDT 24
Peak memory 216384 kb
Host smart-5715919c-bc8a-4d25-8c1c-ee2c6aff0907
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249467673 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_intr_smoke.249467673
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.291902469
Short name T144
Test name
Test status
Simulation time 21429844555 ps
CPU time 444.36 seconds
Started May 09 12:51:22 PM PDT 24
Finished May 09 12:58:49 PM PDT 24
Peak memory 5020184 kb
Host smart-9401df26-3333-4b1e-b7c0-9738dabf9a83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291902469 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.291902469
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stress_all.2955296891
Short name T844
Test name
Test status
Simulation time 22749783458 ps
CPU time 50.12 seconds
Started May 09 12:51:20 PM PDT 24
Finished May 09 12:52:12 PM PDT 24
Peak memory 319908 kb
Host smart-f94c6bcb-8c8e-441f-a7c5-68b8391fd896
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955296891 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_target_stress_all.2955296891
Directory /workspace/40.i2c_target_stress_all/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.1099173624
Short name T408
Test name
Test status
Simulation time 1047153643 ps
CPU time 9.63 seconds
Started May 09 12:51:27 PM PDT 24
Finished May 09 12:51:39 PM PDT 24
Peak memory 204432 kb
Host smart-77811d5c-0c6d-48e7-88ed-2f6f99f2a2a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099173624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.1099173624
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.1901514370
Short name T553
Test name
Test status
Simulation time 22690665021 ps
CPU time 25.17 seconds
Started May 09 12:51:27 PM PDT 24
Finished May 09 12:51:55 PM PDT 24
Peak memory 342968 kb
Host smart-444c699d-d401-493a-89ad-2daabdb93cfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901514370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.1901514370
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1065906697
Short name T562
Test name
Test status
Simulation time 33830267288 ps
CPU time 1150.89 seconds
Started May 09 12:51:20 PM PDT 24
Finished May 09 01:10:33 PM PDT 24
Peak memory 4216460 kb
Host smart-7fc1560f-28e3-48fd-aeef-53dd0cdc67fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065906697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1065906697
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.1466393276
Short name T992
Test name
Test status
Simulation time 1490892323 ps
CPU time 7.45 seconds
Started May 09 12:51:24 PM PDT 24
Finished May 09 12:51:34 PM PDT 24
Peak memory 219900 kb
Host smart-5c033b7e-b3aa-4411-ac0f-a3af42afe891
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466393276 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.1466393276
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.2483852134
Short name T115
Test name
Test status
Simulation time 43354812 ps
CPU time 0.64 seconds
Started May 09 12:51:30 PM PDT 24
Finished May 09 12:51:33 PM PDT 24
Peak memory 204128 kb
Host smart-3fd4787a-3059-43aa-b0a2-6711f7bfdb5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483852134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.2483852134
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.244028491
Short name T191
Test name
Test status
Simulation time 210683690 ps
CPU time 2.01 seconds
Started May 09 12:51:19 PM PDT 24
Finished May 09 12:51:23 PM PDT 24
Peak memory 212772 kb
Host smart-9d17cc3a-53e9-4be6-9aa2-a5803363528f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244028491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.244028491
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.3415223883
Short name T256
Test name
Test status
Simulation time 413156040 ps
CPU time 12.36 seconds
Started May 09 12:51:26 PM PDT 24
Finished May 09 12:51:41 PM PDT 24
Peak memory 253800 kb
Host smart-a899661e-1ef1-4103-b68d-3eaf4aa63972
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415223883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.3415223883
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.1940252691
Short name T113
Test name
Test status
Simulation time 1837651846 ps
CPU time 109.36 seconds
Started May 09 12:51:22 PM PDT 24
Finished May 09 12:53:15 PM PDT 24
Peak memory 601912 kb
Host smart-7127d69e-b952-4f88-a624-ee75cadd9549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940252691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.1940252691
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.1192707259
Short name T10
Test name
Test status
Simulation time 7065394212 ps
CPU time 52.07 seconds
Started May 09 12:51:22 PM PDT 24
Finished May 09 12:52:17 PM PDT 24
Peak memory 645944 kb
Host smart-0f142c35-234d-4f8a-a857-9be7e206d243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192707259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1192707259
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.1134166536
Short name T216
Test name
Test status
Simulation time 239075057 ps
CPU time 1.06 seconds
Started May 09 12:51:19 PM PDT 24
Finished May 09 12:51:22 PM PDT 24
Peak memory 204392 kb
Host smart-3e361439-a8c8-4b01-8720-00f9c3287b59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134166536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.1134166536
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.3276905419
Short name T1008
Test name
Test status
Simulation time 167822215 ps
CPU time 7.99 seconds
Started May 09 12:51:22 PM PDT 24
Finished May 09 12:51:33 PM PDT 24
Peak memory 204372 kb
Host smart-4ade77bb-ae8a-4978-9af8-7952de53737e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276905419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.3276905419
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.2070100019
Short name T653
Test name
Test status
Simulation time 20734688552 ps
CPU time 66.15 seconds
Started May 09 12:51:19 PM PDT 24
Finished May 09 12:52:27 PM PDT 24
Peak memory 928400 kb
Host smart-1500335f-46e6-44e0-ac61-942ad05a9985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070100019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.2070100019
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.1690673669
Short name T965
Test name
Test status
Simulation time 905904443 ps
CPU time 3.3 seconds
Started May 09 12:51:29 PM PDT 24
Finished May 09 12:51:34 PM PDT 24
Peak memory 204380 kb
Host smart-5fe1c706-a60f-41b3-8005-d6659f4e8c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690673669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.1690673669
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_override.2394120573
Short name T120
Test name
Test status
Simulation time 50511876 ps
CPU time 0.67 seconds
Started May 09 12:51:28 PM PDT 24
Finished May 09 12:51:31 PM PDT 24
Peak memory 204148 kb
Host smart-b0954d3b-805d-4c1c-9cc7-2259464708d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394120573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.2394120573
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.2894670998
Short name T429
Test name
Test status
Simulation time 51462248491 ps
CPU time 219.14 seconds
Started May 09 12:51:22 PM PDT 24
Finished May 09 12:55:04 PM PDT 24
Peak memory 728480 kb
Host smart-4bda6934-f255-45b8-b69c-fc52fc60b9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894670998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.2894670998
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.1201133643
Short name T355
Test name
Test status
Simulation time 1502723463 ps
CPU time 34.5 seconds
Started May 09 12:51:19 PM PDT 24
Finished May 09 12:51:56 PM PDT 24
Peak memory 405140 kb
Host smart-fc875846-8fd4-4215-895b-ea6135bdcfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201133643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.1201133643
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.908363098
Short name T108
Test name
Test status
Simulation time 142987716842 ps
CPU time 467.54 seconds
Started May 09 12:51:25 PM PDT 24
Finished May 09 12:59:15 PM PDT 24
Peak memory 2319396 kb
Host smart-22a7d421-cb4a-461f-8000-fa6260ad3559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908363098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.908363098
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.3582082524
Short name T564
Test name
Test status
Simulation time 597876666 ps
CPU time 25.35 seconds
Started May 09 12:51:24 PM PDT 24
Finished May 09 12:51:52 PM PDT 24
Peak memory 212680 kb
Host smart-d362e629-854b-4501-bd7a-18d750349a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582082524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.3582082524
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.975542710
Short name T672
Test name
Test status
Simulation time 1391998175 ps
CPU time 4.04 seconds
Started May 09 12:51:32 PM PDT 24
Finished May 09 12:51:39 PM PDT 24
Peak memory 212352 kb
Host smart-bb8d9bae-ac77-47c6-85f9-bb3c7053ac33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975542710 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.975542710
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.848824218
Short name T58
Test name
Test status
Simulation time 10160994839 ps
CPU time 14.63 seconds
Started May 09 12:51:32 PM PDT 24
Finished May 09 12:51:50 PM PDT 24
Peak memory 268476 kb
Host smart-67beeb59-0a54-408e-8955-f3182a0a7800
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848824218 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.848824218
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.648625507
Short name T238
Test name
Test status
Simulation time 10042226288 ps
CPU time 62.8 seconds
Started May 09 12:51:37 PM PDT 24
Finished May 09 12:52:41 PM PDT 24
Peak memory 531580 kb
Host smart-215defaf-f3e5-4589-a1dd-046f5d09c7cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648625507 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.i2c_target_fifo_reset_tx.648625507
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.1665699632
Short name T605
Test name
Test status
Simulation time 411727452 ps
CPU time 2.64 seconds
Started May 09 12:51:30 PM PDT 24
Finished May 09 12:51:35 PM PDT 24
Peak memory 204400 kb
Host smart-df5a7808-ae27-4159-a9a5-d88d6baa59d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665699632 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.1665699632
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.3963151660
Short name T260
Test name
Test status
Simulation time 3011503134 ps
CPU time 3.9 seconds
Started May 09 12:51:20 PM PDT 24
Finished May 09 12:51:26 PM PDT 24
Peak memory 206092 kb
Host smart-4bdf880d-c55c-4b75-8c02-b6c1ad38e021
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963151660 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.3963151660
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.891676150
Short name T1079
Test name
Test status
Simulation time 22040644105 ps
CPU time 59.29 seconds
Started May 09 12:51:22 PM PDT 24
Finished May 09 12:52:25 PM PDT 24
Peak memory 1261208 kb
Host smart-553d23c9-5f0a-409a-9948-688dbbfed9f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891676150 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.891676150
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.558226221
Short name T298
Test name
Test status
Simulation time 4202149834 ps
CPU time 34.26 seconds
Started May 09 12:51:27 PM PDT 24
Finished May 09 12:52:03 PM PDT 24
Peak memory 204332 kb
Host smart-5905acc6-b2b8-419d-aa62-c1e40c1f10ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558226221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_tar
get_smoke.558226221
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.3464326750
Short name T360
Test name
Test status
Simulation time 1239943396 ps
CPU time 19.18 seconds
Started May 09 12:51:24 PM PDT 24
Finished May 09 12:51:46 PM PDT 24
Peak memory 228300 kb
Host smart-7a78cb36-6c81-44cc-9fce-ee41ff69af14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464326750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.3464326750
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.1265046111
Short name T688
Test name
Test status
Simulation time 23008596135 ps
CPU time 27 seconds
Started May 09 12:51:27 PM PDT 24
Finished May 09 12:51:56 PM PDT 24
Peak memory 439160 kb
Host smart-4e5edcd0-f49f-488b-bf1c-1f5b85fc5b87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265046111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.1265046111
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.3635334362
Short name T721
Test name
Test status
Simulation time 32772231743 ps
CPU time 387.7 seconds
Started May 09 12:51:24 PM PDT 24
Finished May 09 12:57:54 PM PDT 24
Peak memory 1255108 kb
Host smart-f61f4587-bbe2-437c-a7cd-081e9f796a5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635334362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.3635334362
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.4098602836
Short name T1250
Test name
Test status
Simulation time 1459430888 ps
CPU time 6.66 seconds
Started May 09 12:51:26 PM PDT 24
Finished May 09 12:51:35 PM PDT 24
Peak memory 204456 kb
Host smart-4f2801b1-225a-470c-9a26-319a6cf420a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098602836 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.4098602836
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.4005720977
Short name T263
Test name
Test status
Simulation time 14945627 ps
CPU time 0.62 seconds
Started May 09 12:51:47 PM PDT 24
Finished May 09 12:51:52 PM PDT 24
Peak memory 204232 kb
Host smart-77179f80-efad-4087-9776-b653c918ab6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005720977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.4005720977
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.2227563705
Short name T927
Test name
Test status
Simulation time 359181365 ps
CPU time 1.53 seconds
Started May 09 12:51:32 PM PDT 24
Finished May 09 12:51:37 PM PDT 24
Peak memory 212704 kb
Host smart-094cbc4a-41b6-44a5-a1ca-b5acece8c637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227563705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2227563705
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.3350263391
Short name T1248
Test name
Test status
Simulation time 233239427 ps
CPU time 4.86 seconds
Started May 09 12:51:34 PM PDT 24
Finished May 09 12:51:41 PM PDT 24
Peak memory 242536 kb
Host smart-881efd3a-51b1-4855-a79b-6e48e7698c56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350263391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.3350263391
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3764834292
Short name T1255
Test name
Test status
Simulation time 1688669618 ps
CPU time 110.62 seconds
Started May 09 12:51:33 PM PDT 24
Finished May 09 12:53:27 PM PDT 24
Peak memory 542608 kb
Host smart-c15969d7-4dae-4eb8-9f8c-a36e48a9da30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764834292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3764834292
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.2652295194
Short name T361
Test name
Test status
Simulation time 5235803510 ps
CPU time 97.51 seconds
Started May 09 12:51:32 PM PDT 24
Finished May 09 12:53:13 PM PDT 24
Peak memory 543904 kb
Host smart-8cbb4a1f-7e32-49cc-9463-1fb62ad77005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652295194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.2652295194
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.2314590427
Short name T530
Test name
Test status
Simulation time 128432427 ps
CPU time 1.03 seconds
Started May 09 12:51:30 PM PDT 24
Finished May 09 12:51:33 PM PDT 24
Peak memory 204128 kb
Host smart-efc0a666-8c00-48e2-8f71-a206bdbed7a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314590427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.2314590427
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3709980573
Short name T626
Test name
Test status
Simulation time 123369121 ps
CPU time 2.98 seconds
Started May 09 12:51:33 PM PDT 24
Finished May 09 12:51:39 PM PDT 24
Peak memory 222264 kb
Host smart-bc71f784-f9bd-4b83-954c-0cb4123d4b65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709980573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.3709980573
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.3288990182
Short name T221
Test name
Test status
Simulation time 18479011594 ps
CPU time 145.9 seconds
Started May 09 12:51:35 PM PDT 24
Finished May 09 12:54:03 PM PDT 24
Peak memory 1307292 kb
Host smart-b5e1ac6b-cb91-4d01-ba76-51edd7228d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288990182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3288990182
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.1546856726
Short name T989
Test name
Test status
Simulation time 376782379 ps
CPU time 4.67 seconds
Started May 09 12:51:47 PM PDT 24
Finished May 09 12:51:56 PM PDT 24
Peak memory 204488 kb
Host smart-b1d0a36f-332b-40a2-ba2e-b1f6a5b6c63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546856726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.1546856726
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.2484319054
Short name T756
Test name
Test status
Simulation time 1391471554 ps
CPU time 30.84 seconds
Started May 09 12:51:45 PM PDT 24
Finished May 09 12:52:20 PM PDT 24
Peak memory 376064 kb
Host smart-4440d36a-b9b5-4b25-a772-00910704ba27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484319054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.2484319054
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.1256437671
Short name T417
Test name
Test status
Simulation time 49050998 ps
CPU time 0.67 seconds
Started May 09 12:51:48 PM PDT 24
Finished May 09 12:51:52 PM PDT 24
Peak memory 204148 kb
Host smart-8714b314-e16f-474d-ac29-19605d296adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256437671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.1256437671
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.3062520149
Short name T1252
Test name
Test status
Simulation time 2614936246 ps
CPU time 108.58 seconds
Started May 09 12:51:32 PM PDT 24
Finished May 09 12:53:24 PM PDT 24
Peak memory 204524 kb
Host smart-68126b72-036f-47cc-895b-c884f1d092ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062520149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.3062520149
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.2564260795
Short name T738
Test name
Test status
Simulation time 3000372627 ps
CPU time 73.24 seconds
Started May 09 12:51:30 PM PDT 24
Finished May 09 12:52:45 PM PDT 24
Peak memory 391960 kb
Host smart-14a9382c-bb74-44e3-9caa-34ae0fd17103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564260795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.2564260795
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.3978350965
Short name T70
Test name
Test status
Simulation time 16263725975 ps
CPU time 1697.87 seconds
Started May 09 12:51:32 PM PDT 24
Finished May 09 01:19:53 PM PDT 24
Peak memory 2291160 kb
Host smart-3df4b760-2a21-40fa-9544-8d7107a1680c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978350965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.3978350965
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.1928168372
Short name T628
Test name
Test status
Simulation time 1663308535 ps
CPU time 19.97 seconds
Started May 09 12:51:32 PM PDT 24
Finished May 09 12:51:55 PM PDT 24
Peak memory 212636 kb
Host smart-226513d1-61c2-44bb-8d15-4a7bbe19c5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928168372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.1928168372
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.344867591
Short name T1158
Test name
Test status
Simulation time 582575606 ps
CPU time 2.67 seconds
Started May 09 12:51:42 PM PDT 24
Finished May 09 12:51:46 PM PDT 24
Peak memory 204444 kb
Host smart-b1055941-f8ce-44bd-b273-8f89388d4075
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344867591 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.344867591
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.3491170204
Short name T1163
Test name
Test status
Simulation time 10188031687 ps
CPU time 13.21 seconds
Started May 09 12:51:31 PM PDT 24
Finished May 09 12:51:48 PM PDT 24
Peak memory 243392 kb
Host smart-21a5c9ca-c2dc-4148-b2ff-fb38fc34787e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491170204 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.3491170204
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.2334512041
Short name T1120
Test name
Test status
Simulation time 10142476872 ps
CPU time 14.52 seconds
Started May 09 12:51:41 PM PDT 24
Finished May 09 12:51:58 PM PDT 24
Peak memory 274872 kb
Host smart-633aa0ae-7de6-4a94-b26f-48a9d1a85fde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334512041 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.2334512041
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.2263675544
Short name T8
Test name
Test status
Simulation time 328453286 ps
CPU time 2.19 seconds
Started May 09 12:51:44 PM PDT 24
Finished May 09 12:51:50 PM PDT 24
Peak memory 204456 kb
Host smart-56bf6680-f440-463e-89c3-c5dd96ce4f90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263675544 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.2263675544
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.3257692494
Short name T466
Test name
Test status
Simulation time 12254976165 ps
CPU time 8.66 seconds
Started May 09 12:51:34 PM PDT 24
Finished May 09 12:51:45 PM PDT 24
Peak memory 220688 kb
Host smart-dc080c43-18d0-41d8-8515-d77b74221744
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257692494 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.3257692494
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.288980838
Short name T538
Test name
Test status
Simulation time 18356451741 ps
CPU time 37.81 seconds
Started May 09 12:51:31 PM PDT 24
Finished May 09 12:52:12 PM PDT 24
Peak memory 754456 kb
Host smart-a5f5d5dd-75a9-403c-b2ca-7c7719dbc96f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288980838 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.288980838
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.2481336859
Short name T1356
Test name
Test status
Simulation time 1032538468 ps
CPU time 38.82 seconds
Started May 09 12:51:31 PM PDT 24
Finished May 09 12:52:13 PM PDT 24
Peak memory 204452 kb
Host smart-6bd564d2-f516-4b20-a436-b2fe658226c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481336859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.2481336859
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2389412691
Short name T891
Test name
Test status
Simulation time 10724492497 ps
CPU time 54.25 seconds
Started May 09 12:51:31 PM PDT 24
Finished May 09 12:52:28 PM PDT 24
Peak memory 207180 kb
Host smart-9348b711-8b99-4f8d-948e-f2509b1a16d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389412691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2389412691
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.3621851051
Short name T869
Test name
Test status
Simulation time 22697936916 ps
CPU time 10.71 seconds
Started May 09 12:51:34 PM PDT 24
Finished May 09 12:51:47 PM PDT 24
Peak memory 215012 kb
Host smart-4b75932a-e009-4160-b2fd-f29b854ebbf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621851051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.3621851051
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.2368358391
Short name T388
Test name
Test status
Simulation time 1210193710 ps
CPU time 6.58 seconds
Started May 09 12:51:30 PM PDT 24
Finished May 09 12:51:40 PM PDT 24
Peak memory 212676 kb
Host smart-aa290192-bf5a-44d5-88f7-d2d26a0536d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368358391 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.2368358391
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.191776867
Short name T376
Test name
Test status
Simulation time 49022954 ps
CPU time 0.63 seconds
Started May 09 12:51:46 PM PDT 24
Finished May 09 12:51:51 PM PDT 24
Peak memory 204072 kb
Host smart-1c169ba1-b431-44d3-b57b-9de1ac94a643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191776867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.191776867
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.1412320576
Short name T625
Test name
Test status
Simulation time 206372231 ps
CPU time 1.55 seconds
Started May 09 12:51:44 PM PDT 24
Finished May 09 12:51:49 PM PDT 24
Peak memory 212720 kb
Host smart-aff840df-a0b4-4db6-a41f-4f1ec389b500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412320576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1412320576
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.3667956190
Short name T892
Test name
Test status
Simulation time 1104876104 ps
CPU time 13.65 seconds
Started May 09 12:51:41 PM PDT 24
Finished May 09 12:51:57 PM PDT 24
Peak memory 249408 kb
Host smart-c59c7cba-bbac-47e3-a139-7de9b0208566
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667956190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.3667956190
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.3728344429
Short name T1324
Test name
Test status
Simulation time 1096098325 ps
CPU time 69.61 seconds
Started May 09 12:51:46 PM PDT 24
Finished May 09 12:53:00 PM PDT 24
Peak memory 441364 kb
Host smart-9f2f86ac-1cf1-4577-bae9-d95d2ce71a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728344429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.3728344429
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.1790502394
Short name T524
Test name
Test status
Simulation time 10447845425 ps
CPU time 80.43 seconds
Started May 09 12:51:43 PM PDT 24
Finished May 09 12:53:07 PM PDT 24
Peak memory 464976 kb
Host smart-aa514810-ea04-4b9e-ab30-379d5a1ddf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790502394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.1790502394
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.654804690
Short name T498
Test name
Test status
Simulation time 159429336 ps
CPU time 1.14 seconds
Started May 09 12:51:46 PM PDT 24
Finished May 09 12:51:52 PM PDT 24
Peak memory 204356 kb
Host smart-fd362ed3-a7df-46cb-b1a0-f8a160f97210
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654804690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.654804690
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.3316676703
Short name T826
Test name
Test status
Simulation time 133620877 ps
CPU time 6.8 seconds
Started May 09 12:51:43 PM PDT 24
Finished May 09 12:51:54 PM PDT 24
Peak memory 204448 kb
Host smart-515020e3-db14-4e7a-a52d-6bb65bf1a1fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316676703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.3316676703
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.1217656775
Short name T224
Test name
Test status
Simulation time 6959714125 ps
CPU time 78.28 seconds
Started May 09 12:51:46 PM PDT 24
Finished May 09 12:53:09 PM PDT 24
Peak memory 870880 kb
Host smart-4637bcd7-55e0-4184-bbb8-84a8a8558515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217656775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.1217656775
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.3442480380
Short name T744
Test name
Test status
Simulation time 1316342209 ps
CPU time 12.52 seconds
Started May 09 12:51:41 PM PDT 24
Finished May 09 12:51:55 PM PDT 24
Peak memory 204444 kb
Host smart-39bed299-eb7b-4b47-bdb5-c6c48bd398bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442480380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.3442480380
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.746096498
Short name T608
Test name
Test status
Simulation time 1195693606 ps
CPU time 20.84 seconds
Started May 09 12:51:45 PM PDT 24
Finished May 09 12:52:10 PM PDT 24
Peak memory 342584 kb
Host smart-334bf2f9-fcbb-49da-8a06-50767ff92271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746096498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.746096498
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.2325635169
Short name T434
Test name
Test status
Simulation time 15991183 ps
CPU time 0.65 seconds
Started May 09 12:51:43 PM PDT 24
Finished May 09 12:51:47 PM PDT 24
Peak memory 204024 kb
Host smart-b77f56cd-519b-4376-93d4-52c04023367b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325635169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.2325635169
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.2385764929
Short name T638
Test name
Test status
Simulation time 10872014620 ps
CPU time 47.82 seconds
Started May 09 12:51:41 PM PDT 24
Finished May 09 12:52:31 PM PDT 24
Peak memory 283104 kb
Host smart-3df63f82-0272-4e1f-8a48-506ce8c4f6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385764929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.2385764929
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.14466651
Short name T974
Test name
Test status
Simulation time 12502528038 ps
CPU time 355.53 seconds
Started May 09 12:51:43 PM PDT 24
Finished May 09 12:57:42 PM PDT 24
Peak memory 1620436 kb
Host smart-ac428420-0361-47e6-bc19-54cd10a711c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14466651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.14466651
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.38812616
Short name T289
Test name
Test status
Simulation time 734619275 ps
CPU time 11.52 seconds
Started May 09 12:51:41 PM PDT 24
Finished May 09 12:51:54 PM PDT 24
Peak memory 228896 kb
Host smart-5cc4ffb1-3e09-4d3a-be58-faf8af7da5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38812616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.38812616
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.3327984503
Short name T747
Test name
Test status
Simulation time 3075170428 ps
CPU time 3.84 seconds
Started May 09 12:51:41 PM PDT 24
Finished May 09 12:51:47 PM PDT 24
Peak memory 204416 kb
Host smart-6f3a101e-6d07-40ee-b22a-e9d6579007a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327984503 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.3327984503
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.611901159
Short name T1148
Test name
Test status
Simulation time 10119618295 ps
CPU time 28.43 seconds
Started May 09 12:51:45 PM PDT 24
Finished May 09 12:52:18 PM PDT 24
Peak memory 342584 kb
Host smart-1729c951-e206-42e1-9932-71483633a1c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611901159 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_acq.611901159
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.61355717
Short name T1353
Test name
Test status
Simulation time 10179448512 ps
CPU time 13.14 seconds
Started May 09 12:51:44 PM PDT 24
Finished May 09 12:52:02 PM PDT 24
Peak memory 260156 kb
Host smart-555b1423-c640-43fb-b5c6-ca6841c0403e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61355717 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_fifo_reset_tx.61355717
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.73105567
Short name T23
Test name
Test status
Simulation time 1904687618 ps
CPU time 2.52 seconds
Started May 09 12:51:43 PM PDT 24
Finished May 09 12:51:49 PM PDT 24
Peak memory 204412 kb
Host smart-56a5f06e-6253-47c1-a520-2ead35b138b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73105567 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.i2c_target_hrst.73105567
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.2675057155
Short name T1270
Test name
Test status
Simulation time 2469162495 ps
CPU time 3.6 seconds
Started May 09 12:51:44 PM PDT 24
Finished May 09 12:51:52 PM PDT 24
Peak memory 204396 kb
Host smart-deab397c-f183-4e53-89d1-8dbcdb48a1c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675057155 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.2675057155
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.1581108515
Short name T944
Test name
Test status
Simulation time 7727765834 ps
CPU time 19.27 seconds
Started May 09 12:51:42 PM PDT 24
Finished May 09 12:52:03 PM PDT 24
Peak memory 307248 kb
Host smart-89a9ab37-2f42-48c5-b707-1312b198381a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581108515 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.1581108515
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.396423145
Short name T1182
Test name
Test status
Simulation time 1578022556 ps
CPU time 11.26 seconds
Started May 09 12:51:44 PM PDT 24
Finished May 09 12:51:59 PM PDT 24
Peak memory 204444 kb
Host smart-dfc35eaf-c2ab-4f04-a916-7368760f18ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396423145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_tar
get_smoke.396423145
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.3529743234
Short name T846
Test name
Test status
Simulation time 1269067709 ps
CPU time 5.09 seconds
Started May 09 12:51:44 PM PDT 24
Finished May 09 12:51:54 PM PDT 24
Peak memory 204452 kb
Host smart-4fcb7df3-69a8-4da6-a0de-7659b8643544
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529743234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.3529743234
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.3364521614
Short name T923
Test name
Test status
Simulation time 47870618100 ps
CPU time 225.68 seconds
Started May 09 12:51:42 PM PDT 24
Finished May 09 12:55:30 PM PDT 24
Peak memory 2852848 kb
Host smart-b579d15a-e7fd-4a2d-9264-bac9cd8bdd1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364521614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.3364521614
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.1010473586
Short name T1233
Test name
Test status
Simulation time 5804494592 ps
CPU time 5.92 seconds
Started May 09 12:51:43 PM PDT 24
Finished May 09 12:51:53 PM PDT 24
Peak memory 212700 kb
Host smart-43546216-491b-47d3-b123-917bdda031c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010473586 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.1010473586
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.2798429651
Short name T153
Test name
Test status
Simulation time 18887248 ps
CPU time 0.58 seconds
Started May 09 12:51:56 PM PDT 24
Finished May 09 12:51:59 PM PDT 24
Peak memory 204068 kb
Host smart-305152d6-5fa9-462d-a212-069bdb204416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798429651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2798429651
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.2906983979
Short name T762
Test name
Test status
Simulation time 124398019 ps
CPU time 1.55 seconds
Started May 09 12:51:52 PM PDT 24
Finished May 09 12:51:57 PM PDT 24
Peak memory 212748 kb
Host smart-00e0692e-e50a-45aa-ade6-ee96f2be3e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906983979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.2906983979
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.2984301734
Short name T1326
Test name
Test status
Simulation time 232066906 ps
CPU time 4.76 seconds
Started May 09 12:51:54 PM PDT 24
Finished May 09 12:52:02 PM PDT 24
Peak memory 241076 kb
Host smart-564a664a-8ae4-463a-8f49-662420922990
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984301734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.2984301734
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.3061554228
Short name T1109
Test name
Test status
Simulation time 16254038535 ps
CPU time 36.2 seconds
Started May 09 12:51:51 PM PDT 24
Finished May 09 12:52:31 PM PDT 24
Peak memory 479724 kb
Host smart-cbe81ab2-4225-46f8-92ed-48d7ac4b47ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061554228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.3061554228
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.2214158141
Short name T1014
Test name
Test status
Simulation time 1226673365 ps
CPU time 68.57 seconds
Started May 09 12:51:56 PM PDT 24
Finished May 09 12:53:07 PM PDT 24
Peak memory 481832 kb
Host smart-81754503-8412-456d-8e5d-5fa6006616f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214158141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2214158141
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.1732822854
Short name T962
Test name
Test status
Simulation time 131109281 ps
CPU time 0.93 seconds
Started May 09 12:51:51 PM PDT 24
Finished May 09 12:51:56 PM PDT 24
Peak memory 204164 kb
Host smart-4f9278f5-9c8e-4b16-ba5c-d94dcb6abf74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732822854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.1732822854
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.752368767
Short name T274
Test name
Test status
Simulation time 370248637 ps
CPU time 3.8 seconds
Started May 09 12:51:51 PM PDT 24
Finished May 09 12:51:59 PM PDT 24
Peak memory 204324 kb
Host smart-6d0ecd55-f524-4aa8-bad1-9e5a55dcd20e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752368767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.
752368767
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.2578976261
Short name T269
Test name
Test status
Simulation time 3755402294 ps
CPU time 83.33 seconds
Started May 09 12:51:57 PM PDT 24
Finished May 09 12:53:22 PM PDT 24
Peak memory 1007772 kb
Host smart-81f5ebbf-6002-4d10-8d9a-c15cfa7eef8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578976261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2578976261
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.1235724471
Short name T745
Test name
Test status
Simulation time 2432141350 ps
CPU time 6.3 seconds
Started May 09 12:51:52 PM PDT 24
Finished May 09 12:52:02 PM PDT 24
Peak memory 204404 kb
Host smart-fe353c44-53e1-42d9-aace-9c2adf1248e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235724471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.1235724471
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.1800421489
Short name T687
Test name
Test status
Simulation time 3687701069 ps
CPU time 39.7 seconds
Started May 09 12:51:50 PM PDT 24
Finished May 09 12:52:34 PM PDT 24
Peak memory 382332 kb
Host smart-a0d8d7ca-1ae5-477b-bade-b0aabe40951b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800421489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.1800421489
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.694073022
Short name T358
Test name
Test status
Simulation time 46744756 ps
CPU time 0.63 seconds
Started May 09 12:51:52 PM PDT 24
Finished May 09 12:51:56 PM PDT 24
Peak memory 204148 kb
Host smart-87ea7a21-fb03-476e-9603-1bdc53ecc559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694073022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.694073022
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.2453404212
Short name T38
Test name
Test status
Simulation time 7243203417 ps
CPU time 23.66 seconds
Started May 09 12:51:54 PM PDT 24
Finished May 09 12:52:20 PM PDT 24
Peak memory 266120 kb
Host smart-246df3a2-10ec-4bfd-9c28-3bba82e3b09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453404212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2453404212
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.501458779
Short name T1156
Test name
Test status
Simulation time 1240619892 ps
CPU time 19.71 seconds
Started May 09 12:51:51 PM PDT 24
Finished May 09 12:52:14 PM PDT 24
Peak memory 318224 kb
Host smart-c80a5314-0596-409a-aced-7fc310efddbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501458779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.501458779
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.1223843387
Short name T1031
Test name
Test status
Simulation time 7954823023 ps
CPU time 7.01 seconds
Started May 09 12:51:51 PM PDT 24
Finished May 09 12:52:02 PM PDT 24
Peak memory 213784 kb
Host smart-44c6a4bc-f849-4aa8-9407-2f26774c15e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223843387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1223843387
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3926032812
Short name T1030
Test name
Test status
Simulation time 926381695 ps
CPU time 3.02 seconds
Started May 09 12:51:52 PM PDT 24
Finished May 09 12:51:58 PM PDT 24
Peak memory 204512 kb
Host smart-1ec2a6ba-bb0f-4e31-9ac4-56fdc106a34f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926032812 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3926032812
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.2113848564
Short name T531
Test name
Test status
Simulation time 10049559207 ps
CPU time 80.11 seconds
Started May 09 12:51:51 PM PDT 24
Finished May 09 12:53:15 PM PDT 24
Peak memory 445280 kb
Host smart-6b2ab01e-412d-4545-9d03-59983f223dab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113848564 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.2113848564
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.3570518077
Short name T972
Test name
Test status
Simulation time 10046785664 ps
CPU time 84.38 seconds
Started May 09 12:51:57 PM PDT 24
Finished May 09 12:53:23 PM PDT 24
Peak memory 471072 kb
Host smart-bbe6b99d-c385-4f37-9b3f-383dc692d29f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570518077 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.3570518077
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.2381317217
Short name T1271
Test name
Test status
Simulation time 2249562928 ps
CPU time 3.27 seconds
Started May 09 12:51:58 PM PDT 24
Finished May 09 12:52:03 PM PDT 24
Peak memory 204476 kb
Host smart-8ca7e0e9-fa44-45f7-af89-4d4ec0f7f55d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381317217 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.2381317217
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.2618491078
Short name T312
Test name
Test status
Simulation time 1589352023 ps
CPU time 4.94 seconds
Started May 09 12:51:51 PM PDT 24
Finished May 09 12:51:59 PM PDT 24
Peak memory 204452 kb
Host smart-e37995f6-e81c-4396-b4a6-f8fbf6118f7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618491078 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.2618491078
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.1393854720
Short name T1172
Test name
Test status
Simulation time 9562012962 ps
CPU time 10.61 seconds
Started May 09 12:51:56 PM PDT 24
Finished May 09 12:52:09 PM PDT 24
Peak memory 301928 kb
Host smart-81a391b4-1905-49c4-9aa4-e8bd0dd78995
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393854720 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.1393854720
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.3788605910
Short name T822
Test name
Test status
Simulation time 1114148263 ps
CPU time 40.03 seconds
Started May 09 12:51:54 PM PDT 24
Finished May 09 12:52:37 PM PDT 24
Peak memory 204328 kb
Host smart-63d6f2a8-8727-47a5-8519-ccf366ddc412
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788605910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.3788605910
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.3077810385
Short name T1169
Test name
Test status
Simulation time 6611817668 ps
CPU time 14.25 seconds
Started May 09 12:51:51 PM PDT 24
Finished May 09 12:52:09 PM PDT 24
Peak memory 211748 kb
Host smart-bb16a09a-1f1b-4c05-9b5f-9d0e2f343158
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077810385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.3077810385
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.1594545507
Short name T314
Test name
Test status
Simulation time 57932958618 ps
CPU time 1698.55 seconds
Started May 09 12:51:57 PM PDT 24
Finished May 09 01:20:18 PM PDT 24
Peak memory 9483268 kb
Host smart-9cffa15a-e05a-4d45-9db0-92510ed7fb94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594545507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.1594545507
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.2562530543
Short name T401
Test name
Test status
Simulation time 32492979596 ps
CPU time 2187.62 seconds
Started May 09 12:51:50 PM PDT 24
Finished May 09 01:28:21 PM PDT 24
Peak memory 3884556 kb
Host smart-4e083b9e-604c-40b2-bead-101916ec7b00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562530543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.2562530543
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.2353978256
Short name T508
Test name
Test status
Simulation time 1010575487 ps
CPU time 6.25 seconds
Started May 09 12:51:57 PM PDT 24
Finished May 09 12:52:06 PM PDT 24
Peak memory 212568 kb
Host smart-a3aba6a7-79e1-4935-90ec-4e727fb0d728
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353978256 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.2353978256
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.3826893010
Short name T1242
Test name
Test status
Simulation time 16826231 ps
CPU time 0.63 seconds
Started May 09 12:52:04 PM PDT 24
Finished May 09 12:52:08 PM PDT 24
Peak memory 204216 kb
Host smart-809a9b99-b6b8-4ddf-9097-3db82c1646ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826893010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.3826893010
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.2969774339
Short name T656
Test name
Test status
Simulation time 80838250 ps
CPU time 1.88 seconds
Started May 09 12:52:05 PM PDT 24
Finished May 09 12:52:09 PM PDT 24
Peak memory 212772 kb
Host smart-dd8e43fb-d9f6-4898-8d31-176a8cc75475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969774339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.2969774339
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.4291119400
Short name T375
Test name
Test status
Simulation time 764314609 ps
CPU time 4.68 seconds
Started May 09 12:52:01 PM PDT 24
Finished May 09 12:52:07 PM PDT 24
Peak memory 254588 kb
Host smart-03c0c5dd-ff21-4a35-a1d6-0b44695f56c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291119400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.4291119400
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.755966923
Short name T543
Test name
Test status
Simulation time 3491194464 ps
CPU time 83.94 seconds
Started May 09 12:52:05 PM PDT 24
Finished May 09 12:53:32 PM PDT 24
Peak memory 821496 kb
Host smart-e2efeaf2-763d-4a7e-8615-52d12ba2861e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755966923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.755966923
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.2271514739
Short name T293
Test name
Test status
Simulation time 3656359612 ps
CPU time 55.63 seconds
Started May 09 12:51:57 PM PDT 24
Finished May 09 12:52:55 PM PDT 24
Peak memory 648900 kb
Host smart-707f0e79-4ebd-4353-9f4d-40f28e2a3eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271514739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2271514739
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.460839907
Short name T369
Test name
Test status
Simulation time 751125011 ps
CPU time 1.02 seconds
Started May 09 12:51:52 PM PDT 24
Finished May 09 12:51:57 PM PDT 24
Peak memory 204236 kb
Host smart-df2ee911-08cf-4139-ab6c-46d7e7db07a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460839907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fm
t.460839907
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.3758788893
Short name T990
Test name
Test status
Simulation time 218433173 ps
CPU time 5.34 seconds
Started May 09 12:52:01 PM PDT 24
Finished May 09 12:52:08 PM PDT 24
Peak memory 237812 kb
Host smart-3ac58072-7565-429b-8edf-cd473e5fc773
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758788893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.3758788893
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.377785863
Short name T1094
Test name
Test status
Simulation time 11564637030 ps
CPU time 74.18 seconds
Started May 09 12:51:53 PM PDT 24
Finished May 09 12:53:11 PM PDT 24
Peak memory 843256 kb
Host smart-a32f09a5-f87b-4e96-a922-4735ffab2f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377785863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.377785863
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.3973633013
Short name T1133
Test name
Test status
Simulation time 1147573071 ps
CPU time 4.01 seconds
Started May 09 12:52:02 PM PDT 24
Finished May 09 12:52:07 PM PDT 24
Peak memory 204440 kb
Host smart-54146794-10ff-41b1-972a-3d533ba07102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973633013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.3973633013
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.3582377870
Short name T1160
Test name
Test status
Simulation time 1462337678 ps
CPU time 27.51 seconds
Started May 09 12:52:01 PM PDT 24
Finished May 09 12:52:30 PM PDT 24
Peak memory 361000 kb
Host smart-7f2fbe85-eb5d-438a-b25b-2b08d097bbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582377870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.3582377870
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.2823810905
Short name T1020
Test name
Test status
Simulation time 44298860 ps
CPU time 0.7 seconds
Started May 09 12:51:51 PM PDT 24
Finished May 09 12:51:55 PM PDT 24
Peak memory 204132 kb
Host smart-7039e363-acd9-4f4d-b513-4c2734aeec9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823810905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.2823810905
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.3123441270
Short name T580
Test name
Test status
Simulation time 27222578399 ps
CPU time 1715.94 seconds
Started May 09 12:52:04 PM PDT 24
Finished May 09 01:20:43 PM PDT 24
Peak memory 3909016 kb
Host smart-6daee9e3-3776-47aa-a720-9ce0569f05a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123441270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.3123441270
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.1945964653
Short name T1284
Test name
Test status
Simulation time 5703449065 ps
CPU time 22.86 seconds
Started May 09 12:51:57 PM PDT 24
Finished May 09 12:52:23 PM PDT 24
Peak memory 325088 kb
Host smart-9327f5f9-1b39-4e49-9f3e-fa376db2392b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945964653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.1945964653
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.4001624043
Short name T1064
Test name
Test status
Simulation time 1233596151 ps
CPU time 11.68 seconds
Started May 09 12:52:05 PM PDT 24
Finished May 09 12:52:20 PM PDT 24
Peak memory 213728 kb
Host smart-506cbafb-3937-480f-a428-609ab4a863a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001624043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.4001624043
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.480482367
Short name T736
Test name
Test status
Simulation time 3416256879 ps
CPU time 4.1 seconds
Started May 09 12:52:02 PM PDT 24
Finished May 09 12:52:08 PM PDT 24
Peak memory 212644 kb
Host smart-330fb056-64f8-42d5-bc25-1d1b281edadb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480482367 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.480482367
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.2075534564
Short name T920
Test name
Test status
Simulation time 10454579758 ps
CPU time 4.84 seconds
Started May 09 12:52:02 PM PDT 24
Finished May 09 12:52:08 PM PDT 24
Peak memory 221084 kb
Host smart-086cc089-b8dd-4688-bb01-a555e18da976
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075534564 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.2075534564
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.3692692124
Short name T1040
Test name
Test status
Simulation time 10061068356 ps
CPU time 87.62 seconds
Started May 09 12:52:05 PM PDT 24
Finished May 09 12:53:35 PM PDT 24
Peak memory 617828 kb
Host smart-b4d9a004-50ea-4f89-9570-200003867941
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692692124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.3692692124
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.817997355
Short name T1357
Test name
Test status
Simulation time 936103711 ps
CPU time 2.87 seconds
Started May 09 12:52:05 PM PDT 24
Finished May 09 12:52:10 PM PDT 24
Peak memory 204476 kb
Host smart-aae2844b-b5c2-48b1-9cf0-d3fdc7c014f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817997355 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.i2c_target_hrst.817997355
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.3153068972
Short name T268
Test name
Test status
Simulation time 2875977129 ps
CPU time 4.76 seconds
Started May 09 12:52:04 PM PDT 24
Finished May 09 12:52:12 PM PDT 24
Peak memory 204912 kb
Host smart-26787146-57a0-4b4a-a6d7-70c71478500c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153068972 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.3153068972
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.2264357484
Short name T17
Test name
Test status
Simulation time 16194004393 ps
CPU time 205.52 seconds
Started May 09 12:52:09 PM PDT 24
Finished May 09 12:55:36 PM PDT 24
Peak memory 2475688 kb
Host smart-27ae4881-7122-4942-a188-46c260887f4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264357484 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.2264357484
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.631010743
Short name T1122
Test name
Test status
Simulation time 1482220207 ps
CPU time 17.99 seconds
Started May 09 12:52:02 PM PDT 24
Finished May 09 12:52:22 PM PDT 24
Peak memory 204484 kb
Host smart-0eb840ad-4b5d-4547-a3f7-dc278eec3d58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631010743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_tar
get_smoke.631010743
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.26504740
Short name T642
Test name
Test status
Simulation time 1271998241 ps
CPU time 52.3 seconds
Started May 09 12:52:04 PM PDT 24
Finished May 09 12:52:59 PM PDT 24
Peak memory 204476 kb
Host smart-91ab3bf8-204f-4e0c-b317-85c826e1f182
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26504740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stress_rd.26504740
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.541592333
Short name T1108
Test name
Test status
Simulation time 48140174408 ps
CPU time 801.12 seconds
Started May 09 12:52:04 PM PDT 24
Finished May 09 01:05:27 PM PDT 24
Peak memory 5872624 kb
Host smart-e27b3a93-d50e-497c-9799-31390f179ca4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541592333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_wr.541592333
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.561083995
Short name T713
Test name
Test status
Simulation time 19732205594 ps
CPU time 3280.06 seconds
Started May 09 12:52:03 PM PDT 24
Finished May 09 01:46:45 PM PDT 24
Peak memory 4571020 kb
Host smart-86cd57cb-8206-40b8-9544-99e276e7fd2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561083995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_t
arget_stretch.561083995
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.1295297521
Short name T1328
Test name
Test status
Simulation time 1064541452 ps
CPU time 7.03 seconds
Started May 09 12:52:05 PM PDT 24
Finished May 09 12:52:15 PM PDT 24
Peak memory 220796 kb
Host smart-67e1b464-33c1-4b64-ab0e-47801f567bd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295297521 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.1295297521
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.3924090546
Short name T439
Test name
Test status
Simulation time 18825609 ps
CPU time 0.66 seconds
Started May 09 12:52:15 PM PDT 24
Finished May 09 12:52:19 PM PDT 24
Peak memory 204472 kb
Host smart-8f666a6e-dc92-4c2d-8414-4497920f5e14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924090546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.3924090546
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.3255515272
Short name T365
Test name
Test status
Simulation time 62956634 ps
CPU time 1.62 seconds
Started May 09 12:52:03 PM PDT 24
Finished May 09 12:52:07 PM PDT 24
Peak memory 212768 kb
Host smart-0beafd0d-03f0-4cd7-94cf-9b4c99f14733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255515272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3255515272
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.2502938631
Short name T1228
Test name
Test status
Simulation time 1197644921 ps
CPU time 15.76 seconds
Started May 09 12:52:06 PM PDT 24
Finished May 09 12:52:25 PM PDT 24
Peak memory 268100 kb
Host smart-6a71838b-7aff-417d-b9fc-6d6d8d7f1091
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502938631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.2502938631
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.863871019
Short name T1317
Test name
Test status
Simulation time 18012310534 ps
CPU time 30.43 seconds
Started May 09 12:52:02 PM PDT 24
Finished May 09 12:52:35 PM PDT 24
Peak memory 474712 kb
Host smart-55ca7f13-ff0d-4d83-8ae9-278cff7b610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863871019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.863871019
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.1174826356
Short name T163
Test name
Test status
Simulation time 3358016944 ps
CPU time 83.42 seconds
Started May 09 12:52:02 PM PDT 24
Finished May 09 12:53:27 PM PDT 24
Peak memory 743392 kb
Host smart-5a55f32f-5adb-4b46-9c76-1878e62ecc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174826356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.1174826356
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.2484607038
Short name T442
Test name
Test status
Simulation time 363737388 ps
CPU time 0.92 seconds
Started May 09 12:52:05 PM PDT 24
Finished May 09 12:52:09 PM PDT 24
Peak memory 204136 kb
Host smart-6e955bdf-e817-413d-93b3-3a22b0abfe22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484607038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.2484607038
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.3425228860
Short name T872
Test name
Test status
Simulation time 104728395 ps
CPU time 2.4 seconds
Started May 09 12:52:03 PM PDT 24
Finished May 09 12:52:08 PM PDT 24
Peak memory 204496 kb
Host smart-0b412c5d-cac0-4b6c-bf69-c82533b4127d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425228860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.3425228860
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.760581877
Short name T1129
Test name
Test status
Simulation time 3300927035 ps
CPU time 70.84 seconds
Started May 09 12:52:05 PM PDT 24
Finished May 09 12:53:19 PM PDT 24
Peak memory 913092 kb
Host smart-b113952d-69a3-4cfe-9c0b-c736129bc007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760581877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.760581877
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.1016222105
Short name T468
Test name
Test status
Simulation time 3016194470 ps
CPU time 29.55 seconds
Started May 09 12:52:14 PM PDT 24
Finished May 09 12:52:46 PM PDT 24
Peak memory 204492 kb
Host smart-44d191a4-856c-413b-bae5-af915c2040e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016222105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.1016222105
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.20665976
Short name T830
Test name
Test status
Simulation time 1757660480 ps
CPU time 32.95 seconds
Started May 09 12:52:14 PM PDT 24
Finished May 09 12:52:50 PM PDT 24
Peak memory 411152 kb
Host smart-80a4b99c-4063-49b9-a699-45eb5729b14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20665976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.20665976
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.246093304
Short name T728
Test name
Test status
Simulation time 59880267 ps
CPU time 0.67 seconds
Started May 09 12:52:04 PM PDT 24
Finished May 09 12:52:08 PM PDT 24
Peak memory 204160 kb
Host smart-100da908-bcb0-4a57-aefb-f05d67882c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246093304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.246093304
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.3402778996
Short name T1361
Test name
Test status
Simulation time 6401973412 ps
CPU time 51.71 seconds
Started May 09 12:52:04 PM PDT 24
Finished May 09 12:52:58 PM PDT 24
Peak memory 212616 kb
Host smart-2ba4f77b-761c-4024-a851-ec3220b33ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402778996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.3402778996
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.586910481
Short name T784
Test name
Test status
Simulation time 2419912722 ps
CPU time 55.56 seconds
Started May 09 12:52:02 PM PDT 24
Finished May 09 12:53:00 PM PDT 24
Peak memory 286072 kb
Host smart-a80cff55-a91a-46f5-b8a2-81b4a1605b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586910481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.586910481
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.55452826
Short name T1012
Test name
Test status
Simulation time 52607129798 ps
CPU time 904.38 seconds
Started May 09 12:52:04 PM PDT 24
Finished May 09 01:07:11 PM PDT 24
Peak memory 2860808 kb
Host smart-aa36167f-c2e9-41ba-a86a-3f63152d7071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55452826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.55452826
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.2848776500
Short name T557
Test name
Test status
Simulation time 1688358487 ps
CPU time 39.08 seconds
Started May 09 12:52:04 PM PDT 24
Finished May 09 12:52:46 PM PDT 24
Peak memory 213540 kb
Host smart-dcb877e9-3847-4bce-b514-1a3898757036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848776500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2848776500
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.878026605
Short name T787
Test name
Test status
Simulation time 790444000 ps
CPU time 3.86 seconds
Started May 09 12:52:12 PM PDT 24
Finished May 09 12:52:18 PM PDT 24
Peak memory 212628 kb
Host smart-740bc2d1-5994-4bbf-bc1c-a0034f07bd2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878026605 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.878026605
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.974961645
Short name T709
Test name
Test status
Simulation time 10255489318 ps
CPU time 13.06 seconds
Started May 09 12:52:12 PM PDT 24
Finished May 09 12:52:26 PM PDT 24
Peak memory 262636 kb
Host smart-16678fb8-1853-465f-bac7-b2930cc60ef0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974961645 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_acq.974961645
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.2943011130
Short name T836
Test name
Test status
Simulation time 10228722221 ps
CPU time 14.44 seconds
Started May 09 12:52:15 PM PDT 24
Finished May 09 12:52:33 PM PDT 24
Peak memory 299048 kb
Host smart-cd4373b7-494d-4ae4-92ec-5161976bb96c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943011130 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.2943011130
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.2791614079
Short name T1275
Test name
Test status
Simulation time 439889487 ps
CPU time 2.82 seconds
Started May 09 12:52:13 PM PDT 24
Finished May 09 12:52:18 PM PDT 24
Peak memory 204460 kb
Host smart-003eb331-ca97-49e9-a349-eb560edee449
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791614079 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.2791614079
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.807310590
Short name T309
Test name
Test status
Simulation time 2387503355 ps
CPU time 5.88 seconds
Started May 09 12:52:04 PM PDT 24
Finished May 09 12:52:13 PM PDT 24
Peak memory 218816 kb
Host smart-1e716e46-7357-4cbd-b359-d08e8f8df927
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807310590 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.807310590
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.4032751874
Short name T340
Test name
Test status
Simulation time 17708028213 ps
CPU time 20.26 seconds
Started May 09 12:52:13 PM PDT 24
Finished May 09 12:52:35 PM PDT 24
Peak memory 585148 kb
Host smart-6f9b7a47-f54d-441d-8cb0-6041170b12b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032751874 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.4032751874
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.4096054835
Short name T574
Test name
Test status
Simulation time 4676088695 ps
CPU time 27.04 seconds
Started May 09 12:52:03 PM PDT 24
Finished May 09 12:52:32 PM PDT 24
Peak memory 204528 kb
Host smart-c907d7c2-f085-4f17-9db4-ce1b2521f973
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096054835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.4096054835
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.3661208607
Short name T335
Test name
Test status
Simulation time 852985216 ps
CPU time 13.51 seconds
Started May 09 12:52:05 PM PDT 24
Finished May 09 12:52:21 PM PDT 24
Peak memory 212236 kb
Host smart-74b20890-a754-4f97-980b-5db93e4ebef1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661208607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.3661208607
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.3555550942
Short name T914
Test name
Test status
Simulation time 47102079071 ps
CPU time 689.14 seconds
Started May 09 12:52:04 PM PDT 24
Finished May 09 01:03:37 PM PDT 24
Peak memory 4821952 kb
Host smart-c0b927d3-f508-40c0-849e-9fa400ab9caa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555550942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.3555550942
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.3831452129
Short name T264
Test name
Test status
Simulation time 6298244634 ps
CPU time 14.28 seconds
Started May 09 12:52:01 PM PDT 24
Finished May 09 12:52:17 PM PDT 24
Peak memory 313268 kb
Host smart-bea5f8ce-0acc-4d8c-bb27-8395f9adfcd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831452129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.3831452129
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.1088398453
Short name T1247
Test name
Test status
Simulation time 4455993802 ps
CPU time 6.15 seconds
Started May 09 12:52:14 PM PDT 24
Finished May 09 12:52:23 PM PDT 24
Peak memory 212976 kb
Host smart-e623384c-fbbc-4295-8523-1da01cbc07c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088398453 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.1088398453
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.184727087
Short name T647
Test name
Test status
Simulation time 16150523 ps
CPU time 0.64 seconds
Started May 09 12:52:15 PM PDT 24
Finished May 09 12:52:19 PM PDT 24
Peak memory 204232 kb
Host smart-e1df1c63-38f0-4a74-8f4e-6d1b902ace7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184727087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.184727087
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.4024305959
Short name T1259
Test name
Test status
Simulation time 607682388 ps
CPU time 1.55 seconds
Started May 09 12:52:16 PM PDT 24
Finished May 09 12:52:21 PM PDT 24
Peak memory 212772 kb
Host smart-5d9cab38-6be2-4cf4-84b6-8ad96396b4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024305959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.4024305959
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.718174855
Short name T285
Test name
Test status
Simulation time 492409273 ps
CPU time 12.65 seconds
Started May 09 12:52:17 PM PDT 24
Finished May 09 12:52:33 PM PDT 24
Peak memory 241600 kb
Host smart-79954fab-9ce2-4b9f-bb2e-737507ae8375
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718174855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empt
y.718174855
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1728778165
Short name T1210
Test name
Test status
Simulation time 3374255348 ps
CPU time 45.01 seconds
Started May 09 12:52:13 PM PDT 24
Finished May 09 12:53:01 PM PDT 24
Peak memory 538092 kb
Host smart-83f8f16e-eda6-4b4a-82c9-61078b349a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728778165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1728778165
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.1597874845
Short name T889
Test name
Test status
Simulation time 2327576531 ps
CPU time 71.69 seconds
Started May 09 12:52:14 PM PDT 24
Finished May 09 12:53:29 PM PDT 24
Peak memory 767008 kb
Host smart-12289163-d8ea-481e-bf8b-109c75bd925e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597874845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1597874845
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.51433766
Short name T385
Test name
Test status
Simulation time 1137921954 ps
CPU time 0.86 seconds
Started May 09 12:52:14 PM PDT 24
Finished May 09 12:52:18 PM PDT 24
Peak memory 204196 kb
Host smart-64cb6db9-a2c9-47ae-8b0d-7e50ce094c61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51433766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fmt
.51433766
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.4010035724
Short name T833
Test name
Test status
Simulation time 229183073 ps
CPU time 4.43 seconds
Started May 09 12:52:15 PM PDT 24
Finished May 09 12:52:22 PM PDT 24
Peak memory 204496 kb
Host smart-431f1be5-779c-420f-8b60-42eefcc64c54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010035724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.4010035724
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.815187427
Short name T103
Test name
Test status
Simulation time 7045942612 ps
CPU time 84.31 seconds
Started May 09 12:52:14 PM PDT 24
Finished May 09 12:53:41 PM PDT 24
Peak memory 1047096 kb
Host smart-4679e0de-a2b4-4011-bd16-a2167547a27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815187427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.815187427
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.3456614743
Short name T968
Test name
Test status
Simulation time 691454076 ps
CPU time 2.48 seconds
Started May 09 12:52:23 PM PDT 24
Finished May 09 12:52:28 PM PDT 24
Peak memory 204428 kb
Host smart-05a5b18b-f072-4601-bc54-7742d7468663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456614743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.3456614743
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.2153629174
Short name T42
Test name
Test status
Simulation time 6275156289 ps
CPU time 75.99 seconds
Started May 09 12:52:14 PM PDT 24
Finished May 09 12:53:33 PM PDT 24
Peak memory 326156 kb
Host smart-d5787133-b361-4e30-a420-928e93d34a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153629174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.2153629174
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.979482399
Short name T116
Test name
Test status
Simulation time 19671882 ps
CPU time 0.65 seconds
Started May 09 12:52:24 PM PDT 24
Finished May 09 12:52:28 PM PDT 24
Peak memory 204192 kb
Host smart-09f9fda6-cdb8-46a4-b857-a6751d574796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979482399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.979482399
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.1481210368
Short name T520
Test name
Test status
Simulation time 1615126315 ps
CPU time 9.57 seconds
Started May 09 12:52:12 PM PDT 24
Finished May 09 12:52:24 PM PDT 24
Peak memory 220540 kb
Host smart-13669f8b-a7a9-4831-9934-598603947b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481210368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.1481210368
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.1945806056
Short name T1127
Test name
Test status
Simulation time 1780792857 ps
CPU time 36.77 seconds
Started May 09 12:52:13 PM PDT 24
Finished May 09 12:52:52 PM PDT 24
Peak memory 349460 kb
Host smart-aca80d2f-2cdb-4f3a-b028-f973f4fbaada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945806056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.1945806056
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.1028682491
Short name T415
Test name
Test status
Simulation time 12057973199 ps
CPU time 32.21 seconds
Started May 09 12:52:14 PM PDT 24
Finished May 09 12:52:48 PM PDT 24
Peak memory 212724 kb
Host smart-f337eee3-b8bc-4124-bf55-f98634fcc070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028682491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.1028682491
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.4290304458
Short name T27
Test name
Test status
Simulation time 771762013 ps
CPU time 3.9 seconds
Started May 09 12:52:13 PM PDT 24
Finished May 09 12:52:19 PM PDT 24
Peak memory 204336 kb
Host smart-99adcc86-d93f-4837-94d8-a2180fcca4df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290304458 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.4290304458
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.754735023
Short name T649
Test name
Test status
Simulation time 10542670051 ps
CPU time 4.94 seconds
Started May 09 12:52:13 PM PDT 24
Finished May 09 12:52:20 PM PDT 24
Peak memory 223476 kb
Host smart-1a6c4dd5-9c39-4dc5-ab0e-6979c244bd19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754735023 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_acq.754735023
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.3850699646
Short name T613
Test name
Test status
Simulation time 10077553539 ps
CPU time 77.73 seconds
Started May 09 12:52:18 PM PDT 24
Finished May 09 12:53:39 PM PDT 24
Peak memory 529104 kb
Host smart-bf5e97ca-3fa5-4cb0-ad52-b43dff9fb97a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850699646 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.3850699646
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.342905084
Short name T862
Test name
Test status
Simulation time 256039108 ps
CPU time 1.94 seconds
Started May 09 12:52:14 PM PDT 24
Finished May 09 12:52:19 PM PDT 24
Peak memory 204364 kb
Host smart-346cd0e4-7563-4001-9ea4-5becc01ed359
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342905084 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.i2c_target_hrst.342905084
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.241768839
Short name T849
Test name
Test status
Simulation time 1598801758 ps
CPU time 4.76 seconds
Started May 09 12:52:15 PM PDT 24
Finished May 09 12:52:23 PM PDT 24
Peak memory 204312 kb
Host smart-b94557af-9551-4592-96fc-767e0183997a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241768839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_intr_smoke.241768839
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.1103604011
Short name T950
Test name
Test status
Simulation time 3083214178 ps
CPU time 25.65 seconds
Started May 09 12:52:15 PM PDT 24
Finished May 09 12:52:43 PM PDT 24
Peak memory 891424 kb
Host smart-c393163d-7c62-4f25-b59e-37cfd0f9dba6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103604011 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.1103604011
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.967511464
Short name T1312
Test name
Test status
Simulation time 1627027128 ps
CPU time 31.04 seconds
Started May 09 12:52:24 PM PDT 24
Finished May 09 12:52:58 PM PDT 24
Peak memory 204432 kb
Host smart-fe3dfdde-bda6-4a4a-bc78-16b9759e9e44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967511464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_tar
get_smoke.967511464
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.769221414
Short name T847
Test name
Test status
Simulation time 842593945 ps
CPU time 6.45 seconds
Started May 09 12:52:25 PM PDT 24
Finished May 09 12:52:34 PM PDT 24
Peak memory 206232 kb
Host smart-0f93d03e-f623-4b35-866f-dc746d4e7f65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769221414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_rd.769221414
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.890420769
Short name T578
Test name
Test status
Simulation time 39281055081 ps
CPU time 609.46 seconds
Started May 09 12:52:16 PM PDT 24
Finished May 09 01:02:30 PM PDT 24
Peak memory 4890316 kb
Host smart-8332a7c5-0820-4e30-9f26-35d5aaafab5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890420769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_wr.890420769
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.4003607982
Short name T929
Test name
Test status
Simulation time 16573107995 ps
CPU time 795.83 seconds
Started May 09 12:52:20 PM PDT 24
Finished May 09 01:05:39 PM PDT 24
Peak memory 4068884 kb
Host smart-cb3873e8-7715-4091-a7c7-6e07c3496c1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003607982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.4003607982
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.2965098867
Short name T582
Test name
Test status
Simulation time 6194888402 ps
CPU time 7.45 seconds
Started May 09 12:52:15 PM PDT 24
Finished May 09 12:52:25 PM PDT 24
Peak memory 220736 kb
Host smart-154cfeb3-d49f-42a9-9edf-3facae276949
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965098867 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.2965098867
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.3148059743
Short name T819
Test name
Test status
Simulation time 17508057 ps
CPU time 0.61 seconds
Started May 09 12:52:26 PM PDT 24
Finished May 09 12:52:30 PM PDT 24
Peak memory 204204 kb
Host smart-55c52e45-6478-4a1e-8dd4-287f57449962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148059743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.3148059743
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.1352933713
Short name T906
Test name
Test status
Simulation time 53411094 ps
CPU time 1.18 seconds
Started May 09 12:52:26 PM PDT 24
Finished May 09 12:52:30 PM PDT 24
Peak memory 212708 kb
Host smart-21c4df01-7a8a-4e22-97dc-5b5a8042677a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352933713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.1352933713
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3104314502
Short name T86
Test name
Test status
Simulation time 1506496272 ps
CPU time 19.48 seconds
Started May 09 12:52:13 PM PDT 24
Finished May 09 12:52:34 PM PDT 24
Peak memory 282292 kb
Host smart-fc90e18b-0438-43e0-b153-1de60b81747b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104314502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3104314502
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.669220819
Short name T54
Test name
Test status
Simulation time 5152432258 ps
CPU time 36.35 seconds
Started May 09 12:52:25 PM PDT 24
Finished May 09 12:53:05 PM PDT 24
Peak memory 456232 kb
Host smart-ecdc18b2-0b22-4b5a-89df-3edc5977e11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669220819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.669220819
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.1093512811
Short name T1066
Test name
Test status
Simulation time 1288009001 ps
CPU time 34.93 seconds
Started May 09 12:52:14 PM PDT 24
Finished May 09 12:52:52 PM PDT 24
Peak memory 516980 kb
Host smart-b0422703-edc7-4025-b754-e14fa2227c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093512811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.1093512811
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.2731678938
Short name T860
Test name
Test status
Simulation time 340121771 ps
CPU time 0.85 seconds
Started May 09 12:52:14 PM PDT 24
Finished May 09 12:52:18 PM PDT 24
Peak memory 204140 kb
Host smart-affc2af1-7224-4e6a-b5a4-d0471cbc37ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731678938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.2731678938
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.2419748570
Short name T161
Test name
Test status
Simulation time 1446275098 ps
CPU time 7.53 seconds
Started May 09 12:52:16 PM PDT 24
Finished May 09 12:52:27 PM PDT 24
Peak memory 204436 kb
Host smart-9321b74e-c35e-4089-858c-50939414986b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419748570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.2419748570
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.4230894672
Short name T1005
Test name
Test status
Simulation time 9652580966 ps
CPU time 52.66 seconds
Started May 09 12:52:23 PM PDT 24
Finished May 09 12:53:18 PM PDT 24
Peak memory 779620 kb
Host smart-2d2fe032-8fd5-4425-b6b5-df147f30b422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230894672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.4230894672
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.3822327136
Short name T349
Test name
Test status
Simulation time 7956514312 ps
CPU time 16.67 seconds
Started May 09 12:52:30 PM PDT 24
Finished May 09 12:52:49 PM PDT 24
Peak memory 204348 kb
Host smart-51a5f324-f8a0-4eb0-9a52-cf4f45c04542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822327136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.3822327136
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.1389385629
Short name T367
Test name
Test status
Simulation time 3799075886 ps
CPU time 19.82 seconds
Started May 09 12:52:28 PM PDT 24
Finished May 09 12:52:50 PM PDT 24
Peak memory 358936 kb
Host smart-d445f8e2-2216-4ba2-bb84-c674fd62c42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389385629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.1389385629
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.3662666123
Short name T635
Test name
Test status
Simulation time 31025037 ps
CPU time 0.65 seconds
Started May 09 12:52:12 PM PDT 24
Finished May 09 12:52:14 PM PDT 24
Peak memory 204124 kb
Host smart-7a38a969-79f7-47e7-9aa5-52055c11f068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662666123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.3662666123
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.722772276
Short name T828
Test name
Test status
Simulation time 2671343524 ps
CPU time 34.09 seconds
Started May 09 12:52:28 PM PDT 24
Finished May 09 12:53:04 PM PDT 24
Peak memory 361812 kb
Host smart-6e740a13-c8f7-4a8d-af0d-c1948a1e5bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722772276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.722772276
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2149818793
Short name T905
Test name
Test status
Simulation time 5519619377 ps
CPU time 54.99 seconds
Started May 09 12:52:20 PM PDT 24
Finished May 09 12:53:17 PM PDT 24
Peak memory 303320 kb
Host smart-25994a9a-eff1-4b48-b013-44ee980d1774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149818793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2149818793
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.1125468487
Short name T773
Test name
Test status
Simulation time 7688563237 ps
CPU time 99.25 seconds
Started May 09 12:52:23 PM PDT 24
Finished May 09 12:54:05 PM PDT 24
Peak memory 937900 kb
Host smart-16f99241-09d7-41a0-86f0-7007822b68e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125468487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.1125468487
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.4106659558
Short name T162
Test name
Test status
Simulation time 744394148 ps
CPU time 10.88 seconds
Started May 09 12:52:31 PM PDT 24
Finished May 09 12:52:46 PM PDT 24
Peak memory 228892 kb
Host smart-2c9041aa-efaf-419b-8275-91f17d337abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106659558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.4106659558
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.2854903638
Short name T418
Test name
Test status
Simulation time 2394607793 ps
CPU time 3.44 seconds
Started May 09 12:52:22 PM PDT 24
Finished May 09 12:52:28 PM PDT 24
Peak memory 204484 kb
Host smart-6426673d-f1b6-452c-8737-b378f7a8bc0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854903638 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.2854903638
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.452873057
Short name T137
Test name
Test status
Simulation time 10173013271 ps
CPU time 8.29 seconds
Started May 09 12:52:31 PM PDT 24
Finished May 09 12:52:43 PM PDT 24
Peak memory 239896 kb
Host smart-dda191a0-33a9-4554-b75d-afb2a3344ba6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452873057 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_acq.452873057
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.1248466352
Short name T566
Test name
Test status
Simulation time 10125553590 ps
CPU time 78.13 seconds
Started May 09 12:52:23 PM PDT 24
Finished May 09 12:53:44 PM PDT 24
Peak memory 481112 kb
Host smart-112e4515-3291-4b57-8f5f-0b03599e205a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248466352 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.1248466352
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.1834573827
Short name T533
Test name
Test status
Simulation time 2971540350 ps
CPU time 4.33 seconds
Started May 09 12:52:28 PM PDT 24
Finished May 09 12:52:35 PM PDT 24
Peak memory 207600 kb
Host smart-1e203477-416e-44f9-9bbe-d4b899e93688
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834573827 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.1834573827
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.2719469045
Short name T1225
Test name
Test status
Simulation time 15380993698 ps
CPU time 275.19 seconds
Started May 09 12:52:27 PM PDT 24
Finished May 09 12:57:05 PM PDT 24
Peak memory 3687900 kb
Host smart-8934008b-9ef8-44d7-99fe-77946baab535
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719469045 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.2719469045
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.107595953
Short name T29
Test name
Test status
Simulation time 890254939 ps
CPU time 13.87 seconds
Started May 09 12:52:31 PM PDT 24
Finished May 09 12:52:48 PM PDT 24
Peak memory 204292 kb
Host smart-16694f64-9c90-4527-9090-41c2b7ef3050
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107595953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_tar
get_smoke.107595953
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.925291399
Short name T1180
Test name
Test status
Simulation time 943731399 ps
CPU time 17.76 seconds
Started May 09 12:52:24 PM PDT 24
Finished May 09 12:52:45 PM PDT 24
Peak memory 209772 kb
Host smart-39e2b457-da08-4dcb-a226-91122bc2ffa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925291399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c
_target_stress_rd.925291399
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.2152940509
Short name T499
Test name
Test status
Simulation time 53321862526 ps
CPU time 23.94 seconds
Started May 09 12:52:21 PM PDT 24
Finished May 09 12:52:48 PM PDT 24
Peak memory 490200 kb
Host smart-064bdd47-d453-41bb-ad5a-10805b621d5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152940509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.2152940509
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.2364548790
Short name T786
Test name
Test status
Simulation time 9688646309 ps
CPU time 490.87 seconds
Started May 09 12:52:25 PM PDT 24
Finished May 09 01:00:39 PM PDT 24
Peak memory 1645252 kb
Host smart-b2a6f789-e1cd-401c-b37f-cfce665c1a96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364548790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.2364548790
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.1161088285
Short name T568
Test name
Test status
Simulation time 3465374125 ps
CPU time 8.27 seconds
Started May 09 12:52:23 PM PDT 24
Finished May 09 12:52:33 PM PDT 24
Peak memory 220840 kb
Host smart-ccbfc6ea-2fc9-4d56-a039-4f5e3aae51ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161088285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.1161088285
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.1420135860
Short name T1222
Test name
Test status
Simulation time 36381346 ps
CPU time 0.63 seconds
Started May 09 12:52:32 PM PDT 24
Finished May 09 12:52:36 PM PDT 24
Peak memory 204232 kb
Host smart-090a999c-a9d1-4b77-812f-54f4c1d81f24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420135860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.1420135860
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.1895100921
Short name T46
Test name
Test status
Simulation time 137631140 ps
CPU time 1.62 seconds
Started May 09 12:52:32 PM PDT 24
Finished May 09 12:52:37 PM PDT 24
Peak memory 212676 kb
Host smart-89f04706-7c41-45d1-8ed4-9516bb4871bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895100921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.1895100921
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.1257273472
Short name T354
Test name
Test status
Simulation time 936947028 ps
CPU time 4.4 seconds
Started May 09 12:52:22 PM PDT 24
Finished May 09 12:52:29 PM PDT 24
Peak memory 251352 kb
Host smart-75c992a5-5e33-4009-96da-783244be6fbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257273472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.1257273472
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.3524669198
Short name T660
Test name
Test status
Simulation time 6561547211 ps
CPU time 46.8 seconds
Started May 09 12:52:29 PM PDT 24
Finished May 09 12:53:18 PM PDT 24
Peak memory 612336 kb
Host smart-5622c995-21b4-4634-82b8-ed1c382f7277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524669198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.3524669198
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.69940148
Short name T143
Test name
Test status
Simulation time 12110608379 ps
CPU time 112.36 seconds
Started May 09 12:52:33 PM PDT 24
Finished May 09 12:54:29 PM PDT 24
Peak memory 576244 kb
Host smart-b2797181-4644-4b24-b787-a18c1f0c4d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69940148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.69940148
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.2856084603
Short name T1204
Test name
Test status
Simulation time 467220907 ps
CPU time 1.1 seconds
Started May 09 12:52:24 PM PDT 24
Finished May 09 12:52:28 PM PDT 24
Peak memory 204336 kb
Host smart-04add898-f3b5-461f-9849-ff8e1fca288a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856084603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.2856084603
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.2941052516
Short name T665
Test name
Test status
Simulation time 1131224871 ps
CPU time 7.33 seconds
Started May 09 12:52:26 PM PDT 24
Finished May 09 12:52:36 PM PDT 24
Peak memory 224356 kb
Host smart-79c4277e-d21e-4de8-a742-de9d5b315be4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941052516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.2941052516
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.4225663726
Short name T223
Test name
Test status
Simulation time 16359624284 ps
CPU time 112.61 seconds
Started May 09 12:52:27 PM PDT 24
Finished May 09 12:54:22 PM PDT 24
Peak memory 1047872 kb
Host smart-7a30fa3b-0857-49ec-8f00-095739044410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225663726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.4225663726
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.3375707974
Short name T960
Test name
Test status
Simulation time 455866854 ps
CPU time 17.93 seconds
Started May 09 12:52:32 PM PDT 24
Finished May 09 12:52:54 PM PDT 24
Peak memory 204492 kb
Host smart-e6380db2-ec0b-4e63-8553-debc3c106033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375707974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.3375707974
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.1414357283
Short name T1266
Test name
Test status
Simulation time 3928624076 ps
CPU time 93.23 seconds
Started May 09 12:52:33 PM PDT 24
Finished May 09 12:54:10 PM PDT 24
Peak memory 387576 kb
Host smart-b25f5a3e-5181-4d8e-aa7c-f0c437850429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414357283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.1414357283
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.1625831010
Short name T991
Test name
Test status
Simulation time 43413539 ps
CPU time 0.65 seconds
Started May 09 12:52:23 PM PDT 24
Finished May 09 12:52:27 PM PDT 24
Peak memory 204132 kb
Host smart-5bcd3ad7-8141-4b94-9801-0259d79f99ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625831010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1625831010
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.2675970184
Short name T1011
Test name
Test status
Simulation time 6773790363 ps
CPU time 15.28 seconds
Started May 09 12:52:23 PM PDT 24
Finished May 09 12:52:40 PM PDT 24
Peak memory 212728 kb
Host smart-3261d8c0-e763-45f9-8b2c-272f26ccc5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675970184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.2675970184
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.2843299164
Short name T331
Test name
Test status
Simulation time 1383729994 ps
CPU time 68.94 seconds
Started May 09 12:52:25 PM PDT 24
Finished May 09 12:53:37 PM PDT 24
Peak memory 351648 kb
Host smart-e0f6c1d3-5ffb-479e-80ed-5f430caa9bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843299164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.2843299164
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.1803863599
Short name T84
Test name
Test status
Simulation time 139329807741 ps
CPU time 3239.16 seconds
Started May 09 12:52:23 PM PDT 24
Finished May 09 01:46:25 PM PDT 24
Peak memory 1548140 kb
Host smart-93c2f84f-b3f2-4e23-a413-e35ebc36eff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803863599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.1803863599
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.417035836
Short name T853
Test name
Test status
Simulation time 1898071635 ps
CPU time 9.12 seconds
Started May 09 12:52:27 PM PDT 24
Finished May 09 12:52:39 PM PDT 24
Peak memory 212664 kb
Host smart-73396a6c-7cdb-40e6-862e-a57cd828789b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417035836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.417035836
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.762538714
Short name T861
Test name
Test status
Simulation time 702770043 ps
CPU time 3.47 seconds
Started May 09 12:52:34 PM PDT 24
Finished May 09 12:52:41 PM PDT 24
Peak memory 204388 kb
Host smart-a58dabe7-5af2-4b10-be8c-e74685998c46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762538714 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.762538714
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.1723147346
Short name T488
Test name
Test status
Simulation time 10524342912 ps
CPU time 4.69 seconds
Started May 09 12:52:35 PM PDT 24
Finished May 09 12:52:43 PM PDT 24
Peak memory 211056 kb
Host smart-3e2c1c25-b86e-4f46-84c5-e99b5750de92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723147346 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.1723147346
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.4106713646
Short name T1015
Test name
Test status
Simulation time 10102812954 ps
CPU time 71.12 seconds
Started May 09 12:52:32 PM PDT 24
Finished May 09 12:53:46 PM PDT 24
Peak memory 480752 kb
Host smart-689ef1fd-f212-4bbe-97ed-b68e8906e6f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106713646 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.4106713646
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.1659347051
Short name T571
Test name
Test status
Simulation time 1304526283 ps
CPU time 2.28 seconds
Started May 09 12:52:38 PM PDT 24
Finished May 09 12:52:43 PM PDT 24
Peak memory 204480 kb
Host smart-33d4bbb0-ee0d-4a2a-ba4c-b89fd940fd89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659347051 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.1659347051
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.207953874
Short name T1272
Test name
Test status
Simulation time 4576427026 ps
CPU time 6.06 seconds
Started May 09 12:52:25 PM PDT 24
Finished May 09 12:52:34 PM PDT 24
Peak memory 211724 kb
Host smart-c70dfe23-da05-4d84-b171-3565ec07c6f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207953874 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_intr_smoke.207953874
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.1639257094
Short name T949
Test name
Test status
Simulation time 20490155522 ps
CPU time 56.42 seconds
Started May 09 12:52:33 PM PDT 24
Finished May 09 12:53:33 PM PDT 24
Peak memory 1190072 kb
Host smart-27ee2ca4-2790-43d8-b7c3-570bc2e71849
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639257094 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.1639257094
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.30505088
Short name T454
Test name
Test status
Simulation time 4907967790 ps
CPU time 16.59 seconds
Started May 09 12:52:29 PM PDT 24
Finished May 09 12:52:48 PM PDT 24
Peak memory 204512 kb
Host smart-63644e30-196e-48d6-81e7-208e83655604
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30505088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_targ
et_smoke.30505088
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.2291550701
Short name T1349
Test name
Test status
Simulation time 6962459551 ps
CPU time 7.49 seconds
Started May 09 12:52:32 PM PDT 24
Finished May 09 12:52:42 PM PDT 24
Peak memory 208560 kb
Host smart-ba900211-c7f2-41d3-8a61-0e485230d4af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291550701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.2291550701
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.3582376624
Short name T1057
Test name
Test status
Simulation time 13893843997 ps
CPU time 27.73 seconds
Started May 09 12:52:25 PM PDT 24
Finished May 09 12:52:56 PM PDT 24
Peak memory 204516 kb
Host smart-4f900036-9b73-40f2-af7c-26029a0d496e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582376624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.3582376624
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.4278001861
Short name T31
Test name
Test status
Simulation time 35582459171 ps
CPU time 306.77 seconds
Started May 09 12:52:23 PM PDT 24
Finished May 09 12:57:32 PM PDT 24
Peak memory 2164144 kb
Host smart-016fd9f8-85a0-4ffd-877e-d99aa4cda212
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278001861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.4278001861
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.2824597279
Short name T1243
Test name
Test status
Simulation time 6125708561 ps
CPU time 8.06 seconds
Started May 09 12:52:35 PM PDT 24
Finished May 09 12:52:47 PM PDT 24
Peak memory 217976 kb
Host smart-d6417abe-62cb-4e1b-9042-f00aaa223020
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824597279 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.2824597279
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.3350946875
Short name T831
Test name
Test status
Simulation time 16505305 ps
CPU time 0.59 seconds
Started May 09 12:46:35 PM PDT 24
Finished May 09 12:46:37 PM PDT 24
Peak memory 204012 kb
Host smart-ddceef86-29a8-492f-930a-65bec0c90f63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350946875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3350946875
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.2166661655
Short name T422
Test name
Test status
Simulation time 106466563 ps
CPU time 1.37 seconds
Started May 09 12:46:35 PM PDT 24
Finished May 09 12:46:39 PM PDT 24
Peak memory 212732 kb
Host smart-aa8fabc0-bee5-42ec-b666-e0b4b81a88dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166661655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2166661655
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.2072029881
Short name T957
Test name
Test status
Simulation time 550110110 ps
CPU time 6.23 seconds
Started May 09 12:46:23 PM PDT 24
Finished May 09 12:46:31 PM PDT 24
Peak memory 257676 kb
Host smart-8ef3a114-ce20-486e-8164-c92da4f2f0fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072029881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.2072029881
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2125200925
Short name T1098
Test name
Test status
Simulation time 7389737585 ps
CPU time 64.25 seconds
Started May 09 12:46:36 PM PDT 24
Finished May 09 12:47:43 PM PDT 24
Peak memory 645176 kb
Host smart-b5a84556-ee29-4bc9-9794-03454161966e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125200925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2125200925
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1018787899
Short name T691
Test name
Test status
Simulation time 3525478432 ps
CPU time 129.64 seconds
Started May 09 12:46:22 PM PDT 24
Finished May 09 12:48:34 PM PDT 24
Peak memory 579856 kb
Host smart-693f26e6-db71-458a-b6e0-7d9868557615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018787899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1018787899
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.703823080
Short name T1303
Test name
Test status
Simulation time 150007841 ps
CPU time 1.14 seconds
Started May 09 12:46:23 PM PDT 24
Finished May 09 12:46:26 PM PDT 24
Peak memory 204480 kb
Host smart-6315fff3-43d4-4503-ae71-7d9af5b73dce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703823080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt
.703823080
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.2673069146
Short name T1178
Test name
Test status
Simulation time 132110452 ps
CPU time 3.45 seconds
Started May 09 12:46:23 PM PDT 24
Finished May 09 12:46:28 PM PDT 24
Peak memory 226200 kb
Host smart-4002f3b4-0161-4c72-a411-f86ca3ee78bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673069146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
2673069146
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.3553027468
Short name T612
Test name
Test status
Simulation time 9225375501 ps
CPU time 64.73 seconds
Started May 09 12:46:22 PM PDT 24
Finished May 09 12:47:29 PM PDT 24
Peak memory 779552 kb
Host smart-f0602af0-c11f-46af-b754-a0703a4c2602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553027468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3553027468
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.3273509336
Short name T1278
Test name
Test status
Simulation time 2440407816 ps
CPU time 15.35 seconds
Started May 09 12:46:35 PM PDT 24
Finished May 09 12:46:52 PM PDT 24
Peak memory 204488 kb
Host smart-fd626cb4-35d6-4252-b91a-134b571fe231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273509336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.3273509336
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.2599839779
Short name T763
Test name
Test status
Simulation time 5749704678 ps
CPU time 18.8 seconds
Started May 09 12:46:33 PM PDT 24
Finished May 09 12:46:53 PM PDT 24
Peak memory 276464 kb
Host smart-39d3df18-abd7-45ff-9811-8c2988800930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599839779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.2599839779
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.3981146293
Short name T122
Test name
Test status
Simulation time 105386224 ps
CPU time 0.7 seconds
Started May 09 12:46:21 PM PDT 24
Finished May 09 12:46:24 PM PDT 24
Peak memory 204056 kb
Host smart-7e114663-0b42-4e1d-b5f8-28fc5818661f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981146293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.3981146293
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.3451976790
Short name T1145
Test name
Test status
Simulation time 5007941374 ps
CPU time 223.27 seconds
Started May 09 12:46:34 PM PDT 24
Finished May 09 12:50:18 PM PDT 24
Peak memory 1377936 kb
Host smart-4c43ca92-074d-483b-b156-958f17009299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451976790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.3451976790
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3812348405
Short name T1130
Test name
Test status
Simulation time 3644727352 ps
CPU time 19.09 seconds
Started May 09 12:46:22 PM PDT 24
Finished May 09 12:46:43 PM PDT 24
Peak memory 296844 kb
Host smart-5517de87-5908-4bef-865c-54b0501d81c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812348405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3812348405
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.694801103
Short name T1338
Test name
Test status
Simulation time 314429034420 ps
CPU time 1316.38 seconds
Started May 09 12:46:34 PM PDT 24
Finished May 09 01:08:32 PM PDT 24
Peak memory 3241024 kb
Host smart-b50e0ce9-7619-412e-88ed-eeadaf5e8961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694801103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.694801103
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.189514426
Short name T339
Test name
Test status
Simulation time 778069051 ps
CPU time 15.48 seconds
Started May 09 12:46:34 PM PDT 24
Finished May 09 12:46:51 PM PDT 24
Peak memory 217612 kb
Host smart-feb45e9f-1200-42a8-aff9-1a16335bda49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189514426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.189514426
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.2582064100
Short name T859
Test name
Test status
Simulation time 777715676 ps
CPU time 3.77 seconds
Started May 09 12:46:36 PM PDT 24
Finished May 09 12:46:42 PM PDT 24
Peak memory 204448 kb
Host smart-a717b41e-5956-433b-a8da-089b8efc9c75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582064100 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2582064100
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.2727668097
Short name T353
Test name
Test status
Simulation time 10080485011 ps
CPU time 67.95 seconds
Started May 09 12:46:36 PM PDT 24
Finished May 09 12:47:46 PM PDT 24
Peak memory 476360 kb
Host smart-5b860c0f-f1be-43f9-8d8c-e245d469f811
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727668097 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.2727668097
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.1963477044
Short name T825
Test name
Test status
Simulation time 10161740282 ps
CPU time 13.13 seconds
Started May 09 12:46:35 PM PDT 24
Finished May 09 12:46:51 PM PDT 24
Peak memory 270808 kb
Host smart-9e2ebe3e-c752-41b0-809b-709a3476743a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963477044 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.1963477044
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.1468036607
Short name T13
Test name
Test status
Simulation time 2858082625 ps
CPU time 2.77 seconds
Started May 09 12:46:34 PM PDT 24
Finished May 09 12:46:38 PM PDT 24
Peak memory 204512 kb
Host smart-b789c3e7-0305-40e5-89e3-fb8a87f1430f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468036607 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.1468036607
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.4167919426
Short name T790
Test name
Test status
Simulation time 5825691342 ps
CPU time 6.65 seconds
Started May 09 12:46:35 PM PDT 24
Finished May 09 12:46:45 PM PDT 24
Peak memory 220664 kb
Host smart-3a834723-f65f-4682-af16-ef71a1d4e346
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167919426 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.4167919426
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.2344140304
Short name T753
Test name
Test status
Simulation time 13864996402 ps
CPU time 134.48 seconds
Started May 09 12:46:36 PM PDT 24
Finished May 09 12:48:53 PM PDT 24
Peak memory 1799340 kb
Host smart-fb11b89e-b7c8-4f07-8c34-3e980b73063d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344140304 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.2344140304
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.3474836822
Short name T1174
Test name
Test status
Simulation time 2022182465 ps
CPU time 8.68 seconds
Started May 09 12:46:36 PM PDT 24
Finished May 09 12:46:47 PM PDT 24
Peak memory 204328 kb
Host smart-736d2bfe-7e93-4bd1-b8ea-05f2d786055a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474836822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.3474836822
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.3425254109
Short name T650
Test name
Test status
Simulation time 1009599250 ps
CPU time 4.21 seconds
Started May 09 12:46:38 PM PDT 24
Finished May 09 12:46:44 PM PDT 24
Peak memory 204216 kb
Host smart-fcd53868-4470-4461-b4ea-feb307306832
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425254109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.3425254109
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.1130196136
Short name T1214
Test name
Test status
Simulation time 40566508422 ps
CPU time 213.31 seconds
Started May 09 12:46:35 PM PDT 24
Finished May 09 12:50:11 PM PDT 24
Peak memory 2631224 kb
Host smart-5672ebaf-031c-4578-adc3-d89e40282551
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130196136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.1130196136
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.1667016402
Short name T677
Test name
Test status
Simulation time 40669925483 ps
CPU time 211.23 seconds
Started May 09 12:46:40 PM PDT 24
Finished May 09 12:50:12 PM PDT 24
Peak memory 1837824 kb
Host smart-02648480-3d78-43ae-8939-7cc53c643b01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667016402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.1667016402
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.2850537541
Short name T882
Test name
Test status
Simulation time 1237359097 ps
CPU time 6.74 seconds
Started May 09 12:46:37 PM PDT 24
Finished May 09 12:46:46 PM PDT 24
Peak memory 218388 kb
Host smart-a2b3acca-7be1-4199-94c2-e10cb4cc6106
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850537541 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.2850537541
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.2697155830
Short name T904
Test name
Test status
Simulation time 48081396 ps
CPU time 0.62 seconds
Started May 09 12:46:35 PM PDT 24
Finished May 09 12:46:38 PM PDT 24
Peak memory 204244 kb
Host smart-58f14114-9d4a-44a5-85a4-4e61d9090c78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697155830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2697155830
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1371370103
Short name T600
Test name
Test status
Simulation time 64842452 ps
CPU time 1.13 seconds
Started May 09 12:46:37 PM PDT 24
Finished May 09 12:46:40 PM PDT 24
Peak memory 215192 kb
Host smart-3516a4a0-eaba-4069-823f-57d7e02f807f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371370103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1371370103
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.1182844211
Short name T976
Test name
Test status
Simulation time 768340576 ps
CPU time 4.84 seconds
Started May 09 12:46:36 PM PDT 24
Finished May 09 12:46:43 PM PDT 24
Peak memory 246708 kb
Host smart-405ec9bd-a68a-4892-91f3-4c78524a1887
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182844211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.1182844211
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.289763866
Short name T1107
Test name
Test status
Simulation time 2662619654 ps
CPU time 37.54 seconds
Started May 09 12:46:37 PM PDT 24
Finished May 09 12:47:17 PM PDT 24
Peak memory 488148 kb
Host smart-c3361be7-9f68-4b81-9e26-68e2da17303a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289763866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.289763866
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.2077249810
Short name T259
Test name
Test status
Simulation time 4798616614 ps
CPU time 29.82 seconds
Started May 09 12:46:38 PM PDT 24
Finished May 09 12:47:10 PM PDT 24
Peak memory 465752 kb
Host smart-8168961a-6c95-4510-a7c9-f2da2b6fe0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077249810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.2077249810
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.846074454
Short name T700
Test name
Test status
Simulation time 166736155 ps
CPU time 1.13 seconds
Started May 09 12:46:33 PM PDT 24
Finished May 09 12:46:36 PM PDT 24
Peak memory 204400 kb
Host smart-a45bda9f-eb79-49f0-b0ef-6f46bcef049b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846074454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt
.846074454
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.1219292247
Short name T1339
Test name
Test status
Simulation time 610876498 ps
CPU time 3.65 seconds
Started May 09 12:46:36 PM PDT 24
Finished May 09 12:46:42 PM PDT 24
Peak memory 204420 kb
Host smart-c6d9878e-e5cb-4d24-b4c5-e041923332d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219292247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
1219292247
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.2442141051
Short name T527
Test name
Test status
Simulation time 4775581796 ps
CPU time 140.34 seconds
Started May 09 12:46:36 PM PDT 24
Finished May 09 12:48:59 PM PDT 24
Peak memory 696468 kb
Host smart-caabd707-7612-489a-a19e-8c40e5fe8c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442141051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2442141051
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.173674646
Short name T301
Test name
Test status
Simulation time 182156074 ps
CPU time 7.45 seconds
Started May 09 12:46:35 PM PDT 24
Finished May 09 12:46:44 PM PDT 24
Peak memory 204464 kb
Host smart-5982b846-2dd6-416f-a80a-e0c7635a3d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173674646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.173674646
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.1653279542
Short name T475
Test name
Test status
Simulation time 1304788395 ps
CPU time 20.71 seconds
Started May 09 12:46:35 PM PDT 24
Finished May 09 12:46:59 PM PDT 24
Peak memory 304076 kb
Host smart-3bfb17c7-a340-4459-8a61-76421ad89eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653279542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.1653279542
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.2551770981
Short name T1044
Test name
Test status
Simulation time 27737178 ps
CPU time 0.65 seconds
Started May 09 12:46:39 PM PDT 24
Finished May 09 12:46:41 PM PDT 24
Peak memory 204140 kb
Host smart-880ccd76-755e-46e8-8796-a8cf3eb17e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551770981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.2551770981
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.600863032
Short name T37
Test name
Test status
Simulation time 1866738171 ps
CPU time 20.21 seconds
Started May 09 12:46:37 PM PDT 24
Finished May 09 12:46:59 PM PDT 24
Peak memory 243496 kb
Host smart-92d53946-c3f7-4124-8425-1515f58a7440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600863032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.600863032
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1080398088
Short name T465
Test name
Test status
Simulation time 3242283051 ps
CPU time 12.62 seconds
Started May 09 12:46:33 PM PDT 24
Finished May 09 12:46:48 PM PDT 24
Peak memory 268144 kb
Host smart-328ed62a-dacd-4b12-ac4b-7fda301b6781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080398088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1080398088
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.3872886906
Short name T1050
Test name
Test status
Simulation time 21151352403 ps
CPU time 503.93 seconds
Started May 09 12:46:35 PM PDT 24
Finished May 09 12:55:02 PM PDT 24
Peak memory 2312076 kb
Host smart-b6b2cf73-af6a-4054-81d3-e4a6eb79ea07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872886906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.3872886906
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.1177875253
Short name T634
Test name
Test status
Simulation time 1246080325 ps
CPU time 11.98 seconds
Started May 09 12:46:33 PM PDT 24
Finished May 09 12:46:46 PM PDT 24
Peak memory 215876 kb
Host smart-a1d2e4da-6b97-4023-945b-062bfa422dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177875253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1177875253
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.1220245798
Short name T1096
Test name
Test status
Simulation time 2029261552 ps
CPU time 3.13 seconds
Started May 09 12:46:40 PM PDT 24
Finished May 09 12:46:44 PM PDT 24
Peak memory 204468 kb
Host smart-f341c30f-2719-46b7-a6f3-0431d9838dde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220245798 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.1220245798
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.555204900
Short name T138
Test name
Test status
Simulation time 10565748164 ps
CPU time 6.42 seconds
Started May 09 12:46:34 PM PDT 24
Finished May 09 12:46:41 PM PDT 24
Peak memory 232420 kb
Host smart-20cf15d4-8eda-4d75-bf9f-ba7c8e8a11c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555204900 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_acq.555204900
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.1410312851
Short name T815
Test name
Test status
Simulation time 10410617854 ps
CPU time 14.6 seconds
Started May 09 12:46:48 PM PDT 24
Finished May 09 12:47:04 PM PDT 24
Peak memory 283216 kb
Host smart-4e56b007-3e5a-44f9-bbb4-8ac3c4cf0179
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410312851 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.1410312851
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.1707928178
Short name T427
Test name
Test status
Simulation time 468272734 ps
CPU time 2.61 seconds
Started May 09 12:46:39 PM PDT 24
Finished May 09 12:46:43 PM PDT 24
Peak memory 204488 kb
Host smart-1333e486-e415-4fce-b750-5c8e9d8f387b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707928178 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.1707928178
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.2330208825
Short name T251
Test name
Test status
Simulation time 3530196991 ps
CPU time 5.17 seconds
Started May 09 12:46:38 PM PDT 24
Finished May 09 12:46:45 PM PDT 24
Peak memory 212460 kb
Host smart-d6dca001-59f6-4830-a3d5-077b4a1e5661
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330208825 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.2330208825
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.3719386698
Short name T275
Test name
Test status
Simulation time 18093348169 ps
CPU time 6.93 seconds
Started May 09 12:46:35 PM PDT 24
Finished May 09 12:46:45 PM PDT 24
Peak memory 204416 kb
Host smart-b83c3d79-2c1a-4af6-b298-a3a51d1cc630
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719386698 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.3719386698
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.3222215066
Short name T792
Test name
Test status
Simulation time 1106192143 ps
CPU time 15.19 seconds
Started May 09 12:46:35 PM PDT 24
Finished May 09 12:46:52 PM PDT 24
Peak memory 204360 kb
Host smart-9b3fde5e-1bc9-4f80-b7e3-b7834b3a96de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222215066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.3222215066
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.1039389655
Short name T1159
Test name
Test status
Simulation time 11653781866 ps
CPU time 50.5 seconds
Started May 09 12:46:34 PM PDT 24
Finished May 09 12:47:26 PM PDT 24
Peak memory 209184 kb
Host smart-0eae9de5-6258-453b-8886-b0635414c8eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039389655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.1039389655
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.1584171903
Short name T288
Test name
Test status
Simulation time 13550513624 ps
CPU time 53.19 seconds
Started May 09 12:46:34 PM PDT 24
Finished May 09 12:47:29 PM PDT 24
Peak memory 744980 kb
Host smart-46d4a87b-990a-4e0a-a549-475374d74f58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584171903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.1584171903
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.3456188247
Short name T1331
Test name
Test status
Simulation time 1342297009 ps
CPU time 6.39 seconds
Started May 09 12:46:39 PM PDT 24
Finished May 09 12:46:47 PM PDT 24
Peak memory 216772 kb
Host smart-35a4df00-7be7-4748-9f43-8608351916b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456188247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.3456188247
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.2220291597
Short name T746
Test name
Test status
Simulation time 196937264 ps
CPU time 0.59 seconds
Started May 09 12:46:58 PM PDT 24
Finished May 09 12:47:00 PM PDT 24
Peak memory 204228 kb
Host smart-6caa3f71-2e92-4123-bffc-df95054a63a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220291597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2220291597
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.3911137650
Short name T778
Test name
Test status
Simulation time 169270997 ps
CPU time 1.97 seconds
Started May 09 12:46:46 PM PDT 24
Finished May 09 12:46:49 PM PDT 24
Peak memory 212764 kb
Host smart-a5d03a6b-3c61-4bd3-abd4-11ebee2ac1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911137650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.3911137650
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.512857597
Short name T1149
Test name
Test status
Simulation time 262763406 ps
CPU time 5.46 seconds
Started May 09 12:46:46 PM PDT 24
Finished May 09 12:46:53 PM PDT 24
Peak memory 254652 kb
Host smart-a6ed39a6-2fb1-403b-8be2-7ebe41607fd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512857597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.512857597
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.21077947
Short name T494
Test name
Test status
Simulation time 9220345251 ps
CPU time 58.06 seconds
Started May 09 12:46:45 PM PDT 24
Finished May 09 12:47:45 PM PDT 24
Peak memory 618808 kb
Host smart-3de333cc-3a42-4875-a09c-066368b1b8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21077947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.21077947
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.3146642560
Short name T393
Test name
Test status
Simulation time 5520182628 ps
CPU time 42.89 seconds
Started May 09 12:46:45 PM PDT 24
Finished May 09 12:47:29 PM PDT 24
Peak memory 506564 kb
Host smart-7b1185a9-82c1-46ce-b1d0-21975250cdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146642560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.3146642560
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.180091870
Short name T639
Test name
Test status
Simulation time 540437065 ps
CPU time 1.02 seconds
Started May 09 12:46:48 PM PDT 24
Finished May 09 12:46:51 PM PDT 24
Peak memory 204424 kb
Host smart-b2afe9cb-2bff-4520-a24f-8395f61f5e28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180091870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt
.180091870
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.623128443
Short name T1244
Test name
Test status
Simulation time 168442728 ps
CPU time 9.27 seconds
Started May 09 12:46:49 PM PDT 24
Finished May 09 12:47:00 PM PDT 24
Peak memory 233628 kb
Host smart-87414861-d5c2-41b7-b85b-181e30228c16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623128443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.623128443
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.2742707356
Short name T1010
Test name
Test status
Simulation time 4310807225 ps
CPU time 352.96 seconds
Started May 09 12:46:58 PM PDT 24
Finished May 09 12:52:53 PM PDT 24
Peak memory 1220824 kb
Host smart-3abae0c2-3d33-41c1-9ece-c7e9da5f331d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742707356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.2742707356
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.4169348382
Short name T1358
Test name
Test status
Simulation time 1960744193 ps
CPU time 6.33 seconds
Started May 09 12:46:51 PM PDT 24
Finished May 09 12:46:59 PM PDT 24
Peak memory 204324 kb
Host smart-dbb41475-1b34-4b36-80be-4abb110638da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169348382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.4169348382
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.591642845
Short name T1036
Test name
Test status
Simulation time 1382271106 ps
CPU time 65.45 seconds
Started May 09 12:46:47 PM PDT 24
Finished May 09 12:47:54 PM PDT 24
Peak memory 424060 kb
Host smart-f5f8e224-5f7e-4e88-acc4-5139d856a9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591642845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.591642845
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.3856502136
Short name T827
Test name
Test status
Simulation time 30149023 ps
CPU time 0.69 seconds
Started May 09 12:46:35 PM PDT 24
Finished May 09 12:46:37 PM PDT 24
Peak memory 204092 kb
Host smart-9e6aff02-4a33-48f6-9cbf-a6b6779dcd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856502136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.3856502136
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.3662278983
Short name T69
Test name
Test status
Simulation time 6631507799 ps
CPU time 62.49 seconds
Started May 09 12:46:58 PM PDT 24
Finished May 09 12:48:02 PM PDT 24
Peak memory 462492 kb
Host smart-39abe12b-b812-422b-9dba-d48cb9fd183d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662278983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.3662278983
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.266660864
Short name T435
Test name
Test status
Simulation time 1588274174 ps
CPU time 82.24 seconds
Started May 09 12:46:36 PM PDT 24
Finished May 09 12:48:01 PM PDT 24
Peak memory 382936 kb
Host smart-5c19cc1f-2392-49f8-be94-4470230d93c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266660864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.266660864
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.2919313474
Short name T245
Test name
Test status
Simulation time 61494987366 ps
CPU time 1132.47 seconds
Started May 09 12:46:49 PM PDT 24
Finished May 09 01:05:44 PM PDT 24
Peak memory 1892760 kb
Host smart-ad058f9d-4d2c-4ddc-a27a-266c7d418788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919313474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.2919313474
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.154480386
Short name T1086
Test name
Test status
Simulation time 4953674567 ps
CPU time 40.17 seconds
Started May 09 12:46:45 PM PDT 24
Finished May 09 12:47:26 PM PDT 24
Peak memory 212696 kb
Host smart-657099d1-ae59-4361-99d4-9f83a96c1cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154480386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.154480386
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.3193961614
Short name T1230
Test name
Test status
Simulation time 1458114466 ps
CPU time 3.83 seconds
Started May 09 12:46:47 PM PDT 24
Finished May 09 12:46:52 PM PDT 24
Peak memory 204436 kb
Host smart-8ab408db-6f45-4ed0-b2ac-99266493b6a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193961614 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3193961614
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2511026189
Short name T973
Test name
Test status
Simulation time 10096361860 ps
CPU time 74.53 seconds
Started May 09 12:46:57 PM PDT 24
Finished May 09 12:48:13 PM PDT 24
Peak memory 542652 kb
Host smart-95b630ae-5820-4616-afc4-8e2dc9474f51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511026189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2511026189
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.3942889180
Short name T780
Test name
Test status
Simulation time 10127405578 ps
CPU time 15.79 seconds
Started May 09 12:46:47 PM PDT 24
Finished May 09 12:47:04 PM PDT 24
Peak memory 302512 kb
Host smart-175e6972-e9dd-42f8-aa4b-3573d1807bc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942889180 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.3942889180
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.3713105687
Short name T1033
Test name
Test status
Simulation time 906914943 ps
CPU time 2.94 seconds
Started May 09 12:46:59 PM PDT 24
Finished May 09 12:47:03 PM PDT 24
Peak memory 204492 kb
Host smart-b0095db1-4b4b-473a-9ba3-0eadb66ae311
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713105687 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.3713105687
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1031138141
Short name T955
Test name
Test status
Simulation time 19659689359 ps
CPU time 5.27 seconds
Started May 09 12:46:46 PM PDT 24
Finished May 09 12:46:52 PM PDT 24
Peak memory 211520 kb
Host smart-5283f481-458f-40db-958d-0d4c54a0df34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031138141 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1031138141
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.2525383584
Short name T521
Test name
Test status
Simulation time 9959050969 ps
CPU time 30.28 seconds
Started May 09 12:46:52 PM PDT 24
Finished May 09 12:47:24 PM PDT 24
Peak memory 841064 kb
Host smart-3545e59c-11f6-465e-a467-6335294af7cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525383584 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.2525383584
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.898026538
Short name T837
Test name
Test status
Simulation time 1186491682 ps
CPU time 19.05 seconds
Started May 09 12:46:47 PM PDT 24
Finished May 09 12:47:07 PM PDT 24
Peak memory 204336 kb
Host smart-d1d91448-40d6-4724-97b5-abf2ce35e2b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898026538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_targ
et_smoke.898026538
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.2050096150
Short name T1190
Test name
Test status
Simulation time 3513143364 ps
CPU time 14.99 seconds
Started May 09 12:46:49 PM PDT 24
Finished May 09 12:47:05 PM PDT 24
Peak memory 215080 kb
Host smart-34d50640-81d4-4172-99ed-a131a5a16a5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050096150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.2050096150
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.3709455
Short name T467
Test name
Test status
Simulation time 49492505497 ps
CPU time 1179.47 seconds
Started May 09 12:46:57 PM PDT 24
Finished May 09 01:06:38 PM PDT 24
Peak memory 7545724 kb
Host smart-22b409da-5c7d-4c2e-aa15-4e0264d7e7ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_ta
rget_stress_wr.3709455
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.4148956259
Short name T497
Test name
Test status
Simulation time 27942385588 ps
CPU time 1775.71 seconds
Started May 09 12:46:46 PM PDT 24
Finished May 09 01:16:23 PM PDT 24
Peak memory 3384408 kb
Host smart-352a9a73-c7fe-4863-8c54-e01522a3b059
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148956259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.4148956259
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.3142206831
Short name T514
Test name
Test status
Simulation time 6193776354 ps
CPU time 7.34 seconds
Started May 09 12:46:47 PM PDT 24
Finished May 09 12:46:56 PM PDT 24
Peak memory 219264 kb
Host smart-c5483804-61d8-46ee-813f-85453abfec31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142206831 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.3142206831
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.1789319947
Short name T459
Test name
Test status
Simulation time 18825210 ps
CPU time 0.65 seconds
Started May 09 12:47:02 PM PDT 24
Finished May 09 12:47:05 PM PDT 24
Peak memory 204232 kb
Host smart-6b493ca2-f011-454d-814a-97f61fdc6662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789319947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.1789319947
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.103454860
Short name T1311
Test name
Test status
Simulation time 160417803 ps
CPU time 1.47 seconds
Started May 09 12:46:50 PM PDT 24
Finished May 09 12:46:54 PM PDT 24
Peak memory 216120 kb
Host smart-a9200e62-29ad-4cc8-9d7c-45be82c1307f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103454860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.103454860
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.579216331
Short name T1161
Test name
Test status
Simulation time 853831851 ps
CPU time 4.94 seconds
Started May 09 12:46:46 PM PDT 24
Finished May 09 12:46:53 PM PDT 24
Peak memory 244888 kb
Host smart-a2d36304-3581-4338-943d-bc65cd8ae1e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579216331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty
.579216331
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.2685731342
Short name T619
Test name
Test status
Simulation time 5690311456 ps
CPU time 95.73 seconds
Started May 09 12:46:48 PM PDT 24
Finished May 09 12:48:26 PM PDT 24
Peak memory 545584 kb
Host smart-e2f6da0f-c1f6-4036-82b8-dd8f4c6530ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685731342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2685731342
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.1122170726
Short name T966
Test name
Test status
Simulation time 19004020536 ps
CPU time 98.43 seconds
Started May 09 12:46:50 PM PDT 24
Finished May 09 12:48:30 PM PDT 24
Peak memory 484684 kb
Host smart-aab10263-b5dd-400d-9750-175811ad714b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122170726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.1122170726
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.2489414605
Short name T567
Test name
Test status
Simulation time 334439931 ps
CPU time 1.06 seconds
Started May 09 12:46:49 PM PDT 24
Finished May 09 12:46:53 PM PDT 24
Peak memory 204392 kb
Host smart-59d0555c-2cbc-4691-87b8-c5e11e3df955
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489414605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.2489414605
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.2815519897
Short name T302
Test name
Test status
Simulation time 559399627 ps
CPU time 3.38 seconds
Started May 09 12:46:47 PM PDT 24
Finished May 09 12:46:52 PM PDT 24
Peak memory 204428 kb
Host smart-17af4deb-26ee-4523-bd44-79202a38e224
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815519897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
2815519897
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.2415725698
Short name T1351
Test name
Test status
Simulation time 2108737160 ps
CPU time 131.67 seconds
Started May 09 12:46:57 PM PDT 24
Finished May 09 12:49:10 PM PDT 24
Peak memory 702568 kb
Host smart-ae3d560c-badd-47b0-8a47-f0039b3de666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415725698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.2415725698
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.2461289641
Short name T1100
Test name
Test status
Simulation time 1965506631 ps
CPU time 20.7 seconds
Started May 09 12:46:59 PM PDT 24
Finished May 09 12:47:21 PM PDT 24
Peak memory 204456 kb
Host smart-2789322c-4c17-46b3-bf35-a57346187730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461289641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2461289641
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.3813721635
Short name T1073
Test name
Test status
Simulation time 4694378451 ps
CPU time 84.58 seconds
Started May 09 12:47:01 PM PDT 24
Finished May 09 12:48:28 PM PDT 24
Peak memory 318216 kb
Host smart-25b19a5c-acea-47c7-933d-05154e4349c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813721635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.3813721635
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.3792426933
Short name T43
Test name
Test status
Simulation time 51338866 ps
CPU time 0.67 seconds
Started May 09 12:46:47 PM PDT 24
Finished May 09 12:46:49 PM PDT 24
Peak memory 204144 kb
Host smart-1c31106f-6d3f-45f5-9200-302987c9076f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792426933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.3792426933
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.2765124537
Short name T1218
Test name
Test status
Simulation time 596541346 ps
CPU time 24.29 seconds
Started May 09 12:46:52 PM PDT 24
Finished May 09 12:47:18 PM PDT 24
Peak memory 225420 kb
Host smart-a973c784-ec9f-41a6-a5e4-6cfa17ac6689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765124537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.2765124537
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.4121686800
Short name T919
Test name
Test status
Simulation time 4903019774 ps
CPU time 36.77 seconds
Started May 09 12:46:46 PM PDT 24
Finished May 09 12:47:25 PM PDT 24
Peak memory 350772 kb
Host smart-b1f71bc1-354a-485b-8d25-8e0853aa725a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121686800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.4121686800
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.3902578589
Short name T39
Test name
Test status
Simulation time 202034282600 ps
CPU time 558.62 seconds
Started May 09 12:47:03 PM PDT 24
Finished May 09 12:56:24 PM PDT 24
Peak memory 2019056 kb
Host smart-7d76504d-d573-46b7-a767-d5b94efe56be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902578589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.3902578589
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.3022868226
Short name T515
Test name
Test status
Simulation time 2656990047 ps
CPU time 10.76 seconds
Started May 09 12:46:52 PM PDT 24
Finished May 09 12:47:04 PM PDT 24
Peak memory 220796 kb
Host smart-a73a06e5-0f99-4387-88d4-3080715cd4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022868226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.3022868226
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.2814372220
Short name T755
Test name
Test status
Simulation time 1007378960 ps
CPU time 3.87 seconds
Started May 09 12:47:03 PM PDT 24
Finished May 09 12:47:09 PM PDT 24
Peak memory 204484 kb
Host smart-d9226521-44e1-43bd-9990-43ff85ffbd71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814372220 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.2814372220
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.1105449306
Short name T513
Test name
Test status
Simulation time 10207417048 ps
CPU time 16.65 seconds
Started May 09 12:47:03 PM PDT 24
Finished May 09 12:47:22 PM PDT 24
Peak memory 281924 kb
Host smart-c7b28d74-ebf5-4a67-8d42-2f64dfdc5567
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105449306 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.1105449306
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.3076246890
Short name T1344
Test name
Test status
Simulation time 10051731104 ps
CPU time 61.34 seconds
Started May 09 12:46:59 PM PDT 24
Finished May 09 12:48:03 PM PDT 24
Peak memory 434300 kb
Host smart-b9368432-88ef-4dab-9422-098dd8054f6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076246890 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.3076246890
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.1742417215
Short name T1212
Test name
Test status
Simulation time 1795013463 ps
CPU time 2.88 seconds
Started May 09 12:47:02 PM PDT 24
Finished May 09 12:47:07 PM PDT 24
Peak memory 204412 kb
Host smart-3cf6afff-c96b-4f65-9dc7-6b392dad7e3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742417215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.1742417215
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.3575187210
Short name T1023
Test name
Test status
Simulation time 792448875 ps
CPU time 5.2 seconds
Started May 09 12:47:01 PM PDT 24
Finished May 09 12:47:09 PM PDT 24
Peak memory 212472 kb
Host smart-be124c4d-5aa0-4ce3-af32-fff4a427f59d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575187210 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.3575187210
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.3229600022
Short name T855
Test name
Test status
Simulation time 21595789844 ps
CPU time 498.98 seconds
Started May 09 12:47:01 PM PDT 24
Finished May 09 12:55:22 PM PDT 24
Peak memory 3691552 kb
Host smart-69e57d23-c562-459f-a0d5-826578cf4fe9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229600022 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.3229600022
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.746923923
Short name T609
Test name
Test status
Simulation time 4083678482 ps
CPU time 38.57 seconds
Started May 09 12:47:00 PM PDT 24
Finished May 09 12:47:41 PM PDT 24
Peak memory 204432 kb
Host smart-c4ced17a-18dc-4f91-ae3e-a517876e14b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746923923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_targ
et_smoke.746923923
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.3214716338
Short name T922
Test name
Test status
Simulation time 1476155195 ps
CPU time 6.79 seconds
Started May 09 12:47:01 PM PDT 24
Finished May 09 12:47:10 PM PDT 24
Peak memory 204480 kb
Host smart-a34693c7-0a44-49d0-90e1-780c3db6d996
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214716338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.3214716338
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.575053716
Short name T129
Test name
Test status
Simulation time 23634369427 ps
CPU time 8.26 seconds
Started May 09 12:47:01 PM PDT 24
Finished May 09 12:47:11 PM PDT 24
Peak memory 204472 kb
Host smart-628f45bf-343d-4d42-9e8b-c9ed977a82df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575053716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_wr.575053716
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.3339010074
Short name T386
Test name
Test status
Simulation time 24066203274 ps
CPU time 2063.47 seconds
Started May 09 12:47:02 PM PDT 24
Finished May 09 01:21:28 PM PDT 24
Peak memory 6079660 kb
Host smart-e83e4d10-7069-4325-8391-e3245acf0f2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339010074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.3339010074
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.2554499640
Short name T130
Test name
Test status
Simulation time 13003514118 ps
CPU time 8.18 seconds
Started May 09 12:47:01 PM PDT 24
Finished May 09 12:47:11 PM PDT 24
Peak memory 219016 kb
Host smart-fc7c83b3-a5bd-4947-8a0c-6d5d291a2e80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554499640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.2554499640
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_unexp_stop.895266876
Short name T14
Test name
Test status
Simulation time 1055532833 ps
CPU time 7.91 seconds
Started May 09 12:47:00 PM PDT 24
Finished May 09 12:47:09 PM PDT 24
Peak memory 212692 kb
Host smart-39300730-c6a9-4b3c-bac5-f54eb89d1410
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895266876 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_unexp_stop.895266876
Directory /workspace/8.i2c_target_unexp_stop/latest

Test location /workspace/coverage/default/9.i2c_alert_test.1947675623
Short name T492
Test name
Test status
Simulation time 17708507 ps
CPU time 0.6 seconds
Started May 09 12:47:12 PM PDT 24
Finished May 09 12:47:15 PM PDT 24
Peak memory 204156 kb
Host smart-22a81ffe-100f-4489-ba8f-bb363d1a1225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947675623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1947675623
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.3309641227
Short name T767
Test name
Test status
Simulation time 84110693 ps
CPU time 2 seconds
Started May 09 12:47:11 PM PDT 24
Finished May 09 12:47:15 PM PDT 24
Peak memory 212712 kb
Host smart-2354e78b-1689-483d-9a77-5621702e47d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309641227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3309641227
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.237817682
Short name T1231
Test name
Test status
Simulation time 1105352094 ps
CPU time 4.84 seconds
Started May 09 12:47:10 PM PDT 24
Finished May 09 12:47:16 PM PDT 24
Peak memory 254156 kb
Host smart-0125383b-708e-4b98-8091-b41ccdd8e41a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237817682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty
.237817682
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.2438582043
Short name T1323
Test name
Test status
Simulation time 1090894943 ps
CPU time 24.65 seconds
Started May 09 12:47:12 PM PDT 24
Finished May 09 12:47:39 PM PDT 24
Peak memory 212624 kb
Host smart-1574ebaf-f17f-4c8b-892e-901d368b4795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438582043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.2438582043
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.592091315
Short name T311
Test name
Test status
Simulation time 1362537888 ps
CPU time 30.95 seconds
Started May 09 12:47:00 PM PDT 24
Finished May 09 12:47:33 PM PDT 24
Peak memory 387712 kb
Host smart-6845868f-efb4-4ba3-ac8b-4cf56591306d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592091315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.592091315
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.3769465873
Short name T416
Test name
Test status
Simulation time 645812435 ps
CPU time 1.07 seconds
Started May 09 12:47:01 PM PDT 24
Finished May 09 12:47:05 PM PDT 24
Peak memory 204268 kb
Host smart-c1f80cd3-93e7-4560-a8e8-a8a79fd5caba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769465873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.3769465873
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.2811599755
Short name T783
Test name
Test status
Simulation time 741627936 ps
CPU time 8.96 seconds
Started May 09 12:47:11 PM PDT 24
Finished May 09 12:47:21 PM PDT 24
Peak memory 204320 kb
Host smart-9871834c-b7f5-44b8-b4b4-ad664c1cb5e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811599755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
2811599755
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.307468475
Short name T378
Test name
Test status
Simulation time 3659295147 ps
CPU time 245.6 seconds
Started May 09 12:47:00 PM PDT 24
Finished May 09 12:51:08 PM PDT 24
Peak memory 1078564 kb
Host smart-e0b42d31-f659-4a1b-81ae-eac64363c86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307468475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.307468475
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.36139868
Short name T411
Test name
Test status
Simulation time 1507813324 ps
CPU time 6.21 seconds
Started May 09 12:47:11 PM PDT 24
Finished May 09 12:47:18 PM PDT 24
Peak memory 204400 kb
Host smart-963d9ed9-fdd7-4518-9940-006be3929465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36139868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.36139868
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.31399629
Short name T723
Test name
Test status
Simulation time 5033634732 ps
CPU time 24.82 seconds
Started May 09 12:47:12 PM PDT 24
Finished May 09 12:47:39 PM PDT 24
Peak memory 279448 kb
Host smart-d07a7f8a-5836-4c47-9e29-35426dac9b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31399629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.31399629
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.1870963707
Short name T1095
Test name
Test status
Simulation time 28640172 ps
CPU time 0.66 seconds
Started May 09 12:46:59 PM PDT 24
Finished May 09 12:47:01 PM PDT 24
Peak memory 204128 kb
Host smart-b8c583f5-f222-4861-bf62-b36e14835bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870963707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.1870963707
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.2124437175
Short name T81
Test name
Test status
Simulation time 423853147 ps
CPU time 16.92 seconds
Started May 09 12:47:09 PM PDT 24
Finished May 09 12:47:28 PM PDT 24
Peak memory 216920 kb
Host smart-fc08df55-5fef-4c3b-8167-9cf50c6129b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124437175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.2124437175
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.3412023679
Short name T591
Test name
Test status
Simulation time 6295079436 ps
CPU time 79.28 seconds
Started May 09 12:47:02 PM PDT 24
Finished May 09 12:48:23 PM PDT 24
Peak memory 403300 kb
Host smart-1328d27b-899b-4061-ac1b-27877b21adc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412023679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.3412023679
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.241494268
Short name T1327
Test name
Test status
Simulation time 1108777986 ps
CPU time 10.55 seconds
Started May 09 12:47:10 PM PDT 24
Finished May 09 12:47:22 PM PDT 24
Peak memory 217624 kb
Host smart-39388e4c-a2f5-41ae-a078-6cfc48f26c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241494268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.241494268
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.320171335
Short name T9
Test name
Test status
Simulation time 2016339113 ps
CPU time 5.25 seconds
Started May 09 12:47:12 PM PDT 24
Finished May 09 12:47:20 PM PDT 24
Peak memory 212588 kb
Host smart-5002c3c6-c755-4a93-92ad-bc3417fae83d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320171335 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.320171335
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.414038661
Short name T1075
Test name
Test status
Simulation time 10134077568 ps
CPU time 15.8 seconds
Started May 09 12:47:13 PM PDT 24
Finished May 09 12:47:31 PM PDT 24
Peak memory 265728 kb
Host smart-e5a2fb47-3c76-47af-9516-d0fafe208da7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414038661 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_acq.414038661
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.435256423
Short name T402
Test name
Test status
Simulation time 10081878867 ps
CPU time 70.95 seconds
Started May 09 12:47:13 PM PDT 24
Finished May 09 12:48:27 PM PDT 24
Peak memory 465516 kb
Host smart-e1276303-795e-4f01-bcb5-b5e679a639f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435256423 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_fifo_reset_tx.435256423
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.1276633203
Short name T1334
Test name
Test status
Simulation time 3487086052 ps
CPU time 2.43 seconds
Started May 09 12:47:10 PM PDT 24
Finished May 09 12:47:14 PM PDT 24
Peak memory 204544 kb
Host smart-b650512f-0df7-4082-b4e9-6e7f264aaef2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276633203 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.1276633203
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.3290935882
Short name T696
Test name
Test status
Simulation time 2524007765 ps
CPU time 6.39 seconds
Started May 09 12:47:13 PM PDT 24
Finished May 09 12:47:23 PM PDT 24
Peak memory 212708 kb
Host smart-5990f3d7-03a6-40d3-a5a0-c569323ccdca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290935882 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.3290935882
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.426731883
Short name T984
Test name
Test status
Simulation time 13408612678 ps
CPU time 27.61 seconds
Started May 09 12:47:13 PM PDT 24
Finished May 09 12:47:43 PM PDT 24
Peak memory 810848 kb
Host smart-9fd635f4-2072-493a-8a2b-c767c69e3ecd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426731883 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.426731883
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.3433455088
Short name T759
Test name
Test status
Simulation time 3605088660 ps
CPU time 37.6 seconds
Started May 09 12:47:10 PM PDT 24
Finished May 09 12:47:49 PM PDT 24
Peak memory 204440 kb
Host smart-5a85f331-5c45-4f87-b734-7e9ab5a87577
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433455088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.3433455088
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.497246423
Short name T726
Test name
Test status
Simulation time 1350772213 ps
CPU time 10.93 seconds
Started May 09 12:47:11 PM PDT 24
Finished May 09 12:47:24 PM PDT 24
Peak memory 204416 kb
Host smart-7866507c-c198-4965-a104-2890b9d107f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497246423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_rd.497246423
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.3431947821
Short name T403
Test name
Test status
Simulation time 43363807238 ps
CPU time 772.53 seconds
Started May 09 12:47:09 PM PDT 24
Finished May 09 01:00:03 PM PDT 24
Peak memory 6119480 kb
Host smart-7e1f6db6-41ea-4d96-a424-b6de2afda59e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431947821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.3431947821
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.1491443883
Short name T1063
Test name
Test status
Simulation time 8679549948 ps
CPU time 321.16 seconds
Started May 09 12:47:10 PM PDT 24
Finished May 09 12:52:32 PM PDT 24
Peak memory 2206116 kb
Host smart-e44a3043-487c-4269-9874-970f2bb7fcd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491443883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.1491443883
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.203123369
Short name T858
Test name
Test status
Simulation time 1645267114 ps
CPU time 7.24 seconds
Started May 09 12:47:11 PM PDT 24
Finished May 09 12:47:20 PM PDT 24
Peak memory 212668 kb
Host smart-8bb5080c-b9ac-420a-ba98-1da1271bd711
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203123369 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_timeout.203123369
Directory /workspace/9.i2c_target_timeout/latest
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