Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	801174	1			T1	3		T2	3		T3	3
all_values[1]	801174	1			T1	3		T2	3		T3	3
all_values[2]	801174	1			T1	3		T2	3		T3	3
all_values[3]	801174	1			T1	3		T2	3		T3	3
all_values[4]	801174	1			T1	3		T2	3		T3	3
all_values[5]	801174	1			T1	3		T2	3		T3	3
all_values[6]	801174	1			T1	3		T2	3		T3	3
all_values[7]	801174	1			T1	3		T2	3		T3	3
all_values[8]	801174	1			T1	3		T2	3		T3	3
all_values[9]	801174	1			T1	3		T2	3		T3	3
all_values[10]	801174	1			T1	3		T2	3		T3	3
all_values[11]	801174	1			T1	3		T2	3		T3	3
all_values[12]	801174	1			T1	3		T2	3		T3	3
all_values[13]	801174	1			T1	3		T2	3		T3	3
all_values[14]	801174	1			T1	3		T2	3		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8559977

1

T1

38

T2

37

T3

37

auto[1]

3457633

1

T1

7

T2

8

T3

8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10207191

1

T1

45

T2

45

T3

45

auto[1]

1810419

1

T38

171845

T39

165378

T147

122

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[2] , all_values[3]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[5]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[12] , all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	63598	1			T2	1		T3	1		T8	6
all_values[0]	auto[0]	auto[1]	11250	1			T38	892		T39	2208		T118	384
all_values[0]	auto[1]	auto[0]	611690	1			T1	3		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	114636	1			T38	11383		T39	10513		T147	8
all_values[1]	auto[0]	auto[0]	683948	1			T1	3		T2	3		T3	3
all_values[1]	auto[0]	auto[1]	116686	1			T38	12274		T39	12719		T147	4
all_values[1]	auto[1]	auto[0]	301	1			T72	1		T112	6		T239	13
all_values[1]	auto[1]	auto[1]	239	1			T38	1		T39	1		T147	3
all_values[2]	auto[0]	auto[0]	682535	1			T1	3		T2	3		T3	3
all_values[2]	auto[0]	auto[1]	118437	1			T38	12272		T39	12719		T147	6
all_values[2]	auto[1]	auto[1]	202	1			T38	3		T39	3		T147	3
all_values[3]	auto[0]	auto[0]	680245	1			T1	3		T2	3		T3	3
all_values[3]	auto[0]	auto[1]	120664	1			T38	12273		T39	12718		T147	3
all_values[3]	auto[1]	auto[1]	265	1			T38	2		T39	4		T147	5
all_values[4]	auto[0]	auto[0]	675241	1			T1	3		T2	3		T3	3
all_values[4]	auto[0]	auto[1]	125714	1			T38	12272		T39	12720		T147	3
all_values[4]	auto[1]	auto[0]	14	1			T240	1		T241	2		T242	1
all_values[4]	auto[1]	auto[1]	205	1			T38	2		T39	1		T147	1
all_values[5]	auto[0]	auto[0]	683158	1			T1	3		T2	3		T3	3
all_values[5]	auto[0]	auto[1]	117770	1			T38	12273		T39	12721		T147	6
all_values[5]	auto[1]	auto[1]	246	1			T39	1		T147	2		T173	9
all_values[6]	auto[0]	auto[0]	147064	1			T1	3		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	27655	1			T38	3640		T39	398		T147	2
all_values[6]	auto[1]	auto[0]	528197	1			T2	1		T3	1		T8	2
all_values[6]	auto[1]	auto[1]	98258	1			T38	8635		T39	12323		T147	7
all_values[7]	auto[0]	auto[0]	667719	1			T1	3		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	102223	1			T38	12060		T147	2		T118	671
all_values[7]	auto[1]	auto[0]	27406	1			T2	1		T3	1		T8	7
all_values[7]	auto[1]	auto[1]	3826	1			T38	215		T147	7		T118	259
all_values[8]	auto[0]	auto[0]	132418	1			T1	3		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	20761	1			T39	51		T147	5		T118	825
all_values[8]	auto[1]	auto[0]	555115	1			T2	1		T3	1		T8	3
all_values[8]	auto[1]	auto[1]	92880	1			T39	12671		T147	4		T118	106
all_values[9]	auto[0]	auto[0]	148280	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	27312	1			T38	3406		T39	174		T147	7
all_values[9]	auto[1]	auto[0]	527182	1			T1	1		T2	1		T3	1
all_values[9]	auto[1]	auto[1]	98400	1			T38	8869		T39	12548		T147	2
all_values[10]	auto[0]	auto[0]	677529	1			T1	3		T2	3		T3	3
all_values[10]	auto[0]	auto[1]	123451	1			T38	12273		T39	12720		T147	5
all_values[10]	auto[1]	auto[1]	194	1			T38	1		T39	2		T147	4
all_values[11]	auto[0]	auto[0]	2908	1			T2	1		T3	1		T8	4
all_values[11]	auto[0]	auto[1]	550	1			T38	35		T39	12		T118	16
all_values[11]	auto[1]	auto[0]	672612	1			T1	3		T2	2		T3	2
all_values[11]	auto[1]	auto[1]	125104	1			T38	12240		T39	12709		T147	7
all_values[12]	auto[0]	auto[0]	688576	1			T1	3		T2	3		T3	3
all_values[12]	auto[0]	auto[1]	112411	1			T38	12273		T147	4		T118	929
all_values[12]	auto[1]	auto[1]	187	1			T38	2		T147	4		T118	3
all_values[13]	auto[0]	auto[0]	675258	1			T1	3		T2	3		T3	3
all_values[13]	auto[0]	auto[1]	125681	1			T38	12274		T39	12720		T147	3
all_values[13]	auto[1]	auto[1]	235	1			T38	1		T39	1		T147	6
all_values[14]	auto[0]	auto[0]	676197	1			T1	3		T2	3		T3	3
all_values[14]	auto[0]	auto[1]	124738	1			T38	12271		T39	12718		T147	4
all_values[14]	auto[1]	auto[1]	239	1			T38	3		T39	3		T147	5