Summary for Variable cp_acq_fifo_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_acq_fifo_size
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
not_empty |
103280212 |
1 |
|
|
T5 |
140904 |
|
T6 |
199942 |
|
T7 |
1522 |
empty |
83103481 |
1 |
|
|
T1 |
2810 |
|
T2 |
100315 |
|
T3 |
447942 |
Summary for Variable cp_host_mode_stretch
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_host_mode_stretch
Excluded/Illegal bins
NAME | COUNT | STATUS |
unused |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
stretch |
53024857 |
1 |
|
|
T2 |
80127 |
|
T3 |
276388 |
|
T57 |
8622 |
Summary for Variable cp_target_scl_stretch_addr_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_target_scl_stretch_addr_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
addr_write_byte_stretch |
356968 |
1 |
|
|
T19 |
5399 |
|
T20 |
6795 |
|
T21 |
6858 |
Summary for Variable cp_tx_fifo_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_tx_fifo_size
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
not_empty |
44784878 |
1 |
|
|
T5 |
140844 |
|
T6 |
199666 |
|
T7 |
1072 |
empty |
141598848 |
1 |
|
|
T1 |
2810 |
|
T2 |
100315 |
|
T3 |
447942 |
Summary for Cross cp_target_scl_stretch_read
Samples crossed: cp_acq_fifo_size cp_tx_fifo_size
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
User Defined Cross Bins |
2 |
0 |
2 |
100.00 |
|
Automatically Generated Cross Bins for cp_target_scl_stretch_read
Bins
cp_acq_fifo_size | cp_tx_fifo_size | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
empty |
not_empty |
27 |
1 |
|
|
T275 |
20 |
|
T220 |
7 |
|
- |
- |
empty |
empty |
1239309 |
1 |
|
|
T1 |
2810 |
|
T5 |
33 |
|
T6 |
306 |
User Defined Cross Bins for cp_target_scl_stretch_read
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
read_byte_stretch |
439004 |
1 |
|
|
T5 |
60 |
|
T6 |
276 |
|
T7 |
138 |
scl_stretch_read_request |
45045476 |
1 |
|
|
T5 |
140904 |
|
T6 |
199942 |
|
T7 |
1210 |