Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	801174	1			T1	3		T2	3		T3	3
all_pins[1]	801174	1			T1	3		T2	3		T3	3
all_pins[2]	801174	1			T1	3		T2	3		T3	3
all_pins[3]	801174	1			T1	3		T2	3		T3	3
all_pins[4]	801174	1			T1	3		T2	3		T3	3
all_pins[5]	801174	1			T1	3		T2	3		T3	3
all_pins[6]	801174	1			T1	3		T2	3		T3	3
all_pins[7]	801174	1			T1	3		T2	3		T3	3
all_pins[8]	801174	1			T1	3		T2	3		T3	3
all_pins[9]	801174	1			T1	3		T2	3		T3	3
all_pins[10]	801174	1			T1	3		T2	3		T3	3
all_pins[11]	801174	1			T1	3		T2	3		T3	3
all_pins[12]	801174	1			T1	3		T2	3		T3	3
all_pins[13]	801174	1			T1	3		T2	3		T3	3
all_pins[14]	801174	1			T1	3		T2	3		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	8566216	1			T1	38		T2	37		T3	37
values[0x1]	3451394	1			T1	7		T2	8		T3	8
transitions[0x0=>0x1]	2790888	1			T1	7		T2	5		T3	5
transitions[0x1=>0x0]	2789848	1			T1	6		T2	4		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	78348	1			T2	1		T3	1		T8	35
all_pins[0]	values[0x1]	722826	1			T1	3		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	722380	1			T1	3		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	75	1			T39	1		T118	1		T173	4
all_pins[1]	values[0x0]	800653	1			T1	3		T2	3		T3	3
all_pins[1]	values[0x1]	521	1			T72	2		T112	7		T39	1
all_pins[1]	transitions[0x0=>0x1]	490	1			T72	2		T112	7		T239	14
all_pins[1]	transitions[0x1=>0x0]	70	1			T38	1		T39	1		T147	2
all_pins[2]	values[0x0]	801073	1			T1	3		T2	3		T3	3
all_pins[2]	values[0x1]	101	1			T38	1		T39	2		T147	2
all_pins[2]	transitions[0x0=>0x1]	78	1			T38	1		T39	1		T147	2
all_pins[2]	transitions[0x1=>0x0]	107	1			T39	2		T147	2		T173	1
all_pins[3]	values[0x0]	801044	1			T1	3		T2	3		T3	3
all_pins[3]	values[0x1]	130	1			T39	3		T147	2		T173	2
all_pins[3]	transitions[0x0=>0x1]	103	1			T39	3		T147	2		T173	2
all_pins[3]	transitions[0x1=>0x0]	85	1			T38	1		T240	2		T39	1
all_pins[4]	values[0x0]	801062	1			T1	3		T2	3		T3	3
all_pins[4]	values[0x1]	112	1			T38	1		T240	2		T39	1
all_pins[4]	transitions[0x0=>0x1]	81	1			T38	1		T240	2		T39	1
all_pins[4]	transitions[0x1=>0x0]	104	1			T147	1		T173	1		T82	1
all_pins[5]	values[0x0]	801039	1			T1	3		T2	3		T3	3
all_pins[5]	values[0x1]	135	1			T147	1		T173	2		T82	1
all_pins[5]	transitions[0x0=>0x1]	100	1			T173	2		T82	1		T238	1
all_pins[5]	transitions[0x1=>0x0]	626083	1			T2	1		T3	1		T57	8
all_pins[6]	values[0x0]	175056	1			T1	3		T2	2		T3	2
all_pins[6]	values[0x1]	626118	1			T2	1		T3	1		T57	8
all_pins[6]	transitions[0x0=>0x1]	608952	1			T57	7		T43	1		T45	1
all_pins[6]	transitions[0x1=>0x0]	16731	1			T57	5		T41	51		T144	1
all_pins[7]	values[0x0]	767277	1			T1	3		T2	2		T3	2
all_pins[7]	values[0x1]	33897	1			T2	1		T3	1		T57	6
all_pins[7]	transitions[0x0=>0x1]	14563	1			T57	3		T41	51		T73	243
all_pins[7]	transitions[0x1=>0x0]	628410	1			T57	6		T41	15		T73	57
all_pins[8]	values[0x0]	153430	1			T1	3		T2	2		T3	2
all_pins[8]	values[0x1]	647744	1			T2	1		T3	1		T57	9
all_pins[8]	transitions[0x0=>0x1]	24524	1			T57	8		T41	13		T73	120
all_pins[8]	transitions[0x1=>0x0]	2267	1			T1	1		T5	1		T6	1
all_pins[9]	values[0x0]	175687	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	625487	1			T1	1		T2	1		T3	1
all_pins[9]	transitions[0x0=>0x1]	625459	1			T1	1		T2	1		T3	1
all_pins[9]	transitions[0x1=>0x0]	73	1			T38	1		T39	1		T118	1
all_pins[10]	values[0x0]	801073	1			T1	3		T2	3		T3	3
all_pins[10]	values[0x1]	101	1			T38	1		T39	1		T147	2
all_pins[10]	transitions[0x0=>0x1]	64	1			T38	1		T39	1		T147	2
all_pins[10]	transitions[0x1=>0x0]	793857	1			T1	3		T2	2		T3	2
all_pins[11]	values[0x0]	7280	1			T2	1		T3	1		T8	35
all_pins[11]	values[0x1]	793894	1			T1	3		T2	2		T3	2
all_pins[11]	transitions[0x0=>0x1]	793851	1			T1	3		T2	2		T3	2
all_pins[11]	transitions[0x1=>0x0]	60	1			T173	5		T82	2		T106	1
all_pins[12]	values[0x0]	801071	1			T1	3		T2	3		T3	3
all_pins[12]	values[0x1]	103	1			T38	1		T173	7		T82	3
all_pins[12]	transitions[0x0=>0x1]	81	1			T38	1		T173	4		T82	2
all_pins[12]	transitions[0x1=>0x0]	90	1			T147	2		T118	1		T173	3
all_pins[13]	values[0x0]	801062	1			T1	3		T2	3		T3	3
all_pins[13]	values[0x1]	112	1			T147	2		T118	1		T173	6
all_pins[13]	transitions[0x0=>0x1]	93	1			T147	2		T118	1		T173	6
all_pins[13]	transitions[0x1=>0x0]	94	1			T38	3		T39	1		T147	4
all_pins[14]	values[0x0]	801061	1			T1	3		T2	3		T3	3
all_pins[14]	values[0x1]	113	1			T38	3		T39	1		T147	4
all_pins[14]	transitions[0x0=>0x1]	69	1			T38	3		T39	1		T147	1
all_pins[14]	transitions[0x1=>0x0]	721742	1			T1	2		T2	1		T3	1