Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	494	1			T38	4		T39	4		T147	7
all_values[1]	494	1			T38	4		T39	4		T147	7
all_values[2]	494	1			T38	4		T39	4		T147	7
all_values[3]	494	1			T38	4		T39	4		T147	7
all_values[4]	494	1			T38	4		T39	4		T147	7
all_values[5]	494	1			T38	4		T39	4		T147	7
all_values[6]	494	1			T38	4		T39	4		T147	7
all_values[7]	494	1			T38	4		T39	4		T147	7
all_values[8]	494	1			T38	4		T39	4		T147	7
all_values[9]	494	1			T38	4		T39	4		T147	7
all_values[10]	494	1			T38	4		T39	4		T147	7
all_values[11]	494	1			T38	4		T39	4		T147	7
all_values[12]	494	1			T38	4		T39	4		T147	7
all_values[13]	494	1			T38	4		T39	4		T147	7
all_values[14]	494	1			T38	4		T39	4		T147	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3926

1

T38

24

T39

29

T147

40

auto[1]

3484

1

T38

36

T39

31

T147

65

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1173

1

T38

9

T39

16

T147

13

auto[1]

6237

1

T38

51

T39

44

T147

92

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4339

1

T38

32

T39

39

T147

55

auto[1]

3071

1

T38

28

T39

21

T147

50

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	56	1			T39	1		T173	1		T82	1
all_values[0]	auto[0]	auto[0]	auto[1]	99	1			T38	1		T118	2		T106	2
all_values[0]	auto[0]	auto[1]	auto[0]	36	1			T147	1		T118	1		T173	1
all_values[0]	auto[0]	auto[1]	auto[1]	114	1			T38	1		T39	2		T147	4
all_values[0]	auto[1]	auto[0]	auto[1]	109	1			T38	2		T173	2		T82	1
all_values[0]	auto[1]	auto[1]	auto[1]	80	1			T39	1		T147	2		T118	1
all_values[1]	auto[0]	auto[0]	auto[0]	68	1			T39	1		T147	1		T118	1
all_values[1]	auto[0]	auto[0]	auto[1]	93	1			T38	2		T147	1		T173	4
all_values[1]	auto[0]	auto[1]	auto[0]	37	1			T39	1		T147	1		T82	2
all_values[1]	auto[0]	auto[1]	auto[1]	101	1			T38	1		T39	1		T147	1
all_values[1]	auto[1]	auto[0]	auto[1]	96	1			T38	1		T147	2		T118	1
all_values[1]	auto[1]	auto[1]	auto[1]	99	1			T39	1		T147	1		T173	2
all_values[2]	auto[0]	auto[0]	auto[0]	41	1			T173	1		T106	1		T119	1
all_values[2]	auto[0]	auto[0]	auto[1]	118	1			T38	1		T147	1		T173	4
all_values[2]	auto[0]	auto[1]	auto[0]	31	1			T118	2		T106	2		T86	2
all_values[2]	auto[0]	auto[1]	auto[1]	102	1			T39	1		T147	3		T118	1
all_values[2]	auto[1]	auto[0]	auto[1]	120	1			T38	2		T39	1		T147	1
all_values[2]	auto[1]	auto[1]	auto[1]	82	1			T38	1		T39	2		T147	2
all_values[3]	auto[0]	auto[0]	auto[0]	35	1			T238	1		T86	1		T256	1
all_values[3]	auto[0]	auto[0]	auto[1]	100	1			T38	1		T39	1		T147	1
all_values[3]	auto[0]	auto[1]	auto[0]	24	1			T147	1		T238	1		T106	1
all_values[3]	auto[0]	auto[1]	auto[1]	110	1			T38	1		T39	1		T147	1
all_values[3]	auto[1]	auto[0]	auto[1]	114	1			T39	2		T147	1		T118	2
all_values[3]	auto[1]	auto[1]	auto[1]	111	1			T38	2		T147	3		T173	3
all_values[4]	auto[0]	auto[0]	auto[0]	33	1			T39	1		T147	2		T106	1
all_values[4]	auto[0]	auto[0]	auto[1]	111	1			T38	1		T118	1		T173	2
all_values[4]	auto[0]	auto[1]	auto[0]	29	1			T38	1		T147	3		T106	3
all_values[4]	auto[0]	auto[1]	auto[1]	116	1			T39	2		T147	1		T118	1
all_values[4]	auto[1]	auto[0]	auto[1]	124	1			T118	1		T173	4		T82	2
all_values[4]	auto[1]	auto[1]	auto[1]	81	1			T38	2		T39	1		T147	1
all_values[5]	auto[0]	auto[0]	auto[0]	38	1			T38	2		T82	1		T86	1
all_values[5]	auto[0]	auto[0]	auto[1]	126	1			T38	1		T39	3		T147	1
all_values[5]	auto[0]	auto[1]	auto[0]	35	1			T147	1		T118	4		T86	1
all_values[5]	auto[0]	auto[1]	auto[1]	94	1			T147	3		T173	1		T238	1
all_values[5]	auto[1]	auto[0]	auto[1]	104	1			T39	1		T147	2		T173	5
all_values[5]	auto[1]	auto[1]	auto[1]	97	1			T38	1		T173	2		T82	1
all_values[6]	auto[0]	auto[0]	auto[0]	41	1			T39	1		T173	2		T119	1
all_values[6]	auto[0]	auto[0]	auto[1]	91	1			T39	1		T118	1		T173	1
all_values[6]	auto[0]	auto[1]	auto[0]	27	1			T118	2		T173	1		T122	1
all_values[6]	auto[0]	auto[1]	auto[1]	117	1			T38	1		T147	1		T173	3
all_values[6]	auto[1]	auto[0]	auto[1]	106	1			T38	1		T147	2		T118	1
all_values[6]	auto[1]	auto[1]	auto[1]	112	1			T38	2		T39	2		T147	4
all_values[7]	auto[0]	auto[0]	auto[0]	52	1			T39	1		T118	2		T173	2
all_values[7]	auto[0]	auto[0]	auto[1]	94	1			T147	2		T173	3		T82	1
all_values[7]	auto[0]	auto[1]	auto[0]	28	1			T39	3		T238	2		T106	1
all_values[7]	auto[0]	auto[1]	auto[1]	114	1			T38	1		T147	1		T118	1
all_values[7]	auto[1]	auto[0]	auto[1]	103	1			T147	2		T173	4		T82	2
all_values[7]	auto[1]	auto[1]	auto[1]	103	1			T38	3		T147	2		T118	1
all_values[8]	auto[0]	auto[0]	auto[0]	45	1			T38	2		T173	1		T256	1
all_values[8]	auto[0]	auto[0]	auto[1]	106	1			T39	1		T147	1		T118	1
all_values[8]	auto[0]	auto[1]	auto[0]	25	1			T38	2		T118	1		T173	1
all_values[8]	auto[0]	auto[1]	auto[1]	94	1			T147	3		T173	2		T82	3
all_values[8]	auto[1]	auto[0]	auto[1]	121	1			T39	1		T147	1		T118	1
all_values[8]	auto[1]	auto[1]	auto[1]	103	1			T39	2		T147	2		T118	1
all_values[9]	auto[0]	auto[0]	auto[0]	50	1			T118	1		T82	1		T238	1
all_values[9]	auto[0]	auto[0]	auto[1]	99	1			T38	1		T147	1		T173	3
all_values[9]	auto[0]	auto[1]	auto[0]	40	1			T82	2		T238	1		T119	4
all_values[9]	auto[0]	auto[1]	auto[1]	95	1			T38	1		T39	3		T147	4
all_values[9]	auto[1]	auto[0]	auto[1]	106	1			T39	1		T118	1		T173	4
all_values[9]	auto[1]	auto[1]	auto[1]	104	1			T38	2		T147	2		T118	1
all_values[10]	auto[0]	auto[0]	auto[0]	49	1			T173	1		T106	2		T119	1
all_values[10]	auto[0]	auto[0]	auto[1]	108	1			T39	1		T118	2		T173	3
all_values[10]	auto[0]	auto[1]	auto[0]	41	1			T38	1		T82	1		T106	5
all_values[10]	auto[0]	auto[1]	auto[1]	102	1			T38	2		T39	1		T147	3
all_values[10]	auto[1]	auto[0]	auto[1]	107	1			T39	2		T147	1		T173	4
all_values[10]	auto[1]	auto[1]	auto[1]	87	1			T38	1		T147	3		T118	2
all_values[11]	auto[0]	auto[0]	auto[0]	44	1			T39	1		T147	1		T173	1
all_values[11]	auto[0]	auto[0]	auto[1]	102	1			T38	1		T147	2		T118	1
all_values[11]	auto[0]	auto[1]	auto[0]	39	1			T147	1		T82	2		T238	1
all_values[11]	auto[0]	auto[1]	auto[1]	100	1			T38	2		T39	2		T118	2
all_values[11]	auto[1]	auto[0]	auto[1]	99	1			T147	2		T118	1		T173	4
all_values[11]	auto[1]	auto[1]	auto[1]	110	1			T38	1		T39	1		T147	1
all_values[12]	auto[0]	auto[0]	auto[0]	50	1			T39	3		T267	3		T268	1
all_values[12]	auto[0]	auto[0]	auto[1]	115	1			T38	2		T147	2		T118	1
all_values[12]	auto[0]	auto[1]	auto[0]	38	1			T39	1		T147	1		T86	1
all_values[12]	auto[0]	auto[1]	auto[1]	104	1			T173	4		T82	1		T106	7
all_values[12]	auto[1]	auto[0]	auto[1]	89	1			T147	4		T118	3		T173	3
all_values[12]	auto[1]	auto[1]	auto[1]	98	1			T38	2		T173	5		T82	2
all_values[13]	auto[0]	auto[0]	auto[0]	44	1			T39	1		T118	1		T106	1
all_values[13]	auto[0]	auto[0]	auto[1]	112	1			T39	1		T147	2		T238	1
all_values[13]	auto[0]	auto[1]	auto[0]	21	1			T86	1		T256	1		T119	2
all_values[13]	auto[0]	auto[1]	auto[1]	120	1			T38	1		T39	1		T118	2
all_values[13]	auto[1]	auto[0]	auto[1]	127	1			T38	1		T39	1		T147	4
all_values[13]	auto[1]	auto[1]	auto[1]	70	1			T38	2		T147	1		T173	2
all_values[14]	auto[0]	auto[0]	auto[0]	50	1			T38	1		T39	1		T118	2
all_values[14]	auto[0]	auto[0]	auto[1]	112	1			T39	1		T173	5		T82	3
all_values[14]	auto[0]	auto[1]	auto[0]	26	1			T118	2		T86	1		T161	1
all_values[14]	auto[0]	auto[1]	auto[1]	97	1			T38	1		T147	3		T173	2
all_values[14]	auto[1]	auto[0]	auto[1]	119	1			T38	1		T173	3		T82	2
all_values[14]	auto[1]	auto[1]	auto[1]	90	1			T38	1		T39	2		T147	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal